drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 140
 141 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 142 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 143 #define DEFAULT_ETAG_ETYPE                     0x893f
 144 #define IXGBE_ETAG_ETYPE                       0x00005084
 145 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 146 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 147 #define IXGBE_RAH_ADTYPE                       0x40000000
 148 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 149 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 150 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 151 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 152 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 153 #define IXGBE_VTEICR_MASK                      0x07
 154
 155 enum ixgbevf_xcast_modes {
 156         IXGBEVF_XCAST_MODE_NONE = 0,
 157         IXGBEVF_XCAST_MODE_MULTI,
 158         IXGBEVF_XCAST_MODE_ALLMULTI,
 159 };
 160
 161 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 162 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 163
 164 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 165 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 166 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 167 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 170 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 177                                 int wait_to_complete);
 178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 179                                 struct rte_eth_stats *stats);
 180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_xstat *xstats, unsigned n);
 182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 183                                   struct rte_eth_xstat *xstats, unsigned n);
 184 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 185 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 186 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 187         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 188 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 191                                              uint16_t queue_id,
 192                                              uint8_t stat_idx,
 193                                              uint8_t is_rx);
 194 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 195                                struct rte_eth_dev_info *dev_info);
 196 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 198                                  struct rte_eth_dev_info *dev_info);
 199 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 200
 201 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 202                 uint16_t vlan_id, int on);
 203 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 204                                enum rte_vlan_type vlan_type,
 205                                uint16_t tpid_id);
 206 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 207                 uint16_t queue, bool on);
 208 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 209                 int on);
 210 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 211 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 212 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 213 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 214 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 215
 216 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 217 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 218 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 219                                struct rte_eth_fc_conf *fc_conf);
 220 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 221                                struct rte_eth_fc_conf *fc_conf);
 222 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 223                 struct rte_eth_pfc_conf *pfc_conf);
 224 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 225                         struct rte_eth_rss_reta_entry64 *reta_conf,
 226                         uint16_t reta_size);
 227 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 228                         struct rte_eth_rss_reta_entry64 *reta_conf,
 229                         uint16_t reta_size);
 230 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 231 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 232 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 233 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 234 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 235 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 236                 void *param);
 237 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 238 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 239                 uint32_t index, uint32_t pool);
 240 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 241 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 242                                            struct ether_addr *mac_addr);
 243 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 244
 245 /* For Virtual Function support */
 246 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 249 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 250 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 251 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 252 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 253 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 254 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 255                 struct rte_eth_stats *stats);
 256 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 257 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 258                 uint16_t vlan_id, int on);
 259 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 260                 uint16_t queue, int on);
 261 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 262 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 263 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 264                                             uint16_t queue_id);
 265 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 266                                              uint16_t queue_id);
 267 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 268                                  uint8_t queue, uint8_t msix_vector);
 269 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 270 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 271 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 272
 273 /* For Eth VMDQ APIs support */
 274 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 275                 ether_addr * mac_addr, uint8_t on);
 276 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 277 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 278                 uint16_t rx_mask, uint8_t on);
 279 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 280 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 281 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 282                 uint64_t pool_mask, uint8_t vlan_on);
 283 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 284                 struct rte_eth_mirror_conf *mirror_conf,
 285                 uint8_t rule_id, uint8_t on);
 286 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 287                 uint8_t rule_id);
 288 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 289                                           uint16_t queue_id);
 290 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 291                                            uint16_t queue_id);
 292 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 293                                uint8_t queue, uint8_t msix_vector);
 294 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 295
 296 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 297                 uint16_t queue_idx, uint16_t tx_rate);
 298 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 299                 uint16_t tx_rate, uint64_t q_msk);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter,
 309                         bool add);
 310 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 311                         struct rte_eth_syn_filter *filter);
 312 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 313                         enum rte_filter_op filter_op,
 314                         void *arg);
 315 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 316                         struct ixgbe_5tuple_filter *filter);
 317 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter,
 321                         bool add);
 322 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 323                                 enum rte_filter_op filter_op,
 324                                 void *arg);
 325 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter);
 327 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 328                         struct rte_eth_ethertype_filter *filter,
 329                         bool add);
 330 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 331                                 enum rte_filter_op filter_op,
 332                                 void *arg);
 333 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter);
 335 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 336                      enum rte_filter_type filter_type,
 337                      enum rte_filter_op filter_op,
 338                      void *arg);
 339 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 340
 341 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 342                                       struct ether_addr *mc_addr_set,
 343                                       uint32_t nb_mc_addr);
 344 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                    struct rte_eth_dcb_info *dcb_info);
 346
 347 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 349                             struct rte_dev_reg_info *regs);
 350 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 351 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 352                                 struct rte_dev_eeprom_info *eeprom);
 353 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 354                                 struct rte_dev_eeprom_info *eeprom);
 355
 356 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 357 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 358                                 struct rte_dev_reg_info *regs);
 359
 360 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 361 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 362 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 363                                             struct timespec *timestamp,
 364                                             uint32_t flags);
 365 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 366                                             struct timespec *timestamp);
 367 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 368 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 369                                    struct timespec *timestamp);
 370 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 371                                    const struct timespec *timestamp);
 372 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 373                                           void *param);
 374
 375 static int ixgbe_dev_l2_tunnel_eth_type_conf
 376         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 377 static int ixgbe_dev_l2_tunnel_offload_set
 378         (struct rte_eth_dev *dev,
 379          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 380          uint32_t mask,
 381          uint8_t en);
 382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 383                                              enum rte_filter_op filter_op,
 384                                              void *arg);
 385
 386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 387                                          struct rte_eth_udp_tunnel *udp_tunnel);
 388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 389                                          struct rte_eth_udp_tunnel *udp_tunnel);
 390
 391 /*
 392  * Define VF Stats MACRO for Non "cleared on read" register
 393  */
 394 #define UPDATE_VF_STAT(reg, last, cur)                          \
 395 {                                                               \
 396         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 397         cur += (latest - last) & UINT_MAX;                      \
 398         last = latest;                                          \
 399 }
 400
 401 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 402 {                                                                \
 403         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 404         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 405         u64 latest = ((new_msb << 32) | new_lsb);                \
 406         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 407         last = latest;                                           \
 408 }
 409
 410 #define IXGBE_SET_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] |= 1 << bit;\
 414         } while (0)
 415
 416 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] &= ~(1 << bit);\
 420         } while (0)
 421
 422 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (r) = (h)->bitmap[idx] >> bit & 1;\
 426         } while (0)
 427
 428 /*
 429  * The set of PCI devices this driver supports
 430  */
 431 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 432
 433 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 434 #include "rte_pci_dev_ids.h"
 435
 436 { .vendor_id = 0, /* sentinel */ },
 437 };
 438
 439
 440 /*
 441  * The set of PCI devices this driver supports (for 82599 VF)
 442  */
 443 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 444
 445 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 446 #include "rte_pci_dev_ids.h"
 447 { .vendor_id = 0, /* sentinel */ },
 448
 449 };
 450
 451 static const struct rte_eth_desc_lim rx_desc_lim = {
 452         .nb_max = IXGBE_MAX_RING_DESC,
 453         .nb_min = IXGBE_MIN_RING_DESC,
 454         .nb_align = IXGBE_RXD_ALIGN,
 455 };
 456
 457 static const struct rte_eth_desc_lim tx_desc_lim = {
 458         .nb_max = IXGBE_MAX_RING_DESC,
 459         .nb_min = IXGBE_MIN_RING_DESC,
 460         .nb_align = IXGBE_TXD_ALIGN,
 461 };
 462
 463 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 464         .dev_configure        = ixgbe_dev_configure,
 465         .dev_start            = ixgbe_dev_start,
 466         .dev_stop             = ixgbe_dev_stop,
 467         .dev_set_link_up    = ixgbe_dev_set_link_up,
 468         .dev_set_link_down  = ixgbe_dev_set_link_down,
 469         .dev_close            = ixgbe_dev_close,
 470         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 471         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 472         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 473         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 474         .link_update          = ixgbe_dev_link_update,
 475         .stats_get            = ixgbe_dev_stats_get,
 476         .xstats_get           = ixgbe_dev_xstats_get,
 477         .stats_reset          = ixgbe_dev_stats_reset,
 478         .xstats_reset         = ixgbe_dev_xstats_reset,
 479         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 480         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 481         .dev_infos_get        = ixgbe_dev_info_get,
 482         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 483         .mtu_set              = ixgbe_dev_mtu_set,
 484         .vlan_filter_set      = ixgbe_vlan_filter_set,
 485         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 486         .vlan_offload_set     = ixgbe_vlan_offload_set,
 487         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 488         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 489         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 490         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 491         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 492         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 493         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 494         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 495         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 496         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 497         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 498         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 499         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 500         .dev_led_on           = ixgbe_dev_led_on,
 501         .dev_led_off          = ixgbe_dev_led_off,
 502         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 503         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 504         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 505         .mac_addr_add         = ixgbe_add_rar,
 506         .mac_addr_remove      = ixgbe_remove_rar,
 507         .mac_addr_set         = ixgbe_set_default_mac_addr,
 508         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 509         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 510         .mirror_rule_set      = ixgbe_mirror_rule_set,
 511         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 512         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 513         .set_vf_rx            = ixgbe_set_pool_rx,
 514         .set_vf_tx            = ixgbe_set_pool_tx,
 515         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 516         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 517         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 518         .reta_update          = ixgbe_dev_rss_reta_update,
 519         .reta_query           = ixgbe_dev_rss_reta_query,
 520 #ifdef RTE_NIC_BYPASS
 521         .bypass_init          = ixgbe_bypass_init,
 522         .bypass_state_set     = ixgbe_bypass_state_store,
 523         .bypass_state_show    = ixgbe_bypass_state_show,
 524         .bypass_event_set     = ixgbe_bypass_event_store,
 525         .bypass_event_show    = ixgbe_bypass_event_show,
 526         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 527         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 528         .bypass_ver_show      = ixgbe_bypass_ver_show,
 529         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 530 #endif /* RTE_NIC_BYPASS */
 531         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 532         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 533         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 534         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 535         .rxq_info_get         = ixgbe_rxq_info_get,
 536         .txq_info_get         = ixgbe_txq_info_get,
 537         .timesync_enable      = ixgbe_timesync_enable,
 538         .timesync_disable     = ixgbe_timesync_disable,
 539         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 540         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 541         .get_reg_length       = ixgbe_get_reg_length,
 542         .get_reg              = ixgbe_get_regs,
 543         .get_eeprom_length    = ixgbe_get_eeprom_length,
 544         .get_eeprom           = ixgbe_get_eeprom,
 545         .set_eeprom           = ixgbe_set_eeprom,
 546         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 547         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 548         .timesync_read_time   = ixgbe_timesync_read_time,
 549         .timesync_write_time  = ixgbe_timesync_write_time,
 550         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 551         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 552         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 553         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 554 };
 555
 556 /*
 557  * dev_ops for virtual function, bare necessities for basic vf
 558  * operation have been implemented
 559  */
 560 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 561         .dev_configure        = ixgbevf_dev_configure,
 562         .dev_start            = ixgbevf_dev_start,
 563         .dev_stop             = ixgbevf_dev_stop,
 564         .link_update          = ixgbe_dev_link_update,
 565         .stats_get            = ixgbevf_dev_stats_get,
 566         .xstats_get           = ixgbevf_dev_xstats_get,
 567         .stats_reset          = ixgbevf_dev_stats_reset,
 568         .xstats_reset         = ixgbevf_dev_stats_reset,
 569         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 570         .dev_close            = ixgbevf_dev_close,
 571         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 572         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 573         .dev_infos_get        = ixgbevf_dev_info_get,
 574         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 575         .mtu_set              = ixgbevf_dev_set_mtu,
 576         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 577         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 578         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 579         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 580         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 581         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 582         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 583         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 584         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 585         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 586         .mac_addr_add         = ixgbevf_add_mac_addr,
 587         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 588         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 589         .rxq_info_get         = ixgbe_rxq_info_get,
 590         .txq_info_get         = ixgbe_txq_info_get,
 591         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 592         .get_reg_length       = ixgbevf_get_reg_length,
 593         .get_reg              = ixgbevf_get_regs,
 594         .reta_update          = ixgbe_dev_rss_reta_update,
 595         .reta_query           = ixgbe_dev_rss_reta_query,
 596         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 597         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 598 };
 599
 600 /* store statistics names and its offset in stats structure */
 601 struct rte_ixgbe_xstats_name_off {
 602         char name[RTE_ETH_XSTATS_NAME_SIZE];
 603         unsigned offset;
 604 };
 605
 606 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 607         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 608         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 609         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 610         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 611         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 612         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 613         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 614         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 615         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 616         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 617         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 618         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 619         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 620         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 621         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 622                 prc1023)},
 623         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 624                 prc1522)},
 625         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 626         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 627         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 628         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 629         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 630         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 631         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 632         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 633         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 634         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 635         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 636         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 637         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 638         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 639         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 640         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 641         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 642                 ptc1023)},
 643         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 644                 ptc1522)},
 645         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 646         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 647         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 648         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 649
 650         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 651                 fdirustat_add)},
 652         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 653                 fdirustat_remove)},
 654         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 655                 fdirfstat_fadd)},
 656         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 657                 fdirfstat_fremove)},
 658         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 659                 fdirmatch)},
 660         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 661                 fdirmiss)},
 662
 663         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 664         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 665         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 666                 fclast)},
 667         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 668         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 669         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 670         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 671         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 672                 fcoe_noddp)},
 673         {"rx_fcoe_no_direct_data_placement_ext_buff",
 674                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 675
 676         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 677                 lxontxc)},
 678         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 679                 lxonrxc)},
 680         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 681                 lxofftxc)},
 682         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 683                 lxoffrxc)},
 684         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 685 };
 686
 687 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 688                            sizeof(rte_ixgbe_stats_strings[0]))
 689
 690 /* Per-queue statistics */
 691 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 692         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 693         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 694         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 695         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 696 };
 697
 698 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 699                            sizeof(rte_ixgbe_rxq_strings[0]))
 700 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 701
 702 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 703         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 704         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 705         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 706                 pxon2offc)},
 707 };
 708
 709 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 710                            sizeof(rte_ixgbe_txq_strings[0]))
 711 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 712
 713 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 714         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 715 };
 716
 717 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 718                 sizeof(rte_ixgbevf_stats_strings[0]))
 719
 720 /**
 721  * Atomically reads the link status information from global
 722  * structure rte_eth_dev.
 723  *
 724  * @param dev
 725  *   - Pointer to the structure rte_eth_dev to read from.
 726  *   - Pointer to the buffer to be saved with the link status.
 727  *
 728  * @return
 729  *   - On success, zero.
 730  *   - On failure, negative value.
 731  */
 732 static inline int
 733 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 734                                 struct rte_eth_link *link)
 735 {
 736         struct rte_eth_link *dst = link;
 737         struct rte_eth_link *src = &(dev->data->dev_link);
 738
 739         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 740                                         *(uint64_t *)src) == 0)
 741                 return -1;
 742
 743         return 0;
 744 }
 745
 746 /**
 747  * Atomically writes the link status information into global
 748  * structure rte_eth_dev.
 749  *
 750  * @param dev
 751  *   - Pointer to the structure rte_eth_dev to read from.
 752  *   - Pointer to the buffer to be saved with the link status.
 753  *
 754  * @return
 755  *   - On success, zero.
 756  *   - On failure, negative value.
 757  */
 758 static inline int
 759 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 760                                 struct rte_eth_link *link)
 761 {
 762         struct rte_eth_link *dst = &(dev->data->dev_link);
 763         struct rte_eth_link *src = link;
 764
 765         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 766                                         *(uint64_t *)src) == 0)
 767                 return -1;
 768
 769         return 0;
 770 }
 771
 772 /*
 773  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 774  */
 775 static inline int
 776 ixgbe_is_sfp(struct ixgbe_hw *hw)
 777 {
 778         switch (hw->phy.type) {
 779         case ixgbe_phy_sfp_avago:
 780         case ixgbe_phy_sfp_ftl:
 781         case ixgbe_phy_sfp_intel:
 782         case ixgbe_phy_sfp_unknown:
 783         case ixgbe_phy_sfp_passive_tyco:
 784         case ixgbe_phy_sfp_passive_unknown:
 785                 return 1;
 786         default:
 787                 return 0;
 788         }
 789 }
 790
 791 static inline int32_t
 792 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 793 {
 794         uint32_t ctrl_ext;
 795         int32_t status;
 796
 797         status = ixgbe_reset_hw(hw);
 798
 799         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 800         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 801         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 802         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 803         IXGBE_WRITE_FLUSH(hw);
 804
 805         return status;
 806 }
 807
 808 static inline void
 809 ixgbe_enable_intr(struct rte_eth_dev *dev)
 810 {
 811         struct ixgbe_interrupt *intr =
 812                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 813         struct ixgbe_hw *hw =
 814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 815
 816         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 817         IXGBE_WRITE_FLUSH(hw);
 818 }
 819
 820 /*
 821  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 822  */
 823 static void
 824 ixgbe_disable_intr(struct ixgbe_hw *hw)
 825 {
 826         PMD_INIT_FUNC_TRACE();
 827
 828         if (hw->mac.type == ixgbe_mac_82598EB) {
 829                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 830         } else {
 831                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 832                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 833                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 834         }
 835         IXGBE_WRITE_FLUSH(hw);
 836 }
 837
 838 /*
 839  * This function resets queue statistics mapping registers.
 840  * From Niantic datasheet, Initialization of Statistics section:
 841  * "...if software requires the queue counters, the RQSMR and TQSM registers
 842  * must be re-programmed following a device reset.
 843  */
 844 static void
 845 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 846 {
 847         uint32_t i;
 848
 849         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 850                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 851                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 852         }
 853 }
 854
 855
 856 static int
 857 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 858                                   uint16_t queue_id,
 859                                   uint8_t stat_idx,
 860                                   uint8_t is_rx)
 861 {
 862 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 863 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 864 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 865
 866         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 867         struct ixgbe_stat_mapping_registers *stat_mappings =
 868                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 869         uint32_t qsmr_mask = 0;
 870         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 871         uint32_t q_map;
 872         uint8_t n, offset;
 873
 874         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 875                 (hw->mac.type != ixgbe_mac_X540) &&
 876                 (hw->mac.type != ixgbe_mac_X550) &&
 877                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 878                 (hw->mac.type != ixgbe_mac_X550EM_a))
 879                 return -ENOSYS;
 880
 881         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 882                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 883                      queue_id, stat_idx);
 884
 885         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 886         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 887                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 888                 return -EIO;
 889         }
 890         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 891
 892         /* Now clear any previous stat_idx set */
 893         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 894         if (!is_rx)
 895                 stat_mappings->tqsm[n] &= ~clearing_mask;
 896         else
 897                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 898
 899         q_map = (uint32_t)stat_idx;
 900         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 901         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 902         if (!is_rx)
 903                 stat_mappings->tqsm[n] |= qsmr_mask;
 904         else
 905                 stat_mappings->rqsmr[n] |= qsmr_mask;
 906
 907         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 908                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 909                      queue_id, stat_idx);
 910         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 911                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 912
 913         /* Now write the mapping in the appropriate register */
 914         if (is_rx) {
 915                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 916                              stat_mappings->rqsmr[n], n);
 917                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 918         } else {
 919                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 920                              stat_mappings->tqsm[n], n);
 921                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 922         }
 923         return 0;
 924 }
 925
 926 static void
 927 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 928 {
 929         struct ixgbe_stat_mapping_registers *stat_mappings =
 930                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 931         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932         int i;
 933
 934         /* write whatever was in stat mapping table to the NIC */
 935         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 936                 /* rx */
 937                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 938
 939                 /* tx */
 940                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 941         }
 942 }
 943
 944 static void
 945 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 946 {
 947         uint8_t i;
 948         struct ixgbe_dcb_tc_config *tc;
 949         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 950
 951         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 952         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 953         for (i = 0; i < dcb_max_tc; i++) {
 954                 tc = &dcb_config->tc_config[i];
 955                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 956                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 957                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 958                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 959                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 960                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 961                 tc->pfc = ixgbe_dcb_pfc_disabled;
 962         }
 963
 964         /* Initialize default user to priority mapping, UPx->TC0 */
 965         tc = &dcb_config->tc_config[0];
 966         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 967         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 968         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 969                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 970                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 971         }
 972         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 973         dcb_config->pfc_mode_enable = false;
 974         dcb_config->vt_mode = true;
 975         dcb_config->round_robin_enable = false;
 976         /* support all DCB capabilities in 82599 */
 977         dcb_config->support.capabilities = 0xFF;
 978
 979         /*we only support 4 Tcs for X540, X550 */
 980         if (hw->mac.type == ixgbe_mac_X540 ||
 981                 hw->mac.type == ixgbe_mac_X550 ||
 982                 hw->mac.type == ixgbe_mac_X550EM_x ||
 983                 hw->mac.type == ixgbe_mac_X550EM_a) {
 984                 dcb_config->num_tcs.pg_tcs = 4;
 985                 dcb_config->num_tcs.pfc_tcs = 4;
 986         }
 987 }
 988
 989 /*
 990  * Ensure that all locks are released before first NVM or PHY access
 991  */
 992 static void
 993 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 994 {
 995         uint16_t mask;
 996
 997         /*
 998          * Phy lock should not fail in this early stage. If this is the case,
 999          * it is due to an improper exit of the application.
1000          * So force the release of the faulty lock. Release of common lock
1001          * is done automatically by swfw_sync function.
1002          */
1003         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1004         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1005                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1006         }
1007         ixgbe_release_swfw_semaphore(hw, mask);
1008
1009         /*
1010          * These ones are more tricky since they are common to all ports; but
1011          * swfw_sync retries last long enough (1s) to be almost sure that if
1012          * lock can not be taken it is due to an improper lock of the
1013          * semaphore.
1014          */
1015         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1016         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1017                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1018         }
1019         ixgbe_release_swfw_semaphore(hw, mask);
1020 }
1021
1022 /*
1023  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1024  * It returns 0 on success.
1025  */
1026 static int
1027 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1028 {
1029         struct rte_pci_device *pci_dev;
1030         struct ixgbe_hw *hw =
1031                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1032         struct ixgbe_vfta *shadow_vfta =
1033                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1034         struct ixgbe_hwstrip *hwstrip =
1035                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1036         struct ixgbe_dcb_config *dcb_config =
1037                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1038         struct ixgbe_filter_info *filter_info =
1039                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1040         uint32_t ctrl_ext;
1041         uint16_t csum;
1042         int diag, i;
1043
1044         PMD_INIT_FUNC_TRACE();
1045
1046         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1047         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1048         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1049
1050         /*
1051          * For secondary processes, we don't initialise any further as primary
1052          * has already done this work. Only check we don't need a different
1053          * RX and TX function.
1054          */
1055         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1056                 struct ixgbe_tx_queue *txq;
1057                 /* TX queue function in primary, set by last queue initialized
1058                  * Tx queue may not initialized by primary process
1059                  */
1060                 if (eth_dev->data->tx_queues) {
1061                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1062                         ixgbe_set_tx_function(eth_dev, txq);
1063                 } else {
1064                         /* Use default TX function if we get here */
1065                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1066                                      "Using default TX function.");
1067                 }
1068
1069                 ixgbe_set_rx_function(eth_dev);
1070
1071                 return 0;
1072         }
1073         pci_dev = eth_dev->pci_dev;
1074
1075         rte_eth_copy_pci_info(eth_dev, pci_dev);
1076
1077         /* Vendor and Device ID need to be set before init of shared code */
1078         hw->device_id = pci_dev->id.device_id;
1079         hw->vendor_id = pci_dev->id.vendor_id;
1080         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1081         hw->allow_unsupported_sfp = 1;
1082
1083         /* Initialize the shared code (base driver) */
1084 #ifdef RTE_NIC_BYPASS
1085         diag = ixgbe_bypass_init_shared_code(hw);
1086 #else
1087         diag = ixgbe_init_shared_code(hw);
1088 #endif /* RTE_NIC_BYPASS */
1089
1090         if (diag != IXGBE_SUCCESS) {
1091                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1092                 return -EIO;
1093         }
1094
1095         /* pick up the PCI bus settings for reporting later */
1096         ixgbe_get_bus_info(hw);
1097
1098         /* Unlock any pending hardware semaphore */
1099         ixgbe_swfw_lock_reset(hw);
1100
1101         /* Initialize DCB configuration*/
1102         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1103         ixgbe_dcb_init(hw, dcb_config);
1104         /* Get Hardware Flow Control setting */
1105         hw->fc.requested_mode = ixgbe_fc_full;
1106         hw->fc.current_mode = ixgbe_fc_full;
1107         hw->fc.pause_time = IXGBE_FC_PAUSE;
1108         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1109                 hw->fc.low_water[i] = IXGBE_FC_LO;
1110                 hw->fc.high_water[i] = IXGBE_FC_HI;
1111         }
1112         hw->fc.send_xon = 1;
1113
1114         /* Make sure we have a good EEPROM before we read from it */
1115         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1116         if (diag != IXGBE_SUCCESS) {
1117                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1118                 return -EIO;
1119         }
1120
1121 #ifdef RTE_NIC_BYPASS
1122         diag = ixgbe_bypass_init_hw(hw);
1123 #else
1124         diag = ixgbe_init_hw(hw);
1125 #endif /* RTE_NIC_BYPASS */
1126
1127         /*
1128          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1129          * is called too soon after the kernel driver unbinding/binding occurs.
1130          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1131          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1132          * also called. See ixgbe_identify_phy_82599(). The reason for the
1133          * failure is not known, and only occuts when virtualisation features
1134          * are disabled in the bios. A delay of 100ms  was found to be enough by
1135          * trial-and-error, and is doubled to be safe.
1136          */
1137         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1138                 rte_delay_ms(200);
1139                 diag = ixgbe_init_hw(hw);
1140         }
1141
1142         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1143                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1144                              "LOM.  Please be aware there may be issues associated "
1145                              "with your hardware.");
1146                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1147                              "please contact your Intel or hardware representative "
1148                              "who provided you with this hardware.");
1149         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1150                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1151         if (diag) {
1152                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1153                 return -EIO;
1154         }
1155
1156         /* Reset the hw statistics */
1157         ixgbe_dev_stats_reset(eth_dev);
1158
1159         /* disable interrupt */
1160         ixgbe_disable_intr(hw);
1161
1162         /* reset mappings for queue statistics hw counters*/
1163         ixgbe_reset_qstat_mappings(hw);
1164
1165         /* Allocate memory for storing MAC addresses */
1166         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1167                                                hw->mac.num_rar_entries, 0);
1168         if (eth_dev->data->mac_addrs == NULL) {
1169                 PMD_INIT_LOG(ERR,
1170                              "Failed to allocate %u bytes needed to store "
1171                              "MAC addresses",
1172                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1173                 return -ENOMEM;
1174         }
1175         /* Copy the permanent MAC address */
1176         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1177                         &eth_dev->data->mac_addrs[0]);
1178
1179         /* Allocate memory for storing hash filter MAC addresses */
1180         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1181                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1182         if (eth_dev->data->hash_mac_addrs == NULL) {
1183                 PMD_INIT_LOG(ERR,
1184                              "Failed to allocate %d bytes needed to store MAC addresses",
1185                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1186                 return -ENOMEM;
1187         }
1188
1189         /* initialize the vfta */
1190         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1191
1192         /* initialize the hw strip bitmap*/
1193         memset(hwstrip, 0, sizeof(*hwstrip));
1194
1195         /* initialize PF if max_vfs not zero */
1196         ixgbe_pf_host_init(eth_dev);
1197
1198         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1199         /* let hardware know driver is loaded */
1200         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1201         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1202         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1203         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1204         IXGBE_WRITE_FLUSH(hw);
1205
1206         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1207                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1208                              (int) hw->mac.type, (int) hw->phy.type,
1209                              (int) hw->phy.sfp_type);
1210         else
1211                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1212                              (int) hw->mac.type, (int) hw->phy.type);
1213
1214         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1215                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1216                      pci_dev->id.device_id);
1217
1218         rte_intr_callback_register(&pci_dev->intr_handle,
1219                                    ixgbe_dev_interrupt_handler,
1220                                    (void *)eth_dev);
1221
1222         /* enable uio/vfio intr/eventfd mapping */
1223         rte_intr_enable(&pci_dev->intr_handle);
1224
1225         /* enable support intr */
1226         ixgbe_enable_intr(eth_dev);
1227
1228         /* initialize 5tuple filter list */
1229         TAILQ_INIT(&filter_info->fivetuple_list);
1230         memset(filter_info->fivetuple_mask, 0,
1231                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1232
1233         return 0;
1234 }
1235
1236 static int
1237 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1238 {
1239         struct rte_pci_device *pci_dev;
1240         struct ixgbe_hw *hw;
1241
1242         PMD_INIT_FUNC_TRACE();
1243
1244         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1245                 return -EPERM;
1246
1247         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1248         pci_dev = eth_dev->pci_dev;
1249
1250         if (hw->adapter_stopped == 0)
1251                 ixgbe_dev_close(eth_dev);
1252
1253         eth_dev->dev_ops = NULL;
1254         eth_dev->rx_pkt_burst = NULL;
1255         eth_dev->tx_pkt_burst = NULL;
1256
1257         /* Unlock any pending hardware semaphore */
1258         ixgbe_swfw_lock_reset(hw);
1259
1260         /* disable uio intr before callback unregister */
1261         rte_intr_disable(&(pci_dev->intr_handle));
1262         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1263                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1264
1265         /* uninitialize PF if max_vfs not zero */
1266         ixgbe_pf_host_uninit(eth_dev);
1267
1268         rte_free(eth_dev->data->mac_addrs);
1269         eth_dev->data->mac_addrs = NULL;
1270
1271         rte_free(eth_dev->data->hash_mac_addrs);
1272         eth_dev->data->hash_mac_addrs = NULL;
1273
1274         return 0;
1275 }
1276
1277 /*
1278  * Negotiate mailbox API version with the PF.
1279  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1280  * Then we try to negotiate starting with the most recent one.
1281  * If all negotiation attempts fail, then we will proceed with
1282  * the default one (ixgbe_mbox_api_10).
1283  */
1284 static void
1285 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1286 {
1287         int32_t i;
1288
1289         /* start with highest supported, proceed down */
1290         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1291                 ixgbe_mbox_api_12,
1292                 ixgbe_mbox_api_11,
1293                 ixgbe_mbox_api_10,
1294         };
1295
1296         for (i = 0;
1297                         i != RTE_DIM(sup_ver) &&
1298                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1299                         i++)
1300                 ;
1301 }
1302
1303 static void
1304 generate_random_mac_addr(struct ether_addr *mac_addr)
1305 {
1306         uint64_t random;
1307
1308         /* Set Organizationally Unique Identifier (OUI) prefix. */
1309         mac_addr->addr_bytes[0] = 0x00;
1310         mac_addr->addr_bytes[1] = 0x09;
1311         mac_addr->addr_bytes[2] = 0xC0;
1312         /* Force indication of locally assigned MAC address. */
1313         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1314         /* Generate the last 3 bytes of the MAC address with a random number. */
1315         random = rte_rand();
1316         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1317 }
1318
1319 /*
1320  * Virtual Function device init
1321  */
1322 static int
1323 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1324 {
1325         int diag;
1326         uint32_t tc, tcs;
1327         struct rte_pci_device *pci_dev;
1328         struct ixgbe_hw *hw =
1329                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1330         struct ixgbe_vfta *shadow_vfta =
1331                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1332         struct ixgbe_hwstrip *hwstrip =
1333                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1334         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1335
1336         PMD_INIT_FUNC_TRACE();
1337
1338         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1339         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1340         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1341
1342         /* for secondary processes, we don't initialise any further as primary
1343          * has already done this work. Only check we don't need a different
1344          * RX function
1345          */
1346         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1347                 struct ixgbe_tx_queue *txq;
1348                 /* TX queue function in primary, set by last queue initialized
1349                  * Tx queue may not initialized by primary process
1350                  */
1351                 if (eth_dev->data->tx_queues) {
1352                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1353                         ixgbe_set_tx_function(eth_dev, txq);
1354                 } else {
1355                         /* Use default TX function if we get here */
1356                         PMD_INIT_LOG(NOTICE,
1357                                      "No TX queues configured yet. Using default TX function.");
1358                 }
1359
1360                 ixgbe_set_rx_function(eth_dev);
1361
1362                 return 0;
1363         }
1364
1365         pci_dev = eth_dev->pci_dev;
1366
1367         rte_eth_copy_pci_info(eth_dev, pci_dev);
1368
1369         hw->device_id = pci_dev->id.device_id;
1370         hw->vendor_id = pci_dev->id.vendor_id;
1371         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1372
1373         /* initialize the vfta */
1374         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1375
1376         /* initialize the hw strip bitmap*/
1377         memset(hwstrip, 0, sizeof(*hwstrip));
1378
1379         /* Initialize the shared code (base driver) */
1380         diag = ixgbe_init_shared_code(hw);
1381         if (diag != IXGBE_SUCCESS) {
1382                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1383                 return -EIO;
1384         }
1385
1386         /* init_mailbox_params */
1387         hw->mbx.ops.init_params(hw);
1388
1389         /* Reset the hw statistics */
1390         ixgbevf_dev_stats_reset(eth_dev);
1391
1392         /* Disable the interrupts for VF */
1393         ixgbevf_intr_disable(hw);
1394
1395         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1396         diag = hw->mac.ops.reset_hw(hw);
1397
1398         /*
1399          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1400          * the underlying PF driver has not assigned a MAC address to the VF.
1401          * In this case, assign a random MAC address.
1402          */
1403         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1404                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1405                 return diag;
1406         }
1407
1408         /* negotiate mailbox API version to use with the PF. */
1409         ixgbevf_negotiate_api(hw);
1410
1411         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1412         ixgbevf_get_queues(hw, &tcs, &tc);
1413
1414         /* Allocate memory for storing MAC addresses */
1415         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1416                                                hw->mac.num_rar_entries, 0);
1417         if (eth_dev->data->mac_addrs == NULL) {
1418                 PMD_INIT_LOG(ERR,
1419                              "Failed to allocate %u bytes needed to store "
1420                              "MAC addresses",
1421                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1422                 return -ENOMEM;
1423         }
1424
1425         /* Generate a random MAC address, if none was assigned by PF. */
1426         if (is_zero_ether_addr(perm_addr)) {
1427                 generate_random_mac_addr(perm_addr);
1428                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1429                 if (diag) {
1430                         rte_free(eth_dev->data->mac_addrs);
1431                         eth_dev->data->mac_addrs = NULL;
1432                         return diag;
1433                 }
1434                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1435                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1436                              "%02x:%02x:%02x:%02x:%02x:%02x",
1437                              perm_addr->addr_bytes[0],
1438                              perm_addr->addr_bytes[1],
1439                              perm_addr->addr_bytes[2],
1440                              perm_addr->addr_bytes[3],
1441                              perm_addr->addr_bytes[4],
1442                              perm_addr->addr_bytes[5]);
1443         }
1444
1445         /* Copy the permanent MAC address */
1446         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1447
1448         /* reset the hardware with the new settings */
1449         diag = hw->mac.ops.start_hw(hw);
1450         switch (diag) {
1451         case  0:
1452                 break;
1453
1454         default:
1455                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1456                 return -EIO;
1457         }
1458
1459         rte_intr_callback_register(&pci_dev->intr_handle,
1460                                    ixgbevf_dev_interrupt_handler,
1461                                    (void *)eth_dev);
1462         rte_intr_enable(&pci_dev->intr_handle);
1463         ixgbevf_intr_enable(hw);
1464
1465         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1466                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1467                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1468
1469         return 0;
1470 }
1471
1472 /* Virtual Function device uninit */
1473
1474 static int
1475 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1476 {
1477         struct ixgbe_hw *hw;
1478         struct rte_pci_device *pci_dev = eth_dev->pci_dev;
1479
1480         PMD_INIT_FUNC_TRACE();
1481
1482         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1483                 return -EPERM;
1484
1485         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1486
1487         if (hw->adapter_stopped == 0)
1488                 ixgbevf_dev_close(eth_dev);
1489
1490         eth_dev->dev_ops = NULL;
1491         eth_dev->rx_pkt_burst = NULL;
1492         eth_dev->tx_pkt_burst = NULL;
1493
1494         /* Disable the interrupts for VF */
1495         ixgbevf_intr_disable(hw);
1496
1497         rte_free(eth_dev->data->mac_addrs);
1498         eth_dev->data->mac_addrs = NULL;
1499
1500         rte_intr_disable(&pci_dev->intr_handle);
1501         rte_intr_callback_unregister(&pci_dev->intr_handle,
1502                                      ixgbevf_dev_interrupt_handler,
1503                                      (void *)eth_dev);
1504
1505         return 0;
1506 }
1507
1508 static struct eth_driver rte_ixgbe_pmd = {
1509         .pci_drv = {
1510                 .name = "rte_ixgbe_pmd",
1511                 .id_table = pci_id_ixgbe_map,
1512                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1513                         RTE_PCI_DRV_DETACHABLE,
1514         },
1515         .eth_dev_init = eth_ixgbe_dev_init,
1516         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1517         .dev_private_size = sizeof(struct ixgbe_adapter),
1518 };
1519
1520 /*
1521  * virtual function driver struct
1522  */
1523 static struct eth_driver rte_ixgbevf_pmd = {
1524         .pci_drv = {
1525                 .name = "rte_ixgbevf_pmd",
1526                 .id_table = pci_id_ixgbevf_map,
1527                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1528         },
1529         .eth_dev_init = eth_ixgbevf_dev_init,
1530         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1531         .dev_private_size = sizeof(struct ixgbe_adapter),
1532 };
1533
1534 /*
1535  * Driver initialization routine.
1536  * Invoked once at EAL init time.
1537  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1538  */
1539 static int
1540 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1541 {
1542         PMD_INIT_FUNC_TRACE();
1543
1544         rte_eth_driver_register(&rte_ixgbe_pmd);
1545         return 0;
1546 }
1547
1548 /*
1549  * VF Driver initialization routine.
1550  * Invoked one at EAL init time.
1551  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1552  */
1553 static int
1554 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1555 {
1556         PMD_INIT_FUNC_TRACE();
1557
1558         rte_eth_driver_register(&rte_ixgbevf_pmd);
1559         return 0;
1560 }
1561
1562 static int
1563 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1564 {
1565         struct ixgbe_hw *hw =
1566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567         struct ixgbe_vfta *shadow_vfta =
1568                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1569         uint32_t vfta;
1570         uint32_t vid_idx;
1571         uint32_t vid_bit;
1572
1573         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1574         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1575         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1576         if (on)
1577                 vfta |= vid_bit;
1578         else
1579                 vfta &= ~vid_bit;
1580         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1581
1582         /* update local VFTA copy */
1583         shadow_vfta->vfta[vid_idx] = vfta;
1584
1585         return 0;
1586 }
1587
1588 static void
1589 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1590 {
1591         if (on)
1592                 ixgbe_vlan_hw_strip_enable(dev, queue);
1593         else
1594                 ixgbe_vlan_hw_strip_disable(dev, queue);
1595 }
1596
1597 static int
1598 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1599                     enum rte_vlan_type vlan_type,
1600                     uint16_t tpid)
1601 {
1602         struct ixgbe_hw *hw =
1603                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         int ret = 0;
1605         uint32_t reg;
1606         uint32_t qinq;
1607
1608         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1609         qinq &= IXGBE_DMATXCTL_GDV;
1610
1611         switch (vlan_type) {
1612         case ETH_VLAN_TYPE_INNER:
1613                 if (qinq) {
1614                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1615                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1616                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1617                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1618                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1619                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1620                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1621                 } else {
1622                         ret = -ENOTSUP;
1623                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1624                                     " by single VLAN");
1625                 }
1626                 break;
1627         case ETH_VLAN_TYPE_OUTER:
1628                 if (qinq) {
1629                         /* Only the high 16-bits is valid */
1630                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1631                                         IXGBE_EXVET_VET_EXT_SHIFT);
1632                 } else {
1633                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1634                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1635                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1636                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1637                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1638                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1639                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1640                 }
1641
1642                 break;
1643         default:
1644                 ret = -EINVAL;
1645                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1646                 break;
1647         }
1648
1649         return ret;
1650 }
1651
1652 void
1653 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1654 {
1655         struct ixgbe_hw *hw =
1656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657         uint32_t vlnctrl;
1658
1659         PMD_INIT_FUNC_TRACE();
1660
1661         /* Filter Table Disable */
1662         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1663         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1664
1665         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1666 }
1667
1668 void
1669 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1670 {
1671         struct ixgbe_hw *hw =
1672                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1673         struct ixgbe_vfta *shadow_vfta =
1674                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1675         uint32_t vlnctrl;
1676         uint16_t i;
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         /* Filter Table Enable */
1681         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1682         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1683         vlnctrl |= IXGBE_VLNCTRL_VFE;
1684
1685         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1686
1687         /* write whatever is in local vfta copy */
1688         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1689                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1690 }
1691
1692 static void
1693 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1694 {
1695         struct ixgbe_hwstrip *hwstrip =
1696                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1697         struct ixgbe_rx_queue *rxq;
1698
1699         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1700                 return;
1701
1702         if (on)
1703                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1704         else
1705                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1706
1707         if (queue >= dev->data->nb_rx_queues)
1708                 return;
1709
1710         rxq = dev->data->rx_queues[queue];
1711
1712         if (on)
1713                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1714         else
1715                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1716 }
1717
1718 static void
1719 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1720 {
1721         struct ixgbe_hw *hw =
1722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1723         uint32_t ctrl;
1724
1725         PMD_INIT_FUNC_TRACE();
1726
1727         if (hw->mac.type == ixgbe_mac_82598EB) {
1728                 /* No queue level support */
1729                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1730                 return;
1731         }
1732
1733         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1734         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1735         ctrl &= ~IXGBE_RXDCTL_VME;
1736         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1737
1738         /* record those setting for HW strip per queue */
1739         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1740 }
1741
1742 static void
1743 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1744 {
1745         struct ixgbe_hw *hw =
1746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747         uint32_t ctrl;
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         if (hw->mac.type == ixgbe_mac_82598EB) {
1752                 /* No queue level supported */
1753                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1754                 return;
1755         }
1756
1757         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1758         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1759         ctrl |= IXGBE_RXDCTL_VME;
1760         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1761
1762         /* record those setting for HW strip per queue */
1763         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1764 }
1765
1766 void
1767 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1768 {
1769         struct ixgbe_hw *hw =
1770                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1771         uint32_t ctrl;
1772         uint16_t i;
1773
1774         PMD_INIT_FUNC_TRACE();
1775
1776         if (hw->mac.type == ixgbe_mac_82598EB) {
1777                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1778                 ctrl &= ~IXGBE_VLNCTRL_VME;
1779                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1780         } else {
1781                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1782                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1783                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1784                         ctrl &= ~IXGBE_RXDCTL_VME;
1785                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1786
1787                         /* record those setting for HW strip per queue */
1788                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1789                 }
1790         }
1791 }
1792
1793 void
1794 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1795 {
1796         struct ixgbe_hw *hw =
1797                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798         uint32_t ctrl;
1799         uint16_t i;
1800
1801         PMD_INIT_FUNC_TRACE();
1802
1803         if (hw->mac.type == ixgbe_mac_82598EB) {
1804                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1805                 ctrl |= IXGBE_VLNCTRL_VME;
1806                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1807         } else {
1808                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1809                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1810                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1811                         ctrl |= IXGBE_RXDCTL_VME;
1812                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1813
1814                         /* record those setting for HW strip per queue */
1815                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1816                 }
1817         }
1818 }
1819
1820 static void
1821 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1822 {
1823         struct ixgbe_hw *hw =
1824                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         uint32_t ctrl;
1826
1827         PMD_INIT_FUNC_TRACE();
1828
1829         /* DMATXCTRL: Geric Double VLAN Disable */
1830         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1831         ctrl &= ~IXGBE_DMATXCTL_GDV;
1832         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1833
1834         /* CTRL_EXT: Global Double VLAN Disable */
1835         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1836         ctrl &= ~IXGBE_EXTENDED_VLAN;
1837         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1838
1839 }
1840
1841 static void
1842 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1843 {
1844         struct ixgbe_hw *hw =
1845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1846         uint32_t ctrl;
1847
1848         PMD_INIT_FUNC_TRACE();
1849
1850         /* DMATXCTRL: Geric Double VLAN Enable */
1851         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1852         ctrl |= IXGBE_DMATXCTL_GDV;
1853         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1854
1855         /* CTRL_EXT: Global Double VLAN Enable */
1856         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1857         ctrl |= IXGBE_EXTENDED_VLAN;
1858         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1859
1860         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1861         if (hw->mac.type == ixgbe_mac_X550 ||
1862             hw->mac.type == ixgbe_mac_X550EM_x ||
1863             hw->mac.type == ixgbe_mac_X550EM_a) {
1864                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1865                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1866                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1867         }
1868
1869         /*
1870          * VET EXT field in the EXVET register = 0x8100 by default
1871          * So no need to change. Same to VT field of DMATXCTL register
1872          */
1873 }
1874
1875 static void
1876 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1877 {
1878         if (mask & ETH_VLAN_STRIP_MASK) {
1879                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1880                         ixgbe_vlan_hw_strip_enable_all(dev);
1881                 else
1882                         ixgbe_vlan_hw_strip_disable_all(dev);
1883         }
1884
1885         if (mask & ETH_VLAN_FILTER_MASK) {
1886                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1887                         ixgbe_vlan_hw_filter_enable(dev);
1888                 else
1889                         ixgbe_vlan_hw_filter_disable(dev);
1890         }
1891
1892         if (mask & ETH_VLAN_EXTEND_MASK) {
1893                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1894                         ixgbe_vlan_hw_extend_enable(dev);
1895                 else
1896                         ixgbe_vlan_hw_extend_disable(dev);
1897         }
1898 }
1899
1900 static void
1901 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1902 {
1903         struct ixgbe_hw *hw =
1904                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1905         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1906         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1907
1908         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1909         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1910 }
1911
1912 static int
1913 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1914 {
1915         switch (nb_rx_q) {
1916         case 1:
1917         case 2:
1918                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1919                 break;
1920         case 4:
1921                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1922                 break;
1923         default:
1924                 return -EINVAL;
1925         }
1926
1927         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1928         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1929
1930         return 0;
1931 }
1932
1933 static int
1934 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1935 {
1936         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1939         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1940
1941         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1942                 /* check multi-queue mode */
1943                 switch (dev_conf->rxmode.mq_mode) {
1944                 case ETH_MQ_RX_VMDQ_DCB:
1945                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1946                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1947                         PMD_INIT_LOG(ERR, "SRIOV active,"
1948                                         " unsupported mq_mode rx %d.",
1949                                         dev_conf->rxmode.mq_mode);
1950                         return -EINVAL;
1951                 case ETH_MQ_RX_RSS:
1952                 case ETH_MQ_RX_VMDQ_RSS:
1953                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1954                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1955                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1956                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1957                                                 " invalid queue number"
1958                                                 " for VMDQ RSS, allowed"
1959                                                 " value are 1, 2 or 4.");
1960                                         return -EINVAL;
1961                                 }
1962                         break;
1963                 case ETH_MQ_RX_VMDQ_ONLY:
1964                 case ETH_MQ_RX_NONE:
1965                         /* if nothing mq mode configure, use default scheme */
1966                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1967                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1968                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1969                         break;
1970                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1971                         /* SRIOV only works in VMDq enable mode */
1972                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1973                                         " wrong mq_mode rx %d.",
1974                                         dev_conf->rxmode.mq_mode);
1975                         return -EINVAL;
1976                 }
1977
1978                 switch (dev_conf->txmode.mq_mode) {
1979                 case ETH_MQ_TX_VMDQ_DCB:
1980                         /* DCB VMDQ in SRIOV mode, not implement yet */
1981                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1982                                         " unsupported VMDQ mq_mode tx %d.",
1983                                         dev_conf->txmode.mq_mode);
1984                         return -EINVAL;
1985                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1986                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1987                         break;
1988                 }
1989
1990                 /* check valid queue number */
1991                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1992                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1993                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1994                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1995                                         " must be less than or equal to %d.",
1996                                         nb_rx_q, nb_tx_q,
1997                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1998                         return -EINVAL;
1999                 }
2000         } else {
2001                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2002                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2003                                           " not supported.");
2004                         return -EINVAL;
2005                 }
2006                 /* check configuration for vmdb+dcb mode */
2007                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2008                         const struct rte_eth_vmdq_dcb_conf *conf;
2009
2010                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2011                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2012                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2013                                 return -EINVAL;
2014                         }
2015                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2016                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2017                                conf->nb_queue_pools == ETH_32_POOLS)) {
2018                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2019                                                 " nb_queue_pools must be %d or %d.",
2020                                                 ETH_16_POOLS, ETH_32_POOLS);
2021                                 return -EINVAL;
2022                         }
2023                 }
2024                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2025                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2026
2027                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2028                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2029                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2030                                 return -EINVAL;
2031                         }
2032                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2033                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2034                                conf->nb_queue_pools == ETH_32_POOLS)) {
2035                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2036                                                 " nb_queue_pools != %d and"
2037                                                 " nb_queue_pools != %d.",
2038                                                 ETH_16_POOLS, ETH_32_POOLS);
2039                                 return -EINVAL;
2040                         }
2041                 }
2042
2043                 /* For DCB mode check our configuration before we go further */
2044                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2045                         const struct rte_eth_dcb_rx_conf *conf;
2046
2047                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2048                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2049                                                  IXGBE_DCB_NB_QUEUES);
2050                                 return -EINVAL;
2051                         }
2052                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2053                         if (!(conf->nb_tcs == ETH_4_TCS ||
2054                                conf->nb_tcs == ETH_8_TCS)) {
2055                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2056                                                 " and nb_tcs != %d.",
2057                                                 ETH_4_TCS, ETH_8_TCS);
2058                                 return -EINVAL;
2059                         }
2060                 }
2061
2062                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2063                         const struct rte_eth_dcb_tx_conf *conf;
2064
2065                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2066                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2067                                                  IXGBE_DCB_NB_QUEUES);
2068                                 return -EINVAL;
2069                         }
2070                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2071                         if (!(conf->nb_tcs == ETH_4_TCS ||
2072                                conf->nb_tcs == ETH_8_TCS)) {
2073                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2074                                                 " and nb_tcs != %d.",
2075                                                 ETH_4_TCS, ETH_8_TCS);
2076                                 return -EINVAL;
2077                         }
2078                 }
2079
2080                 /*
2081                  * When DCB/VT is off, maximum number of queues changes,
2082                  * except for 82598EB, which remains constant.
2083                  */
2084                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2085                                 hw->mac.type != ixgbe_mac_82598EB) {
2086                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2087                                 PMD_INIT_LOG(ERR,
2088                                              "Neither VT nor DCB are enabled, "
2089                                              "nb_tx_q > %d.",
2090                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2091                                 return -EINVAL;
2092                         }
2093                 }
2094         }
2095         return 0;
2096 }
2097
2098 static int
2099 ixgbe_dev_configure(struct rte_eth_dev *dev)
2100 {
2101         struct ixgbe_interrupt *intr =
2102                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2103         struct ixgbe_adapter *adapter =
2104                 (struct ixgbe_adapter *)dev->data->dev_private;
2105         int ret;
2106
2107         PMD_INIT_FUNC_TRACE();
2108         /* multipe queue mode checking */
2109         ret  = ixgbe_check_mq_mode(dev);
2110         if (ret != 0) {
2111                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2112                             ret);
2113                 return ret;
2114         }
2115
2116         /* set flag to update link status after init */
2117         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2118
2119         /*
2120          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2121          * allocation or vector Rx preconditions we will reset it.
2122          */
2123         adapter->rx_bulk_alloc_allowed = true;
2124         adapter->rx_vec_allowed = true;
2125
2126         return 0;
2127 }
2128
2129 static void
2130 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2131 {
2132         struct ixgbe_hw *hw =
2133                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134         struct ixgbe_interrupt *intr =
2135                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2136         uint32_t gpie;
2137
2138         /* only set up it on X550EM_X */
2139         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2140                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2141                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2142                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2143                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2144                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2145         }
2146 }
2147
2148 /*
2149  * Configure device link speed and setup link.
2150  * It returns 0 on success.
2151  */
2152 static int
2153 ixgbe_dev_start(struct rte_eth_dev *dev)
2154 {
2155         struct ixgbe_hw *hw =
2156                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2157         struct ixgbe_vf_info *vfinfo =
2158                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2159         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2160         uint32_t intr_vector = 0;
2161         int err, link_up = 0, negotiate = 0;
2162         uint32_t speed = 0;
2163         int mask = 0;
2164         int status;
2165         uint16_t vf, idx;
2166         uint32_t *link_speeds;
2167
2168         PMD_INIT_FUNC_TRACE();
2169
2170         /* IXGBE devices don't support:
2171         *    - half duplex (checked afterwards for valid speeds)
2172         *    - fixed speed: TODO implement
2173         */
2174         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2175                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2176                              dev->data->port_id);
2177                 return -EINVAL;
2178         }
2179
2180         /* disable uio/vfio intr/eventfd mapping */
2181         rte_intr_disable(intr_handle);
2182
2183         /* stop adapter */
2184         hw->adapter_stopped = 0;
2185         ixgbe_stop_adapter(hw);
2186
2187         /* reinitialize adapter
2188          * this calls reset and start
2189          */
2190         status = ixgbe_pf_reset_hw(hw);
2191         if (status != 0)
2192                 return -1;
2193         hw->mac.ops.start_hw(hw);
2194         hw->mac.get_link_status = true;
2195
2196         /* configure PF module if SRIOV enabled */
2197         ixgbe_pf_host_configure(dev);
2198
2199         ixgbe_dev_phy_intr_setup(dev);
2200
2201         /* check and configure queue intr-vector mapping */
2202         if ((rte_intr_cap_multiple(intr_handle) ||
2203              !RTE_ETH_DEV_SRIOV(dev).active) &&
2204             dev->data->dev_conf.intr_conf.rxq != 0) {
2205                 intr_vector = dev->data->nb_rx_queues;
2206                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2207                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2208                                         IXGBE_MAX_INTR_QUEUE_NUM);
2209                         return -ENOTSUP;
2210                 }
2211                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2212                         return -1;
2213         }
2214
2215         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2216                 intr_handle->intr_vec =
2217                         rte_zmalloc("intr_vec",
2218                                     dev->data->nb_rx_queues * sizeof(int), 0);
2219                 if (intr_handle->intr_vec == NULL) {
2220                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2221                                      " intr_vec\n", dev->data->nb_rx_queues);
2222                         return -ENOMEM;
2223                 }
2224         }
2225
2226         /* confiugre msix for sleep until rx interrupt */
2227         ixgbe_configure_msix(dev);
2228
2229         /* initialize transmission unit */
2230         ixgbe_dev_tx_init(dev);
2231
2232         /* This can fail when allocating mbufs for descriptor rings */
2233         err = ixgbe_dev_rx_init(dev);
2234         if (err) {
2235                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2236                 goto error;
2237         }
2238
2239         err = ixgbe_dev_rxtx_start(dev);
2240         if (err < 0) {
2241                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2242                 goto error;
2243         }
2244
2245         /* Skip link setup if loopback mode is enabled for 82599. */
2246         if (hw->mac.type == ixgbe_mac_82599EB &&
2247                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2248                 goto skip_link_setup;
2249
2250         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2251                 err = hw->mac.ops.setup_sfp(hw);
2252                 if (err)
2253                         goto error;
2254         }
2255
2256         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2257                 /* Turn on the copper */
2258                 ixgbe_set_phy_power(hw, true);
2259         } else {
2260                 /* Turn on the laser */
2261                 ixgbe_enable_tx_laser(hw);
2262         }
2263
2264         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2265         if (err)
2266                 goto error;
2267         dev->data->dev_link.link_status = link_up;
2268
2269         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2270         if (err)
2271                 goto error;
2272
2273         link_speeds = &dev->data->dev_conf.link_speeds;
2274         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2275                         ETH_LINK_SPEED_10G)) {
2276                 PMD_INIT_LOG(ERR, "Invalid link setting");
2277                 goto error;
2278         }
2279
2280         speed = 0x0;
2281         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2282                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2283                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2284                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2285         } else {
2286                 if (*link_speeds & ETH_LINK_SPEED_10G)
2287                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2288                 if (*link_speeds & ETH_LINK_SPEED_1G)
2289                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2290                 if (*link_speeds & ETH_LINK_SPEED_100M)
2291                         speed |= IXGBE_LINK_SPEED_100_FULL;
2292         }
2293
2294         err = ixgbe_setup_link(hw, speed, link_up);
2295         if (err)
2296                 goto error;
2297
2298 skip_link_setup:
2299
2300         if (rte_intr_allow_others(intr_handle)) {
2301                 /* check if lsc interrupt is enabled */
2302                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2303                         ixgbe_dev_lsc_interrupt_setup(dev);
2304         } else {
2305                 rte_intr_callback_unregister(intr_handle,
2306                                              ixgbe_dev_interrupt_handler,
2307                                              (void *)dev);
2308                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2309                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2310                                      " no intr multiplex\n");
2311         }
2312
2313         /* check if rxq interrupt is enabled */
2314         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2315             rte_intr_dp_is_en(intr_handle))
2316                 ixgbe_dev_rxq_interrupt_setup(dev);
2317
2318         /* enable uio/vfio intr/eventfd mapping */
2319         rte_intr_enable(intr_handle);
2320
2321         /* resume enabled intr since hw reset */
2322         ixgbe_enable_intr(dev);
2323
2324         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2325                 ETH_VLAN_EXTEND_MASK;
2326         ixgbe_vlan_offload_set(dev, mask);
2327
2328         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2329                 /* Enable vlan filtering for VMDq */
2330                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2331         }
2332
2333         /* Configure DCB hw */
2334         ixgbe_configure_dcb(dev);
2335
2336         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2337                 err = ixgbe_fdir_configure(dev);
2338                 if (err)
2339                         goto error;
2340         }
2341
2342         /* Restore vf rate limit */
2343         if (vfinfo != NULL) {
2344                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2345                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2346                                 if (vfinfo[vf].tx_rate[idx] != 0)
2347                                         ixgbe_set_vf_rate_limit(dev, vf,
2348                                                 vfinfo[vf].tx_rate[idx],
2349                                                 1 << idx);
2350         }
2351
2352         ixgbe_restore_statistics_mapping(dev);
2353
2354         return 0;
2355
2356 error:
2357         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2358         ixgbe_dev_clear_queues(dev);
2359         return -EIO;
2360 }
2361
2362 /*
2363  * Stop device: disable rx and tx functions to allow for reconfiguring.
2364  */
2365 static void
2366 ixgbe_dev_stop(struct rte_eth_dev *dev)
2367 {
2368         struct rte_eth_link link;
2369         struct ixgbe_hw *hw =
2370                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2371         struct ixgbe_vf_info *vfinfo =
2372                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2373         struct ixgbe_filter_info *filter_info =
2374                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2375         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2376         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2377         int vf;
2378
2379         PMD_INIT_FUNC_TRACE();
2380
2381         /* disable interrupts */
2382         ixgbe_disable_intr(hw);
2383
2384         /* reset the NIC */
2385         ixgbe_pf_reset_hw(hw);
2386         hw->adapter_stopped = 0;
2387
2388         /* stop adapter */
2389         ixgbe_stop_adapter(hw);
2390
2391         for (vf = 0; vfinfo != NULL &&
2392                      vf < dev->pci_dev->max_vfs; vf++)
2393                 vfinfo[vf].clear_to_send = false;
2394
2395         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2396                 /* Turn off the copper */
2397                 ixgbe_set_phy_power(hw, false);
2398         } else {
2399                 /* Turn off the laser */
2400                 ixgbe_disable_tx_laser(hw);
2401         }
2402
2403         ixgbe_dev_clear_queues(dev);
2404
2405         /* Clear stored conf */
2406         dev->data->scattered_rx = 0;
2407         dev->data->lro = 0;
2408
2409         /* Clear recorded link status */
2410         memset(&link, 0, sizeof(link));
2411         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2412
2413         /* Remove all ntuple filters of the device */
2414         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2415              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2416                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2417                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2418                              p_5tuple, entries);
2419                 rte_free(p_5tuple);
2420         }
2421         memset(filter_info->fivetuple_mask, 0,
2422                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2423
2424         if (!rte_intr_allow_others(intr_handle))
2425                 /* resume to the default handler */
2426                 rte_intr_callback_register(intr_handle,
2427                                            ixgbe_dev_interrupt_handler,
2428                                            (void *)dev);
2429
2430         /* Clean datapath event and queue/vec mapping */
2431         rte_intr_efd_disable(intr_handle);
2432         if (intr_handle->intr_vec != NULL) {
2433                 rte_free(intr_handle->intr_vec);
2434                 intr_handle->intr_vec = NULL;
2435         }
2436 }
2437
2438 /*
2439  * Set device link up: enable tx.
2440  */
2441 static int
2442 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2443 {
2444         struct ixgbe_hw *hw =
2445                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2446         if (hw->mac.type == ixgbe_mac_82599EB) {
2447 #ifdef RTE_NIC_BYPASS
2448                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2449                         /* Not suported in bypass mode */
2450                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2451                                      "by device id 0x%x", hw->device_id);
2452                         return -ENOTSUP;
2453                 }
2454 #endif
2455         }
2456
2457         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2458                 /* Turn on the copper */
2459                 ixgbe_set_phy_power(hw, true);
2460         } else {
2461                 /* Turn on the laser */
2462                 ixgbe_enable_tx_laser(hw);
2463         }
2464
2465         return 0;
2466 }
2467
2468 /*
2469  * Set device link down: disable tx.
2470  */
2471 static int
2472 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2473 {
2474         struct ixgbe_hw *hw =
2475                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2476         if (hw->mac.type == ixgbe_mac_82599EB) {
2477 #ifdef RTE_NIC_BYPASS
2478                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2479                         /* Not suported in bypass mode */
2480                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2481                                      "by device id 0x%x", hw->device_id);
2482                         return -ENOTSUP;
2483                 }
2484 #endif
2485         }
2486
2487         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2488                 /* Turn off the copper */
2489                 ixgbe_set_phy_power(hw, false);
2490         } else {
2491                 /* Turn off the laser */
2492                 ixgbe_disable_tx_laser(hw);
2493         }
2494
2495         return 0;
2496 }
2497
2498 /*
2499  * Reest and stop device.
2500  */
2501 static void
2502 ixgbe_dev_close(struct rte_eth_dev *dev)
2503 {
2504         struct ixgbe_hw *hw =
2505                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506
2507         PMD_INIT_FUNC_TRACE();
2508
2509         ixgbe_pf_reset_hw(hw);
2510
2511         ixgbe_dev_stop(dev);
2512         hw->adapter_stopped = 1;
2513
2514         ixgbe_dev_free_queues(dev);
2515
2516         ixgbe_disable_pcie_master(hw);
2517
2518         /* reprogram the RAR[0] in case user changed it. */
2519         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2520 }
2521
2522 static void
2523 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2524                            struct ixgbe_hw_stats *hw_stats,
2525                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2526                            uint64_t *total_qprc, uint64_t *total_qprdc)
2527 {
2528         uint32_t bprc, lxon, lxoff, total;
2529         uint32_t delta_gprc = 0;
2530         unsigned i;
2531         /* Workaround for RX byte count not including CRC bytes when CRC
2532 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2533          * is disabled.
2534 +        */
2535         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2536                         IXGBE_HLREG0_RXCRCSTRP);
2537
2538         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2539         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2540         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2541         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2542
2543         for (i = 0; i < 8; i++) {
2544                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2545
2546                 /* global total per queue */
2547                 hw_stats->mpc[i] += mp;
2548                 /* Running comprehensive total for stats display */
2549                 *total_missed_rx += hw_stats->mpc[i];
2550                 if (hw->mac.type == ixgbe_mac_82598EB) {
2551                         hw_stats->rnbc[i] +=
2552                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2553                         hw_stats->pxonrxc[i] +=
2554                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2555                         hw_stats->pxoffrxc[i] +=
2556                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2557                 } else {
2558                         hw_stats->pxonrxc[i] +=
2559                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2560                         hw_stats->pxoffrxc[i] +=
2561                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2562                         hw_stats->pxon2offc[i] +=
2563                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2564                 }
2565                 hw_stats->pxontxc[i] +=
2566                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2567                 hw_stats->pxofftxc[i] +=
2568                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2569         }
2570         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2571                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2572                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2573                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2574
2575                 delta_gprc += delta_qprc;
2576
2577                 hw_stats->qprc[i] += delta_qprc;
2578                 hw_stats->qptc[i] += delta_qptc;
2579
2580                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2581                 hw_stats->qbrc[i] +=
2582                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2583                 if (crc_strip == 0)
2584                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2585
2586                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2587                 hw_stats->qbtc[i] +=
2588                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2589
2590                 hw_stats->qprdc[i] += delta_qprdc;
2591                 *total_qprdc += hw_stats->qprdc[i];
2592
2593                 *total_qprc += hw_stats->qprc[i];
2594                 *total_qbrc += hw_stats->qbrc[i];
2595         }
2596         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2597         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2598         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2599
2600         /*
2601          * An errata states that gprc actually counts good + missed packets:
2602          * Workaround to set gprc to summated queue packet receives
2603          */
2604         hw_stats->gprc = *total_qprc;
2605
2606         if (hw->mac.type != ixgbe_mac_82598EB) {
2607                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2608                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2609                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2610                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2611                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2612                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2613                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2614                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2615         } else {
2616                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2617                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2618                 /* 82598 only has a counter in the high register */
2619                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2620                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2621                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2622         }
2623         uint64_t old_tpr = hw_stats->tpr;
2624
2625         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2626         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2627
2628         if (crc_strip == 0)
2629                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2630
2631         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2632         hw_stats->gptc += delta_gptc;
2633         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2634         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2635
2636         /*
2637          * Workaround: mprc hardware is incorrectly counting
2638          * broadcasts, so for now we subtract those.
2639          */
2640         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2641         hw_stats->bprc += bprc;
2642         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2643         if (hw->mac.type == ixgbe_mac_82598EB)
2644                 hw_stats->mprc -= bprc;
2645
2646         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2647         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2648         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2649         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2650         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2651         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2652
2653         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2654         hw_stats->lxontxc += lxon;
2655         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2656         hw_stats->lxofftxc += lxoff;
2657         total = lxon + lxoff;
2658
2659         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2660         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2661         hw_stats->gptc -= total;
2662         hw_stats->mptc -= total;
2663         hw_stats->ptc64 -= total;
2664         hw_stats->gotc -= total * ETHER_MIN_LEN;
2665
2666         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2667         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2668         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2669         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2670         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2671         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2672         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2673         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2674         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2675         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2676         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2677         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2678         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2679         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2680         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2681         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2682         /* Only read FCOE on 82599 */
2683         if (hw->mac.type != ixgbe_mac_82598EB) {
2684                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2685                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2686                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2687                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2688                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2689         }
2690
2691         /* Flow Director Stats registers */
2692         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2693         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2694 }
2695
2696 /*
2697  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2698  */
2699 static void
2700 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2701 {
2702         struct ixgbe_hw *hw =
2703                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704         struct ixgbe_hw_stats *hw_stats =
2705                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2706         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2707         unsigned i;
2708
2709         total_missed_rx = 0;
2710         total_qbrc = 0;
2711         total_qprc = 0;
2712         total_qprdc = 0;
2713
2714         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2715                         &total_qprc, &total_qprdc);
2716
2717         if (stats == NULL)
2718                 return;
2719
2720         /* Fill out the rte_eth_stats statistics structure */
2721         stats->ipackets = total_qprc;
2722         stats->ibytes = total_qbrc;
2723         stats->opackets = hw_stats->gptc;
2724         stats->obytes = hw_stats->gotc;
2725
2726         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2727                 stats->q_ipackets[i] = hw_stats->qprc[i];
2728                 stats->q_opackets[i] = hw_stats->qptc[i];
2729                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2730                 stats->q_obytes[i] = hw_stats->qbtc[i];
2731                 stats->q_errors[i] = hw_stats->qprdc[i];
2732         }
2733
2734         /* Rx Errors */
2735         stats->imissed  = total_missed_rx;
2736         stats->ierrors  = hw_stats->crcerrs +
2737                           hw_stats->mspdc +
2738                           hw_stats->rlec +
2739                           hw_stats->ruc +
2740                           hw_stats->roc +
2741                           hw_stats->illerrc +
2742                           hw_stats->errbc +
2743                           hw_stats->rfc +
2744                           hw_stats->fccrc +
2745                           hw_stats->fclast;
2746
2747         /* Tx Errors */
2748         stats->oerrors  = 0;
2749 }
2750
2751 static void
2752 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2753 {
2754         struct ixgbe_hw_stats *stats =
2755                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2756
2757         /* HW registers are cleared on read */
2758         ixgbe_dev_stats_get(dev, NULL);
2759
2760         /* Reset software totals */
2761         memset(stats, 0, sizeof(*stats));
2762 }
2763
2764 /* This function calculates the number of xstats based on the current config */
2765 static unsigned
2766 ixgbe_xstats_calc_num(void) {
2767         return IXGBE_NB_HW_STATS +
2768                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2769                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2770 }
2771
2772 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2773         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2774 {
2775         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2776         unsigned stat, i, count;
2777
2778         if (xstats_names != NULL) {
2779                 count = 0;
2780
2781                 /* Note: limit >= cnt_stats checked upstream
2782                  * in rte_eth_xstats_names()
2783                  */
2784
2785                 /* Extended stats from ixgbe_hw_stats */
2786                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2787                         xstats_names[count].id = count;
2788                         snprintf(xstats_names[count].name,
2789                                 sizeof(xstats_names[count].name),
2790                                 "%s",
2791                                 rte_ixgbe_stats_strings[i].name);
2792                         count++;
2793                 }
2794
2795                 /* RX Priority Stats */
2796                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2797                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2798                                 xstats_names[count].id = count;
2799                                 snprintf(xstats_names[count].name,
2800                                         sizeof(xstats_names[count].name),
2801                                         "rx_priority%u_%s", i,
2802                                         rte_ixgbe_rxq_strings[stat].name);
2803                                 count++;
2804                         }
2805                 }
2806
2807                 /* TX Priority Stats */
2808                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2809                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2810                                 xstats_names[count].id = count;
2811                                 snprintf(xstats_names[count].name,
2812                                         sizeof(xstats_names[count].name),
2813                                         "tx_priority%u_%s", i,
2814                                         rte_ixgbe_txq_strings[stat].name);
2815                                 count++;
2816                         }
2817                 }
2818         }
2819         return cnt_stats;
2820 }
2821
2822 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2823         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2824 {
2825         unsigned i;
2826
2827         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2828                 return -ENOMEM;
2829
2830         if (xstats_names != NULL)
2831                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2832                         snprintf(xstats_names[i].name,
2833                                 sizeof(xstats_names[i].name),
2834                                 "%s", rte_ixgbevf_stats_strings[i].name);
2835         return IXGBEVF_NB_XSTATS;
2836 }
2837
2838 static int
2839 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2840                                          unsigned n)
2841 {
2842         struct ixgbe_hw *hw =
2843                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct ixgbe_hw_stats *hw_stats =
2845                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2846         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2847         unsigned i, stat, count = 0;
2848
2849         count = ixgbe_xstats_calc_num();
2850
2851         if (n < count)
2852                 return count;
2853
2854         total_missed_rx = 0;
2855         total_qbrc = 0;
2856         total_qprc = 0;
2857         total_qprdc = 0;
2858
2859         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2860                                    &total_qprc, &total_qprdc);
2861
2862         /* If this is a reset xstats is NULL, and we have cleared the
2863          * registers by reading them.
2864          */
2865         if (!xstats)
2866                 return 0;
2867
2868         /* Extended stats from ixgbe_hw_stats */
2869         count = 0;
2870         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2871                 xstats[count].id = count;
2872                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2873                                 rte_ixgbe_stats_strings[i].offset);
2874                 count++;
2875         }
2876
2877         /* RX Priority Stats */
2878         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2879                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2880                         xstats[count].id = count;
2881                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2882                                         rte_ixgbe_rxq_strings[stat].offset +
2883                                         (sizeof(uint64_t) * i));
2884                         count++;
2885                 }
2886         }
2887
2888         /* TX Priority Stats */
2889         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2890                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2891                         xstats[count].id = count;
2892                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2893                                         rte_ixgbe_txq_strings[stat].offset +
2894                                         (sizeof(uint64_t) * i));
2895                         count++;
2896                 }
2897         }
2898         return count;
2899 }
2900
2901 static void
2902 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2903 {
2904         struct ixgbe_hw_stats *stats =
2905                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2906
2907         unsigned count = ixgbe_xstats_calc_num();
2908
2909         /* HW registers are cleared on read */
2910         ixgbe_dev_xstats_get(dev, NULL, count);
2911
2912         /* Reset software totals */
2913         memset(stats, 0, sizeof(*stats));
2914 }
2915
2916 static void
2917 ixgbevf_update_stats(struct rte_eth_dev *dev)
2918 {
2919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2920         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2921                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2922
2923         /* Good Rx packet, include VF loopback */
2924         UPDATE_VF_STAT(IXGBE_VFGPRC,
2925             hw_stats->last_vfgprc, hw_stats->vfgprc);
2926
2927         /* Good Rx octets, include VF loopback */
2928         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2929             hw_stats->last_vfgorc, hw_stats->vfgorc);
2930
2931         /* Good Tx packet, include VF loopback */
2932         UPDATE_VF_STAT(IXGBE_VFGPTC,
2933             hw_stats->last_vfgptc, hw_stats->vfgptc);
2934
2935         /* Good Tx octets, include VF loopback */
2936         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2937             hw_stats->last_vfgotc, hw_stats->vfgotc);
2938
2939         /* Rx Multicst Packet */
2940         UPDATE_VF_STAT(IXGBE_VFMPRC,
2941             hw_stats->last_vfmprc, hw_stats->vfmprc);
2942 }
2943
2944 static int
2945 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2946                        unsigned n)
2947 {
2948         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2949                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2950         unsigned i;
2951
2952         if (n < IXGBEVF_NB_XSTATS)
2953                 return IXGBEVF_NB_XSTATS;
2954
2955         ixgbevf_update_stats(dev);
2956
2957         if (!xstats)
2958                 return 0;
2959
2960         /* Extended stats */
2961         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2962                 xstats[i].id = i;
2963                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2964                         rte_ixgbevf_stats_strings[i].offset);
2965         }
2966
2967         return IXGBEVF_NB_XSTATS;
2968 }
2969
2970 static void
2971 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2972 {
2973         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2974                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2975
2976         ixgbevf_update_stats(dev);
2977
2978         if (stats == NULL)
2979                 return;
2980
2981         stats->ipackets = hw_stats->vfgprc;
2982         stats->ibytes = hw_stats->vfgorc;
2983         stats->opackets = hw_stats->vfgptc;
2984         stats->obytes = hw_stats->vfgotc;
2985 }
2986
2987 static void
2988 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2989 {
2990         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2991                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2992
2993         /* Sync HW register to the last stats */
2994         ixgbevf_dev_stats_get(dev, NULL);
2995
2996         /* reset HW current stats*/
2997         hw_stats->vfgprc = 0;
2998         hw_stats->vfgorc = 0;
2999         hw_stats->vfgptc = 0;
3000         hw_stats->vfgotc = 0;
3001 }
3002
3003 static void
3004 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3005 {
3006         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3007         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3008
3009         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3010         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3011         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3012                 /*
3013                  * When DCB/VT is off, maximum number of queues changes,
3014                  * except for 82598EB, which remains constant.
3015                  */
3016                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3017                                 hw->mac.type != ixgbe_mac_82598EB)
3018                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3019         }
3020         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3021         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3022         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3023         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3024         dev_info->max_vfs = dev->pci_dev->max_vfs;
3025         if (hw->mac.type == ixgbe_mac_82598EB)
3026                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3027         else
3028                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3029         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3030         dev_info->rx_offload_capa =
3031                 DEV_RX_OFFLOAD_VLAN_STRIP |
3032                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3033                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3034                 DEV_RX_OFFLOAD_TCP_CKSUM;
3035
3036         /*
3037          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3038          * mode.
3039          */
3040         if ((hw->mac.type == ixgbe_mac_82599EB ||
3041              hw->mac.type == ixgbe_mac_X540) &&
3042             !RTE_ETH_DEV_SRIOV(dev).active)
3043                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3044
3045         if (hw->mac.type == ixgbe_mac_X550 ||
3046             hw->mac.type == ixgbe_mac_X550EM_x ||
3047             hw->mac.type == ixgbe_mac_X550EM_a)
3048                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3049
3050         dev_info->tx_offload_capa =
3051                 DEV_TX_OFFLOAD_VLAN_INSERT |
3052                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3053                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3054                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3055                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3056                 DEV_TX_OFFLOAD_TCP_TSO;
3057
3058         if (hw->mac.type == ixgbe_mac_X550 ||
3059             hw->mac.type == ixgbe_mac_X550EM_x ||
3060             hw->mac.type == ixgbe_mac_X550EM_a)
3061                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3062
3063         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3064                 .rx_thresh = {
3065                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3066                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3067                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3068                 },
3069                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3070                 .rx_drop_en = 0,
3071         };
3072
3073         dev_info->default_txconf = (struct rte_eth_txconf) {
3074                 .tx_thresh = {
3075                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3076                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3077                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3078                 },
3079                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3080                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3081                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3082                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3083         };
3084
3085         dev_info->rx_desc_lim = rx_desc_lim;
3086         dev_info->tx_desc_lim = tx_desc_lim;
3087
3088         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3089         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3090         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3091
3092         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3093         if (hw->mac.type == ixgbe_mac_X540 ||
3094             hw->mac.type == ixgbe_mac_X540_vf ||
3095             hw->mac.type == ixgbe_mac_X550 ||
3096             hw->mac.type == ixgbe_mac_X550_vf) {
3097                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3098         }
3099 }
3100
3101 static const uint32_t *
3102 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3103 {
3104         static const uint32_t ptypes[] = {
3105                 /* For non-vec functions,
3106                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3107                  * for vec functions,
3108                  * refers to _recv_raw_pkts_vec().
3109                  */
3110                 RTE_PTYPE_L2_ETHER,
3111                 RTE_PTYPE_L3_IPV4,
3112                 RTE_PTYPE_L3_IPV4_EXT,
3113                 RTE_PTYPE_L3_IPV6,
3114                 RTE_PTYPE_L3_IPV6_EXT,
3115                 RTE_PTYPE_L4_SCTP,
3116                 RTE_PTYPE_L4_TCP,
3117                 RTE_PTYPE_L4_UDP,
3118                 RTE_PTYPE_TUNNEL_IP,
3119                 RTE_PTYPE_INNER_L3_IPV6,
3120                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3121                 RTE_PTYPE_INNER_L4_TCP,
3122                 RTE_PTYPE_INNER_L4_UDP,
3123                 RTE_PTYPE_UNKNOWN
3124         };
3125
3126         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3127             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3128             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3129             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3130                 return ptypes;
3131         return NULL;
3132 }
3133
3134 static void
3135 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3136                      struct rte_eth_dev_info *dev_info)
3137 {
3138         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3139
3140         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3141         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3142         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3143         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3144         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3145         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3146         dev_info->max_vfs = dev->pci_dev->max_vfs;
3147         if (hw->mac.type == ixgbe_mac_82598EB)
3148                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3149         else
3150                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3151         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3152                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3153                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3154                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3155         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3156                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3157                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3158                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3159                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3160                                 DEV_TX_OFFLOAD_TCP_TSO;
3161
3162         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3163                 .rx_thresh = {
3164                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3165                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3166                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3167                 },
3168                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3169                 .rx_drop_en = 0,
3170         };
3171
3172         dev_info->default_txconf = (struct rte_eth_txconf) {
3173                 .tx_thresh = {
3174                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3175                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3176                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3177                 },
3178                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3179                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3180                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3181                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3182         };
3183
3184         dev_info->rx_desc_lim = rx_desc_lim;
3185         dev_info->tx_desc_lim = tx_desc_lim;
3186 }
3187
3188 /* return 0 means link status changed, -1 means not changed */
3189 static int
3190 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3191 {
3192         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3193         struct rte_eth_link link, old;
3194         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3195         int link_up;
3196         int diag;
3197
3198         link.link_status = ETH_LINK_DOWN;
3199         link.link_speed = 0;
3200         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3201         memset(&old, 0, sizeof(old));
3202         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3203
3204         hw->mac.get_link_status = true;
3205
3206         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3207         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3208                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3209         else
3210                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3211
3212         if (diag != 0) {
3213                 link.link_speed = ETH_SPEED_NUM_100M;
3214                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3215                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3216                 if (link.link_status == old.link_status)
3217                         return -1;
3218                 return 0;
3219         }
3220
3221         if (link_up == 0) {
3222                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3223                 if (link.link_status == old.link_status)
3224                         return -1;
3225                 return 0;
3226         }
3227         link.link_status = ETH_LINK_UP;
3228         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3229
3230         switch (link_speed) {
3231         default:
3232         case IXGBE_LINK_SPEED_UNKNOWN:
3233                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3234                 link.link_speed = ETH_SPEED_NUM_100M;
3235                 break;
3236
3237         case IXGBE_LINK_SPEED_100_FULL:
3238                 link.link_speed = ETH_SPEED_NUM_100M;
3239                 break;
3240
3241         case IXGBE_LINK_SPEED_1GB_FULL:
3242                 link.link_speed = ETH_SPEED_NUM_1G;
3243                 break;
3244
3245         case IXGBE_LINK_SPEED_10GB_FULL:
3246                 link.link_speed = ETH_SPEED_NUM_10G;
3247                 break;
3248         }
3249         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3250
3251         if (link.link_status == old.link_status)
3252                 return -1;
3253
3254         return 0;
3255 }
3256
3257 static void
3258 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3259 {
3260         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3261         uint32_t fctrl;
3262
3263         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3264         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3265         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3266 }
3267
3268 static void
3269 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3270 {
3271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3272         uint32_t fctrl;
3273
3274         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3275         fctrl &= (~IXGBE_FCTRL_UPE);
3276         if (dev->data->all_multicast == 1)
3277                 fctrl |= IXGBE_FCTRL_MPE;
3278         else
3279                 fctrl &= (~IXGBE_FCTRL_MPE);
3280         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3281 }
3282
3283 static void
3284 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3285 {
3286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3287         uint32_t fctrl;
3288
3289         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3290         fctrl |= IXGBE_FCTRL_MPE;
3291         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3292 }
3293
3294 static void
3295 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3296 {
3297         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3298         uint32_t fctrl;
3299
3300         if (dev->data->promiscuous == 1)
3301                 return; /* must remain in all_multicast mode */
3302
3303         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3304         fctrl &= (~IXGBE_FCTRL_MPE);
3305         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3306 }
3307
3308 /**
3309  * It clears the interrupt causes and enables the interrupt.
3310  * It will be called once only during nic initialized.
3311  *
3312  * @param dev
3313  *  Pointer to struct rte_eth_dev.
3314  *
3315  * @return
3316  *  - On success, zero.
3317  *  - On failure, a negative value.
3318  */
3319 static int
3320 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3321 {
3322         struct ixgbe_interrupt *intr =
3323                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3324
3325         ixgbe_dev_link_status_print(dev);
3326         intr->mask |= IXGBE_EICR_LSC;
3327
3328         return 0;
3329 }
3330
3331 /**
3332  * It clears the interrupt causes and enables the interrupt.
3333  * It will be called once only during nic initialized.
3334  *
3335  * @param dev
3336  *  Pointer to struct rte_eth_dev.
3337  *
3338  * @return
3339  *  - On success, zero.
3340  *  - On failure, a negative value.
3341  */
3342 static int
3343 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3344 {
3345         struct ixgbe_interrupt *intr =
3346                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3347
3348         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3349
3350         return 0;
3351 }
3352
3353 /*
3354  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3355  *
3356  * @param dev
3357  *  Pointer to struct rte_eth_dev.
3358  *
3359  * @return
3360  *  - On success, zero.
3361  *  - On failure, a negative value.
3362  */
3363 static int
3364 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3365 {
3366         uint32_t eicr;
3367         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368         struct ixgbe_interrupt *intr =
3369                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3370
3371         /* clear all cause mask */
3372         ixgbe_disable_intr(hw);
3373
3374         /* read-on-clear nic registers here */
3375         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3376         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3377
3378         intr->flags = 0;
3379
3380         /* set flag for async link update */
3381         if (eicr & IXGBE_EICR_LSC)
3382                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3383
3384         if (eicr & IXGBE_EICR_MAILBOX)
3385                 intr->flags |= IXGBE_FLAG_MAILBOX;
3386
3387         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3388             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3389             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3390                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3391
3392         return 0;
3393 }
3394
3395 /**
3396  * It gets and then prints the link status.
3397  *
3398  * @param dev
3399  *  Pointer to struct rte_eth_dev.
3400  *
3401  * @return
3402  *  - On success, zero.
3403  *  - On failure, a negative value.
3404  */
3405 static void
3406 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3407 {
3408         struct rte_eth_link link;
3409
3410         memset(&link, 0, sizeof(link));
3411         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3412         if (link.link_status) {
3413                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3414                                         (int)(dev->data->port_id),
3415                                         (unsigned)link.link_speed,
3416                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3417                                         "full-duplex" : "half-duplex");
3418         } else {
3419                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3420                                 (int)(dev->data->port_id));
3421         }
3422         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3423                                 dev->pci_dev->addr.domain,
3424                                 dev->pci_dev->addr.bus,
3425                                 dev->pci_dev->addr.devid,
3426                                 dev->pci_dev->addr.function);
3427 }
3428
3429 /*
3430  * It executes link_update after knowing an interrupt occurred.
3431  *
3432  * @param dev
3433  *  Pointer to struct rte_eth_dev.
3434  *
3435  * @return
3436  *  - On success, zero.
3437  *  - On failure, a negative value.
3438  */
3439 static int
3440 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3441 {
3442         struct ixgbe_interrupt *intr =
3443                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3444         int64_t timeout;
3445         struct rte_eth_link link;
3446         int intr_enable_delay = false;
3447         struct ixgbe_hw *hw =
3448                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449
3450         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3451
3452         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3453                 ixgbe_pf_mbx_process(dev);
3454                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3455         }
3456
3457         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3458                 ixgbe_handle_lasi(hw);
3459                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3460         }
3461
3462         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3463                 /* get the link status before link update, for predicting later */
3464                 memset(&link, 0, sizeof(link));
3465                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3466
3467                 ixgbe_dev_link_update(dev, 0);
3468
3469                 /* likely to up */
3470                 if (!link.link_status)
3471                         /* handle it 1 sec later, wait it being stable */
3472                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3473                 /* likely to down */
3474                 else
3475                         /* handle it 4 sec later, wait it being stable */
3476                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3477
3478                 ixgbe_dev_link_status_print(dev);
3479
3480                 intr_enable_delay = true;
3481         }
3482
3483         if (intr_enable_delay) {
3484                 if (rte_eal_alarm_set(timeout * 1000,
3485                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3486                         PMD_DRV_LOG(ERR, "Error setting alarm");
3487         } else {
3488                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3489                 ixgbe_enable_intr(dev);
3490                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3491         }
3492
3493
3494         return 0;
3495 }
3496
3497 /**
3498  * Interrupt handler which shall be registered for alarm callback for delayed
3499  * handling specific interrupt to wait for the stable nic state. As the
3500  * NIC interrupt state is not stable for ixgbe after link is just down,
3501  * it needs to wait 4 seconds to get the stable status.
3502  *
3503  * @param handle
3504  *  Pointer to interrupt handle.
3505  * @param param
3506  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3507  *
3508  * @return
3509  *  void
3510  */
3511 static void
3512 ixgbe_dev_interrupt_delayed_handler(void *param)
3513 {
3514         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3515         struct ixgbe_interrupt *intr =
3516                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3517         struct ixgbe_hw *hw =
3518                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3519         uint32_t eicr;
3520
3521         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3522         if (eicr & IXGBE_EICR_MAILBOX)
3523                 ixgbe_pf_mbx_process(dev);
3524
3525         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3526                 ixgbe_handle_lasi(hw);
3527                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3528         }
3529
3530         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3531                 ixgbe_dev_link_update(dev, 0);
3532                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3533                 ixgbe_dev_link_status_print(dev);
3534                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3535         }
3536
3537         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3538         ixgbe_enable_intr(dev);
3539         rte_intr_enable(&(dev->pci_dev->intr_handle));
3540 }
3541
3542 /**
3543  * Interrupt handler triggered by NIC  for handling
3544  * specific interrupt.
3545  *
3546  * @param handle
3547  *  Pointer to interrupt handle.
3548  * @param param
3549  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3550  *
3551  * @return
3552  *  void
3553  */
3554 static void
3555 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3556                             void *param)
3557 {
3558         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3559
3560         ixgbe_dev_interrupt_get_status(dev);
3561         ixgbe_dev_interrupt_action(dev);
3562 }
3563
3564 static int
3565 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3566 {
3567         struct ixgbe_hw *hw;
3568
3569         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3570         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3571 }
3572
3573 static int
3574 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3575 {
3576         struct ixgbe_hw *hw;
3577
3578         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3579         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3580 }
3581
3582 static int
3583 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3584 {
3585         struct ixgbe_hw *hw;
3586         uint32_t mflcn_reg;
3587         uint32_t fccfg_reg;
3588         int rx_pause;
3589         int tx_pause;
3590
3591         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592
3593         fc_conf->pause_time = hw->fc.pause_time;
3594         fc_conf->high_water = hw->fc.high_water[0];
3595         fc_conf->low_water = hw->fc.low_water[0];
3596         fc_conf->send_xon = hw->fc.send_xon;
3597         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3598
3599         /*
3600          * Return rx_pause status according to actual setting of
3601          * MFLCN register.
3602          */
3603         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3604         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3605                 rx_pause = 1;
3606         else
3607                 rx_pause = 0;
3608
3609         /*
3610          * Return tx_pause status according to actual setting of
3611          * FCCFG register.
3612          */
3613         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3614         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3615                 tx_pause = 1;
3616         else
3617                 tx_pause = 0;
3618
3619         if (rx_pause && tx_pause)
3620                 fc_conf->mode = RTE_FC_FULL;
3621         else if (rx_pause)
3622                 fc_conf->mode = RTE_FC_RX_PAUSE;
3623         else if (tx_pause)
3624                 fc_conf->mode = RTE_FC_TX_PAUSE;
3625         else
3626                 fc_conf->mode = RTE_FC_NONE;
3627
3628         return 0;
3629 }
3630
3631 static int
3632 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3633 {
3634         struct ixgbe_hw *hw;
3635         int err;
3636         uint32_t rx_buf_size;
3637         uint32_t max_high_water;
3638         uint32_t mflcn;
3639         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3640                 ixgbe_fc_none,
3641                 ixgbe_fc_rx_pause,
3642                 ixgbe_fc_tx_pause,
3643                 ixgbe_fc_full
3644         };
3645
3646         PMD_INIT_FUNC_TRACE();
3647
3648         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3649         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3650         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3651
3652         /*
3653          * At least reserve one Ethernet frame for watermark
3654          * high_water/low_water in kilo bytes for ixgbe
3655          */
3656         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3657         if ((fc_conf->high_water > max_high_water) ||
3658                 (fc_conf->high_water < fc_conf->low_water)) {
3659                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3660                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3661                 return -EINVAL;
3662         }
3663
3664         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3665         hw->fc.pause_time     = fc_conf->pause_time;
3666         hw->fc.high_water[0]  = fc_conf->high_water;
3667         hw->fc.low_water[0]   = fc_conf->low_water;
3668         hw->fc.send_xon       = fc_conf->send_xon;
3669         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3670
3671         err = ixgbe_fc_enable(hw);
3672
3673         /* Not negotiated is not an error case */
3674         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3675
3676                 /* check if we want to forward MAC frames - driver doesn't have native
3677                  * capability to do that, so we'll write the registers ourselves */
3678
3679                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3680
3681                 /* set or clear MFLCN.PMCF bit depending on configuration */
3682                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3683                         mflcn |= IXGBE_MFLCN_PMCF;
3684                 else
3685                         mflcn &= ~IXGBE_MFLCN_PMCF;
3686
3687                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3688                 IXGBE_WRITE_FLUSH(hw);
3689
3690                 return 0;
3691         }
3692
3693         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3694         return -EIO;
3695 }
3696
3697 /**
3698  *  ixgbe_pfc_enable_generic - Enable flow control
3699  *  @hw: pointer to hardware structure
3700  *  @tc_num: traffic class number
3701  *  Enable flow control according to the current settings.
3702  */
3703 static int
3704 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3705 {
3706         int ret_val = 0;
3707         uint32_t mflcn_reg, fccfg_reg;
3708         uint32_t reg;
3709         uint32_t fcrtl, fcrth;
3710         uint8_t i;
3711         uint8_t nb_rx_en;
3712
3713         /* Validate the water mark configuration */
3714         if (!hw->fc.pause_time) {
3715                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3716                 goto out;
3717         }
3718
3719         /* Low water mark of zero causes XOFF floods */
3720         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3721                  /* High/Low water can not be 0 */
3722                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3723                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3724                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3725                         goto out;
3726                 }
3727
3728                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3729                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3730                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3731                         goto out;
3732                 }
3733         }
3734         /* Negotiate the fc mode to use */
3735         ixgbe_fc_autoneg(hw);
3736
3737         /* Disable any previous flow control settings */
3738         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3739         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3740
3741         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3742         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3743
3744         switch (hw->fc.current_mode) {
3745         case ixgbe_fc_none:
3746                 /*
3747                  * If the count of enabled RX Priority Flow control >1,
3748                  * and the TX pause can not be disabled
3749                  */
3750                 nb_rx_en = 0;
3751                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3752                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3753                         if (reg & IXGBE_FCRTH_FCEN)
3754                                 nb_rx_en++;
3755                 }
3756                 if (nb_rx_en > 1)
3757                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3758                 break;
3759         case ixgbe_fc_rx_pause:
3760                 /*
3761                  * Rx Flow control is enabled and Tx Flow control is
3762                  * disabled by software override. Since there really
3763                  * isn't a way to advertise that we are capable of RX
3764                  * Pause ONLY, we will advertise that we support both
3765                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3766                  * disable the adapter's ability to send PAUSE frames.
3767                  */
3768                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3769                 /*
3770                  * If the count of enabled RX Priority Flow control >1,
3771                  * and the TX pause can not be disabled
3772                  */
3773                 nb_rx_en = 0;
3774                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3775                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3776                         if (reg & IXGBE_FCRTH_FCEN)
3777                                 nb_rx_en++;
3778                 }
3779                 if (nb_rx_en > 1)
3780                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3781                 break;
3782         case ixgbe_fc_tx_pause:
3783                 /*
3784                  * Tx Flow control is enabled, and Rx Flow control is
3785                  * disabled by software override.
3786                  */
3787                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3788                 break;
3789         case ixgbe_fc_full:
3790                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3791                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3792                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3793                 break;
3794         default:
3795                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3796                 ret_val = IXGBE_ERR_CONFIG;
3797                 goto out;
3798         }
3799
3800         /* Set 802.3x based flow control settings. */
3801         mflcn_reg |= IXGBE_MFLCN_DPF;
3802         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3803         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3804
3805         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3806         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3807                 hw->fc.high_water[tc_num]) {
3808                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3809                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3810                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3811         } else {
3812                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3813                 /*
3814                  * In order to prevent Tx hangs when the internal Tx
3815                  * switch is enabled we must set the high water mark
3816                  * to the maximum FCRTH value.  This allows the Tx
3817                  * switch to function even under heavy Rx workloads.
3818                  */
3819                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3820         }
3821         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3822
3823         /* Configure pause time (2 TCs per register) */
3824         reg = hw->fc.pause_time * 0x00010001;
3825         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3826                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3827
3828         /* Configure flow control refresh threshold value */
3829         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3830
3831 out:
3832         return ret_val;
3833 }
3834
3835 static int
3836 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
3837 {
3838         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3839         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3840
3841         if (hw->mac.type != ixgbe_mac_82598EB) {
3842                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
3843         }
3844         return ret_val;
3845 }
3846
3847 static int
3848 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3849 {
3850         int err;
3851         uint32_t rx_buf_size;
3852         uint32_t max_high_water;
3853         uint8_t tc_num;
3854         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3855         struct ixgbe_hw *hw =
3856                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857         struct ixgbe_dcb_config *dcb_config =
3858                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3859
3860         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3861                 ixgbe_fc_none,
3862                 ixgbe_fc_rx_pause,
3863                 ixgbe_fc_tx_pause,
3864                 ixgbe_fc_full
3865         };
3866
3867         PMD_INIT_FUNC_TRACE();
3868
3869         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3870         tc_num = map[pfc_conf->priority];
3871         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3872         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3873         /*
3874          * At least reserve one Ethernet frame for watermark
3875          * high_water/low_water in kilo bytes for ixgbe
3876          */
3877         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3878         if ((pfc_conf->fc.high_water > max_high_water) ||
3879             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3880                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3881                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3882                 return -EINVAL;
3883         }
3884
3885         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3886         hw->fc.pause_time = pfc_conf->fc.pause_time;
3887         hw->fc.send_xon = pfc_conf->fc.send_xon;
3888         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3889         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3890
3891         err = ixgbe_dcb_pfc_enable(dev, tc_num);
3892
3893         /* Not negotiated is not an error case */
3894         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3895                 return 0;
3896
3897         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3898         return -EIO;
3899 }
3900
3901 static int
3902 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3903                           struct rte_eth_rss_reta_entry64 *reta_conf,
3904                           uint16_t reta_size)
3905 {
3906         uint16_t i, sp_reta_size;
3907         uint8_t j, mask;
3908         uint32_t reta, r;
3909         uint16_t idx, shift;
3910         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3911         uint32_t reta_reg;
3912
3913         PMD_INIT_FUNC_TRACE();
3914
3915         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3916                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3917                         "NIC.");
3918                 return -ENOTSUP;
3919         }
3920
3921         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3922         if (reta_size != sp_reta_size) {
3923                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3924                         "(%d) doesn't match the number hardware can supported "
3925                         "(%d)\n", reta_size, sp_reta_size);
3926                 return -EINVAL;
3927         }
3928
3929         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3930                 idx = i / RTE_RETA_GROUP_SIZE;
3931                 shift = i % RTE_RETA_GROUP_SIZE;
3932                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3933                                                 IXGBE_4_BIT_MASK);
3934                 if (!mask)
3935                         continue;
3936                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3937                 if (mask == IXGBE_4_BIT_MASK)
3938                         r = 0;
3939                 else
3940                         r = IXGBE_READ_REG(hw, reta_reg);
3941                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3942                         if (mask & (0x1 << j))
3943                                 reta |= reta_conf[idx].reta[shift + j] <<
3944                                                         (CHAR_BIT * j);
3945                         else
3946                                 reta |= r & (IXGBE_8_BIT_MASK <<
3947                                                 (CHAR_BIT * j));
3948                 }
3949                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3950         }
3951
3952         return 0;
3953 }
3954
3955 static int
3956 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3957                          struct rte_eth_rss_reta_entry64 *reta_conf,
3958                          uint16_t reta_size)
3959 {
3960         uint16_t i, sp_reta_size;
3961         uint8_t j, mask;
3962         uint32_t reta;
3963         uint16_t idx, shift;
3964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3965         uint32_t reta_reg;
3966
3967         PMD_INIT_FUNC_TRACE();
3968         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3969         if (reta_size != sp_reta_size) {
3970                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3971                         "(%d) doesn't match the number hardware can supported "
3972                         "(%d)\n", reta_size, sp_reta_size);
3973                 return -EINVAL;
3974         }
3975
3976         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3977                 idx = i / RTE_RETA_GROUP_SIZE;
3978                 shift = i % RTE_RETA_GROUP_SIZE;
3979                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3980                                                 IXGBE_4_BIT_MASK);
3981                 if (!mask)
3982                         continue;
3983
3984                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3985                 reta = IXGBE_READ_REG(hw, reta_reg);
3986                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3987                         if (mask & (0x1 << j))
3988                                 reta_conf[idx].reta[shift + j] =
3989                                         ((reta >> (CHAR_BIT * j)) &
3990                                                 IXGBE_8_BIT_MASK);
3991                 }
3992         }
3993
3994         return 0;
3995 }
3996
3997 static void
3998 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3999                                 uint32_t index, uint32_t pool)
4000 {
4001         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4002         uint32_t enable_addr = 1;
4003
4004         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4005 }
4006
4007 static void
4008 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4009 {
4010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011
4012         ixgbe_clear_rar(hw, index);
4013 }
4014
4015 static void
4016 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4017 {
4018         ixgbe_remove_rar(dev, 0);
4019
4020         ixgbe_add_rar(dev, addr, 0, 0);
4021 }
4022
4023 static int
4024 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4025 {
4026         uint32_t hlreg0;
4027         uint32_t maxfrs;
4028         struct ixgbe_hw *hw;
4029         struct rte_eth_dev_info dev_info;
4030         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4031
4032         ixgbe_dev_info_get(dev, &dev_info);
4033
4034         /* check that mtu is within the allowed range */
4035         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4036                 return -EINVAL;
4037
4038         /* refuse mtu that requires the support of scattered packets when this
4039          * feature has not been enabled before.
4040          */
4041         if (!dev->data->scattered_rx &&
4042             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4043              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4044                 return -EINVAL;
4045
4046         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4047         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4048
4049         /* switch to jumbo mode if needed */
4050         if (frame_size > ETHER_MAX_LEN) {
4051                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4052                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4053         } else {
4054                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4055                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4056         }
4057         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4058
4059         /* update max frame size */
4060         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4061
4062         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4063         maxfrs &= 0x0000FFFF;
4064         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4065         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4066
4067         return 0;
4068 }
4069
4070 /*
4071  * Virtual Function operations
4072  */
4073 static void
4074 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4075 {
4076         PMD_INIT_FUNC_TRACE();
4077
4078         /* Clear interrupt mask to stop from interrupts being generated */
4079         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4080
4081         IXGBE_WRITE_FLUSH(hw);
4082 }
4083
4084 static void
4085 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4086 {
4087         PMD_INIT_FUNC_TRACE();
4088
4089         /* VF enable interrupt autoclean */
4090         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4091         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4092         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4093
4094         IXGBE_WRITE_FLUSH(hw);
4095 }
4096
4097 static int
4098 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4099 {
4100         struct rte_eth_conf *conf = &dev->data->dev_conf;
4101         struct ixgbe_adapter *adapter =
4102                         (struct ixgbe_adapter *)dev->data->dev_private;
4103
4104         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4105                      dev->data->port_id);
4106
4107         /*
4108          * VF has no ability to enable/disable HW CRC
4109          * Keep the persistent behavior the same as Host PF
4110          */
4111 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4112         if (!conf->rxmode.hw_strip_crc) {
4113                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4114                 conf->rxmode.hw_strip_crc = 1;
4115         }
4116 #else
4117         if (conf->rxmode.hw_strip_crc) {
4118                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4119                 conf->rxmode.hw_strip_crc = 0;
4120         }
4121 #endif
4122
4123         /*
4124          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4125          * allocation or vector Rx preconditions we will reset it.
4126          */
4127         adapter->rx_bulk_alloc_allowed = true;
4128         adapter->rx_vec_allowed = true;
4129
4130         return 0;
4131 }
4132
4133 static int
4134 ixgbevf_dev_start(struct rte_eth_dev *dev)
4135 {
4136         struct ixgbe_hw *hw =
4137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4138         uint32_t intr_vector = 0;
4139         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4140
4141         int err, mask = 0;
4142
4143         PMD_INIT_FUNC_TRACE();
4144
4145         hw->mac.ops.reset_hw(hw);
4146         hw->mac.get_link_status = true;
4147
4148         /* negotiate mailbox API version to use with the PF. */
4149         ixgbevf_negotiate_api(hw);
4150
4151         ixgbevf_dev_tx_init(dev);
4152
4153         /* This can fail when allocating mbufs for descriptor rings */
4154         err = ixgbevf_dev_rx_init(dev);
4155         if (err) {
4156                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4157                 ixgbe_dev_clear_queues(dev);
4158                 return err;
4159         }
4160
4161         /* Set vfta */
4162         ixgbevf_set_vfta_all(dev, 1);
4163
4164         /* Set HW strip */
4165         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4166                 ETH_VLAN_EXTEND_MASK;
4167         ixgbevf_vlan_offload_set(dev, mask);
4168
4169         ixgbevf_dev_rxtx_start(dev);
4170
4171         /* check and configure queue intr-vector mapping */
4172         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4173                 intr_vector = dev->data->nb_rx_queues;
4174                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4175                         return -1;
4176         }
4177
4178         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4179                 intr_handle->intr_vec =
4180                         rte_zmalloc("intr_vec",
4181                                     dev->data->nb_rx_queues * sizeof(int), 0);
4182                 if (intr_handle->intr_vec == NULL) {
4183                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4184                                      " intr_vec\n", dev->data->nb_rx_queues);
4185                         return -ENOMEM;
4186                 }
4187         }
4188         ixgbevf_configure_msix(dev);
4189
4190         rte_intr_enable(intr_handle);
4191
4192         /* Re-enable interrupt for VF */
4193         ixgbevf_intr_enable(hw);
4194
4195         return 0;
4196 }
4197
4198 static void
4199 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4200 {
4201         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4203
4204         PMD_INIT_FUNC_TRACE();
4205
4206         ixgbevf_intr_disable(hw);
4207
4208         hw->adapter_stopped = 1;
4209         ixgbe_stop_adapter(hw);
4210
4211         /*
4212           * Clear what we set, but we still keep shadow_vfta to
4213           * restore after device starts
4214           */
4215         ixgbevf_set_vfta_all(dev, 0);
4216
4217         /* Clear stored conf */
4218         dev->data->scattered_rx = 0;
4219
4220         ixgbe_dev_clear_queues(dev);
4221
4222         /* Clean datapath event and queue/vec mapping */
4223         rte_intr_efd_disable(intr_handle);
4224         if (intr_handle->intr_vec != NULL) {
4225                 rte_free(intr_handle->intr_vec);
4226                 intr_handle->intr_vec = NULL;
4227         }
4228 }
4229
4230 static void
4231 ixgbevf_dev_close(struct rte_eth_dev *dev)
4232 {
4233         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4234
4235         PMD_INIT_FUNC_TRACE();
4236
4237         ixgbe_reset_hw(hw);
4238
4239         ixgbevf_dev_stop(dev);
4240
4241         ixgbe_dev_free_queues(dev);
4242
4243         /**
4244          * Remove the VF MAC address ro ensure
4245          * that the VF traffic goes to the PF
4246          * after stop, close and detach of the VF
4247          **/
4248         ixgbevf_remove_mac_addr(dev, 0);
4249 }
4250
4251 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4252 {
4253         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4254         struct ixgbe_vfta *shadow_vfta =
4255                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4256         int i = 0, j = 0, vfta = 0, mask = 1;
4257
4258         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4259                 vfta = shadow_vfta->vfta[i];
4260                 if (vfta) {
4261                         mask = 1;
4262                         for (j = 0; j < 32; j++) {
4263                                 if (vfta & mask)
4264                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
4265                                 mask <<= 1;
4266                         }
4267                 }
4268         }
4269
4270 }
4271
4272 static int
4273 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4274 {
4275         struct ixgbe_hw *hw =
4276                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4277         struct ixgbe_vfta *shadow_vfta =
4278                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4279         uint32_t vid_idx = 0;
4280         uint32_t vid_bit = 0;
4281         int ret = 0;
4282
4283         PMD_INIT_FUNC_TRACE();
4284
4285         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4286         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4287         if (ret) {
4288                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4289                 return ret;
4290         }
4291         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4292         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4293
4294         /* Save what we set and retore it after device reset */
4295         if (on)
4296                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4297         else
4298                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4299
4300         return 0;
4301 }
4302
4303 static void
4304 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4305 {
4306         struct ixgbe_hw *hw =
4307                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4308         uint32_t ctrl;
4309
4310         PMD_INIT_FUNC_TRACE();
4311
4312         if (queue >= hw->mac.max_rx_queues)
4313                 return;
4314
4315         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4316         if (on)
4317                 ctrl |= IXGBE_RXDCTL_VME;
4318         else
4319                 ctrl &= ~IXGBE_RXDCTL_VME;
4320         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4321
4322         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4323 }
4324
4325 static void
4326 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4327 {
4328         struct ixgbe_hw *hw =
4329                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4330         uint16_t i;
4331         int on = 0;
4332
4333         /* VF function only support hw strip feature, others are not support */
4334         if (mask & ETH_VLAN_STRIP_MASK) {
4335                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4336
4337                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4338                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4339         }
4340 }
4341
4342 static int
4343 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4344 {
4345         uint32_t reg_val;
4346
4347         /* we only need to do this if VMDq is enabled */
4348         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4349         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4350                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4351                 return -1;
4352         }
4353
4354         return 0;
4355 }
4356
4357 static uint32_t
4358 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4359 {
4360         uint32_t vector = 0;
4361
4362         switch (hw->mac.mc_filter_type) {
4363         case 0:   /* use bits [47:36] of the address */
4364                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4365                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4366                 break;
4367         case 1:   /* use bits [46:35] of the address */
4368                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4369                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4370                 break;
4371         case 2:   /* use bits [45:34] of the address */
4372                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4373                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4374                 break;
4375         case 3:   /* use bits [43:32] of the address */
4376                 vector = ((uc_addr->addr_bytes[4]) |
4377                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4378                 break;
4379         default:  /* Invalid mc_filter_type */
4380                 break;
4381         }
4382
4383         /* vector can only be 12-bits or boundary will be exceeded */
4384         vector &= 0xFFF;
4385         return vector;
4386 }
4387
4388 static int
4389 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4390                         uint8_t on)
4391 {
4392         uint32_t vector;
4393         uint32_t uta_idx;
4394         uint32_t reg_val;
4395         uint32_t uta_shift;
4396         uint32_t rc;
4397         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4398         const uint32_t ixgbe_uta_bit_shift = 5;
4399         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4400         const uint32_t bit1 = 0x1;
4401
4402         struct ixgbe_hw *hw =
4403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4404         struct ixgbe_uta_info *uta_info =
4405                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4406
4407         /* The UTA table only exists on 82599 hardware and newer */
4408         if (hw->mac.type < ixgbe_mac_82599EB)
4409                 return -ENOTSUP;
4410
4411         vector = ixgbe_uta_vector(hw, mac_addr);
4412         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4413         uta_shift = vector & ixgbe_uta_bit_mask;
4414
4415         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4416         if (rc == on)
4417                 return 0;
4418
4419         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4420         if (on) {
4421                 uta_info->uta_in_use++;
4422                 reg_val |= (bit1 << uta_shift);
4423                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4424         } else {
4425                 uta_info->uta_in_use--;
4426                 reg_val &= ~(bit1 << uta_shift);
4427                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4428         }
4429
4430         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4431
4432         if (uta_info->uta_in_use > 0)
4433                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4434                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4435         else
4436                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4437
4438         return 0;
4439 }
4440
4441 static int
4442 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4443 {
4444         int i;
4445         struct ixgbe_hw *hw =
4446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         struct ixgbe_uta_info *uta_info =
4448                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4449
4450         /* The UTA table only exists on 82599 hardware and newer */
4451         if (hw->mac.type < ixgbe_mac_82599EB)
4452                 return -ENOTSUP;
4453
4454         if (on) {
4455                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4456                         uta_info->uta_shadow[i] = ~0;
4457                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4458                 }
4459         } else {
4460                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4461                         uta_info->uta_shadow[i] = 0;
4462                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4463                 }
4464         }
4465         return 0;
4466
4467 }
4468
4469 uint32_t
4470 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4471 {
4472         uint32_t new_val = orig_val;
4473
4474         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4475                 new_val |= IXGBE_VMOLR_AUPE;
4476         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4477                 new_val |= IXGBE_VMOLR_ROMPE;
4478         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4479                 new_val |= IXGBE_VMOLR_ROPE;
4480         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4481                 new_val |= IXGBE_VMOLR_BAM;
4482         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4483                 new_val |= IXGBE_VMOLR_MPE;
4484
4485         return new_val;
4486 }
4487
4488 static int
4489 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4490                                uint16_t rx_mask, uint8_t on)
4491 {
4492         int val = 0;
4493
4494         struct ixgbe_hw *hw =
4495                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4496         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4497
4498         if (hw->mac.type == ixgbe_mac_82598EB) {
4499                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4500                              " on 82599 hardware and newer");
4501                 return -ENOTSUP;
4502         }
4503         if (ixgbe_vmdq_mode_check(hw) < 0)
4504                 return -ENOTSUP;
4505
4506         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4507
4508         if (on)
4509                 vmolr |= val;
4510         else
4511                 vmolr &= ~val;
4512
4513         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4514
4515         return 0;
4516 }
4517
4518 static int
4519 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4520 {
4521         uint32_t reg, addr;
4522         uint32_t val;
4523         const uint8_t bit1 = 0x1;
4524
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527
4528         if (ixgbe_vmdq_mode_check(hw) < 0)
4529                 return -ENOTSUP;
4530
4531         if (pool >= ETH_64_POOLS)
4532                 return -EINVAL;
4533
4534         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4535         if (pool >= 32) {
4536                 addr = IXGBE_VFRE(1);
4537                 val = bit1 << (pool - 32);
4538         } else {
4539                 addr = IXGBE_VFRE(0);
4540                 val = bit1 << pool;
4541         }
4542
4543         reg = IXGBE_READ_REG(hw, addr);
4544
4545         if (on)
4546                 reg |= val;
4547         else
4548                 reg &= ~val;
4549
4550         IXGBE_WRITE_REG(hw, addr, reg);
4551
4552         return 0;
4553 }
4554
4555 static int
4556 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4557 {
4558         uint32_t reg, addr;
4559         uint32_t val;
4560         const uint8_t bit1 = 0x1;
4561
4562         struct ixgbe_hw *hw =
4563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4564
4565         if (ixgbe_vmdq_mode_check(hw) < 0)
4566                 return -ENOTSUP;
4567
4568         if (pool >= ETH_64_POOLS)
4569                 return -EINVAL;
4570
4571         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4572         if (pool >= 32) {
4573                 addr = IXGBE_VFTE(1);
4574                 val = bit1 << (pool - 32);
4575         } else {
4576                 addr = IXGBE_VFTE(0);
4577                 val = bit1 << pool;
4578         }
4579
4580         reg = IXGBE_READ_REG(hw, addr);
4581
4582         if (on)
4583                 reg |= val;
4584         else
4585                 reg &= ~val;
4586
4587         IXGBE_WRITE_REG(hw, addr, reg);
4588
4589         return 0;
4590 }
4591
4592 static int
4593 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4594                         uint64_t pool_mask, uint8_t vlan_on)
4595 {
4596         int ret = 0;
4597         uint16_t pool_idx;
4598         struct ixgbe_hw *hw =
4599                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600
4601         if (ixgbe_vmdq_mode_check(hw) < 0)
4602                 return -ENOTSUP;
4603         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4604                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4605                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx, vlan_on);
4606                         if (ret < 0)
4607                                 return ret;
4608                 }
4609         }
4610
4611         return ret;
4612 }
4613
4614 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4615 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4616 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4617 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4618 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4619         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4620         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4621
4622 static int
4623 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4624                         struct rte_eth_mirror_conf *mirror_conf,
4625                         uint8_t rule_id, uint8_t on)
4626 {
4627         uint32_t mr_ctl, vlvf;
4628         uint32_t mp_lsb = 0;
4629         uint32_t mv_msb = 0;
4630         uint32_t mv_lsb = 0;
4631         uint32_t mp_msb = 0;
4632         uint8_t i = 0;
4633         int reg_index = 0;
4634         uint64_t vlan_mask = 0;
4635
4636         const uint8_t pool_mask_offset = 32;
4637         const uint8_t vlan_mask_offset = 32;
4638         const uint8_t dst_pool_offset = 8;
4639         const uint8_t rule_mr_offset  = 4;
4640         const uint8_t mirror_rule_mask = 0x0F;
4641
4642         struct ixgbe_mirror_info *mr_info =
4643                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4644         struct ixgbe_hw *hw =
4645                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4646         uint8_t mirror_type = 0;
4647
4648         if (ixgbe_vmdq_mode_check(hw) < 0)
4649                 return -ENOTSUP;
4650
4651         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4652                 return -EINVAL;
4653
4654         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4655                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4656                         mirror_conf->rule_type);
4657                 return -EINVAL;
4658         }
4659
4660         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4661                 mirror_type |= IXGBE_MRCTL_VLME;
4662                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4663                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
4664                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4665                                 /* search vlan id related pool vlan filter index */
4666                                 reg_index = ixgbe_find_vlvf_slot(hw,
4667                                                 mirror_conf->vlan.vlan_id[i]);
4668                                 if (reg_index < 0)
4669                                         return -EINVAL;
4670                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4671                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4672                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4673                                       mirror_conf->vlan.vlan_id[i]))
4674                                         vlan_mask |= (1ULL << reg_index);
4675                                 else
4676                                         return -EINVAL;
4677                         }
4678                 }
4679
4680                 if (on) {
4681                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4682                         mv_msb = vlan_mask >> vlan_mask_offset;
4683
4684                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4685                                                 mirror_conf->vlan.vlan_mask;
4686                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4687                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
4688                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4689                                                 mirror_conf->vlan.vlan_id[i];
4690                         }
4691                 } else {
4692                         mv_lsb = 0;
4693                         mv_msb = 0;
4694                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4695                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4696                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4697                 }
4698         }
4699
4700         /*
4701          * if enable pool mirror, write related pool mask register,if disable
4702          * pool mirror, clear PFMRVM register
4703          */
4704         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4705                 mirror_type |= IXGBE_MRCTL_VPME;
4706                 if (on) {
4707                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4708                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4709                         mr_info->mr_conf[rule_id].pool_mask =
4710                                         mirror_conf->pool_mask;
4711
4712                 } else {
4713                         mp_lsb = 0;
4714                         mp_msb = 0;
4715                         mr_info->mr_conf[rule_id].pool_mask = 0;
4716                 }
4717         }
4718         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4719                 mirror_type |= IXGBE_MRCTL_UPME;
4720         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4721                 mirror_type |= IXGBE_MRCTL_DPME;
4722
4723         /* read  mirror control register and recalculate it */
4724         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4725
4726         if (on) {
4727                 mr_ctl |= mirror_type;
4728                 mr_ctl &= mirror_rule_mask;
4729                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4730         } else
4731                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4732
4733         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4734         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4735
4736         /* write mirrror control  register */
4737         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4738
4739         /* write pool mirrror control  register */
4740         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4741                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4742                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4743                                 mp_msb);
4744         }
4745         /* write VLAN mirrror control  register */
4746         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4747                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4748                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4749                                 mv_msb);
4750         }
4751
4752         return 0;
4753 }
4754
4755 static int
4756 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4757 {
4758         int mr_ctl = 0;
4759         uint32_t lsb_val = 0;
4760         uint32_t msb_val = 0;
4761         const uint8_t rule_mr_offset = 4;
4762
4763         struct ixgbe_hw *hw =
4764                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4765         struct ixgbe_mirror_info *mr_info =
4766                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4767
4768         if (ixgbe_vmdq_mode_check(hw) < 0)
4769                 return -ENOTSUP;
4770
4771         memset(&mr_info->mr_conf[rule_id], 0,
4772                 sizeof(struct rte_eth_mirror_conf));
4773
4774         /* clear PFVMCTL register */
4775         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4776
4777         /* clear pool mask register */
4778         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4779         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4780
4781         /* clear vlan mask register */
4782         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4783         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4784
4785         return 0;
4786 }
4787
4788 static int
4789 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4790 {
4791         uint32_t mask;
4792         struct ixgbe_hw *hw =
4793                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4794
4795         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4796         mask |= (1 << IXGBE_MISC_VEC_ID);
4797         RTE_SET_USED(queue_id);
4798         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4799
4800         rte_intr_enable(&dev->pci_dev->intr_handle);
4801
4802         return 0;
4803 }
4804
4805 static int
4806 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4807 {
4808         uint32_t mask;
4809         struct ixgbe_hw *hw =
4810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4811
4812         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4813         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4814         RTE_SET_USED(queue_id);
4815         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4816
4817         return 0;
4818 }
4819
4820 static int
4821 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4822 {
4823         uint32_t mask;
4824         struct ixgbe_hw *hw =
4825                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4826         struct ixgbe_interrupt *intr =
4827                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4828
4829         if (queue_id < 16) {
4830                 ixgbe_disable_intr(hw);
4831                 intr->mask |= (1 << queue_id);
4832                 ixgbe_enable_intr(dev);
4833         } else if (queue_id < 32) {
4834                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4835                 mask &= (1 << queue_id);
4836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4837         } else if (queue_id < 64) {
4838                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4839                 mask &= (1 << (queue_id - 32));
4840                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4841         }
4842         rte_intr_enable(&dev->pci_dev->intr_handle);
4843
4844         return 0;
4845 }
4846
4847 static int
4848 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4849 {
4850         uint32_t mask;
4851         struct ixgbe_hw *hw =
4852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4853         struct ixgbe_interrupt *intr =
4854                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4855
4856         if (queue_id < 16) {
4857                 ixgbe_disable_intr(hw);
4858                 intr->mask &= ~(1 << queue_id);
4859                 ixgbe_enable_intr(dev);
4860         } else if (queue_id < 32) {
4861                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4862                 mask &= ~(1 << queue_id);
4863                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4864         } else if (queue_id < 64) {
4865                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4866                 mask &= ~(1 << (queue_id - 32));
4867                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4868         }
4869
4870         return 0;
4871 }
4872
4873 static void
4874 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4875                      uint8_t queue, uint8_t msix_vector)
4876 {
4877         uint32_t tmp, idx;
4878
4879         if (direction == -1) {
4880                 /* other causes */
4881                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4882                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4883                 tmp &= ~0xFF;
4884                 tmp |= msix_vector;
4885                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4886         } else {
4887                 /* rx or tx cause */
4888                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4889                 idx = ((16 * (queue & 1)) + (8 * direction));
4890                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4891                 tmp &= ~(0xFF << idx);
4892                 tmp |= (msix_vector << idx);
4893                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4894         }
4895 }
4896
4897 /**
4898  * set the IVAR registers, mapping interrupt causes to vectors
4899  * @param hw
4900  *  pointer to ixgbe_hw struct
4901  * @direction
4902  *  0 for Rx, 1 for Tx, -1 for other causes
4903  * @queue
4904  *  queue to map the corresponding interrupt to
4905  * @msix_vector
4906  *  the vector to map to the corresponding queue
4907  */
4908 static void
4909 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4910                    uint8_t queue, uint8_t msix_vector)
4911 {
4912         uint32_t tmp, idx;
4913
4914         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4915         if (hw->mac.type == ixgbe_mac_82598EB) {
4916                 if (direction == -1)
4917                         direction = 0;
4918                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4919                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4920                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4921                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4922                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4923         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4924                         (hw->mac.type == ixgbe_mac_X540)) {
4925                 if (direction == -1) {
4926                         /* other causes */
4927                         idx = ((queue & 1) * 8);
4928                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4929                         tmp &= ~(0xFF << idx);
4930                         tmp |= (msix_vector << idx);
4931                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4932                 } else {
4933                         /* rx or tx causes */
4934                         idx = ((16 * (queue & 1)) + (8 * direction));
4935                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4936                         tmp &= ~(0xFF << idx);
4937                         tmp |= (msix_vector << idx);
4938                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4939                 }
4940         }
4941 }
4942
4943 static void
4944 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4945 {
4946         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4947         struct ixgbe_hw *hw =
4948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         uint32_t q_idx;
4950         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4951
4952         /* Configure VF other cause ivar */
4953         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4954
4955         /* won't configure msix register if no mapping is done
4956          * between intr vector and event fd.
4957          */
4958         if (!rte_intr_dp_is_en(intr_handle))
4959                 return;
4960
4961         /* Configure all RX queues of VF */
4962         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4963                 /* Force all queue use vector 0,
4964                  * as IXGBE_VF_MAXMSIVECOTR = 1
4965                  */
4966                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4967                 intr_handle->intr_vec[q_idx] = vector_idx;
4968         }
4969 }
4970
4971 /**
4972  * Sets up the hardware to properly generate MSI-X interrupts
4973  * @hw
4974  *  board private structure
4975  */
4976 static void
4977 ixgbe_configure_msix(struct rte_eth_dev *dev)
4978 {
4979         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4980         struct ixgbe_hw *hw =
4981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4982         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4983         uint32_t vec = IXGBE_MISC_VEC_ID;
4984         uint32_t mask;
4985         uint32_t gpie;
4986
4987         /* won't configure msix register if no mapping is done
4988          * between intr vector and event fd
4989          */
4990         if (!rte_intr_dp_is_en(intr_handle))
4991                 return;
4992
4993         if (rte_intr_allow_others(intr_handle))
4994                 vec = base = IXGBE_RX_VEC_START;
4995
4996         /* setup GPIE for MSI-x mode */
4997         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4998         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4999                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5000         /* auto clearing and auto setting corresponding bits in EIMS
5001          * when MSI-X interrupt is triggered
5002          */
5003         if (hw->mac.type == ixgbe_mac_82598EB) {
5004                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5005         } else {
5006                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5007                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5008         }
5009         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5010
5011         /* Populate the IVAR table and set the ITR values to the
5012          * corresponding register.
5013          */
5014         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5015              queue_id++) {
5016                 /* by default, 1:1 mapping */
5017                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5018                 intr_handle->intr_vec[queue_id] = vec;
5019                 if (vec < base + intr_handle->nb_efd - 1)
5020                         vec++;
5021         }
5022
5023         switch (hw->mac.type) {
5024         case ixgbe_mac_82598EB:
5025                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5026                                    IXGBE_MISC_VEC_ID);
5027                 break;
5028         case ixgbe_mac_82599EB:
5029         case ixgbe_mac_X540:
5030                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5031                 break;
5032         default:
5033                 break;
5034         }
5035         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5036                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5037
5038         /* set up to autoclear timer, and the vectors */
5039         mask = IXGBE_EIMS_ENABLE_MASK;
5040         mask &= ~(IXGBE_EIMS_OTHER |
5041                   IXGBE_EIMS_MAILBOX |
5042                   IXGBE_EIMS_LSC);
5043
5044         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5045 }
5046
5047 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5048         uint16_t queue_idx, uint16_t tx_rate)
5049 {
5050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         uint32_t rf_dec, rf_int;
5052         uint32_t bcnrc_val;
5053         uint16_t link_speed = dev->data->dev_link.link_speed;
5054
5055         if (queue_idx >= hw->mac.max_tx_queues)
5056                 return -EINVAL;
5057
5058         if (tx_rate != 0) {
5059                 /* Calculate the rate factor values to set */
5060                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5061                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5062                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5063
5064                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5065                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5066                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5067                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5068         } else {
5069                 bcnrc_val = 0;
5070         }
5071
5072         /*
5073          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5074          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5075          * set as 0x4.
5076          */
5077         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5078                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5079                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5080                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5081                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5082         else
5083                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5084                         IXGBE_MMW_SIZE_DEFAULT);
5085
5086         /* Set RTTBCNRC of queue X */
5087         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5088         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5089         IXGBE_WRITE_FLUSH(hw);
5090
5091         return 0;
5092 }
5093
5094 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5095         uint16_t tx_rate, uint64_t q_msk)
5096 {
5097         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5098         struct ixgbe_vf_info *vfinfo =
5099                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5100         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5101         uint32_t queue_stride =
5102                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5103         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5104         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5105         uint16_t total_rate = 0;
5106
5107         if (queue_end >= hw->mac.max_tx_queues)
5108                 return -EINVAL;
5109
5110         if (vfinfo != NULL) {
5111                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
5112                         if (vf_idx == vf)
5113                                 continue;
5114                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5115                                 idx++)
5116                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5117                 }
5118         } else
5119                 return -EINVAL;
5120
5121         /* Store tx_rate for this vf. */
5122         for (idx = 0; idx < nb_q_per_pool; idx++) {
5123                 if (((uint64_t)0x1 << idx) & q_msk) {
5124                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5125                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5126                         total_rate += tx_rate;
5127                 }
5128         }
5129
5130         if (total_rate > dev->data->dev_link.link_speed) {
5131                 /*
5132                  * Reset stored TX rate of the VF if it causes exceed
5133                  * link speed.
5134                  */
5135                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5136                 return -EINVAL;
5137         }
5138
5139         /* Set RTTBCNRC of each queue/pool for vf X  */
5140         for (; queue_idx <= queue_end; queue_idx++) {
5141                 if (0x1 & q_msk)
5142                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5143                 q_msk = q_msk >> 1;
5144         }
5145
5146         return 0;
5147 }
5148
5149 static void
5150 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5151                      __attribute__((unused)) uint32_t index,
5152                      __attribute__((unused)) uint32_t pool)
5153 {
5154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5155         int diag;
5156
5157         /*
5158          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5159          * operation. Trap this case to avoid exhausting the [very limited]
5160          * set of PF resources used to store VF MAC addresses.
5161          */
5162         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5163                 return;
5164         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5165         if (diag == 0)
5166                 return;
5167         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5168 }
5169
5170 static void
5171 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5172 {
5173         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5174         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5175         struct ether_addr *mac_addr;
5176         uint32_t i;
5177         int diag;
5178
5179         /*
5180          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5181          * not support the deletion of a given MAC address.
5182          * Instead, it imposes to delete all MAC addresses, then to add again
5183          * all MAC addresses with the exception of the one to be deleted.
5184          */
5185         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5186
5187         /*
5188          * Add again all MAC addresses, with the exception of the deleted one
5189          * and of the permanent MAC address.
5190          */
5191         for (i = 0, mac_addr = dev->data->mac_addrs;
5192              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5193                 /* Skip the deleted MAC address */
5194                 if (i == index)
5195                         continue;
5196                 /* Skip NULL MAC addresses */
5197                 if (is_zero_ether_addr(mac_addr))
5198                         continue;
5199                 /* Skip the permanent MAC address */
5200                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5201                         continue;
5202                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5203                 if (diag != 0)
5204                         PMD_DRV_LOG(ERR,
5205                                     "Adding again MAC address "
5206                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5207                                     "diag=%d",
5208                                     mac_addr->addr_bytes[0],
5209                                     mac_addr->addr_bytes[1],
5210                                     mac_addr->addr_bytes[2],
5211                                     mac_addr->addr_bytes[3],
5212                                     mac_addr->addr_bytes[4],
5213                                     mac_addr->addr_bytes[5],
5214                                     diag);
5215         }
5216 }
5217
5218 static void
5219 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5220 {
5221         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5222
5223         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5224 }
5225
5226 #define MAC_TYPE_FILTER_SUP(type)    do {\
5227         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5228                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5229                 (type) != ixgbe_mac_X550EM_a)\
5230                 return -ENOTSUP;\
5231 } while (0)
5232
5233 static int
5234 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5235                         struct rte_eth_syn_filter *filter,
5236                         bool add)
5237 {
5238         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5239         uint32_t synqf;
5240
5241         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5242                 return -EINVAL;
5243
5244         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5245
5246         if (add) {
5247                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5248                         return -EINVAL;
5249                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5250                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5251
5252                 if (filter->hig_pri)
5253                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5254                 else
5255                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5256         } else {
5257                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5258                         return -ENOENT;
5259                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5260         }
5261         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5262         IXGBE_WRITE_FLUSH(hw);
5263         return 0;
5264 }
5265
5266 static int
5267 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5268                         struct rte_eth_syn_filter *filter)
5269 {
5270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5271         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5272
5273         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5274                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5275                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5276                 return 0;
5277         }
5278         return -ENOENT;
5279 }
5280
5281 static int
5282 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5283                         enum rte_filter_op filter_op,
5284                         void *arg)
5285 {
5286         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5287         int ret;
5288
5289         MAC_TYPE_FILTER_SUP(hw->mac.type);
5290
5291         if (filter_op == RTE_ETH_FILTER_NOP)
5292                 return 0;
5293
5294         if (arg == NULL) {
5295                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5296                             filter_op);
5297                 return -EINVAL;
5298         }
5299
5300         switch (filter_op) {
5301         case RTE_ETH_FILTER_ADD:
5302                 ret = ixgbe_syn_filter_set(dev,
5303                                 (struct rte_eth_syn_filter *)arg,
5304                                 TRUE);
5305                 break;
5306         case RTE_ETH_FILTER_DELETE:
5307                 ret = ixgbe_syn_filter_set(dev,
5308                                 (struct rte_eth_syn_filter *)arg,
5309                                 FALSE);
5310                 break;
5311         case RTE_ETH_FILTER_GET:
5312                 ret = ixgbe_syn_filter_get(dev,
5313                                 (struct rte_eth_syn_filter *)arg);
5314                 break;
5315         default:
5316                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5317                 ret = -EINVAL;
5318                 break;
5319         }
5320
5321         return ret;
5322 }
5323
5324
5325 static inline enum ixgbe_5tuple_protocol
5326 convert_protocol_type(uint8_t protocol_value)
5327 {
5328         if (protocol_value == IPPROTO_TCP)
5329                 return IXGBE_FILTER_PROTOCOL_TCP;
5330         else if (protocol_value == IPPROTO_UDP)
5331                 return IXGBE_FILTER_PROTOCOL_UDP;
5332         else if (protocol_value == IPPROTO_SCTP)
5333                 return IXGBE_FILTER_PROTOCOL_SCTP;
5334         else
5335                 return IXGBE_FILTER_PROTOCOL_NONE;
5336 }
5337
5338 /*
5339  * add a 5tuple filter
5340  *
5341  * @param
5342  * dev: Pointer to struct rte_eth_dev.
5343  * index: the index the filter allocates.
5344  * filter: ponter to the filter that will be added.
5345  * rx_queue: the queue id the filter assigned to.
5346  *
5347  * @return
5348  *    - On success, zero.
5349  *    - On failure, a negative value.
5350  */
5351 static int
5352 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5353                         struct ixgbe_5tuple_filter *filter)
5354 {
5355         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5356         struct ixgbe_filter_info *filter_info =
5357                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5358         int i, idx, shift;
5359         uint32_t ftqf, sdpqf;
5360         uint32_t l34timir = 0;
5361         uint8_t mask = 0xff;
5362
5363         /*
5364          * look for an unused 5tuple filter index,
5365          * and insert the filter to list.
5366          */
5367         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5368                 idx = i / (sizeof(uint32_t) * NBBY);
5369                 shift = i % (sizeof(uint32_t) * NBBY);
5370                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5371                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5372                         filter->index = i;
5373                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5374                                           filter,
5375                                           entries);
5376                         break;
5377                 }
5378         }
5379         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5380                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5381                 return -ENOSYS;
5382         }
5383
5384         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5385                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5386         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5387
5388         ftqf = (uint32_t)(filter->filter_info.proto &
5389                 IXGBE_FTQF_PROTOCOL_MASK);
5390         ftqf |= (uint32_t)((filter->filter_info.priority &
5391                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5392         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5393                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5394         if (filter->filter_info.dst_ip_mask == 0)
5395                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5396         if (filter->filter_info.src_port_mask == 0)
5397                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5398         if (filter->filter_info.dst_port_mask == 0)
5399                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5400         if (filter->filter_info.proto_mask == 0)
5401                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5402         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5403         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5404         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5405
5406         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5407         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5408         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5409         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5410
5411         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5412         l34timir |= (uint32_t)(filter->queue <<
5413                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5414         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5415         return 0;
5416 }
5417
5418 /*
5419  * remove a 5tuple filter
5420  *
5421  * @param
5422  * dev: Pointer to struct rte_eth_dev.
5423  * filter: the pointer of the filter will be removed.
5424  */
5425 static void
5426 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5427                         struct ixgbe_5tuple_filter *filter)
5428 {
5429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5430         struct ixgbe_filter_info *filter_info =
5431                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5432         uint16_t index = filter->index;
5433
5434         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5435                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5436         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5437         rte_free(filter);
5438
5439         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5440         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5441         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5442         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5443         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5444 }
5445
5446 static int
5447 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5448 {
5449         struct ixgbe_hw *hw;
5450         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5451
5452         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5453
5454         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5455                 return -EINVAL;
5456
5457         /* refuse mtu that requires the support of scattered packets when this
5458          * feature has not been enabled before.
5459          */
5460         if (!dev->data->scattered_rx &&
5461             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5462              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5463                 return -EINVAL;
5464
5465         /*
5466          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5467          * request of the version 2.0 of the mailbox API.
5468          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5469          * of the mailbox API.
5470          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5471          * prior to 3.11.33 which contains the following change:
5472          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5473          */
5474         ixgbevf_rlpml_set_vf(hw, max_frame);
5475
5476         /* update max frame size */
5477         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5478         return 0;
5479 }
5480
5481 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5482         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5483                 return -ENOTSUP;\
5484 } while (0)
5485
5486 static inline struct ixgbe_5tuple_filter *
5487 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5488                         struct ixgbe_5tuple_filter_info *key)
5489 {
5490         struct ixgbe_5tuple_filter *it;
5491
5492         TAILQ_FOREACH(it, filter_list, entries) {
5493                 if (memcmp(key, &it->filter_info,
5494                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5495                         return it;
5496                 }
5497         }
5498         return NULL;
5499 }
5500
5501 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5502 static inline int
5503 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5504                         struct ixgbe_5tuple_filter_info *filter_info)
5505 {
5506         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5507                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5508                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5509                 return -EINVAL;
5510
5511         switch (filter->dst_ip_mask) {
5512         case UINT32_MAX:
5513                 filter_info->dst_ip_mask = 0;
5514                 filter_info->dst_ip = filter->dst_ip;
5515                 break;
5516         case 0:
5517                 filter_info->dst_ip_mask = 1;
5518                 break;
5519         default:
5520                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5521                 return -EINVAL;
5522         }
5523
5524         switch (filter->src_ip_mask) {
5525         case UINT32_MAX:
5526                 filter_info->src_ip_mask = 0;
5527                 filter_info->src_ip = filter->src_ip;
5528                 break;
5529         case 0:
5530                 filter_info->src_ip_mask = 1;
5531                 break;
5532         default:
5533                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5534                 return -EINVAL;
5535         }
5536
5537         switch (filter->dst_port_mask) {
5538         case UINT16_MAX:
5539                 filter_info->dst_port_mask = 0;
5540                 filter_info->dst_port = filter->dst_port;
5541                 break;
5542         case 0:
5543                 filter_info->dst_port_mask = 1;
5544                 break;
5545         default:
5546                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5547                 return -EINVAL;
5548         }
5549
5550         switch (filter->src_port_mask) {
5551         case UINT16_MAX:
5552                 filter_info->src_port_mask = 0;
5553                 filter_info->src_port = filter->src_port;
5554                 break;
5555         case 0:
5556                 filter_info->src_port_mask = 1;
5557                 break;
5558         default:
5559                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5560                 return -EINVAL;
5561         }
5562
5563         switch (filter->proto_mask) {
5564         case UINT8_MAX:
5565                 filter_info->proto_mask = 0;
5566                 filter_info->proto =
5567                         convert_protocol_type(filter->proto);
5568                 break;
5569         case 0:
5570                 filter_info->proto_mask = 1;
5571                 break;
5572         default:
5573                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5574                 return -EINVAL;
5575         }
5576
5577         filter_info->priority = (uint8_t)filter->priority;
5578         return 0;
5579 }
5580
5581 /*
5582  * add or delete a ntuple filter
5583  *
5584  * @param
5585  * dev: Pointer to struct rte_eth_dev.
5586  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5587  * add: if true, add filter, if false, remove filter
5588  *
5589  * @return
5590  *    - On success, zero.
5591  *    - On failure, a negative value.
5592  */
5593 static int
5594 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5595                         struct rte_eth_ntuple_filter *ntuple_filter,
5596                         bool add)
5597 {
5598         struct ixgbe_filter_info *filter_info =
5599                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5600         struct ixgbe_5tuple_filter_info filter_5tuple;
5601         struct ixgbe_5tuple_filter *filter;
5602         int ret;
5603
5604         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5605                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5606                 return -EINVAL;
5607         }
5608
5609         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5610         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5611         if (ret < 0)
5612                 return ret;
5613
5614         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5615                                          &filter_5tuple);
5616         if (filter != NULL && add) {
5617                 PMD_DRV_LOG(ERR, "filter exists.");
5618                 return -EEXIST;
5619         }
5620         if (filter == NULL && !add) {
5621                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5622                 return -ENOENT;
5623         }
5624
5625         if (add) {
5626                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5627                                 sizeof(struct ixgbe_5tuple_filter), 0);
5628                 if (filter == NULL)
5629                         return -ENOMEM;
5630                 (void)rte_memcpy(&filter->filter_info,
5631                                  &filter_5tuple,
5632                                  sizeof(struct ixgbe_5tuple_filter_info));
5633                 filter->queue = ntuple_filter->queue;
5634                 ret = ixgbe_add_5tuple_filter(dev, filter);
5635                 if (ret < 0) {
5636                         rte_free(filter);
5637                         return ret;
5638                 }
5639         } else
5640                 ixgbe_remove_5tuple_filter(dev, filter);
5641
5642         return 0;
5643 }
5644
5645 /*
5646  * get a ntuple filter
5647  *
5648  * @param
5649  * dev: Pointer to struct rte_eth_dev.
5650  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5651  *
5652  * @return
5653  *    - On success, zero.
5654  *    - On failure, a negative value.
5655  */
5656 static int
5657 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5658                         struct rte_eth_ntuple_filter *ntuple_filter)
5659 {
5660         struct ixgbe_filter_info *filter_info =
5661                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5662         struct ixgbe_5tuple_filter_info filter_5tuple;
5663         struct ixgbe_5tuple_filter *filter;
5664         int ret;
5665
5666         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5667                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5668                 return -EINVAL;
5669         }
5670
5671         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5672         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5673         if (ret < 0)
5674                 return ret;
5675
5676         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5677                                          &filter_5tuple);
5678         if (filter == NULL) {
5679                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5680                 return -ENOENT;
5681         }
5682         ntuple_filter->queue = filter->queue;
5683         return 0;
5684 }
5685
5686 /*
5687  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5688  * @dev: pointer to rte_eth_dev structure
5689  * @filter_op:operation will be taken.
5690  * @arg: a pointer to specific structure corresponding to the filter_op
5691  *
5692  * @return
5693  *    - On success, zero.
5694  *    - On failure, a negative value.
5695  */
5696 static int
5697 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5698                                 enum rte_filter_op filter_op,
5699                                 void *arg)
5700 {
5701         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5702         int ret;
5703
5704         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5705
5706         if (filter_op == RTE_ETH_FILTER_NOP)
5707                 return 0;
5708
5709         if (arg == NULL) {
5710                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5711                             filter_op);
5712                 return -EINVAL;
5713         }
5714
5715         switch (filter_op) {
5716         case RTE_ETH_FILTER_ADD:
5717                 ret = ixgbe_add_del_ntuple_filter(dev,
5718                         (struct rte_eth_ntuple_filter *)arg,
5719                         TRUE);
5720                 break;
5721         case RTE_ETH_FILTER_DELETE:
5722                 ret = ixgbe_add_del_ntuple_filter(dev,
5723                         (struct rte_eth_ntuple_filter *)arg,
5724                         FALSE);
5725                 break;
5726         case RTE_ETH_FILTER_GET:
5727                 ret = ixgbe_get_ntuple_filter(dev,
5728                         (struct rte_eth_ntuple_filter *)arg);
5729                 break;
5730         default:
5731                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5732                 ret = -EINVAL;
5733                 break;
5734         }
5735         return ret;
5736 }
5737
5738 static inline int
5739 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5740                         uint16_t ethertype)
5741 {
5742         int i;
5743
5744         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5745                 if (filter_info->ethertype_filters[i] == ethertype &&
5746                     (filter_info->ethertype_mask & (1 << i)))
5747                         return i;
5748         }
5749         return -1;
5750 }
5751
5752 static inline int
5753 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5754                         uint16_t ethertype)
5755 {
5756         int i;
5757
5758         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5759                 if (!(filter_info->ethertype_mask & (1 << i))) {
5760                         filter_info->ethertype_mask |= 1 << i;
5761                         filter_info->ethertype_filters[i] = ethertype;
5762                         return i;
5763                 }
5764         }
5765         return -1;
5766 }
5767
5768 static inline int
5769 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5770                         uint8_t idx)
5771 {
5772         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5773                 return -1;
5774         filter_info->ethertype_mask &= ~(1 << idx);
5775         filter_info->ethertype_filters[idx] = 0;
5776         return idx;
5777 }
5778
5779 static int
5780 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5781                         struct rte_eth_ethertype_filter *filter,
5782                         bool add)
5783 {
5784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5785         struct ixgbe_filter_info *filter_info =
5786                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5787         uint32_t etqf = 0;
5788         uint32_t etqs = 0;
5789         int ret;
5790
5791         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5792                 return -EINVAL;
5793
5794         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5795                 filter->ether_type == ETHER_TYPE_IPv6) {
5796                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5797                         " ethertype filter.", filter->ether_type);
5798                 return -EINVAL;
5799         }
5800
5801         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5802                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5803                 return -EINVAL;
5804         }
5805         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5806                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5807                 return -EINVAL;
5808         }
5809
5810         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5811         if (ret >= 0 && add) {
5812                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5813                             filter->ether_type);
5814                 return -EEXIST;
5815         }
5816         if (ret < 0 && !add) {
5817                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5818                             filter->ether_type);
5819                 return -ENOENT;
5820         }
5821
5822         if (add) {
5823                 ret = ixgbe_ethertype_filter_insert(filter_info,
5824                         filter->ether_type);
5825                 if (ret < 0) {
5826                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5827                         return -ENOSYS;
5828                 }
5829                 etqf = IXGBE_ETQF_FILTER_EN;
5830                 etqf |= (uint32_t)filter->ether_type;
5831                 etqs |= (uint32_t)((filter->queue <<
5832                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5833                                     IXGBE_ETQS_RX_QUEUE);
5834                 etqs |= IXGBE_ETQS_QUEUE_EN;
5835         } else {
5836                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5837                 if (ret < 0)
5838                         return -ENOSYS;
5839         }
5840         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5841         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5842         IXGBE_WRITE_FLUSH(hw);
5843
5844         return 0;
5845 }
5846
5847 static int
5848 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5849                         struct rte_eth_ethertype_filter *filter)
5850 {
5851         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5852         struct ixgbe_filter_info *filter_info =
5853                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5854         uint32_t etqf, etqs;
5855         int ret;
5856
5857         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5858         if (ret < 0) {
5859                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5860                             filter->ether_type);
5861                 return -ENOENT;
5862         }
5863
5864         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5865         if (etqf & IXGBE_ETQF_FILTER_EN) {
5866                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5867                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5868                 filter->flags = 0;
5869                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5870                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5871                 return 0;
5872         }
5873         return -ENOENT;
5874 }
5875
5876 /*
5877  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5878  * @dev: pointer to rte_eth_dev structure
5879  * @filter_op:operation will be taken.
5880  * @arg: a pointer to specific structure corresponding to the filter_op
5881  */
5882 static int
5883 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5884                                 enum rte_filter_op filter_op,
5885                                 void *arg)
5886 {
5887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5888         int ret;
5889
5890         MAC_TYPE_FILTER_SUP(hw->mac.type);
5891
5892         if (filter_op == RTE_ETH_FILTER_NOP)
5893                 return 0;
5894
5895         if (arg == NULL) {
5896                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5897                             filter_op);
5898                 return -EINVAL;
5899         }
5900
5901         switch (filter_op) {
5902         case RTE_ETH_FILTER_ADD:
5903                 ret = ixgbe_add_del_ethertype_filter(dev,
5904                         (struct rte_eth_ethertype_filter *)arg,
5905                         TRUE);
5906                 break;
5907         case RTE_ETH_FILTER_DELETE:
5908                 ret = ixgbe_add_del_ethertype_filter(dev,
5909                         (struct rte_eth_ethertype_filter *)arg,
5910                         FALSE);
5911                 break;
5912         case RTE_ETH_FILTER_GET:
5913                 ret = ixgbe_get_ethertype_filter(dev,
5914                         (struct rte_eth_ethertype_filter *)arg);
5915                 break;
5916         default:
5917                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5918                 ret = -EINVAL;
5919                 break;
5920         }
5921         return ret;
5922 }
5923
5924 static int
5925 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5926                      enum rte_filter_type filter_type,
5927                      enum rte_filter_op filter_op,
5928                      void *arg)
5929 {
5930         int ret = -EINVAL;
5931
5932         switch (filter_type) {
5933         case RTE_ETH_FILTER_NTUPLE:
5934                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5935                 break;
5936         case RTE_ETH_FILTER_ETHERTYPE:
5937                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5938                 break;
5939         case RTE_ETH_FILTER_SYN:
5940                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5941                 break;
5942         case RTE_ETH_FILTER_FDIR:
5943                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5944                 break;
5945         case RTE_ETH_FILTER_L2_TUNNEL:
5946                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
5947                 break;
5948         default:
5949                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5950                                                         filter_type);
5951                 break;
5952         }
5953
5954         return ret;
5955 }
5956
5957 static u8 *
5958 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5959                         u8 **mc_addr_ptr, u32 *vmdq)
5960 {
5961         u8 *mc_addr;
5962
5963         *vmdq = 0;
5964         mc_addr = *mc_addr_ptr;
5965         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5966         return mc_addr;
5967 }
5968
5969 static int
5970 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5971                           struct ether_addr *mc_addr_set,
5972                           uint32_t nb_mc_addr)
5973 {
5974         struct ixgbe_hw *hw;
5975         u8 *mc_addr_list;
5976
5977         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5978         mc_addr_list = (u8 *)mc_addr_set;
5979         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5980                                          ixgbe_dev_addr_list_itr, TRUE);
5981 }
5982
5983 static uint64_t
5984 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5985 {
5986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5987         uint64_t systime_cycles;
5988
5989         switch (hw->mac.type) {
5990         case ixgbe_mac_X550:
5991         case ixgbe_mac_X550EM_x:
5992         case ixgbe_mac_X550EM_a:
5993                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5994                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5995                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5996                                 * NSEC_PER_SEC;
5997                 break;
5998         default:
5999                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6000                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6001                                 << 32;
6002         }
6003
6004         return systime_cycles;
6005 }
6006
6007 static uint64_t
6008 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6009 {
6010         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6011         uint64_t rx_tstamp_cycles;
6012
6013         switch (hw->mac.type) {
6014         case ixgbe_mac_X550:
6015         case ixgbe_mac_X550EM_x:
6016         case ixgbe_mac_X550EM_a:
6017                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6018                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6019                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6020                                 * NSEC_PER_SEC;
6021                 break;
6022         default:
6023                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6024                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6025                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6026                                 << 32;
6027         }
6028
6029         return rx_tstamp_cycles;
6030 }
6031
6032 static uint64_t
6033 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6034 {
6035         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6036         uint64_t tx_tstamp_cycles;
6037
6038         switch (hw->mac.type) {
6039         case ixgbe_mac_X550:
6040         case ixgbe_mac_X550EM_x:
6041         case ixgbe_mac_X550EM_a:
6042                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6043                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6044                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6045                                 * NSEC_PER_SEC;
6046                 break;
6047         default:
6048                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6049                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6050                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6051                                 << 32;
6052         }
6053
6054         return tx_tstamp_cycles;
6055 }
6056
6057 static void
6058 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6059 {
6060         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6061         struct ixgbe_adapter *adapter =
6062                 (struct ixgbe_adapter *)dev->data->dev_private;
6063         struct rte_eth_link link;
6064         uint32_t incval = 0;
6065         uint32_t shift = 0;
6066
6067         /* Get current link speed. */
6068         memset(&link, 0, sizeof(link));
6069         ixgbe_dev_link_update(dev, 1);
6070         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6071
6072         switch (link.link_speed) {
6073         case ETH_SPEED_NUM_100M:
6074                 incval = IXGBE_INCVAL_100;
6075                 shift = IXGBE_INCVAL_SHIFT_100;
6076                 break;
6077         case ETH_SPEED_NUM_1G:
6078                 incval = IXGBE_INCVAL_1GB;
6079                 shift = IXGBE_INCVAL_SHIFT_1GB;
6080                 break;
6081         case ETH_SPEED_NUM_10G:
6082         default:
6083                 incval = IXGBE_INCVAL_10GB;
6084                 shift = IXGBE_INCVAL_SHIFT_10GB;
6085                 break;
6086         }
6087
6088         switch (hw->mac.type) {
6089         case ixgbe_mac_X550:
6090         case ixgbe_mac_X550EM_x:
6091         case ixgbe_mac_X550EM_a:
6092                 /* Independent of link speed. */
6093                 incval = 1;
6094                 /* Cycles read will be interpreted as ns. */
6095                 shift = 0;
6096                 /* Fall-through */
6097         case ixgbe_mac_X540:
6098                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6099                 break;
6100         case ixgbe_mac_82599EB:
6101                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6102                 shift -= IXGBE_INCVAL_SHIFT_82599;
6103                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6104                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6105                 break;
6106         default:
6107                 /* Not supported. */
6108                 return;
6109         }
6110
6111         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6112         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6113         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6114
6115         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6116         adapter->systime_tc.cc_shift = shift;
6117         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6118
6119         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6120         adapter->rx_tstamp_tc.cc_shift = shift;
6121         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6122
6123         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6124         adapter->tx_tstamp_tc.cc_shift = shift;
6125         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6126 }
6127
6128 static int
6129 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6130 {
6131         struct ixgbe_adapter *adapter =
6132                         (struct ixgbe_adapter *)dev->data->dev_private;
6133
6134         adapter->systime_tc.nsec += delta;
6135         adapter->rx_tstamp_tc.nsec += delta;
6136         adapter->tx_tstamp_tc.nsec += delta;
6137
6138         return 0;
6139 }
6140
6141 static int
6142 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6143 {
6144         uint64_t ns;
6145         struct ixgbe_adapter *adapter =
6146                         (struct ixgbe_adapter *)dev->data->dev_private;
6147
6148         ns = rte_timespec_to_ns(ts);
6149         /* Set the timecounters to a new value. */
6150         adapter->systime_tc.nsec = ns;
6151         adapter->rx_tstamp_tc.nsec = ns;
6152         adapter->tx_tstamp_tc.nsec = ns;
6153
6154         return 0;
6155 }
6156
6157 static int
6158 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6159 {
6160         uint64_t ns, systime_cycles;
6161         struct ixgbe_adapter *adapter =
6162                         (struct ixgbe_adapter *)dev->data->dev_private;
6163
6164         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6165         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6166         *ts = rte_ns_to_timespec(ns);
6167
6168         return 0;
6169 }
6170
6171 static int
6172 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6173 {
6174         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175         uint32_t tsync_ctl;
6176         uint32_t tsauxc;
6177
6178         /* Stop the timesync system time. */
6179         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6180         /* Reset the timesync system time value. */
6181         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6182         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6183
6184         /* Enable system time for platforms where it isn't on by default. */
6185         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6186         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6187         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6188
6189         ixgbe_start_timecounters(dev);
6190
6191         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6192         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6193                         (ETHER_TYPE_1588 |
6194                          IXGBE_ETQF_FILTER_EN |
6195                          IXGBE_ETQF_1588));
6196
6197         /* Enable timestamping of received PTP packets. */
6198         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6199         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6200         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6201
6202         /* Enable timestamping of transmitted PTP packets. */
6203         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6204         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6205         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6206
6207         IXGBE_WRITE_FLUSH(hw);
6208
6209         return 0;
6210 }
6211
6212 static int
6213 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6214 {
6215         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6216         uint32_t tsync_ctl;
6217
6218         /* Disable timestamping of transmitted PTP packets. */
6219         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6220         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6221         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6222
6223         /* Disable timestamping of received PTP packets. */
6224         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6225         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6226         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6227
6228         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6229         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6230
6231         /* Stop incrementating the System Time registers. */
6232         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6233
6234         return 0;
6235 }
6236
6237 static int
6238 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6239                                  struct timespec *timestamp,
6240                                  uint32_t flags __rte_unused)
6241 {
6242         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6243         struct ixgbe_adapter *adapter =
6244                 (struct ixgbe_adapter *)dev->data->dev_private;
6245         uint32_t tsync_rxctl;
6246         uint64_t rx_tstamp_cycles;
6247         uint64_t ns;
6248
6249         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6250         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6251                 return -EINVAL;
6252
6253         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6254         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6255         *timestamp = rte_ns_to_timespec(ns);
6256
6257         return  0;
6258 }
6259
6260 static int
6261 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6262                                  struct timespec *timestamp)
6263 {
6264         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6265         struct ixgbe_adapter *adapter =
6266                 (struct ixgbe_adapter *)dev->data->dev_private;
6267         uint32_t tsync_txctl;
6268         uint64_t tx_tstamp_cycles;
6269         uint64_t ns;
6270
6271         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6272         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6273                 return -EINVAL;
6274
6275         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6276         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6277         *timestamp = rte_ns_to_timespec(ns);
6278
6279         return 0;
6280 }
6281
6282 static int
6283 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6284 {
6285         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6286         int count = 0;
6287         int g_ind = 0;
6288         const struct reg_info *reg_group;
6289         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6290                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6291
6292         while ((reg_group = reg_set[g_ind++]))
6293                 count += ixgbe_regs_group_count(reg_group);
6294
6295         return count;
6296 }
6297
6298 static int
6299 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6300 {
6301         int count = 0;
6302         int g_ind = 0;
6303         const struct reg_info *reg_group;
6304
6305         while ((reg_group = ixgbevf_regs[g_ind++]))
6306                 count += ixgbe_regs_group_count(reg_group);
6307
6308         return count;
6309 }
6310
6311 static int
6312 ixgbe_get_regs(struct rte_eth_dev *dev,
6313               struct rte_dev_reg_info *regs)
6314 {
6315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6316         uint32_t *data = regs->data;
6317         int g_ind = 0;
6318         int count = 0;
6319         const struct reg_info *reg_group;
6320         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6321                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6322
6323         /* Support only full register dump */
6324         if ((regs->length == 0) ||
6325             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6326                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6327                         hw->device_id;
6328                 while ((reg_group = reg_set[g_ind++]))
6329                         count += ixgbe_read_regs_group(dev, &data[count],
6330                                 reg_group);
6331                 return 0;
6332         }
6333
6334         return -ENOTSUP;
6335 }
6336
6337 static int
6338 ixgbevf_get_regs(struct rte_eth_dev *dev,
6339                 struct rte_dev_reg_info *regs)
6340 {
6341         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6342         uint32_t *data = regs->data;
6343         int g_ind = 0;
6344         int count = 0;
6345         const struct reg_info *reg_group;
6346
6347         /* Support only full register dump */
6348         if ((regs->length == 0) ||
6349             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6350                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6351                         hw->device_id;
6352                 while ((reg_group = ixgbevf_regs[g_ind++]))
6353                         count += ixgbe_read_regs_group(dev, &data[count],
6354                                                       reg_group);
6355                 return 0;
6356         }
6357
6358         return -ENOTSUP;
6359 }
6360
6361 static int
6362 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6363 {
6364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365
6366         /* Return unit is byte count */
6367         return hw->eeprom.word_size * 2;
6368 }
6369
6370 static int
6371 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6372                 struct rte_dev_eeprom_info *in_eeprom)
6373 {
6374         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6375         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6376         uint16_t *data = in_eeprom->data;
6377         int first, length;
6378
6379         first = in_eeprom->offset >> 1;
6380         length = in_eeprom->length >> 1;
6381         if ((first > hw->eeprom.word_size) ||
6382             ((first + length) > hw->eeprom.word_size))
6383                 return -EINVAL;
6384
6385         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6386
6387         return eeprom->ops.read_buffer(hw, first, length, data);
6388 }
6389
6390 static int
6391 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6392                 struct rte_dev_eeprom_info *in_eeprom)
6393 {
6394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6395         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6396         uint16_t *data = in_eeprom->data;
6397         int first, length;
6398
6399         first = in_eeprom->offset >> 1;
6400         length = in_eeprom->length >> 1;
6401         if ((first > hw->eeprom.word_size) ||
6402             ((first + length) > hw->eeprom.word_size))
6403                 return -EINVAL;
6404
6405         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6406
6407         return eeprom->ops.write_buffer(hw,  first, length, data);
6408 }
6409
6410 uint16_t
6411 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6412         switch (mac_type) {
6413         case ixgbe_mac_X550:
6414         case ixgbe_mac_X550EM_x:
6415         case ixgbe_mac_X550EM_a:
6416                 return ETH_RSS_RETA_SIZE_512;
6417         case ixgbe_mac_X550_vf:
6418         case ixgbe_mac_X550EM_x_vf:
6419         case ixgbe_mac_X550EM_a_vf:
6420                 return ETH_RSS_RETA_SIZE_64;
6421         default:
6422                 return ETH_RSS_RETA_SIZE_128;
6423         }
6424 }
6425
6426 uint32_t
6427 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6428         switch (mac_type) {
6429         case ixgbe_mac_X550:
6430         case ixgbe_mac_X550EM_x:
6431         case ixgbe_mac_X550EM_a:
6432                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6433                         return IXGBE_RETA(reta_idx >> 2);
6434                 else
6435                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6436         case ixgbe_mac_X550_vf:
6437         case ixgbe_mac_X550EM_x_vf:
6438         case ixgbe_mac_X550EM_a_vf:
6439                 return IXGBE_VFRETA(reta_idx >> 2);
6440         default:
6441                 return IXGBE_RETA(reta_idx >> 2);
6442         }
6443 }
6444
6445 uint32_t
6446 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6447         switch (mac_type) {
6448         case ixgbe_mac_X550_vf:
6449         case ixgbe_mac_X550EM_x_vf:
6450         case ixgbe_mac_X550EM_a_vf:
6451                 return IXGBE_VFMRQC;
6452         default:
6453                 return IXGBE_MRQC;
6454         }
6455 }
6456
6457 uint32_t
6458 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6459         switch (mac_type) {
6460         case ixgbe_mac_X550_vf:
6461         case ixgbe_mac_X550EM_x_vf:
6462         case ixgbe_mac_X550EM_a_vf:
6463                 return IXGBE_VFRSSRK(i);
6464         default:
6465                 return IXGBE_RSSRK(i);
6466         }
6467 }
6468
6469 bool
6470 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6471         switch (mac_type) {
6472         case ixgbe_mac_82599_vf:
6473         case ixgbe_mac_X540_vf:
6474                 return 0;
6475         default:
6476                 return 1;
6477         }
6478 }
6479
6480 static int
6481 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6482                         struct rte_eth_dcb_info *dcb_info)
6483 {
6484         struct ixgbe_dcb_config *dcb_config =
6485                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6486         struct ixgbe_dcb_tc_config *tc;
6487         uint8_t i, j;
6488
6489         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6490                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6491         else
6492                 dcb_info->nb_tcs = 1;
6493
6494         if (dcb_config->vt_mode) { /* vt is enabled*/
6495                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6496                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6497                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6498                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6499                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6500                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6501                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6502                                                 i * dcb_info->nb_tcs + j;
6503                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6504                                 dcb_info->tc_queue.tc_txq[i][j].base =
6505                                                 i * dcb_info->nb_tcs + j;
6506                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6507                         }
6508                 }
6509         } else { /* vt is disabled*/
6510                 struct rte_eth_dcb_rx_conf *rx_conf =
6511                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6512                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6513                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6514                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6515                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6516                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6517                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6518                         }
6519                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6520                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6521                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6522                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6523                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6524                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6525                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6526                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6527                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6528                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6529                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6530                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6531                         }
6532                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6533                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6534                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6535                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6536                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6537                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6538                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6539                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6540                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6541                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6542                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6543                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6544                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6545                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6546                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6547                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6548                 }
6549         }
6550         for (i = 0; i < dcb_info->nb_tcs; i++) {
6551                 tc = &dcb_config->tc_config[i];
6552                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6553         }
6554         return 0;
6555 }
6556
6557 /* Update e-tag ether type */
6558 static int
6559 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
6560                             uint16_t ether_type)
6561 {
6562         uint32_t etag_etype;
6563
6564         if (hw->mac.type != ixgbe_mac_X550 &&
6565             hw->mac.type != ixgbe_mac_X550EM_x &&
6566             hw->mac.type != ixgbe_mac_X550EM_a) {
6567                 return -ENOTSUP;
6568         }
6569
6570         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6571         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
6572         etag_etype |= ether_type;
6573         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6574         IXGBE_WRITE_FLUSH(hw);
6575
6576         return 0;
6577 }
6578
6579 /* Config l2 tunnel ether type */
6580 static int
6581 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
6582                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
6583 {
6584         int ret = 0;
6585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6586
6587         if (l2_tunnel == NULL)
6588                 return -EINVAL;
6589
6590         switch (l2_tunnel->l2_tunnel_type) {
6591         case RTE_L2_TUNNEL_TYPE_E_TAG:
6592                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
6593                 break;
6594         default:
6595                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6596                 ret = -EINVAL;
6597                 break;
6598         }
6599
6600         return ret;
6601 }
6602
6603 /* Enable e-tag tunnel */
6604 static int
6605 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
6606 {
6607         uint32_t etag_etype;
6608
6609         if (hw->mac.type != ixgbe_mac_X550 &&
6610             hw->mac.type != ixgbe_mac_X550EM_x &&
6611             hw->mac.type != ixgbe_mac_X550EM_a) {
6612                 return -ENOTSUP;
6613         }
6614
6615         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6616         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
6617         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6618         IXGBE_WRITE_FLUSH(hw);
6619
6620         return 0;
6621 }
6622
6623 /* Enable l2 tunnel */
6624 static int
6625 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
6626                            enum rte_eth_tunnel_type l2_tunnel_type)
6627 {
6628         int ret = 0;
6629         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6630
6631         switch (l2_tunnel_type) {
6632         case RTE_L2_TUNNEL_TYPE_E_TAG:
6633                 ret = ixgbe_e_tag_enable(hw);
6634                 break;
6635         default:
6636                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6637                 ret = -EINVAL;
6638                 break;
6639         }
6640
6641         return ret;
6642 }
6643
6644 /* Disable e-tag tunnel */
6645 static int
6646 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
6647 {
6648         uint32_t etag_etype;
6649
6650         if (hw->mac.type != ixgbe_mac_X550 &&
6651             hw->mac.type != ixgbe_mac_X550EM_x &&
6652             hw->mac.type != ixgbe_mac_X550EM_a) {
6653                 return -ENOTSUP;
6654         }
6655
6656         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
6657         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
6658         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
6659         IXGBE_WRITE_FLUSH(hw);
6660
6661         return 0;
6662 }
6663
6664 /* Disable l2 tunnel */
6665 static int
6666 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
6667                             enum rte_eth_tunnel_type l2_tunnel_type)
6668 {
6669         int ret = 0;
6670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6671
6672         switch (l2_tunnel_type) {
6673         case RTE_L2_TUNNEL_TYPE_E_TAG:
6674                 ret = ixgbe_e_tag_disable(hw);
6675                 break;
6676         default:
6677                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6678                 ret = -EINVAL;
6679                 break;
6680         }
6681
6682         return ret;
6683 }
6684
6685 static int
6686 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
6687                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6688 {
6689         int ret = 0;
6690         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6691         uint32_t i, rar_entries;
6692         uint32_t rar_low, rar_high;
6693
6694         if (hw->mac.type != ixgbe_mac_X550 &&
6695             hw->mac.type != ixgbe_mac_X550EM_x &&
6696             hw->mac.type != ixgbe_mac_X550EM_a) {
6697                 return -ENOTSUP;
6698         }
6699
6700         rar_entries = ixgbe_get_num_rx_addrs(hw);
6701
6702         for (i = 1; i < rar_entries; i++) {
6703                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6704                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
6705                 if ((rar_high & IXGBE_RAH_AV) &&
6706                     (rar_high & IXGBE_RAH_ADTYPE) &&
6707                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
6708                      l2_tunnel->tunnel_id)) {
6709                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
6710                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
6711
6712                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
6713
6714                         return ret;
6715                 }
6716         }
6717
6718         return ret;
6719 }
6720
6721 static int
6722 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
6723                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
6724 {
6725         int ret = 0;
6726         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6727         uint32_t i, rar_entries;
6728         uint32_t rar_low, rar_high;
6729
6730         if (hw->mac.type != ixgbe_mac_X550 &&
6731             hw->mac.type != ixgbe_mac_X550EM_x &&
6732             hw->mac.type != ixgbe_mac_X550EM_a) {
6733                 return -ENOTSUP;
6734         }
6735
6736         /* One entry for one tunnel. Try to remove potential existing entry. */
6737         ixgbe_e_tag_filter_del(dev, l2_tunnel);
6738
6739         rar_entries = ixgbe_get_num_rx_addrs(hw);
6740
6741         for (i = 1; i < rar_entries; i++) {
6742                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
6743                 if (rar_high & IXGBE_RAH_AV) {
6744                         continue;
6745                 } else {
6746                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
6747                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
6748                         rar_low = l2_tunnel->tunnel_id;
6749
6750                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
6751                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
6752
6753                         return ret;
6754                 }
6755         }
6756
6757         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
6758                      " Please remove a rule before adding a new one.");
6759         return -EINVAL;
6760 }
6761
6762 /* Add l2 tunnel filter */
6763 static int
6764 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
6765                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6766 {
6767         int ret = 0;
6768
6769         switch (l2_tunnel->l2_tunnel_type) {
6770         case RTE_L2_TUNNEL_TYPE_E_TAG:
6771                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
6772                 break;
6773         default:
6774                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6775                 ret = -EINVAL;
6776                 break;
6777         }
6778
6779         return ret;
6780 }
6781
6782 /* Delete l2 tunnel filter */
6783 static int
6784 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
6785                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
6786 {
6787         int ret = 0;
6788
6789         switch (l2_tunnel->l2_tunnel_type) {
6790         case RTE_L2_TUNNEL_TYPE_E_TAG:
6791                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
6792                 break;
6793         default:
6794                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6795                 ret = -EINVAL;
6796                 break;
6797         }
6798
6799         return ret;
6800 }
6801
6802 /**
6803  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
6804  * @dev: pointer to rte_eth_dev structure
6805  * @filter_op:operation will be taken.
6806  * @arg: a pointer to specific structure corresponding to the filter_op
6807  */
6808 static int
6809 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
6810                                   enum rte_filter_op filter_op,
6811                                   void *arg)
6812 {
6813         int ret = 0;
6814
6815         if (filter_op == RTE_ETH_FILTER_NOP)
6816                 return 0;
6817
6818         if (arg == NULL) {
6819                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6820                             filter_op);
6821                 return -EINVAL;
6822         }
6823
6824         switch (filter_op) {
6825         case RTE_ETH_FILTER_ADD:
6826                 ret = ixgbe_dev_l2_tunnel_filter_add
6827                         (dev,
6828                          (struct rte_eth_l2_tunnel_conf *)arg);
6829                 break;
6830         case RTE_ETH_FILTER_DELETE:
6831                 ret = ixgbe_dev_l2_tunnel_filter_del
6832                         (dev,
6833                          (struct rte_eth_l2_tunnel_conf *)arg);
6834                 break;
6835         default:
6836                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6837                 ret = -EINVAL;
6838                 break;
6839         }
6840         return ret;
6841 }
6842
6843 static int
6844 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
6845 {
6846         int ret = 0;
6847         uint32_t ctrl;
6848         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6849
6850         if (hw->mac.type != ixgbe_mac_X550 &&
6851             hw->mac.type != ixgbe_mac_X550EM_x &&
6852             hw->mac.type != ixgbe_mac_X550EM_a) {
6853                 return -ENOTSUP;
6854         }
6855
6856         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
6857         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
6858         if (en)
6859                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
6860         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
6861
6862         return ret;
6863 }
6864
6865 /* Enable l2 tunnel forwarding */
6866 static int
6867 ixgbe_dev_l2_tunnel_forwarding_enable
6868         (struct rte_eth_dev *dev,
6869          enum rte_eth_tunnel_type l2_tunnel_type)
6870 {
6871         int ret = 0;
6872
6873         switch (l2_tunnel_type) {
6874         case RTE_L2_TUNNEL_TYPE_E_TAG:
6875                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
6876                 break;
6877         default:
6878                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6879                 ret = -EINVAL;
6880                 break;
6881         }
6882
6883         return ret;
6884 }
6885
6886 /* Disable l2 tunnel forwarding */
6887 static int
6888 ixgbe_dev_l2_tunnel_forwarding_disable
6889         (struct rte_eth_dev *dev,
6890          enum rte_eth_tunnel_type l2_tunnel_type)
6891 {
6892         int ret = 0;
6893
6894         switch (l2_tunnel_type) {
6895         case RTE_L2_TUNNEL_TYPE_E_TAG:
6896                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
6897                 break;
6898         default:
6899                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6900                 ret = -EINVAL;
6901                 break;
6902         }
6903
6904         return ret;
6905 }
6906
6907 static int
6908 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
6909                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
6910                              bool en)
6911 {
6912         int ret = 0;
6913         uint32_t vmtir, vmvir;
6914         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6915
6916         if (l2_tunnel->vf_id >= dev->pci_dev->max_vfs) {
6917                 PMD_DRV_LOG(ERR,
6918                             "VF id %u should be less than %u",
6919                             l2_tunnel->vf_id,
6920                             dev->pci_dev->max_vfs);
6921                 return -EINVAL;
6922         }
6923
6924         if (hw->mac.type != ixgbe_mac_X550 &&
6925             hw->mac.type != ixgbe_mac_X550EM_x &&
6926             hw->mac.type != ixgbe_mac_X550EM_a) {
6927                 return -ENOTSUP;
6928         }
6929
6930         if (en)
6931                 vmtir = l2_tunnel->tunnel_id;
6932         else
6933                 vmtir = 0;
6934
6935         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
6936
6937         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
6938         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
6939         if (en)
6940                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
6941         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
6942
6943         return ret;
6944 }
6945
6946 /* Enable l2 tunnel tag insertion */
6947 static int
6948 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
6949                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
6950 {
6951         int ret = 0;
6952
6953         switch (l2_tunnel->l2_tunnel_type) {
6954         case RTE_L2_TUNNEL_TYPE_E_TAG:
6955                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
6956                 break;
6957         default:
6958                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6959                 ret = -EINVAL;
6960                 break;
6961         }
6962
6963         return ret;
6964 }
6965
6966 /* Disable l2 tunnel tag insertion */
6967 static int
6968 ixgbe_dev_l2_tunnel_insertion_disable
6969         (struct rte_eth_dev *dev,
6970          struct rte_eth_l2_tunnel_conf *l2_tunnel)
6971 {
6972         int ret = 0;
6973
6974         switch (l2_tunnel->l2_tunnel_type) {
6975         case RTE_L2_TUNNEL_TYPE_E_TAG:
6976                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
6977                 break;
6978         default:
6979                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6980                 ret = -EINVAL;
6981                 break;
6982         }
6983
6984         return ret;
6985 }
6986
6987 static int
6988 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
6989                              bool en)
6990 {
6991         int ret = 0;
6992         uint32_t qde;
6993         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6994
6995         if (hw->mac.type != ixgbe_mac_X550 &&
6996             hw->mac.type != ixgbe_mac_X550EM_x &&
6997             hw->mac.type != ixgbe_mac_X550EM_a) {
6998                 return -ENOTSUP;
6999         }
7000
7001         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7002         if (en)
7003                 qde |= IXGBE_QDE_STRIP_TAG;
7004         else
7005                 qde &= ~IXGBE_QDE_STRIP_TAG;
7006         qde &= ~IXGBE_QDE_READ;
7007         qde |= IXGBE_QDE_WRITE;
7008         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7009
7010         return ret;
7011 }
7012
7013 /* Enable l2 tunnel tag stripping */
7014 static int
7015 ixgbe_dev_l2_tunnel_stripping_enable
7016         (struct rte_eth_dev *dev,
7017          enum rte_eth_tunnel_type l2_tunnel_type)
7018 {
7019         int ret = 0;
7020
7021         switch (l2_tunnel_type) {
7022         case RTE_L2_TUNNEL_TYPE_E_TAG:
7023                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7024                 break;
7025         default:
7026                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7027                 ret = -EINVAL;
7028                 break;
7029         }
7030
7031         return ret;
7032 }
7033
7034 /* Disable l2 tunnel tag stripping */
7035 static int
7036 ixgbe_dev_l2_tunnel_stripping_disable
7037         (struct rte_eth_dev *dev,
7038          enum rte_eth_tunnel_type l2_tunnel_type)
7039 {
7040         int ret = 0;
7041
7042         switch (l2_tunnel_type) {
7043         case RTE_L2_TUNNEL_TYPE_E_TAG:
7044                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7045                 break;
7046         default:
7047                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7048                 ret = -EINVAL;
7049                 break;
7050         }
7051
7052         return ret;
7053 }
7054
7055 /* Enable/disable l2 tunnel offload functions */
7056 static int
7057 ixgbe_dev_l2_tunnel_offload_set
7058         (struct rte_eth_dev *dev,
7059          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7060          uint32_t mask,
7061          uint8_t en)
7062 {
7063         int ret = 0;
7064
7065         if (l2_tunnel == NULL)
7066                 return -EINVAL;
7067
7068         ret = -EINVAL;
7069         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7070                 if (en)
7071                         ret = ixgbe_dev_l2_tunnel_enable(
7072                                 dev,
7073                                 l2_tunnel->l2_tunnel_type);
7074                 else
7075                         ret = ixgbe_dev_l2_tunnel_disable(
7076                                 dev,
7077                                 l2_tunnel->l2_tunnel_type);
7078         }
7079
7080         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7081                 if (en)
7082                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7083                                 dev,
7084                                 l2_tunnel);
7085                 else
7086                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7087                                 dev,
7088                                 l2_tunnel);
7089         }
7090
7091         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7092                 if (en)
7093                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7094                                 dev,
7095                                 l2_tunnel->l2_tunnel_type);
7096                 else
7097                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7098                                 dev,
7099                                 l2_tunnel->l2_tunnel_type);
7100         }
7101
7102         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7103                 if (en)
7104                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7105                                 dev,
7106                                 l2_tunnel->l2_tunnel_type);
7107                 else
7108                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7109                                 dev,
7110                                 l2_tunnel->l2_tunnel_type);
7111         }
7112
7113         return ret;
7114 }
7115
7116 static int
7117 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7118                         uint16_t port)
7119 {
7120         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7121         IXGBE_WRITE_FLUSH(hw);
7122
7123         return 0;
7124 }
7125
7126 /* There's only one register for VxLAN UDP port.
7127  * So, we cannot add several ports. Will update it.
7128  */
7129 static int
7130 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7131                      uint16_t port)
7132 {
7133         if (port == 0) {
7134                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7135                 return -EINVAL;
7136         }
7137
7138         return ixgbe_update_vxlan_port(hw, port);
7139 }
7140
7141 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7142  * UDP port, it must have a value.
7143  * So, will reset it to the original value 0.
7144  */
7145 static int
7146 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7147                      uint16_t port)
7148 {
7149         uint16_t cur_port;
7150
7151         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7152
7153         if (cur_port != port) {
7154                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7155                 return -EINVAL;
7156         }
7157
7158         return ixgbe_update_vxlan_port(hw, 0);
7159 }
7160
7161 /* Add UDP tunneling port */
7162 static int
7163 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7164                               struct rte_eth_udp_tunnel *udp_tunnel)
7165 {
7166         int ret = 0;
7167         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7168
7169         if (hw->mac.type != ixgbe_mac_X550 &&
7170             hw->mac.type != ixgbe_mac_X550EM_x &&
7171             hw->mac.type != ixgbe_mac_X550EM_a) {
7172                 return -ENOTSUP;
7173         }
7174
7175         if (udp_tunnel == NULL)
7176                 return -EINVAL;
7177
7178         switch (udp_tunnel->prot_type) {
7179         case RTE_TUNNEL_TYPE_VXLAN:
7180                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7181                 break;
7182
7183         case RTE_TUNNEL_TYPE_GENEVE:
7184         case RTE_TUNNEL_TYPE_TEREDO:
7185                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7186                 ret = -EINVAL;
7187                 break;
7188
7189         default:
7190                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7191                 ret = -EINVAL;
7192                 break;
7193         }
7194
7195         return ret;
7196 }
7197
7198 /* Remove UDP tunneling port */
7199 static int
7200 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7201                               struct rte_eth_udp_tunnel *udp_tunnel)
7202 {
7203         int ret = 0;
7204         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7205
7206         if (hw->mac.type != ixgbe_mac_X550 &&
7207             hw->mac.type != ixgbe_mac_X550EM_x &&
7208             hw->mac.type != ixgbe_mac_X550EM_a) {
7209                 return -ENOTSUP;
7210         }
7211
7212         if (udp_tunnel == NULL)
7213                 return -EINVAL;
7214
7215         switch (udp_tunnel->prot_type) {
7216         case RTE_TUNNEL_TYPE_VXLAN:
7217                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7218                 break;
7219         case RTE_TUNNEL_TYPE_GENEVE:
7220         case RTE_TUNNEL_TYPE_TEREDO:
7221                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7222                 ret = -EINVAL;
7223                 break;
7224         default:
7225                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7226                 ret = -EINVAL;
7227                 break;
7228         }
7229
7230         return ret;
7231 }
7232
7233 /* ixgbevf_update_xcast_mode - Update Multicast mode
7234  * @hw: pointer to the HW structure
7235  * @netdev: pointer to net device structure
7236  * @xcast_mode: new multicast mode
7237  *
7238  * Updates the Multicast Mode of VF.
7239  */
7240 static int ixgbevf_update_xcast_mode(struct ixgbe_hw *hw,
7241                                      int xcast_mode)
7242 {
7243         struct ixgbe_mbx_info *mbx = &hw->mbx;
7244         u32 msgbuf[2];
7245         s32 err;
7246
7247         switch (hw->api_version) {
7248         case ixgbe_mbox_api_12:
7249                 break;
7250         default:
7251                 return -EOPNOTSUPP;
7252         }
7253
7254         msgbuf[0] = IXGBE_VF_UPDATE_XCAST_MODE;
7255         msgbuf[1] = xcast_mode;
7256
7257         err = mbx->ops.write_posted(hw, msgbuf, 2, 0);
7258         if (err)
7259                 return err;
7260
7261         err = mbx->ops.read_posted(hw, msgbuf, 2, 0);
7262         if (err)
7263                 return err;
7264
7265         msgbuf[0] &= ~IXGBE_VT_MSGTYPE_CTS;
7266         if (msgbuf[0] == (IXGBE_VF_UPDATE_XCAST_MODE | IXGBE_VT_MSGTYPE_NACK))
7267                 return -EPERM;
7268
7269         return 0;
7270 }
7271
7272 static void
7273 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7274 {
7275         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7276
7277         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7278 }
7279
7280 static void
7281 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7282 {
7283         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7284
7285         ixgbevf_update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7286 }
7287
7288 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7289 {
7290         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7291         u32 in_msg = 0;
7292
7293         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7294                 return;
7295
7296         /* PF reset VF event */
7297         if (in_msg == IXGBE_PF_CONTROL_MSG)
7298                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
7299 }
7300
7301 static int
7302 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7303 {
7304         uint32_t eicr;
7305         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7306         struct ixgbe_interrupt *intr =
7307                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7308         ixgbevf_intr_disable(hw);
7309
7310         /* read-on-clear nic registers here */
7311         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7312         intr->flags = 0;
7313
7314         /* only one misc vector supported - mailbox */
7315         eicr &= IXGBE_VTEICR_MASK;
7316         if (eicr == IXGBE_MISC_VEC_ID)
7317                 intr->flags |= IXGBE_FLAG_MAILBOX;
7318
7319         return 0;
7320 }
7321
7322 static int
7323 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7324 {
7325         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7326         struct ixgbe_interrupt *intr =
7327                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7328
7329         if (intr->flags & IXGBE_FLAG_MAILBOX) {
7330                 ixgbevf_mbx_process(dev);
7331                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7332         }
7333
7334         ixgbevf_intr_enable(hw);
7335
7336         return 0;
7337 }
7338
7339 static void
7340 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
7341                               void *param)
7342 {
7343         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7344
7345         ixgbevf_dev_interrupt_get_status(dev);
7346         ixgbevf_dev_interrupt_action(dev);
7347 }
7348
7349 static struct rte_driver rte_ixgbe_driver = {
7350         .type = PMD_PDEV,
7351         .init = rte_ixgbe_pmd_init,
7352 };
7353
7354 static struct rte_driver rte_ixgbevf_driver = {
7355         .type = PMD_PDEV,
7356         .init = rte_ixgbevf_pmd_init,
7357 };
7358
7359 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
7360 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);