drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 153 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 155                                              uint16_t queue_id,
 156                                              uint8_t stat_idx,
 157                                              uint8_t is_rx);
 158 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 159                                struct rte_eth_dev_info *dev_info);
 160 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 161                                  struct rte_eth_dev_info *dev_info);
 162 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 163
 164 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 165                 uint16_t vlan_id, int on);
 166 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 167 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 168                 uint16_t queue, bool on);
 169 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 170                 int on);
 171 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 172 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 173 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 174 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 176
 177 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 179 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 180                                struct rte_eth_fc_conf *fc_conf);
 181 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 184                 struct rte_eth_pfc_conf *pfc_conf);
 185 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 186                         struct rte_eth_rss_reta_entry64 *reta_conf,
 187                         uint16_t reta_size);
 188 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 189                         struct rte_eth_rss_reta_entry64 *reta_conf,
 190                         uint16_t reta_size);
 191 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 192 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 193 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 196 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 197                 void *param);
 198 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 199 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 200                 uint32_t index, uint32_t pool);
 201 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 202 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 203                                            struct ether_addr *mac_addr);
 204 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 205
 206 /* For Virtual Function support */
 207 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 208 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 209 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 210 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 211 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 212 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 213 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 214 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 215 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 216 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 217 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 218                 struct rte_eth_stats *stats);
 219 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 220 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 221                 uint16_t vlan_id, int on);
 222 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 223                 uint16_t queue, int on);
 224 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 225 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 226 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 227                                           void *param);
 228 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 229                                             uint16_t queue_id);
 230 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 231                                              uint16_t queue_id);
 232 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 233                                  uint8_t queue, uint8_t msix_vector);
 234 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 235
 236 /* For Eth VMDQ APIs support */
 237 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 238                 ether_addr* mac_addr,uint8_t on);
 239 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 240 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 241                 uint16_t rx_mask, uint8_t on);
 242 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 243 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 244 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 245                 uint64_t pool_mask,uint8_t vlan_on);
 246 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 247                 struct rte_eth_mirror_conf *mirror_conf,
 248                 uint8_t rule_id, uint8_t on);
 249 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 250                 uint8_t rule_id);
 251 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 252                                           uint16_t queue_id);
 253 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 254                                            uint16_t queue_id);
 255 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 256                                uint8_t queue, uint8_t msix_vector);
 257 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 258
 259 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 260                 uint16_t queue_idx, uint16_t tx_rate);
 261 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 262                 uint16_t tx_rate, uint64_t q_msk);
 263
 264 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 265                                  struct ether_addr *mac_addr,
 266                                  uint32_t index, uint32_t pool);
 267 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 268 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 269                                              struct ether_addr *mac_addr);
 270 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 271                         struct rte_eth_syn_filter *filter,
 272                         bool add);
 273 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 274                         struct rte_eth_syn_filter *filter);
 275 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 276                         enum rte_filter_op filter_op,
 277                         void *arg);
 278 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 279                         struct ixgbe_5tuple_filter *filter);
 280 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 283                         struct rte_eth_ntuple_filter *filter,
 284                         bool add);
 285 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 286                                 enum rte_filter_op filter_op,
 287                                 void *arg);
 288 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 289                         struct rte_eth_ntuple_filter *filter);
 290 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ethertype_filter *filter,
 292                         bool add);
 293 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 294                                 enum rte_filter_op filter_op,
 295                                 void *arg);
 296 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 297                         struct rte_eth_ethertype_filter *filter);
 298 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 299                      enum rte_filter_type filter_type,
 300                      enum rte_filter_op filter_op,
 301                      void *arg);
 302 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 303
 304 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 305                                       struct ether_addr *mc_addr_set,
 306                                       uint32_t nb_mc_addr);
 307
 308 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 309 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 310                             struct rte_dev_reg_info *regs);
 311 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 312 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 313                                 struct rte_dev_eeprom_info *eeprom);
 314 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 315                                 struct rte_dev_eeprom_info *eeprom);
 316
 317 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 318 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 319                                 struct rte_dev_reg_info *regs);
 320
 321 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 322 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 323 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 324                                             struct timespec *timestamp,
 325                                             uint32_t flags);
 326 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 327                                             struct timespec *timestamp);
 328
 329 /*
 330  * Define VF Stats MACRO for Non "cleared on read" register
 331  */
 332 #define UPDATE_VF_STAT(reg, last, cur)                          \
 333 {                                                               \
 334         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 335         cur += (latest - last) & UINT_MAX;                      \
 336         last = latest;                                          \
 337 }
 338
 339 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 340 {                                                                \
 341         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 342         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 343         u64 latest = ((new_msb << 32) | new_lsb);                \
 344         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 345         last = latest;                                           \
 346 }
 347
 348 #define IXGBE_SET_HWSTRIP(h, q) do{\
 349                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 350                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 351                 (h)->bitmap[idx] |= 1 << bit;\
 352         }while(0)
 353
 354 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 355                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 356                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 357                 (h)->bitmap[idx] &= ~(1 << bit);\
 358         }while(0)
 359
 360 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (r) = (h)->bitmap[idx] >> bit & 1;\
 364         }while(0)
 365
 366 /*
 367  * The set of PCI devices this driver supports
 368  */
 369 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 370
 371 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 372 #include "rte_pci_dev_ids.h"
 373
 374 { .vendor_id = 0, /* sentinel */ },
 375 };
 376
 377
 378 /*
 379  * The set of PCI devices this driver supports (for 82599 VF)
 380  */
 381 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385 { .vendor_id = 0, /* sentinel */ },
 386
 387 };
 388
 389 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 390         .dev_configure        = ixgbe_dev_configure,
 391         .dev_start            = ixgbe_dev_start,
 392         .dev_stop             = ixgbe_dev_stop,
 393         .dev_set_link_up    = ixgbe_dev_set_link_up,
 394         .dev_set_link_down  = ixgbe_dev_set_link_down,
 395         .dev_close            = ixgbe_dev_close,
 396         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 397         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 398         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 399         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 400         .link_update          = ixgbe_dev_link_update,
 401         .stats_get            = ixgbe_dev_stats_get,
 402         .xstats_get           = ixgbe_dev_xstats_get,
 403         .stats_reset          = ixgbe_dev_stats_reset,
 404         .xstats_reset         = ixgbe_dev_xstats_reset,
 405         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 406         .dev_infos_get        = ixgbe_dev_info_get,
 407         .mtu_set              = ixgbe_dev_mtu_set,
 408         .vlan_filter_set      = ixgbe_vlan_filter_set,
 409         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 410         .vlan_offload_set     = ixgbe_vlan_offload_set,
 411         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 412         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 413         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 414         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 415         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 416         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 417         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 418         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 419         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 420         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 421         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 422         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 423         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 424         .dev_led_on           = ixgbe_dev_led_on,
 425         .dev_led_off          = ixgbe_dev_led_off,
 426         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 427         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 428         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 429         .mac_addr_add         = ixgbe_add_rar,
 430         .mac_addr_remove      = ixgbe_remove_rar,
 431         .mac_addr_set         = ixgbe_set_default_mac_addr,
 432         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 433         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 434         .mirror_rule_set      = ixgbe_mirror_rule_set,
 435         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 436         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 437         .set_vf_rx            = ixgbe_set_pool_rx,
 438         .set_vf_tx            = ixgbe_set_pool_tx,
 439         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 440         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 441         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 442         .reta_update          = ixgbe_dev_rss_reta_update,
 443         .reta_query           = ixgbe_dev_rss_reta_query,
 444 #ifdef RTE_NIC_BYPASS
 445         .bypass_init          = ixgbe_bypass_init,
 446         .bypass_state_set     = ixgbe_bypass_state_store,
 447         .bypass_state_show    = ixgbe_bypass_state_show,
 448         .bypass_event_set     = ixgbe_bypass_event_store,
 449         .bypass_event_show    = ixgbe_bypass_event_show,
 450         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 451         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 452         .bypass_ver_show      = ixgbe_bypass_ver_show,
 453         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 454 #endif /* RTE_NIC_BYPASS */
 455         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 456         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 457         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 458         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 459         .timesync_enable      = ixgbe_timesync_enable,
 460         .timesync_disable     = ixgbe_timesync_disable,
 461         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 462         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 463         .get_reg_length       = ixgbe_get_reg_length,
 464         .get_reg              = ixgbe_get_regs,
 465         .get_eeprom_length    = ixgbe_get_eeprom_length,
 466         .get_eeprom           = ixgbe_get_eeprom,
 467         .set_eeprom           = ixgbe_set_eeprom,
 468 };
 469
 470 /*
 471  * dev_ops for virtual function, bare necessities for basic vf
 472  * operation have been implemented
 473  */
 474 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 475         .dev_configure        = ixgbevf_dev_configure,
 476         .dev_start            = ixgbevf_dev_start,
 477         .dev_stop             = ixgbevf_dev_stop,
 478         .link_update          = ixgbe_dev_link_update,
 479         .stats_get            = ixgbevf_dev_stats_get,
 480         .stats_reset          = ixgbevf_dev_stats_reset,
 481         .dev_close            = ixgbevf_dev_close,
 482         .dev_infos_get        = ixgbevf_dev_info_get,
 483         .mtu_set              = ixgbevf_dev_set_mtu,
 484         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 485         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 486         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 487         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 488         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 489         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 490         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 491         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 492         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 493         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 494         .mac_addr_add         = ixgbevf_add_mac_addr,
 495         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 496         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 497         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 498         .get_reg_length       = ixgbevf_get_reg_length,
 499         .get_reg              = ixgbevf_get_regs,
 500         .reta_update          = ixgbe_dev_rss_reta_update,
 501         .reta_query           = ixgbe_dev_rss_reta_query,
 502         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 503         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 504 };
 505
 506 /* store statistics names and its offset in stats structure */
 507 struct rte_ixgbe_xstats_name_off {
 508         char name[RTE_ETH_XSTATS_NAME_SIZE];
 509         unsigned offset;
 510 };
 511
 512 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 513         {"rx_illegal_byte_err", offsetof(struct ixgbe_hw_stats, errbc)},
 514         {"rx_len_err", offsetof(struct ixgbe_hw_stats, rlec)},
 515         {"rx_undersize_count", offsetof(struct ixgbe_hw_stats, ruc)},
 516         {"rx_oversize_count", offsetof(struct ixgbe_hw_stats, roc)},
 517         {"rx_fragment_count", offsetof(struct ixgbe_hw_stats, rfc)},
 518         {"rx_jabber_count", offsetof(struct ixgbe_hw_stats, rjc)},
 519         {"l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 520         {"mac_local_fault", offsetof(struct ixgbe_hw_stats, mlfc)},
 521         {"mac_remote_fault", offsetof(struct ixgbe_hw_stats, mrfc)},
 522         {"mac_short_pkt_discard", offsetof(struct ixgbe_hw_stats, mspdc)},
 523         {"fccrc_error", offsetof(struct ixgbe_hw_stats, fccrc)},
 524         {"fcoe_drop", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 525         {"fc_last_error", offsetof(struct ixgbe_hw_stats, fclast)},
 526         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 527         {"rx_phy_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 528         {"mgmt_pkts_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 529         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 530         {"fdir_match", offsetof(struct ixgbe_hw_stats, fdirmatch)},
 531         {"fdir_miss", offsetof(struct ixgbe_hw_stats, fdirmiss)},
 532         {"tx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxontxc)},
 533         {"rx_flow_control_xon", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 534         {"tx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 535         {"rx_flow_control_xoff", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 536 };
 537
 538 #define IXGBE_NB_XSTATS (sizeof(rte_ixgbe_stats_strings) /      \
 539                 sizeof(rte_ixgbe_stats_strings[0]))
 540
 541 /**
 542  * Atomically reads the link status information from global
 543  * structure rte_eth_dev.
 544  *
 545  * @param dev
 546  *   - Pointer to the structure rte_eth_dev to read from.
 547  *   - Pointer to the buffer to be saved with the link status.
 548  *
 549  * @return
 550  *   - On success, zero.
 551  *   - On failure, negative value.
 552  */
 553 static inline int
 554 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 555                                 struct rte_eth_link *link)
 556 {
 557         struct rte_eth_link *dst = link;
 558         struct rte_eth_link *src = &(dev->data->dev_link);
 559
 560         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 561                                         *(uint64_t *)src) == 0)
 562                 return -1;
 563
 564         return 0;
 565 }
 566
 567 /**
 568  * Atomically writes the link status information into global
 569  * structure rte_eth_dev.
 570  *
 571  * @param dev
 572  *   - Pointer to the structure rte_eth_dev to read from.
 573  *   - Pointer to the buffer to be saved with the link status.
 574  *
 575  * @return
 576  *   - On success, zero.
 577  *   - On failure, negative value.
 578  */
 579 static inline int
 580 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 581                                 struct rte_eth_link *link)
 582 {
 583         struct rte_eth_link *dst = &(dev->data->dev_link);
 584         struct rte_eth_link *src = link;
 585
 586         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 587                                         *(uint64_t *)src) == 0)
 588                 return -1;
 589
 590         return 0;
 591 }
 592
 593 /*
 594  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 595  */
 596 static inline int
 597 ixgbe_is_sfp(struct ixgbe_hw *hw)
 598 {
 599         switch (hw->phy.type) {
 600         case ixgbe_phy_sfp_avago:
 601         case ixgbe_phy_sfp_ftl:
 602         case ixgbe_phy_sfp_intel:
 603         case ixgbe_phy_sfp_unknown:
 604         case ixgbe_phy_sfp_passive_tyco:
 605         case ixgbe_phy_sfp_passive_unknown:
 606                 return 1;
 607         default:
 608                 return 0;
 609         }
 610 }
 611
 612 static inline int32_t
 613 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 614 {
 615         uint32_t ctrl_ext;
 616         int32_t status;
 617
 618         status = ixgbe_reset_hw(hw);
 619
 620         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 621         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 622         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 623         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 624         IXGBE_WRITE_FLUSH(hw);
 625
 626         return status;
 627 }
 628
 629 static inline void
 630 ixgbe_enable_intr(struct rte_eth_dev *dev)
 631 {
 632         struct ixgbe_interrupt *intr =
 633                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 634         struct ixgbe_hw *hw =
 635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 636
 637         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 638         IXGBE_WRITE_FLUSH(hw);
 639 }
 640
 641 /*
 642  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 643  */
 644 static void
 645 ixgbe_disable_intr(struct ixgbe_hw *hw)
 646 {
 647         PMD_INIT_FUNC_TRACE();
 648
 649         if (hw->mac.type == ixgbe_mac_82598EB) {
 650                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 651         } else {
 652                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 653                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 654                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 655         }
 656         IXGBE_WRITE_FLUSH(hw);
 657 }
 658
 659 /*
 660  * This function resets queue statistics mapping registers.
 661  * From Niantic datasheet, Initialization of Statistics section:
 662  * "...if software requires the queue counters, the RQSMR and TQSM registers
 663  * must be re-programmed following a device reset.
 664  */
 665 static void
 666 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 667 {
 668         uint32_t i;
 669
 670         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 671                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 672                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 673         }
 674 }
 675
 676
 677 static int
 678 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 679                                   uint16_t queue_id,
 680                                   uint8_t stat_idx,
 681                                   uint8_t is_rx)
 682 {
 683 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 684 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 685 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 686
 687         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 688         struct ixgbe_stat_mapping_registers *stat_mappings =
 689                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 690         uint32_t qsmr_mask = 0;
 691         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 692         uint32_t q_map;
 693         uint8_t n, offset;
 694
 695         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 696                 (hw->mac.type != ixgbe_mac_X540) &&
 697                 (hw->mac.type != ixgbe_mac_X550) &&
 698                 (hw->mac.type != ixgbe_mac_X550EM_x))
 699                 return -ENOSYS;
 700
 701         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 702                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 703                      queue_id, stat_idx);
 704
 705         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 706         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 707                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 708                 return -EIO;
 709         }
 710         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 711
 712         /* Now clear any previous stat_idx set */
 713         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 714         if (!is_rx)
 715                 stat_mappings->tqsm[n] &= ~clearing_mask;
 716         else
 717                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 718
 719         q_map = (uint32_t)stat_idx;
 720         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 721         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 722         if (!is_rx)
 723                 stat_mappings->tqsm[n] |= qsmr_mask;
 724         else
 725                 stat_mappings->rqsmr[n] |= qsmr_mask;
 726
 727         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 728                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 729                      queue_id, stat_idx);
 730         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 731                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 732
 733         /* Now write the mapping in the appropriate register */
 734         if (is_rx) {
 735                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 736                              stat_mappings->rqsmr[n], n);
 737                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 738         }
 739         else {
 740                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 741                              stat_mappings->tqsm[n], n);
 742                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 743         }
 744         return 0;
 745 }
 746
 747 static void
 748 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 749 {
 750         struct ixgbe_stat_mapping_registers *stat_mappings =
 751                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 752         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753         int i;
 754
 755         /* write whatever was in stat mapping table to the NIC */
 756         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 757                 /* rx */
 758                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 759
 760                 /* tx */
 761                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 762         }
 763 }
 764
 765 static void
 766 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 767 {
 768         uint8_t i;
 769         struct ixgbe_dcb_tc_config *tc;
 770         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 771
 772         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 773         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 774         for (i = 0; i < dcb_max_tc; i++) {
 775                 tc = &dcb_config->tc_config[i];
 776                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 777                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 778                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 779                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 780                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 781                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 782                 tc->pfc = ixgbe_dcb_pfc_disabled;
 783         }
 784
 785         /* Initialize default user to priority mapping, UPx->TC0 */
 786         tc = &dcb_config->tc_config[0];
 787         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 788         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 789         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 790                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 791                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 792         }
 793         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 794         dcb_config->pfc_mode_enable = false;
 795         dcb_config->vt_mode = true;
 796         dcb_config->round_robin_enable = false;
 797         /* support all DCB capabilities in 82599 */
 798         dcb_config->support.capabilities = 0xFF;
 799
 800         /*we only support 4 Tcs for X540, X550 */
 801         if (hw->mac.type == ixgbe_mac_X540 ||
 802                 hw->mac.type == ixgbe_mac_X550 ||
 803                 hw->mac.type == ixgbe_mac_X550EM_x) {
 804                 dcb_config->num_tcs.pg_tcs = 4;
 805                 dcb_config->num_tcs.pfc_tcs = 4;
 806         }
 807 }
 808
 809 /*
 810  * Ensure that all locks are released before first NVM or PHY access
 811  */
 812 static void
 813 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 814 {
 815         uint16_t mask;
 816
 817         /*
 818          * Phy lock should not fail in this early stage. If this is the case,
 819          * it is due to an improper exit of the application.
 820          * So force the release of the faulty lock. Release of common lock
 821          * is done automatically by swfw_sync function.
 822          */
 823         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 824         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 825                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 826         }
 827         ixgbe_release_swfw_semaphore(hw, mask);
 828
 829         /*
 830          * These ones are more tricky since they are common to all ports; but
 831          * swfw_sync retries last long enough (1s) to be almost sure that if
 832          * lock can not be taken it is due to an improper lock of the
 833          * semaphore.
 834          */
 835         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 836         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 837                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 838         }
 839         ixgbe_release_swfw_semaphore(hw, mask);
 840 }
 841
 842 /*
 843  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 844  * It returns 0 on success.
 845  */
 846 static int
 847 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 848 {
 849         struct rte_pci_device *pci_dev;
 850         struct ixgbe_hw *hw =
 851                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 852         struct ixgbe_vfta * shadow_vfta =
 853                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 854         struct ixgbe_hwstrip *hwstrip =
 855                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 856         struct ixgbe_dcb_config *dcb_config =
 857                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 858         struct ixgbe_filter_info *filter_info =
 859                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 860         uint32_t ctrl_ext;
 861         uint16_t csum;
 862         int diag, i;
 863
 864         PMD_INIT_FUNC_TRACE();
 865
 866         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 867         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 868         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 869
 870         /*
 871          * For secondary processes, we don't initialise any further as primary
 872          * has already done this work. Only check we don't need a different
 873          * RX and TX function.
 874          */
 875         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 876                 struct ixgbe_tx_queue *txq;
 877                 /* TX queue function in primary, set by last queue initialized
 878                  * Tx queue may not initialized by primary process */
 879                 if (eth_dev->data->tx_queues) {
 880                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 881                         ixgbe_set_tx_function(eth_dev, txq);
 882                 } else {
 883                         /* Use default TX function if we get here */
 884                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 885                                              "Using default TX function.");
 886                 }
 887
 888                 ixgbe_set_rx_function(eth_dev);
 889
 890                 return 0;
 891         }
 892         pci_dev = eth_dev->pci_dev;
 893
 894         /* Vendor and Device ID need to be set before init of shared code */
 895         hw->device_id = pci_dev->id.device_id;
 896         hw->vendor_id = pci_dev->id.vendor_id;
 897         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 898         hw->allow_unsupported_sfp = 1;
 899
 900         /* Initialize the shared code (base driver) */
 901 #ifdef RTE_NIC_BYPASS
 902         diag = ixgbe_bypass_init_shared_code(hw);
 903 #else
 904         diag = ixgbe_init_shared_code(hw);
 905 #endif /* RTE_NIC_BYPASS */
 906
 907         if (diag != IXGBE_SUCCESS) {
 908                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 909                 return -EIO;
 910         }
 911
 912         /* pick up the PCI bus settings for reporting later */
 913         ixgbe_get_bus_info(hw);
 914
 915         /* Unlock any pending hardware semaphore */
 916         ixgbe_swfw_lock_reset(hw);
 917
 918         /* Initialize DCB configuration*/
 919         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 920         ixgbe_dcb_init(hw,dcb_config);
 921         /* Get Hardware Flow Control setting */
 922         hw->fc.requested_mode = ixgbe_fc_full;
 923         hw->fc.current_mode = ixgbe_fc_full;
 924         hw->fc.pause_time = IXGBE_FC_PAUSE;
 925         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 926                 hw->fc.low_water[i] = IXGBE_FC_LO;
 927                 hw->fc.high_water[i] = IXGBE_FC_HI;
 928         }
 929         hw->fc.send_xon = 1;
 930
 931         /* Make sure we have a good EEPROM before we read from it */
 932         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 933         if (diag != IXGBE_SUCCESS) {
 934                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 935                 return -EIO;
 936         }
 937
 938 #ifdef RTE_NIC_BYPASS
 939         diag = ixgbe_bypass_init_hw(hw);
 940 #else
 941         diag = ixgbe_init_hw(hw);
 942 #endif /* RTE_NIC_BYPASS */
 943
 944         /*
 945          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 946          * is called too soon after the kernel driver unbinding/binding occurs.
 947          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 948          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 949          * also called. See ixgbe_identify_phy_82599(). The reason for the
 950          * failure is not known, and only occuts when virtualisation features
 951          * are disabled in the bios. A delay of 100ms  was found to be enough by
 952          * trial-and-error, and is doubled to be safe.
 953          */
 954         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 955                 rte_delay_ms(200);
 956                 diag = ixgbe_init_hw(hw);
 957         }
 958
 959         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 960                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 961                     "LOM.  Please be aware there may be issues associated "
 962                     "with your hardware.");
 963                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 964                     "please contact your Intel or hardware representative "
 965                     "who provided you with this hardware.");
 966         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 967                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 968         if (diag) {
 969                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 970                 return -EIO;
 971         }
 972
 973         /* Reset the hw statistics */
 974         ixgbe_dev_stats_reset(eth_dev);
 975
 976         /* disable interrupt */
 977         ixgbe_disable_intr(hw);
 978
 979         /* reset mappings for queue statistics hw counters*/
 980         ixgbe_reset_qstat_mappings(hw);
 981
 982         /* Allocate memory for storing MAC addresses */
 983         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 984                         hw->mac.num_rar_entries, 0);
 985         if (eth_dev->data->mac_addrs == NULL) {
 986                 PMD_INIT_LOG(ERR,
 987                         "Failed to allocate %u bytes needed to store "
 988                         "MAC addresses",
 989                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 990                 return -ENOMEM;
 991         }
 992         /* Copy the permanent MAC address */
 993         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 994                         &eth_dev->data->mac_addrs[0]);
 995
 996         /* Allocate memory for storing hash filter MAC addresses */
 997         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 998                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 999         if (eth_dev->data->hash_mac_addrs == NULL) {
1000                 PMD_INIT_LOG(ERR,
1001                         "Failed to allocate %d bytes needed to store MAC addresses",
1002                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1003                 return -ENOMEM;
1004         }
1005
1006         /* initialize the vfta */
1007         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1008
1009         /* initialize the hw strip bitmap*/
1010         memset(hwstrip, 0, sizeof(*hwstrip));
1011
1012         /* initialize PF if max_vfs not zero */
1013         ixgbe_pf_host_init(eth_dev);
1014
1015         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1016         /* let hardware know driver is loaded */
1017         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1018         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1019         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1020         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1021         IXGBE_WRITE_FLUSH(hw);
1022
1023         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1024                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1025                              (int) hw->mac.type, (int) hw->phy.type,
1026                              (int) hw->phy.sfp_type);
1027         else
1028                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1029                              (int) hw->mac.type, (int) hw->phy.type);
1030
1031         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1032                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1033                         pci_dev->id.device_id);
1034
1035         /* enable support intr */
1036         ixgbe_enable_intr(eth_dev);
1037
1038         /* initialize 5tuple filter list */
1039         TAILQ_INIT(&filter_info->fivetuple_list);
1040         memset(filter_info->fivetuple_mask, 0,
1041                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1042
1043         return 0;
1044 }
1045
1046 static int
1047 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1048 {
1049         struct rte_pci_device *pci_dev;
1050         struct ixgbe_hw *hw;
1051
1052         PMD_INIT_FUNC_TRACE();
1053
1054         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1055                 return -EPERM;
1056
1057         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1058         pci_dev = eth_dev->pci_dev;
1059
1060         if (hw->adapter_stopped == 0)
1061                 ixgbe_dev_close(eth_dev);
1062
1063         eth_dev->dev_ops = NULL;
1064         eth_dev->rx_pkt_burst = NULL;
1065         eth_dev->tx_pkt_burst = NULL;
1066
1067         /* Unlock any pending hardware semaphore */
1068         ixgbe_swfw_lock_reset(hw);
1069
1070         /* disable uio intr before callback unregister */
1071         rte_intr_disable(&(pci_dev->intr_handle));
1072         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1073                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1074
1075         /* uninitialize PF if max_vfs not zero */
1076         ixgbe_pf_host_uninit(eth_dev);
1077
1078         rte_free(eth_dev->data->mac_addrs);
1079         eth_dev->data->mac_addrs = NULL;
1080
1081         rte_free(eth_dev->data->hash_mac_addrs);
1082         eth_dev->data->hash_mac_addrs = NULL;
1083
1084         return 0;
1085 }
1086
1087 /*
1088  * Negotiate mailbox API version with the PF.
1089  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1090  * Then we try to negotiate starting with the most recent one.
1091  * If all negotiation attempts fail, then we will proceed with
1092  * the default one (ixgbe_mbox_api_10).
1093  */
1094 static void
1095 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1096 {
1097         int32_t i;
1098
1099         /* start with highest supported, proceed down */
1100         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1101                 ixgbe_mbox_api_11,
1102                 ixgbe_mbox_api_10,
1103         };
1104
1105         for (i = 0;
1106                         i != RTE_DIM(sup_ver) &&
1107                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1108                         i++)
1109                 ;
1110 }
1111
1112 static void
1113 generate_random_mac_addr(struct ether_addr *mac_addr)
1114 {
1115         uint64_t random;
1116
1117         /* Set Organizationally Unique Identifier (OUI) prefix. */
1118         mac_addr->addr_bytes[0] = 0x00;
1119         mac_addr->addr_bytes[1] = 0x09;
1120         mac_addr->addr_bytes[2] = 0xC0;
1121         /* Force indication of locally assigned MAC address. */
1122         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1123         /* Generate the last 3 bytes of the MAC address with a random number. */
1124         random = rte_rand();
1125         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1126 }
1127
1128 /*
1129  * Virtual Function device init
1130  */
1131 static int
1132 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1133 {
1134         int diag;
1135         uint32_t tc, tcs;
1136         struct rte_pci_device *pci_dev;
1137         struct ixgbe_hw *hw =
1138                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1139         struct ixgbe_vfta * shadow_vfta =
1140                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1141         struct ixgbe_hwstrip *hwstrip =
1142                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1143         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1144
1145         PMD_INIT_FUNC_TRACE();
1146
1147         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1148         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1149         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1150
1151         /* for secondary processes, we don't initialise any further as primary
1152          * has already done this work. Only check we don't need a different
1153          * RX function */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1155                 if (eth_dev->data->scattered_rx)
1156                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1157                 return 0;
1158         }
1159
1160         pci_dev = eth_dev->pci_dev;
1161
1162         hw->device_id = pci_dev->id.device_id;
1163         hw->vendor_id = pci_dev->id.vendor_id;
1164         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1165
1166         /* initialize the vfta */
1167         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1168
1169         /* initialize the hw strip bitmap*/
1170         memset(hwstrip, 0, sizeof(*hwstrip));
1171
1172         /* Initialize the shared code (base driver) */
1173         diag = ixgbe_init_shared_code(hw);
1174         if (diag != IXGBE_SUCCESS) {
1175                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1176                 return -EIO;
1177         }
1178
1179         /* init_mailbox_params */
1180         hw->mbx.ops.init_params(hw);
1181
1182         /* Reset the hw statistics */
1183         ixgbevf_dev_stats_reset(eth_dev);
1184
1185         /* Disable the interrupts for VF */
1186         ixgbevf_intr_disable(hw);
1187
1188         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1189         diag = hw->mac.ops.reset_hw(hw);
1190
1191         /*
1192          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1193          * the underlying PF driver has not assigned a MAC address to the VF.
1194          * In this case, assign a random MAC address.
1195          */
1196         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1197                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1198                 return (diag);
1199         }
1200
1201         /* negotiate mailbox API version to use with the PF. */
1202         ixgbevf_negotiate_api(hw);
1203
1204         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1205         ixgbevf_get_queues(hw, &tcs, &tc);
1206
1207         /* Allocate memory for storing MAC addresses */
1208         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1209                         hw->mac.num_rar_entries, 0);
1210         if (eth_dev->data->mac_addrs == NULL) {
1211                 PMD_INIT_LOG(ERR,
1212                         "Failed to allocate %u bytes needed to store "
1213                         "MAC addresses",
1214                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1215                 return -ENOMEM;
1216         }
1217
1218         /* Generate a random MAC address, if none was assigned by PF. */
1219         if (is_zero_ether_addr(perm_addr)) {
1220                 generate_random_mac_addr(perm_addr);
1221                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1222                 if (diag) {
1223                         rte_free(eth_dev->data->mac_addrs);
1224                         eth_dev->data->mac_addrs = NULL;
1225                         return diag;
1226                 }
1227                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1228                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1229                              "%02x:%02x:%02x:%02x:%02x:%02x",
1230                              perm_addr->addr_bytes[0],
1231                              perm_addr->addr_bytes[1],
1232                              perm_addr->addr_bytes[2],
1233                              perm_addr->addr_bytes[3],
1234                              perm_addr->addr_bytes[4],
1235                              perm_addr->addr_bytes[5]);
1236         }
1237
1238         /* Copy the permanent MAC address */
1239         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1240
1241         /* reset the hardware with the new settings */
1242         diag = hw->mac.ops.start_hw(hw);
1243         switch (diag) {
1244                 case  0:
1245                         break;
1246
1247                 default:
1248                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1249                         return (-EIO);
1250         }
1251
1252         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1253                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1254                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1255
1256         return 0;
1257 }
1258
1259 /* Virtual Function device uninit */
1260
1261 static int
1262 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1263 {
1264         struct ixgbe_hw *hw;
1265         unsigned i;
1266
1267         PMD_INIT_FUNC_TRACE();
1268
1269         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1270                 return -EPERM;
1271
1272         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1273
1274         if (hw->adapter_stopped == 0)
1275                 ixgbevf_dev_close(eth_dev);
1276
1277         eth_dev->dev_ops = NULL;
1278         eth_dev->rx_pkt_burst = NULL;
1279         eth_dev->tx_pkt_burst = NULL;
1280
1281         /* Disable the interrupts for VF */
1282         ixgbevf_intr_disable(hw);
1283
1284         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1285                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1286                 eth_dev->data->rx_queues[i] = NULL;
1287         }
1288         eth_dev->data->nb_rx_queues = 0;
1289
1290         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1291                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1292                 eth_dev->data->tx_queues[i] = NULL;
1293         }
1294         eth_dev->data->nb_tx_queues = 0;
1295
1296         rte_free(eth_dev->data->mac_addrs);
1297         eth_dev->data->mac_addrs = NULL;
1298
1299         return 0;
1300 }
1301
1302 static struct eth_driver rte_ixgbe_pmd = {
1303         .pci_drv = {
1304                 .name = "rte_ixgbe_pmd",
1305                 .id_table = pci_id_ixgbe_map,
1306                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1307                         RTE_PCI_DRV_DETACHABLE,
1308         },
1309         .eth_dev_init = eth_ixgbe_dev_init,
1310         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1311         .dev_private_size = sizeof(struct ixgbe_adapter),
1312 };
1313
1314 /*
1315  * virtual function driver struct
1316  */
1317 static struct eth_driver rte_ixgbevf_pmd = {
1318         .pci_drv = {
1319                 .name = "rte_ixgbevf_pmd",
1320                 .id_table = pci_id_ixgbevf_map,
1321                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1322         },
1323         .eth_dev_init = eth_ixgbevf_dev_init,
1324         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1325         .dev_private_size = sizeof(struct ixgbe_adapter),
1326 };
1327
1328 /*
1329  * Driver initialization routine.
1330  * Invoked once at EAL init time.
1331  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1332  */
1333 static int
1334 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1335 {
1336         PMD_INIT_FUNC_TRACE();
1337
1338         rte_eth_driver_register(&rte_ixgbe_pmd);
1339         return 0;
1340 }
1341
1342 /*
1343  * VF Driver initialization routine.
1344  * Invoked one at EAL init time.
1345  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1346  */
1347 static int
1348 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1349 {
1350         PMD_INIT_FUNC_TRACE();
1351
1352         rte_eth_driver_register(&rte_ixgbevf_pmd);
1353         return (0);
1354 }
1355
1356 static int
1357 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1358 {
1359         struct ixgbe_hw *hw =
1360                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1361         struct ixgbe_vfta * shadow_vfta =
1362                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1363         uint32_t vfta;
1364         uint32_t vid_idx;
1365         uint32_t vid_bit;
1366
1367         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1368         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1369         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1370         if (on)
1371                 vfta |= vid_bit;
1372         else
1373                 vfta &= ~vid_bit;
1374         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1375
1376         /* update local VFTA copy */
1377         shadow_vfta->vfta[vid_idx] = vfta;
1378
1379         return 0;
1380 }
1381
1382 static void
1383 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1384 {
1385         if (on)
1386                 ixgbe_vlan_hw_strip_enable(dev, queue);
1387         else
1388                 ixgbe_vlan_hw_strip_disable(dev, queue);
1389 }
1390
1391 static void
1392 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1393 {
1394         struct ixgbe_hw *hw =
1395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1396
1397         /* Only the high 16-bits is valid */
1398         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1399 }
1400
1401 void
1402 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1403 {
1404         struct ixgbe_hw *hw =
1405                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1406         uint32_t vlnctrl;
1407
1408         PMD_INIT_FUNC_TRACE();
1409
1410         /* Filter Table Disable */
1411         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1412         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1413
1414         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1415 }
1416
1417 void
1418 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1419 {
1420         struct ixgbe_hw *hw =
1421                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1422         struct ixgbe_vfta * shadow_vfta =
1423                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1424         uint32_t vlnctrl;
1425         uint16_t i;
1426
1427         PMD_INIT_FUNC_TRACE();
1428
1429         /* Filter Table Enable */
1430         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1431         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1432         vlnctrl |= IXGBE_VLNCTRL_VFE;
1433
1434         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1435
1436         /* write whatever is in local vfta copy */
1437         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1438                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1439 }
1440
1441 static void
1442 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1443 {
1444         struct ixgbe_hwstrip *hwstrip =
1445                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1446
1447         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1448                 return;
1449
1450         if (on)
1451                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1452         else
1453                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1454 }
1455
1456 static void
1457 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1458 {
1459         struct ixgbe_hw *hw =
1460                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1461         uint32_t ctrl;
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         if (hw->mac.type == ixgbe_mac_82598EB) {
1466                 /* No queue level support */
1467                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1468                 return;
1469         }
1470         else {
1471                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1472                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1473                 ctrl &= ~IXGBE_RXDCTL_VME;
1474                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1475         }
1476         /* record those setting for HW strip per queue */
1477         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1478 }
1479
1480 static void
1481 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1482 {
1483         struct ixgbe_hw *hw =
1484                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1485         uint32_t ctrl;
1486
1487         PMD_INIT_FUNC_TRACE();
1488
1489         if (hw->mac.type == ixgbe_mac_82598EB) {
1490                 /* No queue level supported */
1491                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1492                 return;
1493         }
1494         else {
1495                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1496                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1497                 ctrl |= IXGBE_RXDCTL_VME;
1498                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1499         }
1500         /* record those setting for HW strip per queue */
1501         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1502 }
1503
1504 void
1505 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1506 {
1507         struct ixgbe_hw *hw =
1508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         uint32_t ctrl;
1510         uint16_t i;
1511
1512         PMD_INIT_FUNC_TRACE();
1513
1514         if (hw->mac.type == ixgbe_mac_82598EB) {
1515                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1516                 ctrl &= ~IXGBE_VLNCTRL_VME;
1517                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1518         }
1519         else {
1520                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1521                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1522                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1523                         ctrl &= ~IXGBE_RXDCTL_VME;
1524                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1525
1526                         /* record those setting for HW strip per queue */
1527                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1528                 }
1529         }
1530 }
1531
1532 void
1533 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1534 {
1535         struct ixgbe_hw *hw =
1536                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1537         uint32_t ctrl;
1538         uint16_t i;
1539
1540         PMD_INIT_FUNC_TRACE();
1541
1542         if (hw->mac.type == ixgbe_mac_82598EB) {
1543                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1544                 ctrl |= IXGBE_VLNCTRL_VME;
1545                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1546         }
1547         else {
1548                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1549                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1550                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1551                         ctrl |= IXGBE_RXDCTL_VME;
1552                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1553
1554                         /* record those setting for HW strip per queue */
1555                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1556                 }
1557         }
1558 }
1559
1560 static void
1561 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1562 {
1563         struct ixgbe_hw *hw =
1564                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565         uint32_t ctrl;
1566
1567         PMD_INIT_FUNC_TRACE();
1568
1569         /* DMATXCTRL: Geric Double VLAN Disable */
1570         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1571         ctrl &= ~IXGBE_DMATXCTL_GDV;
1572         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1573
1574         /* CTRL_EXT: Global Double VLAN Disable */
1575         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1576         ctrl &= ~IXGBE_EXTENDED_VLAN;
1577         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1578
1579 }
1580
1581 static void
1582 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1583 {
1584         struct ixgbe_hw *hw =
1585                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1586         uint32_t ctrl;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         /* DMATXCTRL: Geric Double VLAN Enable */
1591         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1592         ctrl |= IXGBE_DMATXCTL_GDV;
1593         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1594
1595         /* CTRL_EXT: Global Double VLAN Enable */
1596         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1597         ctrl |= IXGBE_EXTENDED_VLAN;
1598         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1599
1600         /*
1601          * VET EXT field in the EXVET register = 0x8100 by default
1602          * So no need to change. Same to VT field of DMATXCTL register
1603          */
1604 }
1605
1606 static void
1607 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1608 {
1609         if(mask & ETH_VLAN_STRIP_MASK){
1610                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1611                         ixgbe_vlan_hw_strip_enable_all(dev);
1612                 else
1613                         ixgbe_vlan_hw_strip_disable_all(dev);
1614         }
1615
1616         if(mask & ETH_VLAN_FILTER_MASK){
1617                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1618                         ixgbe_vlan_hw_filter_enable(dev);
1619                 else
1620                         ixgbe_vlan_hw_filter_disable(dev);
1621         }
1622
1623         if(mask & ETH_VLAN_EXTEND_MASK){
1624                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1625                         ixgbe_vlan_hw_extend_enable(dev);
1626                 else
1627                         ixgbe_vlan_hw_extend_disable(dev);
1628         }
1629 }
1630
1631 static void
1632 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1633 {
1634         struct ixgbe_hw *hw =
1635                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1637         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1638         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1639         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1640 }
1641
1642 static int
1643 ixgbe_dev_configure(struct rte_eth_dev *dev)
1644 {
1645         struct ixgbe_interrupt *intr =
1646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1647         struct ixgbe_adapter *adapter =
1648                 (struct ixgbe_adapter *)dev->data->dev_private;
1649
1650         PMD_INIT_FUNC_TRACE();
1651
1652         /* set flag to update link status after init */
1653         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1654
1655         /*
1656          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1657          * allocation or vector Rx preconditions we will reset it.
1658          */
1659         adapter->rx_bulk_alloc_allowed = true;
1660         adapter->rx_vec_allowed = true;
1661
1662         return 0;
1663 }
1664
1665 /*
1666  * Configure device link speed and setup link.
1667  * It returns 0 on success.
1668  */
1669 static int
1670 ixgbe_dev_start(struct rte_eth_dev *dev)
1671 {
1672         struct ixgbe_hw *hw =
1673                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674         struct ixgbe_vf_info *vfinfo =
1675                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1676         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1677         uint32_t intr_vector = 0;
1678         int err, link_up = 0, negotiate = 0;
1679         uint32_t speed = 0;
1680         int mask = 0;
1681         int status;
1682         uint16_t vf, idx;
1683
1684         PMD_INIT_FUNC_TRACE();
1685
1686         /* IXGBE devices don't support half duplex */
1687         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1688                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1689                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1690                              dev->data->dev_conf.link_duplex,
1691                              dev->data->port_id);
1692                 return -EINVAL;
1693         }
1694
1695         /* stop adapter */
1696         hw->adapter_stopped = 0;
1697         ixgbe_stop_adapter(hw);
1698
1699         /* reinitialize adapter
1700          * this calls reset and start */
1701         status = ixgbe_pf_reset_hw(hw);
1702         if (status != 0)
1703                 return -1;
1704         hw->mac.ops.start_hw(hw);
1705         hw->mac.get_link_status = true;
1706
1707         /* configure PF module if SRIOV enabled */
1708         ixgbe_pf_host_configure(dev);
1709
1710         /* check and configure queue intr-vector mapping */
1711         if (dev->data->dev_conf.intr_conf.rxq != 0)
1712                 intr_vector = dev->data->nb_rx_queues;
1713
1714         if (rte_intr_efd_enable(intr_handle, intr_vector))
1715                 return -1;
1716
1717         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1718                 intr_handle->intr_vec =
1719                         rte_zmalloc("intr_vec",
1720                                     dev->data->nb_rx_queues * sizeof(int),
1721                                     0);
1722                 if (intr_handle->intr_vec == NULL) {
1723                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1724                                      " intr_vec\n", dev->data->nb_rx_queues);
1725                         return -ENOMEM;
1726                 }
1727         }
1728
1729         /* confiugre msix for sleep until rx interrupt */
1730         ixgbe_configure_msix(dev);
1731
1732         /* initialize transmission unit */
1733         ixgbe_dev_tx_init(dev);
1734
1735         /* This can fail when allocating mbufs for descriptor rings */
1736         err = ixgbe_dev_rx_init(dev);
1737         if (err) {
1738                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1739                 goto error;
1740         }
1741
1742         err = ixgbe_dev_rxtx_start(dev);
1743         if (err < 0) {
1744                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1745                 goto error;
1746         }
1747
1748         /* Skip link setup if loopback mode is enabled for 82599. */
1749         if (hw->mac.type == ixgbe_mac_82599EB &&
1750                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1751                 goto skip_link_setup;
1752
1753         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1754                 err = hw->mac.ops.setup_sfp(hw);
1755                 if (err)
1756                         goto error;
1757         }
1758
1759         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1760                 /* Turn on the copper */
1761                 ixgbe_set_phy_power(hw, true);
1762         } else {
1763                 /* Turn on the laser */
1764                 ixgbe_enable_tx_laser(hw);
1765         }
1766
1767         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1768         if (err)
1769                 goto error;
1770         dev->data->dev_link.link_status = link_up;
1771
1772         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1773         if (err)
1774                 goto error;
1775
1776         switch(dev->data->dev_conf.link_speed) {
1777         case ETH_LINK_SPEED_AUTONEG:
1778                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1779                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1780                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1781                 break;
1782         case ETH_LINK_SPEED_100:
1783                 /*
1784                  * Invalid for 82598 but error will be detected by
1785                  * ixgbe_setup_link()
1786                  */
1787                 speed = IXGBE_LINK_SPEED_100_FULL;
1788                 break;
1789         case ETH_LINK_SPEED_1000:
1790                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1791                 break;
1792         case ETH_LINK_SPEED_10000:
1793                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1794                 break;
1795         default:
1796                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1797                              dev->data->dev_conf.link_speed,
1798                              dev->data->port_id);
1799                 goto error;
1800         }
1801
1802         err = ixgbe_setup_link(hw, speed, link_up);
1803         if (err)
1804                 goto error;
1805
1806 skip_link_setup:
1807
1808         /* check if lsc interrupt is enabled */
1809         if (dev->data->dev_conf.intr_conf.lsc != 0) {
1810                 if (rte_intr_allow_others(intr_handle)) {
1811                         rte_intr_callback_register(intr_handle,
1812                                                    ixgbe_dev_interrupt_handler,
1813                                                    (void *)dev);
1814                         ixgbe_dev_lsc_interrupt_setup(dev);
1815                 } else
1816                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1817                                      " no intr multiplex\n");
1818         }
1819
1820         /* check if rxq interrupt is enabled */
1821         if (dev->data->dev_conf.intr_conf.rxq != 0)
1822                 ixgbe_dev_rxq_interrupt_setup(dev);
1823
1824         /* enable uio/vfio intr/eventfd mapping */
1825         rte_intr_enable(intr_handle);
1826
1827         /* resume enabled intr since hw reset */
1828         ixgbe_enable_intr(dev);
1829
1830         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1831                 ETH_VLAN_EXTEND_MASK;
1832         ixgbe_vlan_offload_set(dev, mask);
1833
1834         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1835                 /* Enable vlan filtering for VMDq */
1836                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1837         }
1838
1839         /* Configure DCB hw */
1840         ixgbe_configure_dcb(dev);
1841
1842         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1843                 err = ixgbe_fdir_configure(dev);
1844                 if (err)
1845                         goto error;
1846         }
1847
1848         /* Restore vf rate limit */
1849         if (vfinfo != NULL) {
1850                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1851                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1852                                 if (vfinfo[vf].tx_rate[idx] != 0)
1853                                         ixgbe_set_vf_rate_limit(dev, vf,
1854                                                 vfinfo[vf].tx_rate[idx],
1855                                                 1 << idx);
1856         }
1857
1858         ixgbe_restore_statistics_mapping(dev);
1859
1860         return (0);
1861
1862 error:
1863         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1864         ixgbe_dev_clear_queues(dev);
1865         return -EIO;
1866 }
1867
1868 /*
1869  * Stop device: disable rx and tx functions to allow for reconfiguring.
1870  */
1871 static void
1872 ixgbe_dev_stop(struct rte_eth_dev *dev)
1873 {
1874         struct rte_eth_link link;
1875         struct ixgbe_hw *hw =
1876                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1877         struct ixgbe_vf_info *vfinfo =
1878                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1879         struct ixgbe_filter_info *filter_info =
1880                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1881         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1882         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1883         int vf;
1884
1885         PMD_INIT_FUNC_TRACE();
1886
1887         /* disable interrupts */
1888         ixgbe_disable_intr(hw);
1889
1890         /* disable intr eventfd mapping */
1891         rte_intr_disable(intr_handle);
1892
1893         /* reset the NIC */
1894         ixgbe_pf_reset_hw(hw);
1895         hw->adapter_stopped = 0;
1896
1897         /* stop adapter */
1898         ixgbe_stop_adapter(hw);
1899
1900         for (vf = 0; vfinfo != NULL &&
1901                      vf < dev->pci_dev->max_vfs; vf++)
1902                 vfinfo[vf].clear_to_send = false;
1903
1904         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1905                 /* Turn off the copper */
1906                 ixgbe_set_phy_power(hw, false);
1907         } else {
1908                 /* Turn off the laser */
1909                 ixgbe_disable_tx_laser(hw);
1910         }
1911
1912         ixgbe_dev_clear_queues(dev);
1913
1914         /* Clear stored conf */
1915         dev->data->scattered_rx = 0;
1916         dev->data->lro = 0;
1917
1918         /* Clear recorded link status */
1919         memset(&link, 0, sizeof(link));
1920         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1921
1922         /* Remove all ntuple filters of the device */
1923         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1924              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1925                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1926                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1927                              p_5tuple, entries);
1928                 rte_free(p_5tuple);
1929         }
1930         memset(filter_info->fivetuple_mask, 0,
1931                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1932
1933         /* Clean datapath event and queue/vec mapping */
1934         rte_intr_efd_disable(intr_handle);
1935         if (intr_handle->intr_vec != NULL) {
1936                 rte_free(intr_handle->intr_vec);
1937                 intr_handle->intr_vec = NULL;
1938         }
1939 }
1940
1941 /*
1942  * Set device link up: enable tx.
1943  */
1944 static int
1945 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1946 {
1947         struct ixgbe_hw *hw =
1948                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1949         if (hw->mac.type == ixgbe_mac_82599EB) {
1950 #ifdef RTE_NIC_BYPASS
1951                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1952                         /* Not suported in bypass mode */
1953                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1954                                      "by device id 0x%x", hw->device_id);
1955                         return -ENOTSUP;
1956                 }
1957 #endif
1958         }
1959
1960         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1961                 /* Turn on the copper */
1962                 ixgbe_set_phy_power(hw, true);
1963         } else {
1964                 /* Turn on the laser */
1965                 ixgbe_enable_tx_laser(hw);
1966         }
1967
1968         return 0;
1969 }
1970
1971 /*
1972  * Set device link down: disable tx.
1973  */
1974 static int
1975 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1976 {
1977         struct ixgbe_hw *hw =
1978                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979         if (hw->mac.type == ixgbe_mac_82599EB) {
1980 #ifdef RTE_NIC_BYPASS
1981                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1982                         /* Not suported in bypass mode */
1983                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1984                                      "by device id 0x%x", hw->device_id);
1985                         return -ENOTSUP;
1986                 }
1987 #endif
1988         }
1989
1990         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1991                 /* Turn off the copper */
1992                 ixgbe_set_phy_power(hw, false);
1993         } else {
1994                 /* Turn off the laser */
1995                 ixgbe_disable_tx_laser(hw);
1996         }
1997
1998         return 0;
1999 }
2000
2001 /*
2002  * Reest and stop device.
2003  */
2004 static void
2005 ixgbe_dev_close(struct rte_eth_dev *dev)
2006 {
2007         struct ixgbe_hw *hw =
2008                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009
2010         PMD_INIT_FUNC_TRACE();
2011
2012         ixgbe_pf_reset_hw(hw);
2013
2014         ixgbe_dev_stop(dev);
2015         hw->adapter_stopped = 1;
2016
2017         ixgbe_dev_free_queues(dev);
2018
2019         ixgbe_disable_pcie_master(hw);
2020
2021         /* reprogram the RAR[0] in case user changed it. */
2022         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2023 }
2024
2025 static void
2026 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2027                                                    *hw_stats, uint64_t *total_missed_rx,
2028                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2029                                                    uint64_t *total_qprdc)
2030 {
2031         uint32_t bprc, lxon, lxoff, total;
2032         unsigned i;
2033
2034         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2035         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2036         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2037         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2038
2039         for (i = 0; i < 8; i++) {
2040                 uint32_t mp;
2041                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2042                 /* global total per queue */
2043                 hw_stats->mpc[i] += mp;
2044                 /* Running comprehensive total for stats display */
2045                 *total_missed_rx += hw_stats->mpc[i];
2046                 if (hw->mac.type == ixgbe_mac_82598EB) {
2047                         hw_stats->rnbc[i] +=
2048                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2049                         hw_stats->pxonrxc[i] +=
2050                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2051                         hw_stats->pxoffrxc[i] +=
2052                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2053                 } else {
2054                         hw_stats->pxonrxc[i] +=
2055                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2056                         hw_stats->pxoffrxc[i] +=
2057                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2058                         hw_stats->pxon2offc[i] +=
2059                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2060                 }
2061                 hw_stats->pxontxc[i] +=
2062                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2063                 hw_stats->pxofftxc[i] +=
2064                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2065         }
2066         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2067                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2068                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2069                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2070                 hw_stats->qbrc[i] +=
2071                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2072                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2073                 hw_stats->qbtc[i] +=
2074                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2075                 *total_qprdc += hw_stats->qprdc[i] +=
2076                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2077
2078                 *total_qprc += hw_stats->qprc[i];
2079                 *total_qbrc += hw_stats->qbrc[i];
2080         }
2081         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2082         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2083         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2084
2085         /* Note that gprc counts missed packets */
2086         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2087
2088         if (hw->mac.type != ixgbe_mac_82598EB) {
2089                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2090                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2091                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2092                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2093                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2094                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2095                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2096                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2097         } else {
2098                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2099                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2100                 /* 82598 only has a counter in the high register */
2101                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2102                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2103                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2104         }
2105
2106         /*
2107          * Workaround: mprc hardware is incorrectly counting
2108          * broadcasts, so for now we subtract those.
2109          */
2110         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2111         hw_stats->bprc += bprc;
2112         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2113         if (hw->mac.type == ixgbe_mac_82598EB)
2114                 hw_stats->mprc -= bprc;
2115
2116         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2117         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2118         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2119         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2120         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2121         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2122
2123         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2124         hw_stats->lxontxc += lxon;
2125         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2126         hw_stats->lxofftxc += lxoff;
2127         total = lxon + lxoff;
2128
2129         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2130         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2131         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2132         hw_stats->gptc -= total;
2133         hw_stats->mptc -= total;
2134         hw_stats->ptc64 -= total;
2135         hw_stats->gotc -= total * ETHER_MIN_LEN;
2136
2137         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2138         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2139         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2140         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2141         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2142         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2143         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2144         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2145         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2146         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2147         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2148         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2149         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2150         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2151         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2152         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2153         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2154         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2155         /* Only read FCOE on 82599 */
2156         if (hw->mac.type != ixgbe_mac_82598EB) {
2157                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2158                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2159                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2160                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2161                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2162         }
2163
2164         /* Flow Director Stats registers */
2165         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2166         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2167 }
2168
2169 /*
2170  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2171  */
2172 static void
2173 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2174 {
2175         struct ixgbe_hw *hw =
2176                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         struct ixgbe_hw_stats *hw_stats =
2178                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2179         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2180         unsigned i;
2181
2182         total_missed_rx = 0;
2183         total_qbrc = 0;
2184         total_qprc = 0;
2185         total_qprdc = 0;
2186
2187         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2188                         &total_qprc, &total_qprdc);
2189
2190         if (stats == NULL)
2191                 return;
2192
2193         /* Fill out the rte_eth_stats statistics structure */
2194         stats->ipackets = total_qprc;
2195         stats->ibytes = total_qbrc;
2196         stats->opackets = hw_stats->gptc;
2197         stats->obytes = hw_stats->gotc;
2198
2199         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2200                 stats->q_ipackets[i] = hw_stats->qprc[i];
2201                 stats->q_opackets[i] = hw_stats->qptc[i];
2202                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2203                 stats->q_obytes[i] = hw_stats->qbtc[i];
2204                 stats->q_errors[i] = hw_stats->qprdc[i];
2205         }
2206
2207         /* Rx Errors */
2208         stats->ierrors  = hw_stats->crcerrs +
2209                           hw_stats->mspdc +
2210                           hw_stats->rlec +
2211                           hw_stats->ruc +
2212                           hw_stats->roc +
2213                           total_missed_rx +
2214                           hw_stats->illerrc +
2215                           hw_stats->errbc +
2216                           hw_stats->xec +
2217                           hw_stats->mlfc +
2218                           hw_stats->mrfc +
2219                           hw_stats->rfc +
2220                           hw_stats->fccrc +
2221                           hw_stats->fclast;
2222
2223         /* Tx Errors */
2224         stats->oerrors  = 0;
2225 }
2226
2227 static void
2228 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2229 {
2230         struct ixgbe_hw_stats *stats =
2231                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2232
2233         /* HW registers are cleared on read */
2234         ixgbe_dev_stats_get(dev, NULL);
2235
2236         /* Reset software totals */
2237         memset(stats, 0, sizeof(*stats));
2238 }
2239
2240 static int
2241 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2242                                          unsigned n)
2243 {
2244         struct ixgbe_hw *hw =
2245                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246         struct ixgbe_hw_stats *hw_stats =
2247                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2248         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2249         unsigned i, count = IXGBE_NB_XSTATS;
2250
2251         if (n < count)
2252                 return count;
2253
2254         total_missed_rx = 0;
2255         total_qbrc = 0;
2256         total_qprc = 0;
2257         total_qprdc = 0;
2258
2259         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2260                                                            &total_qprc, &total_qprdc);
2261
2262         /* If this is a reset xstats is NULL, and we have cleared the
2263          * registers by reading them.
2264          */
2265         if (!xstats)
2266                 return 0;
2267
2268         /* Extended stats */
2269         for (i = 0; i < IXGBE_NB_XSTATS; i++) {
2270                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2271                                 "%s", rte_ixgbe_stats_strings[i].name);
2272                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2273                                                         rte_ixgbe_stats_strings[i].offset);
2274         }
2275
2276         return count;
2277 }
2278
2279 static void
2280 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2281 {
2282         struct ixgbe_hw_stats *stats =
2283                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2284
2285         /* HW registers are cleared on read */
2286         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2287
2288         /* Reset software totals */
2289         memset(stats, 0, sizeof(*stats));
2290 }
2291
2292 static void
2293 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2294 {
2295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2297                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2298
2299         /* Good Rx packet, include VF loopback */
2300         UPDATE_VF_STAT(IXGBE_VFGPRC,
2301             hw_stats->last_vfgprc, hw_stats->vfgprc);
2302
2303         /* Good Rx octets, include VF loopback */
2304         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2305             hw_stats->last_vfgorc, hw_stats->vfgorc);
2306
2307         /* Good Tx packet, include VF loopback */
2308         UPDATE_VF_STAT(IXGBE_VFGPTC,
2309             hw_stats->last_vfgptc, hw_stats->vfgptc);
2310
2311         /* Good Tx octets, include VF loopback */
2312         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2313             hw_stats->last_vfgotc, hw_stats->vfgotc);
2314
2315         /* Rx Multicst Packet */
2316         UPDATE_VF_STAT(IXGBE_VFMPRC,
2317             hw_stats->last_vfmprc, hw_stats->vfmprc);
2318
2319         if (stats == NULL)
2320                 return;
2321
2322         stats->ipackets = hw_stats->vfgprc;
2323         stats->ibytes = hw_stats->vfgorc;
2324         stats->opackets = hw_stats->vfgptc;
2325         stats->obytes = hw_stats->vfgotc;
2326         stats->imcasts = hw_stats->vfmprc;
2327         /* stats->imcasts should be removed as imcasts is deprecated */
2328 }
2329
2330 static void
2331 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2332 {
2333         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2334                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2335
2336         /* Sync HW register to the last stats */
2337         ixgbevf_dev_stats_get(dev, NULL);
2338
2339         /* reset HW current stats*/
2340         hw_stats->vfgprc = 0;
2341         hw_stats->vfgorc = 0;
2342         hw_stats->vfgptc = 0;
2343         hw_stats->vfgotc = 0;
2344         hw_stats->vfmprc = 0;
2345
2346 }
2347
2348 static void
2349 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2350 {
2351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352
2353         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2354         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2355         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2356         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2357         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2358         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2359         dev_info->max_vfs = dev->pci_dev->max_vfs;
2360         if (hw->mac.type == ixgbe_mac_82598EB)
2361                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2362         else
2363                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2364         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2365         dev_info->rx_offload_capa =
2366                 DEV_RX_OFFLOAD_VLAN_STRIP |
2367                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2368                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2369                 DEV_RX_OFFLOAD_TCP_CKSUM;
2370
2371         /*
2372          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2373          * mode.
2374          */
2375         if ((hw->mac.type == ixgbe_mac_82599EB ||
2376              hw->mac.type == ixgbe_mac_X540) &&
2377             !RTE_ETH_DEV_SRIOV(dev).active)
2378                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2379
2380         dev_info->tx_offload_capa =
2381                 DEV_TX_OFFLOAD_VLAN_INSERT |
2382                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2383                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2384                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2385                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2386                 DEV_TX_OFFLOAD_TCP_TSO;
2387
2388         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2389                 .rx_thresh = {
2390                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2391                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2392                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2393                 },
2394                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2395                 .rx_drop_en = 0,
2396         };
2397
2398         dev_info->default_txconf = (struct rte_eth_txconf) {
2399                 .tx_thresh = {
2400                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2401                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2402                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2403                 },
2404                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2405                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2406                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2407                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2408         };
2409         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2410         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2411         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2412 }
2413
2414 static void
2415 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2416                      struct rte_eth_dev_info *dev_info)
2417 {
2418         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2419
2420         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2421         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2422         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2423         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2424         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2425         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2426         dev_info->max_vfs = dev->pci_dev->max_vfs;
2427         if (hw->mac.type == ixgbe_mac_82598EB)
2428                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2429         else
2430                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2431         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2432                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2433                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2434                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2435         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2436                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2437                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2438                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2439                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2440                                 DEV_TX_OFFLOAD_TCP_TSO;
2441
2442         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2443                 .rx_thresh = {
2444                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2445                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2446                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2447                 },
2448                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2449                 .rx_drop_en = 0,
2450         };
2451
2452         dev_info->default_txconf = (struct rte_eth_txconf) {
2453                 .tx_thresh = {
2454                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2455                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2456                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2457                 },
2458                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2459                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2460                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2461                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2462         };
2463 }
2464
2465 /* return 0 means link status changed, -1 means not changed */
2466 static int
2467 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2468 {
2469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2470         struct rte_eth_link link, old;
2471         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2472         int link_up;
2473         int diag;
2474
2475         link.link_status = 0;
2476         link.link_speed = 0;
2477         link.link_duplex = 0;
2478         memset(&old, 0, sizeof(old));
2479         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2480
2481         hw->mac.get_link_status = true;
2482
2483         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2484         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2485                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2486         else
2487                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2488
2489         if (diag != 0) {
2490                 link.link_speed = ETH_LINK_SPEED_100;
2491                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2492                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2493                 if (link.link_status == old.link_status)
2494                         return -1;
2495                 return 0;
2496         }
2497
2498         if (link_up == 0) {
2499                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2500                 if (link.link_status == old.link_status)
2501                         return -1;
2502                 return 0;
2503         }
2504         link.link_status = 1;
2505         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2506
2507         switch (link_speed) {
2508         default:
2509         case IXGBE_LINK_SPEED_UNKNOWN:
2510                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2511                 link.link_speed = ETH_LINK_SPEED_100;
2512                 break;
2513
2514         case IXGBE_LINK_SPEED_100_FULL:
2515                 link.link_speed = ETH_LINK_SPEED_100;
2516                 break;
2517
2518         case IXGBE_LINK_SPEED_1GB_FULL:
2519                 link.link_speed = ETH_LINK_SPEED_1000;
2520                 break;
2521
2522         case IXGBE_LINK_SPEED_10GB_FULL:
2523                 link.link_speed = ETH_LINK_SPEED_10000;
2524                 break;
2525         }
2526         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2527
2528         if (link.link_status == old.link_status)
2529                 return -1;
2530
2531         return 0;
2532 }
2533
2534 static void
2535 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2536 {
2537         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         uint32_t fctrl;
2539
2540         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2541         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2542         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2543 }
2544
2545 static void
2546 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2547 {
2548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549         uint32_t fctrl;
2550
2551         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2552         fctrl &= (~IXGBE_FCTRL_UPE);
2553         if (dev->data->all_multicast == 1)
2554                 fctrl |= IXGBE_FCTRL_MPE;
2555         else
2556                 fctrl &= (~IXGBE_FCTRL_MPE);
2557         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2558 }
2559
2560 static void
2561 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2562 {
2563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2564         uint32_t fctrl;
2565
2566         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2567         fctrl |= IXGBE_FCTRL_MPE;
2568         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2569 }
2570
2571 static void
2572 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2573 {
2574         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2575         uint32_t fctrl;
2576
2577         if (dev->data->promiscuous == 1)
2578                 return; /* must remain in all_multicast mode */
2579
2580         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2581         fctrl &= (~IXGBE_FCTRL_MPE);
2582         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2583 }
2584
2585 /**
2586  * It clears the interrupt causes and enables the interrupt.
2587  * It will be called once only during nic initialized.
2588  *
2589  * @param dev
2590  *  Pointer to struct rte_eth_dev.
2591  *
2592  * @return
2593  *  - On success, zero.
2594  *  - On failure, a negative value.
2595  */
2596 static int
2597 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2598 {
2599         struct ixgbe_interrupt *intr =
2600                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2601
2602         ixgbe_dev_link_status_print(dev);
2603         intr->mask |= IXGBE_EICR_LSC;
2604
2605         return 0;
2606 }
2607
2608 /**
2609  * It clears the interrupt causes and enables the interrupt.
2610  * It will be called once only during nic initialized.
2611  *
2612  * @param dev
2613  *  Pointer to struct rte_eth_dev.
2614  *
2615  * @return
2616  *  - On success, zero.
2617  *  - On failure, a negative value.
2618  */
2619 static int
2620 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2621 {
2622         struct ixgbe_interrupt *intr =
2623                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2624
2625         intr->mask |= IXGBE_EICR_RTX_QUEUE;
2626
2627         return 0;
2628 }
2629
2630 /*
2631  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2632  *
2633  * @param dev
2634  *  Pointer to struct rte_eth_dev.
2635  *
2636  * @return
2637  *  - On success, zero.
2638  *  - On failure, a negative value.
2639  */
2640 static int
2641 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2642 {
2643         uint32_t eicr;
2644         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645         struct ixgbe_interrupt *intr =
2646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2647
2648         /* clear all cause mask */
2649         ixgbe_disable_intr(hw);
2650
2651         /* read-on-clear nic registers here */
2652         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2653         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2654
2655         intr->flags = 0;
2656
2657         /* set flag for async link update */
2658         if (eicr & IXGBE_EICR_LSC)
2659                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2660
2661         if (eicr & IXGBE_EICR_MAILBOX)
2662                 intr->flags |= IXGBE_FLAG_MAILBOX;
2663
2664         return 0;
2665 }
2666
2667 static int
2668 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
2669 {
2670         uint32_t eicr;
2671         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2672         struct ixgbe_interrupt *intr =
2673                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2674
2675         /* clear all cause mask */
2676         ixgbevf_intr_disable(hw);
2677
2678         /* read-on-clear nic registers here */
2679         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
2680         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2681
2682         intr->flags = 0;
2683
2684         /* set flag for async link update */
2685         if (eicr & IXGBE_EICR_LSC)
2686                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2687
2688         return 0;
2689 }
2690
2691 /**
2692  * It gets and then prints the link status.
2693  *
2694  * @param dev
2695  *  Pointer to struct rte_eth_dev.
2696  *
2697  * @return
2698  *  - On success, zero.
2699  *  - On failure, a negative value.
2700  */
2701 static void
2702 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2703 {
2704         struct rte_eth_link link;
2705
2706         memset(&link, 0, sizeof(link));
2707         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2708         if (link.link_status) {
2709                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2710                                         (int)(dev->data->port_id),
2711                                         (unsigned)link.link_speed,
2712                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2713                                         "full-duplex" : "half-duplex");
2714         } else {
2715                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2716                                 (int)(dev->data->port_id));
2717         }
2718         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
2719                                 dev->pci_dev->addr.domain,
2720                                 dev->pci_dev->addr.bus,
2721                                 dev->pci_dev->addr.devid,
2722                                 dev->pci_dev->addr.function);
2723 }
2724
2725 /*
2726  * It executes link_update after knowing an interrupt occurred.
2727  *
2728  * @param dev
2729  *  Pointer to struct rte_eth_dev.
2730  *
2731  * @return
2732  *  - On success, zero.
2733  *  - On failure, a negative value.
2734  */
2735 static int
2736 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2737 {
2738         struct ixgbe_interrupt *intr =
2739                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2740         int64_t timeout;
2741         struct rte_eth_link link;
2742         int intr_enable_delay = false;
2743
2744         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2745
2746         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2747                 ixgbe_pf_mbx_process(dev);
2748                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2749         }
2750
2751         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2752                 /* get the link status before link update, for predicting later */
2753                 memset(&link, 0, sizeof(link));
2754                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2755
2756                 ixgbe_dev_link_update(dev, 0);
2757
2758                 /* likely to up */
2759                 if (!link.link_status)
2760                         /* handle it 1 sec later, wait it being stable */
2761                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2762                 /* likely to down */
2763                 else
2764                         /* handle it 4 sec later, wait it being stable */
2765                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2766
2767                 ixgbe_dev_link_status_print(dev);
2768
2769                 intr_enable_delay = true;
2770         }
2771
2772         if (intr_enable_delay) {
2773                 if (rte_eal_alarm_set(timeout * 1000,
2774                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2775                         PMD_DRV_LOG(ERR, "Error setting alarm");
2776         } else {
2777                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2778                 ixgbe_enable_intr(dev);
2779                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2780         }
2781
2782
2783         return 0;
2784 }
2785
2786 static int
2787 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
2788 {
2789         struct ixgbe_hw *hw =
2790                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791
2792         PMD_DRV_LOG(DEBUG, "enable intr immediately");
2793         ixgbevf_intr_enable(hw);
2794         rte_intr_enable(&dev->pci_dev->intr_handle);
2795         return 0;
2796 }
2797
2798 /**
2799  * Interrupt handler which shall be registered for alarm callback for delayed
2800  * handling specific interrupt to wait for the stable nic state. As the
2801  * NIC interrupt state is not stable for ixgbe after link is just down,
2802  * it needs to wait 4 seconds to get the stable status.
2803  *
2804  * @param handle
2805  *  Pointer to interrupt handle.
2806  * @param param
2807  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2808  *
2809  * @return
2810  *  void
2811  */
2812 static void
2813 ixgbe_dev_interrupt_delayed_handler(void *param)
2814 {
2815         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2816         struct ixgbe_interrupt *intr =
2817                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2818         struct ixgbe_hw *hw =
2819                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         uint32_t eicr;
2821
2822         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2823         if (eicr & IXGBE_EICR_MAILBOX)
2824                 ixgbe_pf_mbx_process(dev);
2825
2826         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2827                 ixgbe_dev_link_update(dev, 0);
2828                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2829                 ixgbe_dev_link_status_print(dev);
2830                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2831         }
2832
2833         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2834         ixgbe_enable_intr(dev);
2835         rte_intr_enable(&(dev->pci_dev->intr_handle));
2836 }
2837
2838 /**
2839  * Interrupt handler triggered by NIC  for handling
2840  * specific interrupt.
2841  *
2842  * @param handle
2843  *  Pointer to interrupt handle.
2844  * @param param
2845  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2846  *
2847  * @return
2848  *  void
2849  */
2850 static void
2851 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2852                             void *param)
2853 {
2854         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2855
2856         ixgbe_dev_interrupt_get_status(dev);
2857         ixgbe_dev_interrupt_action(dev);
2858 }
2859
2860 static void
2861 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2862                               void *param)
2863 {
2864         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2865
2866         ixgbevf_dev_interrupt_get_status(dev);
2867         ixgbevf_dev_interrupt_action(dev);
2868 }
2869
2870 static int
2871 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2872 {
2873         struct ixgbe_hw *hw;
2874
2875         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2876         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2877 }
2878
2879 static int
2880 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2881 {
2882         struct ixgbe_hw *hw;
2883
2884         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2885         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2886 }
2887
2888 static int
2889 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2890 {
2891         struct ixgbe_hw *hw;
2892         uint32_t mflcn_reg;
2893         uint32_t fccfg_reg;
2894         int rx_pause;
2895         int tx_pause;
2896
2897         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2898
2899         fc_conf->pause_time = hw->fc.pause_time;
2900         fc_conf->high_water = hw->fc.high_water[0];
2901         fc_conf->low_water = hw->fc.low_water[0];
2902         fc_conf->send_xon = hw->fc.send_xon;
2903         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2904
2905         /*
2906          * Return rx_pause status according to actual setting of
2907          * MFLCN register.
2908          */
2909         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2910         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2911                 rx_pause = 1;
2912         else
2913                 rx_pause = 0;
2914
2915         /*
2916          * Return tx_pause status according to actual setting of
2917          * FCCFG register.
2918          */
2919         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2920         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2921                 tx_pause = 1;
2922         else
2923                 tx_pause = 0;
2924
2925         if (rx_pause && tx_pause)
2926                 fc_conf->mode = RTE_FC_FULL;
2927         else if (rx_pause)
2928                 fc_conf->mode = RTE_FC_RX_PAUSE;
2929         else if (tx_pause)
2930                 fc_conf->mode = RTE_FC_TX_PAUSE;
2931         else
2932                 fc_conf->mode = RTE_FC_NONE;
2933
2934         return 0;
2935 }
2936
2937 static int
2938 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2939 {
2940         struct ixgbe_hw *hw;
2941         int err;
2942         uint32_t rx_buf_size;
2943         uint32_t max_high_water;
2944         uint32_t mflcn;
2945         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2946                 ixgbe_fc_none,
2947                 ixgbe_fc_rx_pause,
2948                 ixgbe_fc_tx_pause,
2949                 ixgbe_fc_full
2950         };
2951
2952         PMD_INIT_FUNC_TRACE();
2953
2954         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2955         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2956         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2957
2958         /*
2959          * At least reserve one Ethernet frame for watermark
2960          * high_water/low_water in kilo bytes for ixgbe
2961          */
2962         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2963         if ((fc_conf->high_water > max_high_water) ||
2964                 (fc_conf->high_water < fc_conf->low_water)) {
2965                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2966                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2967                 return (-EINVAL);
2968         }
2969
2970         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2971         hw->fc.pause_time     = fc_conf->pause_time;
2972         hw->fc.high_water[0]  = fc_conf->high_water;
2973         hw->fc.low_water[0]   = fc_conf->low_water;
2974         hw->fc.send_xon       = fc_conf->send_xon;
2975         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2976
2977         err = ixgbe_fc_enable(hw);
2978
2979         /* Not negotiated is not an error case */
2980         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2981
2982                 /* check if we want to forward MAC frames - driver doesn't have native
2983                  * capability to do that, so we'll write the registers ourselves */
2984
2985                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2986
2987                 /* set or clear MFLCN.PMCF bit depending on configuration */
2988                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2989                         mflcn |= IXGBE_MFLCN_PMCF;
2990                 else
2991                         mflcn &= ~IXGBE_MFLCN_PMCF;
2992
2993                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2994                 IXGBE_WRITE_FLUSH(hw);
2995
2996                 return 0;
2997         }
2998
2999         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3000         return -EIO;
3001 }
3002
3003 /**
3004  *  ixgbe_pfc_enable_generic - Enable flow control
3005  *  @hw: pointer to hardware structure
3006  *  @tc_num: traffic class number
3007  *  Enable flow control according to the current settings.
3008  */
3009 static int
3010 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3011 {
3012         int ret_val = 0;
3013         uint32_t mflcn_reg, fccfg_reg;
3014         uint32_t reg;
3015         uint32_t fcrtl, fcrth;
3016         uint8_t i;
3017         uint8_t nb_rx_en;
3018
3019         /* Validate the water mark configuration */
3020         if (!hw->fc.pause_time) {
3021                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3022                 goto out;
3023         }
3024
3025         /* Low water mark of zero causes XOFF floods */
3026         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3027                  /* High/Low water can not be 0 */
3028                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3029                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3030                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3031                         goto out;
3032                 }
3033
3034                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3035                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3036                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3037                         goto out;
3038                 }
3039         }
3040         /* Negotiate the fc mode to use */
3041         ixgbe_fc_autoneg(hw);
3042
3043         /* Disable any previous flow control settings */
3044         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3045         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3046
3047         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3048         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3049
3050         switch (hw->fc.current_mode) {
3051         case ixgbe_fc_none:
3052                 /*
3053                  * If the count of enabled RX Priority Flow control >1,
3054                  * and the TX pause can not be disabled
3055                  */
3056                 nb_rx_en = 0;
3057                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3058                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3059                         if (reg & IXGBE_FCRTH_FCEN)
3060                                 nb_rx_en++;
3061                 }
3062                 if (nb_rx_en > 1)
3063                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3064                 break;
3065         case ixgbe_fc_rx_pause:
3066                 /*
3067                  * Rx Flow control is enabled and Tx Flow control is
3068                  * disabled by software override. Since there really
3069                  * isn't a way to advertise that we are capable of RX
3070                  * Pause ONLY, we will advertise that we support both
3071                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3072                  * disable the adapter's ability to send PAUSE frames.
3073                  */
3074                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3075                 /*
3076                  * If the count of enabled RX Priority Flow control >1,
3077                  * and the TX pause can not be disabled
3078                  */
3079                 nb_rx_en = 0;
3080                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3081                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3082                         if (reg & IXGBE_FCRTH_FCEN)
3083                                 nb_rx_en++;
3084                 }
3085                 if (nb_rx_en > 1)
3086                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3087                 break;
3088         case ixgbe_fc_tx_pause:
3089                 /*
3090                  * Tx Flow control is enabled, and Rx Flow control is
3091                  * disabled by software override.
3092                  */
3093                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3094                 break;
3095         case ixgbe_fc_full:
3096                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3097                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3098                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3099                 break;
3100         default:
3101                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3102                 ret_val = IXGBE_ERR_CONFIG;
3103                 goto out;
3104                 break;
3105         }
3106
3107         /* Set 802.3x based flow control settings. */
3108         mflcn_reg |= IXGBE_MFLCN_DPF;
3109         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3110         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3111
3112         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3113         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3114                 hw->fc.high_water[tc_num]) {
3115                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3116                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3117                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3118         } else {
3119                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3120                 /*
3121                  * In order to prevent Tx hangs when the internal Tx
3122                  * switch is enabled we must set the high water mark
3123                  * to the maximum FCRTH value.  This allows the Tx
3124                  * switch to function even under heavy Rx workloads.
3125                  */
3126                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3127         }
3128         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3129
3130         /* Configure pause time (2 TCs per register) */
3131         reg = hw->fc.pause_time * 0x00010001;
3132         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3133                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3134
3135         /* Configure flow control refresh threshold value */
3136         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3137
3138 out:
3139         return ret_val;
3140 }
3141
3142 static int
3143 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3144 {
3145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3146         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3147
3148         if(hw->mac.type != ixgbe_mac_82598EB) {
3149                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3150         }
3151         return ret_val;
3152 }
3153
3154 static int
3155 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3156 {
3157         int err;
3158         uint32_t rx_buf_size;
3159         uint32_t max_high_water;
3160         uint8_t tc_num;
3161         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3162         struct ixgbe_hw *hw =
3163                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3164         struct ixgbe_dcb_config *dcb_config =
3165                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3166
3167         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3168                 ixgbe_fc_none,
3169                 ixgbe_fc_rx_pause,
3170                 ixgbe_fc_tx_pause,
3171                 ixgbe_fc_full
3172         };
3173
3174         PMD_INIT_FUNC_TRACE();
3175
3176         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3177         tc_num = map[pfc_conf->priority];
3178         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3179         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3180         /*
3181          * At least reserve one Ethernet frame for watermark
3182          * high_water/low_water in kilo bytes for ixgbe
3183          */
3184         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3185         if ((pfc_conf->fc.high_water > max_high_water) ||
3186             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3187                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3188                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3189                 return (-EINVAL);
3190         }
3191
3192         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3193         hw->fc.pause_time = pfc_conf->fc.pause_time;
3194         hw->fc.send_xon = pfc_conf->fc.send_xon;
3195         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3196         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3197
3198         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3199
3200         /* Not negotiated is not an error case */
3201         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3202                 return 0;
3203
3204         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3205         return -EIO;
3206 }
3207
3208 static int
3209 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3210                           struct rte_eth_rss_reta_entry64 *reta_conf,
3211                           uint16_t reta_size)
3212 {
3213         uint8_t i, j, mask;
3214         uint32_t reta, r;
3215         uint16_t idx, shift;
3216         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3217         uint16_t sp_reta_size;
3218         uint32_t reta_reg;
3219
3220         PMD_INIT_FUNC_TRACE();
3221
3222         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3223                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3224                         "NIC.");
3225                 return -ENOTSUP;
3226         }
3227
3228         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3229         if (reta_size != sp_reta_size) {
3230                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3231                         "(%d) doesn't match the number hardware can supported "
3232                         "(%d)\n", reta_size, sp_reta_size);
3233                 return -EINVAL;
3234         }
3235
3236         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3237                 idx = i / RTE_RETA_GROUP_SIZE;
3238                 shift = i % RTE_RETA_GROUP_SIZE;
3239                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3240                                                 IXGBE_4_BIT_MASK);
3241                 if (!mask)
3242                         continue;
3243                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3244                 if (mask == IXGBE_4_BIT_MASK)
3245                         r = 0;
3246                 else
3247                         r = IXGBE_READ_REG(hw, reta_reg);
3248                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3249                         if (mask & (0x1 << j))
3250                                 reta |= reta_conf[idx].reta[shift + j] <<
3251                                                         (CHAR_BIT * j);
3252                         else
3253                                 reta |= r & (IXGBE_8_BIT_MASK <<
3254                                                 (CHAR_BIT * j));
3255                 }
3256                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3257         }
3258
3259         return 0;
3260 }
3261
3262 static int
3263 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3264                          struct rte_eth_rss_reta_entry64 *reta_conf,
3265                          uint16_t reta_size)
3266 {
3267         uint8_t i, j, mask;
3268         uint32_t reta;
3269         uint16_t idx, shift;
3270         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271         uint16_t sp_reta_size;
3272         uint32_t reta_reg;
3273
3274         PMD_INIT_FUNC_TRACE();
3275         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3276         if (reta_size != sp_reta_size) {
3277                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3278                         "(%d) doesn't match the number hardware can supported "
3279                         "(%d)\n", reta_size, sp_reta_size);
3280                 return -EINVAL;
3281         }
3282
3283         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3284                 idx = i / RTE_RETA_GROUP_SIZE;
3285                 shift = i % RTE_RETA_GROUP_SIZE;
3286                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3287                                                 IXGBE_4_BIT_MASK);
3288                 if (!mask)
3289                         continue;
3290
3291                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3292                 reta = IXGBE_READ_REG(hw, reta_reg);
3293                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3294                         if (mask & (0x1 << j))
3295                                 reta_conf[idx].reta[shift + j] =
3296                                         ((reta >> (CHAR_BIT * j)) &
3297                                                 IXGBE_8_BIT_MASK);
3298                 }
3299         }
3300
3301         return 0;
3302 }
3303
3304 static void
3305 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3306                                 uint32_t index, uint32_t pool)
3307 {
3308         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3309         uint32_t enable_addr = 1;
3310
3311         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3312 }
3313
3314 static void
3315 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3316 {
3317         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3318
3319         ixgbe_clear_rar(hw, index);
3320 }
3321
3322 static void
3323 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3324 {
3325         ixgbe_remove_rar(dev, 0);
3326
3327         ixgbe_add_rar(dev, addr, 0, 0);
3328 }
3329
3330 static int
3331 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3332 {
3333         uint32_t hlreg0;
3334         uint32_t maxfrs;
3335         struct ixgbe_hw *hw;
3336         struct rte_eth_dev_info dev_info;
3337         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3338
3339         ixgbe_dev_info_get(dev, &dev_info);
3340
3341         /* check that mtu is within the allowed range */
3342         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3343                 return -EINVAL;
3344
3345         /* refuse mtu that requires the support of scattered packets when this
3346          * feature has not been enabled before. */
3347         if (!dev->data->scattered_rx &&
3348             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3349              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3350                 return -EINVAL;
3351
3352         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3353         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3354
3355         /* switch to jumbo mode if needed */
3356         if (frame_size > ETHER_MAX_LEN) {
3357                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3358                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3359         } else {
3360                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3361                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3362         }
3363         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3364
3365         /* update max frame size */
3366         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3367
3368         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3369         maxfrs &= 0x0000FFFF;
3370         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3371         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3372
3373         return 0;
3374 }
3375
3376 /*
3377  * Virtual Function operations
3378  */
3379 static void
3380 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3381 {
3382         PMD_INIT_FUNC_TRACE();
3383
3384         /* Clear interrupt mask to stop from interrupts being generated */
3385         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3386
3387         IXGBE_WRITE_FLUSH(hw);
3388 }
3389
3390 static void
3391 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3392 {
3393         PMD_INIT_FUNC_TRACE();
3394
3395         /* VF enable interrupt autoclean */
3396         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3397         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3398         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3399
3400         IXGBE_WRITE_FLUSH(hw);
3401 }
3402
3403 static int
3404 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3405 {
3406         struct rte_eth_conf* conf = &dev->data->dev_conf;
3407         struct ixgbe_adapter *adapter =
3408                         (struct ixgbe_adapter *)dev->data->dev_private;
3409
3410         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3411                      dev->data->port_id);
3412
3413         /*
3414          * VF has no ability to enable/disable HW CRC
3415          * Keep the persistent behavior the same as Host PF
3416          */
3417 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3418         if (!conf->rxmode.hw_strip_crc) {
3419                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3420                 conf->rxmode.hw_strip_crc = 1;
3421         }
3422 #else
3423         if (conf->rxmode.hw_strip_crc) {
3424                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3425                 conf->rxmode.hw_strip_crc = 0;
3426         }
3427 #endif
3428
3429         /*
3430          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3431          * allocation or vector Rx preconditions we will reset it.
3432          */
3433         adapter->rx_bulk_alloc_allowed = true;
3434         adapter->rx_vec_allowed = true;
3435
3436         return 0;
3437 }
3438
3439 static int
3440 ixgbevf_dev_start(struct rte_eth_dev *dev)
3441 {
3442         struct ixgbe_hw *hw =
3443                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3444         uint32_t intr_vector = 0;
3445         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3446
3447         int err, mask = 0;
3448
3449         PMD_INIT_FUNC_TRACE();
3450
3451         hw->mac.ops.reset_hw(hw);
3452         hw->mac.get_link_status = true;
3453
3454         /* negotiate mailbox API version to use with the PF. */
3455         ixgbevf_negotiate_api(hw);
3456
3457         ixgbevf_dev_tx_init(dev);
3458
3459         /* This can fail when allocating mbufs for descriptor rings */
3460         err = ixgbevf_dev_rx_init(dev);
3461         if (err) {
3462                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3463                 ixgbe_dev_clear_queues(dev);
3464                 return err;
3465         }
3466
3467         /* Set vfta */
3468         ixgbevf_set_vfta_all(dev,1);
3469
3470         /* Set HW strip */
3471         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3472                 ETH_VLAN_EXTEND_MASK;
3473         ixgbevf_vlan_offload_set(dev, mask);
3474
3475         ixgbevf_dev_rxtx_start(dev);
3476
3477         /* check and configure queue intr-vector mapping */
3478         if (dev->data->dev_conf.intr_conf.rxq != 0)
3479                 intr_vector = dev->data->nb_rx_queues;
3480
3481         if (rte_intr_efd_enable(intr_handle, intr_vector))
3482                 return -1;
3483
3484         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3485                 intr_handle->intr_vec =
3486                         rte_zmalloc("intr_vec",
3487                                     dev->data->nb_rx_queues * sizeof(int), 0);
3488                 if (intr_handle->intr_vec == NULL) {
3489                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3490                                      " intr_vec\n", dev->data->nb_rx_queues);
3491                         return -ENOMEM;
3492                 }
3493         }
3494         ixgbevf_configure_msix(dev);
3495
3496         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3497                 if (rte_intr_allow_others(intr_handle))
3498                         rte_intr_callback_register(intr_handle,
3499                                         ixgbevf_dev_interrupt_handler,
3500                                         (void *)dev);
3501                 else
3502                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3503                                      " no intr multiplex\n");
3504         }
3505
3506         rte_intr_enable(intr_handle);
3507
3508         /* Re-enable interrupt for VF */
3509         ixgbevf_intr_enable(hw);
3510
3511         return 0;
3512 }
3513
3514 static void
3515 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3516 {
3517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3519
3520         PMD_INIT_FUNC_TRACE();
3521
3522         hw->adapter_stopped = 1;
3523         ixgbe_stop_adapter(hw);
3524
3525         /*
3526           * Clear what we set, but we still keep shadow_vfta to
3527           * restore after device starts
3528           */
3529         ixgbevf_set_vfta_all(dev,0);
3530
3531         /* Clear stored conf */
3532         dev->data->scattered_rx = 0;
3533
3534         ixgbe_dev_clear_queues(dev);
3535
3536         /* disable intr eventfd mapping */
3537         rte_intr_disable(intr_handle);
3538
3539         /* Clean datapath event and queue/vec mapping */
3540         rte_intr_efd_disable(intr_handle);
3541         if (intr_handle->intr_vec != NULL) {
3542                 rte_free(intr_handle->intr_vec);
3543                 intr_handle->intr_vec = NULL;
3544         }
3545 }
3546
3547 static void
3548 ixgbevf_dev_close(struct rte_eth_dev *dev)
3549 {
3550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3551         struct rte_pci_device *pci_dev;
3552
3553         PMD_INIT_FUNC_TRACE();
3554
3555         ixgbe_reset_hw(hw);
3556
3557         ixgbevf_dev_stop(dev);
3558
3559         ixgbe_dev_free_queues(dev);
3560
3561         /* reprogram the RAR[0] in case user changed it. */
3562         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3563
3564         pci_dev = dev->pci_dev;
3565         if (pci_dev->intr_handle.intr_vec) {
3566                 rte_free(pci_dev->intr_handle.intr_vec);
3567                 pci_dev->intr_handle.intr_vec = NULL;
3568         }
3569 }
3570
3571 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3572 {
3573         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3574         struct ixgbe_vfta * shadow_vfta =
3575                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3576         int i = 0, j = 0, vfta = 0, mask = 1;
3577
3578         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3579                 vfta = shadow_vfta->vfta[i];
3580                 if(vfta){
3581                         mask = 1;
3582                         for (j = 0; j < 32; j++){
3583                                 if(vfta & mask)
3584                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3585                                 mask<<=1;
3586                         }
3587                 }
3588         }
3589
3590 }
3591
3592 static int
3593 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3594 {
3595         struct ixgbe_hw *hw =
3596                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597         struct ixgbe_vfta * shadow_vfta =
3598                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3599         uint32_t vid_idx = 0;
3600         uint32_t vid_bit = 0;
3601         int ret = 0;
3602
3603         PMD_INIT_FUNC_TRACE();
3604
3605         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3606         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3607         if(ret){
3608                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3609                 return ret;
3610         }
3611         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3612         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3613
3614         /* Save what we set and retore it after device reset */
3615         if (on)
3616                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3617         else
3618                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3619
3620         return 0;
3621 }
3622
3623 static void
3624 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3625 {
3626         struct ixgbe_hw *hw =
3627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3628         uint32_t ctrl;
3629
3630         PMD_INIT_FUNC_TRACE();
3631
3632         if(queue >= hw->mac.max_rx_queues)
3633                 return;
3634
3635         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3636         if(on)
3637                 ctrl |= IXGBE_RXDCTL_VME;
3638         else
3639                 ctrl &= ~IXGBE_RXDCTL_VME;
3640         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3641
3642         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3643 }
3644
3645 static void
3646 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3647 {
3648         struct ixgbe_hw *hw =
3649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3650         uint16_t i;
3651         int on = 0;
3652
3653         /* VF function only support hw strip feature, others are not support */
3654         if(mask & ETH_VLAN_STRIP_MASK){
3655                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3656
3657                 for(i=0; i < hw->mac.max_rx_queues; i++)
3658                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3659         }
3660 }
3661
3662 static int
3663 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3664 {
3665         uint32_t reg_val;
3666
3667         /* we only need to do this if VMDq is enabled */
3668         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3669         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3670                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3671                 return (-1);
3672         }
3673
3674         return 0;
3675 }
3676
3677 static uint32_t
3678 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3679 {
3680         uint32_t vector = 0;
3681         switch (hw->mac.mc_filter_type) {
3682         case 0:   /* use bits [47:36] of the address */
3683                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3684                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3685                 break;
3686         case 1:   /* use bits [46:35] of the address */
3687                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3688                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3689                 break;
3690         case 2:   /* use bits [45:34] of the address */
3691                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3692                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3693                 break;
3694         case 3:   /* use bits [43:32] of the address */
3695                 vector = ((uc_addr->addr_bytes[4]) |
3696                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3697                 break;
3698         default:  /* Invalid mc_filter_type */
3699                 break;
3700         }
3701
3702         /* vector can only be 12-bits or boundary will be exceeded */
3703         vector &= 0xFFF;
3704         return vector;
3705 }
3706
3707 static int
3708 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3709                                uint8_t on)
3710 {
3711         uint32_t vector;
3712         uint32_t uta_idx;
3713         uint32_t reg_val;
3714         uint32_t uta_shift;
3715         uint32_t rc;
3716         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3717         const uint32_t ixgbe_uta_bit_shift = 5;
3718         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3719         const uint32_t bit1 = 0x1;
3720
3721         struct ixgbe_hw *hw =
3722                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3723         struct ixgbe_uta_info *uta_info =
3724                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3725
3726         /* The UTA table only exists on 82599 hardware and newer */
3727         if (hw->mac.type < ixgbe_mac_82599EB)
3728                 return (-ENOTSUP);
3729
3730         vector = ixgbe_uta_vector(hw,mac_addr);
3731         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3732         uta_shift = vector & ixgbe_uta_bit_mask;
3733
3734         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3735         if(rc == on)
3736                 return 0;
3737
3738         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3739         if (on) {
3740                 uta_info->uta_in_use++;
3741                 reg_val |= (bit1 << uta_shift);
3742                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3743         } else {
3744                 uta_info->uta_in_use--;
3745                 reg_val &= ~(bit1 << uta_shift);
3746                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3747         }
3748
3749         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3750
3751         if (uta_info->uta_in_use > 0)
3752                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3753                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3754         else
3755                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3756
3757         return 0;
3758 }
3759
3760 static int
3761 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3762 {
3763         int i;
3764         struct ixgbe_hw *hw =
3765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3766         struct ixgbe_uta_info *uta_info =
3767                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3768
3769         /* The UTA table only exists on 82599 hardware and newer */
3770         if (hw->mac.type < ixgbe_mac_82599EB)
3771                 return (-ENOTSUP);
3772
3773         if(on) {
3774                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3775                         uta_info->uta_shadow[i] = ~0;
3776                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3777                 }
3778         } else {
3779                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3780                         uta_info->uta_shadow[i] = 0;
3781                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3782                 }
3783         }
3784         return 0;
3785
3786 }
3787
3788 uint32_t
3789 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3790 {
3791         uint32_t new_val = orig_val;
3792
3793         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3794                 new_val |= IXGBE_VMOLR_AUPE;
3795         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3796                 new_val |= IXGBE_VMOLR_ROMPE;
3797         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3798                 new_val |= IXGBE_VMOLR_ROPE;
3799         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3800                 new_val |= IXGBE_VMOLR_BAM;
3801         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3802                 new_val |= IXGBE_VMOLR_MPE;
3803
3804         return new_val;
3805 }
3806
3807 static int
3808 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3809                                uint16_t rx_mask, uint8_t on)
3810 {
3811         int val = 0;
3812
3813         struct ixgbe_hw *hw =
3814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3815         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3816
3817         if (hw->mac.type == ixgbe_mac_82598EB) {
3818                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3819                              " on 82599 hardware and newer");
3820                 return (-ENOTSUP);
3821         }
3822         if (ixgbe_vmdq_mode_check(hw) < 0)
3823                 return (-ENOTSUP);
3824
3825         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3826
3827         if (on)
3828                 vmolr |= val;
3829         else
3830                 vmolr &= ~val;
3831
3832         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3833
3834         return 0;
3835 }
3836
3837 static int
3838 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3839 {
3840         uint32_t reg,addr;
3841         uint32_t val;
3842         const uint8_t bit1 = 0x1;
3843
3844         struct ixgbe_hw *hw =
3845                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3846
3847         if (ixgbe_vmdq_mode_check(hw) < 0)
3848                 return (-ENOTSUP);
3849
3850         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3851         reg = IXGBE_READ_REG(hw, addr);
3852         val = bit1 << pool;
3853
3854         if (on)
3855                 reg |= val;
3856         else
3857                 reg &= ~val;
3858
3859         IXGBE_WRITE_REG(hw, addr,reg);
3860
3861         return 0;
3862 }
3863
3864 static int
3865 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3866 {
3867         uint32_t reg,addr;
3868         uint32_t val;
3869         const uint8_t bit1 = 0x1;
3870
3871         struct ixgbe_hw *hw =
3872                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3873
3874         if (ixgbe_vmdq_mode_check(hw) < 0)
3875                 return (-ENOTSUP);
3876
3877         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3878         reg = IXGBE_READ_REG(hw, addr);
3879         val = bit1 << pool;
3880
3881         if (on)
3882                 reg |= val;
3883         else
3884                 reg &= ~val;
3885
3886         IXGBE_WRITE_REG(hw, addr,reg);
3887
3888         return 0;
3889 }
3890
3891 static int
3892 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3893                         uint64_t pool_mask, uint8_t vlan_on)
3894 {
3895         int ret = 0;
3896         uint16_t pool_idx;
3897         struct ixgbe_hw *hw =
3898                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3899
3900         if (ixgbe_vmdq_mode_check(hw) < 0)
3901                 return (-ENOTSUP);
3902         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3903                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3904                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3905                         if (ret < 0)
3906                                 return ret;
3907         }
3908
3909         return ret;
3910 }
3911
3912 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3913 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3914 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3915 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3916 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3917         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3918         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3919
3920 static int
3921 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3922                         struct rte_eth_mirror_conf *mirror_conf,
3923                         uint8_t rule_id, uint8_t on)
3924 {
3925         uint32_t mr_ctl,vlvf;
3926         uint32_t mp_lsb = 0;
3927         uint32_t mv_msb = 0;
3928         uint32_t mv_lsb = 0;
3929         uint32_t mp_msb = 0;
3930         uint8_t i = 0;
3931         int reg_index = 0;
3932         uint64_t vlan_mask = 0;
3933
3934         const uint8_t pool_mask_offset = 32;
3935         const uint8_t vlan_mask_offset = 32;
3936         const uint8_t dst_pool_offset = 8;
3937         const uint8_t rule_mr_offset  = 4;
3938         const uint8_t mirror_rule_mask= 0x0F;
3939
3940         struct ixgbe_mirror_info *mr_info =
3941                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3942         struct ixgbe_hw *hw =
3943                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         uint8_t mirror_type = 0;
3945
3946         if (ixgbe_vmdq_mode_check(hw) < 0)
3947                 return -ENOTSUP;
3948
3949         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3950                 return -EINVAL;
3951
3952         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3953                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3954                         mirror_conf->rule_type);
3955                 return -EINVAL;
3956         }
3957
3958         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3959                 mirror_type |= IXGBE_MRCTL_VLME;
3960                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3961                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3962                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3963                                 /* search vlan id related pool vlan filter index */
3964                                 reg_index = ixgbe_find_vlvf_slot(hw,
3965                                                 mirror_conf->vlan.vlan_id[i]);
3966                                 if(reg_index < 0)
3967                                         return -EINVAL;
3968                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3969                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3970                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3971                                       mirror_conf->vlan.vlan_id[i]))
3972                                         vlan_mask |= (1ULL << reg_index);
3973                                 else
3974                                         return -EINVAL;
3975                         }
3976                 }
3977
3978                 if (on) {
3979                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3980                         mv_msb = vlan_mask >> vlan_mask_offset;
3981
3982                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3983                                                 mirror_conf->vlan.vlan_mask;
3984                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3985                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3986                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3987                                                 mirror_conf->vlan.vlan_id[i];
3988                         }
3989                 } else {
3990                         mv_lsb = 0;
3991                         mv_msb = 0;
3992                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3993                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3994                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3995                 }
3996         }
3997
3998         /*
3999          * if enable pool mirror, write related pool mask register,if disable
4000          * pool mirror, clear PFMRVM register
4001          */
4002         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4003                 mirror_type |= IXGBE_MRCTL_VPME;
4004                 if (on) {
4005                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4006                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4007                         mr_info->mr_conf[rule_id].pool_mask =
4008                                         mirror_conf->pool_mask;
4009
4010                 } else {
4011                         mp_lsb = 0;
4012                         mp_msb = 0;
4013                         mr_info->mr_conf[rule_id].pool_mask = 0;
4014                 }
4015         }
4016         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4017                 mirror_type |= IXGBE_MRCTL_UPME;
4018         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4019                 mirror_type |= IXGBE_MRCTL_DPME;
4020
4021         /* read  mirror control register and recalculate it */
4022         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4023
4024         if (on) {
4025                 mr_ctl |= mirror_type;
4026                 mr_ctl &= mirror_rule_mask;
4027                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4028         } else
4029                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4030
4031         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4032         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4033
4034         /* write mirrror control  register */
4035         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4036
4037         /* write pool mirrror control  register */
4038         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4039                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4040                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4041                                 mp_msb);
4042         }
4043         /* write VLAN mirrror control  register */
4044         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4045                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4046                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4047                                 mv_msb);
4048         }
4049
4050         return 0;
4051 }
4052
4053 static int
4054 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4055 {
4056         int mr_ctl = 0;
4057         uint32_t lsb_val = 0;
4058         uint32_t msb_val = 0;
4059         const uint8_t rule_mr_offset = 4;
4060
4061         struct ixgbe_hw *hw =
4062                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4063         struct ixgbe_mirror_info *mr_info =
4064                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4065
4066         if (ixgbe_vmdq_mode_check(hw) < 0)
4067                 return (-ENOTSUP);
4068
4069         memset(&mr_info->mr_conf[rule_id], 0,
4070                 sizeof(struct rte_eth_mirror_conf));
4071
4072         /* clear PFVMCTL register */
4073         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4074
4075         /* clear pool mask register */
4076         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4077         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4078
4079         /* clear vlan mask register */
4080         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4081         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4082
4083         return 0;
4084 }
4085
4086 static int
4087 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4088 {
4089         uint32_t mask;
4090         struct ixgbe_hw *hw =
4091                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4092
4093         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4094         mask |= (1 << queue_id);
4095         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4096
4097         rte_intr_enable(&dev->pci_dev->intr_handle);
4098
4099         return 0;
4100 }
4101
4102 static int
4103 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4104 {
4105         uint32_t mask;
4106         struct ixgbe_hw *hw =
4107                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4108
4109         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4110         mask &= ~(1 << queue_id);
4111         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4112
4113         return 0;
4114 }
4115
4116 static int
4117 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4118 {
4119         uint32_t mask;
4120         struct ixgbe_hw *hw =
4121                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4122         struct ixgbe_interrupt *intr =
4123                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4124
4125         if (queue_id < 16) {
4126                 ixgbe_disable_intr(hw);
4127                 intr->mask |= (1 << queue_id);
4128                 ixgbe_enable_intr(dev);
4129         } else if (queue_id < 32) {
4130                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4131                 mask &= (1 << queue_id);
4132                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4133         } else if (queue_id < 64) {
4134                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4135                 mask &= (1 << (queue_id - 32));
4136                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4137         }
4138         rte_intr_enable(&dev->pci_dev->intr_handle);
4139
4140         return 0;
4141 }
4142
4143 static int
4144 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4145 {
4146         uint32_t mask;
4147         struct ixgbe_hw *hw =
4148                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149         struct ixgbe_interrupt *intr =
4150                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4151
4152         if (queue_id < 16) {
4153                 ixgbe_disable_intr(hw);
4154                 intr->mask &= ~(1 << queue_id);
4155                 ixgbe_enable_intr(dev);
4156         } else if (queue_id < 32) {
4157                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4158                 mask &= ~(1 << queue_id);
4159                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4160         } else if (queue_id < 64) {
4161                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4162                 mask &= ~(1 << (queue_id - 32));
4163                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4164         }
4165
4166         return 0;
4167 }
4168
4169 static void
4170 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4171                      uint8_t queue, uint8_t msix_vector)
4172 {
4173         uint32_t tmp, idx;
4174
4175         if (direction == -1) {
4176                 /* other causes */
4177                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4178                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4179                 tmp &= ~0xFF;
4180                 tmp |= msix_vector;
4181                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4182         } else {
4183                 /* rx or tx cause */
4184                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4185                 idx = ((16 * (queue & 1)) + (8 * direction));
4186                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4187                 tmp &= ~(0xFF << idx);
4188                 tmp |= (msix_vector << idx);
4189                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4190         }
4191 }
4192
4193 /**
4194  * set the IVAR registers, mapping interrupt causes to vectors
4195  * @param hw
4196  *  pointer to ixgbe_hw struct
4197  * @direction
4198  *  0 for Rx, 1 for Tx, -1 for other causes
4199  * @queue
4200  *  queue to map the corresponding interrupt to
4201  * @msix_vector
4202  *  the vector to map to the corresponding queue
4203  */
4204 static void
4205 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4206                    uint8_t queue, uint8_t msix_vector)
4207 {
4208         uint32_t tmp, idx;
4209
4210         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4211         if (hw->mac.type == ixgbe_mac_82598EB) {
4212                 if (direction == -1)
4213                         direction = 0;
4214                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4215                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4216                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4217                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4218                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4219         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4220                         (hw->mac.type == ixgbe_mac_X540)) {
4221                 if (direction == -1) {
4222                         /* other causes */
4223                         idx = ((queue & 1) * 8);
4224                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4225                         tmp &= ~(0xFF << idx);
4226                         tmp |= (msix_vector << idx);
4227                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4228                 } else {
4229                         /* rx or tx causes */
4230                         idx = ((16 * (queue & 1)) + (8 * direction));
4231                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4232                         tmp &= ~(0xFF << idx);
4233                         tmp |= (msix_vector << idx);
4234                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4235                 }
4236         }
4237 }
4238
4239 static void
4240 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4241 {
4242         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4243         struct ixgbe_hw *hw =
4244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4245         uint32_t q_idx;
4246         uint32_t vector_idx = 0;
4247
4248         /* won't configure msix register if no mapping is done
4249          * between intr vector and event fd.
4250          */
4251         if (!rte_intr_dp_is_en(intr_handle))
4252                 return;
4253
4254         /* Configure all RX queues of VF */
4255         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4256                 /* Force all queue use vector 0,
4257                  * as IXGBE_VF_MAXMSIVECOTR = 1
4258                  */
4259                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4260                 intr_handle->intr_vec[q_idx] = vector_idx;
4261         }
4262
4263         /* Configure VF Rx queue ivar */
4264         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4265 }
4266
4267 /**
4268  * Sets up the hardware to properly generate MSI-X interrupts
4269  * @hw
4270  *  board private structure
4271  */
4272 static void
4273 ixgbe_configure_msix(struct rte_eth_dev *dev)
4274 {
4275         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4276         struct ixgbe_hw *hw =
4277                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4278         uint32_t queue_id, vec = 0;
4279         uint32_t mask;
4280         uint32_t gpie;
4281
4282         /* won't configure msix register if no mapping is done
4283          * between intr vector and event fd
4284          */
4285         if (!rte_intr_dp_is_en(intr_handle))
4286                 return;
4287
4288         /* setup GPIE for MSI-x mode */
4289         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4290         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4291                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4292         /* auto clearing and auto setting corresponding bits in EIMS
4293          * when MSI-X interrupt is triggered
4294          */
4295         if (hw->mac.type == ixgbe_mac_82598EB) {
4296                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4297         } else {
4298                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4299                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4300         }
4301         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4302
4303         /* Populate the IVAR table and set the ITR values to the
4304          * corresponding register.
4305          */
4306         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4307              queue_id++) {
4308                 /* by default, 1:1 mapping */
4309                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4310                 intr_handle->intr_vec[queue_id] = vec;
4311                 if (vec < intr_handle->nb_efd - 1)
4312                         vec++;
4313         }
4314
4315         switch (hw->mac.type) {
4316         case ixgbe_mac_82598EB:
4317                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4318                                    intr_handle->max_intr - 1);
4319                 break;
4320         case ixgbe_mac_82599EB:
4321         case ixgbe_mac_X540:
4322                 ixgbe_set_ivar_map(hw, -1, 1, intr_handle->max_intr - 1);
4323                 break;
4324         default:
4325                 break;
4326         }
4327         IXGBE_WRITE_REG(hw, IXGBE_EITR(queue_id),
4328                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4329
4330         /* set up to autoclear timer, and the vectors */
4331         mask = IXGBE_EIMS_ENABLE_MASK;
4332         mask &= ~(IXGBE_EIMS_OTHER |
4333                   IXGBE_EIMS_MAILBOX |
4334                   IXGBE_EIMS_LSC);
4335
4336         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4337 }
4338
4339 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4340         uint16_t queue_idx, uint16_t tx_rate)
4341 {
4342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4343         uint32_t rf_dec, rf_int;
4344         uint32_t bcnrc_val;
4345         uint16_t link_speed = dev->data->dev_link.link_speed;
4346
4347         if (queue_idx >= hw->mac.max_tx_queues)
4348                 return -EINVAL;
4349
4350         if (tx_rate != 0) {
4351                 /* Calculate the rate factor values to set */
4352                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4353                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4354                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4355
4356                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4357                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4358                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4359                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4360         } else {
4361                 bcnrc_val = 0;
4362         }
4363
4364         /*
4365          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4366          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4367          * set as 0x4.
4368          */
4369         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4370                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4371                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4372                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4373                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4374         else
4375                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4376                         IXGBE_MMW_SIZE_DEFAULT);
4377
4378         /* Set RTTBCNRC of queue X */
4379         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4380         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4381         IXGBE_WRITE_FLUSH(hw);
4382
4383         return 0;
4384 }
4385
4386 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4387         uint16_t tx_rate, uint64_t q_msk)
4388 {
4389         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4390         struct ixgbe_vf_info *vfinfo =
4391                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4392         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4393         uint32_t queue_stride =
4394                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4395         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4396         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4397         uint16_t total_rate = 0;
4398
4399         if (queue_end >= hw->mac.max_tx_queues)
4400                 return -EINVAL;
4401
4402         if (vfinfo != NULL) {
4403                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4404                         if (vf_idx == vf)
4405                                 continue;
4406                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4407                                 idx++)
4408                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4409                 }
4410         } else
4411                 return -EINVAL;
4412
4413         /* Store tx_rate for this vf. */
4414         for (idx = 0; idx < nb_q_per_pool; idx++) {
4415                 if (((uint64_t)0x1 << idx) & q_msk) {
4416                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4417                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4418                         total_rate += tx_rate;
4419                 }
4420         }
4421
4422         if (total_rate > dev->data->dev_link.link_speed) {
4423                 /*
4424                  * Reset stored TX rate of the VF if it causes exceed
4425                  * link speed.
4426                  */
4427                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4428                 return -EINVAL;
4429         }
4430
4431         /* Set RTTBCNRC of each queue/pool for vf X  */
4432         for (; queue_idx <= queue_end; queue_idx++) {
4433                 if (0x1 & q_msk)
4434                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4435                 q_msk = q_msk >> 1;
4436         }
4437
4438         return 0;
4439 }
4440
4441 static void
4442 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4443                      __attribute__((unused)) uint32_t index,
4444                      __attribute__((unused)) uint32_t pool)
4445 {
4446         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447         int diag;
4448
4449         /*
4450          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4451          * operation. Trap this case to avoid exhausting the [very limited]
4452          * set of PF resources used to store VF MAC addresses.
4453          */
4454         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4455                 return;
4456         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4457         if (diag == 0)
4458                 return;
4459         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4460 }
4461
4462 static void
4463 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4464 {
4465         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4467         struct ether_addr *mac_addr;
4468         uint32_t i;
4469         int diag;
4470
4471         /*
4472          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4473          * not support the deletion of a given MAC address.
4474          * Instead, it imposes to delete all MAC addresses, then to add again
4475          * all MAC addresses with the exception of the one to be deleted.
4476          */
4477         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4478
4479         /*
4480          * Add again all MAC addresses, with the exception of the deleted one
4481          * and of the permanent MAC address.
4482          */
4483         for (i = 0, mac_addr = dev->data->mac_addrs;
4484              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4485                 /* Skip the deleted MAC address */
4486                 if (i == index)
4487                         continue;
4488                 /* Skip NULL MAC addresses */
4489                 if (is_zero_ether_addr(mac_addr))
4490                         continue;
4491                 /* Skip the permanent MAC address */
4492                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4493                         continue;
4494                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4495                 if (diag != 0)
4496                         PMD_DRV_LOG(ERR,
4497                                     "Adding again MAC address "
4498                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4499                                     "diag=%d",
4500                                     mac_addr->addr_bytes[0],
4501                                     mac_addr->addr_bytes[1],
4502                                     mac_addr->addr_bytes[2],
4503                                     mac_addr->addr_bytes[3],
4504                                     mac_addr->addr_bytes[4],
4505                                     mac_addr->addr_bytes[5],
4506                                     diag);
4507         }
4508 }
4509
4510 static void
4511 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4512 {
4513         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514
4515         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4516 }
4517
4518 #define MAC_TYPE_FILTER_SUP(type)    do {\
4519         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4520                 (type) != ixgbe_mac_X550)\
4521                 return -ENOTSUP;\
4522 } while (0)
4523
4524 static int
4525 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4526                         struct rte_eth_syn_filter *filter,
4527                         bool add)
4528 {
4529         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4530         uint32_t synqf;
4531
4532         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4533                 return -EINVAL;
4534
4535         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4536
4537         if (add) {
4538                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4539                         return -EINVAL;
4540                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4541                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4542
4543                 if (filter->hig_pri)
4544                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4545                 else
4546                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4547         } else {
4548                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4549                         return -ENOENT;
4550                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4551         }
4552         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4553         IXGBE_WRITE_FLUSH(hw);
4554         return 0;
4555 }
4556
4557 static int
4558 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4559                         struct rte_eth_syn_filter *filter)
4560 {
4561         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4562         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4563
4564         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4565                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4566                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4567                 return 0;
4568         }
4569         return -ENOENT;
4570 }
4571
4572 static int
4573 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4574                         enum rte_filter_op filter_op,
4575                         void *arg)
4576 {
4577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578         int ret;
4579
4580         MAC_TYPE_FILTER_SUP(hw->mac.type);
4581
4582         if (filter_op == RTE_ETH_FILTER_NOP)
4583                 return 0;
4584
4585         if (arg == NULL) {
4586                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4587                             filter_op);
4588                 return -EINVAL;
4589         }
4590
4591         switch (filter_op) {
4592         case RTE_ETH_FILTER_ADD:
4593                 ret = ixgbe_syn_filter_set(dev,
4594                                 (struct rte_eth_syn_filter *)arg,
4595                                 TRUE);
4596                 break;
4597         case RTE_ETH_FILTER_DELETE:
4598                 ret = ixgbe_syn_filter_set(dev,
4599                                 (struct rte_eth_syn_filter *)arg,
4600                                 FALSE);
4601                 break;
4602         case RTE_ETH_FILTER_GET:
4603                 ret = ixgbe_syn_filter_get(dev,
4604                                 (struct rte_eth_syn_filter *)arg);
4605                 break;
4606         default:
4607                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4608                 ret = -EINVAL;
4609                 break;
4610         }
4611
4612         return ret;
4613 }
4614
4615
4616 static inline enum ixgbe_5tuple_protocol
4617 convert_protocol_type(uint8_t protocol_value)
4618 {
4619         if (protocol_value == IPPROTO_TCP)
4620                 return IXGBE_FILTER_PROTOCOL_TCP;
4621         else if (protocol_value == IPPROTO_UDP)
4622                 return IXGBE_FILTER_PROTOCOL_UDP;
4623         else if (protocol_value == IPPROTO_SCTP)
4624                 return IXGBE_FILTER_PROTOCOL_SCTP;
4625         else
4626                 return IXGBE_FILTER_PROTOCOL_NONE;
4627 }
4628
4629 /*
4630  * add a 5tuple filter
4631  *
4632  * @param
4633  * dev: Pointer to struct rte_eth_dev.
4634  * index: the index the filter allocates.
4635  * filter: ponter to the filter that will be added.
4636  * rx_queue: the queue id the filter assigned to.
4637  *
4638  * @return
4639  *    - On success, zero.
4640  *    - On failure, a negative value.
4641  */
4642 static int
4643 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
4644                         struct ixgbe_5tuple_filter *filter)
4645 {
4646         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4647         struct ixgbe_filter_info *filter_info =
4648                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4649         int i, idx, shift;
4650         uint32_t ftqf, sdpqf;
4651         uint32_t l34timir = 0;
4652         uint8_t mask = 0xff;
4653
4654         /*
4655          * look for an unused 5tuple filter index,
4656          * and insert the filter to list.
4657          */
4658         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
4659                 idx = i / (sizeof(uint32_t) * NBBY);
4660                 shift = i % (sizeof(uint32_t) * NBBY);
4661                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
4662                         filter_info->fivetuple_mask[idx] |= 1 << shift;
4663                         filter->index = i;
4664                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
4665                                           filter,
4666                                           entries);
4667                         break;
4668                 }
4669         }
4670         if (i >= IXGBE_MAX_FTQF_FILTERS) {
4671                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
4672                 return -ENOSYS;
4673         }
4674
4675         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
4676                                 IXGBE_SDPQF_DSTPORT_SHIFT);
4677         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
4678
4679         ftqf = (uint32_t)(filter->filter_info.proto &
4680                 IXGBE_FTQF_PROTOCOL_MASK);
4681         ftqf |= (uint32_t)((filter->filter_info.priority &
4682                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
4683         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
4684                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
4685         if (filter->filter_info.dst_ip_mask == 0)
4686                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
4687         if (filter->filter_info.src_port_mask == 0)
4688                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
4689         if (filter->filter_info.dst_port_mask == 0)
4690                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
4691         if (filter->filter_info.proto_mask == 0)
4692                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
4693         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
4694         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
4695         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
4696
4697         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
4698         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
4699         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
4700         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
4701
4702         l34timir |= IXGBE_L34T_IMIR_RESERVE;
4703         l34timir |= (uint32_t)(filter->queue <<
4704                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
4705         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
4706         return 0;
4707 }
4708
4709 /*
4710  * remove a 5tuple filter
4711  *
4712  * @param
4713  * dev: Pointer to struct rte_eth_dev.
4714  * filter: the pointer of the filter will be removed.
4715  */
4716 static void
4717 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
4718                         struct ixgbe_5tuple_filter *filter)
4719 {
4720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         struct ixgbe_filter_info *filter_info =
4722                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4723         uint16_t index = filter->index;
4724
4725         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
4726                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
4727         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
4728         rte_free(filter);
4729
4730         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4731         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4732         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4733         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4734         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4735 }
4736
4737 static int
4738 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4739 {
4740         struct ixgbe_hw *hw;
4741         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4742
4743         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4744
4745         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4746                 return -EINVAL;
4747
4748         /* refuse mtu that requires the support of scattered packets when this
4749          * feature has not been enabled before. */
4750         if (!dev->data->scattered_rx &&
4751             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4752              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4753                 return -EINVAL;
4754
4755         /*
4756          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4757          * request of the version 2.0 of the mailbox API.
4758          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4759          * of the mailbox API.
4760          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4761          * prior to 3.11.33 which contains the following change:
4762          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4763          */
4764         ixgbevf_rlpml_set_vf(hw, max_frame);
4765
4766         /* update max frame size */
4767         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4768         return 0;
4769 }
4770
4771 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4772         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4773                 return -ENOTSUP;\
4774 } while (0)
4775
4776 static inline struct ixgbe_5tuple_filter *
4777 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4778                         struct ixgbe_5tuple_filter_info *key)
4779 {
4780         struct ixgbe_5tuple_filter *it;
4781
4782         TAILQ_FOREACH(it, filter_list, entries) {
4783                 if (memcmp(key, &it->filter_info,
4784                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4785                         return it;
4786                 }
4787         }
4788         return NULL;
4789 }
4790
4791 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4792 static inline int
4793 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4794                         struct ixgbe_5tuple_filter_info *filter_info)
4795 {
4796         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4797                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4798                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4799                 return -EINVAL;
4800
4801         switch (filter->dst_ip_mask) {
4802         case UINT32_MAX:
4803                 filter_info->dst_ip_mask = 0;
4804                 filter_info->dst_ip = filter->dst_ip;
4805                 break;
4806         case 0:
4807                 filter_info->dst_ip_mask = 1;
4808                 break;
4809         default:
4810                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4811                 return -EINVAL;
4812         }
4813
4814         switch (filter->src_ip_mask) {
4815         case UINT32_MAX:
4816                 filter_info->src_ip_mask = 0;
4817                 filter_info->src_ip = filter->src_ip;
4818                 break;
4819         case 0:
4820                 filter_info->src_ip_mask = 1;
4821                 break;
4822         default:
4823                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4824                 return -EINVAL;
4825         }
4826
4827         switch (filter->dst_port_mask) {
4828         case UINT16_MAX:
4829                 filter_info->dst_port_mask = 0;
4830                 filter_info->dst_port = filter->dst_port;
4831                 break;
4832         case 0:
4833                 filter_info->dst_port_mask = 1;
4834                 break;
4835         default:
4836                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4837                 return -EINVAL;
4838         }
4839
4840         switch (filter->src_port_mask) {
4841         case UINT16_MAX:
4842                 filter_info->src_port_mask = 0;
4843                 filter_info->src_port = filter->src_port;
4844                 break;
4845         case 0:
4846                 filter_info->src_port_mask = 1;
4847                 break;
4848         default:
4849                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4850                 return -EINVAL;
4851         }
4852
4853         switch (filter->proto_mask) {
4854         case UINT8_MAX:
4855                 filter_info->proto_mask = 0;
4856                 filter_info->proto =
4857                         convert_protocol_type(filter->proto);
4858                 break;
4859         case 0:
4860                 filter_info->proto_mask = 1;
4861                 break;
4862         default:
4863                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4864                 return -EINVAL;
4865         }
4866
4867         filter_info->priority = (uint8_t)filter->priority;
4868         return 0;
4869 }
4870
4871 /*
4872  * add or delete a ntuple filter
4873  *
4874  * @param
4875  * dev: Pointer to struct rte_eth_dev.
4876  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4877  * add: if true, add filter, if false, remove filter
4878  *
4879  * @return
4880  *    - On success, zero.
4881  *    - On failure, a negative value.
4882  */
4883 static int
4884 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4885                         struct rte_eth_ntuple_filter *ntuple_filter,
4886                         bool add)
4887 {
4888         struct ixgbe_filter_info *filter_info =
4889                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4890         struct ixgbe_5tuple_filter_info filter_5tuple;
4891         struct ixgbe_5tuple_filter *filter;
4892         int ret;
4893
4894         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4895                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4896                 return -EINVAL;
4897         }
4898
4899         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4900         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4901         if (ret < 0)
4902                 return ret;
4903
4904         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4905                                          &filter_5tuple);
4906         if (filter != NULL && add) {
4907                 PMD_DRV_LOG(ERR, "filter exists.");
4908                 return -EEXIST;
4909         }
4910         if (filter == NULL && !add) {
4911                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4912                 return -ENOENT;
4913         }
4914
4915         if (add) {
4916                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4917                                 sizeof(struct ixgbe_5tuple_filter), 0);
4918                 if (filter == NULL)
4919                         return -ENOMEM;
4920                 (void)rte_memcpy(&filter->filter_info,
4921                                  &filter_5tuple,
4922                                  sizeof(struct ixgbe_5tuple_filter_info));
4923                 filter->queue = ntuple_filter->queue;
4924                 ret = ixgbe_add_5tuple_filter(dev, filter);
4925                 if (ret < 0) {
4926                         rte_free(filter);
4927                         return ret;
4928                 }
4929         } else
4930                 ixgbe_remove_5tuple_filter(dev, filter);
4931
4932         return 0;
4933 }
4934
4935 /*
4936  * get a ntuple filter
4937  *
4938  * @param
4939  * dev: Pointer to struct rte_eth_dev.
4940  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4941  *
4942  * @return
4943  *    - On success, zero.
4944  *    - On failure, a negative value.
4945  */
4946 static int
4947 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4948                         struct rte_eth_ntuple_filter *ntuple_filter)
4949 {
4950         struct ixgbe_filter_info *filter_info =
4951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4952         struct ixgbe_5tuple_filter_info filter_5tuple;
4953         struct ixgbe_5tuple_filter *filter;
4954         int ret;
4955
4956         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4957                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4958                 return -EINVAL;
4959         }
4960
4961         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4962         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4963         if (ret < 0)
4964                 return ret;
4965
4966         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4967                                          &filter_5tuple);
4968         if (filter == NULL) {
4969                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4970                 return -ENOENT;
4971         }
4972         ntuple_filter->queue = filter->queue;
4973         return 0;
4974 }
4975
4976 /*
4977  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4978  * @dev: pointer to rte_eth_dev structure
4979  * @filter_op:operation will be taken.
4980  * @arg: a pointer to specific structure corresponding to the filter_op
4981  *
4982  * @return
4983  *    - On success, zero.
4984  *    - On failure, a negative value.
4985  */
4986 static int
4987 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4988                                 enum rte_filter_op filter_op,
4989                                 void *arg)
4990 {
4991         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4992         int ret;
4993
4994         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4995
4996         if (filter_op == RTE_ETH_FILTER_NOP)
4997                 return 0;
4998
4999         if (arg == NULL) {
5000                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5001                             filter_op);
5002                 return -EINVAL;
5003         }
5004
5005         switch (filter_op) {
5006         case RTE_ETH_FILTER_ADD:
5007                 ret = ixgbe_add_del_ntuple_filter(dev,
5008                         (struct rte_eth_ntuple_filter *)arg,
5009                         TRUE);
5010                 break;
5011         case RTE_ETH_FILTER_DELETE:
5012                 ret = ixgbe_add_del_ntuple_filter(dev,
5013                         (struct rte_eth_ntuple_filter *)arg,
5014                         FALSE);
5015                 break;
5016         case RTE_ETH_FILTER_GET:
5017                 ret = ixgbe_get_ntuple_filter(dev,
5018                         (struct rte_eth_ntuple_filter *)arg);
5019                 break;
5020         default:
5021                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5022                 ret = -EINVAL;
5023                 break;
5024         }
5025         return ret;
5026 }
5027
5028 static inline int
5029 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5030                         uint16_t ethertype)
5031 {
5032         int i;
5033
5034         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5035                 if (filter_info->ethertype_filters[i] == ethertype &&
5036                     (filter_info->ethertype_mask & (1 << i)))
5037                         return i;
5038         }
5039         return -1;
5040 }
5041
5042 static inline int
5043 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5044                         uint16_t ethertype)
5045 {
5046         int i;
5047
5048         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5049                 if (!(filter_info->ethertype_mask & (1 << i))) {
5050                         filter_info->ethertype_mask |= 1 << i;
5051                         filter_info->ethertype_filters[i] = ethertype;
5052                         return i;
5053                 }
5054         }
5055         return -1;
5056 }
5057
5058 static inline int
5059 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5060                         uint8_t idx)
5061 {
5062         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5063                 return -1;
5064         filter_info->ethertype_mask &= ~(1 << idx);
5065         filter_info->ethertype_filters[idx] = 0;
5066         return idx;
5067 }
5068
5069 static int
5070 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5071                         struct rte_eth_ethertype_filter *filter,
5072                         bool add)
5073 {
5074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         struct ixgbe_filter_info *filter_info =
5076                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5077         uint32_t etqf = 0;
5078         uint32_t etqs = 0;
5079         int ret;
5080
5081         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5082                 return -EINVAL;
5083
5084         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5085                 filter->ether_type == ETHER_TYPE_IPv6) {
5086                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5087                         " ethertype filter.", filter->ether_type);
5088                 return -EINVAL;
5089         }
5090
5091         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5092                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5093                 return -EINVAL;
5094         }
5095         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5096                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5097                 return -EINVAL;
5098         }
5099
5100         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5101         if (ret >= 0 && add) {
5102                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5103                             filter->ether_type);
5104                 return -EEXIST;
5105         }
5106         if (ret < 0 && !add) {
5107                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5108                             filter->ether_type);
5109                 return -ENOENT;
5110         }
5111
5112         if (add) {
5113                 ret = ixgbe_ethertype_filter_insert(filter_info,
5114                         filter->ether_type);
5115                 if (ret < 0) {
5116                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5117                         return -ENOSYS;
5118                 }
5119                 etqf = IXGBE_ETQF_FILTER_EN;
5120                 etqf |= (uint32_t)filter->ether_type;
5121                 etqs |= (uint32_t)((filter->queue <<
5122                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5123                                     IXGBE_ETQS_RX_QUEUE);
5124                 etqs |= IXGBE_ETQS_QUEUE_EN;
5125         } else {
5126                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5127                 if (ret < 0)
5128                         return -ENOSYS;
5129         }
5130         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5131         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5132         IXGBE_WRITE_FLUSH(hw);
5133
5134         return 0;
5135 }
5136
5137 static int
5138 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5139                         struct rte_eth_ethertype_filter *filter)
5140 {
5141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5142         struct ixgbe_filter_info *filter_info =
5143                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5144         uint32_t etqf, etqs;
5145         int ret;
5146
5147         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5148         if (ret < 0) {
5149                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5150                             filter->ether_type);
5151                 return -ENOENT;
5152         }
5153
5154         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5155         if (etqf & IXGBE_ETQF_FILTER_EN) {
5156                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5157                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5158                 filter->flags = 0;
5159                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5160                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5161                 return 0;
5162         }
5163         return -ENOENT;
5164 }
5165
5166 /*
5167  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5168  * @dev: pointer to rte_eth_dev structure
5169  * @filter_op:operation will be taken.
5170  * @arg: a pointer to specific structure corresponding to the filter_op
5171  */
5172 static int
5173 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5174                                 enum rte_filter_op filter_op,
5175                                 void *arg)
5176 {
5177         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5178         int ret;
5179
5180         MAC_TYPE_FILTER_SUP(hw->mac.type);
5181
5182         if (filter_op == RTE_ETH_FILTER_NOP)
5183                 return 0;
5184
5185         if (arg == NULL) {
5186                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5187                             filter_op);
5188                 return -EINVAL;
5189         }
5190
5191         switch (filter_op) {
5192         case RTE_ETH_FILTER_ADD:
5193                 ret = ixgbe_add_del_ethertype_filter(dev,
5194                         (struct rte_eth_ethertype_filter *)arg,
5195                         TRUE);
5196                 break;
5197         case RTE_ETH_FILTER_DELETE:
5198                 ret = ixgbe_add_del_ethertype_filter(dev,
5199                         (struct rte_eth_ethertype_filter *)arg,
5200                         FALSE);
5201                 break;
5202         case RTE_ETH_FILTER_GET:
5203                 ret = ixgbe_get_ethertype_filter(dev,
5204                         (struct rte_eth_ethertype_filter *)arg);
5205                 break;
5206         default:
5207                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5208                 ret = -EINVAL;
5209                 break;
5210         }
5211         return ret;
5212 }
5213
5214 static int
5215 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5216                      enum rte_filter_type filter_type,
5217                      enum rte_filter_op filter_op,
5218                      void *arg)
5219 {
5220         int ret = -EINVAL;
5221
5222         switch (filter_type) {
5223         case RTE_ETH_FILTER_NTUPLE:
5224                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5225                 break;
5226         case RTE_ETH_FILTER_ETHERTYPE:
5227                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5228                 break;
5229         case RTE_ETH_FILTER_SYN:
5230                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5231                 break;
5232         case RTE_ETH_FILTER_FDIR:
5233                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5234                 break;
5235         default:
5236                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5237                                                         filter_type);
5238                 break;
5239         }
5240
5241         return ret;
5242 }
5243
5244 static u8 *
5245 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5246                         u8 **mc_addr_ptr, u32 *vmdq)
5247 {
5248         u8 *mc_addr;
5249
5250         *vmdq = 0;
5251         mc_addr = *mc_addr_ptr;
5252         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5253         return mc_addr;
5254 }
5255
5256 static int
5257 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5258                           struct ether_addr *mc_addr_set,
5259                           uint32_t nb_mc_addr)
5260 {
5261         struct ixgbe_hw *hw;
5262         u8 *mc_addr_list;
5263
5264         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5265         mc_addr_list = (u8 *)mc_addr_set;
5266         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5267                                          ixgbe_dev_addr_list_itr, TRUE);
5268 }
5269
5270 static int
5271 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5272 {
5273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5274         uint32_t tsync_ctl;
5275         uint32_t tsauxc;
5276
5277         /* Enable system time for platforms where it isn't on by default. */
5278         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5279         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5280         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5281
5282         /* Start incrementing the register used to timestamp PTP packets. */
5283         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5284
5285         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5286         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5287                         (ETHER_TYPE_1588 |
5288                          IXGBE_ETQF_FILTER_EN |
5289                          IXGBE_ETQF_1588));
5290
5291         /* Enable timestamping of received PTP packets. */
5292         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5293         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5294         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5295
5296         /* Enable timestamping of transmitted PTP packets. */
5297         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5298         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5299         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5300
5301         return 0;
5302 }
5303
5304 static int
5305 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5306 {
5307         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5308         uint32_t tsync_ctl;
5309
5310         /* Disable timestamping of transmitted PTP packets. */
5311         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5312         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5313         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5314
5315         /* Disable timestamping of received PTP packets. */
5316         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5317         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5318         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5319
5320         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5321         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5322
5323         /* Stop incrementating the System Time registers. */
5324         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5325
5326         return 0;
5327 }
5328
5329 static int
5330 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5331                                  struct timespec *timestamp,
5332                                  uint32_t flags __rte_unused)
5333 {
5334         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5335         uint32_t tsync_rxctl;
5336         uint32_t rx_stmpl;
5337         uint32_t rx_stmph;
5338
5339         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5340         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5341                 return -EINVAL;
5342
5343         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5344         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5345
5346         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5347         timestamp->tv_nsec = 0;
5348
5349         return  0;
5350 }
5351
5352 static int
5353 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5354                                  struct timespec *timestamp)
5355 {
5356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5357         uint32_t tsync_txctl;
5358         uint32_t tx_stmpl;
5359         uint32_t tx_stmph;
5360
5361         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5362         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5363                 return -EINVAL;
5364
5365         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5366         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5367
5368         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5369         timestamp->tv_nsec = 0;
5370
5371         return  0;
5372 }
5373
5374 static int
5375 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5376 {
5377         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5378         int count = 0;
5379         int g_ind = 0;
5380         const struct reg_info *reg_group;
5381         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5382                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5383
5384         while ((reg_group = reg_set[g_ind++]))
5385                 count += ixgbe_regs_group_count(reg_group);
5386
5387         return count;
5388 }
5389
5390 static int
5391 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5392 {
5393         int count = 0;
5394         int g_ind = 0;
5395         const struct reg_info *reg_group;
5396
5397         while ((reg_group = ixgbevf_regs[g_ind++]))
5398                 count += ixgbe_regs_group_count(reg_group);
5399
5400         return count;
5401 }
5402
5403 static int
5404 ixgbe_get_regs(struct rte_eth_dev *dev,
5405               struct rte_dev_reg_info *regs)
5406 {
5407         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5408         uint32_t *data = regs->data;
5409         int g_ind = 0;
5410         int count = 0;
5411         const struct reg_info *reg_group;
5412         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5413                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5414
5415         /* Support only full register dump */
5416         if ((regs->length == 0) ||
5417             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5418                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5419                         hw->device_id;
5420                 while ((reg_group = reg_set[g_ind++]))
5421                         count += ixgbe_read_regs_group(dev, &data[count],
5422                                 reg_group);
5423                 return 0;
5424         }
5425
5426         return -ENOTSUP;
5427 }
5428
5429 static int
5430 ixgbevf_get_regs(struct rte_eth_dev *dev,
5431                 struct rte_dev_reg_info *regs)
5432 {
5433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5434         uint32_t *data = regs->data;
5435         int g_ind = 0;
5436         int count = 0;
5437         const struct reg_info *reg_group;
5438
5439         /* Support only full register dump */
5440         if ((regs->length == 0) ||
5441             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5442                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5443                         hw->device_id;
5444                 while ((reg_group = ixgbevf_regs[g_ind++]))
5445                         count += ixgbe_read_regs_group(dev, &data[count],
5446                                                       reg_group);
5447                 return 0;
5448         }
5449
5450         return -ENOTSUP;
5451 }
5452
5453 static int
5454 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5455 {
5456         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5457
5458         /* Return unit is byte count */
5459         return hw->eeprom.word_size * 2;
5460 }
5461
5462 static int
5463 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5464                 struct rte_dev_eeprom_info *in_eeprom)
5465 {
5466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5467         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5468         uint16_t *data = in_eeprom->data;
5469         int first, length;
5470
5471         first = in_eeprom->offset >> 1;
5472         length = in_eeprom->length >> 1;
5473         if ((first > hw->eeprom.word_size) ||
5474             ((first + length) > hw->eeprom.word_size))
5475                 return -EINVAL;
5476
5477         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5478
5479         return eeprom->ops.read_buffer(hw, first, length, data);
5480 }
5481
5482 static int
5483 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5484                 struct rte_dev_eeprom_info *in_eeprom)
5485 {
5486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5487         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5488         uint16_t *data = in_eeprom->data;
5489         int first, length;
5490
5491         first = in_eeprom->offset >> 1;
5492         length = in_eeprom->length >> 1;
5493         if ((first > hw->eeprom.word_size) ||
5494             ((first + length) > hw->eeprom.word_size))
5495                 return -EINVAL;
5496
5497         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5498
5499         return eeprom->ops.write_buffer(hw,  first, length, data);
5500 }
5501
5502 uint16_t
5503 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5504         switch (mac_type) {
5505         case ixgbe_mac_X550:
5506         case ixgbe_mac_X550EM_x:
5507                 return ETH_RSS_RETA_SIZE_512;
5508         case ixgbe_mac_X550_vf:
5509         case ixgbe_mac_X550EM_x_vf:
5510                 return ETH_RSS_RETA_SIZE_64;
5511         default:
5512                 return ETH_RSS_RETA_SIZE_128;
5513         }
5514 }
5515
5516 uint32_t
5517 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5518         switch (mac_type) {
5519         case ixgbe_mac_X550:
5520         case ixgbe_mac_X550EM_x:
5521                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5522                         return IXGBE_RETA(reta_idx >> 2);
5523                 else
5524                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5525         case ixgbe_mac_X550_vf:
5526         case ixgbe_mac_X550EM_x_vf:
5527                 return IXGBE_VFRETA(reta_idx >> 2);
5528         default:
5529                 return IXGBE_RETA(reta_idx >> 2);
5530         }
5531 }
5532
5533 uint32_t
5534 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5535         switch (mac_type) {
5536         case ixgbe_mac_X550_vf:
5537         case ixgbe_mac_X550EM_x_vf:
5538                 return IXGBE_VFMRQC;
5539         default:
5540                 return IXGBE_MRQC;
5541         }
5542 }
5543
5544 uint32_t
5545 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5546         switch (mac_type) {
5547         case ixgbe_mac_X550_vf:
5548         case ixgbe_mac_X550EM_x_vf:
5549                 return IXGBE_VFRSSRK(i);
5550         default:
5551                 return IXGBE_RSSRK(i);
5552         }
5553 }
5554
5555 bool
5556 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5557         switch (mac_type) {
5558         case ixgbe_mac_82599_vf:
5559         case ixgbe_mac_X540_vf:
5560                 return 0;
5561         default:
5562                 return 1;
5563         }
5564 }
5565
5566
5567 static struct rte_driver rte_ixgbe_driver = {
5568         .type = PMD_PDEV,
5569         .init = rte_ixgbe_pmd_init,
5570 };
5571
5572 static struct rte_driver rte_ixgbevf_driver = {
5573         .type = PMD_PDEV,
5574         .init = rte_ixgbevf_pmd_init,
5575 };
5576
5577 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
5578 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);