drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 #define IXGBE_HKEY_MAX_INDEX 10
 120
 121 /* Additional timesync values. */
 122 #define IXGBE_TIMINCA_16NS_SHIFT 24
 123 #define IXGBE_TIMINCA_INCVALUE   16000000
 124 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 125                                   | IXGBE_TIMINCA_INCVALUE)
 126
 127 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 128 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 129 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 130 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 131 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 132 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 133 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 134 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 135 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 136 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 137 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 138 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 139                                 int wait_to_complete);
 140 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 141                                 struct rte_eth_stats *stats);
 142 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 143 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 144                                              uint16_t queue_id,
 145                                              uint8_t stat_idx,
 146                                              uint8_t is_rx);
 147 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 148                                struct rte_eth_dev_info *dev_info);
 149 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 150                                  struct rte_eth_dev_info *dev_info);
 151 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 152
 153 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 154                 uint16_t vlan_id, int on);
 155 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 156 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 157                 uint16_t queue, bool on);
 158 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 159                 int on);
 160 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 161 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 162 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 163 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 164 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 165
 166 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 167 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 168 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 169                                struct rte_eth_fc_conf *fc_conf);
 170 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 171                                struct rte_eth_fc_conf *fc_conf);
 172 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 173                 struct rte_eth_pfc_conf *pfc_conf);
 174 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 175                         struct rte_eth_rss_reta_entry64 *reta_conf,
 176                         uint16_t reta_size);
 177 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 178                         struct rte_eth_rss_reta_entry64 *reta_conf,
 179                         uint16_t reta_size);
 180 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 181 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 182 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 183 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 184 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 185                 void *param);
 186 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 187 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 188                 uint32_t index, uint32_t pool);
 189 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 190 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 191
 192 /* For Virtual Function support */
 193 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 194 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 195 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 196 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 197 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 198 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 199 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 200                 struct rte_eth_stats *stats);
 201 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 202 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 203                 uint16_t vlan_id, int on);
 204 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 205                 uint16_t queue, int on);
 206 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 207 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 208
 209 /* For Eth VMDQ APIs support */
 210 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 211                 ether_addr* mac_addr,uint8_t on);
 212 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 213 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 214                 uint16_t rx_mask, uint8_t on);
 215 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 216 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 217 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 218                 uint64_t pool_mask,uint8_t vlan_on);
 219 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 220                 struct rte_eth_mirror_conf *mirror_conf,
 221                 uint8_t rule_id, uint8_t on);
 222 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 223                 uint8_t rule_id);
 224
 225 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 226                 uint16_t queue_idx, uint16_t tx_rate);
 227 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 228                 uint16_t tx_rate, uint64_t q_msk);
 229
 230 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 231                                  struct ether_addr *mac_addr,
 232                                  uint32_t index, uint32_t pool);
 233 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 234 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 235                         struct rte_eth_syn_filter *filter,
 236                         bool add);
 237 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 238                         struct rte_eth_syn_filter *filter);
 239 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 240                         enum rte_filter_op filter_op,
 241                         void *arg);
 242 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 243                         struct ixgbe_5tuple_filter *filter);
 244 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 245                         struct ixgbe_5tuple_filter *filter);
 246 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ntuple_filter *filter,
 248                         bool add);
 249 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ntuple_filter *filter);
 254 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 255                         struct rte_eth_ethertype_filter *filter,
 256                         bool add);
 257 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 258                                 enum rte_filter_op filter_op,
 259                                 void *arg);
 260 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 261                         struct rte_eth_ethertype_filter *filter);
 262 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 263                      enum rte_filter_type filter_type,
 264                      enum rte_filter_op filter_op,
 265                      void *arg);
 266 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 267
 268 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 269                                       struct ether_addr *mc_addr_set,
 270                                       uint32_t nb_mc_addr);
 271
 272 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 273 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 274 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 275                                             struct timespec *timestamp,
 276                                             uint32_t flags);
 277 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 278                                             struct timespec *timestamp);
 279
 280 /*
 281  * Define VF Stats MACRO for Non "cleared on read" register
 282  */
 283 #define UPDATE_VF_STAT(reg, last, cur)                          \
 284 {                                                               \
 285         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 286         cur += latest - last;                                   \
 287         last = latest;                                          \
 288 }
 289
 290 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 291 {                                                                \
 292         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 293         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 294         u64 latest = ((new_msb << 32) | new_lsb);                \
 295         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 296         last = latest;                                           \
 297 }
 298
 299 #define IXGBE_SET_HWSTRIP(h, q) do{\
 300                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 301                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 302                 (h)->bitmap[idx] |= 1 << bit;\
 303         }while(0)
 304
 305 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 306                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 307                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 308                 (h)->bitmap[idx] &= ~(1 << bit);\
 309         }while(0)
 310
 311 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 312                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 313                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 314                 (r) = (h)->bitmap[idx] >> bit & 1;\
 315         }while(0)
 316
 317 /*
 318  * The set of PCI devices this driver supports
 319  */
 320 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 321
 322 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 323 #include "rte_pci_dev_ids.h"
 324
 325 { .vendor_id = 0, /* sentinel */ },
 326 };
 327
 328
 329 /*
 330  * The set of PCI devices this driver supports (for 82599 VF)
 331  */
 332 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 333
 334 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 335 #include "rte_pci_dev_ids.h"
 336 { .vendor_id = 0, /* sentinel */ },
 337
 338 };
 339
 340 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 341         .dev_configure        = ixgbe_dev_configure,
 342         .dev_start            = ixgbe_dev_start,
 343         .dev_stop             = ixgbe_dev_stop,
 344         .dev_set_link_up    = ixgbe_dev_set_link_up,
 345         .dev_set_link_down  = ixgbe_dev_set_link_down,
 346         .dev_close            = ixgbe_dev_close,
 347         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 348         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 349         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 350         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 351         .link_update          = ixgbe_dev_link_update,
 352         .stats_get            = ixgbe_dev_stats_get,
 353         .stats_reset          = ixgbe_dev_stats_reset,
 354         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 355         .dev_infos_get        = ixgbe_dev_info_get,
 356         .mtu_set              = ixgbe_dev_mtu_set,
 357         .vlan_filter_set      = ixgbe_vlan_filter_set,
 358         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 359         .vlan_offload_set     = ixgbe_vlan_offload_set,
 360         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 361         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 362         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 363         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 364         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 365         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 366         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 367         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 368         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 369         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 370         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 371         .dev_led_on           = ixgbe_dev_led_on,
 372         .dev_led_off          = ixgbe_dev_led_off,
 373         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 374         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 375         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 376         .mac_addr_add         = ixgbe_add_rar,
 377         .mac_addr_remove      = ixgbe_remove_rar,
 378         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 379         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 380         .mirror_rule_set      = ixgbe_mirror_rule_set,
 381         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 382         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 383         .set_vf_rx            = ixgbe_set_pool_rx,
 384         .set_vf_tx            = ixgbe_set_pool_tx,
 385         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 386         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 387         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 388         .reta_update          = ixgbe_dev_rss_reta_update,
 389         .reta_query           = ixgbe_dev_rss_reta_query,
 390 #ifdef RTE_NIC_BYPASS
 391         .bypass_init          = ixgbe_bypass_init,
 392         .bypass_state_set     = ixgbe_bypass_state_store,
 393         .bypass_state_show    = ixgbe_bypass_state_show,
 394         .bypass_event_set     = ixgbe_bypass_event_store,
 395         .bypass_event_show    = ixgbe_bypass_event_show,
 396         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 397         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 398         .bypass_ver_show      = ixgbe_bypass_ver_show,
 399         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 400 #endif /* RTE_NIC_BYPASS */
 401         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 402         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 403         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 404         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 405         .timesync_enable      = ixgbe_timesync_enable,
 406         .timesync_disable     = ixgbe_timesync_disable,
 407         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 408         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 409 };
 410
 411 /*
 412  * dev_ops for virtual function, bare necessities for basic vf
 413  * operation have been implemented
 414  */
 415 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 416         .dev_configure        = ixgbevf_dev_configure,
 417         .dev_start            = ixgbevf_dev_start,
 418         .dev_stop             = ixgbevf_dev_stop,
 419         .link_update          = ixgbe_dev_link_update,
 420         .stats_get            = ixgbevf_dev_stats_get,
 421         .stats_reset          = ixgbevf_dev_stats_reset,
 422         .dev_close            = ixgbevf_dev_close,
 423         .dev_infos_get        = ixgbevf_dev_info_get,
 424         .mtu_set              = ixgbevf_dev_set_mtu,
 425         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 426         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 427         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 428         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 429         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 430         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 431         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 432         .mac_addr_add         = ixgbevf_add_mac_addr,
 433         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 434         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 435 };
 436
 437 /**
 438  * Atomically reads the link status information from global
 439  * structure rte_eth_dev.
 440  *
 441  * @param dev
 442  *   - Pointer to the structure rte_eth_dev to read from.
 443  *   - Pointer to the buffer to be saved with the link status.
 444  *
 445  * @return
 446  *   - On success, zero.
 447  *   - On failure, negative value.
 448  */
 449 static inline int
 450 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 451                                 struct rte_eth_link *link)
 452 {
 453         struct rte_eth_link *dst = link;
 454         struct rte_eth_link *src = &(dev->data->dev_link);
 455
 456         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 457                                         *(uint64_t *)src) == 0)
 458                 return -1;
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * Atomically writes the link status information into global
 465  * structure rte_eth_dev.
 466  *
 467  * @param dev
 468  *   - Pointer to the structure rte_eth_dev to read from.
 469  *   - Pointer to the buffer to be saved with the link status.
 470  *
 471  * @return
 472  *   - On success, zero.
 473  *   - On failure, negative value.
 474  */
 475 static inline int
 476 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 477                                 struct rte_eth_link *link)
 478 {
 479         struct rte_eth_link *dst = &(dev->data->dev_link);
 480         struct rte_eth_link *src = link;
 481
 482         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 483                                         *(uint64_t *)src) == 0)
 484                 return -1;
 485
 486         return 0;
 487 }
 488
 489 /*
 490  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 491  */
 492 static inline int
 493 ixgbe_is_sfp(struct ixgbe_hw *hw)
 494 {
 495         switch (hw->phy.type) {
 496         case ixgbe_phy_sfp_avago:
 497         case ixgbe_phy_sfp_ftl:
 498         case ixgbe_phy_sfp_intel:
 499         case ixgbe_phy_sfp_unknown:
 500         case ixgbe_phy_sfp_passive_tyco:
 501         case ixgbe_phy_sfp_passive_unknown:
 502                 return 1;
 503         default:
 504                 return 0;
 505         }
 506 }
 507
 508 static inline int32_t
 509 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 510 {
 511         uint32_t ctrl_ext;
 512         int32_t status;
 513
 514         status = ixgbe_reset_hw(hw);
 515
 516         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 517         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 518         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 519         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 520         IXGBE_WRITE_FLUSH(hw);
 521
 522         return status;
 523 }
 524
 525 static inline void
 526 ixgbe_enable_intr(struct rte_eth_dev *dev)
 527 {
 528         struct ixgbe_interrupt *intr =
 529                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 530         struct ixgbe_hw *hw =
 531                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 532
 533         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 534         IXGBE_WRITE_FLUSH(hw);
 535 }
 536
 537 /*
 538  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 539  */
 540 static void
 541 ixgbe_disable_intr(struct ixgbe_hw *hw)
 542 {
 543         PMD_INIT_FUNC_TRACE();
 544
 545         if (hw->mac.type == ixgbe_mac_82598EB) {
 546                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 547         } else {
 548                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 549                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 550                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 551         }
 552         IXGBE_WRITE_FLUSH(hw);
 553 }
 554
 555 /*
 556  * This function resets queue statistics mapping registers.
 557  * From Niantic datasheet, Initialization of Statistics section:
 558  * "...if software requires the queue counters, the RQSMR and TQSM registers
 559  * must be re-programmed following a device reset.
 560  */
 561 static void
 562 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 563 {
 564         uint32_t i;
 565
 566         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 567                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 568                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 569         }
 570 }
 571
 572
 573 static int
 574 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 575                                   uint16_t queue_id,
 576                                   uint8_t stat_idx,
 577                                   uint8_t is_rx)
 578 {
 579 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 580 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 581 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 582
 583         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 584         struct ixgbe_stat_mapping_registers *stat_mappings =
 585                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 586         uint32_t qsmr_mask = 0;
 587         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 588         uint32_t q_map;
 589         uint8_t n, offset;
 590
 591         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 592                 (hw->mac.type != ixgbe_mac_X540) &&
 593                 (hw->mac.type != ixgbe_mac_X550) &&
 594                 (hw->mac.type != ixgbe_mac_X550EM_x))
 595                 return -ENOSYS;
 596
 597         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 598                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 599                      queue_id, stat_idx);
 600
 601         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 602         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 603                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 604                 return -EIO;
 605         }
 606         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 607
 608         /* Now clear any previous stat_idx set */
 609         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 610         if (!is_rx)
 611                 stat_mappings->tqsm[n] &= ~clearing_mask;
 612         else
 613                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 614
 615         q_map = (uint32_t)stat_idx;
 616         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 617         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 618         if (!is_rx)
 619                 stat_mappings->tqsm[n] |= qsmr_mask;
 620         else
 621                 stat_mappings->rqsmr[n] |= qsmr_mask;
 622
 623         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 624                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 625                      queue_id, stat_idx);
 626         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 627                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 628
 629         /* Now write the mapping in the appropriate register */
 630         if (is_rx) {
 631                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 632                              stat_mappings->rqsmr[n], n);
 633                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 634         }
 635         else {
 636                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 637                              stat_mappings->tqsm[n], n);
 638                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 639         }
 640         return 0;
 641 }
 642
 643 static void
 644 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 645 {
 646         struct ixgbe_stat_mapping_registers *stat_mappings =
 647                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 648         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 649         int i;
 650
 651         /* write whatever was in stat mapping table to the NIC */
 652         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 653                 /* rx */
 654                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 655
 656                 /* tx */
 657                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 658         }
 659 }
 660
 661 static void
 662 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 663 {
 664         uint8_t i;
 665         struct ixgbe_dcb_tc_config *tc;
 666         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 667
 668         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 669         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 670         for (i = 0; i < dcb_max_tc; i++) {
 671                 tc = &dcb_config->tc_config[i];
 672                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 673                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 674                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 675                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 676                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 677                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 678                 tc->pfc = ixgbe_dcb_pfc_disabled;
 679         }
 680
 681         /* Initialize default user to priority mapping, UPx->TC0 */
 682         tc = &dcb_config->tc_config[0];
 683         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 684         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 685         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 686                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 687                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 688         }
 689         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 690         dcb_config->pfc_mode_enable = false;
 691         dcb_config->vt_mode = true;
 692         dcb_config->round_robin_enable = false;
 693         /* support all DCB capabilities in 82599 */
 694         dcb_config->support.capabilities = 0xFF;
 695
 696         /*we only support 4 Tcs for X540, X550 */
 697         if (hw->mac.type == ixgbe_mac_X540 ||
 698                 hw->mac.type == ixgbe_mac_X550 ||
 699                 hw->mac.type == ixgbe_mac_X550EM_x) {
 700                 dcb_config->num_tcs.pg_tcs = 4;
 701                 dcb_config->num_tcs.pfc_tcs = 4;
 702         }
 703 }
 704
 705 /*
 706  * Ensure that all locks are released before first NVM or PHY access
 707  */
 708 static void
 709 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 710 {
 711         uint16_t mask;
 712
 713         /*
 714          * Phy lock should not fail in this early stage. If this is the case,
 715          * it is due to an improper exit of the application.
 716          * So force the release of the faulty lock. Release of common lock
 717          * is done automatically by swfw_sync function.
 718          */
 719         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 720         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 721                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 722         }
 723         ixgbe_release_swfw_semaphore(hw, mask);
 724
 725         /*
 726          * These ones are more tricky since they are common to all ports; but
 727          * swfw_sync retries last long enough (1s) to be almost sure that if
 728          * lock can not be taken it is due to an improper lock of the
 729          * semaphore.
 730          */
 731         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 732         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 733                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 734         }
 735         ixgbe_release_swfw_semaphore(hw, mask);
 736 }
 737
 738 /*
 739  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 740  * It returns 0 on success.
 741  */
 742 static int
 743 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 744 {
 745         struct rte_pci_device *pci_dev;
 746         struct ixgbe_hw *hw =
 747                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 748         struct ixgbe_vfta * shadow_vfta =
 749                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 750         struct ixgbe_hwstrip *hwstrip =
 751                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 752         struct ixgbe_dcb_config *dcb_config =
 753                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 754         struct ixgbe_filter_info *filter_info =
 755                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 756         uint32_t ctrl_ext;
 757         uint16_t csum;
 758         int diag, i;
 759
 760         PMD_INIT_FUNC_TRACE();
 761
 762         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 763         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 764         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 765
 766         /*
 767          * For secondary processes, we don't initialise any further as primary
 768          * has already done this work. Only check we don't need a different
 769          * RX and TX function.
 770          */
 771         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 772                 struct ixgbe_tx_queue *txq;
 773                 /* TX queue function in primary, set by last queue initialized
 774                  * Tx queue may not initialized by primary process */
 775                 if (eth_dev->data->tx_queues) {
 776                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 777                         ixgbe_set_tx_function(eth_dev, txq);
 778                 } else {
 779                         /* Use default TX function if we get here */
 780                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 781                                            "Using default TX function.");
 782                 }
 783
 784                 ixgbe_set_rx_function(eth_dev);
 785
 786                 return 0;
 787         }
 788         pci_dev = eth_dev->pci_dev;
 789
 790         /* Vendor and Device ID need to be set before init of shared code */
 791         hw->device_id = pci_dev->id.device_id;
 792         hw->vendor_id = pci_dev->id.vendor_id;
 793         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 794         hw->allow_unsupported_sfp = 1;
 795
 796         /* Initialize the shared code (base driver) */
 797 #ifdef RTE_NIC_BYPASS
 798         diag = ixgbe_bypass_init_shared_code(hw);
 799 #else
 800         diag = ixgbe_init_shared_code(hw);
 801 #endif /* RTE_NIC_BYPASS */
 802
 803         if (diag != IXGBE_SUCCESS) {
 804                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 805                 return -EIO;
 806         }
 807
 808         /* pick up the PCI bus settings for reporting later */
 809         ixgbe_get_bus_info(hw);
 810
 811         /* Unlock any pending hardware semaphore */
 812         ixgbe_swfw_lock_reset(hw);
 813
 814         /* Initialize DCB configuration*/
 815         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 816         ixgbe_dcb_init(hw,dcb_config);
 817         /* Get Hardware Flow Control setting */
 818         hw->fc.requested_mode = ixgbe_fc_full;
 819         hw->fc.current_mode = ixgbe_fc_full;
 820         hw->fc.pause_time = IXGBE_FC_PAUSE;
 821         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 822                 hw->fc.low_water[i] = IXGBE_FC_LO;
 823                 hw->fc.high_water[i] = IXGBE_FC_HI;
 824         }
 825         hw->fc.send_xon = 1;
 826
 827         /* Make sure we have a good EEPROM before we read from it */
 828         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 829         if (diag != IXGBE_SUCCESS) {
 830                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 831                 return -EIO;
 832         }
 833
 834 #ifdef RTE_NIC_BYPASS
 835         diag = ixgbe_bypass_init_hw(hw);
 836 #else
 837         diag = ixgbe_init_hw(hw);
 838 #endif /* RTE_NIC_BYPASS */
 839
 840         /*
 841          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 842          * is called too soon after the kernel driver unbinding/binding occurs.
 843          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 844          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 845          * also called. See ixgbe_identify_phy_82599(). The reason for the
 846          * failure is not known, and only occuts when virtualisation features
 847          * are disabled in the bios. A delay of 100ms  was found to be enough by
 848          * trial-and-error, and is doubled to be safe.
 849          */
 850         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 851                 rte_delay_ms(200);
 852                 diag = ixgbe_init_hw(hw);
 853         }
 854
 855         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 856                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 857                     "LOM.  Please be aware there may be issues associated "
 858                     "with your hardware.");
 859                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 860                     "please contact your Intel or hardware representative "
 861                     "who provided you with this hardware.");
 862         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 863                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 864         if (diag) {
 865                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 866                 return -EIO;
 867         }
 868
 869         /* Reset the hw statistics */
 870         ixgbe_dev_stats_reset(eth_dev);
 871
 872         /* disable interrupt */
 873         ixgbe_disable_intr(hw);
 874
 875         /* reset mappings for queue statistics hw counters*/
 876         ixgbe_reset_qstat_mappings(hw);
 877
 878         /* Allocate memory for storing MAC addresses */
 879         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 880                         hw->mac.num_rar_entries, 0);
 881         if (eth_dev->data->mac_addrs == NULL) {
 882                 PMD_INIT_LOG(ERR,
 883                         "Failed to allocate %u bytes needed to store "
 884                         "MAC addresses",
 885                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 886                 return -ENOMEM;
 887         }
 888         /* Copy the permanent MAC address */
 889         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 890                         &eth_dev->data->mac_addrs[0]);
 891
 892         /* Allocate memory for storing hash filter MAC addresses */
 893         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 894                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 895         if (eth_dev->data->hash_mac_addrs == NULL) {
 896                 PMD_INIT_LOG(ERR,
 897                         "Failed to allocate %d bytes needed to store MAC addresses",
 898                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 899                 return -ENOMEM;
 900         }
 901
 902         /* initialize the vfta */
 903         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 904
 905         /* initialize the hw strip bitmap*/
 906         memset(hwstrip, 0, sizeof(*hwstrip));
 907
 908         /* initialize PF if max_vfs not zero */
 909         ixgbe_pf_host_init(eth_dev);
 910
 911         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 912         /* let hardware know driver is loaded */
 913         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 914         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 915         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 916         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 917         IXGBE_WRITE_FLUSH(hw);
 918
 919         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 920                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 921                              (int) hw->mac.type, (int) hw->phy.type,
 922                              (int) hw->phy.sfp_type);
 923         else
 924                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 925                              (int) hw->mac.type, (int) hw->phy.type);
 926
 927         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 928                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 929                         pci_dev->id.device_id);
 930
 931         rte_intr_callback_register(&(pci_dev->intr_handle),
 932                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 933
 934         /* enable uio intr after callback register */
 935         rte_intr_enable(&(pci_dev->intr_handle));
 936
 937         /* enable support intr */
 938         ixgbe_enable_intr(eth_dev);
 939
 940         /* initialize 5tuple filter list */
 941         TAILQ_INIT(&filter_info->fivetuple_list);
 942         memset(filter_info->fivetuple_mask, 0,
 943                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 944
 945         return 0;
 946 }
 947
 948
 949 /*
 950  * Negotiate mailbox API version with the PF.
 951  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 952  * Then we try to negotiate starting with the most recent one.
 953  * If all negotiation attempts fail, then we will proceed with
 954  * the default one (ixgbe_mbox_api_10).
 955  */
 956 static void
 957 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 958 {
 959         int32_t i;
 960
 961         /* start with highest supported, proceed down */
 962         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 963                 ixgbe_mbox_api_11,
 964                 ixgbe_mbox_api_10,
 965         };
 966
 967         for (i = 0;
 968                         i != RTE_DIM(sup_ver) &&
 969                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 970                         i++)
 971                 ;
 972 }
 973
 974 static void
 975 generate_random_mac_addr(struct ether_addr *mac_addr)
 976 {
 977         uint64_t random;
 978
 979         /* Set Organizationally Unique Identifier (OUI) prefix. */
 980         mac_addr->addr_bytes[0] = 0x00;
 981         mac_addr->addr_bytes[1] = 0x09;
 982         mac_addr->addr_bytes[2] = 0xC0;
 983         /* Force indication of locally assigned MAC address. */
 984         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 985         /* Generate the last 3 bytes of the MAC address with a random number. */
 986         random = rte_rand();
 987         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 988 }
 989
 990 /*
 991  * Virtual Function device init
 992  */
 993 static int
 994 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 995 {
 996         int diag;
 997         uint32_t tc, tcs;
 998         struct rte_pci_device *pci_dev;
 999         struct ixgbe_hw *hw =
1000                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1001         struct ixgbe_vfta * shadow_vfta =
1002                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1003         struct ixgbe_hwstrip *hwstrip =
1004                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1005         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1006
1007         PMD_INIT_FUNC_TRACE();
1008
1009         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1010         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1011         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1012
1013         /* for secondary processes, we don't initialise any further as primary
1014          * has already done this work. Only check we don't need a different
1015          * RX function */
1016         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1017                 if (eth_dev->data->scattered_rx)
1018                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1019                 return 0;
1020         }
1021
1022         pci_dev = eth_dev->pci_dev;
1023
1024         hw->device_id = pci_dev->id.device_id;
1025         hw->vendor_id = pci_dev->id.vendor_id;
1026         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1027
1028         /* initialize the vfta */
1029         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1030
1031         /* initialize the hw strip bitmap*/
1032         memset(hwstrip, 0, sizeof(*hwstrip));
1033
1034         /* Initialize the shared code (base driver) */
1035         diag = ixgbe_init_shared_code(hw);
1036         if (diag != IXGBE_SUCCESS) {
1037                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1038                 return -EIO;
1039         }
1040
1041         /* init_mailbox_params */
1042         hw->mbx.ops.init_params(hw);
1043
1044         /* Reset the hw statistics */
1045         ixgbevf_dev_stats_reset(eth_dev);
1046
1047         /* Disable the interrupts for VF */
1048         ixgbevf_intr_disable(hw);
1049
1050         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1051         diag = hw->mac.ops.reset_hw(hw);
1052
1053         /*
1054          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1055          * the underlying PF driver has not assigned a MAC address to the VF.
1056          * In this case, assign a random MAC address.
1057          */
1058         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1059                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1060                 return (diag);
1061         }
1062
1063         /* negotiate mailbox API version to use with the PF. */
1064         ixgbevf_negotiate_api(hw);
1065
1066         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1067         ixgbevf_get_queues(hw, &tcs, &tc);
1068
1069         /* Allocate memory for storing MAC addresses */
1070         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1071                         hw->mac.num_rar_entries, 0);
1072         if (eth_dev->data->mac_addrs == NULL) {
1073                 PMD_INIT_LOG(ERR,
1074                         "Failed to allocate %u bytes needed to store "
1075                         "MAC addresses",
1076                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1077                 return -ENOMEM;
1078         }
1079
1080         /* Generate a random MAC address, if none was assigned by PF. */
1081         if (is_zero_ether_addr(perm_addr)) {
1082                 generate_random_mac_addr(perm_addr);
1083                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1084                 if (diag) {
1085                         rte_free(eth_dev->data->mac_addrs);
1086                         eth_dev->data->mac_addrs = NULL;
1087                         return diag;
1088                 }
1089                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1090                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1091                              "%02x:%02x:%02x:%02x:%02x:%02x",
1092                              perm_addr->addr_bytes[0],
1093                              perm_addr->addr_bytes[1],
1094                              perm_addr->addr_bytes[2],
1095                              perm_addr->addr_bytes[3],
1096                              perm_addr->addr_bytes[4],
1097                              perm_addr->addr_bytes[5]);
1098         }
1099
1100         /* Copy the permanent MAC address */
1101         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1102
1103         /* reset the hardware with the new settings */
1104         diag = hw->mac.ops.start_hw(hw);
1105         switch (diag) {
1106                 case  0:
1107                         break;
1108
1109                 default:
1110                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1111                         return (-EIO);
1112         }
1113
1114         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1115                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1116                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1117
1118         return 0;
1119 }
1120
1121 static struct eth_driver rte_ixgbe_pmd = {
1122         .pci_drv = {
1123                 .name = "rte_ixgbe_pmd",
1124                 .id_table = pci_id_ixgbe_map,
1125                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1126         },
1127         .eth_dev_init = eth_ixgbe_dev_init,
1128         .dev_private_size = sizeof(struct ixgbe_adapter),
1129 };
1130
1131 /*
1132  * virtual function driver struct
1133  */
1134 static struct eth_driver rte_ixgbevf_pmd = {
1135         .pci_drv = {
1136                 .name = "rte_ixgbevf_pmd",
1137                 .id_table = pci_id_ixgbevf_map,
1138                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1139         },
1140         .eth_dev_init = eth_ixgbevf_dev_init,
1141         .dev_private_size = sizeof(struct ixgbe_adapter),
1142 };
1143
1144 /*
1145  * Driver initialization routine.
1146  * Invoked once at EAL init time.
1147  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1148  */
1149 static int
1150 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1151 {
1152         PMD_INIT_FUNC_TRACE();
1153
1154         rte_eth_driver_register(&rte_ixgbe_pmd);
1155         return 0;
1156 }
1157
1158 /*
1159  * VF Driver initialization routine.
1160  * Invoked one at EAL init time.
1161  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1162  */
1163 static int
1164 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1165 {
1166         PMD_INIT_FUNC_TRACE();
1167
1168         rte_eth_driver_register(&rte_ixgbevf_pmd);
1169         return (0);
1170 }
1171
1172 static int
1173 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1174 {
1175         struct ixgbe_hw *hw =
1176                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1177         struct ixgbe_vfta * shadow_vfta =
1178                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1179         uint32_t vfta;
1180         uint32_t vid_idx;
1181         uint32_t vid_bit;
1182
1183         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1184         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1185         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1186         if (on)
1187                 vfta |= vid_bit;
1188         else
1189                 vfta &= ~vid_bit;
1190         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1191
1192         /* update local VFTA copy */
1193         shadow_vfta->vfta[vid_idx] = vfta;
1194
1195         return 0;
1196 }
1197
1198 static void
1199 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1200 {
1201         if (on)
1202                 ixgbe_vlan_hw_strip_enable(dev, queue);
1203         else
1204                 ixgbe_vlan_hw_strip_disable(dev, queue);
1205 }
1206
1207 static void
1208 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1209 {
1210         struct ixgbe_hw *hw =
1211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212
1213         /* Only the high 16-bits is valid */
1214         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1215 }
1216
1217 void
1218 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1219 {
1220         struct ixgbe_hw *hw =
1221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1222         uint32_t vlnctrl;
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         /* Filter Table Disable */
1227         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1228         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1229
1230         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1231 }
1232
1233 void
1234 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1235 {
1236         struct ixgbe_hw *hw =
1237                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1238         struct ixgbe_vfta * shadow_vfta =
1239                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1240         uint32_t vlnctrl;
1241         uint16_t i;
1242
1243         PMD_INIT_FUNC_TRACE();
1244
1245         /* Filter Table Enable */
1246         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1247         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1248         vlnctrl |= IXGBE_VLNCTRL_VFE;
1249
1250         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1251
1252         /* write whatever is in local vfta copy */
1253         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1254                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1255 }
1256
1257 static void
1258 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1259 {
1260         struct ixgbe_hwstrip *hwstrip =
1261                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1262
1263         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1264                 return;
1265
1266         if (on)
1267                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1268         else
1269                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1270 }
1271
1272 static void
1273 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1274 {
1275         struct ixgbe_hw *hw =
1276                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277         uint32_t ctrl;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         if (hw->mac.type == ixgbe_mac_82598EB) {
1282                 /* No queue level support */
1283                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1284                 return;
1285         }
1286         else {
1287                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1288                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1289                 ctrl &= ~IXGBE_RXDCTL_VME;
1290                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1291         }
1292         /* record those setting for HW strip per queue */
1293         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1294 }
1295
1296 static void
1297 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1298 {
1299         struct ixgbe_hw *hw =
1300                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1301         uint32_t ctrl;
1302
1303         PMD_INIT_FUNC_TRACE();
1304
1305         if (hw->mac.type == ixgbe_mac_82598EB) {
1306                 /* No queue level supported */
1307                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1308                 return;
1309         }
1310         else {
1311                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1312                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1313                 ctrl |= IXGBE_RXDCTL_VME;
1314                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1315         }
1316         /* record those setting for HW strip per queue */
1317         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1318 }
1319
1320 void
1321 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1322 {
1323         struct ixgbe_hw *hw =
1324                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1325         uint32_t ctrl;
1326         uint16_t i;
1327
1328         PMD_INIT_FUNC_TRACE();
1329
1330         if (hw->mac.type == ixgbe_mac_82598EB) {
1331                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1332                 ctrl &= ~IXGBE_VLNCTRL_VME;
1333                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1334         }
1335         else {
1336                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1337                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1338                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1339                         ctrl &= ~IXGBE_RXDCTL_VME;
1340                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1341
1342                         /* record those setting for HW strip per queue */
1343                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1344                 }
1345         }
1346 }
1347
1348 void
1349 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1350 {
1351         struct ixgbe_hw *hw =
1352                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1353         uint32_t ctrl;
1354         uint16_t i;
1355
1356         PMD_INIT_FUNC_TRACE();
1357
1358         if (hw->mac.type == ixgbe_mac_82598EB) {
1359                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1360                 ctrl |= IXGBE_VLNCTRL_VME;
1361                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1362         }
1363         else {
1364                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1365                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1366                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1367                         ctrl |= IXGBE_RXDCTL_VME;
1368                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1369
1370                         /* record those setting for HW strip per queue */
1371                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1372                 }
1373         }
1374 }
1375
1376 static void
1377 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1378 {
1379         struct ixgbe_hw *hw =
1380                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1381         uint32_t ctrl;
1382
1383         PMD_INIT_FUNC_TRACE();
1384
1385         /* DMATXCTRL: Geric Double VLAN Disable */
1386         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1387         ctrl &= ~IXGBE_DMATXCTL_GDV;
1388         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1389
1390         /* CTRL_EXT: Global Double VLAN Disable */
1391         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1392         ctrl &= ~IXGBE_EXTENDED_VLAN;
1393         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1394
1395 }
1396
1397 static void
1398 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1399 {
1400         struct ixgbe_hw *hw =
1401                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1402         uint32_t ctrl;
1403
1404         PMD_INIT_FUNC_TRACE();
1405
1406         /* DMATXCTRL: Geric Double VLAN Enable */
1407         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1408         ctrl |= IXGBE_DMATXCTL_GDV;
1409         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1410
1411         /* CTRL_EXT: Global Double VLAN Enable */
1412         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1413         ctrl |= IXGBE_EXTENDED_VLAN;
1414         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1415
1416         /*
1417          * VET EXT field in the EXVET register = 0x8100 by default
1418          * So no need to change. Same to VT field of DMATXCTL register
1419          */
1420 }
1421
1422 static void
1423 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1424 {
1425         if(mask & ETH_VLAN_STRIP_MASK){
1426                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1427                         ixgbe_vlan_hw_strip_enable_all(dev);
1428                 else
1429                         ixgbe_vlan_hw_strip_disable_all(dev);
1430         }
1431
1432         if(mask & ETH_VLAN_FILTER_MASK){
1433                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1434                         ixgbe_vlan_hw_filter_enable(dev);
1435                 else
1436                         ixgbe_vlan_hw_filter_disable(dev);
1437         }
1438
1439         if(mask & ETH_VLAN_EXTEND_MASK){
1440                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1441                         ixgbe_vlan_hw_extend_enable(dev);
1442                 else
1443                         ixgbe_vlan_hw_extend_disable(dev);
1444         }
1445 }
1446
1447 static void
1448 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1449 {
1450         struct ixgbe_hw *hw =
1451                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1452         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1453         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1454         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1455         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1456 }
1457
1458 static int
1459 ixgbe_dev_configure(struct rte_eth_dev *dev)
1460 {
1461         struct ixgbe_interrupt *intr =
1462                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1463         struct ixgbe_adapter *adapter =
1464                 (struct ixgbe_adapter *)dev->data->dev_private;
1465
1466         PMD_INIT_FUNC_TRACE();
1467
1468         /* set flag to update link status after init */
1469         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1470
1471         /*
1472          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1473          * allocation or vector Rx preconditions we will reset it.
1474          */
1475         adapter->rx_bulk_alloc_allowed = true;
1476         adapter->rx_vec_allowed = true;
1477
1478         return 0;
1479 }
1480
1481 /*
1482  * Configure device link speed and setup link.
1483  * It returns 0 on success.
1484  */
1485 static int
1486 ixgbe_dev_start(struct rte_eth_dev *dev)
1487 {
1488         struct ixgbe_hw *hw =
1489                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490         struct ixgbe_vf_info *vfinfo =
1491                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1492         int err, link_up = 0, negotiate = 0;
1493         uint32_t speed = 0;
1494         int mask = 0;
1495         int status;
1496         uint16_t vf, idx;
1497
1498         PMD_INIT_FUNC_TRACE();
1499
1500         /* IXGBE devices don't support half duplex */
1501         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1502                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1503                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1504                              dev->data->dev_conf.link_duplex,
1505                              dev->data->port_id);
1506                 return -EINVAL;
1507         }
1508
1509         /* stop adapter */
1510         hw->adapter_stopped = FALSE;
1511         ixgbe_stop_adapter(hw);
1512
1513         /* reinitialize adapter
1514          * this calls reset and start */
1515         status = ixgbe_pf_reset_hw(hw);
1516         if (status != 0)
1517                 return -1;
1518         hw->mac.ops.start_hw(hw);
1519         hw->mac.get_link_status = true;
1520
1521         /* configure PF module if SRIOV enabled */
1522         ixgbe_pf_host_configure(dev);
1523
1524         /* initialize transmission unit */
1525         ixgbe_dev_tx_init(dev);
1526
1527         /* This can fail when allocating mbufs for descriptor rings */
1528         err = ixgbe_dev_rx_init(dev);
1529         if (err) {
1530                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1531                 goto error;
1532         }
1533
1534         err = ixgbe_dev_rxtx_start(dev);
1535         if (err < 0) {
1536                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1537                 goto error;
1538         }
1539
1540         /* Skip link setup if loopback mode is enabled for 82599. */
1541         if (hw->mac.type == ixgbe_mac_82599EB &&
1542                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1543                 goto skip_link_setup;
1544
1545         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1546                 err = hw->mac.ops.setup_sfp(hw);
1547                 if (err)
1548                         goto error;
1549         }
1550
1551         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1552                 /* Turn on the copper */
1553                 ixgbe_set_phy_power(hw, true);
1554         } else {
1555                 /* Turn on the laser */
1556                 ixgbe_enable_tx_laser(hw);
1557         }
1558
1559         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1560         if (err)
1561                 goto error;
1562         dev->data->dev_link.link_status = link_up;
1563
1564         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1565         if (err)
1566                 goto error;
1567
1568         switch(dev->data->dev_conf.link_speed) {
1569         case ETH_LINK_SPEED_AUTONEG:
1570                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1571                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1572                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1573                 break;
1574         case ETH_LINK_SPEED_100:
1575                 /*
1576                  * Invalid for 82598 but error will be detected by
1577                  * ixgbe_setup_link()
1578                  */
1579                 speed = IXGBE_LINK_SPEED_100_FULL;
1580                 break;
1581         case ETH_LINK_SPEED_1000:
1582                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1583                 break;
1584         case ETH_LINK_SPEED_10000:
1585                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1586                 break;
1587         default:
1588                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1589                              dev->data->dev_conf.link_speed,
1590                              dev->data->port_id);
1591                 goto error;
1592         }
1593
1594         err = ixgbe_setup_link(hw, speed, link_up);
1595         if (err)
1596                 goto error;
1597
1598 skip_link_setup:
1599
1600         /* check if lsc interrupt is enabled */
1601         if (dev->data->dev_conf.intr_conf.lsc != 0)
1602                 ixgbe_dev_lsc_interrupt_setup(dev);
1603
1604         /* resume enabled intr since hw reset */
1605         ixgbe_enable_intr(dev);
1606
1607         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1608                 ETH_VLAN_EXTEND_MASK;
1609         ixgbe_vlan_offload_set(dev, mask);
1610
1611         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1612                 /* Enable vlan filtering for VMDq */
1613                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1614         }
1615
1616         /* Configure DCB hw */
1617         ixgbe_configure_dcb(dev);
1618
1619         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1620                 err = ixgbe_fdir_configure(dev);
1621                 if (err)
1622                         goto error;
1623         }
1624
1625         /* Restore vf rate limit */
1626         if (vfinfo != NULL) {
1627                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1628                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1629                                 if (vfinfo[vf].tx_rate[idx] != 0)
1630                                         ixgbe_set_vf_rate_limit(dev, vf,
1631                                                 vfinfo[vf].tx_rate[idx],
1632                                                 1 << idx);
1633         }
1634
1635         ixgbe_restore_statistics_mapping(dev);
1636
1637         return (0);
1638
1639 error:
1640         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1641         ixgbe_dev_clear_queues(dev);
1642         return -EIO;
1643 }
1644
1645 /*
1646  * Stop device: disable rx and tx functions to allow for reconfiguring.
1647  */
1648 static void
1649 ixgbe_dev_stop(struct rte_eth_dev *dev)
1650 {
1651         struct rte_eth_link link;
1652         struct ixgbe_hw *hw =
1653                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct ixgbe_vf_info *vfinfo =
1655                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1656         struct ixgbe_filter_info *filter_info =
1657                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1658         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1659         int vf;
1660
1661         PMD_INIT_FUNC_TRACE();
1662
1663         /* disable interrupts */
1664         ixgbe_disable_intr(hw);
1665
1666         /* reset the NIC */
1667         ixgbe_pf_reset_hw(hw);
1668         hw->adapter_stopped = FALSE;
1669
1670         /* stop adapter */
1671         ixgbe_stop_adapter(hw);
1672
1673         for (vf = 0; vfinfo != NULL &&
1674                      vf < dev->pci_dev->max_vfs; vf++)
1675                 vfinfo[vf].clear_to_send = false;
1676
1677         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1678                 /* Turn off the copper */
1679                 ixgbe_set_phy_power(hw, false);
1680         } else {
1681                 /* Turn off the laser */
1682                 ixgbe_disable_tx_laser(hw);
1683         }
1684
1685         ixgbe_dev_clear_queues(dev);
1686
1687         /* Clear stored conf */
1688         dev->data->scattered_rx = 0;
1689         dev->data->lro = 0;
1690
1691         /* Clear recorded link status */
1692         memset(&link, 0, sizeof(link));
1693         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1694
1695         /* Remove all ntuple filters of the device */
1696         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1697              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1698                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1699                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1700                              p_5tuple, entries);
1701                 rte_free(p_5tuple);
1702         }
1703         memset(filter_info->fivetuple_mask, 0,
1704                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1705
1706 }
1707
1708 /*
1709  * Set device link up: enable tx.
1710  */
1711 static int
1712 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1713 {
1714         struct ixgbe_hw *hw =
1715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716         if (hw->mac.type == ixgbe_mac_82599EB) {
1717 #ifdef RTE_NIC_BYPASS
1718                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1719                         /* Not suported in bypass mode */
1720                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1721                                      "by device id 0x%x", hw->device_id);
1722                         return -ENOTSUP;
1723                 }
1724 #endif
1725         }
1726
1727         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1728                 /* Turn on the copper */
1729                 ixgbe_set_phy_power(hw, true);
1730         } else {
1731                 /* Turn on the laser */
1732                 ixgbe_enable_tx_laser(hw);
1733         }
1734
1735         return 0;
1736 }
1737
1738 /*
1739  * Set device link down: disable tx.
1740  */
1741 static int
1742 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1743 {
1744         struct ixgbe_hw *hw =
1745                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1746         if (hw->mac.type == ixgbe_mac_82599EB) {
1747 #ifdef RTE_NIC_BYPASS
1748                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1749                         /* Not suported in bypass mode */
1750                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1751                                      "by device id 0x%x", hw->device_id);
1752                         return -ENOTSUP;
1753                 }
1754 #endif
1755         }
1756
1757         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1758                 /* Turn off the copper */
1759                 ixgbe_set_phy_power(hw, false);
1760         } else {
1761                 /* Turn off the laser */
1762                 ixgbe_disable_tx_laser(hw);
1763         }
1764
1765         return 0;
1766 }
1767
1768 /*
1769  * Reest and stop device.
1770  */
1771 static void
1772 ixgbe_dev_close(struct rte_eth_dev *dev)
1773 {
1774         struct ixgbe_hw *hw =
1775                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1776
1777         PMD_INIT_FUNC_TRACE();
1778
1779         ixgbe_pf_reset_hw(hw);
1780
1781         ixgbe_dev_stop(dev);
1782         hw->adapter_stopped = 1;
1783
1784         ixgbe_disable_pcie_master(hw);
1785
1786         /* reprogram the RAR[0] in case user changed it. */
1787         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1788 }
1789
1790 /*
1791  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1792  */
1793 static void
1794 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1795 {
1796         struct ixgbe_hw *hw =
1797                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1798         struct ixgbe_hw_stats *hw_stats =
1799                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1800         uint32_t bprc, lxon, lxoff, total;
1801         uint64_t total_missed_rx, total_qbrc, total_qprc;
1802         unsigned i;
1803
1804         total_missed_rx = 0;
1805         total_qbrc = 0;
1806         total_qprc = 0;
1807
1808         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1809         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1810         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1811         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1812
1813         for (i = 0; i < 8; i++) {
1814                 uint32_t mp;
1815                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1816                 /* global total per queue */
1817                 hw_stats->mpc[i] += mp;
1818                 /* Running comprehensive total for stats display */
1819                 total_missed_rx += hw_stats->mpc[i];
1820                 if (hw->mac.type == ixgbe_mac_82598EB)
1821                         hw_stats->rnbc[i] +=
1822                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1823                 hw_stats->pxontxc[i] +=
1824                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1825                 hw_stats->pxonrxc[i] +=
1826                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1827                 hw_stats->pxofftxc[i] +=
1828                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1829                 hw_stats->pxoffrxc[i] +=
1830                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1831                 hw_stats->pxon2offc[i] +=
1832                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1833         }
1834         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1835                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1836                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1837                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1838                 hw_stats->qbrc[i] +=
1839                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1840                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1841                 hw_stats->qbtc[i] +=
1842                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1843                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1844
1845                 total_qprc += hw_stats->qprc[i];
1846                 total_qbrc += hw_stats->qbrc[i];
1847         }
1848         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1849         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1850         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1851
1852         /* Note that gprc counts missed packets */
1853         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1854
1855         if (hw->mac.type != ixgbe_mac_82598EB) {
1856                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1857                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1858                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1859                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1860                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1861                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1862                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1863                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1864         } else {
1865                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1866                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1867                 /* 82598 only has a counter in the high register */
1868                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1869                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1870                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1871         }
1872
1873         /*
1874          * Workaround: mprc hardware is incorrectly counting
1875          * broadcasts, so for now we subtract those.
1876          */
1877         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1878         hw_stats->bprc += bprc;
1879         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1880         if (hw->mac.type == ixgbe_mac_82598EB)
1881                 hw_stats->mprc -= bprc;
1882
1883         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1884         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1885         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1886         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1887         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1888         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1889
1890         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1891         hw_stats->lxontxc += lxon;
1892         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1893         hw_stats->lxofftxc += lxoff;
1894         total = lxon + lxoff;
1895
1896         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1897         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1898         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1899         hw_stats->gptc -= total;
1900         hw_stats->mptc -= total;
1901         hw_stats->ptc64 -= total;
1902         hw_stats->gotc -= total * ETHER_MIN_LEN;
1903
1904         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1905         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1906         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1907         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1908         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1909         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1910         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1911         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1912         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1913         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1914         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1915         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1916         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1917         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1918         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1919         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1920         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1921         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1922         /* Only read FCOE on 82599 */
1923         if (hw->mac.type != ixgbe_mac_82598EB) {
1924                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1925                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1926                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1927                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1928                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1929         }
1930
1931         if (stats == NULL)
1932                 return;
1933
1934         /* Fill out the rte_eth_stats statistics structure */
1935         stats->ipackets = total_qprc;
1936         stats->ibytes = total_qbrc;
1937         stats->opackets = hw_stats->gptc;
1938         stats->obytes = hw_stats->gotc;
1939         stats->imcasts = hw_stats->mprc;
1940
1941         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1942                 stats->q_ipackets[i] = hw_stats->qprc[i];
1943                 stats->q_opackets[i] = hw_stats->qptc[i];
1944                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1945                 stats->q_obytes[i] = hw_stats->qbtc[i];
1946                 stats->q_errors[i] = hw_stats->qprdc[i];
1947         }
1948
1949         /* Rx Errors */
1950         stats->ibadcrc  = hw_stats->crcerrs;
1951         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1952         stats->imissed  = total_missed_rx;
1953         stats->ierrors  = stats->ibadcrc +
1954                           stats->ibadlen +
1955                           stats->imissed +
1956                           hw_stats->illerrc + hw_stats->errbc;
1957
1958         /* Tx Errors */
1959         stats->oerrors  = 0;
1960
1961         /* XON/XOFF pause frames */
1962         stats->tx_pause_xon  = hw_stats->lxontxc;
1963         stats->rx_pause_xon  = hw_stats->lxonrxc;
1964         stats->tx_pause_xoff = hw_stats->lxofftxc;
1965         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1966
1967         /* Flow Director Stats registers */
1968         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1969         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1970         stats->fdirmatch = hw_stats->fdirmatch;
1971         stats->fdirmiss = hw_stats->fdirmiss;
1972 }
1973
1974 static void
1975 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1976 {
1977         struct ixgbe_hw_stats *stats =
1978                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1979
1980         /* HW registers are cleared on read */
1981         ixgbe_dev_stats_get(dev, NULL);
1982
1983         /* Reset software totals */
1984         memset(stats, 0, sizeof(*stats));
1985 }
1986
1987 static void
1988 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1989 {
1990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1992                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1993
1994         /* Good Rx packet, include VF loopback */
1995         UPDATE_VF_STAT(IXGBE_VFGPRC,
1996             hw_stats->last_vfgprc, hw_stats->vfgprc);
1997
1998         /* Good Rx octets, include VF loopback */
1999         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2000             hw_stats->last_vfgorc, hw_stats->vfgorc);
2001
2002         /* Good Tx packet, include VF loopback */
2003         UPDATE_VF_STAT(IXGBE_VFGPTC,
2004             hw_stats->last_vfgptc, hw_stats->vfgptc);
2005
2006         /* Good Tx octets, include VF loopback */
2007         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2008             hw_stats->last_vfgotc, hw_stats->vfgotc);
2009
2010         /* Rx Multicst Packet */
2011         UPDATE_VF_STAT(IXGBE_VFMPRC,
2012             hw_stats->last_vfmprc, hw_stats->vfmprc);
2013
2014         if (stats == NULL)
2015                 return;
2016
2017         stats->ipackets = hw_stats->vfgprc;
2018         stats->ibytes = hw_stats->vfgorc;
2019         stats->opackets = hw_stats->vfgptc;
2020         stats->obytes = hw_stats->vfgotc;
2021         stats->imcasts = hw_stats->vfmprc;
2022 }
2023
2024 static void
2025 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2028                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2029
2030         /* Sync HW register to the last stats */
2031         ixgbevf_dev_stats_get(dev, NULL);
2032
2033         /* reset HW current stats*/
2034         hw_stats->vfgprc = 0;
2035         hw_stats->vfgorc = 0;
2036         hw_stats->vfgptc = 0;
2037         hw_stats->vfgotc = 0;
2038         hw_stats->vfmprc = 0;
2039
2040 }
2041
2042 static void
2043 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2044 {
2045         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2046
2047         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2048         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2049         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2050         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2051         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2052         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2053         dev_info->max_vfs = dev->pci_dev->max_vfs;
2054         if (hw->mac.type == ixgbe_mac_82598EB)
2055                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2056         else
2057                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2058         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2059         dev_info->rx_offload_capa =
2060                 DEV_RX_OFFLOAD_VLAN_STRIP |
2061                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2062                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2063                 DEV_RX_OFFLOAD_TCP_CKSUM;
2064
2065         /*
2066          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2067          * mode.
2068          */
2069         if ((hw->mac.type == ixgbe_mac_82599EB ||
2070              hw->mac.type == ixgbe_mac_X540) &&
2071             !RTE_ETH_DEV_SRIOV(dev).active)
2072                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2073
2074         dev_info->tx_offload_capa =
2075                 DEV_TX_OFFLOAD_VLAN_INSERT |
2076                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2077                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2078                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2079                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2080                 DEV_TX_OFFLOAD_TCP_TSO;
2081
2082         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2083                 .rx_thresh = {
2084                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2085                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2086                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2087                 },
2088                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2089                 .rx_drop_en = 0,
2090         };
2091
2092         dev_info->default_txconf = (struct rte_eth_txconf) {
2093                 .tx_thresh = {
2094                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2095                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2096                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2097                 },
2098                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2099                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2100                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2101                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2102         };
2103         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2104         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2105         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2106 }
2107
2108 static void
2109 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2110                      struct rte_eth_dev_info *dev_info)
2111 {
2112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2113
2114         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2115         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2116         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2117         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2118         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2119         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2120         dev_info->max_vfs = dev->pci_dev->max_vfs;
2121         if (hw->mac.type == ixgbe_mac_82598EB)
2122                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2123         else
2124                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2125         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2126                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2127                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2128                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2129         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2130                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2131                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2132                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2133                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2134
2135         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2136                 .rx_thresh = {
2137                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2138                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2139                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2140                 },
2141                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2142                 .rx_drop_en = 0,
2143         };
2144
2145         dev_info->default_txconf = (struct rte_eth_txconf) {
2146                 .tx_thresh = {
2147                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2148                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2149                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2150                 },
2151                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2152                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2153                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2154                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2155         };
2156 }
2157
2158 /* return 0 means link status changed, -1 means not changed */
2159 static int
2160 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2161 {
2162         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163         struct rte_eth_link link, old;
2164         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2165         int link_up;
2166         int diag;
2167
2168         link.link_status = 0;
2169         link.link_speed = 0;
2170         link.link_duplex = 0;
2171         memset(&old, 0, sizeof(old));
2172         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2173
2174         hw->mac.get_link_status = true;
2175
2176         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2177         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2178                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2179         else
2180                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2181
2182         if (diag != 0) {
2183                 link.link_speed = ETH_LINK_SPEED_100;
2184                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2185                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2186                 if (link.link_status == old.link_status)
2187                         return -1;
2188                 return 0;
2189         }
2190
2191         if (link_up == 0) {
2192                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2193                 if (link.link_status == old.link_status)
2194                         return -1;
2195                 return 0;
2196         }
2197         link.link_status = 1;
2198         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2199
2200         switch (link_speed) {
2201         default:
2202         case IXGBE_LINK_SPEED_UNKNOWN:
2203                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2204                 link.link_speed = ETH_LINK_SPEED_100;
2205                 break;
2206
2207         case IXGBE_LINK_SPEED_100_FULL:
2208                 link.link_speed = ETH_LINK_SPEED_100;
2209                 break;
2210
2211         case IXGBE_LINK_SPEED_1GB_FULL:
2212                 link.link_speed = ETH_LINK_SPEED_1000;
2213                 break;
2214
2215         case IXGBE_LINK_SPEED_10GB_FULL:
2216                 link.link_speed = ETH_LINK_SPEED_10000;
2217                 break;
2218         }
2219         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2220
2221         if (link.link_status == old.link_status)
2222                 return -1;
2223
2224         return 0;
2225 }
2226
2227 static void
2228 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2229 {
2230         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2231         uint32_t fctrl;
2232
2233         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2234         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2235         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2236 }
2237
2238 static void
2239 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2240 {
2241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2242         uint32_t fctrl;
2243
2244         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2245         fctrl &= (~IXGBE_FCTRL_UPE);
2246         if (dev->data->all_multicast == 1)
2247                 fctrl |= IXGBE_FCTRL_MPE;
2248         else
2249                 fctrl &= (~IXGBE_FCTRL_MPE);
2250         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2251 }
2252
2253 static void
2254 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2255 {
2256         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257         uint32_t fctrl;
2258
2259         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2260         fctrl |= IXGBE_FCTRL_MPE;
2261         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2262 }
2263
2264 static void
2265 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2266 {
2267         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2268         uint32_t fctrl;
2269
2270         if (dev->data->promiscuous == 1)
2271                 return; /* must remain in all_multicast mode */
2272
2273         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2274         fctrl &= (~IXGBE_FCTRL_MPE);
2275         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2276 }
2277
2278 /**
2279  * It clears the interrupt causes and enables the interrupt.
2280  * It will be called once only during nic initialized.
2281  *
2282  * @param dev
2283  *  Pointer to struct rte_eth_dev.
2284  *
2285  * @return
2286  *  - On success, zero.
2287  *  - On failure, a negative value.
2288  */
2289 static int
2290 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2291 {
2292         struct ixgbe_interrupt *intr =
2293                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2294
2295         ixgbe_dev_link_status_print(dev);
2296         intr->mask |= IXGBE_EICR_LSC;
2297
2298         return 0;
2299 }
2300
2301 /*
2302  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2303  *
2304  * @param dev
2305  *  Pointer to struct rte_eth_dev.
2306  *
2307  * @return
2308  *  - On success, zero.
2309  *  - On failure, a negative value.
2310  */
2311 static int
2312 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2313 {
2314         uint32_t eicr;
2315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2316         struct ixgbe_interrupt *intr =
2317                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2318
2319         /* clear all cause mask */
2320         ixgbe_disable_intr(hw);
2321
2322         /* read-on-clear nic registers here */
2323         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2324         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2325
2326         intr->flags = 0;
2327         if (eicr & IXGBE_EICR_LSC) {
2328                 /* set flag for async link update */
2329                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2330         }
2331
2332         if (eicr & IXGBE_EICR_MAILBOX)
2333                 intr->flags |= IXGBE_FLAG_MAILBOX;
2334
2335         return 0;
2336 }
2337
2338 /**
2339  * It gets and then prints the link status.
2340  *
2341  * @param dev
2342  *  Pointer to struct rte_eth_dev.
2343  *
2344  * @return
2345  *  - On success, zero.
2346  *  - On failure, a negative value.
2347  */
2348 static void
2349 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2350 {
2351         struct rte_eth_link link;
2352
2353         memset(&link, 0, sizeof(link));
2354         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2355         if (link.link_status) {
2356                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2357                                         (int)(dev->data->port_id),
2358                                         (unsigned)link.link_speed,
2359                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2360                                         "full-duplex" : "half-duplex");
2361         } else {
2362                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2363                                 (int)(dev->data->port_id));
2364         }
2365         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2366                                 dev->pci_dev->addr.domain,
2367                                 dev->pci_dev->addr.bus,
2368                                 dev->pci_dev->addr.devid,
2369                                 dev->pci_dev->addr.function);
2370 }
2371
2372 /*
2373  * It executes link_update after knowing an interrupt occurred.
2374  *
2375  * @param dev
2376  *  Pointer to struct rte_eth_dev.
2377  *
2378  * @return
2379  *  - On success, zero.
2380  *  - On failure, a negative value.
2381  */
2382 static int
2383 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2384 {
2385         struct ixgbe_interrupt *intr =
2386                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2387         int64_t timeout;
2388         struct rte_eth_link link;
2389         int intr_enable_delay = false;
2390
2391         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2392
2393         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2394                 ixgbe_pf_mbx_process(dev);
2395                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2396         }
2397
2398         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2399                 /* get the link status before link update, for predicting later */
2400                 memset(&link, 0, sizeof(link));
2401                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2402
2403                 ixgbe_dev_link_update(dev, 0);
2404
2405                 /* likely to up */
2406                 if (!link.link_status)
2407                         /* handle it 1 sec later, wait it being stable */
2408                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2409                 /* likely to down */
2410                 else
2411                         /* handle it 4 sec later, wait it being stable */
2412                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2413
2414                 ixgbe_dev_link_status_print(dev);
2415
2416                 intr_enable_delay = true;
2417         }
2418
2419         if (intr_enable_delay) {
2420                 if (rte_eal_alarm_set(timeout * 1000,
2421                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2422                         PMD_DRV_LOG(ERR, "Error setting alarm");
2423         } else {
2424                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2425                 ixgbe_enable_intr(dev);
2426                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2427         }
2428
2429
2430         return 0;
2431 }
2432
2433 /**
2434  * Interrupt handler which shall be registered for alarm callback for delayed
2435  * handling specific interrupt to wait for the stable nic state. As the
2436  * NIC interrupt state is not stable for ixgbe after link is just down,
2437  * it needs to wait 4 seconds to get the stable status.
2438  *
2439  * @param handle
2440  *  Pointer to interrupt handle.
2441  * @param param
2442  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2443  *
2444  * @return
2445  *  void
2446  */
2447 static void
2448 ixgbe_dev_interrupt_delayed_handler(void *param)
2449 {
2450         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2451         struct ixgbe_interrupt *intr =
2452                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2453         struct ixgbe_hw *hw =
2454                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2455         uint32_t eicr;
2456
2457         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2458         if (eicr & IXGBE_EICR_MAILBOX)
2459                 ixgbe_pf_mbx_process(dev);
2460
2461         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2462                 ixgbe_dev_link_update(dev, 0);
2463                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2464                 ixgbe_dev_link_status_print(dev);
2465                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2466         }
2467
2468         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2469         ixgbe_enable_intr(dev);
2470         rte_intr_enable(&(dev->pci_dev->intr_handle));
2471 }
2472
2473 /**
2474  * Interrupt handler triggered by NIC  for handling
2475  * specific interrupt.
2476  *
2477  * @param handle
2478  *  Pointer to interrupt handle.
2479  * @param param
2480  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2481  *
2482  * @return
2483  *  void
2484  */
2485 static void
2486 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2487                                                         void *param)
2488 {
2489         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2490         ixgbe_dev_interrupt_get_status(dev);
2491         ixgbe_dev_interrupt_action(dev);
2492 }
2493
2494 static int
2495 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2496 {
2497         struct ixgbe_hw *hw;
2498
2499         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2500         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2501 }
2502
2503 static int
2504 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2505 {
2506         struct ixgbe_hw *hw;
2507
2508         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2510 }
2511
2512 static int
2513 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2514 {
2515         struct ixgbe_hw *hw;
2516         uint32_t mflcn_reg;
2517         uint32_t fccfg_reg;
2518         int rx_pause;
2519         int tx_pause;
2520
2521         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522
2523         fc_conf->pause_time = hw->fc.pause_time;
2524         fc_conf->high_water = hw->fc.high_water[0];
2525         fc_conf->low_water = hw->fc.low_water[0];
2526         fc_conf->send_xon = hw->fc.send_xon;
2527         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2528
2529         /*
2530          * Return rx_pause status according to actual setting of
2531          * MFLCN register.
2532          */
2533         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2534         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2535                 rx_pause = 1;
2536         else
2537                 rx_pause = 0;
2538
2539         /*
2540          * Return tx_pause status according to actual setting of
2541          * FCCFG register.
2542          */
2543         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2544         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2545                 tx_pause = 1;
2546         else
2547                 tx_pause = 0;
2548
2549         if (rx_pause && tx_pause)
2550                 fc_conf->mode = RTE_FC_FULL;
2551         else if (rx_pause)
2552                 fc_conf->mode = RTE_FC_RX_PAUSE;
2553         else if (tx_pause)
2554                 fc_conf->mode = RTE_FC_TX_PAUSE;
2555         else
2556                 fc_conf->mode = RTE_FC_NONE;
2557
2558         return 0;
2559 }
2560
2561 static int
2562 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2563 {
2564         struct ixgbe_hw *hw;
2565         int err;
2566         uint32_t rx_buf_size;
2567         uint32_t max_high_water;
2568         uint32_t mflcn;
2569         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2570                 ixgbe_fc_none,
2571                 ixgbe_fc_rx_pause,
2572                 ixgbe_fc_tx_pause,
2573                 ixgbe_fc_full
2574         };
2575
2576         PMD_INIT_FUNC_TRACE();
2577
2578         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2579         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2580         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2581
2582         /*
2583          * At least reserve one Ethernet frame for watermark
2584          * high_water/low_water in kilo bytes for ixgbe
2585          */
2586         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2587         if ((fc_conf->high_water > max_high_water) ||
2588                 (fc_conf->high_water < fc_conf->low_water)) {
2589                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2590                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2591                 return (-EINVAL);
2592         }
2593
2594         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2595         hw->fc.pause_time     = fc_conf->pause_time;
2596         hw->fc.high_water[0]  = fc_conf->high_water;
2597         hw->fc.low_water[0]   = fc_conf->low_water;
2598         hw->fc.send_xon       = fc_conf->send_xon;
2599         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
2600
2601         err = ixgbe_fc_enable(hw);
2602
2603         /* Not negotiated is not an error case */
2604         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2605
2606                 /* check if we want to forward MAC frames - driver doesn't have native
2607                  * capability to do that, so we'll write the registers ourselves */
2608
2609                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2610
2611                 /* set or clear MFLCN.PMCF bit depending on configuration */
2612                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2613                         mflcn |= IXGBE_MFLCN_PMCF;
2614                 else
2615                         mflcn &= ~IXGBE_MFLCN_PMCF;
2616
2617                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2618                 IXGBE_WRITE_FLUSH(hw);
2619
2620                 return 0;
2621         }
2622
2623         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2624         return -EIO;
2625 }
2626
2627 /**
2628  *  ixgbe_pfc_enable_generic - Enable flow control
2629  *  @hw: pointer to hardware structure
2630  *  @tc_num: traffic class number
2631  *  Enable flow control according to the current settings.
2632  */
2633 static int
2634 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2635 {
2636         int ret_val = 0;
2637         uint32_t mflcn_reg, fccfg_reg;
2638         uint32_t reg;
2639         uint32_t fcrtl, fcrth;
2640         uint8_t i;
2641         uint8_t nb_rx_en;
2642
2643         /* Validate the water mark configuration */
2644         if (!hw->fc.pause_time) {
2645                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2646                 goto out;
2647         }
2648
2649         /* Low water mark of zero causes XOFF floods */
2650         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2651                  /* High/Low water can not be 0 */
2652                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2653                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2654                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2655                         goto out;
2656                 }
2657
2658                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2659                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2660                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2661                         goto out;
2662                 }
2663         }
2664         /* Negotiate the fc mode to use */
2665         ixgbe_fc_autoneg(hw);
2666
2667         /* Disable any previous flow control settings */
2668         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2669         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2670
2671         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2672         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2673
2674         switch (hw->fc.current_mode) {
2675         case ixgbe_fc_none:
2676                 /*
2677                  * If the count of enabled RX Priority Flow control >1,
2678                  * and the TX pause can not be disabled
2679                  */
2680                 nb_rx_en = 0;
2681                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2682                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2683                         if (reg & IXGBE_FCRTH_FCEN)
2684                                 nb_rx_en++;
2685                 }
2686                 if (nb_rx_en > 1)
2687                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2688                 break;
2689         case ixgbe_fc_rx_pause:
2690                 /*
2691                  * Rx Flow control is enabled and Tx Flow control is
2692                  * disabled by software override. Since there really
2693                  * isn't a way to advertise that we are capable of RX
2694                  * Pause ONLY, we will advertise that we support both
2695                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2696                  * disable the adapter's ability to send PAUSE frames.
2697                  */
2698                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2699                 /*
2700                  * If the count of enabled RX Priority Flow control >1,
2701                  * and the TX pause can not be disabled
2702                  */
2703                 nb_rx_en = 0;
2704                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2705                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2706                         if (reg & IXGBE_FCRTH_FCEN)
2707                                 nb_rx_en++;
2708                 }
2709                 if (nb_rx_en > 1)
2710                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2711                 break;
2712         case ixgbe_fc_tx_pause:
2713                 /*
2714                  * Tx Flow control is enabled, and Rx Flow control is
2715                  * disabled by software override.
2716                  */
2717                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2718                 break;
2719         case ixgbe_fc_full:
2720                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2721                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2722                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2723                 break;
2724         default:
2725                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2726                 ret_val = IXGBE_ERR_CONFIG;
2727                 goto out;
2728                 break;
2729         }
2730
2731         /* Set 802.3x based flow control settings. */
2732         mflcn_reg |= IXGBE_MFLCN_DPF;
2733         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2734         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2735
2736         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2737         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2738                 hw->fc.high_water[tc_num]) {
2739                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2740                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2741                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2742         } else {
2743                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2744                 /*
2745                  * In order to prevent Tx hangs when the internal Tx
2746                  * switch is enabled we must set the high water mark
2747                  * to the maximum FCRTH value.  This allows the Tx
2748                  * switch to function even under heavy Rx workloads.
2749                  */
2750                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2751         }
2752         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2753
2754         /* Configure pause time (2 TCs per register) */
2755         reg = hw->fc.pause_time * 0x00010001;
2756         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2757                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2758
2759         /* Configure flow control refresh threshold value */
2760         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2761
2762 out:
2763         return ret_val;
2764 }
2765
2766 static int
2767 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2768 {
2769         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2770         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2771
2772         if(hw->mac.type != ixgbe_mac_82598EB) {
2773                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2774         }
2775         return ret_val;
2776 }
2777
2778 static int
2779 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2780 {
2781         int err;
2782         uint32_t rx_buf_size;
2783         uint32_t max_high_water;
2784         uint8_t tc_num;
2785         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2786         struct ixgbe_hw *hw =
2787                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788         struct ixgbe_dcb_config *dcb_config =
2789                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2790
2791         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2792                 ixgbe_fc_none,
2793                 ixgbe_fc_rx_pause,
2794                 ixgbe_fc_tx_pause,
2795                 ixgbe_fc_full
2796         };
2797
2798         PMD_INIT_FUNC_TRACE();
2799
2800         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2801         tc_num = map[pfc_conf->priority];
2802         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2803         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2804         /*
2805          * At least reserve one Ethernet frame for watermark
2806          * high_water/low_water in kilo bytes for ixgbe
2807          */
2808         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2809         if ((pfc_conf->fc.high_water > max_high_water) ||
2810             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2811                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2812                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2813                 return (-EINVAL);
2814         }
2815
2816         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2817         hw->fc.pause_time = pfc_conf->fc.pause_time;
2818         hw->fc.send_xon = pfc_conf->fc.send_xon;
2819         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2820         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2821
2822         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2823
2824         /* Not negotiated is not an error case */
2825         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2826                 return 0;
2827
2828         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2829         return -EIO;
2830 }
2831
2832 static int
2833 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2834                           struct rte_eth_rss_reta_entry64 *reta_conf,
2835                           uint16_t reta_size)
2836 {
2837         uint8_t i, j, mask;
2838         uint32_t reta, r;
2839         uint16_t idx, shift;
2840         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2841
2842         PMD_INIT_FUNC_TRACE();
2843         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2844                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2845                         "(%d) doesn't match the number hardware can supported "
2846                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2847                 return -EINVAL;
2848         }
2849
2850         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2851                 idx = i / RTE_RETA_GROUP_SIZE;
2852                 shift = i % RTE_RETA_GROUP_SIZE;
2853                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2854                                                 IXGBE_4_BIT_MASK);
2855                 if (!mask)
2856                         continue;
2857                 if (mask == IXGBE_4_BIT_MASK)
2858                         r = 0;
2859                 else
2860                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2861                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2862                         if (mask & (0x1 << j))
2863                                 reta |= reta_conf[idx].reta[shift + j] <<
2864                                                         (CHAR_BIT * j);
2865                         else
2866                                 reta |= r & (IXGBE_8_BIT_MASK <<
2867                                                 (CHAR_BIT * j));
2868                 }
2869                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2870         }
2871
2872         return 0;
2873 }
2874
2875 static int
2876 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2877                          struct rte_eth_rss_reta_entry64 *reta_conf,
2878                          uint16_t reta_size)
2879 {
2880         uint8_t i, j, mask;
2881         uint32_t reta;
2882         uint16_t idx, shift;
2883         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884
2885         PMD_INIT_FUNC_TRACE();
2886         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2887                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2888                         "(%d) doesn't match the number hardware can supported "
2889                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2890                 return -EINVAL;
2891         }
2892
2893         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2894                 idx = i / RTE_RETA_GROUP_SIZE;
2895                 shift = i % RTE_RETA_GROUP_SIZE;
2896                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2897                                                 IXGBE_4_BIT_MASK);
2898                 if (!mask)
2899                         continue;
2900
2901                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2902                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2903                         if (mask & (0x1 << j))
2904                                 reta_conf[idx].reta[shift + j] =
2905                                         ((reta >> (CHAR_BIT * j)) &
2906                                                 IXGBE_8_BIT_MASK);
2907                 }
2908         }
2909
2910         return 0;
2911 }
2912
2913 static void
2914 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2915                                 uint32_t index, uint32_t pool)
2916 {
2917         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2918         uint32_t enable_addr = 1;
2919
2920         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2921 }
2922
2923 static void
2924 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2925 {
2926         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927
2928         ixgbe_clear_rar(hw, index);
2929 }
2930
2931 static int
2932 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2933 {
2934         uint32_t hlreg0;
2935         uint32_t maxfrs;
2936         struct ixgbe_hw *hw;
2937         struct rte_eth_dev_info dev_info;
2938         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2939
2940         ixgbe_dev_info_get(dev, &dev_info);
2941
2942         /* check that mtu is within the allowed range */
2943         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2944                 return -EINVAL;
2945
2946         /* refuse mtu that requires the support of scattered packets when this
2947          * feature has not been enabled before. */
2948         if (!dev->data->scattered_rx &&
2949             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2950              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2951                 return -EINVAL;
2952
2953         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2955
2956         /* switch to jumbo mode if needed */
2957         if (frame_size > ETHER_MAX_LEN) {
2958                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2959                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2960         } else {
2961                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2962                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2963         }
2964         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2965
2966         /* update max frame size */
2967         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2968
2969         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2970         maxfrs &= 0x0000FFFF;
2971         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2972         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2973
2974         return 0;
2975 }
2976
2977 /*
2978  * Virtual Function operations
2979  */
2980 static void
2981 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2982 {
2983         PMD_INIT_FUNC_TRACE();
2984
2985         /* Clear interrupt mask to stop from interrupts being generated */
2986         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2987
2988         IXGBE_WRITE_FLUSH(hw);
2989 }
2990
2991 static int
2992 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2993 {
2994         struct rte_eth_conf* conf = &dev->data->dev_conf;
2995         struct ixgbe_adapter *adapter =
2996                         (struct ixgbe_adapter *)dev->data->dev_private;
2997
2998         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2999                      dev->data->port_id);
3000
3001         /*
3002          * VF has no ability to enable/disable HW CRC
3003          * Keep the persistent behavior the same as Host PF
3004          */
3005 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3006         if (!conf->rxmode.hw_strip_crc) {
3007                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
3008                 conf->rxmode.hw_strip_crc = 1;
3009         }
3010 #else
3011         if (conf->rxmode.hw_strip_crc) {
3012                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
3013                 conf->rxmode.hw_strip_crc = 0;
3014         }
3015 #endif
3016
3017         /*
3018          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3019          * allocation or vector Rx preconditions we will reset it.
3020          */
3021         adapter->rx_bulk_alloc_allowed = true;
3022         adapter->rx_vec_allowed = true;
3023
3024         return 0;
3025 }
3026
3027 static int
3028 ixgbevf_dev_start(struct rte_eth_dev *dev)
3029 {
3030         struct ixgbe_hw *hw =
3031                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3032         int err, mask = 0;
3033
3034         PMD_INIT_FUNC_TRACE();
3035
3036         hw->mac.ops.reset_hw(hw);
3037         hw->mac.get_link_status = true;
3038
3039         /* negotiate mailbox API version to use with the PF. */
3040         ixgbevf_negotiate_api(hw);
3041
3042         ixgbevf_dev_tx_init(dev);
3043
3044         /* This can fail when allocating mbufs for descriptor rings */
3045         err = ixgbevf_dev_rx_init(dev);
3046         if (err) {
3047                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3048                 ixgbe_dev_clear_queues(dev);
3049                 return err;
3050         }
3051
3052         /* Set vfta */
3053         ixgbevf_set_vfta_all(dev,1);
3054
3055         /* Set HW strip */
3056         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3057                 ETH_VLAN_EXTEND_MASK;
3058         ixgbevf_vlan_offload_set(dev, mask);
3059
3060         ixgbevf_dev_rxtx_start(dev);
3061
3062         return 0;
3063 }
3064
3065 static void
3066 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3067 {
3068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069
3070         PMD_INIT_FUNC_TRACE();
3071
3072         hw->adapter_stopped = TRUE;
3073         ixgbe_stop_adapter(hw);
3074
3075         /*
3076           * Clear what we set, but we still keep shadow_vfta to
3077           * restore after device starts
3078           */
3079         ixgbevf_set_vfta_all(dev,0);
3080
3081         /* Clear stored conf */
3082         dev->data->scattered_rx = 0;
3083
3084         ixgbe_dev_clear_queues(dev);
3085 }
3086
3087 static void
3088 ixgbevf_dev_close(struct rte_eth_dev *dev)
3089 {
3090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3091
3092         PMD_INIT_FUNC_TRACE();
3093
3094         ixgbe_reset_hw(hw);
3095
3096         ixgbevf_dev_stop(dev);
3097
3098         /* reprogram the RAR[0] in case user changed it. */
3099         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3100 }
3101
3102 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3103 {
3104         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105         struct ixgbe_vfta * shadow_vfta =
3106                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3107         int i = 0, j = 0, vfta = 0, mask = 1;
3108
3109         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3110                 vfta = shadow_vfta->vfta[i];
3111                 if(vfta){
3112                         mask = 1;
3113                         for (j = 0; j < 32; j++){
3114                                 if(vfta & mask)
3115                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3116                                 mask<<=1;
3117                         }
3118                 }
3119         }
3120
3121 }
3122
3123 static int
3124 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3125 {
3126         struct ixgbe_hw *hw =
3127                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3128         struct ixgbe_vfta * shadow_vfta =
3129                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3130         uint32_t vid_idx = 0;
3131         uint32_t vid_bit = 0;
3132         int ret = 0;
3133
3134         PMD_INIT_FUNC_TRACE();
3135
3136         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3137         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3138         if(ret){
3139                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3140                 return ret;
3141         }
3142         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3143         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3144
3145         /* Save what we set and retore it after device reset */
3146         if (on)
3147                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3148         else
3149                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3150
3151         return 0;
3152 }
3153
3154 static void
3155 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3156 {
3157         struct ixgbe_hw *hw =
3158                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         uint32_t ctrl;
3160
3161         PMD_INIT_FUNC_TRACE();
3162
3163         if(queue >= hw->mac.max_rx_queues)
3164                 return;
3165
3166         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3167         if(on)
3168                 ctrl |= IXGBE_RXDCTL_VME;
3169         else
3170                 ctrl &= ~IXGBE_RXDCTL_VME;
3171         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3172
3173         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3174 }
3175
3176 static void
3177 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3178 {
3179         struct ixgbe_hw *hw =
3180                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3181         uint16_t i;
3182         int on = 0;
3183
3184         /* VF function only support hw strip feature, others are not support */
3185         if(mask & ETH_VLAN_STRIP_MASK){
3186                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3187
3188                 for(i=0; i < hw->mac.max_rx_queues; i++)
3189                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3190         }
3191 }
3192
3193 static int
3194 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3195 {
3196         uint32_t reg_val;
3197
3198         /* we only need to do this if VMDq is enabled */
3199         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3200         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3201                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3202                 return (-1);
3203         }
3204
3205         return 0;
3206 }
3207
3208 static uint32_t
3209 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3210 {
3211         uint32_t vector = 0;
3212         switch (hw->mac.mc_filter_type) {
3213         case 0:   /* use bits [47:36] of the address */
3214                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3215                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3216                 break;
3217         case 1:   /* use bits [46:35] of the address */
3218                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3219                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3220                 break;
3221         case 2:   /* use bits [45:34] of the address */
3222                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3223                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3224                 break;
3225         case 3:   /* use bits [43:32] of the address */
3226                 vector = ((uc_addr->addr_bytes[4]) |
3227                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3228                 break;
3229         default:  /* Invalid mc_filter_type */
3230                 break;
3231         }
3232
3233         /* vector can only be 12-bits or boundary will be exceeded */
3234         vector &= 0xFFF;
3235         return vector;
3236 }
3237
3238 static int
3239 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3240                                uint8_t on)
3241 {
3242         uint32_t vector;
3243         uint32_t uta_idx;
3244         uint32_t reg_val;
3245         uint32_t uta_shift;
3246         uint32_t rc;
3247         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3248         const uint32_t ixgbe_uta_bit_shift = 5;
3249         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3250         const uint32_t bit1 = 0x1;
3251
3252         struct ixgbe_hw *hw =
3253                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3254         struct ixgbe_uta_info *uta_info =
3255                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3256
3257         /* The UTA table only exists on 82599 hardware and newer */
3258         if (hw->mac.type < ixgbe_mac_82599EB)
3259                 return (-ENOTSUP);
3260
3261         vector = ixgbe_uta_vector(hw,mac_addr);
3262         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3263         uta_shift = vector & ixgbe_uta_bit_mask;
3264
3265         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3266         if(rc == on)
3267                 return 0;
3268
3269         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3270         if (on) {
3271                 uta_info->uta_in_use++;
3272                 reg_val |= (bit1 << uta_shift);
3273                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3274         } else {
3275                 uta_info->uta_in_use--;
3276                 reg_val &= ~(bit1 << uta_shift);
3277                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3278         }
3279
3280         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3281
3282         if (uta_info->uta_in_use > 0)
3283                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3284                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3285         else
3286                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3287
3288         return 0;
3289 }
3290
3291 static int
3292 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3293 {
3294         int i;
3295         struct ixgbe_hw *hw =
3296                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3297         struct ixgbe_uta_info *uta_info =
3298                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3299
3300         /* The UTA table only exists on 82599 hardware and newer */
3301         if (hw->mac.type < ixgbe_mac_82599EB)
3302                 return (-ENOTSUP);
3303
3304         if(on) {
3305                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3306                         uta_info->uta_shadow[i] = ~0;
3307                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3308                 }
3309         } else {
3310                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3311                         uta_info->uta_shadow[i] = 0;
3312                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3313                 }
3314         }
3315         return 0;
3316
3317 }
3318
3319 uint32_t
3320 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3321 {
3322         uint32_t new_val = orig_val;
3323
3324         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3325                 new_val |= IXGBE_VMOLR_AUPE;
3326         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3327                 new_val |= IXGBE_VMOLR_ROMPE;
3328         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3329                 new_val |= IXGBE_VMOLR_ROPE;
3330         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3331                 new_val |= IXGBE_VMOLR_BAM;
3332         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3333                 new_val |= IXGBE_VMOLR_MPE;
3334
3335         return new_val;
3336 }
3337
3338 static int
3339 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3340                                uint16_t rx_mask, uint8_t on)
3341 {
3342         int val = 0;
3343
3344         struct ixgbe_hw *hw =
3345                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3347
3348         if (hw->mac.type == ixgbe_mac_82598EB) {
3349                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3350                              " on 82599 hardware and newer");
3351                 return (-ENOTSUP);
3352         }
3353         if (ixgbe_vmdq_mode_check(hw) < 0)
3354                 return (-ENOTSUP);
3355
3356         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3357
3358         if (on)
3359                 vmolr |= val;
3360         else
3361                 vmolr &= ~val;
3362
3363         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3364
3365         return 0;
3366 }
3367
3368 static int
3369 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3370 {
3371         uint32_t reg,addr;
3372         uint32_t val;
3373         const uint8_t bit1 = 0x1;
3374
3375         struct ixgbe_hw *hw =
3376                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377
3378         if (ixgbe_vmdq_mode_check(hw) < 0)
3379                 return (-ENOTSUP);
3380
3381         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3382         reg = IXGBE_READ_REG(hw, addr);
3383         val = bit1 << pool;
3384
3385         if (on)
3386                 reg |= val;
3387         else
3388                 reg &= ~val;
3389
3390         IXGBE_WRITE_REG(hw, addr,reg);
3391
3392         return 0;
3393 }
3394
3395 static int
3396 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3397 {
3398         uint32_t reg,addr;
3399         uint32_t val;
3400         const uint8_t bit1 = 0x1;
3401
3402         struct ixgbe_hw *hw =
3403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404
3405         if (ixgbe_vmdq_mode_check(hw) < 0)
3406                 return (-ENOTSUP);
3407
3408         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3409         reg = IXGBE_READ_REG(hw, addr);
3410         val = bit1 << pool;
3411
3412         if (on)
3413                 reg |= val;
3414         else
3415                 reg &= ~val;
3416
3417         IXGBE_WRITE_REG(hw, addr,reg);
3418
3419         return 0;
3420 }
3421
3422 static int
3423 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3424                         uint64_t pool_mask, uint8_t vlan_on)
3425 {
3426         int ret = 0;
3427         uint16_t pool_idx;
3428         struct ixgbe_hw *hw =
3429                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3430
3431         if (ixgbe_vmdq_mode_check(hw) < 0)
3432                 return (-ENOTSUP);
3433         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3434                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3435                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3436                         if (ret < 0)
3437                                 return ret;
3438         }
3439
3440         return ret;
3441 }
3442
3443 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
3444 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
3445 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
3446 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
3447 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
3448         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
3449         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
3450
3451 static int
3452 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3453                         struct rte_eth_mirror_conf *mirror_conf,
3454                         uint8_t rule_id, uint8_t on)
3455 {
3456         uint32_t mr_ctl,vlvf;
3457         uint32_t mp_lsb = 0;
3458         uint32_t mv_msb = 0;
3459         uint32_t mv_lsb = 0;
3460         uint32_t mp_msb = 0;
3461         uint8_t i = 0;
3462         int reg_index = 0;
3463         uint64_t vlan_mask = 0;
3464
3465         const uint8_t pool_mask_offset = 32;
3466         const uint8_t vlan_mask_offset = 32;
3467         const uint8_t dst_pool_offset = 8;
3468         const uint8_t rule_mr_offset  = 4;
3469         const uint8_t mirror_rule_mask= 0x0F;
3470
3471         struct ixgbe_mirror_info *mr_info =
3472                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3473         struct ixgbe_hw *hw =
3474                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3475         uint8_t mirror_type = 0;
3476
3477         if (ixgbe_vmdq_mode_check(hw) < 0)
3478                 return -ENOTSUP;
3479
3480         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3481                 return -EINVAL;
3482
3483         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
3484                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
3485                         mirror_conf->rule_type);
3486                 return -EINVAL;
3487         }
3488
3489         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
3490                 mirror_type |= IXGBE_MRCTL_VLME;
3491                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3492                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3493                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3494                                 /* search vlan id related pool vlan filter index */
3495                                 reg_index = ixgbe_find_vlvf_slot(hw,
3496                                                 mirror_conf->vlan.vlan_id[i]);
3497                                 if(reg_index < 0)
3498                                         return -EINVAL;
3499                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3500                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3501                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
3502                                       mirror_conf->vlan.vlan_id[i]))
3503                                         vlan_mask |= (1ULL << reg_index);
3504                                 else
3505                                         return -EINVAL;
3506                         }
3507                 }
3508
3509                 if (on) {
3510                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3511                         mv_msb = vlan_mask >> vlan_mask_offset;
3512
3513                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3514                                                 mirror_conf->vlan.vlan_mask;
3515                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3516                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3517                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3518                                                 mirror_conf->vlan.vlan_id[i];
3519                         }
3520                 } else {
3521                         mv_lsb = 0;
3522                         mv_msb = 0;
3523                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3524                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3525                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3526                 }
3527         }
3528
3529         /*
3530          * if enable pool mirror, write related pool mask register,if disable
3531          * pool mirror, clear PFMRVM register
3532          */
3533         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
3534                 mirror_type |= IXGBE_MRCTL_VPME;
3535                 if (on) {
3536                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3537                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3538                         mr_info->mr_conf[rule_id].pool_mask =
3539                                         mirror_conf->pool_mask;
3540
3541                 } else {
3542                         mp_lsb = 0;
3543                         mp_msb = 0;
3544                         mr_info->mr_conf[rule_id].pool_mask = 0;
3545                 }
3546         }
3547         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
3548                 mirror_type |= IXGBE_MRCTL_UPME;
3549         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
3550                 mirror_type |= IXGBE_MRCTL_DPME;
3551
3552         /* read  mirror control register and recalculate it */
3553         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
3554
3555         if (on) {
3556                 mr_ctl |= mirror_type;
3557                 mr_ctl &= mirror_rule_mask;
3558                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3559         } else
3560                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
3561
3562         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
3563         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3564
3565         /* write mirrror control  register */
3566         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3567
3568         /* write pool mirrror control  register */
3569         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
3570                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3571                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3572                                 mp_msb);
3573         }
3574         /* write VLAN mirrror control  register */
3575         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
3576                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3577                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3578                                 mv_msb);
3579         }
3580
3581         return 0;
3582 }
3583
3584 static int
3585 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3586 {
3587         int mr_ctl = 0;
3588         uint32_t lsb_val = 0;
3589         uint32_t msb_val = 0;
3590         const uint8_t rule_mr_offset = 4;
3591
3592         struct ixgbe_hw *hw =
3593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3594         struct ixgbe_mirror_info *mr_info =
3595                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3596
3597         if (ixgbe_vmdq_mode_check(hw) < 0)
3598                 return (-ENOTSUP);
3599
3600         memset(&mr_info->mr_conf[rule_id], 0,
3601                 sizeof(struct rte_eth_mirror_conf));
3602
3603         /* clear PFVMCTL register */
3604         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3605
3606         /* clear pool mask register */
3607         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3608         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3609
3610         /* clear vlan mask register */
3611         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3612         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3613
3614         return 0;
3615 }
3616
3617 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3618         uint16_t queue_idx, uint16_t tx_rate)
3619 {
3620         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3621         uint32_t rf_dec, rf_int;
3622         uint32_t bcnrc_val;
3623         uint16_t link_speed = dev->data->dev_link.link_speed;
3624
3625         if (queue_idx >= hw->mac.max_tx_queues)
3626                 return -EINVAL;
3627
3628         if (tx_rate != 0) {
3629                 /* Calculate the rate factor values to set */
3630                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3631                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3632                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3633
3634                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3635                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3636                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3637                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3638         } else {
3639                 bcnrc_val = 0;
3640         }
3641
3642         /*
3643          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3644          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3645          * set as 0x4.
3646          */
3647         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3648                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3649                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3650                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3651                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3652         else
3653                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3654                         IXGBE_MMW_SIZE_DEFAULT);
3655
3656         /* Set RTTBCNRC of queue X */
3657         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3658         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3659         IXGBE_WRITE_FLUSH(hw);
3660
3661         return 0;
3662 }
3663
3664 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3665         uint16_t tx_rate, uint64_t q_msk)
3666 {
3667         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3668         struct ixgbe_vf_info *vfinfo =
3669                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3670         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3671         uint32_t queue_stride =
3672                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3673         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3674         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3675         uint16_t total_rate = 0;
3676
3677         if (queue_end >= hw->mac.max_tx_queues)
3678                 return -EINVAL;
3679
3680         if (vfinfo != NULL) {
3681                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3682                         if (vf_idx == vf)
3683                                 continue;
3684                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3685                                 idx++)
3686                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3687                 }
3688         } else
3689                 return -EINVAL;
3690
3691         /* Store tx_rate for this vf. */
3692         for (idx = 0; idx < nb_q_per_pool; idx++) {
3693                 if (((uint64_t)0x1 << idx) & q_msk) {
3694                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3695                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3696                         total_rate += tx_rate;
3697                 }
3698         }
3699
3700         if (total_rate > dev->data->dev_link.link_speed) {
3701                 /*
3702                  * Reset stored TX rate of the VF if it causes exceed
3703                  * link speed.
3704                  */
3705                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3706                 return -EINVAL;
3707         }
3708
3709         /* Set RTTBCNRC of each queue/pool for vf X  */
3710         for (; queue_idx <= queue_end; queue_idx++) {
3711                 if (0x1 & q_msk)
3712                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3713                 q_msk = q_msk >> 1;
3714         }
3715
3716         return 0;
3717 }
3718
3719 static void
3720 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3721                      __attribute__((unused)) uint32_t index,
3722                      __attribute__((unused)) uint32_t pool)
3723 {
3724         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725         int diag;
3726
3727         /*
3728          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3729          * operation. Trap this case to avoid exhausting the [very limited]
3730          * set of PF resources used to store VF MAC addresses.
3731          */
3732         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3733                 return;
3734         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3735         if (diag == 0)
3736                 return;
3737         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3738 }
3739
3740 static void
3741 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3742 {
3743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3745         struct ether_addr *mac_addr;
3746         uint32_t i;
3747         int diag;
3748
3749         /*
3750          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3751          * not support the deletion of a given MAC address.
3752          * Instead, it imposes to delete all MAC addresses, then to add again
3753          * all MAC addresses with the exception of the one to be deleted.
3754          */
3755         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3756
3757         /*
3758          * Add again all MAC addresses, with the exception of the deleted one
3759          * and of the permanent MAC address.
3760          */
3761         for (i = 0, mac_addr = dev->data->mac_addrs;
3762              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3763                 /* Skip the deleted MAC address */
3764                 if (i == index)
3765                         continue;
3766                 /* Skip NULL MAC addresses */
3767                 if (is_zero_ether_addr(mac_addr))
3768                         continue;
3769                 /* Skip the permanent MAC address */
3770                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3771                         continue;
3772                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3773                 if (diag != 0)
3774                         PMD_DRV_LOG(ERR,
3775                                     "Adding again MAC address "
3776                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3777                                     "diag=%d",
3778                                     mac_addr->addr_bytes[0],
3779                                     mac_addr->addr_bytes[1],
3780                                     mac_addr->addr_bytes[2],
3781                                     mac_addr->addr_bytes[3],
3782                                     mac_addr->addr_bytes[4],
3783                                     mac_addr->addr_bytes[5],
3784                                     diag);
3785         }
3786 }
3787
3788 #define MAC_TYPE_FILTER_SUP(type)    do {\
3789         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3790                 (type) != ixgbe_mac_X550)\
3791                 return -ENOTSUP;\
3792 } while (0)
3793
3794 static int
3795 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3796                         struct rte_eth_syn_filter *filter,
3797                         bool add)
3798 {
3799         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3800         uint32_t synqf;
3801
3802         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3803                 return -EINVAL;
3804
3805         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3806
3807         if (add) {
3808                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3809                         return -EINVAL;
3810                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3811                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3812
3813                 if (filter->hig_pri)
3814                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3815                 else
3816                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3817         } else {
3818                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3819                         return -ENOENT;
3820                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3821         }
3822         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3823         IXGBE_WRITE_FLUSH(hw);
3824         return 0;
3825 }
3826
3827 static int
3828 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3829                         struct rte_eth_syn_filter *filter)
3830 {
3831         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3832         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3833
3834         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3835                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3836                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3837                 return 0;
3838         }
3839         return -ENOENT;
3840 }
3841
3842 static int
3843 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3844                         enum rte_filter_op filter_op,
3845                         void *arg)
3846 {
3847         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848         int ret;
3849
3850         MAC_TYPE_FILTER_SUP(hw->mac.type);
3851
3852         if (filter_op == RTE_ETH_FILTER_NOP)
3853                 return 0;
3854
3855         if (arg == NULL) {
3856                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3857                             filter_op);
3858                 return -EINVAL;
3859         }
3860
3861         switch (filter_op) {
3862         case RTE_ETH_FILTER_ADD:
3863                 ret = ixgbe_syn_filter_set(dev,
3864                                 (struct rte_eth_syn_filter *)arg,
3865                                 TRUE);
3866                 break;
3867         case RTE_ETH_FILTER_DELETE:
3868                 ret = ixgbe_syn_filter_set(dev,
3869                                 (struct rte_eth_syn_filter *)arg,
3870                                 FALSE);
3871                 break;
3872         case RTE_ETH_FILTER_GET:
3873                 ret = ixgbe_syn_filter_get(dev,
3874                                 (struct rte_eth_syn_filter *)arg);
3875                 break;
3876         default:
3877                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3878                 ret = -EINVAL;
3879                 break;
3880         }
3881
3882         return ret;
3883 }
3884
3885
3886 static inline enum ixgbe_5tuple_protocol
3887 convert_protocol_type(uint8_t protocol_value)
3888 {
3889         if (protocol_value == IPPROTO_TCP)
3890                 return IXGBE_FILTER_PROTOCOL_TCP;
3891         else if (protocol_value == IPPROTO_UDP)
3892                 return IXGBE_FILTER_PROTOCOL_UDP;
3893         else if (protocol_value == IPPROTO_SCTP)
3894                 return IXGBE_FILTER_PROTOCOL_SCTP;
3895         else
3896                 return IXGBE_FILTER_PROTOCOL_NONE;
3897 }
3898
3899 /*
3900  * add a 5tuple filter
3901  *
3902  * @param
3903  * dev: Pointer to struct rte_eth_dev.
3904  * index: the index the filter allocates.
3905  * filter: ponter to the filter that will be added.
3906  * rx_queue: the queue id the filter assigned to.
3907  *
3908  * @return
3909  *    - On success, zero.
3910  *    - On failure, a negative value.
3911  */
3912 static int
3913 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3914                         struct ixgbe_5tuple_filter *filter)
3915 {
3916         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917         struct ixgbe_filter_info *filter_info =
3918                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3919         int i, idx, shift;
3920         uint32_t ftqf, sdpqf;
3921         uint32_t l34timir = 0;
3922         uint8_t mask = 0xff;
3923
3924         /*
3925          * look for an unused 5tuple filter index,
3926          * and insert the filter to list.
3927          */
3928         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3929                 idx = i / (sizeof(uint32_t) * NBBY);
3930                 shift = i % (sizeof(uint32_t) * NBBY);
3931                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3932                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3933                         filter->index = i;
3934                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3935                                           filter,
3936                                           entries);
3937                         break;
3938                 }
3939         }
3940         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3941                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3942                 return -ENOSYS;
3943         }
3944
3945         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3946                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3947         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3948
3949         ftqf = (uint32_t)(filter->filter_info.proto &
3950                 IXGBE_FTQF_PROTOCOL_MASK);
3951         ftqf |= (uint32_t)((filter->filter_info.priority &
3952                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3953         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3954                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3955         if (filter->filter_info.dst_ip_mask == 0)
3956                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3957         if (filter->filter_info.src_port_mask == 0)
3958                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3959         if (filter->filter_info.dst_port_mask == 0)
3960                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3961         if (filter->filter_info.proto_mask == 0)
3962                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3963         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3964         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3965         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3966
3967         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3968         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3969         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3970         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3971
3972         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3973         l34timir |= (uint32_t)(filter->queue <<
3974                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3975         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3976         return 0;
3977 }
3978
3979 /*
3980  * remove a 5tuple filter
3981  *
3982  * @param
3983  * dev: Pointer to struct rte_eth_dev.
3984  * filter: the pointer of the filter will be removed.
3985  */
3986 static void
3987 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3988                         struct ixgbe_5tuple_filter *filter)
3989 {
3990         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3991         struct ixgbe_filter_info *filter_info =
3992                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3993         uint16_t index = filter->index;
3994
3995         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3996                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3997         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3998         rte_free(filter);
3999
4000         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
4001         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
4002         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
4003         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
4004         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
4005 }
4006
4007 static int
4008 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
4009 {
4010         struct ixgbe_hw *hw;
4011         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4012
4013         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4014
4015         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
4016                 return -EINVAL;
4017
4018         /* refuse mtu that requires the support of scattered packets when this
4019          * feature has not been enabled before. */
4020         if (!dev->data->scattered_rx &&
4021             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
4022              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4023                 return -EINVAL;
4024
4025         /*
4026          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
4027          * request of the version 2.0 of the mailbox API.
4028          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
4029          * of the mailbox API.
4030          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
4031          * prior to 3.11.33 which contains the following change:
4032          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
4033          */
4034         ixgbevf_rlpml_set_vf(hw, max_frame);
4035
4036         /* update max frame size */
4037         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
4038         return 0;
4039 }
4040
4041 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4042         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4043                 return -ENOTSUP;\
4044 } while (0)
4045
4046 static inline struct ixgbe_5tuple_filter *
4047 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4048                         struct ixgbe_5tuple_filter_info *key)
4049 {
4050         struct ixgbe_5tuple_filter *it;
4051
4052         TAILQ_FOREACH(it, filter_list, entries) {
4053                 if (memcmp(key, &it->filter_info,
4054                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4055                         return it;
4056                 }
4057         }
4058         return NULL;
4059 }
4060
4061 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4062 static inline int
4063 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4064                         struct ixgbe_5tuple_filter_info *filter_info)
4065 {
4066         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4067                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4068                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4069                 return -EINVAL;
4070
4071         switch (filter->dst_ip_mask) {
4072         case UINT32_MAX:
4073                 filter_info->dst_ip_mask = 0;
4074                 filter_info->dst_ip = filter->dst_ip;
4075                 break;
4076         case 0:
4077                 filter_info->dst_ip_mask = 1;
4078                 break;
4079         default:
4080                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4081                 return -EINVAL;
4082         }
4083
4084         switch (filter->src_ip_mask) {
4085         case UINT32_MAX:
4086                 filter_info->src_ip_mask = 0;
4087                 filter_info->src_ip = filter->src_ip;
4088                 break;
4089         case 0:
4090                 filter_info->src_ip_mask = 1;
4091                 break;
4092         default:
4093                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4094                 return -EINVAL;
4095         }
4096
4097         switch (filter->dst_port_mask) {
4098         case UINT16_MAX:
4099                 filter_info->dst_port_mask = 0;
4100                 filter_info->dst_port = filter->dst_port;
4101                 break;
4102         case 0:
4103                 filter_info->dst_port_mask = 1;
4104                 break;
4105         default:
4106                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4107                 return -EINVAL;
4108         }
4109
4110         switch (filter->src_port_mask) {
4111         case UINT16_MAX:
4112                 filter_info->src_port_mask = 0;
4113                 filter_info->src_port = filter->src_port;
4114                 break;
4115         case 0:
4116                 filter_info->src_port_mask = 1;
4117                 break;
4118         default:
4119                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4120                 return -EINVAL;
4121         }
4122
4123         switch (filter->proto_mask) {
4124         case UINT8_MAX:
4125                 filter_info->proto_mask = 0;
4126                 filter_info->proto =
4127                         convert_protocol_type(filter->proto);
4128                 break;
4129         case 0:
4130                 filter_info->proto_mask = 1;
4131                 break;
4132         default:
4133                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4134                 return -EINVAL;
4135         }
4136
4137         filter_info->priority = (uint8_t)filter->priority;
4138         return 0;
4139 }
4140
4141 /*
4142  * add or delete a ntuple filter
4143  *
4144  * @param
4145  * dev: Pointer to struct rte_eth_dev.
4146  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4147  * add: if true, add filter, if false, remove filter
4148  *
4149  * @return
4150  *    - On success, zero.
4151  *    - On failure, a negative value.
4152  */
4153 static int
4154 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4155                         struct rte_eth_ntuple_filter *ntuple_filter,
4156                         bool add)
4157 {
4158         struct ixgbe_filter_info *filter_info =
4159                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4160         struct ixgbe_5tuple_filter_info filter_5tuple;
4161         struct ixgbe_5tuple_filter *filter;
4162         int ret;
4163
4164         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4165                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4166                 return -EINVAL;
4167         }
4168
4169         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4170         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4171         if (ret < 0)
4172                 return ret;
4173
4174         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4175                                          &filter_5tuple);
4176         if (filter != NULL && add) {
4177                 PMD_DRV_LOG(ERR, "filter exists.");
4178                 return -EEXIST;
4179         }
4180         if (filter == NULL && !add) {
4181                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4182                 return -ENOENT;
4183         }
4184
4185         if (add) {
4186                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4187                                 sizeof(struct ixgbe_5tuple_filter), 0);
4188                 if (filter == NULL)
4189                         return -ENOMEM;
4190                 (void)rte_memcpy(&filter->filter_info,
4191                                  &filter_5tuple,
4192                                  sizeof(struct ixgbe_5tuple_filter_info));
4193                 filter->queue = ntuple_filter->queue;
4194                 ret = ixgbe_add_5tuple_filter(dev, filter);
4195                 if (ret < 0) {
4196                         rte_free(filter);
4197                         return ret;
4198                 }
4199         } else
4200                 ixgbe_remove_5tuple_filter(dev, filter);
4201
4202         return 0;
4203 }
4204
4205 /*
4206  * get a ntuple filter
4207  *
4208  * @param
4209  * dev: Pointer to struct rte_eth_dev.
4210  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4211  *
4212  * @return
4213  *    - On success, zero.
4214  *    - On failure, a negative value.
4215  */
4216 static int
4217 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4218                         struct rte_eth_ntuple_filter *ntuple_filter)
4219 {
4220         struct ixgbe_filter_info *filter_info =
4221                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4222         struct ixgbe_5tuple_filter_info filter_5tuple;
4223         struct ixgbe_5tuple_filter *filter;
4224         int ret;
4225
4226         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4227                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4228                 return -EINVAL;
4229         }
4230
4231         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4232         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4233         if (ret < 0)
4234                 return ret;
4235
4236         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4237                                          &filter_5tuple);
4238         if (filter == NULL) {
4239                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4240                 return -ENOENT;
4241         }
4242         ntuple_filter->queue = filter->queue;
4243         return 0;
4244 }
4245
4246 /*
4247  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4248  * @dev: pointer to rte_eth_dev structure
4249  * @filter_op:operation will be taken.
4250  * @arg: a pointer to specific structure corresponding to the filter_op
4251  *
4252  * @return
4253  *    - On success, zero.
4254  *    - On failure, a negative value.
4255  */
4256 static int
4257 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4258                                 enum rte_filter_op filter_op,
4259                                 void *arg)
4260 {
4261         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4262         int ret;
4263
4264         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4265
4266         if (filter_op == RTE_ETH_FILTER_NOP)
4267                 return 0;
4268
4269         if (arg == NULL) {
4270                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4271                             filter_op);
4272                 return -EINVAL;
4273         }
4274
4275         switch (filter_op) {
4276         case RTE_ETH_FILTER_ADD:
4277                 ret = ixgbe_add_del_ntuple_filter(dev,
4278                         (struct rte_eth_ntuple_filter *)arg,
4279                         TRUE);
4280                 break;
4281         case RTE_ETH_FILTER_DELETE:
4282                 ret = ixgbe_add_del_ntuple_filter(dev,
4283                         (struct rte_eth_ntuple_filter *)arg,
4284                         FALSE);
4285                 break;
4286         case RTE_ETH_FILTER_GET:
4287                 ret = ixgbe_get_ntuple_filter(dev,
4288                         (struct rte_eth_ntuple_filter *)arg);
4289                 break;
4290         default:
4291                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4292                 ret = -EINVAL;
4293                 break;
4294         }
4295         return ret;
4296 }
4297
4298 static inline int
4299 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4300                         uint16_t ethertype)
4301 {
4302         int i;
4303
4304         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4305                 if (filter_info->ethertype_filters[i] == ethertype &&
4306                     (filter_info->ethertype_mask & (1 << i)))
4307                         return i;
4308         }
4309         return -1;
4310 }
4311
4312 static inline int
4313 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4314                         uint16_t ethertype)
4315 {
4316         int i;
4317
4318         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4319                 if (!(filter_info->ethertype_mask & (1 << i))) {
4320                         filter_info->ethertype_mask |= 1 << i;
4321                         filter_info->ethertype_filters[i] = ethertype;
4322                         return i;
4323                 }
4324         }
4325         return -1;
4326 }
4327
4328 static inline int
4329 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4330                         uint8_t idx)
4331 {
4332         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4333                 return -1;
4334         filter_info->ethertype_mask &= ~(1 << idx);
4335         filter_info->ethertype_filters[idx] = 0;
4336         return idx;
4337 }
4338
4339 static int
4340 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4341                         struct rte_eth_ethertype_filter *filter,
4342                         bool add)
4343 {
4344         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4345         struct ixgbe_filter_info *filter_info =
4346                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4347         uint32_t etqf = 0;
4348         uint32_t etqs = 0;
4349         int ret;
4350
4351         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4352                 return -EINVAL;
4353
4354         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4355                 filter->ether_type == ETHER_TYPE_IPv6) {
4356                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4357                         " ethertype filter.", filter->ether_type);
4358                 return -EINVAL;
4359         }
4360
4361         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4362                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4363                 return -EINVAL;
4364         }
4365         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4366                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4367                 return -EINVAL;
4368         }
4369
4370         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4371         if (ret >= 0 && add) {
4372                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4373                             filter->ether_type);
4374                 return -EEXIST;
4375         }
4376         if (ret < 0 && !add) {
4377                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4378                             filter->ether_type);
4379                 return -ENOENT;
4380         }
4381
4382         if (add) {
4383                 ret = ixgbe_ethertype_filter_insert(filter_info,
4384                         filter->ether_type);
4385                 if (ret < 0) {
4386                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4387                         return -ENOSYS;
4388                 }
4389                 etqf = IXGBE_ETQF_FILTER_EN;
4390                 etqf |= (uint32_t)filter->ether_type;
4391                 etqs |= (uint32_t)((filter->queue <<
4392                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4393                                     IXGBE_ETQS_RX_QUEUE);
4394                 etqs |= IXGBE_ETQS_QUEUE_EN;
4395         } else {
4396                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4397                 if (ret < 0)
4398                         return -ENOSYS;
4399         }
4400         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4401         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4402         IXGBE_WRITE_FLUSH(hw);
4403
4404         return 0;
4405 }
4406
4407 static int
4408 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4409                         struct rte_eth_ethertype_filter *filter)
4410 {
4411         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4412         struct ixgbe_filter_info *filter_info =
4413                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4414         uint32_t etqf, etqs;
4415         int ret;
4416
4417         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4418         if (ret < 0) {
4419                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4420                             filter->ether_type);
4421                 return -ENOENT;
4422         }
4423
4424         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4425         if (etqf & IXGBE_ETQF_FILTER_EN) {
4426                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4427                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4428                 filter->flags = 0;
4429                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4430                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4431                 return 0;
4432         }
4433         return -ENOENT;
4434 }
4435
4436 /*
4437  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4438  * @dev: pointer to rte_eth_dev structure
4439  * @filter_op:operation will be taken.
4440  * @arg: a pointer to specific structure corresponding to the filter_op
4441  */
4442 static int
4443 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4444                                 enum rte_filter_op filter_op,
4445                                 void *arg)
4446 {
4447         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4448         int ret;
4449
4450         MAC_TYPE_FILTER_SUP(hw->mac.type);
4451
4452         if (filter_op == RTE_ETH_FILTER_NOP)
4453                 return 0;
4454
4455         if (arg == NULL) {
4456                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4457                             filter_op);
4458                 return -EINVAL;
4459         }
4460
4461         switch (filter_op) {
4462         case RTE_ETH_FILTER_ADD:
4463                 ret = ixgbe_add_del_ethertype_filter(dev,
4464                         (struct rte_eth_ethertype_filter *)arg,
4465                         TRUE);
4466                 break;
4467         case RTE_ETH_FILTER_DELETE:
4468                 ret = ixgbe_add_del_ethertype_filter(dev,
4469                         (struct rte_eth_ethertype_filter *)arg,
4470                         FALSE);
4471                 break;
4472         case RTE_ETH_FILTER_GET:
4473                 ret = ixgbe_get_ethertype_filter(dev,
4474                         (struct rte_eth_ethertype_filter *)arg);
4475                 break;
4476         default:
4477                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4478                 ret = -EINVAL;
4479                 break;
4480         }
4481         return ret;
4482 }
4483
4484 static int
4485 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4486                      enum rte_filter_type filter_type,
4487                      enum rte_filter_op filter_op,
4488                      void *arg)
4489 {
4490         int ret = -EINVAL;
4491
4492         switch (filter_type) {
4493         case RTE_ETH_FILTER_NTUPLE:
4494                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4495                 break;
4496         case RTE_ETH_FILTER_ETHERTYPE:
4497                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4498                 break;
4499         case RTE_ETH_FILTER_SYN:
4500                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4501                 break;
4502         case RTE_ETH_FILTER_FDIR:
4503                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4504                 break;
4505         default:
4506                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4507                                                         filter_type);
4508                 break;
4509         }
4510
4511         return ret;
4512 }
4513
4514 static u8 *
4515 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4516                         u8 **mc_addr_ptr, u32 *vmdq)
4517 {
4518         u8 *mc_addr;
4519
4520         *vmdq = 0;
4521         mc_addr = *mc_addr_ptr;
4522         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4523         return mc_addr;
4524 }
4525
4526 static int
4527 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4528                            struct ether_addr *mc_addr_set,
4529                            uint32_t nb_mc_addr)
4530 {
4531         struct ixgbe_hw *hw;
4532         u8 *mc_addr_list;
4533
4534         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4535         mc_addr_list = (u8 *)mc_addr_set;
4536         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4537                                          ixgbe_dev_addr_list_itr, TRUE);
4538 }
4539
4540 static int
4541 ixgbe_timesync_enable(struct rte_eth_dev *dev)
4542 {
4543         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4544         uint32_t tsync_ctl;
4545         uint32_t tsauxc;
4546
4547         /* Enable system time for platforms where it isn't on by default. */
4548         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
4549         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
4550         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
4551
4552         /* Start incrementing the register used to timestamp PTP packets. */
4553         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
4554
4555         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4556         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
4557                         (ETHER_TYPE_1588 |
4558                          IXGBE_ETQF_FILTER_EN |
4559                          IXGBE_ETQF_1588));
4560
4561         /* Enable timestamping of received PTP packets. */
4562         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4563         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
4564         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4565
4566         /* Enable timestamping of transmitted PTP packets. */
4567         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4568         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
4569         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4570
4571         return 0;
4572 }
4573
4574 static int
4575 ixgbe_timesync_disable(struct rte_eth_dev *dev)
4576 {
4577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578         uint32_t tsync_ctl;
4579
4580         /* Disable timestamping of transmitted PTP packets. */
4581         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4582         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
4583         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
4584
4585         /* Disable timestamping of received PTP packets. */
4586         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4587         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
4588         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
4589
4590         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4591         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
4592
4593         /* Stop incrementating the System Time registers. */
4594         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
4595
4596         return 0;
4597 }
4598
4599 static int
4600 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4601                                  struct timespec *timestamp,
4602                                  uint32_t flags __rte_unused)
4603 {
4604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605         uint32_t tsync_rxctl;
4606         uint32_t rx_stmpl;
4607         uint32_t rx_stmph;
4608
4609         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
4610         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
4611                 return -EINVAL;
4612
4613         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
4614         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
4615
4616         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
4617         timestamp->tv_nsec = 0;
4618
4619         return  0;
4620 }
4621
4622 static int
4623 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4624                                  struct timespec *timestamp)
4625 {
4626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627         uint32_t tsync_txctl;
4628         uint32_t tx_stmpl;
4629         uint32_t tx_stmph;
4630
4631         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
4632         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
4633                 return -EINVAL;
4634
4635         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
4636         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
4637
4638         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
4639         timestamp->tv_nsec = 0;
4640
4641         return  0;
4642 }
4643
4644 static struct rte_driver rte_ixgbe_driver = {
4645         .type = PMD_PDEV,
4646         .init = rte_ixgbe_pmd_init,
4647 };
4648
4649 static struct rte_driver rte_ixgbevf_driver = {
4650         .type = PMD_PDEV,
4651         .init = rte_ixgbevf_pmd_init,
4652 };
4653
4654 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4655 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);