drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 #include "rte_pmd_ixgbe.h"
  76
  77 /*
  78  * High threshold controlling when to start sending XOFF frames. Must be at
  79  * least 8 bytes less than receive packet buffer size. This value is in units
  80  * of 1024 bytes.
  81  */
  82 #define IXGBE_FC_HI    0x80
  83
  84 /*
  85  * Low threshold controlling when to start sending XON frames. This value is
  86  * in units of 1024 bytes.
  87  */
  88 #define IXGBE_FC_LO    0x40
  89
  90 /* Default minimum inter-interrupt interval for EITR configuration */
  91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  92
  93 /* Timer value included in XOFF frames. */
  94 #define IXGBE_FC_PAUSE 0x680
  95
  96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  97 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  98 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  99
 100 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 101 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 102 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 103
 104 /*
 105  *  Default values for RX/TX configuration
 106  */
 107 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 108 #define IXGBE_DEFAULT_RX_PTHRESH      8
 109 #define IXGBE_DEFAULT_RX_HTHRESH      8
 110 #define IXGBE_DEFAULT_RX_WTHRESH      0
 111
 112 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 113 #define IXGBE_DEFAULT_TX_PTHRESH      32
 114 #define IXGBE_DEFAULT_TX_HTHRESH      0
 115 #define IXGBE_DEFAULT_TX_WTHRESH      0
 116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 117
 118 /* Bit shift and mask */
 119 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 120 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 121 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 122 #define IXGBE_8_BIT_MASK   UINT8_MAX
 123
 124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 125
 126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 127
 128 #define IXGBE_HKEY_MAX_INDEX 10
 129
 130 /* Additional timesync values. */
 131 #define NSEC_PER_SEC             1000000000L
 132 #define IXGBE_INCVAL_10GB        0x66666666
 133 #define IXGBE_INCVAL_1GB         0x40000000
 134 #define IXGBE_INCVAL_100         0x50000000
 135 #define IXGBE_INCVAL_SHIFT_10GB  28
 136 #define IXGBE_INCVAL_SHIFT_1GB   24
 137 #define IXGBE_INCVAL_SHIFT_100   21
 138 #define IXGBE_INCVAL_SHIFT_82599 7
 139 #define IXGBE_INCPER_SHIFT_82599 24
 140
 141 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 142
 143 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 145 #define DEFAULT_ETAG_ETYPE                     0x893f
 146 #define IXGBE_ETAG_ETYPE                       0x00005084
 147 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 148 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 149 #define IXGBE_RAH_ADTYPE                       0x40000000
 150 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 151 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 154 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 155 #define IXGBE_VTEICR_MASK                      0x07
 156
 157 enum ixgbevf_xcast_modes {
 158         IXGBEVF_XCAST_MODE_NONE = 0,
 159         IXGBEVF_XCAST_MODE_MULTI,
 160         IXGBEVF_XCAST_MODE_ALLMULTI,
 161 };
 162
 163 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 164 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 165
 166 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 167 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250
 251 /* For Virtual Function support */
 252 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 253 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 254 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 256 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 257 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 258 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 259 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 260 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 261                 struct rte_eth_stats *stats);
 262 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 263 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 264                 uint16_t vlan_id, int on);
 265 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 266                 uint16_t queue, int on);
 267 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 268 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 269 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 270                                             uint16_t queue_id);
 271 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 272                                              uint16_t queue_id);
 273 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 274                                  uint8_t queue, uint8_t msix_vector);
 275 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 276 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 277 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 278
 279 /* For Eth VMDQ APIs support */
 280 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 281                 ether_addr * mac_addr, uint8_t on);
 282 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 283 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 284                 uint16_t rx_mask, uint8_t on);
 285 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 286 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on);
 287 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 288                 uint64_t pool_mask, uint8_t vlan_on);
 289 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 290                 struct rte_eth_mirror_conf *mirror_conf,
 291                 uint8_t rule_id, uint8_t on);
 292 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 293                 uint8_t rule_id);
 294 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 295                                           uint16_t queue_id);
 296 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 297                                            uint16_t queue_id);
 298 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 299                                uint8_t queue, uint8_t msix_vector);
 300 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 301
 302 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 303                 uint16_t queue_idx, uint16_t tx_rate);
 304 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 305                 uint16_t tx_rate, uint64_t q_msk);
 306
 307 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 308                                  struct ether_addr *mac_addr,
 309                                  uint32_t index, uint32_t pool);
 310 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 311 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 312                                              struct ether_addr *mac_addr);
 313 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 314                         struct rte_eth_syn_filter *filter,
 315                         bool add);
 316 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 317                         struct rte_eth_syn_filter *filter);
 318 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 319                         enum rte_filter_op filter_op,
 320                         void *arg);
 321 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 322                         struct ixgbe_5tuple_filter *filter);
 323 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 324                         struct ixgbe_5tuple_filter *filter);
 325 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 326                         struct rte_eth_ntuple_filter *filter,
 327                         bool add);
 328 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 329                                 enum rte_filter_op filter_op,
 330                                 void *arg);
 331 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 332                         struct rte_eth_ntuple_filter *filter);
 333 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 334                         struct rte_eth_ethertype_filter *filter,
 335                         bool add);
 336 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 337                                 enum rte_filter_op filter_op,
 338                                 void *arg);
 339 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 340                         struct rte_eth_ethertype_filter *filter);
 341 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 342                      enum rte_filter_type filter_type,
 343                      enum rte_filter_op filter_op,
 344                      void *arg);
 345 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 346
 347 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 348                                       struct ether_addr *mc_addr_set,
 349                                       uint32_t nb_mc_addr);
 350 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 351                                    struct rte_eth_dcb_info *dcb_info);
 352
 353 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 354 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 355                             struct rte_dev_reg_info *regs);
 356 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 357 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 358                                 struct rte_dev_eeprom_info *eeprom);
 359 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 360                                 struct rte_dev_eeprom_info *eeprom);
 361
 362 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 363 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 364                                 struct rte_dev_reg_info *regs);
 365
 366 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 367 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 368 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 369                                             struct timespec *timestamp,
 370                                             uint32_t flags);
 371 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 372                                             struct timespec *timestamp);
 373 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 374 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 375                                    struct timespec *timestamp);
 376 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 377                                    const struct timespec *timestamp);
 378 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 379                                           void *param);
 380
 381 static int ixgbe_dev_l2_tunnel_eth_type_conf
 382         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 383 static int ixgbe_dev_l2_tunnel_offload_set
 384         (struct rte_eth_dev *dev,
 385          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 386          uint32_t mask,
 387          uint8_t en);
 388 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 389                                              enum rte_filter_op filter_op,
 390                                              void *arg);
 391
 392 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 393                                          struct rte_eth_udp_tunnel *udp_tunnel);
 394 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 395                                          struct rte_eth_udp_tunnel *udp_tunnel);
 396
 397 /*
 398  * Define VF Stats MACRO for Non "cleared on read" register
 399  */
 400 #define UPDATE_VF_STAT(reg, last, cur)                          \
 401 {                                                               \
 402         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 403         cur += (latest - last) & UINT_MAX;                      \
 404         last = latest;                                          \
 405 }
 406
 407 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 408 {                                                                \
 409         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 410         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 411         u64 latest = ((new_msb << 32) | new_lsb);                \
 412         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 413         last = latest;                                           \
 414 }
 415
 416 #define IXGBE_SET_HWSTRIP(h, q) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (h)->bitmap[idx] |= 1 << bit;\
 420         } while (0)
 421
 422 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 423                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 424                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 425                 (h)->bitmap[idx] &= ~(1 << bit);\
 426         } while (0)
 427
 428 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 429                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 430                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 431                 (r) = (h)->bitmap[idx] >> bit & 1;\
 432         } while (0)
 433
 434 /*
 435  * The set of PCI devices this driver supports
 436  */
 437 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 483         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 491 #ifdef RTE_NIC_BYPASS
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 493 #endif
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 /*
 498  * The set of PCI devices this driver supports (for 82599 VF)
 499  */
 500 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 503         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 504         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 505         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 506         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 507         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 508         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 509         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 510         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 511         { .vendor_id = 0, /* sentinel */ },
 512 };
 513
 514 static const struct rte_eth_desc_lim rx_desc_lim = {
 515         .nb_max = IXGBE_MAX_RING_DESC,
 516         .nb_min = IXGBE_MIN_RING_DESC,
 517         .nb_align = IXGBE_RXD_ALIGN,
 518 };
 519
 520 static const struct rte_eth_desc_lim tx_desc_lim = {
 521         .nb_max = IXGBE_MAX_RING_DESC,
 522         .nb_min = IXGBE_MIN_RING_DESC,
 523         .nb_align = IXGBE_TXD_ALIGN,
 524         .nb_seg_max = IXGBE_TX_MAX_SEG,
 525         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 526 };
 527
 528 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 529         .dev_configure        = ixgbe_dev_configure,
 530         .dev_start            = ixgbe_dev_start,
 531         .dev_stop             = ixgbe_dev_stop,
 532         .dev_set_link_up    = ixgbe_dev_set_link_up,
 533         .dev_set_link_down  = ixgbe_dev_set_link_down,
 534         .dev_close            = ixgbe_dev_close,
 535         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 536         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 537         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 538         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 539         .link_update          = ixgbe_dev_link_update,
 540         .stats_get            = ixgbe_dev_stats_get,
 541         .xstats_get           = ixgbe_dev_xstats_get,
 542         .stats_reset          = ixgbe_dev_stats_reset,
 543         .xstats_reset         = ixgbe_dev_xstats_reset,
 544         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 545         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 546         .fw_version_get       = ixgbe_fw_version_get,
 547         .dev_infos_get        = ixgbe_dev_info_get,
 548         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 549         .mtu_set              = ixgbe_dev_mtu_set,
 550         .vlan_filter_set      = ixgbe_vlan_filter_set,
 551         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 552         .vlan_offload_set     = ixgbe_vlan_offload_set,
 553         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 554         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 555         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 556         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 557         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 558         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 559         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 560         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 561         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 562         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 563         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 564         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 565         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 566         .dev_led_on           = ixgbe_dev_led_on,
 567         .dev_led_off          = ixgbe_dev_led_off,
 568         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 569         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 570         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 571         .mac_addr_add         = ixgbe_add_rar,
 572         .mac_addr_remove      = ixgbe_remove_rar,
 573         .mac_addr_set         = ixgbe_set_default_mac_addr,
 574         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 575         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 576         .mirror_rule_set      = ixgbe_mirror_rule_set,
 577         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 578         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 579         .set_vf_rx            = ixgbe_set_pool_rx,
 580         .set_vf_tx            = ixgbe_set_pool_tx,
 581         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 582         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 583         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 584         .reta_update          = ixgbe_dev_rss_reta_update,
 585         .reta_query           = ixgbe_dev_rss_reta_query,
 586 #ifdef RTE_NIC_BYPASS
 587         .bypass_init          = ixgbe_bypass_init,
 588         .bypass_state_set     = ixgbe_bypass_state_store,
 589         .bypass_state_show    = ixgbe_bypass_state_show,
 590         .bypass_event_set     = ixgbe_bypass_event_store,
 591         .bypass_event_show    = ixgbe_bypass_event_show,
 592         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 593         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 594         .bypass_ver_show      = ixgbe_bypass_ver_show,
 595         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 596 #endif /* RTE_NIC_BYPASS */
 597         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 598         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 599         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 600         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 601         .rxq_info_get         = ixgbe_rxq_info_get,
 602         .txq_info_get         = ixgbe_txq_info_get,
 603         .timesync_enable      = ixgbe_timesync_enable,
 604         .timesync_disable     = ixgbe_timesync_disable,
 605         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 606         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 607         .get_reg              = ixgbe_get_regs,
 608         .get_eeprom_length    = ixgbe_get_eeprom_length,
 609         .get_eeprom           = ixgbe_get_eeprom,
 610         .set_eeprom           = ixgbe_set_eeprom,
 611         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 612         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 613         .timesync_read_time   = ixgbe_timesync_read_time,
 614         .timesync_write_time  = ixgbe_timesync_write_time,
 615         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 616         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 617         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 618         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 619 };
 620
 621 /*
 622  * dev_ops for virtual function, bare necessities for basic vf
 623  * operation have been implemented
 624  */
 625 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 626         .dev_configure        = ixgbevf_dev_configure,
 627         .dev_start            = ixgbevf_dev_start,
 628         .dev_stop             = ixgbevf_dev_stop,
 629         .link_update          = ixgbe_dev_link_update,
 630         .stats_get            = ixgbevf_dev_stats_get,
 631         .xstats_get           = ixgbevf_dev_xstats_get,
 632         .stats_reset          = ixgbevf_dev_stats_reset,
 633         .xstats_reset         = ixgbevf_dev_stats_reset,
 634         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 635         .dev_close            = ixgbevf_dev_close,
 636         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 637         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 638         .dev_infos_get        = ixgbevf_dev_info_get,
 639         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 640         .mtu_set              = ixgbevf_dev_set_mtu,
 641         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 642         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 643         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 644         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 645         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 646         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 647         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 648         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 649         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 650         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 651         .mac_addr_add         = ixgbevf_add_mac_addr,
 652         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 653         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 654         .rxq_info_get         = ixgbe_rxq_info_get,
 655         .txq_info_get         = ixgbe_txq_info_get,
 656         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 657         .get_reg              = ixgbevf_get_regs,
 658         .reta_update          = ixgbe_dev_rss_reta_update,
 659         .reta_query           = ixgbe_dev_rss_reta_query,
 660         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 661         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 662 };
 663
 664 /* store statistics names and its offset in stats structure */
 665 struct rte_ixgbe_xstats_name_off {
 666         char name[RTE_ETH_XSTATS_NAME_SIZE];
 667         unsigned offset;
 668 };
 669
 670 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 671         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 672         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 673         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 674         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 675         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 676         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 677         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 678         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 679         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 680         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 681         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 682         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 683         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 684         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 685         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 686                 prc1023)},
 687         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 688                 prc1522)},
 689         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 690         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 691         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 692         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 693         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 694         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 695         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 696         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 697         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 698         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 699         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 700         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 701         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 702         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 703         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 704         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 705         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 706                 ptc1023)},
 707         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 708                 ptc1522)},
 709         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 710         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 711         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 712         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 713
 714         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 715                 fdirustat_add)},
 716         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 717                 fdirustat_remove)},
 718         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 719                 fdirfstat_fadd)},
 720         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 721                 fdirfstat_fremove)},
 722         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 723                 fdirmatch)},
 724         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 725                 fdirmiss)},
 726
 727         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 728         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 729         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 730                 fclast)},
 731         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 732         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 733         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 734         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 735         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 736                 fcoe_noddp)},
 737         {"rx_fcoe_no_direct_data_placement_ext_buff",
 738                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 739
 740         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 741                 lxontxc)},
 742         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 743                 lxonrxc)},
 744         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 745                 lxofftxc)},
 746         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 747                 lxoffrxc)},
 748         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 749 };
 750
 751 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 752                            sizeof(rte_ixgbe_stats_strings[0]))
 753
 754 /* MACsec statistics */
 755 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 756         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 757                 out_pkts_untagged)},
 758         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 759                 out_pkts_encrypted)},
 760         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 761                 out_pkts_protected)},
 762         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 763                 out_octets_encrypted)},
 764         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 765                 out_octets_protected)},
 766         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_untagged)},
 768         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_badtag)},
 770         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_nosci)},
 772         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unknownsci)},
 774         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 775                 in_octets_decrypted)},
 776         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 777                 in_octets_validated)},
 778         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_unchecked)},
 780         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 781                 in_pkts_delayed)},
 782         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 783                 in_pkts_late)},
 784         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 785                 in_pkts_ok)},
 786         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 787                 in_pkts_invalid)},
 788         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 789                 in_pkts_notvalid)},
 790         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 791                 in_pkts_unusedsa)},
 792         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 793                 in_pkts_notusingsa)},
 794 };
 795
 796 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 797                            sizeof(rte_ixgbe_macsec_strings[0]))
 798
 799 /* Per-queue statistics */
 800 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 801         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 802         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 803         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 804         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 805 };
 806
 807 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 808                            sizeof(rte_ixgbe_rxq_strings[0]))
 809 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 810
 811 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 812         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 813         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 814         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 815                 pxon2offc)},
 816 };
 817
 818 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 819                            sizeof(rte_ixgbe_txq_strings[0]))
 820 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 821
 822 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 823         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 824 };
 825
 826 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 827                 sizeof(rte_ixgbevf_stats_strings[0]))
 828
 829 /**
 830  * Atomically reads the link status information from global
 831  * structure rte_eth_dev.
 832  *
 833  * @param dev
 834  *   - Pointer to the structure rte_eth_dev to read from.
 835  *   - Pointer to the buffer to be saved with the link status.
 836  *
 837  * @return
 838  *   - On success, zero.
 839  *   - On failure, negative value.
 840  */
 841 static inline int
 842 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 843                                 struct rte_eth_link *link)
 844 {
 845         struct rte_eth_link *dst = link;
 846         struct rte_eth_link *src = &(dev->data->dev_link);
 847
 848         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 849                                         *(uint64_t *)src) == 0)
 850                 return -1;
 851
 852         return 0;
 853 }
 854
 855 /**
 856  * Atomically writes the link status information into global
 857  * structure rte_eth_dev.
 858  *
 859  * @param dev
 860  *   - Pointer to the structure rte_eth_dev to read from.
 861  *   - Pointer to the buffer to be saved with the link status.
 862  *
 863  * @return
 864  *   - On success, zero.
 865  *   - On failure, negative value.
 866  */
 867 static inline int
 868 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 869                                 struct rte_eth_link *link)
 870 {
 871         struct rte_eth_link *dst = &(dev->data->dev_link);
 872         struct rte_eth_link *src = link;
 873
 874         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 875                                         *(uint64_t *)src) == 0)
 876                 return -1;
 877
 878         return 0;
 879 }
 880
 881 /*
 882  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 883  */
 884 static inline int
 885 ixgbe_is_sfp(struct ixgbe_hw *hw)
 886 {
 887         switch (hw->phy.type) {
 888         case ixgbe_phy_sfp_avago:
 889         case ixgbe_phy_sfp_ftl:
 890         case ixgbe_phy_sfp_intel:
 891         case ixgbe_phy_sfp_unknown:
 892         case ixgbe_phy_sfp_passive_tyco:
 893         case ixgbe_phy_sfp_passive_unknown:
 894                 return 1;
 895         default:
 896                 return 0;
 897         }
 898 }
 899
 900 static inline int32_t
 901 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 902 {
 903         uint32_t ctrl_ext;
 904         int32_t status;
 905
 906         status = ixgbe_reset_hw(hw);
 907
 908         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 909         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 910         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 911         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 912         IXGBE_WRITE_FLUSH(hw);
 913
 914         return status;
 915 }
 916
 917 static inline void
 918 ixgbe_enable_intr(struct rte_eth_dev *dev)
 919 {
 920         struct ixgbe_interrupt *intr =
 921                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 922         struct ixgbe_hw *hw =
 923                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 924
 925         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 926         IXGBE_WRITE_FLUSH(hw);
 927 }
 928
 929 /*
 930  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 931  */
 932 static void
 933 ixgbe_disable_intr(struct ixgbe_hw *hw)
 934 {
 935         PMD_INIT_FUNC_TRACE();
 936
 937         if (hw->mac.type == ixgbe_mac_82598EB) {
 938                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 939         } else {
 940                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 941                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 942                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 943         }
 944         IXGBE_WRITE_FLUSH(hw);
 945 }
 946
 947 /*
 948  * This function resets queue statistics mapping registers.
 949  * From Niantic datasheet, Initialization of Statistics section:
 950  * "...if software requires the queue counters, the RQSMR and TQSM registers
 951  * must be re-programmed following a device reset.
 952  */
 953 static void
 954 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 955 {
 956         uint32_t i;
 957
 958         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 959                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 960                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 961         }
 962 }
 963
 964
 965 static int
 966 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 967                                   uint16_t queue_id,
 968                                   uint8_t stat_idx,
 969                                   uint8_t is_rx)
 970 {
 971 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 972 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 973 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 974
 975         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 976         struct ixgbe_stat_mapping_registers *stat_mappings =
 977                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 978         uint32_t qsmr_mask = 0;
 979         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 980         uint32_t q_map;
 981         uint8_t n, offset;
 982
 983         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 984                 (hw->mac.type != ixgbe_mac_X540) &&
 985                 (hw->mac.type != ixgbe_mac_X550) &&
 986                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 987                 (hw->mac.type != ixgbe_mac_X550EM_a))
 988                 return -ENOSYS;
 989
 990         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 991                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 992                      queue_id, stat_idx);
 993
 994         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 995         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 996                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 997                 return -EIO;
 998         }
 999         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
1000
1001         /* Now clear any previous stat_idx set */
1002         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1003         if (!is_rx)
1004                 stat_mappings->tqsm[n] &= ~clearing_mask;
1005         else
1006                 stat_mappings->rqsmr[n] &= ~clearing_mask;
1007
1008         q_map = (uint32_t)stat_idx;
1009         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
1010         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
1011         if (!is_rx)
1012                 stat_mappings->tqsm[n] |= qsmr_mask;
1013         else
1014                 stat_mappings->rqsmr[n] |= qsmr_mask;
1015
1016         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1017                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1018                      queue_id, stat_idx);
1019         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1020                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1021
1022         /* Now write the mapping in the appropriate register */
1023         if (is_rx) {
1024                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1025                              stat_mappings->rqsmr[n], n);
1026                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1027         } else {
1028                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1029                              stat_mappings->tqsm[n], n);
1030                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1031         }
1032         return 0;
1033 }
1034
1035 static void
1036 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1037 {
1038         struct ixgbe_stat_mapping_registers *stat_mappings =
1039                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1040         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1041         int i;
1042
1043         /* write whatever was in stat mapping table to the NIC */
1044         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1045                 /* rx */
1046                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1047
1048                 /* tx */
1049                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1050         }
1051 }
1052
1053 static void
1054 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1055 {
1056         uint8_t i;
1057         struct ixgbe_dcb_tc_config *tc;
1058         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1059
1060         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1061         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1062         for (i = 0; i < dcb_max_tc; i++) {
1063                 tc = &dcb_config->tc_config[i];
1064                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1065                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1066                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1067                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1068                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1069                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1070                 tc->pfc = ixgbe_dcb_pfc_disabled;
1071         }
1072
1073         /* Initialize default user to priority mapping, UPx->TC0 */
1074         tc = &dcb_config->tc_config[0];
1075         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1076         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1077         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1078                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1079                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1080         }
1081         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1082         dcb_config->pfc_mode_enable = false;
1083         dcb_config->vt_mode = true;
1084         dcb_config->round_robin_enable = false;
1085         /* support all DCB capabilities in 82599 */
1086         dcb_config->support.capabilities = 0xFF;
1087
1088         /*we only support 4 Tcs for X540, X550 */
1089         if (hw->mac.type == ixgbe_mac_X540 ||
1090                 hw->mac.type == ixgbe_mac_X550 ||
1091                 hw->mac.type == ixgbe_mac_X550EM_x ||
1092                 hw->mac.type == ixgbe_mac_X550EM_a) {
1093                 dcb_config->num_tcs.pg_tcs = 4;
1094                 dcb_config->num_tcs.pfc_tcs = 4;
1095         }
1096 }
1097
1098 /*
1099  * Ensure that all locks are released before first NVM or PHY access
1100  */
1101 static void
1102 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1103 {
1104         uint16_t mask;
1105
1106         /*
1107          * Phy lock should not fail in this early stage. If this is the case,
1108          * it is due to an improper exit of the application.
1109          * So force the release of the faulty lock. Release of common lock
1110          * is done automatically by swfw_sync function.
1111          */
1112         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117
1118         /*
1119          * These ones are more tricky since they are common to all ports; but
1120          * swfw_sync retries last long enough (1s) to be almost sure that if
1121          * lock can not be taken it is due to an improper lock of the
1122          * semaphore.
1123          */
1124         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1125         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1126                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1127         }
1128         ixgbe_release_swfw_semaphore(hw, mask);
1129 }
1130
1131 /*
1132  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1133  * It returns 0 on success.
1134  */
1135 static int
1136 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1137 {
1138         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1139         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1140         struct ixgbe_hw *hw =
1141                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1142         struct ixgbe_vfta *shadow_vfta =
1143                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1144         struct ixgbe_hwstrip *hwstrip =
1145                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1146         struct ixgbe_dcb_config *dcb_config =
1147                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1148         struct ixgbe_filter_info *filter_info =
1149                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1150         uint32_t ctrl_ext;
1151         uint16_t csum;
1152         int diag, i;
1153
1154         PMD_INIT_FUNC_TRACE();
1155
1156         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1157         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1158         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1159         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1160
1161         /*
1162          * For secondary processes, we don't initialise any further as primary
1163          * has already done this work. Only check we don't need a different
1164          * RX and TX function.
1165          */
1166         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1167                 struct ixgbe_tx_queue *txq;
1168                 /* TX queue function in primary, set by last queue initialized
1169                  * Tx queue may not initialized by primary process
1170                  */
1171                 if (eth_dev->data->tx_queues) {
1172                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1173                         ixgbe_set_tx_function(eth_dev, txq);
1174                 } else {
1175                         /* Use default TX function if we get here */
1176                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1177                                      "Using default TX function.");
1178                 }
1179
1180                 ixgbe_set_rx_function(eth_dev);
1181
1182                 return 0;
1183         }
1184
1185         rte_eth_copy_pci_info(eth_dev, pci_dev);
1186         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1187
1188         /* Vendor and Device ID need to be set before init of shared code */
1189         hw->device_id = pci_dev->id.device_id;
1190         hw->vendor_id = pci_dev->id.vendor_id;
1191         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1192         hw->allow_unsupported_sfp = 1;
1193
1194         /* Initialize the shared code (base driver) */
1195 #ifdef RTE_NIC_BYPASS
1196         diag = ixgbe_bypass_init_shared_code(hw);
1197 #else
1198         diag = ixgbe_init_shared_code(hw);
1199 #endif /* RTE_NIC_BYPASS */
1200
1201         if (diag != IXGBE_SUCCESS) {
1202                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1203                 return -EIO;
1204         }
1205
1206         /* pick up the PCI bus settings for reporting later */
1207         ixgbe_get_bus_info(hw);
1208
1209         /* Unlock any pending hardware semaphore */
1210         ixgbe_swfw_lock_reset(hw);
1211
1212         /* Initialize DCB configuration*/
1213         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1214         ixgbe_dcb_init(hw, dcb_config);
1215         /* Get Hardware Flow Control setting */
1216         hw->fc.requested_mode = ixgbe_fc_full;
1217         hw->fc.current_mode = ixgbe_fc_full;
1218         hw->fc.pause_time = IXGBE_FC_PAUSE;
1219         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1220                 hw->fc.low_water[i] = IXGBE_FC_LO;
1221                 hw->fc.high_water[i] = IXGBE_FC_HI;
1222         }
1223         hw->fc.send_xon = 1;
1224
1225         /* Make sure we have a good EEPROM before we read from it */
1226         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1227         if (diag != IXGBE_SUCCESS) {
1228                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1229                 return -EIO;
1230         }
1231
1232 #ifdef RTE_NIC_BYPASS
1233         diag = ixgbe_bypass_init_hw(hw);
1234 #else
1235         diag = ixgbe_init_hw(hw);
1236 #endif /* RTE_NIC_BYPASS */
1237
1238         /*
1239          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1240          * is called too soon after the kernel driver unbinding/binding occurs.
1241          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1242          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1243          * also called. See ixgbe_identify_phy_82599(). The reason for the
1244          * failure is not known, and only occuts when virtualisation features
1245          * are disabled in the bios. A delay of 100ms  was found to be enough by
1246          * trial-and-error, and is doubled to be safe.
1247          */
1248         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1249                 rte_delay_ms(200);
1250                 diag = ixgbe_init_hw(hw);
1251         }
1252
1253         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1254                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1255                              "LOM.  Please be aware there may be issues associated "
1256                              "with your hardware.");
1257                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1258                              "please contact your Intel or hardware representative "
1259                              "who provided you with this hardware.");
1260         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1261                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1262         if (diag) {
1263                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1264                 return -EIO;
1265         }
1266
1267         /* Reset the hw statistics */
1268         ixgbe_dev_stats_reset(eth_dev);
1269
1270         /* disable interrupt */
1271         ixgbe_disable_intr(hw);
1272
1273         /* reset mappings for queue statistics hw counters*/
1274         ixgbe_reset_qstat_mappings(hw);
1275
1276         /* Allocate memory for storing MAC addresses */
1277         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1278                                                hw->mac.num_rar_entries, 0);
1279         if (eth_dev->data->mac_addrs == NULL) {
1280                 PMD_INIT_LOG(ERR,
1281                              "Failed to allocate %u bytes needed to store "
1282                              "MAC addresses",
1283                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1284                 return -ENOMEM;
1285         }
1286         /* Copy the permanent MAC address */
1287         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1288                         &eth_dev->data->mac_addrs[0]);
1289
1290         /* Allocate memory for storing hash filter MAC addresses */
1291         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1292                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1293         if (eth_dev->data->hash_mac_addrs == NULL) {
1294                 PMD_INIT_LOG(ERR,
1295                              "Failed to allocate %d bytes needed to store MAC addresses",
1296                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1297                 return -ENOMEM;
1298         }
1299
1300         /* initialize the vfta */
1301         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1302
1303         /* initialize the hw strip bitmap*/
1304         memset(hwstrip, 0, sizeof(*hwstrip));
1305
1306         /* initialize PF if max_vfs not zero */
1307         ixgbe_pf_host_init(eth_dev);
1308
1309         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1310         /* let hardware know driver is loaded */
1311         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1312         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1313         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1314         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1315         IXGBE_WRITE_FLUSH(hw);
1316
1317         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1318                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1319                              (int) hw->mac.type, (int) hw->phy.type,
1320                              (int) hw->phy.sfp_type);
1321         else
1322                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1323                              (int) hw->mac.type, (int) hw->phy.type);
1324
1325         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1326                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1327                      pci_dev->id.device_id);
1328
1329         rte_intr_callback_register(intr_handle,
1330                                    ixgbe_dev_interrupt_handler, eth_dev);
1331
1332         /* enable uio/vfio intr/eventfd mapping */
1333         rte_intr_enable(intr_handle);
1334
1335         /* enable support intr */
1336         ixgbe_enable_intr(eth_dev);
1337
1338         /* initialize 5tuple filter list */
1339         TAILQ_INIT(&filter_info->fivetuple_list);
1340         memset(filter_info->fivetuple_mask, 0,
1341                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1342
1343         return 0;
1344 }
1345
1346 static int
1347 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1348 {
1349         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1350         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1351         struct ixgbe_hw *hw;
1352
1353         PMD_INIT_FUNC_TRACE();
1354
1355         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1356                 return -EPERM;
1357
1358         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1359
1360         if (hw->adapter_stopped == 0)
1361                 ixgbe_dev_close(eth_dev);
1362
1363         eth_dev->dev_ops = NULL;
1364         eth_dev->rx_pkt_burst = NULL;
1365         eth_dev->tx_pkt_burst = NULL;
1366
1367         /* Unlock any pending hardware semaphore */
1368         ixgbe_swfw_lock_reset(hw);
1369
1370         /* disable uio intr before callback unregister */
1371         rte_intr_disable(intr_handle);
1372         rte_intr_callback_unregister(intr_handle,
1373                                      ixgbe_dev_interrupt_handler, eth_dev);
1374
1375         /* uninitialize PF if max_vfs not zero */
1376         ixgbe_pf_host_uninit(eth_dev);
1377
1378         rte_free(eth_dev->data->mac_addrs);
1379         eth_dev->data->mac_addrs = NULL;
1380
1381         rte_free(eth_dev->data->hash_mac_addrs);
1382         eth_dev->data->hash_mac_addrs = NULL;
1383
1384         return 0;
1385 }
1386
1387 /*
1388  * Negotiate mailbox API version with the PF.
1389  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1390  * Then we try to negotiate starting with the most recent one.
1391  * If all negotiation attempts fail, then we will proceed with
1392  * the default one (ixgbe_mbox_api_10).
1393  */
1394 static void
1395 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1396 {
1397         int32_t i;
1398
1399         /* start with highest supported, proceed down */
1400         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1401                 ixgbe_mbox_api_12,
1402                 ixgbe_mbox_api_11,
1403                 ixgbe_mbox_api_10,
1404         };
1405
1406         for (i = 0;
1407                         i != RTE_DIM(sup_ver) &&
1408                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1409                         i++)
1410                 ;
1411 }
1412
1413 static void
1414 generate_random_mac_addr(struct ether_addr *mac_addr)
1415 {
1416         uint64_t random;
1417
1418         /* Set Organizationally Unique Identifier (OUI) prefix. */
1419         mac_addr->addr_bytes[0] = 0x00;
1420         mac_addr->addr_bytes[1] = 0x09;
1421         mac_addr->addr_bytes[2] = 0xC0;
1422         /* Force indication of locally assigned MAC address. */
1423         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1424         /* Generate the last 3 bytes of the MAC address with a random number. */
1425         random = rte_rand();
1426         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1427 }
1428
1429 /*
1430  * Virtual Function device init
1431  */
1432 static int
1433 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1434 {
1435         int diag;
1436         uint32_t tc, tcs;
1437         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1438         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1439         struct ixgbe_hw *hw =
1440                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1441         struct ixgbe_vfta *shadow_vfta =
1442                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1443         struct ixgbe_hwstrip *hwstrip =
1444                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1445         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1446
1447         PMD_INIT_FUNC_TRACE();
1448
1449         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1450         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1451         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1452
1453         /* for secondary processes, we don't initialise any further as primary
1454          * has already done this work. Only check we don't need a different
1455          * RX function
1456          */
1457         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1458                 struct ixgbe_tx_queue *txq;
1459                 /* TX queue function in primary, set by last queue initialized
1460                  * Tx queue may not initialized by primary process
1461                  */
1462                 if (eth_dev->data->tx_queues) {
1463                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1464                         ixgbe_set_tx_function(eth_dev, txq);
1465                 } else {
1466                         /* Use default TX function if we get here */
1467                         PMD_INIT_LOG(NOTICE,
1468                                      "No TX queues configured yet. Using default TX function.");
1469                 }
1470
1471                 ixgbe_set_rx_function(eth_dev);
1472
1473                 return 0;
1474         }
1475
1476         rte_eth_copy_pci_info(eth_dev, pci_dev);
1477         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1478
1479         hw->device_id = pci_dev->id.device_id;
1480         hw->vendor_id = pci_dev->id.vendor_id;
1481         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1482
1483         /* initialize the vfta */
1484         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1485
1486         /* initialize the hw strip bitmap*/
1487         memset(hwstrip, 0, sizeof(*hwstrip));
1488
1489         /* Initialize the shared code (base driver) */
1490         diag = ixgbe_init_shared_code(hw);
1491         if (diag != IXGBE_SUCCESS) {
1492                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1493                 return -EIO;
1494         }
1495
1496         /* init_mailbox_params */
1497         hw->mbx.ops.init_params(hw);
1498
1499         /* Reset the hw statistics */
1500         ixgbevf_dev_stats_reset(eth_dev);
1501
1502         /* Disable the interrupts for VF */
1503         ixgbevf_intr_disable(hw);
1504
1505         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1506         diag = hw->mac.ops.reset_hw(hw);
1507
1508         /*
1509          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1510          * the underlying PF driver has not assigned a MAC address to the VF.
1511          * In this case, assign a random MAC address.
1512          */
1513         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1514                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1515                 return diag;
1516         }
1517
1518         /* negotiate mailbox API version to use with the PF. */
1519         ixgbevf_negotiate_api(hw);
1520
1521         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1522         ixgbevf_get_queues(hw, &tcs, &tc);
1523
1524         /* Allocate memory for storing MAC addresses */
1525         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1526                                                hw->mac.num_rar_entries, 0);
1527         if (eth_dev->data->mac_addrs == NULL) {
1528                 PMD_INIT_LOG(ERR,
1529                              "Failed to allocate %u bytes needed to store "
1530                              "MAC addresses",
1531                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1532                 return -ENOMEM;
1533         }
1534
1535         /* Generate a random MAC address, if none was assigned by PF. */
1536         if (is_zero_ether_addr(perm_addr)) {
1537                 generate_random_mac_addr(perm_addr);
1538                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1539                 if (diag) {
1540                         rte_free(eth_dev->data->mac_addrs);
1541                         eth_dev->data->mac_addrs = NULL;
1542                         return diag;
1543                 }
1544                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1545                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1546                              "%02x:%02x:%02x:%02x:%02x:%02x",
1547                              perm_addr->addr_bytes[0],
1548                              perm_addr->addr_bytes[1],
1549                              perm_addr->addr_bytes[2],
1550                              perm_addr->addr_bytes[3],
1551                              perm_addr->addr_bytes[4],
1552                              perm_addr->addr_bytes[5]);
1553         }
1554
1555         /* Copy the permanent MAC address */
1556         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1557
1558         /* reset the hardware with the new settings */
1559         diag = hw->mac.ops.start_hw(hw);
1560         switch (diag) {
1561         case  0:
1562                 break;
1563
1564         default:
1565                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1566                 return -EIO;
1567         }
1568
1569         rte_intr_callback_register(intr_handle,
1570                                    ixgbevf_dev_interrupt_handler, eth_dev);
1571         rte_intr_enable(intr_handle);
1572         ixgbevf_intr_enable(hw);
1573
1574         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1575                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1576                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1577
1578         return 0;
1579 }
1580
1581 /* Virtual Function device uninit */
1582
1583 static int
1584 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1585 {
1586         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1587         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1588         struct ixgbe_hw *hw;
1589
1590         PMD_INIT_FUNC_TRACE();
1591
1592         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1593                 return -EPERM;
1594
1595         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1596
1597         if (hw->adapter_stopped == 0)
1598                 ixgbevf_dev_close(eth_dev);
1599
1600         eth_dev->dev_ops = NULL;
1601         eth_dev->rx_pkt_burst = NULL;
1602         eth_dev->tx_pkt_burst = NULL;
1603
1604         /* Disable the interrupts for VF */
1605         ixgbevf_intr_disable(hw);
1606
1607         rte_free(eth_dev->data->mac_addrs);
1608         eth_dev->data->mac_addrs = NULL;
1609
1610         rte_intr_disable(intr_handle);
1611         rte_intr_callback_unregister(intr_handle,
1612                                      ixgbevf_dev_interrupt_handler, eth_dev);
1613
1614         return 0;
1615 }
1616
1617 static struct eth_driver rte_ixgbe_pmd = {
1618         .pci_drv = {
1619                 .id_table = pci_id_ixgbe_map,
1620                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1621                 .probe = rte_eth_dev_pci_probe,
1622                 .remove = rte_eth_dev_pci_remove,
1623         },
1624         .eth_dev_init = eth_ixgbe_dev_init,
1625         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1626         .dev_private_size = sizeof(struct ixgbe_adapter),
1627 };
1628
1629 /*
1630  * virtual function driver struct
1631  */
1632 static struct eth_driver rte_ixgbevf_pmd = {
1633         .pci_drv = {
1634                 .id_table = pci_id_ixgbevf_map,
1635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1636                 .probe = rte_eth_dev_pci_probe,
1637                 .remove = rte_eth_dev_pci_remove,
1638         },
1639         .eth_dev_init = eth_ixgbevf_dev_init,
1640         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1641         .dev_private_size = sizeof(struct ixgbe_adapter),
1642 };
1643
1644 static int
1645 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1646 {
1647         struct ixgbe_hw *hw =
1648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1649         struct ixgbe_vfta *shadow_vfta =
1650                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1651         uint32_t vfta;
1652         uint32_t vid_idx;
1653         uint32_t vid_bit;
1654
1655         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1656         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1657         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1658         if (on)
1659                 vfta |= vid_bit;
1660         else
1661                 vfta &= ~vid_bit;
1662         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1663
1664         /* update local VFTA copy */
1665         shadow_vfta->vfta[vid_idx] = vfta;
1666
1667         return 0;
1668 }
1669
1670 static void
1671 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1672 {
1673         if (on)
1674                 ixgbe_vlan_hw_strip_enable(dev, queue);
1675         else
1676                 ixgbe_vlan_hw_strip_disable(dev, queue);
1677 }
1678
1679 static int
1680 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1681                     enum rte_vlan_type vlan_type,
1682                     uint16_t tpid)
1683 {
1684         struct ixgbe_hw *hw =
1685                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1686         int ret = 0;
1687         uint32_t reg;
1688         uint32_t qinq;
1689
1690         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1691         qinq &= IXGBE_DMATXCTL_GDV;
1692
1693         switch (vlan_type) {
1694         case ETH_VLAN_TYPE_INNER:
1695                 if (qinq) {
1696                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1697                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1698                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1699                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1700                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1701                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1702                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1703                 } else {
1704                         ret = -ENOTSUP;
1705                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1706                                     " by single VLAN");
1707                 }
1708                 break;
1709         case ETH_VLAN_TYPE_OUTER:
1710                 if (qinq) {
1711                         /* Only the high 16-bits is valid */
1712                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1713                                         IXGBE_EXVET_VET_EXT_SHIFT);
1714                 } else {
1715                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1716                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1717                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1718                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1719                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1720                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1721                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1722                 }
1723
1724                 break;
1725         default:
1726                 ret = -EINVAL;
1727                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1728                 break;
1729         }
1730
1731         return ret;
1732 }
1733
1734 void
1735 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1736 {
1737         struct ixgbe_hw *hw =
1738                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739         uint32_t vlnctrl;
1740
1741         PMD_INIT_FUNC_TRACE();
1742
1743         /* Filter Table Disable */
1744         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1745         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1746
1747         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1748 }
1749
1750 void
1751 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1752 {
1753         struct ixgbe_hw *hw =
1754                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1755         struct ixgbe_vfta *shadow_vfta =
1756                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1757         uint32_t vlnctrl;
1758         uint16_t i;
1759
1760         PMD_INIT_FUNC_TRACE();
1761
1762         /* Filter Table Enable */
1763         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1764         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1765         vlnctrl |= IXGBE_VLNCTRL_VFE;
1766
1767         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1768
1769         /* write whatever is in local vfta copy */
1770         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1771                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1772 }
1773
1774 static void
1775 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1776 {
1777         struct ixgbe_hwstrip *hwstrip =
1778                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1779         struct ixgbe_rx_queue *rxq;
1780
1781         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1782                 return;
1783
1784         if (on)
1785                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1786         else
1787                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1788
1789         if (queue >= dev->data->nb_rx_queues)
1790                 return;
1791
1792         rxq = dev->data->rx_queues[queue];
1793
1794         if (on)
1795                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1796         else
1797                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1798 }
1799
1800 static void
1801 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1802 {
1803         struct ixgbe_hw *hw =
1804                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         uint32_t ctrl;
1806
1807         PMD_INIT_FUNC_TRACE();
1808
1809         if (hw->mac.type == ixgbe_mac_82598EB) {
1810                 /* No queue level support */
1811                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1812                 return;
1813         }
1814
1815         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1816         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1817         ctrl &= ~IXGBE_RXDCTL_VME;
1818         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1819
1820         /* record those setting for HW strip per queue */
1821         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1822 }
1823
1824 static void
1825 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1826 {
1827         struct ixgbe_hw *hw =
1828                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         uint32_t ctrl;
1830
1831         PMD_INIT_FUNC_TRACE();
1832
1833         if (hw->mac.type == ixgbe_mac_82598EB) {
1834                 /* No queue level supported */
1835                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1836                 return;
1837         }
1838
1839         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1840         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1841         ctrl |= IXGBE_RXDCTL_VME;
1842         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1843
1844         /* record those setting for HW strip per queue */
1845         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1846 }
1847
1848 void
1849 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1850 {
1851         struct ixgbe_hw *hw =
1852                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         uint32_t ctrl;
1854         uint16_t i;
1855         struct ixgbe_rx_queue *rxq;
1856
1857         PMD_INIT_FUNC_TRACE();
1858
1859         if (hw->mac.type == ixgbe_mac_82598EB) {
1860                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1861                 ctrl &= ~IXGBE_VLNCTRL_VME;
1862                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1863         } else {
1864                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1865                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1866                         rxq = dev->data->rx_queues[i];
1867                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1868                         ctrl &= ~IXGBE_RXDCTL_VME;
1869                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1870
1871                         /* record those setting for HW strip per queue */
1872                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1873                 }
1874         }
1875 }
1876
1877 void
1878 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         uint32_t ctrl;
1883         uint16_t i;
1884         struct ixgbe_rx_queue *rxq;
1885
1886         PMD_INIT_FUNC_TRACE();
1887
1888         if (hw->mac.type == ixgbe_mac_82598EB) {
1889                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890                 ctrl |= IXGBE_VLNCTRL_VME;
1891                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1892         } else {
1893                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1894                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1895                         rxq = dev->data->rx_queues[i];
1896                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
1897                         ctrl |= IXGBE_RXDCTL_VME;
1898                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
1899
1900                         /* record those setting for HW strip per queue */
1901                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1902                 }
1903         }
1904 }
1905
1906 static void
1907 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1908 {
1909         struct ixgbe_hw *hw =
1910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         uint32_t ctrl;
1912
1913         PMD_INIT_FUNC_TRACE();
1914
1915         /* DMATXCTRL: Geric Double VLAN Disable */
1916         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1917         ctrl &= ~IXGBE_DMATXCTL_GDV;
1918         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1919
1920         /* CTRL_EXT: Global Double VLAN Disable */
1921         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1922         ctrl &= ~IXGBE_EXTENDED_VLAN;
1923         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1924
1925 }
1926
1927 static void
1928 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1929 {
1930         struct ixgbe_hw *hw =
1931                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1932         uint32_t ctrl;
1933
1934         PMD_INIT_FUNC_TRACE();
1935
1936         /* DMATXCTRL: Geric Double VLAN Enable */
1937         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1938         ctrl |= IXGBE_DMATXCTL_GDV;
1939         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1940
1941         /* CTRL_EXT: Global Double VLAN Enable */
1942         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1943         ctrl |= IXGBE_EXTENDED_VLAN;
1944         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1945
1946         /* Clear pooling mode of PFVTCTL. It's required by X550. */
1947         if (hw->mac.type == ixgbe_mac_X550 ||
1948             hw->mac.type == ixgbe_mac_X550EM_x ||
1949             hw->mac.type == ixgbe_mac_X550EM_a) {
1950                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
1951                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
1952                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
1953         }
1954
1955         /*
1956          * VET EXT field in the EXVET register = 0x8100 by default
1957          * So no need to change. Same to VT field of DMATXCTL register
1958          */
1959 }
1960
1961 static void
1962 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1963 {
1964         if (mask & ETH_VLAN_STRIP_MASK) {
1965                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1966                         ixgbe_vlan_hw_strip_enable_all(dev);
1967                 else
1968                         ixgbe_vlan_hw_strip_disable_all(dev);
1969         }
1970
1971         if (mask & ETH_VLAN_FILTER_MASK) {
1972                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1973                         ixgbe_vlan_hw_filter_enable(dev);
1974                 else
1975                         ixgbe_vlan_hw_filter_disable(dev);
1976         }
1977
1978         if (mask & ETH_VLAN_EXTEND_MASK) {
1979                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1980                         ixgbe_vlan_hw_extend_enable(dev);
1981                 else
1982                         ixgbe_vlan_hw_extend_disable(dev);
1983         }
1984 }
1985
1986 static void
1987 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1988 {
1989         struct ixgbe_hw *hw =
1990                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1992         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1993
1994         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
1995         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1996 }
1997
1998 static int
1999 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2000 {
2001         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2002
2003         switch (nb_rx_q) {
2004         case 1:
2005         case 2:
2006                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2007                 break;
2008         case 4:
2009                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2010                 break;
2011         default:
2012                 return -EINVAL;
2013         }
2014
2015         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2016         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2017
2018         return 0;
2019 }
2020
2021 static int
2022 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2023 {
2024         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2025         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2026         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2027         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2028
2029         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2030                 /* check multi-queue mode */
2031                 switch (dev_conf->rxmode.mq_mode) {
2032                 case ETH_MQ_RX_VMDQ_DCB:
2033                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2034                         break;
2035                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2036                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2037                         PMD_INIT_LOG(ERR, "SRIOV active,"
2038                                         " unsupported mq_mode rx %d.",
2039                                         dev_conf->rxmode.mq_mode);
2040                         return -EINVAL;
2041                 case ETH_MQ_RX_RSS:
2042                 case ETH_MQ_RX_VMDQ_RSS:
2043                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2044                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2045                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2046                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2047                                                 " invalid queue number"
2048                                                 " for VMDQ RSS, allowed"
2049                                                 " value are 1, 2 or 4.");
2050                                         return -EINVAL;
2051                                 }
2052                         break;
2053                 case ETH_MQ_RX_VMDQ_ONLY:
2054                 case ETH_MQ_RX_NONE:
2055                         /* if nothing mq mode configure, use default scheme */
2056                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2057                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2058                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2059                         break;
2060                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2061                         /* SRIOV only works in VMDq enable mode */
2062                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2063                                         " wrong mq_mode rx %d.",
2064                                         dev_conf->rxmode.mq_mode);
2065                         return -EINVAL;
2066                 }
2067
2068                 switch (dev_conf->txmode.mq_mode) {
2069                 case ETH_MQ_TX_VMDQ_DCB:
2070                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2071                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2072                         break;
2073                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2074                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2075                         break;
2076                 }
2077
2078                 /* check valid queue number */
2079                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2080                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2081                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2082                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2083                                         " must be less than or equal to %d.",
2084                                         nb_rx_q, nb_tx_q,
2085                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2086                         return -EINVAL;
2087                 }
2088         } else {
2089                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2090                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2091                                           " not supported.");
2092                         return -EINVAL;
2093                 }
2094                 /* check configuration for vmdb+dcb mode */
2095                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2096                         const struct rte_eth_vmdq_dcb_conf *conf;
2097
2098                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2099                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2100                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2101                                 return -EINVAL;
2102                         }
2103                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2104                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2105                                conf->nb_queue_pools == ETH_32_POOLS)) {
2106                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2107                                                 " nb_queue_pools must be %d or %d.",
2108                                                 ETH_16_POOLS, ETH_32_POOLS);
2109                                 return -EINVAL;
2110                         }
2111                 }
2112                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2113                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2114
2115                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2116                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2117                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2118                                 return -EINVAL;
2119                         }
2120                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2121                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2122                                conf->nb_queue_pools == ETH_32_POOLS)) {
2123                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2124                                                 " nb_queue_pools != %d and"
2125                                                 " nb_queue_pools != %d.",
2126                                                 ETH_16_POOLS, ETH_32_POOLS);
2127                                 return -EINVAL;
2128                         }
2129                 }
2130
2131                 /* For DCB mode check our configuration before we go further */
2132                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2133                         const struct rte_eth_dcb_rx_conf *conf;
2134
2135                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2136                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2137                                                  IXGBE_DCB_NB_QUEUES);
2138                                 return -EINVAL;
2139                         }
2140                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2141                         if (!(conf->nb_tcs == ETH_4_TCS ||
2142                                conf->nb_tcs == ETH_8_TCS)) {
2143                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2144                                                 " and nb_tcs != %d.",
2145                                                 ETH_4_TCS, ETH_8_TCS);
2146                                 return -EINVAL;
2147                         }
2148                 }
2149
2150                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2151                         const struct rte_eth_dcb_tx_conf *conf;
2152
2153                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2154                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2155                                                  IXGBE_DCB_NB_QUEUES);
2156                                 return -EINVAL;
2157                         }
2158                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2159                         if (!(conf->nb_tcs == ETH_4_TCS ||
2160                                conf->nb_tcs == ETH_8_TCS)) {
2161                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2162                                                 " and nb_tcs != %d.",
2163                                                 ETH_4_TCS, ETH_8_TCS);
2164                                 return -EINVAL;
2165                         }
2166                 }
2167
2168                 /*
2169                  * When DCB/VT is off, maximum number of queues changes,
2170                  * except for 82598EB, which remains constant.
2171                  */
2172                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2173                                 hw->mac.type != ixgbe_mac_82598EB) {
2174                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2175                                 PMD_INIT_LOG(ERR,
2176                                              "Neither VT nor DCB are enabled, "
2177                                              "nb_tx_q > %d.",
2178                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2179                                 return -EINVAL;
2180                         }
2181                 }
2182         }
2183         return 0;
2184 }
2185
2186 static int
2187 ixgbe_dev_configure(struct rte_eth_dev *dev)
2188 {
2189         struct ixgbe_interrupt *intr =
2190                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2191         struct ixgbe_adapter *adapter =
2192                 (struct ixgbe_adapter *)dev->data->dev_private;
2193         int ret;
2194
2195         PMD_INIT_FUNC_TRACE();
2196         /* multipe queue mode checking */
2197         ret  = ixgbe_check_mq_mode(dev);
2198         if (ret != 0) {
2199                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2200                             ret);
2201                 return ret;
2202         }
2203
2204         /* set flag to update link status after init */
2205         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2206
2207         /*
2208          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2209          * allocation or vector Rx preconditions we will reset it.
2210          */
2211         adapter->rx_bulk_alloc_allowed = true;
2212         adapter->rx_vec_allowed = true;
2213
2214         return 0;
2215 }
2216
2217 static void
2218 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2219 {
2220         struct ixgbe_hw *hw =
2221                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2222         struct ixgbe_interrupt *intr =
2223                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2224         uint32_t gpie;
2225
2226         /* only set up it on X550EM_X */
2227         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2228                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2229                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2230                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2231                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2232                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2233         }
2234 }
2235
2236 /*
2237  * Configure device link speed and setup link.
2238  * It returns 0 on success.
2239  */
2240 static int
2241 ixgbe_dev_start(struct rte_eth_dev *dev)
2242 {
2243         struct ixgbe_hw *hw =
2244                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245         struct ixgbe_vf_info *vfinfo =
2246                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2247         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2248         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2249         uint32_t intr_vector = 0;
2250         int err, link_up = 0, negotiate = 0;
2251         uint32_t speed = 0;
2252         int mask = 0;
2253         int status;
2254         uint16_t vf, idx;
2255         uint32_t *link_speeds;
2256
2257         PMD_INIT_FUNC_TRACE();
2258
2259         /* IXGBE devices don't support:
2260         *    - half duplex (checked afterwards for valid speeds)
2261         *    - fixed speed: TODO implement
2262         */
2263         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2264                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2265                              dev->data->port_id);
2266                 return -EINVAL;
2267         }
2268
2269         /* disable uio/vfio intr/eventfd mapping */
2270         rte_intr_disable(intr_handle);
2271
2272         /* stop adapter */
2273         hw->adapter_stopped = 0;
2274         ixgbe_stop_adapter(hw);
2275
2276         /* reinitialize adapter
2277          * this calls reset and start
2278          */
2279         status = ixgbe_pf_reset_hw(hw);
2280         if (status != 0)
2281                 return -1;
2282         hw->mac.ops.start_hw(hw);
2283         hw->mac.get_link_status = true;
2284
2285         /* configure PF module if SRIOV enabled */
2286         ixgbe_pf_host_configure(dev);
2287
2288         ixgbe_dev_phy_intr_setup(dev);
2289
2290         /* check and configure queue intr-vector mapping */
2291         if ((rte_intr_cap_multiple(intr_handle) ||
2292              !RTE_ETH_DEV_SRIOV(dev).active) &&
2293             dev->data->dev_conf.intr_conf.rxq != 0) {
2294                 intr_vector = dev->data->nb_rx_queues;
2295                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2296                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2297                                         IXGBE_MAX_INTR_QUEUE_NUM);
2298                         return -ENOTSUP;
2299                 }
2300                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2301                         return -1;
2302         }
2303
2304         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2305                 intr_handle->intr_vec =
2306                         rte_zmalloc("intr_vec",
2307                                     dev->data->nb_rx_queues * sizeof(int), 0);
2308                 if (intr_handle->intr_vec == NULL) {
2309                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2310                                      " intr_vec\n", dev->data->nb_rx_queues);
2311                         return -ENOMEM;
2312                 }
2313         }
2314
2315         /* confiugre msix for sleep until rx interrupt */
2316         ixgbe_configure_msix(dev);
2317
2318         /* initialize transmission unit */
2319         ixgbe_dev_tx_init(dev);
2320
2321         /* This can fail when allocating mbufs for descriptor rings */
2322         err = ixgbe_dev_rx_init(dev);
2323         if (err) {
2324                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2325                 goto error;
2326         }
2327
2328     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2329                 ETH_VLAN_EXTEND_MASK;
2330         ixgbe_vlan_offload_set(dev, mask);
2331
2332         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2333                 /* Enable vlan filtering for VMDq */
2334                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2335         }
2336
2337         /* Configure DCB hw */
2338         ixgbe_configure_dcb(dev);
2339
2340         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2341                 err = ixgbe_fdir_configure(dev);
2342                 if (err)
2343                         goto error;
2344         }
2345
2346         /* Restore vf rate limit */
2347         if (vfinfo != NULL) {
2348                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2349                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2350                                 if (vfinfo[vf].tx_rate[idx] != 0)
2351                                         rte_pmd_ixgbe_set_vf_rate_limit(
2352                                                 dev->data->port_id, vf,
2353                                                 vfinfo[vf].tx_rate[idx],
2354                                                 1 << idx);
2355         }
2356
2357         ixgbe_restore_statistics_mapping(dev);
2358
2359         err = ixgbe_dev_rxtx_start(dev);
2360         if (err < 0) {
2361                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2362                 goto error;
2363         }
2364
2365         /* Skip link setup if loopback mode is enabled for 82599. */
2366         if (hw->mac.type == ixgbe_mac_82599EB &&
2367                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2368                 goto skip_link_setup;
2369
2370         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2371                 err = hw->mac.ops.setup_sfp(hw);
2372                 if (err)
2373                         goto error;
2374         }
2375
2376         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2377                 /* Turn on the copper */
2378                 ixgbe_set_phy_power(hw, true);
2379         } else {
2380                 /* Turn on the laser */
2381                 ixgbe_enable_tx_laser(hw);
2382         }
2383
2384         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2385         if (err)
2386                 goto error;
2387         dev->data->dev_link.link_status = link_up;
2388
2389         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2390         if (err)
2391                 goto error;
2392
2393         link_speeds = &dev->data->dev_conf.link_speeds;
2394         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2395                         ETH_LINK_SPEED_10G)) {
2396                 PMD_INIT_LOG(ERR, "Invalid link setting");
2397                 goto error;
2398         }
2399
2400         speed = 0x0;
2401         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2402                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2403                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2404                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2405         } else {
2406                 if (*link_speeds & ETH_LINK_SPEED_10G)
2407                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2408                 if (*link_speeds & ETH_LINK_SPEED_1G)
2409                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2410                 if (*link_speeds & ETH_LINK_SPEED_100M)
2411                         speed |= IXGBE_LINK_SPEED_100_FULL;
2412         }
2413
2414         err = ixgbe_setup_link(hw, speed, link_up);
2415         if (err)
2416                 goto error;
2417
2418 skip_link_setup:
2419
2420         if (rte_intr_allow_others(intr_handle)) {
2421                 /* check if lsc interrupt is enabled */
2422                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2423                         ixgbe_dev_lsc_interrupt_setup(dev);
2424                 ixgbe_dev_macsec_interrupt_setup(dev);
2425         } else {
2426                 rte_intr_callback_unregister(intr_handle,
2427                                              ixgbe_dev_interrupt_handler, dev);
2428                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2429                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2430                                      " no intr multiplex\n");
2431         }
2432
2433         /* check if rxq interrupt is enabled */
2434         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2435             rte_intr_dp_is_en(intr_handle))
2436                 ixgbe_dev_rxq_interrupt_setup(dev);
2437
2438         /* enable uio/vfio intr/eventfd mapping */
2439         rte_intr_enable(intr_handle);
2440
2441         /* resume enabled intr since hw reset */
2442         ixgbe_enable_intr(dev);
2443
2444         return 0;
2445
2446 error:
2447         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2448         ixgbe_dev_clear_queues(dev);
2449         return -EIO;
2450 }
2451
2452 /*
2453  * Stop device: disable rx and tx functions to allow for reconfiguring.
2454  */
2455 static void
2456 ixgbe_dev_stop(struct rte_eth_dev *dev)
2457 {
2458         struct rte_eth_link link;
2459         struct ixgbe_hw *hw =
2460                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2461         struct ixgbe_vf_info *vfinfo =
2462                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2463         struct ixgbe_filter_info *filter_info =
2464                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2465         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2466         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2467         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468         int vf;
2469
2470         PMD_INIT_FUNC_TRACE();
2471
2472         /* disable interrupts */
2473         ixgbe_disable_intr(hw);
2474
2475         /* reset the NIC */
2476         ixgbe_pf_reset_hw(hw);
2477         hw->adapter_stopped = 0;
2478
2479         /* stop adapter */
2480         ixgbe_stop_adapter(hw);
2481
2482         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2483                 vfinfo[vf].clear_to_send = false;
2484
2485         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2486                 /* Turn off the copper */
2487                 ixgbe_set_phy_power(hw, false);
2488         } else {
2489                 /* Turn off the laser */
2490                 ixgbe_disable_tx_laser(hw);
2491         }
2492
2493         ixgbe_dev_clear_queues(dev);
2494
2495         /* Clear stored conf */
2496         dev->data->scattered_rx = 0;
2497         dev->data->lro = 0;
2498
2499         /* Clear recorded link status */
2500         memset(&link, 0, sizeof(link));
2501         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2502
2503         /* Remove all ntuple filters of the device */
2504         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2505              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2506                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2507                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2508                              p_5tuple, entries);
2509                 rte_free(p_5tuple);
2510         }
2511         memset(filter_info->fivetuple_mask, 0,
2512                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2513
2514         if (!rte_intr_allow_others(intr_handle))
2515                 /* resume to the default handler */
2516                 rte_intr_callback_register(intr_handle,
2517                                            ixgbe_dev_interrupt_handler,
2518                                            (void *)dev);
2519
2520         /* Clean datapath event and queue/vec mapping */
2521         rte_intr_efd_disable(intr_handle);
2522         if (intr_handle->intr_vec != NULL) {
2523                 rte_free(intr_handle->intr_vec);
2524                 intr_handle->intr_vec = NULL;
2525         }
2526 }
2527
2528 /*
2529  * Set device link up: enable tx.
2530  */
2531 static int
2532 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2533 {
2534         struct ixgbe_hw *hw =
2535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2536         if (hw->mac.type == ixgbe_mac_82599EB) {
2537 #ifdef RTE_NIC_BYPASS
2538                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2539                         /* Not suported in bypass mode */
2540                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2541                                      "by device id 0x%x", hw->device_id);
2542                         return -ENOTSUP;
2543                 }
2544 #endif
2545         }
2546
2547         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2548                 /* Turn on the copper */
2549                 ixgbe_set_phy_power(hw, true);
2550         } else {
2551                 /* Turn on the laser */
2552                 ixgbe_enable_tx_laser(hw);
2553         }
2554
2555         return 0;
2556 }
2557
2558 /*
2559  * Set device link down: disable tx.
2560  */
2561 static int
2562 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2563 {
2564         struct ixgbe_hw *hw =
2565                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2566         if (hw->mac.type == ixgbe_mac_82599EB) {
2567 #ifdef RTE_NIC_BYPASS
2568                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2569                         /* Not suported in bypass mode */
2570                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2571                                      "by device id 0x%x", hw->device_id);
2572                         return -ENOTSUP;
2573                 }
2574 #endif
2575         }
2576
2577         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2578                 /* Turn off the copper */
2579                 ixgbe_set_phy_power(hw, false);
2580         } else {
2581                 /* Turn off the laser */
2582                 ixgbe_disable_tx_laser(hw);
2583         }
2584
2585         return 0;
2586 }
2587
2588 /*
2589  * Reest and stop device.
2590  */
2591 static void
2592 ixgbe_dev_close(struct rte_eth_dev *dev)
2593 {
2594         struct ixgbe_hw *hw =
2595                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596
2597         PMD_INIT_FUNC_TRACE();
2598
2599         ixgbe_pf_reset_hw(hw);
2600
2601         ixgbe_dev_stop(dev);
2602         hw->adapter_stopped = 1;
2603
2604         ixgbe_dev_free_queues(dev);
2605
2606         ixgbe_disable_pcie_master(hw);
2607
2608         /* reprogram the RAR[0] in case user changed it. */
2609         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2610 }
2611
2612 static void
2613 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2614                            struct ixgbe_hw_stats *hw_stats,
2615                            struct ixgbe_macsec_stats *macsec_stats,
2616                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2617                            uint64_t *total_qprc, uint64_t *total_qprdc)
2618 {
2619         uint32_t bprc, lxon, lxoff, total;
2620         uint32_t delta_gprc = 0;
2621         unsigned i;
2622         /* Workaround for RX byte count not including CRC bytes when CRC
2623          * strip is enabled. CRC bytes are removed from counters when crc_strip
2624          * is disabled.
2625          */
2626         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2627                         IXGBE_HLREG0_RXCRCSTRP);
2628
2629         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2630         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2631         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2632         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2633
2634         for (i = 0; i < 8; i++) {
2635                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2636
2637                 /* global total per queue */
2638                 hw_stats->mpc[i] += mp;
2639                 /* Running comprehensive total for stats display */
2640                 *total_missed_rx += hw_stats->mpc[i];
2641                 if (hw->mac.type == ixgbe_mac_82598EB) {
2642                         hw_stats->rnbc[i] +=
2643                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2644                         hw_stats->pxonrxc[i] +=
2645                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2646                         hw_stats->pxoffrxc[i] +=
2647                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2648                 } else {
2649                         hw_stats->pxonrxc[i] +=
2650                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2651                         hw_stats->pxoffrxc[i] +=
2652                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2653                         hw_stats->pxon2offc[i] +=
2654                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2655                 }
2656                 hw_stats->pxontxc[i] +=
2657                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2658                 hw_stats->pxofftxc[i] +=
2659                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2660         }
2661         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2662                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2663                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2664                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2665
2666                 delta_gprc += delta_qprc;
2667
2668                 hw_stats->qprc[i] += delta_qprc;
2669                 hw_stats->qptc[i] += delta_qptc;
2670
2671                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2672                 hw_stats->qbrc[i] +=
2673                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2674                 if (crc_strip == 0)
2675                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2676
2677                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2678                 hw_stats->qbtc[i] +=
2679                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2680
2681                 hw_stats->qprdc[i] += delta_qprdc;
2682                 *total_qprdc += hw_stats->qprdc[i];
2683
2684                 *total_qprc += hw_stats->qprc[i];
2685                 *total_qbrc += hw_stats->qbrc[i];
2686         }
2687         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2688         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2689         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2690
2691         /*
2692          * An errata states that gprc actually counts good + missed packets:
2693          * Workaround to set gprc to summated queue packet receives
2694          */
2695         hw_stats->gprc = *total_qprc;
2696
2697         if (hw->mac.type != ixgbe_mac_82598EB) {
2698                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2699                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2700                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2701                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2702                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2703                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2704                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2705                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2706         } else {
2707                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2708                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2709                 /* 82598 only has a counter in the high register */
2710                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2711                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2712                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2713         }
2714         uint64_t old_tpr = hw_stats->tpr;
2715
2716         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2717         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2718
2719         if (crc_strip == 0)
2720                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2721
2722         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2723         hw_stats->gptc += delta_gptc;
2724         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2725         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2726
2727         /*
2728          * Workaround: mprc hardware is incorrectly counting
2729          * broadcasts, so for now we subtract those.
2730          */
2731         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2732         hw_stats->bprc += bprc;
2733         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2734         if (hw->mac.type == ixgbe_mac_82598EB)
2735                 hw_stats->mprc -= bprc;
2736
2737         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2738         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2739         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2740         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2741         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2742         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2743
2744         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2745         hw_stats->lxontxc += lxon;
2746         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2747         hw_stats->lxofftxc += lxoff;
2748         total = lxon + lxoff;
2749
2750         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2751         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2752         hw_stats->gptc -= total;
2753         hw_stats->mptc -= total;
2754         hw_stats->ptc64 -= total;
2755         hw_stats->gotc -= total * ETHER_MIN_LEN;
2756
2757         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2758         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2759         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2760         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2761         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2762         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2763         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2764         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2765         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2766         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2767         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2768         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2769         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2770         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2771         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2772         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2773         /* Only read FCOE on 82599 */
2774         if (hw->mac.type != ixgbe_mac_82598EB) {
2775                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2776                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2777                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2778                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2779                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2780         }
2781
2782         /* Flow Director Stats registers */
2783         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2784         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2785
2786         /* MACsec Stats registers */
2787         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2788         macsec_stats->out_pkts_encrypted +=
2789                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2790         macsec_stats->out_pkts_protected +=
2791                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2792         macsec_stats->out_octets_encrypted +=
2793                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2794         macsec_stats->out_octets_protected +=
2795                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2796         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2797         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2798         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2799         macsec_stats->in_pkts_unknownsci +=
2800                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2801         macsec_stats->in_octets_decrypted +=
2802                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2803         macsec_stats->in_octets_validated +=
2804                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2805         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2806         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2807         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2808         for (i = 0; i < 2; i++) {
2809                 macsec_stats->in_pkts_ok +=
2810                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2811                 macsec_stats->in_pkts_invalid +=
2812                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2813                 macsec_stats->in_pkts_notvalid +=
2814                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2815         }
2816         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2817         macsec_stats->in_pkts_notusingsa +=
2818                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2819 }
2820
2821 /*
2822  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2823  */
2824 static void
2825 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2826 {
2827         struct ixgbe_hw *hw =
2828                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829         struct ixgbe_hw_stats *hw_stats =
2830                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2831         struct ixgbe_macsec_stats *macsec_stats =
2832                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2833                                 dev->data->dev_private);
2834         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2835         unsigned i;
2836
2837         total_missed_rx = 0;
2838         total_qbrc = 0;
2839         total_qprc = 0;
2840         total_qprdc = 0;
2841
2842         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2843                         &total_qbrc, &total_qprc, &total_qprdc);
2844
2845         if (stats == NULL)
2846                 return;
2847
2848         /* Fill out the rte_eth_stats statistics structure */
2849         stats->ipackets = total_qprc;
2850         stats->ibytes = total_qbrc;
2851         stats->opackets = hw_stats->gptc;
2852         stats->obytes = hw_stats->gotc;
2853
2854         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2855                 stats->q_ipackets[i] = hw_stats->qprc[i];
2856                 stats->q_opackets[i] = hw_stats->qptc[i];
2857                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2858                 stats->q_obytes[i] = hw_stats->qbtc[i];
2859                 stats->q_errors[i] = hw_stats->qprdc[i];
2860         }
2861
2862         /* Rx Errors */
2863         stats->imissed  = total_missed_rx;
2864         stats->ierrors  = hw_stats->crcerrs +
2865                           hw_stats->mspdc +
2866                           hw_stats->rlec +
2867                           hw_stats->ruc +
2868                           hw_stats->roc +
2869                           hw_stats->illerrc +
2870                           hw_stats->errbc +
2871                           hw_stats->rfc +
2872                           hw_stats->fccrc +
2873                           hw_stats->fclast;
2874
2875         /* Tx Errors */
2876         stats->oerrors  = 0;
2877 }
2878
2879 static void
2880 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2881 {
2882         struct ixgbe_hw_stats *stats =
2883                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2884
2885         /* HW registers are cleared on read */
2886         ixgbe_dev_stats_get(dev, NULL);
2887
2888         /* Reset software totals */
2889         memset(stats, 0, sizeof(*stats));
2890 }
2891
2892 /* This function calculates the number of xstats based on the current config */
2893 static unsigned
2894 ixgbe_xstats_calc_num(void) {
2895         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
2896                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
2897                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
2898 }
2899
2900 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2901         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
2902 {
2903         const unsigned cnt_stats = ixgbe_xstats_calc_num();
2904         unsigned stat, i, count;
2905
2906         if (xstats_names != NULL) {
2907                 count = 0;
2908
2909                 /* Note: limit >= cnt_stats checked upstream
2910                  * in rte_eth_xstats_names()
2911                  */
2912
2913                 /* Extended stats from ixgbe_hw_stats */
2914                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2915                         snprintf(xstats_names[count].name,
2916                                 sizeof(xstats_names[count].name),
2917                                 "%s",
2918                                 rte_ixgbe_stats_strings[i].name);
2919                         count++;
2920                 }
2921
2922                 /* MACsec Stats */
2923                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
2924                         snprintf(xstats_names[count].name,
2925                                 sizeof(xstats_names[count].name),
2926                                 "%s",
2927                                 rte_ixgbe_macsec_strings[i].name);
2928                         count++;
2929                 }
2930
2931                 /* RX Priority Stats */
2932                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2933                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
2934                                 snprintf(xstats_names[count].name,
2935                                         sizeof(xstats_names[count].name),
2936                                         "rx_priority%u_%s", i,
2937                                         rte_ixgbe_rxq_strings[stat].name);
2938                                 count++;
2939                         }
2940                 }
2941
2942                 /* TX Priority Stats */
2943                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2944                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
2945                                 snprintf(xstats_names[count].name,
2946                                         sizeof(xstats_names[count].name),
2947                                         "tx_priority%u_%s", i,
2948                                         rte_ixgbe_txq_strings[stat].name);
2949                                 count++;
2950                         }
2951                 }
2952         }
2953         return cnt_stats;
2954 }
2955
2956 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2957         struct rte_eth_xstat_name *xstats_names, unsigned limit)
2958 {
2959         unsigned i;
2960
2961         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
2962                 return -ENOMEM;
2963
2964         if (xstats_names != NULL)
2965                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
2966                         snprintf(xstats_names[i].name,
2967                                 sizeof(xstats_names[i].name),
2968                                 "%s", rte_ixgbevf_stats_strings[i].name);
2969         return IXGBEVF_NB_XSTATS;
2970 }
2971
2972 static int
2973 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2974                                          unsigned n)
2975 {
2976         struct ixgbe_hw *hw =
2977                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978         struct ixgbe_hw_stats *hw_stats =
2979                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2980         struct ixgbe_macsec_stats *macsec_stats =
2981                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2982                                 dev->data->dev_private);
2983         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2984         unsigned i, stat, count = 0;
2985
2986         count = ixgbe_xstats_calc_num();
2987
2988         if (n < count)
2989                 return count;
2990
2991         total_missed_rx = 0;
2992         total_qbrc = 0;
2993         total_qprc = 0;
2994         total_qprdc = 0;
2995
2996         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2997                         &total_qbrc, &total_qprc, &total_qprdc);
2998
2999         /* If this is a reset xstats is NULL, and we have cleared the
3000          * registers by reading them.
3001          */
3002         if (!xstats)
3003                 return 0;
3004
3005         /* Extended stats from ixgbe_hw_stats */
3006         count = 0;
3007         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3008                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3009                                 rte_ixgbe_stats_strings[i].offset);
3010                 xstats[count].id = count;
3011                 count++;
3012         }
3013
3014         /* MACsec Stats */
3015         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3016                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3017                                 rte_ixgbe_macsec_strings[i].offset);
3018                 xstats[count].id = count;
3019                 count++;
3020         }
3021
3022         /* RX Priority Stats */
3023         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3024                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3025                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3026                                         rte_ixgbe_rxq_strings[stat].offset +
3027                                         (sizeof(uint64_t) * i));
3028                         xstats[count].id = count;
3029                         count++;
3030                 }
3031         }
3032
3033         /* TX Priority Stats */
3034         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3035                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3036                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3037                                         rte_ixgbe_txq_strings[stat].offset +
3038                                         (sizeof(uint64_t) * i));
3039                         xstats[count].id = count;
3040                         count++;
3041                 }
3042         }
3043         return count;
3044 }
3045
3046 static void
3047 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3048 {
3049         struct ixgbe_hw_stats *stats =
3050                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3051         struct ixgbe_macsec_stats *macsec_stats =
3052                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3053                                 dev->data->dev_private);
3054
3055         unsigned count = ixgbe_xstats_calc_num();
3056
3057         /* HW registers are cleared on read */
3058         ixgbe_dev_xstats_get(dev, NULL, count);
3059
3060         /* Reset software totals */
3061         memset(stats, 0, sizeof(*stats));
3062         memset(macsec_stats, 0, sizeof(*macsec_stats));
3063 }
3064
3065 static void
3066 ixgbevf_update_stats(struct rte_eth_dev *dev)
3067 {
3068         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3069         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3070                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3071
3072         /* Good Rx packet, include VF loopback */
3073         UPDATE_VF_STAT(IXGBE_VFGPRC,
3074             hw_stats->last_vfgprc, hw_stats->vfgprc);
3075
3076         /* Good Rx octets, include VF loopback */
3077         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3078             hw_stats->last_vfgorc, hw_stats->vfgorc);
3079
3080         /* Good Tx packet, include VF loopback */
3081         UPDATE_VF_STAT(IXGBE_VFGPTC,
3082             hw_stats->last_vfgptc, hw_stats->vfgptc);
3083
3084         /* Good Tx octets, include VF loopback */
3085         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3086             hw_stats->last_vfgotc, hw_stats->vfgotc);
3087
3088         /* Rx Multicst Packet */
3089         UPDATE_VF_STAT(IXGBE_VFMPRC,
3090             hw_stats->last_vfmprc, hw_stats->vfmprc);
3091 }
3092
3093 static int
3094 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3095                        unsigned n)
3096 {
3097         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3098                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3099         unsigned i;
3100
3101         if (n < IXGBEVF_NB_XSTATS)
3102                 return IXGBEVF_NB_XSTATS;
3103
3104         ixgbevf_update_stats(dev);
3105
3106         if (!xstats)
3107                 return 0;
3108
3109         /* Extended stats */
3110         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3111                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3112                         rte_ixgbevf_stats_strings[i].offset);
3113         }
3114
3115         return IXGBEVF_NB_XSTATS;
3116 }
3117
3118 static void
3119 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3120 {
3121         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3122                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123
3124         ixgbevf_update_stats(dev);
3125
3126         if (stats == NULL)
3127                 return;
3128
3129         stats->ipackets = hw_stats->vfgprc;
3130         stats->ibytes = hw_stats->vfgorc;
3131         stats->opackets = hw_stats->vfgptc;
3132         stats->obytes = hw_stats->vfgotc;
3133 }
3134
3135 static void
3136 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3137 {
3138         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3139                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3140
3141         /* Sync HW register to the last stats */
3142         ixgbevf_dev_stats_get(dev, NULL);
3143
3144         /* reset HW current stats*/
3145         hw_stats->vfgprc = 0;
3146         hw_stats->vfgorc = 0;
3147         hw_stats->vfgptc = 0;
3148         hw_stats->vfgotc = 0;
3149 }
3150
3151 static int
3152 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3153 {
3154         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155         u16 eeprom_verh, eeprom_verl;
3156         u32 etrack_id;
3157         int ret;
3158
3159         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3160         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3161
3162         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3163         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3164
3165         ret += 1; /* add the size of '\0' */
3166         if (fw_size < (u32)ret)
3167                 return ret;
3168         else
3169                 return 0;
3170 }
3171
3172 static void
3173 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3174 {
3175         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3178
3179         dev_info->pci_dev = pci_dev;
3180         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3181         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3182         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3183                 /*
3184                  * When DCB/VT is off, maximum number of queues changes,
3185                  * except for 82598EB, which remains constant.
3186                  */
3187                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3188                                 hw->mac.type != ixgbe_mac_82598EB)
3189                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3190         }
3191         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3192         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3193         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3194         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3195         dev_info->max_vfs = pci_dev->max_vfs;
3196         if (hw->mac.type == ixgbe_mac_82598EB)
3197                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3198         else
3199                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3200         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3201         dev_info->rx_offload_capa =
3202                 DEV_RX_OFFLOAD_VLAN_STRIP |
3203                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3204                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3205                 DEV_RX_OFFLOAD_TCP_CKSUM;
3206
3207         /*
3208          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3209          * mode.
3210          */
3211         if ((hw->mac.type == ixgbe_mac_82599EB ||
3212              hw->mac.type == ixgbe_mac_X540) &&
3213             !RTE_ETH_DEV_SRIOV(dev).active)
3214                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3215
3216         if (hw->mac.type == ixgbe_mac_82599EB ||
3217             hw->mac.type == ixgbe_mac_X540)
3218                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3219
3220         if (hw->mac.type == ixgbe_mac_X550 ||
3221             hw->mac.type == ixgbe_mac_X550EM_x ||
3222             hw->mac.type == ixgbe_mac_X550EM_a)
3223                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3224
3225         dev_info->tx_offload_capa =
3226                 DEV_TX_OFFLOAD_VLAN_INSERT |
3227                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3228                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3229                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3230                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3231                 DEV_TX_OFFLOAD_TCP_TSO;
3232
3233         if (hw->mac.type == ixgbe_mac_82599EB ||
3234             hw->mac.type == ixgbe_mac_X540)
3235                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3236
3237         if (hw->mac.type == ixgbe_mac_X550 ||
3238             hw->mac.type == ixgbe_mac_X550EM_x ||
3239             hw->mac.type == ixgbe_mac_X550EM_a)
3240                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3241
3242         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3243                 .rx_thresh = {
3244                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3245                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3246                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3247                 },
3248                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3249                 .rx_drop_en = 0,
3250         };
3251
3252         dev_info->default_txconf = (struct rte_eth_txconf) {
3253                 .tx_thresh = {
3254                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3255                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3256                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3257                 },
3258                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3259                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3260                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3261                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3262         };
3263
3264         dev_info->rx_desc_lim = rx_desc_lim;
3265         dev_info->tx_desc_lim = tx_desc_lim;
3266
3267         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3268         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3269         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3270
3271         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3272         if (hw->mac.type == ixgbe_mac_X540 ||
3273             hw->mac.type == ixgbe_mac_X540_vf ||
3274             hw->mac.type == ixgbe_mac_X550 ||
3275             hw->mac.type == ixgbe_mac_X550_vf) {
3276                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3277         }
3278 }
3279
3280 static const uint32_t *
3281 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3282 {
3283         static const uint32_t ptypes[] = {
3284                 /* For non-vec functions,
3285                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3286                  * for vec functions,
3287                  * refers to _recv_raw_pkts_vec().
3288                  */
3289                 RTE_PTYPE_L2_ETHER,
3290                 RTE_PTYPE_L3_IPV4,
3291                 RTE_PTYPE_L3_IPV4_EXT,
3292                 RTE_PTYPE_L3_IPV6,
3293                 RTE_PTYPE_L3_IPV6_EXT,
3294                 RTE_PTYPE_L4_SCTP,
3295                 RTE_PTYPE_L4_TCP,
3296                 RTE_PTYPE_L4_UDP,
3297                 RTE_PTYPE_TUNNEL_IP,
3298                 RTE_PTYPE_INNER_L3_IPV6,
3299                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3300                 RTE_PTYPE_INNER_L4_TCP,
3301                 RTE_PTYPE_INNER_L4_UDP,
3302                 RTE_PTYPE_UNKNOWN
3303         };
3304
3305         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3306             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3307             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3308             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3309                 return ptypes;
3310         return NULL;
3311 }
3312
3313 static void
3314 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3315                      struct rte_eth_dev_info *dev_info)
3316 {
3317         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3318         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319
3320         dev_info->pci_dev = pci_dev;
3321         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3322         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3323         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3324         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3325         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3326         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3327         dev_info->max_vfs = pci_dev->max_vfs;
3328         if (hw->mac.type == ixgbe_mac_82598EB)
3329                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3330         else
3331                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3332         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3333                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3334                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3335                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3336         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3337                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3338                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3339                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3340                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3341                                 DEV_TX_OFFLOAD_TCP_TSO;
3342
3343         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3344                 .rx_thresh = {
3345                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3346                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3347                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3348                 },
3349                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3350                 .rx_drop_en = 0,
3351         };
3352
3353         dev_info->default_txconf = (struct rte_eth_txconf) {
3354                 .tx_thresh = {
3355                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3356                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3357                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3358                 },
3359                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3360                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3361                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3362                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3363         };
3364
3365         dev_info->rx_desc_lim = rx_desc_lim;
3366         dev_info->tx_desc_lim = tx_desc_lim;
3367 }
3368
3369 /* return 0 means link status changed, -1 means not changed */
3370 static int
3371 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3372 {
3373         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3374         struct rte_eth_link link, old;
3375         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3376         int link_up;
3377         int diag;
3378
3379         link.link_status = ETH_LINK_DOWN;
3380         link.link_speed = 0;
3381         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3382         memset(&old, 0, sizeof(old));
3383         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3384
3385         hw->mac.get_link_status = true;
3386
3387         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3388         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3389                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3390         else
3391                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3392
3393         if (diag != 0) {
3394                 link.link_speed = ETH_SPEED_NUM_100M;
3395                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3396                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3397                 if (link.link_status == old.link_status)
3398                         return -1;
3399                 return 0;
3400         }
3401
3402         if (link_up == 0) {
3403                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3404                 if (link.link_status == old.link_status)
3405                         return -1;
3406                 return 0;
3407         }
3408         link.link_status = ETH_LINK_UP;
3409         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3410
3411         switch (link_speed) {
3412         default:
3413         case IXGBE_LINK_SPEED_UNKNOWN:
3414                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3415                 link.link_speed = ETH_SPEED_NUM_100M;
3416                 break;
3417
3418         case IXGBE_LINK_SPEED_100_FULL:
3419                 link.link_speed = ETH_SPEED_NUM_100M;
3420                 break;
3421
3422         case IXGBE_LINK_SPEED_1GB_FULL:
3423                 link.link_speed = ETH_SPEED_NUM_1G;
3424                 break;
3425
3426         case IXGBE_LINK_SPEED_10GB_FULL:
3427                 link.link_speed = ETH_SPEED_NUM_10G;
3428                 break;
3429         }
3430         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3431
3432         if (link.link_status == old.link_status)
3433                 return -1;
3434
3435         return 0;
3436 }
3437
3438 static void
3439 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3440 {
3441         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         uint32_t fctrl;
3443
3444         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3445         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3446         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3447 }
3448
3449 static void
3450 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3451 {
3452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3453         uint32_t fctrl;
3454
3455         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3456         fctrl &= (~IXGBE_FCTRL_UPE);
3457         if (dev->data->all_multicast == 1)
3458                 fctrl |= IXGBE_FCTRL_MPE;
3459         else
3460                 fctrl &= (~IXGBE_FCTRL_MPE);
3461         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3462 }
3463
3464 static void
3465 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3466 {
3467         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3468         uint32_t fctrl;
3469
3470         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3471         fctrl |= IXGBE_FCTRL_MPE;
3472         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3473 }
3474
3475 static void
3476 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3477 {
3478         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3479         uint32_t fctrl;
3480
3481         if (dev->data->promiscuous == 1)
3482                 return; /* must remain in all_multicast mode */
3483
3484         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3485         fctrl &= (~IXGBE_FCTRL_MPE);
3486         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3487 }
3488
3489 /**
3490  * It clears the interrupt causes and enables the interrupt.
3491  * It will be called once only during nic initialized.
3492  *
3493  * @param dev
3494  *  Pointer to struct rte_eth_dev.
3495  *
3496  * @return
3497  *  - On success, zero.
3498  *  - On failure, a negative value.
3499  */
3500 static int
3501 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3502 {
3503         struct ixgbe_interrupt *intr =
3504                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3505
3506         ixgbe_dev_link_status_print(dev);
3507         intr->mask |= IXGBE_EICR_LSC;
3508
3509         return 0;
3510 }
3511
3512 /**
3513  * It clears the interrupt causes and enables the interrupt.
3514  * It will be called once only during nic initialized.
3515  *
3516  * @param dev
3517  *  Pointer to struct rte_eth_dev.
3518  *
3519  * @return
3520  *  - On success, zero.
3521  *  - On failure, a negative value.
3522  */
3523 static int
3524 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3525 {
3526         struct ixgbe_interrupt *intr =
3527                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3528
3529         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3530
3531         return 0;
3532 }
3533
3534 /**
3535  * It clears the interrupt causes and enables the interrupt.
3536  * It will be called once only during nic initialized.
3537  *
3538  * @param dev
3539  *  Pointer to struct rte_eth_dev.
3540  *
3541  * @return
3542  *  - On success, zero.
3543  *  - On failure, a negative value.
3544  */
3545 static int
3546 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3547 {
3548         struct ixgbe_interrupt *intr =
3549                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3550
3551         intr->mask |= IXGBE_EICR_LINKSEC;
3552
3553         return 0;
3554 }
3555
3556 /*
3557  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3558  *
3559  * @param dev
3560  *  Pointer to struct rte_eth_dev.
3561  *
3562  * @return
3563  *  - On success, zero.
3564  *  - On failure, a negative value.
3565  */
3566 static int
3567 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3568 {
3569         uint32_t eicr;
3570         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3571         struct ixgbe_interrupt *intr =
3572                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3573
3574         /* clear all cause mask */
3575         ixgbe_disable_intr(hw);
3576
3577         /* read-on-clear nic registers here */
3578         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3579         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3580
3581         intr->flags = 0;
3582
3583         /* set flag for async link update */
3584         if (eicr & IXGBE_EICR_LSC)
3585                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3586
3587         if (eicr & IXGBE_EICR_MAILBOX)
3588                 intr->flags |= IXGBE_FLAG_MAILBOX;
3589
3590         if (eicr & IXGBE_EICR_LINKSEC)
3591                 intr->flags |= IXGBE_FLAG_MACSEC;
3592
3593         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3594             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3595             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3596                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3597
3598         return 0;
3599 }
3600
3601 /**
3602  * It gets and then prints the link status.
3603  *
3604  * @param dev
3605  *  Pointer to struct rte_eth_dev.
3606  *
3607  * @return
3608  *  - On success, zero.
3609  *  - On failure, a negative value.
3610  */
3611 static void
3612 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3613 {
3614         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3615         struct rte_eth_link link;
3616
3617         memset(&link, 0, sizeof(link));
3618         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3619         if (link.link_status) {
3620                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3621                                         (int)(dev->data->port_id),
3622                                         (unsigned)link.link_speed,
3623                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3624                                         "full-duplex" : "half-duplex");
3625         } else {
3626                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3627                                 (int)(dev->data->port_id));
3628         }
3629         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3630                                 pci_dev->addr.domain,
3631                                 pci_dev->addr.bus,
3632                                 pci_dev->addr.devid,
3633                                 pci_dev->addr.function);
3634 }
3635
3636 /*
3637  * It executes link_update after knowing an interrupt occurred.
3638  *
3639  * @param dev
3640  *  Pointer to struct rte_eth_dev.
3641  *
3642  * @return
3643  *  - On success, zero.
3644  *  - On failure, a negative value.
3645  */
3646 static int
3647 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3648                            struct rte_intr_handle *intr_handle)
3649 {
3650         struct ixgbe_interrupt *intr =
3651                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3652         int64_t timeout;
3653         struct rte_eth_link link;
3654         int intr_enable_delay = false;
3655         struct ixgbe_hw *hw =
3656                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3657
3658         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3659
3660         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3661                 ixgbe_pf_mbx_process(dev);
3662                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3663         }
3664
3665         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3666                 ixgbe_handle_lasi(hw);
3667                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3668         }
3669
3670         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3671                 /* get the link status before link update, for predicting later */
3672                 memset(&link, 0, sizeof(link));
3673                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3674
3675                 ixgbe_dev_link_update(dev, 0);
3676
3677                 /* likely to up */
3678                 if (!link.link_status)
3679                         /* handle it 1 sec later, wait it being stable */
3680                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3681                 /* likely to down */
3682                 else
3683                         /* handle it 4 sec later, wait it being stable */
3684                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3685
3686                 ixgbe_dev_link_status_print(dev);
3687
3688                 intr_enable_delay = true;
3689         }
3690
3691         if (intr_enable_delay) {
3692                 if (rte_eal_alarm_set(timeout * 1000,
3693                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3694                         PMD_DRV_LOG(ERR, "Error setting alarm");
3695         } else {
3696                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3697                 ixgbe_enable_intr(dev);
3698                 rte_intr_enable(intr_handle);
3699         }
3700
3701
3702         return 0;
3703 }
3704
3705 /**
3706  * Interrupt handler which shall be registered for alarm callback for delayed
3707  * handling specific interrupt to wait for the stable nic state. As the
3708  * NIC interrupt state is not stable for ixgbe after link is just down,
3709  * it needs to wait 4 seconds to get the stable status.
3710  *
3711  * @param handle
3712  *  Pointer to interrupt handle.
3713  * @param param
3714  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3715  *
3716  * @return
3717  *  void
3718  */
3719 static void
3720 ixgbe_dev_interrupt_delayed_handler(void *param)
3721 {
3722         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3723         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3724         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3725         struct ixgbe_interrupt *intr =
3726                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3727         struct ixgbe_hw *hw =
3728                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3729         uint32_t eicr;
3730
3731         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3732         if (eicr & IXGBE_EICR_MAILBOX)
3733                 ixgbe_pf_mbx_process(dev);
3734
3735         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3736                 ixgbe_handle_lasi(hw);
3737                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3738         }
3739
3740         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3741                 ixgbe_dev_link_update(dev, 0);
3742                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3743                 ixgbe_dev_link_status_print(dev);
3744                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3745         }
3746
3747         if (intr->flags & IXGBE_FLAG_MACSEC) {
3748                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3749                                               NULL);
3750                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3751         }
3752
3753         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3754         ixgbe_enable_intr(dev);
3755         rte_intr_enable(intr_handle);
3756 }
3757
3758 /**
3759  * Interrupt handler triggered by NIC  for handling
3760  * specific interrupt.
3761  *
3762  * @param handle
3763  *  Pointer to interrupt handle.
3764  * @param param
3765  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3766  *
3767  * @return
3768  *  void
3769  */
3770 static void
3771 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3772                             void *param)
3773 {
3774         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3775
3776         ixgbe_dev_interrupt_get_status(dev);
3777         ixgbe_dev_interrupt_action(dev, handle);
3778 }
3779
3780 static int
3781 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3782 {
3783         struct ixgbe_hw *hw;
3784
3785         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3786         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3787 }
3788
3789 static int
3790 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3791 {
3792         struct ixgbe_hw *hw;
3793
3794         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3796 }
3797
3798 static int
3799 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3800 {
3801         struct ixgbe_hw *hw;
3802         uint32_t mflcn_reg;
3803         uint32_t fccfg_reg;
3804         int rx_pause;
3805         int tx_pause;
3806
3807         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3808
3809         fc_conf->pause_time = hw->fc.pause_time;
3810         fc_conf->high_water = hw->fc.high_water[0];
3811         fc_conf->low_water = hw->fc.low_water[0];
3812         fc_conf->send_xon = hw->fc.send_xon;
3813         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3814
3815         /*
3816          * Return rx_pause status according to actual setting of
3817          * MFLCN register.
3818          */
3819         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3820         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3821                 rx_pause = 1;
3822         else
3823                 rx_pause = 0;
3824
3825         /*
3826          * Return tx_pause status according to actual setting of
3827          * FCCFG register.
3828          */
3829         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3830         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3831                 tx_pause = 1;
3832         else
3833                 tx_pause = 0;
3834
3835         if (rx_pause && tx_pause)
3836                 fc_conf->mode = RTE_FC_FULL;
3837         else if (rx_pause)
3838                 fc_conf->mode = RTE_FC_RX_PAUSE;
3839         else if (tx_pause)
3840                 fc_conf->mode = RTE_FC_TX_PAUSE;
3841         else
3842                 fc_conf->mode = RTE_FC_NONE;
3843
3844         return 0;
3845 }
3846
3847 static int
3848 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3849 {
3850         struct ixgbe_hw *hw;
3851         int err;
3852         uint32_t rx_buf_size;
3853         uint32_t max_high_water;
3854         uint32_t mflcn;
3855         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3856                 ixgbe_fc_none,
3857                 ixgbe_fc_rx_pause,
3858                 ixgbe_fc_tx_pause,
3859                 ixgbe_fc_full
3860         };
3861
3862         PMD_INIT_FUNC_TRACE();
3863
3864         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3865         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3866         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3867
3868         /*
3869          * At least reserve one Ethernet frame for watermark
3870          * high_water/low_water in kilo bytes for ixgbe
3871          */
3872         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3873         if ((fc_conf->high_water > max_high_water) ||
3874                 (fc_conf->high_water < fc_conf->low_water)) {
3875                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3876                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3877                 return -EINVAL;
3878         }
3879
3880         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3881         hw->fc.pause_time     = fc_conf->pause_time;
3882         hw->fc.high_water[0]  = fc_conf->high_water;
3883         hw->fc.low_water[0]   = fc_conf->low_water;
3884         hw->fc.send_xon       = fc_conf->send_xon;
3885         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3886
3887         err = ixgbe_fc_enable(hw);
3888
3889         /* Not negotiated is not an error case */
3890         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3891
3892                 /* check if we want to forward MAC frames - driver doesn't have native
3893                  * capability to do that, so we'll write the registers ourselves */
3894
3895                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3896
3897                 /* set or clear MFLCN.PMCF bit depending on configuration */
3898                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3899                         mflcn |= IXGBE_MFLCN_PMCF;
3900                 else
3901                         mflcn &= ~IXGBE_MFLCN_PMCF;
3902
3903                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3904                 IXGBE_WRITE_FLUSH(hw);
3905
3906                 return 0;
3907         }
3908
3909         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3910         return -EIO;
3911 }
3912
3913 /**
3914  *  ixgbe_pfc_enable_generic - Enable flow control
3915  *  @hw: pointer to hardware structure
3916  *  @tc_num: traffic class number
3917  *  Enable flow control according to the current settings.
3918  */
3919 static int
3920 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
3921 {
3922         int ret_val = 0;
3923         uint32_t mflcn_reg, fccfg_reg;
3924         uint32_t reg;
3925         uint32_t fcrtl, fcrth;
3926         uint8_t i;
3927         uint8_t nb_rx_en;
3928
3929         /* Validate the water mark configuration */
3930         if (!hw->fc.pause_time) {
3931                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3932                 goto out;
3933         }
3934
3935         /* Low water mark of zero causes XOFF floods */
3936         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3937                  /* High/Low water can not be 0 */
3938                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
3939                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3940                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3941                         goto out;
3942                 }
3943
3944                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3945                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3946                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3947                         goto out;
3948                 }
3949         }
3950         /* Negotiate the fc mode to use */
3951         ixgbe_fc_autoneg(hw);
3952
3953         /* Disable any previous flow control settings */
3954         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3955         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3956
3957         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3958         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3959
3960         switch (hw->fc.current_mode) {
3961         case ixgbe_fc_none:
3962                 /*
3963                  * If the count of enabled RX Priority Flow control >1,
3964                  * and the TX pause can not be disabled
3965                  */
3966                 nb_rx_en = 0;
3967                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3968                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3969                         if (reg & IXGBE_FCRTH_FCEN)
3970                                 nb_rx_en++;
3971                 }
3972                 if (nb_rx_en > 1)
3973                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3974                 break;
3975         case ixgbe_fc_rx_pause:
3976                 /*
3977                  * Rx Flow control is enabled and Tx Flow control is
3978                  * disabled by software override. Since there really
3979                  * isn't a way to advertise that we are capable of RX
3980                  * Pause ONLY, we will advertise that we support both
3981                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3982                  * disable the adapter's ability to send PAUSE frames.
3983                  */
3984                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3985                 /*
3986                  * If the count of enabled RX Priority Flow control >1,
3987                  * and the TX pause can not be disabled
3988                  */
3989                 nb_rx_en = 0;
3990                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3991                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3992                         if (reg & IXGBE_FCRTH_FCEN)
3993                                 nb_rx_en++;
3994                 }
3995                 if (nb_rx_en > 1)
3996                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3997                 break;
3998         case ixgbe_fc_tx_pause:
3999                 /*
4000                  * Tx Flow control is enabled, and Rx Flow control is
4001                  * disabled by software override.
4002                  */
4003                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4004                 break;
4005         case ixgbe_fc_full:
4006                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4007                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4008                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4009                 break;
4010         default:
4011                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4012                 ret_val = IXGBE_ERR_CONFIG;
4013                 goto out;
4014         }
4015
4016         /* Set 802.3x based flow control settings. */
4017         mflcn_reg |= IXGBE_MFLCN_DPF;
4018         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4019         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4020
4021         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4022         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4023                 hw->fc.high_water[tc_num]) {
4024                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4025                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4026                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4027         } else {
4028                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4029                 /*
4030                  * In order to prevent Tx hangs when the internal Tx
4031                  * switch is enabled we must set the high water mark
4032                  * to the maximum FCRTH value.  This allows the Tx
4033                  * switch to function even under heavy Rx workloads.
4034                  */
4035                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4036         }
4037         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4038
4039         /* Configure pause time (2 TCs per register) */
4040         reg = hw->fc.pause_time * 0x00010001;
4041         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4042                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4043
4044         /* Configure flow control refresh threshold value */
4045         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4046
4047 out:
4048         return ret_val;
4049 }
4050
4051 static int
4052 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4053 {
4054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4055         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4056
4057         if (hw->mac.type != ixgbe_mac_82598EB) {
4058                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4059         }
4060         return ret_val;
4061 }
4062
4063 static int
4064 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4065 {
4066         int err;
4067         uint32_t rx_buf_size;
4068         uint32_t max_high_water;
4069         uint8_t tc_num;
4070         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4071         struct ixgbe_hw *hw =
4072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4073         struct ixgbe_dcb_config *dcb_config =
4074                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4075
4076         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4077                 ixgbe_fc_none,
4078                 ixgbe_fc_rx_pause,
4079                 ixgbe_fc_tx_pause,
4080                 ixgbe_fc_full
4081         };
4082
4083         PMD_INIT_FUNC_TRACE();
4084
4085         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4086         tc_num = map[pfc_conf->priority];
4087         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4088         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4089         /*
4090          * At least reserve one Ethernet frame for watermark
4091          * high_water/low_water in kilo bytes for ixgbe
4092          */
4093         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4094         if ((pfc_conf->fc.high_water > max_high_water) ||
4095             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4096                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4097                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4098                 return -EINVAL;
4099         }
4100
4101         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4102         hw->fc.pause_time = pfc_conf->fc.pause_time;
4103         hw->fc.send_xon = pfc_conf->fc.send_xon;
4104         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4105         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4106
4107         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4108
4109         /* Not negotiated is not an error case */
4110         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4111                 return 0;
4112
4113         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4114         return -EIO;
4115 }
4116
4117 static int
4118 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4119                           struct rte_eth_rss_reta_entry64 *reta_conf,
4120                           uint16_t reta_size)
4121 {
4122         uint16_t i, sp_reta_size;
4123         uint8_t j, mask;
4124         uint32_t reta, r;
4125         uint16_t idx, shift;
4126         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127         uint32_t reta_reg;
4128
4129         PMD_INIT_FUNC_TRACE();
4130
4131         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4132                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4133                         "NIC.");
4134                 return -ENOTSUP;
4135         }
4136
4137         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4138         if (reta_size != sp_reta_size) {
4139                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4140                         "(%d) doesn't match the number hardware can supported "
4141                         "(%d)\n", reta_size, sp_reta_size);
4142                 return -EINVAL;
4143         }
4144
4145         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4146                 idx = i / RTE_RETA_GROUP_SIZE;
4147                 shift = i % RTE_RETA_GROUP_SIZE;
4148                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4149                                                 IXGBE_4_BIT_MASK);
4150                 if (!mask)
4151                         continue;
4152                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4153                 if (mask == IXGBE_4_BIT_MASK)
4154                         r = 0;
4155                 else
4156                         r = IXGBE_READ_REG(hw, reta_reg);
4157                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4158                         if (mask & (0x1 << j))
4159                                 reta |= reta_conf[idx].reta[shift + j] <<
4160                                                         (CHAR_BIT * j);
4161                         else
4162                                 reta |= r & (IXGBE_8_BIT_MASK <<
4163                                                 (CHAR_BIT * j));
4164                 }
4165                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4166         }
4167
4168         return 0;
4169 }
4170
4171 static int
4172 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4173                          struct rte_eth_rss_reta_entry64 *reta_conf,
4174                          uint16_t reta_size)
4175 {
4176         uint16_t i, sp_reta_size;
4177         uint8_t j, mask;
4178         uint32_t reta;
4179         uint16_t idx, shift;
4180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181         uint32_t reta_reg;
4182
4183         PMD_INIT_FUNC_TRACE();
4184         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4185         if (reta_size != sp_reta_size) {
4186                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4187                         "(%d) doesn't match the number hardware can supported "
4188                         "(%d)\n", reta_size, sp_reta_size);
4189                 return -EINVAL;
4190         }
4191
4192         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4193                 idx = i / RTE_RETA_GROUP_SIZE;
4194                 shift = i % RTE_RETA_GROUP_SIZE;
4195                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4196                                                 IXGBE_4_BIT_MASK);
4197                 if (!mask)
4198                         continue;
4199
4200                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4201                 reta = IXGBE_READ_REG(hw, reta_reg);
4202                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4203                         if (mask & (0x1 << j))
4204                                 reta_conf[idx].reta[shift + j] =
4205                                         ((reta >> (CHAR_BIT * j)) &
4206                                                 IXGBE_8_BIT_MASK);
4207                 }
4208         }
4209
4210         return 0;
4211 }
4212
4213 static void
4214 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4215                                 uint32_t index, uint32_t pool)
4216 {
4217         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4218         uint32_t enable_addr = 1;
4219
4220         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4221 }
4222
4223 static void
4224 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4225 {
4226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4227
4228         ixgbe_clear_rar(hw, index);
4229 }
4230
4231 static void
4232 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4233 {
4234         ixgbe_remove_rar(dev, 0);
4235
4236         ixgbe_add_rar(dev, addr, 0, 0);
4237 }
4238
4239 int
4240 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4241                 struct ether_addr *mac_addr)
4242 {
4243         struct ixgbe_hw *hw;
4244         struct ixgbe_vf_info *vfinfo;
4245         int rar_entry;
4246         uint8_t *new_mac = (uint8_t *)(mac_addr);
4247         struct rte_eth_dev *dev;
4248         struct rte_eth_dev_info dev_info;
4249
4250         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4251
4252         dev = &rte_eth_devices[port];
4253         rte_eth_dev_info_get(port, &dev_info);
4254
4255         if (vf >= dev_info.max_vfs)
4256                 return -EINVAL;
4257
4258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4259         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4260         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4261
4262         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4263                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4264                                 ETHER_ADDR_LEN);
4265                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4266                                 IXGBE_RAH_AV);
4267         }
4268         return -EINVAL;
4269 }
4270
4271 static int
4272 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4273 {
4274         uint32_t hlreg0;
4275         uint32_t maxfrs;
4276         struct ixgbe_hw *hw;
4277         struct rte_eth_dev_info dev_info;
4278         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4279
4280         ixgbe_dev_info_get(dev, &dev_info);
4281
4282         /* check that mtu is within the allowed range */
4283         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4284                 return -EINVAL;
4285
4286         /* refuse mtu that requires the support of scattered packets when this
4287          * feature has not been enabled before.
4288          */
4289         if (!dev->data->scattered_rx &&
4290             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4291              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4292                 return -EINVAL;
4293
4294         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4295         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4296
4297         /* switch to jumbo mode if needed */
4298         if (frame_size > ETHER_MAX_LEN) {
4299                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4300                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4301         } else {
4302                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4303                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4304         }
4305         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4306
4307         /* update max frame size */
4308         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4309
4310         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4311         maxfrs &= 0x0000FFFF;
4312         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4313         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4314
4315         return 0;
4316 }
4317
4318 /*
4319  * Virtual Function operations
4320  */
4321 static void
4322 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4323 {
4324         PMD_INIT_FUNC_TRACE();
4325
4326         /* Clear interrupt mask to stop from interrupts being generated */
4327         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4328
4329         IXGBE_WRITE_FLUSH(hw);
4330 }
4331
4332 static void
4333 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4334 {
4335         PMD_INIT_FUNC_TRACE();
4336
4337         /* VF enable interrupt autoclean */
4338         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4339         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4340         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4341
4342         IXGBE_WRITE_FLUSH(hw);
4343 }
4344
4345 static int
4346 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4347 {
4348         struct rte_eth_conf *conf = &dev->data->dev_conf;
4349         struct ixgbe_adapter *adapter =
4350                         (struct ixgbe_adapter *)dev->data->dev_private;
4351
4352         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4353                      dev->data->port_id);
4354
4355         /*
4356          * VF has no ability to enable/disable HW CRC
4357          * Keep the persistent behavior the same as Host PF
4358          */
4359 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4360         if (!conf->rxmode.hw_strip_crc) {
4361                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4362                 conf->rxmode.hw_strip_crc = 1;
4363         }
4364 #else
4365         if (conf->rxmode.hw_strip_crc) {
4366                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4367                 conf->rxmode.hw_strip_crc = 0;
4368         }
4369 #endif
4370
4371         /*
4372          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4373          * allocation or vector Rx preconditions we will reset it.
4374          */
4375         adapter->rx_bulk_alloc_allowed = true;
4376         adapter->rx_vec_allowed = true;
4377
4378         return 0;
4379 }
4380
4381 static int
4382 ixgbevf_dev_start(struct rte_eth_dev *dev)
4383 {
4384         struct ixgbe_hw *hw =
4385                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4386         uint32_t intr_vector = 0;
4387         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4388         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4389
4390         int err, mask = 0;
4391
4392         PMD_INIT_FUNC_TRACE();
4393
4394         hw->mac.ops.reset_hw(hw);
4395         hw->mac.get_link_status = true;
4396
4397         /* negotiate mailbox API version to use with the PF. */
4398         ixgbevf_negotiate_api(hw);
4399
4400         ixgbevf_dev_tx_init(dev);
4401
4402         /* This can fail when allocating mbufs for descriptor rings */
4403         err = ixgbevf_dev_rx_init(dev);
4404         if (err) {
4405                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4406                 ixgbe_dev_clear_queues(dev);
4407                 return err;
4408         }
4409
4410         /* Set vfta */
4411         ixgbevf_set_vfta_all(dev, 1);
4412
4413         /* Set HW strip */
4414         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4415                 ETH_VLAN_EXTEND_MASK;
4416         ixgbevf_vlan_offload_set(dev, mask);
4417
4418         ixgbevf_dev_rxtx_start(dev);
4419
4420         /* check and configure queue intr-vector mapping */
4421         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4422                 intr_vector = dev->data->nb_rx_queues;
4423                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4424                         return -1;
4425         }
4426
4427         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4428                 intr_handle->intr_vec =
4429                         rte_zmalloc("intr_vec",
4430                                     dev->data->nb_rx_queues * sizeof(int), 0);
4431                 if (intr_handle->intr_vec == NULL) {
4432                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4433                                      " intr_vec\n", dev->data->nb_rx_queues);
4434                         return -ENOMEM;
4435                 }
4436         }
4437         ixgbevf_configure_msix(dev);
4438
4439         rte_intr_enable(intr_handle);
4440
4441         /* Re-enable interrupt for VF */
4442         ixgbevf_intr_enable(hw);
4443
4444         return 0;
4445 }
4446
4447 static void
4448 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4449 {
4450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4453
4454         PMD_INIT_FUNC_TRACE();
4455
4456         ixgbevf_intr_disable(hw);
4457
4458         hw->adapter_stopped = 1;
4459         ixgbe_stop_adapter(hw);
4460
4461         /*
4462           * Clear what we set, but we still keep shadow_vfta to
4463           * restore after device starts
4464           */
4465         ixgbevf_set_vfta_all(dev, 0);
4466
4467         /* Clear stored conf */
4468         dev->data->scattered_rx = 0;
4469
4470         ixgbe_dev_clear_queues(dev);
4471
4472         /* Clean datapath event and queue/vec mapping */
4473         rte_intr_efd_disable(intr_handle);
4474         if (intr_handle->intr_vec != NULL) {
4475                 rte_free(intr_handle->intr_vec);
4476                 intr_handle->intr_vec = NULL;
4477         }
4478 }
4479
4480 static void
4481 ixgbevf_dev_close(struct rte_eth_dev *dev)
4482 {
4483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4484
4485         PMD_INIT_FUNC_TRACE();
4486
4487         ixgbe_reset_hw(hw);
4488
4489         ixgbevf_dev_stop(dev);
4490
4491         ixgbe_dev_free_queues(dev);
4492
4493         /**
4494          * Remove the VF MAC address ro ensure
4495          * that the VF traffic goes to the PF
4496          * after stop, close and detach of the VF
4497          **/
4498         ixgbevf_remove_mac_addr(dev, 0);
4499 }
4500
4501 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4502 {
4503         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4504         struct ixgbe_vfta *shadow_vfta =
4505                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4506         int i = 0, j = 0, vfta = 0, mask = 1;
4507
4508         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4509                 vfta = shadow_vfta->vfta[i];
4510                 if (vfta) {
4511                         mask = 1;
4512                         for (j = 0; j < 32; j++) {
4513                                 if (vfta & mask)
4514                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4515                                                        on, false);
4516                                 mask <<= 1;
4517                         }
4518                 }
4519         }
4520
4521 }
4522
4523 static int
4524 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4525 {
4526         struct ixgbe_hw *hw =
4527                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4528         struct ixgbe_vfta *shadow_vfta =
4529                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4530         uint32_t vid_idx = 0;
4531         uint32_t vid_bit = 0;
4532         int ret = 0;
4533
4534         PMD_INIT_FUNC_TRACE();
4535
4536         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4537         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4538         if (ret) {
4539                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4540                 return ret;
4541         }
4542         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4543         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4544
4545         /* Save what we set and retore it after device reset */
4546         if (on)
4547                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4548         else
4549                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4550
4551         return 0;
4552 }
4553
4554 static void
4555 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4556 {
4557         struct ixgbe_hw *hw =
4558                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4559         uint32_t ctrl;
4560
4561         PMD_INIT_FUNC_TRACE();
4562
4563         if (queue >= hw->mac.max_rx_queues)
4564                 return;
4565
4566         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4567         if (on)
4568                 ctrl |= IXGBE_RXDCTL_VME;
4569         else
4570                 ctrl &= ~IXGBE_RXDCTL_VME;
4571         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4572
4573         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4574 }
4575
4576 static void
4577 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4578 {
4579         struct ixgbe_hw *hw =
4580                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4581         uint16_t i;
4582         int on = 0;
4583
4584         /* VF function only support hw strip feature, others are not support */
4585         if (mask & ETH_VLAN_STRIP_MASK) {
4586                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4587
4588                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4589                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4590         }
4591 }
4592
4593 static int
4594 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4595 {
4596         uint32_t reg_val;
4597
4598         /* we only need to do this if VMDq is enabled */
4599         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4600         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4601                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4602                 return -1;
4603         }
4604
4605         return 0;
4606 }
4607
4608 static uint32_t
4609 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4610 {
4611         uint32_t vector = 0;
4612
4613         switch (hw->mac.mc_filter_type) {
4614         case 0:   /* use bits [47:36] of the address */
4615                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4616                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4617                 break;
4618         case 1:   /* use bits [46:35] of the address */
4619                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4620                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4621                 break;
4622         case 2:   /* use bits [45:34] of the address */
4623                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4624                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4625                 break;
4626         case 3:   /* use bits [43:32] of the address */
4627                 vector = ((uc_addr->addr_bytes[4]) |
4628                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4629                 break;
4630         default:  /* Invalid mc_filter_type */
4631                 break;
4632         }
4633
4634         /* vector can only be 12-bits or boundary will be exceeded */
4635         vector &= 0xFFF;
4636         return vector;
4637 }
4638
4639 static int
4640 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4641                         uint8_t on)
4642 {
4643         uint32_t vector;
4644         uint32_t uta_idx;
4645         uint32_t reg_val;
4646         uint32_t uta_shift;
4647         uint32_t rc;
4648         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4649         const uint32_t ixgbe_uta_bit_shift = 5;
4650         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4651         const uint32_t bit1 = 0x1;
4652
4653         struct ixgbe_hw *hw =
4654                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4655         struct ixgbe_uta_info *uta_info =
4656                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4657
4658         /* The UTA table only exists on 82599 hardware and newer */
4659         if (hw->mac.type < ixgbe_mac_82599EB)
4660                 return -ENOTSUP;
4661
4662         vector = ixgbe_uta_vector(hw, mac_addr);
4663         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4664         uta_shift = vector & ixgbe_uta_bit_mask;
4665
4666         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4667         if (rc == on)
4668                 return 0;
4669
4670         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4671         if (on) {
4672                 uta_info->uta_in_use++;
4673                 reg_val |= (bit1 << uta_shift);
4674                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4675         } else {
4676                 uta_info->uta_in_use--;
4677                 reg_val &= ~(bit1 << uta_shift);
4678                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4679         }
4680
4681         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4682
4683         if (uta_info->uta_in_use > 0)
4684                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4685                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4686         else
4687                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4688
4689         return 0;
4690 }
4691
4692 static int
4693 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4694 {
4695         int i;
4696         struct ixgbe_hw *hw =
4697                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4698         struct ixgbe_uta_info *uta_info =
4699                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4700
4701         /* The UTA table only exists on 82599 hardware and newer */
4702         if (hw->mac.type < ixgbe_mac_82599EB)
4703                 return -ENOTSUP;
4704
4705         if (on) {
4706                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4707                         uta_info->uta_shadow[i] = ~0;
4708                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4709                 }
4710         } else {
4711                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4712                         uta_info->uta_shadow[i] = 0;
4713                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4714                 }
4715         }
4716         return 0;
4717
4718 }
4719
4720 uint32_t
4721 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4722 {
4723         uint32_t new_val = orig_val;
4724
4725         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4726                 new_val |= IXGBE_VMOLR_AUPE;
4727         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4728                 new_val |= IXGBE_VMOLR_ROMPE;
4729         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4730                 new_val |= IXGBE_VMOLR_ROPE;
4731         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4732                 new_val |= IXGBE_VMOLR_BAM;
4733         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4734                 new_val |= IXGBE_VMOLR_MPE;
4735
4736         return new_val;
4737 }
4738
4739 static int
4740 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4741                                uint16_t rx_mask, uint8_t on)
4742 {
4743         int val = 0;
4744
4745         struct ixgbe_hw *hw =
4746                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4747         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4748
4749         if (hw->mac.type == ixgbe_mac_82598EB) {
4750                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4751                              " on 82599 hardware and newer");
4752                 return -ENOTSUP;
4753         }
4754         if (ixgbe_vmdq_mode_check(hw) < 0)
4755                 return -ENOTSUP;
4756
4757         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4758
4759         if (on)
4760                 vmolr |= val;
4761         else
4762                 vmolr &= ~val;
4763
4764         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4765
4766         return 0;
4767 }
4768
4769 static int
4770 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4771 {
4772         uint32_t reg, addr;
4773         uint32_t val;
4774         const uint8_t bit1 = 0x1;
4775
4776         struct ixgbe_hw *hw =
4777                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4778
4779         if (ixgbe_vmdq_mode_check(hw) < 0)
4780                 return -ENOTSUP;
4781
4782         if (pool >= ETH_64_POOLS)
4783                 return -EINVAL;
4784
4785         /* for pool >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
4786         if (pool >= 32) {
4787                 addr = IXGBE_VFRE(1);
4788                 val = bit1 << (pool - 32);
4789         } else {
4790                 addr = IXGBE_VFRE(0);
4791                 val = bit1 << pool;
4792         }
4793
4794         reg = IXGBE_READ_REG(hw, addr);
4795
4796         if (on)
4797                 reg |= val;
4798         else
4799                 reg &= ~val;
4800
4801         IXGBE_WRITE_REG(hw, addr, reg);
4802
4803         return 0;
4804 }
4805
4806 static int
4807 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4808 {
4809         uint32_t reg, addr;
4810         uint32_t val;
4811         const uint8_t bit1 = 0x1;
4812
4813         struct ixgbe_hw *hw =
4814                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4815
4816         if (ixgbe_vmdq_mode_check(hw) < 0)
4817                 return -ENOTSUP;
4818
4819         if (pool >= ETH_64_POOLS)
4820                 return -EINVAL;
4821
4822         /* for pool >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
4823         if (pool >= 32) {
4824                 addr = IXGBE_VFTE(1);
4825                 val = bit1 << (pool - 32);
4826         } else {
4827                 addr = IXGBE_VFTE(0);
4828                 val = bit1 << pool;
4829         }
4830
4831         reg = IXGBE_READ_REG(hw, addr);
4832
4833         if (on)
4834                 reg |= val;
4835         else
4836                 reg &= ~val;
4837
4838         IXGBE_WRITE_REG(hw, addr, reg);
4839
4840         return 0;
4841 }
4842
4843 static int
4844 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4845                         uint64_t pool_mask, uint8_t vlan_on)
4846 {
4847         int ret = 0;
4848         uint16_t pool_idx;
4849         struct ixgbe_hw *hw =
4850                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4851
4852         if (ixgbe_vmdq_mode_check(hw) < 0)
4853                 return -ENOTSUP;
4854         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4855                 if (pool_mask & ((uint64_t)(1ULL << pool_idx))) {
4856                         ret = hw->mac.ops.set_vfta(hw, vlan, pool_idx,
4857                                                    vlan_on, false);
4858                         if (ret < 0)
4859                                 return ret;
4860                 }
4861         }
4862
4863         return ret;
4864 }
4865
4866 int
4867 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4868 {
4869         struct ixgbe_hw *hw;
4870         struct ixgbe_mac_info *mac;
4871         struct rte_eth_dev *dev;
4872         struct rte_eth_dev_info dev_info;
4873
4874         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4875
4876         dev = &rte_eth_devices[port];
4877         rte_eth_dev_info_get(port, &dev_info);
4878
4879         if (vf >= dev_info.max_vfs)
4880                 return -EINVAL;
4881
4882         if (on > 1)
4883                 return -EINVAL;
4884
4885         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4886         mac = &hw->mac;
4887
4888         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4889
4890         return 0;
4891 }
4892
4893 int
4894 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4895 {
4896         struct ixgbe_hw *hw;
4897         struct ixgbe_mac_info *mac;
4898         struct rte_eth_dev *dev;
4899         struct rte_eth_dev_info dev_info;
4900
4901         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4902
4903         dev = &rte_eth_devices[port];
4904         rte_eth_dev_info_get(port, &dev_info);
4905
4906         if (vf >= dev_info.max_vfs)
4907                 return -EINVAL;
4908
4909         if (on > 1)
4910                 return -EINVAL;
4911
4912         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4913         mac = &hw->mac;
4914         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4915
4916         return 0;
4917 }
4918
4919 int
4920 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4921 {
4922         struct ixgbe_hw *hw;
4923         uint32_t ctrl;
4924         struct rte_eth_dev *dev;
4925         struct rte_eth_dev_info dev_info;
4926
4927         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4928
4929         dev = &rte_eth_devices[port];
4930         rte_eth_dev_info_get(port, &dev_info);
4931
4932         if (vf >= dev_info.max_vfs)
4933                 return -EINVAL;
4934
4935         if (vlan_id > 4095)
4936                 return -EINVAL;
4937
4938         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4940         if (vlan_id) {
4941                 ctrl = vlan_id;
4942                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4943         } else {
4944                 ctrl = 0;
4945         }
4946
4947         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4948
4949         return 0;
4950 }
4951
4952 int
4953 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4954 {
4955         struct ixgbe_hw *hw;
4956         uint32_t ctrl;
4957         struct rte_eth_dev *dev;
4958
4959         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4960
4961         dev = &rte_eth_devices[port];
4962
4963         if (on > 1)
4964                 return -EINVAL;
4965
4966         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4967         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4968         /* enable or disable VMDQ loopback */
4969         if (on)
4970                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
4971         else
4972                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4973
4974         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
4975
4976         return 0;
4977 }
4978
4979 int
4980 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
4981 {
4982         struct ixgbe_hw *hw;
4983         uint32_t reg_value;
4984         int i;
4985         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
4986         struct rte_eth_dev *dev;
4987
4988         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4989
4990         dev = &rte_eth_devices[port];
4991
4992         if (on > 1)
4993                 return -EINVAL;
4994
4995         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4996         for (i = 0; i <= num_queues; i++) {
4997                 reg_value = IXGBE_QDE_WRITE |
4998                                 (i << IXGBE_QDE_IDX_SHIFT) |
4999                                 (on & IXGBE_QDE_ENABLE);
5000                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5001         }
5002
5003         return 0;
5004 }
5005
5006 int
5007 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5008 {
5009         struct ixgbe_hw *hw;
5010         uint32_t reg_value;
5011         struct rte_eth_dev *dev;
5012         struct rte_eth_dev_info dev_info;
5013
5014         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5015
5016         dev = &rte_eth_devices[port];
5017         rte_eth_dev_info_get(port, &dev_info);
5018
5019         /* only support VF's 0 to 63 */
5020         if ((vf >= dev_info.max_vfs) || (vf > 63))
5021                 return -EINVAL;
5022
5023         if (on > 1)
5024                 return -EINVAL;
5025
5026         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5027         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5028         if (on)
5029                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5030         else
5031                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5032
5033         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5034
5035         return 0;
5036 }
5037
5038 int
5039 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5040 {
5041         struct rte_eth_dev *dev;
5042         struct rte_eth_dev_info dev_info;
5043         uint16_t queues_per_pool;
5044         uint32_t q;
5045
5046         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5047
5048         dev = &rte_eth_devices[port];
5049         rte_eth_dev_info_get(port, &dev_info);
5050
5051         if (vf >= dev_info.max_vfs)
5052                 return -EINVAL;
5053
5054         if (on > 1)
5055                 return -EINVAL;
5056
5057         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5058
5059         /* The PF has 128 queue pairs and in SRIOV configuration
5060          * those queues will be assigned to VF's, so RXDCTL
5061          * registers will be dealing with queues which will be
5062          * assigned to VF's.
5063          * Let's say we have SRIOV configured with 31 VF's then the
5064          * first 124 queues 0-123 will be allocated to VF's and only
5065          * the last 4 queues 123-127 will be assigned to the PF.
5066          */
5067
5068         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5069
5070         for (q = 0; q < queues_per_pool; q++)
5071                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5072                                 q + vf * queues_per_pool, on);
5073         return 0;
5074 }
5075
5076 int
5077 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5078 {
5079         int val = 0;
5080         struct rte_eth_dev *dev;
5081         struct rte_eth_dev_info dev_info;
5082         struct ixgbe_hw *hw;
5083         uint32_t vmolr;
5084
5085         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5086
5087         dev = &rte_eth_devices[port];
5088         rte_eth_dev_info_get(port, &dev_info);
5089
5090         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5091                 return -ENOTSUP;
5092
5093         if (vf >= dev_info.max_vfs)
5094                 return -EINVAL;
5095
5096         if (on > 1)
5097                 return -EINVAL;
5098
5099         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5101
5102         if (hw->mac.type == ixgbe_mac_82598EB) {
5103                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5104                              " on 82599 hardware and newer");
5105                 return -ENOTSUP;
5106         }
5107         if (ixgbe_vmdq_mode_check(hw) < 0)
5108                 return -ENOTSUP;
5109
5110         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5111
5112         if (on)
5113                 vmolr |= val;
5114         else
5115                 vmolr &= ~val;
5116
5117         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5118
5119         return 0;
5120 }
5121
5122 int
5123 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5124 {
5125         struct rte_eth_dev *dev;
5126         struct rte_eth_dev_info dev_info;
5127         uint32_t reg, addr;
5128         uint32_t val;
5129         const uint8_t bit1 = 0x1;
5130         struct ixgbe_hw *hw;
5131
5132         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5133
5134         dev = &rte_eth_devices[port];
5135         rte_eth_dev_info_get(port, &dev_info);
5136
5137         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5138                 return -ENOTSUP;
5139
5140         if (vf >= dev_info.max_vfs)
5141                 return -EINVAL;
5142
5143         if (on > 1)
5144                 return -EINVAL;
5145
5146         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5147
5148         if (ixgbe_vmdq_mode_check(hw) < 0)
5149                 return -ENOTSUP;
5150
5151         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5152         if (vf >= 32) {
5153                 addr = IXGBE_VFRE(1);
5154                 val = bit1 << (vf - 32);
5155         } else {
5156                 addr = IXGBE_VFRE(0);
5157                 val = bit1 << vf;
5158         }
5159
5160         reg = IXGBE_READ_REG(hw, addr);
5161
5162         if (on)
5163                 reg |= val;
5164         else
5165                 reg &= ~val;
5166
5167         IXGBE_WRITE_REG(hw, addr, reg);
5168
5169         return 0;
5170 }
5171
5172 int
5173 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5174 {
5175         struct rte_eth_dev *dev;
5176         struct rte_eth_dev_info dev_info;
5177         uint32_t reg, addr;
5178         uint32_t val;
5179         const uint8_t bit1 = 0x1;
5180
5181         struct ixgbe_hw *hw;
5182
5183         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5184
5185         dev = &rte_eth_devices[port];
5186         rte_eth_dev_info_get(port, &dev_info);
5187
5188         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5189                 return -ENOTSUP;
5190
5191         if (vf >= dev_info.max_vfs)
5192                 return -EINVAL;
5193
5194         if (on > 1)
5195                 return -EINVAL;
5196
5197         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5198         if (ixgbe_vmdq_mode_check(hw) < 0)
5199                 return -ENOTSUP;
5200
5201         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5202         if (vf >= 32) {
5203                 addr = IXGBE_VFTE(1);
5204                 val = bit1 << (vf - 32);
5205         } else {
5206                 addr = IXGBE_VFTE(0);
5207                 val = bit1 << vf;
5208         }
5209
5210         reg = IXGBE_READ_REG(hw, addr);
5211
5212         if (on)
5213                 reg |= val;
5214         else
5215                 reg &= ~val;
5216
5217         IXGBE_WRITE_REG(hw, addr, reg);
5218
5219         return 0;
5220 }
5221
5222 int
5223 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5224                         uint64_t vf_mask, uint8_t vlan_on)
5225 {
5226         struct rte_eth_dev *dev;
5227         struct rte_eth_dev_info dev_info;
5228         int ret = 0;
5229         uint16_t vf_idx;
5230         struct ixgbe_hw *hw;
5231
5232         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5233
5234         dev = &rte_eth_devices[port];
5235         rte_eth_dev_info_get(port, &dev_info);
5236
5237         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5238                 return -ENOTSUP;
5239
5240         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5241                 return -EINVAL;
5242
5243         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5244         if (ixgbe_vmdq_mode_check(hw) < 0)
5245                 return -ENOTSUP;
5246
5247         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5248                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5249                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5250                                                    vlan_on, false);
5251                         if (ret < 0)
5252                                 return ret;
5253                 }
5254         }
5255
5256         return ret;
5257 }
5258
5259 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5260         uint16_t tx_rate, uint64_t q_msk)
5261 {
5262         struct rte_eth_dev *dev;
5263         struct rte_eth_dev_info dev_info;
5264         struct ixgbe_hw *hw;
5265         struct ixgbe_vf_info *vfinfo;
5266         struct rte_eth_link link;
5267         uint8_t  nb_q_per_pool;
5268         uint32_t queue_stride;
5269         uint32_t queue_idx, idx = 0, vf_idx;
5270         uint32_t queue_end;
5271         uint16_t total_rate = 0;
5272         struct rte_pci_device *pci_dev;
5273
5274         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5275
5276         dev = &rte_eth_devices[port];
5277         rte_eth_dev_info_get(port, &dev_info);
5278         rte_eth_link_get_nowait(port, &link);
5279
5280         if (strstr(dev_info.driver_name, "ixgbe_vf"))
5281                 return -ENOTSUP;
5282
5283         if (vf >= dev_info.max_vfs)
5284                 return -EINVAL;
5285
5286         if (tx_rate > link.link_speed)
5287                 return -EINVAL;
5288
5289         if (q_msk == 0)
5290                 return 0;
5291
5292         pci_dev = IXGBE_DEV_TO_PCI(dev);
5293         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5295         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5296         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5297         queue_idx = vf * queue_stride;
5298         queue_end = queue_idx + nb_q_per_pool - 1;
5299         if (queue_end >= hw->mac.max_tx_queues)
5300                 return -EINVAL;
5301
5302         if (vfinfo) {
5303                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5304                         if (vf_idx == vf)
5305                                 continue;
5306                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5307                                 idx++)
5308                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5309                 }
5310         } else {
5311                 return -EINVAL;
5312         }
5313
5314         /* Store tx_rate for this vf. */
5315         for (idx = 0; idx < nb_q_per_pool; idx++) {
5316                 if (((uint64_t)0x1 << idx) & q_msk) {
5317                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5318                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5319                         total_rate += tx_rate;
5320                 }
5321         }
5322
5323         if (total_rate > dev->data->dev_link.link_speed) {
5324                 /* Reset stored TX rate of the VF if it causes exceed
5325                  * link speed.
5326                  */
5327                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5328                 return -EINVAL;
5329         }
5330
5331         /* Set RTTBCNRC of each queue/pool for vf X  */
5332         for (; queue_idx <= queue_end; queue_idx++) {
5333                 if (0x1 & q_msk)
5334                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5335                 q_msk = q_msk >> 1;
5336         }
5337
5338         return 0;
5339 }
5340
5341 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5342 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5343 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5344 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5345 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5346         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5347         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5348
5349 static int
5350 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5351                         struct rte_eth_mirror_conf *mirror_conf,
5352                         uint8_t rule_id, uint8_t on)
5353 {
5354         uint32_t mr_ctl, vlvf;
5355         uint32_t mp_lsb = 0;
5356         uint32_t mv_msb = 0;
5357         uint32_t mv_lsb = 0;
5358         uint32_t mp_msb = 0;
5359         uint8_t i = 0;
5360         int reg_index = 0;
5361         uint64_t vlan_mask = 0;
5362
5363         const uint8_t pool_mask_offset = 32;
5364         const uint8_t vlan_mask_offset = 32;
5365         const uint8_t dst_pool_offset = 8;
5366         const uint8_t rule_mr_offset  = 4;
5367         const uint8_t mirror_rule_mask = 0x0F;
5368
5369         struct ixgbe_mirror_info *mr_info =
5370                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5371         struct ixgbe_hw *hw =
5372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5373         uint8_t mirror_type = 0;
5374
5375         if (ixgbe_vmdq_mode_check(hw) < 0)
5376                 return -ENOTSUP;
5377
5378         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5379                 return -EINVAL;
5380
5381         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5382                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5383                         mirror_conf->rule_type);
5384                 return -EINVAL;
5385         }
5386
5387         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5388                 mirror_type |= IXGBE_MRCTL_VLME;
5389                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5390                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5391                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5392                                 /* search vlan id related pool vlan filter index */
5393                                 reg_index = ixgbe_find_vlvf_slot(hw,
5394                                                  mirror_conf->vlan.vlan_id[i],
5395                                                  false);
5396                                 if (reg_index < 0)
5397                                         return -EINVAL;
5398                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5399                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5400                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5401                                       mirror_conf->vlan.vlan_id[i]))
5402                                         vlan_mask |= (1ULL << reg_index);
5403                                 else
5404                                         return -EINVAL;
5405                         }
5406                 }
5407
5408                 if (on) {
5409                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5410                         mv_msb = vlan_mask >> vlan_mask_offset;
5411
5412                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5413                                                 mirror_conf->vlan.vlan_mask;
5414                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5415                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5416                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5417                                                 mirror_conf->vlan.vlan_id[i];
5418                         }
5419                 } else {
5420                         mv_lsb = 0;
5421                         mv_msb = 0;
5422                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5423                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5424                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5425                 }
5426         }
5427
5428         /*
5429          * if enable pool mirror, write related pool mask register,if disable
5430          * pool mirror, clear PFMRVM register
5431          */
5432         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5433                 mirror_type |= IXGBE_MRCTL_VPME;
5434                 if (on) {
5435                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5436                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5437                         mr_info->mr_conf[rule_id].pool_mask =
5438                                         mirror_conf->pool_mask;
5439
5440                 } else {
5441                         mp_lsb = 0;
5442                         mp_msb = 0;
5443                         mr_info->mr_conf[rule_id].pool_mask = 0;
5444                 }
5445         }
5446         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5447                 mirror_type |= IXGBE_MRCTL_UPME;
5448         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5449                 mirror_type |= IXGBE_MRCTL_DPME;
5450
5451         /* read  mirror control register and recalculate it */
5452         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5453
5454         if (on) {
5455                 mr_ctl |= mirror_type;
5456                 mr_ctl &= mirror_rule_mask;
5457                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5458         } else
5459                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5460
5461         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5462         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5463
5464         /* write mirrror control  register */
5465         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5466
5467         /* write pool mirrror control  register */
5468         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5469                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5470                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5471                                 mp_msb);
5472         }
5473         /* write VLAN mirrror control  register */
5474         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5475                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5476                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5477                                 mv_msb);
5478         }
5479
5480         return 0;
5481 }
5482
5483 static int
5484 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5485 {
5486         int mr_ctl = 0;
5487         uint32_t lsb_val = 0;
5488         uint32_t msb_val = 0;
5489         const uint8_t rule_mr_offset = 4;
5490
5491         struct ixgbe_hw *hw =
5492                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5493         struct ixgbe_mirror_info *mr_info =
5494                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5495
5496         if (ixgbe_vmdq_mode_check(hw) < 0)
5497                 return -ENOTSUP;
5498
5499         memset(&mr_info->mr_conf[rule_id], 0,
5500                 sizeof(struct rte_eth_mirror_conf));
5501
5502         /* clear PFVMCTL register */
5503         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5504
5505         /* clear pool mask register */
5506         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5507         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5508
5509         /* clear vlan mask register */
5510         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5511         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5512
5513         return 0;
5514 }
5515
5516 static int
5517 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5518 {
5519         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5520         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5521         uint32_t mask;
5522         struct ixgbe_hw *hw =
5523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524
5525         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5526         mask |= (1 << IXGBE_MISC_VEC_ID);
5527         RTE_SET_USED(queue_id);
5528         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5529
5530         rte_intr_enable(intr_handle);
5531
5532         return 0;
5533 }
5534
5535 static int
5536 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5537 {
5538         uint32_t mask;
5539         struct ixgbe_hw *hw =
5540                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5541
5542         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5543         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5544         RTE_SET_USED(queue_id);
5545         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5546
5547         return 0;
5548 }
5549
5550 static int
5551 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5552 {
5553         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5554         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5555         uint32_t mask;
5556         struct ixgbe_hw *hw =
5557                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5558         struct ixgbe_interrupt *intr =
5559                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5560
5561         if (queue_id < 16) {
5562                 ixgbe_disable_intr(hw);
5563                 intr->mask |= (1 << queue_id);
5564                 ixgbe_enable_intr(dev);
5565         } else if (queue_id < 32) {
5566                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5567                 mask &= (1 << queue_id);
5568                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5569         } else if (queue_id < 64) {
5570                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5571                 mask &= (1 << (queue_id - 32));
5572                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5573         }
5574         rte_intr_enable(intr_handle);
5575
5576         return 0;
5577 }
5578
5579 static int
5580 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5581 {
5582         uint32_t mask;
5583         struct ixgbe_hw *hw =
5584                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5585         struct ixgbe_interrupt *intr =
5586                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5587
5588         if (queue_id < 16) {
5589                 ixgbe_disable_intr(hw);
5590                 intr->mask &= ~(1 << queue_id);
5591                 ixgbe_enable_intr(dev);
5592         } else if (queue_id < 32) {
5593                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5594                 mask &= ~(1 << queue_id);
5595                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5596         } else if (queue_id < 64) {
5597                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5598                 mask &= ~(1 << (queue_id - 32));
5599                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5600         }
5601
5602         return 0;
5603 }
5604
5605 static void
5606 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5607                      uint8_t queue, uint8_t msix_vector)
5608 {
5609         uint32_t tmp, idx;
5610
5611         if (direction == -1) {
5612                 /* other causes */
5613                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5614                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5615                 tmp &= ~0xFF;
5616                 tmp |= msix_vector;
5617                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5618         } else {
5619                 /* rx or tx cause */
5620                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5621                 idx = ((16 * (queue & 1)) + (8 * direction));
5622                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5623                 tmp &= ~(0xFF << idx);
5624                 tmp |= (msix_vector << idx);
5625                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5626         }
5627 }
5628
5629 /**
5630  * set the IVAR registers, mapping interrupt causes to vectors
5631  * @param hw
5632  *  pointer to ixgbe_hw struct
5633  * @direction
5634  *  0 for Rx, 1 for Tx, -1 for other causes
5635  * @queue
5636  *  queue to map the corresponding interrupt to
5637  * @msix_vector
5638  *  the vector to map to the corresponding queue
5639  */
5640 static void
5641 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5642                    uint8_t queue, uint8_t msix_vector)
5643 {
5644         uint32_t tmp, idx;
5645
5646         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5647         if (hw->mac.type == ixgbe_mac_82598EB) {
5648                 if (direction == -1)
5649                         direction = 0;
5650                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5651                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5652                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5653                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5654                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5655         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5656                         (hw->mac.type == ixgbe_mac_X540)) {
5657                 if (direction == -1) {
5658                         /* other causes */
5659                         idx = ((queue & 1) * 8);
5660                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5661                         tmp &= ~(0xFF << idx);
5662                         tmp |= (msix_vector << idx);
5663                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5664                 } else {
5665                         /* rx or tx causes */
5666                         idx = ((16 * (queue & 1)) + (8 * direction));
5667                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5668                         tmp &= ~(0xFF << idx);
5669                         tmp |= (msix_vector << idx);
5670                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5671                 }
5672         }
5673 }
5674
5675 static void
5676 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5677 {
5678         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5679         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5680         struct ixgbe_hw *hw =
5681                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5682         uint32_t q_idx;
5683         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5684
5685         /* Configure VF other cause ivar */
5686         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5687
5688         /* won't configure msix register if no mapping is done
5689          * between intr vector and event fd.
5690          */
5691         if (!rte_intr_dp_is_en(intr_handle))
5692                 return;
5693
5694         /* Configure all RX queues of VF */
5695         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5696                 /* Force all queue use vector 0,
5697                  * as IXGBE_VF_MAXMSIVECOTR = 1
5698                  */
5699                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5700                 intr_handle->intr_vec[q_idx] = vector_idx;
5701         }
5702 }
5703
5704 /**
5705  * Sets up the hardware to properly generate MSI-X interrupts
5706  * @hw
5707  *  board private structure
5708  */
5709 static void
5710 ixgbe_configure_msix(struct rte_eth_dev *dev)
5711 {
5712         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5713         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5714         struct ixgbe_hw *hw =
5715                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5716         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5717         uint32_t vec = IXGBE_MISC_VEC_ID;
5718         uint32_t mask;
5719         uint32_t gpie;
5720
5721         /* won't configure msix register if no mapping is done
5722          * between intr vector and event fd
5723          */
5724         if (!rte_intr_dp_is_en(intr_handle))
5725                 return;
5726
5727         if (rte_intr_allow_others(intr_handle))
5728                 vec = base = IXGBE_RX_VEC_START;
5729
5730         /* setup GPIE for MSI-x mode */
5731         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5732         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5733                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5734         /* auto clearing and auto setting corresponding bits in EIMS
5735          * when MSI-X interrupt is triggered
5736          */
5737         if (hw->mac.type == ixgbe_mac_82598EB) {
5738                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5739         } else {
5740                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5741                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5742         }
5743         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5744
5745         /* Populate the IVAR table and set the ITR values to the
5746          * corresponding register.
5747          */
5748         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5749              queue_id++) {
5750                 /* by default, 1:1 mapping */
5751                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5752                 intr_handle->intr_vec[queue_id] = vec;
5753                 if (vec < base + intr_handle->nb_efd - 1)
5754                         vec++;
5755         }
5756
5757         switch (hw->mac.type) {
5758         case ixgbe_mac_82598EB:
5759                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5760                                    IXGBE_MISC_VEC_ID);
5761                 break;
5762         case ixgbe_mac_82599EB:
5763         case ixgbe_mac_X540:
5764                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5765                 break;
5766         default:
5767                 break;
5768         }
5769         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5770                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5771
5772         /* set up to autoclear timer, and the vectors */
5773         mask = IXGBE_EIMS_ENABLE_MASK;
5774         mask &= ~(IXGBE_EIMS_OTHER |
5775                   IXGBE_EIMS_MAILBOX |
5776                   IXGBE_EIMS_LSC);
5777
5778         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5779 }
5780
5781 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5782         uint16_t queue_idx, uint16_t tx_rate)
5783 {
5784         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5785         uint32_t rf_dec, rf_int;
5786         uint32_t bcnrc_val;
5787         uint16_t link_speed = dev->data->dev_link.link_speed;
5788
5789         if (queue_idx >= hw->mac.max_tx_queues)
5790                 return -EINVAL;
5791
5792         if (tx_rate != 0) {
5793                 /* Calculate the rate factor values to set */
5794                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5795                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5796                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5797
5798                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5799                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5800                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5801                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5802         } else {
5803                 bcnrc_val = 0;
5804         }
5805
5806         /*
5807          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5808          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5809          * set as 0x4.
5810          */
5811         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5812                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5813                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5814                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5815                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5816         else
5817                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5818                         IXGBE_MMW_SIZE_DEFAULT);
5819
5820         /* Set RTTBCNRC of queue X */
5821         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5822         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5823         IXGBE_WRITE_FLUSH(hw);
5824
5825         return 0;
5826 }
5827
5828 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
5829         uint16_t tx_rate, uint64_t q_msk)
5830 {
5831         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5832         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5833         struct ixgbe_vf_info *vfinfo =
5834                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5835         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5836         uint32_t queue_stride =
5837                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5838         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
5839         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
5840         uint16_t total_rate = 0;
5841
5842         if (queue_end >= hw->mac.max_tx_queues)
5843                 return -EINVAL;
5844
5845         if (vfinfo != NULL) {
5846                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5847                         if (vf_idx == vf)
5848                                 continue;
5849                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5850                                 idx++)
5851                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5852                 }
5853         } else
5854                 return -EINVAL;
5855
5856         /* Store tx_rate for this vf. */
5857         for (idx = 0; idx < nb_q_per_pool; idx++) {
5858                 if (((uint64_t)0x1 << idx) & q_msk) {
5859                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5860                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5861                         total_rate += tx_rate;
5862                 }
5863         }
5864
5865         if (total_rate > dev->data->dev_link.link_speed) {
5866                 /*
5867                  * Reset stored TX rate of the VF if it causes exceed
5868                  * link speed.
5869                  */
5870                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5871                 return -EINVAL;
5872         }
5873
5874         /* Set RTTBCNRC of each queue/pool for vf X  */
5875         for (; queue_idx <= queue_end; queue_idx++) {
5876                 if (0x1 & q_msk)
5877                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5878                 q_msk = q_msk >> 1;
5879         }
5880
5881         return 0;
5882 }
5883
5884 static void
5885 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5886                      __attribute__((unused)) uint32_t index,
5887                      __attribute__((unused)) uint32_t pool)
5888 {
5889         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5890         int diag;
5891
5892         /*
5893          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5894          * operation. Trap this case to avoid exhausting the [very limited]
5895          * set of PF resources used to store VF MAC addresses.
5896          */
5897         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5898                 return;
5899         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5900         if (diag == 0)
5901                 return;
5902         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5903 }
5904
5905 static void
5906 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5907 {
5908         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5909         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5910         struct ether_addr *mac_addr;
5911         uint32_t i;
5912         int diag;
5913
5914         /*
5915          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5916          * not support the deletion of a given MAC address.
5917          * Instead, it imposes to delete all MAC addresses, then to add again
5918          * all MAC addresses with the exception of the one to be deleted.
5919          */
5920         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5921
5922         /*
5923          * Add again all MAC addresses, with the exception of the deleted one
5924          * and of the permanent MAC address.
5925          */
5926         for (i = 0, mac_addr = dev->data->mac_addrs;
5927              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5928                 /* Skip the deleted MAC address */
5929                 if (i == index)
5930                         continue;
5931                 /* Skip NULL MAC addresses */
5932                 if (is_zero_ether_addr(mac_addr))
5933                         continue;
5934                 /* Skip the permanent MAC address */
5935                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5936                         continue;
5937                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5938                 if (diag != 0)
5939                         PMD_DRV_LOG(ERR,
5940                                     "Adding again MAC address "
5941                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5942                                     "diag=%d",
5943                                     mac_addr->addr_bytes[0],
5944                                     mac_addr->addr_bytes[1],
5945                                     mac_addr->addr_bytes[2],
5946                                     mac_addr->addr_bytes[3],
5947                                     mac_addr->addr_bytes[4],
5948                                     mac_addr->addr_bytes[5],
5949                                     diag);
5950         }
5951 }
5952
5953 static void
5954 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5955 {
5956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5957
5958         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5959 }
5960
5961 #define MAC_TYPE_FILTER_SUP(type)    do {\
5962         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5963                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5964                 (type) != ixgbe_mac_X550EM_a)\
5965                 return -ENOTSUP;\
5966 } while (0)
5967
5968 static int
5969 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5970                         struct rte_eth_syn_filter *filter,
5971                         bool add)
5972 {
5973         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5974         uint32_t synqf;
5975
5976         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5977                 return -EINVAL;
5978
5979         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5980
5981         if (add) {
5982                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
5983                         return -EINVAL;
5984                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5985                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5986
5987                 if (filter->hig_pri)
5988                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5989                 else
5990                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5991         } else {
5992                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
5993                         return -ENOENT;
5994                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5995         }
5996         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5997         IXGBE_WRITE_FLUSH(hw);
5998         return 0;
5999 }
6000
6001 static int
6002 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6003                         struct rte_eth_syn_filter *filter)
6004 {
6005         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6006         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6007
6008         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6009                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6010                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6011                 return 0;
6012         }
6013         return -ENOENT;
6014 }
6015
6016 static int
6017 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6018                         enum rte_filter_op filter_op,
6019                         void *arg)
6020 {
6021         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6022         int ret;
6023
6024         MAC_TYPE_FILTER_SUP(hw->mac.type);
6025
6026         if (filter_op == RTE_ETH_FILTER_NOP)
6027                 return 0;
6028
6029         if (arg == NULL) {
6030                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6031                             filter_op);
6032                 return -EINVAL;
6033         }
6034
6035         switch (filter_op) {
6036         case RTE_ETH_FILTER_ADD:
6037                 ret = ixgbe_syn_filter_set(dev,
6038                                 (struct rte_eth_syn_filter *)arg,
6039                                 TRUE);
6040                 break;
6041         case RTE_ETH_FILTER_DELETE:
6042                 ret = ixgbe_syn_filter_set(dev,
6043                                 (struct rte_eth_syn_filter *)arg,
6044                                 FALSE);
6045                 break;
6046         case RTE_ETH_FILTER_GET:
6047                 ret = ixgbe_syn_filter_get(dev,
6048                                 (struct rte_eth_syn_filter *)arg);
6049                 break;
6050         default:
6051                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6052                 ret = -EINVAL;
6053                 break;
6054         }
6055
6056         return ret;
6057 }
6058
6059
6060 static inline enum ixgbe_5tuple_protocol
6061 convert_protocol_type(uint8_t protocol_value)
6062 {
6063         if (protocol_value == IPPROTO_TCP)
6064                 return IXGBE_FILTER_PROTOCOL_TCP;
6065         else if (protocol_value == IPPROTO_UDP)
6066                 return IXGBE_FILTER_PROTOCOL_UDP;
6067         else if (protocol_value == IPPROTO_SCTP)
6068                 return IXGBE_FILTER_PROTOCOL_SCTP;
6069         else
6070                 return IXGBE_FILTER_PROTOCOL_NONE;
6071 }
6072
6073 /*
6074  * add a 5tuple filter
6075  *
6076  * @param
6077  * dev: Pointer to struct rte_eth_dev.
6078  * index: the index the filter allocates.
6079  * filter: ponter to the filter that will be added.
6080  * rx_queue: the queue id the filter assigned to.
6081  *
6082  * @return
6083  *    - On success, zero.
6084  *    - On failure, a negative value.
6085  */
6086 static int
6087 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6088                         struct ixgbe_5tuple_filter *filter)
6089 {
6090         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6091         struct ixgbe_filter_info *filter_info =
6092                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6093         int i, idx, shift;
6094         uint32_t ftqf, sdpqf;
6095         uint32_t l34timir = 0;
6096         uint8_t mask = 0xff;
6097
6098         /*
6099          * look for an unused 5tuple filter index,
6100          * and insert the filter to list.
6101          */
6102         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6103                 idx = i / (sizeof(uint32_t) * NBBY);
6104                 shift = i % (sizeof(uint32_t) * NBBY);
6105                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6106                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6107                         filter->index = i;
6108                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6109                                           filter,
6110                                           entries);
6111                         break;
6112                 }
6113         }
6114         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6115                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6116                 return -ENOSYS;
6117         }
6118
6119         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6120                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6121         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6122
6123         ftqf = (uint32_t)(filter->filter_info.proto &
6124                 IXGBE_FTQF_PROTOCOL_MASK);
6125         ftqf |= (uint32_t)((filter->filter_info.priority &
6126                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6127         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6128                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6129         if (filter->filter_info.dst_ip_mask == 0)
6130                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6131         if (filter->filter_info.src_port_mask == 0)
6132                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6133         if (filter->filter_info.dst_port_mask == 0)
6134                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6135         if (filter->filter_info.proto_mask == 0)
6136                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6137         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6138         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6139         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6140
6141         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6142         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6143         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6144         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6145
6146         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6147         l34timir |= (uint32_t)(filter->queue <<
6148                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6149         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6150         return 0;
6151 }
6152
6153 /*
6154  * remove a 5tuple filter
6155  *
6156  * @param
6157  * dev: Pointer to struct rte_eth_dev.
6158  * filter: the pointer of the filter will be removed.
6159  */
6160 static void
6161 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6162                         struct ixgbe_5tuple_filter *filter)
6163 {
6164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6165         struct ixgbe_filter_info *filter_info =
6166                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6167         uint16_t index = filter->index;
6168
6169         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6170                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6171         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6172         rte_free(filter);
6173
6174         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6175         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6176         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6177         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6178         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6179 }
6180
6181 static int
6182 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6183 {
6184         struct ixgbe_hw *hw;
6185         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6186
6187         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6188
6189         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6190                 return -EINVAL;
6191
6192         /* refuse mtu that requires the support of scattered packets when this
6193          * feature has not been enabled before.
6194          */
6195         if (!dev->data->scattered_rx &&
6196             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6197              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6198                 return -EINVAL;
6199
6200         /*
6201          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6202          * request of the version 2.0 of the mailbox API.
6203          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6204          * of the mailbox API.
6205          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6206          * prior to 3.11.33 which contains the following change:
6207          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6208          */
6209         ixgbevf_rlpml_set_vf(hw, max_frame);
6210
6211         /* update max frame size */
6212         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6213         return 0;
6214 }
6215
6216 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6217         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6218                 return -ENOTSUP;\
6219 } while (0)
6220
6221 static inline struct ixgbe_5tuple_filter *
6222 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6223                         struct ixgbe_5tuple_filter_info *key)
6224 {
6225         struct ixgbe_5tuple_filter *it;
6226
6227         TAILQ_FOREACH(it, filter_list, entries) {
6228                 if (memcmp(key, &it->filter_info,
6229                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6230                         return it;
6231                 }
6232         }
6233         return NULL;
6234 }
6235
6236 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6237 static inline int
6238 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6239                         struct ixgbe_5tuple_filter_info *filter_info)
6240 {
6241         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6242                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6243                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6244                 return -EINVAL;
6245
6246         switch (filter->dst_ip_mask) {
6247         case UINT32_MAX:
6248                 filter_info->dst_ip_mask = 0;
6249                 filter_info->dst_ip = filter->dst_ip;
6250                 break;
6251         case 0:
6252                 filter_info->dst_ip_mask = 1;
6253                 break;
6254         default:
6255                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6256                 return -EINVAL;
6257         }
6258
6259         switch (filter->src_ip_mask) {
6260         case UINT32_MAX:
6261                 filter_info->src_ip_mask = 0;
6262                 filter_info->src_ip = filter->src_ip;
6263                 break;
6264         case 0:
6265                 filter_info->src_ip_mask = 1;
6266                 break;
6267         default:
6268                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6269                 return -EINVAL;
6270         }
6271
6272         switch (filter->dst_port_mask) {
6273         case UINT16_MAX:
6274                 filter_info->dst_port_mask = 0;
6275                 filter_info->dst_port = filter->dst_port;
6276                 break;
6277         case 0:
6278                 filter_info->dst_port_mask = 1;
6279                 break;
6280         default:
6281                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6282                 return -EINVAL;
6283         }
6284
6285         switch (filter->src_port_mask) {
6286         case UINT16_MAX:
6287                 filter_info->src_port_mask = 0;
6288                 filter_info->src_port = filter->src_port;
6289                 break;
6290         case 0:
6291                 filter_info->src_port_mask = 1;
6292                 break;
6293         default:
6294                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6295                 return -EINVAL;
6296         }
6297
6298         switch (filter->proto_mask) {
6299         case UINT8_MAX:
6300                 filter_info->proto_mask = 0;
6301                 filter_info->proto =
6302                         convert_protocol_type(filter->proto);
6303                 break;
6304         case 0:
6305                 filter_info->proto_mask = 1;
6306                 break;
6307         default:
6308                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6309                 return -EINVAL;
6310         }
6311
6312         filter_info->priority = (uint8_t)filter->priority;
6313         return 0;
6314 }
6315
6316 /*
6317  * add or delete a ntuple filter
6318  *
6319  * @param
6320  * dev: Pointer to struct rte_eth_dev.
6321  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6322  * add: if true, add filter, if false, remove filter
6323  *
6324  * @return
6325  *    - On success, zero.
6326  *    - On failure, a negative value.
6327  */
6328 static int
6329 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6330                         struct rte_eth_ntuple_filter *ntuple_filter,
6331                         bool add)
6332 {
6333         struct ixgbe_filter_info *filter_info =
6334                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6335         struct ixgbe_5tuple_filter_info filter_5tuple;
6336         struct ixgbe_5tuple_filter *filter;
6337         int ret;
6338
6339         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6340                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6341                 return -EINVAL;
6342         }
6343
6344         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6345         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6346         if (ret < 0)
6347                 return ret;
6348
6349         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6350                                          &filter_5tuple);
6351         if (filter != NULL && add) {
6352                 PMD_DRV_LOG(ERR, "filter exists.");
6353                 return -EEXIST;
6354         }
6355         if (filter == NULL && !add) {
6356                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6357                 return -ENOENT;
6358         }
6359
6360         if (add) {
6361                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6362                                 sizeof(struct ixgbe_5tuple_filter), 0);
6363                 if (filter == NULL)
6364                         return -ENOMEM;
6365                 (void)rte_memcpy(&filter->filter_info,
6366                                  &filter_5tuple,
6367                                  sizeof(struct ixgbe_5tuple_filter_info));
6368                 filter->queue = ntuple_filter->queue;
6369                 ret = ixgbe_add_5tuple_filter(dev, filter);
6370                 if (ret < 0) {
6371                         rte_free(filter);
6372                         return ret;
6373                 }
6374         } else
6375                 ixgbe_remove_5tuple_filter(dev, filter);
6376
6377         return 0;
6378 }
6379
6380 /*
6381  * get a ntuple filter
6382  *
6383  * @param
6384  * dev: Pointer to struct rte_eth_dev.
6385  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6386  *
6387  * @return
6388  *    - On success, zero.
6389  *    - On failure, a negative value.
6390  */
6391 static int
6392 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6393                         struct rte_eth_ntuple_filter *ntuple_filter)
6394 {
6395         struct ixgbe_filter_info *filter_info =
6396                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6397         struct ixgbe_5tuple_filter_info filter_5tuple;
6398         struct ixgbe_5tuple_filter *filter;
6399         int ret;
6400
6401         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6402                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6403                 return -EINVAL;
6404         }
6405
6406         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6407         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6408         if (ret < 0)
6409                 return ret;
6410
6411         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6412                                          &filter_5tuple);
6413         if (filter == NULL) {
6414                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6415                 return -ENOENT;
6416         }
6417         ntuple_filter->queue = filter->queue;
6418         return 0;
6419 }
6420
6421 /*
6422  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6423  * @dev: pointer to rte_eth_dev structure
6424  * @filter_op:operation will be taken.
6425  * @arg: a pointer to specific structure corresponding to the filter_op
6426  *
6427  * @return
6428  *    - On success, zero.
6429  *    - On failure, a negative value.
6430  */
6431 static int
6432 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6433                                 enum rte_filter_op filter_op,
6434                                 void *arg)
6435 {
6436         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6437         int ret;
6438
6439         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6440
6441         if (filter_op == RTE_ETH_FILTER_NOP)
6442                 return 0;
6443
6444         if (arg == NULL) {
6445                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6446                             filter_op);
6447                 return -EINVAL;
6448         }
6449
6450         switch (filter_op) {
6451         case RTE_ETH_FILTER_ADD:
6452                 ret = ixgbe_add_del_ntuple_filter(dev,
6453                         (struct rte_eth_ntuple_filter *)arg,
6454                         TRUE);
6455                 break;
6456         case RTE_ETH_FILTER_DELETE:
6457                 ret = ixgbe_add_del_ntuple_filter(dev,
6458                         (struct rte_eth_ntuple_filter *)arg,
6459                         FALSE);
6460                 break;
6461         case RTE_ETH_FILTER_GET:
6462                 ret = ixgbe_get_ntuple_filter(dev,
6463                         (struct rte_eth_ntuple_filter *)arg);
6464                 break;
6465         default:
6466                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6467                 ret = -EINVAL;
6468                 break;
6469         }
6470         return ret;
6471 }
6472
6473 static inline int
6474 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
6475                         uint16_t ethertype)
6476 {
6477         int i;
6478
6479         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6480                 if (filter_info->ethertype_filters[i] == ethertype &&
6481                     (filter_info->ethertype_mask & (1 << i)))
6482                         return i;
6483         }
6484         return -1;
6485 }
6486
6487 static inline int
6488 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
6489                         uint16_t ethertype)
6490 {
6491         int i;
6492
6493         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
6494                 if (!(filter_info->ethertype_mask & (1 << i))) {
6495                         filter_info->ethertype_mask |= 1 << i;
6496                         filter_info->ethertype_filters[i] = ethertype;
6497                         return i;
6498                 }
6499         }
6500         return -1;
6501 }
6502
6503 static inline int
6504 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
6505                         uint8_t idx)
6506 {
6507         if (idx >= IXGBE_MAX_ETQF_FILTERS)
6508                 return -1;
6509         filter_info->ethertype_mask &= ~(1 << idx);
6510         filter_info->ethertype_filters[idx] = 0;
6511         return idx;
6512 }
6513
6514 static int
6515 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6516                         struct rte_eth_ethertype_filter *filter,
6517                         bool add)
6518 {
6519         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6520         struct ixgbe_filter_info *filter_info =
6521                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6522         uint32_t etqf = 0;
6523         uint32_t etqs = 0;
6524         int ret;
6525
6526         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6527                 return -EINVAL;
6528
6529         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6530                 filter->ether_type == ETHER_TYPE_IPv6) {
6531                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6532                         " ethertype filter.", filter->ether_type);
6533                 return -EINVAL;
6534         }
6535
6536         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6537                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6538                 return -EINVAL;
6539         }
6540         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6541                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6542                 return -EINVAL;
6543         }
6544
6545         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6546         if (ret >= 0 && add) {
6547                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6548                             filter->ether_type);
6549                 return -EEXIST;
6550         }
6551         if (ret < 0 && !add) {
6552                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6553                             filter->ether_type);
6554                 return -ENOENT;
6555         }
6556
6557         if (add) {
6558                 ret = ixgbe_ethertype_filter_insert(filter_info,
6559                         filter->ether_type);
6560                 if (ret < 0) {
6561                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6562                         return -ENOSYS;
6563                 }
6564                 etqf = IXGBE_ETQF_FILTER_EN;
6565                 etqf |= (uint32_t)filter->ether_type;
6566                 etqs |= (uint32_t)((filter->queue <<
6567                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6568                                     IXGBE_ETQS_RX_QUEUE);
6569                 etqs |= IXGBE_ETQS_QUEUE_EN;
6570         } else {
6571                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6572                 if (ret < 0)
6573                         return -ENOSYS;
6574         }
6575         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6576         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6577         IXGBE_WRITE_FLUSH(hw);
6578
6579         return 0;
6580 }
6581
6582 static int
6583 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6584                         struct rte_eth_ethertype_filter *filter)
6585 {
6586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6587         struct ixgbe_filter_info *filter_info =
6588                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6589         uint32_t etqf, etqs;
6590         int ret;
6591
6592         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6593         if (ret < 0) {
6594                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6595                             filter->ether_type);
6596                 return -ENOENT;
6597         }
6598
6599         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6600         if (etqf & IXGBE_ETQF_FILTER_EN) {
6601                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6602                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6603                 filter->flags = 0;
6604                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6605                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6606                 return 0;
6607         }
6608         return -ENOENT;
6609 }
6610
6611 /*
6612  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6613  * @dev: pointer to rte_eth_dev structure
6614  * @filter_op:operation will be taken.
6615  * @arg: a pointer to specific structure corresponding to the filter_op
6616  */
6617 static int
6618 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6619                                 enum rte_filter_op filter_op,
6620                                 void *arg)
6621 {
6622         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6623         int ret;
6624
6625         MAC_TYPE_FILTER_SUP(hw->mac.type);
6626
6627         if (filter_op == RTE_ETH_FILTER_NOP)
6628                 return 0;
6629
6630         if (arg == NULL) {
6631                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6632                             filter_op);
6633                 return -EINVAL;
6634         }
6635
6636         switch (filter_op) {
6637         case RTE_ETH_FILTER_ADD:
6638                 ret = ixgbe_add_del_ethertype_filter(dev,
6639                         (struct rte_eth_ethertype_filter *)arg,
6640                         TRUE);
6641                 break;
6642         case RTE_ETH_FILTER_DELETE:
6643                 ret = ixgbe_add_del_ethertype_filter(dev,
6644                         (struct rte_eth_ethertype_filter *)arg,
6645                         FALSE);
6646                 break;
6647         case RTE_ETH_FILTER_GET:
6648                 ret = ixgbe_get_ethertype_filter(dev,
6649                         (struct rte_eth_ethertype_filter *)arg);
6650                 break;
6651         default:
6652                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6653                 ret = -EINVAL;
6654                 break;
6655         }
6656         return ret;
6657 }
6658
6659 static int
6660 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6661                      enum rte_filter_type filter_type,
6662                      enum rte_filter_op filter_op,
6663                      void *arg)
6664 {
6665         int ret = -EINVAL;
6666
6667         switch (filter_type) {
6668         case RTE_ETH_FILTER_NTUPLE:
6669                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6670                 break;
6671         case RTE_ETH_FILTER_ETHERTYPE:
6672                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6673                 break;
6674         case RTE_ETH_FILTER_SYN:
6675                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6676                 break;
6677         case RTE_ETH_FILTER_FDIR:
6678                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6679                 break;
6680         case RTE_ETH_FILTER_L2_TUNNEL:
6681                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6682                 break;
6683         default:
6684                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6685                                                         filter_type);
6686                 break;
6687         }
6688
6689         return ret;
6690 }
6691
6692 static u8 *
6693 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6694                         u8 **mc_addr_ptr, u32 *vmdq)
6695 {
6696         u8 *mc_addr;
6697
6698         *vmdq = 0;
6699         mc_addr = *mc_addr_ptr;
6700         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6701         return mc_addr;
6702 }
6703
6704 static int
6705 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6706                           struct ether_addr *mc_addr_set,
6707                           uint32_t nb_mc_addr)
6708 {
6709         struct ixgbe_hw *hw;
6710         u8 *mc_addr_list;
6711
6712         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6713         mc_addr_list = (u8 *)mc_addr_set;
6714         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6715                                          ixgbe_dev_addr_list_itr, TRUE);
6716 }
6717
6718 static uint64_t
6719 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6720 {
6721         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6722         uint64_t systime_cycles;
6723
6724         switch (hw->mac.type) {
6725         case ixgbe_mac_X550:
6726         case ixgbe_mac_X550EM_x:
6727         case ixgbe_mac_X550EM_a:
6728                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6729                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6730                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6731                                 * NSEC_PER_SEC;
6732                 break;
6733         default:
6734                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6735                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6736                                 << 32;
6737         }
6738
6739         return systime_cycles;
6740 }
6741
6742 static uint64_t
6743 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6744 {
6745         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6746         uint64_t rx_tstamp_cycles;
6747
6748         switch (hw->mac.type) {
6749         case ixgbe_mac_X550:
6750         case ixgbe_mac_X550EM_x:
6751         case ixgbe_mac_X550EM_a:
6752                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6753                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6754                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6755                                 * NSEC_PER_SEC;
6756                 break;
6757         default:
6758                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6759                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6760                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6761                                 << 32;
6762         }
6763
6764         return rx_tstamp_cycles;
6765 }
6766
6767 static uint64_t
6768 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6769 {
6770         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6771         uint64_t tx_tstamp_cycles;
6772
6773         switch (hw->mac.type) {
6774         case ixgbe_mac_X550:
6775         case ixgbe_mac_X550EM_x:
6776         case ixgbe_mac_X550EM_a:
6777                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6778                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6779                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6780                                 * NSEC_PER_SEC;
6781                 break;
6782         default:
6783                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6784                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6785                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6786                                 << 32;
6787         }
6788
6789         return tx_tstamp_cycles;
6790 }
6791
6792 static void
6793 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6794 {
6795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6796         struct ixgbe_adapter *adapter =
6797                 (struct ixgbe_adapter *)dev->data->dev_private;
6798         struct rte_eth_link link;
6799         uint32_t incval = 0;
6800         uint32_t shift = 0;
6801
6802         /* Get current link speed. */
6803         memset(&link, 0, sizeof(link));
6804         ixgbe_dev_link_update(dev, 1);
6805         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6806
6807         switch (link.link_speed) {
6808         case ETH_SPEED_NUM_100M:
6809                 incval = IXGBE_INCVAL_100;
6810                 shift = IXGBE_INCVAL_SHIFT_100;
6811                 break;
6812         case ETH_SPEED_NUM_1G:
6813                 incval = IXGBE_INCVAL_1GB;
6814                 shift = IXGBE_INCVAL_SHIFT_1GB;
6815                 break;
6816         case ETH_SPEED_NUM_10G:
6817         default:
6818                 incval = IXGBE_INCVAL_10GB;
6819                 shift = IXGBE_INCVAL_SHIFT_10GB;
6820                 break;
6821         }
6822
6823         switch (hw->mac.type) {
6824         case ixgbe_mac_X550:
6825         case ixgbe_mac_X550EM_x:
6826         case ixgbe_mac_X550EM_a:
6827                 /* Independent of link speed. */
6828                 incval = 1;
6829                 /* Cycles read will be interpreted as ns. */
6830                 shift = 0;
6831                 /* Fall-through */
6832         case ixgbe_mac_X540:
6833                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6834                 break;
6835         case ixgbe_mac_82599EB:
6836                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6837                 shift -= IXGBE_INCVAL_SHIFT_82599;
6838                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6839                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6840                 break;
6841         default:
6842                 /* Not supported. */
6843                 return;
6844         }
6845
6846         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6847         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6848         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6849
6850         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6851         adapter->systime_tc.cc_shift = shift;
6852         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6853
6854         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6855         adapter->rx_tstamp_tc.cc_shift = shift;
6856         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6857
6858         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6859         adapter->tx_tstamp_tc.cc_shift = shift;
6860         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6861 }
6862
6863 static int
6864 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6865 {
6866         struct ixgbe_adapter *adapter =
6867                         (struct ixgbe_adapter *)dev->data->dev_private;
6868
6869         adapter->systime_tc.nsec += delta;
6870         adapter->rx_tstamp_tc.nsec += delta;
6871         adapter->tx_tstamp_tc.nsec += delta;
6872
6873         return 0;
6874 }
6875
6876 static int
6877 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6878 {
6879         uint64_t ns;
6880         struct ixgbe_adapter *adapter =
6881                         (struct ixgbe_adapter *)dev->data->dev_private;
6882
6883         ns = rte_timespec_to_ns(ts);
6884         /* Set the timecounters to a new value. */
6885         adapter->systime_tc.nsec = ns;
6886         adapter->rx_tstamp_tc.nsec = ns;
6887         adapter->tx_tstamp_tc.nsec = ns;
6888
6889         return 0;
6890 }
6891
6892 static int
6893 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6894 {
6895         uint64_t ns, systime_cycles;
6896         struct ixgbe_adapter *adapter =
6897                         (struct ixgbe_adapter *)dev->data->dev_private;
6898
6899         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6900         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6901         *ts = rte_ns_to_timespec(ns);
6902
6903         return 0;
6904 }
6905
6906 static int
6907 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6908 {
6909         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6910         uint32_t tsync_ctl;
6911         uint32_t tsauxc;
6912
6913         /* Stop the timesync system time. */
6914         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6915         /* Reset the timesync system time value. */
6916         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6917         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6918
6919         /* Enable system time for platforms where it isn't on by default. */
6920         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6921         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6922         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6923
6924         ixgbe_start_timecounters(dev);
6925
6926         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6927         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6928                         (ETHER_TYPE_1588 |
6929                          IXGBE_ETQF_FILTER_EN |
6930                          IXGBE_ETQF_1588));
6931
6932         /* Enable timestamping of received PTP packets. */
6933         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6934         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6935         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6936
6937         /* Enable timestamping of transmitted PTP packets. */
6938         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6939         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6940         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6941
6942         IXGBE_WRITE_FLUSH(hw);
6943
6944         return 0;
6945 }
6946
6947 static int
6948 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6949 {
6950         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6951         uint32_t tsync_ctl;
6952
6953         /* Disable timestamping of transmitted PTP packets. */
6954         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6955         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6956         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6957
6958         /* Disable timestamping of received PTP packets. */
6959         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6960         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6961         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6962
6963         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6964         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6965
6966         /* Stop incrementating the System Time registers. */
6967         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6968
6969         return 0;
6970 }
6971
6972 static int
6973 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6974                                  struct timespec *timestamp,
6975                                  uint32_t flags __rte_unused)
6976 {
6977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6978         struct ixgbe_adapter *adapter =
6979                 (struct ixgbe_adapter *)dev->data->dev_private;
6980         uint32_t tsync_rxctl;
6981         uint64_t rx_tstamp_cycles;
6982         uint64_t ns;
6983
6984         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6985         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6986                 return -EINVAL;
6987
6988         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6989         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6990         *timestamp = rte_ns_to_timespec(ns);
6991
6992         return  0;
6993 }
6994
6995 static int
6996 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6997                                  struct timespec *timestamp)
6998 {
6999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7000         struct ixgbe_adapter *adapter =
7001                 (struct ixgbe_adapter *)dev->data->dev_private;
7002         uint32_t tsync_txctl;
7003         uint64_t tx_tstamp_cycles;
7004         uint64_t ns;
7005
7006         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7007         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7008                 return -EINVAL;
7009
7010         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7011         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7012         *timestamp = rte_ns_to_timespec(ns);
7013
7014         return 0;
7015 }
7016
7017 static int
7018 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7019 {
7020         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021         int count = 0;
7022         int g_ind = 0;
7023         const struct reg_info *reg_group;
7024         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7025                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7026
7027         while ((reg_group = reg_set[g_ind++]))
7028                 count += ixgbe_regs_group_count(reg_group);
7029
7030         return count;
7031 }
7032
7033 static int
7034 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7035 {
7036         int count = 0;
7037         int g_ind = 0;
7038         const struct reg_info *reg_group;
7039
7040         while ((reg_group = ixgbevf_regs[g_ind++]))
7041                 count += ixgbe_regs_group_count(reg_group);
7042
7043         return count;
7044 }
7045
7046 static int
7047 ixgbe_get_regs(struct rte_eth_dev *dev,
7048               struct rte_dev_reg_info *regs)
7049 {
7050         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051         uint32_t *data = regs->data;
7052         int g_ind = 0;
7053         int count = 0;
7054         const struct reg_info *reg_group;
7055         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7056                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7057
7058         if (data == NULL) {
7059                 regs->length = ixgbe_get_reg_length(dev);
7060                 regs->width = sizeof(uint32_t);
7061                 return 0;
7062         }
7063
7064         /* Support only full register dump */
7065         if ((regs->length == 0) ||
7066             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7067                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7068                         hw->device_id;
7069                 while ((reg_group = reg_set[g_ind++]))
7070                         count += ixgbe_read_regs_group(dev, &data[count],
7071                                 reg_group);
7072                 return 0;
7073         }
7074
7075         return -ENOTSUP;
7076 }
7077
7078 static int
7079 ixgbevf_get_regs(struct rte_eth_dev *dev,
7080                 struct rte_dev_reg_info *regs)
7081 {
7082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7083         uint32_t *data = regs->data;
7084         int g_ind = 0;
7085         int count = 0;
7086         const struct reg_info *reg_group;
7087
7088         if (data == NULL) {
7089                 regs->length = ixgbevf_get_reg_length(dev);
7090                 regs->width = sizeof(uint32_t);
7091                 return 0;
7092         }
7093
7094         /* Support only full register dump */
7095         if ((regs->length == 0) ||
7096             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7097                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7098                         hw->device_id;
7099                 while ((reg_group = ixgbevf_regs[g_ind++]))
7100                         count += ixgbe_read_regs_group(dev, &data[count],
7101                                                       reg_group);
7102                 return 0;
7103         }
7104
7105         return -ENOTSUP;
7106 }
7107
7108 static int
7109 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7110 {
7111         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7112
7113         /* Return unit is byte count */
7114         return hw->eeprom.word_size * 2;
7115 }
7116
7117 static int
7118 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7119                 struct rte_dev_eeprom_info *in_eeprom)
7120 {
7121         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7122         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7123         uint16_t *data = in_eeprom->data;
7124         int first, length;
7125
7126         first = in_eeprom->offset >> 1;
7127         length = in_eeprom->length >> 1;
7128         if ((first > hw->eeprom.word_size) ||
7129             ((first + length) > hw->eeprom.word_size))
7130                 return -EINVAL;
7131
7132         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7133
7134         return eeprom->ops.read_buffer(hw, first, length, data);
7135 }
7136
7137 static int
7138 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7139                 struct rte_dev_eeprom_info *in_eeprom)
7140 {
7141         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7142         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7143         uint16_t *data = in_eeprom->data;
7144         int first, length;
7145
7146         first = in_eeprom->offset >> 1;
7147         length = in_eeprom->length >> 1;
7148         if ((first > hw->eeprom.word_size) ||
7149             ((first + length) > hw->eeprom.word_size))
7150                 return -EINVAL;
7151
7152         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7153
7154         return eeprom->ops.write_buffer(hw,  first, length, data);
7155 }
7156
7157 uint16_t
7158 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7159         switch (mac_type) {
7160         case ixgbe_mac_X550:
7161         case ixgbe_mac_X550EM_x:
7162         case ixgbe_mac_X550EM_a:
7163                 return ETH_RSS_RETA_SIZE_512;
7164         case ixgbe_mac_X550_vf:
7165         case ixgbe_mac_X550EM_x_vf:
7166         case ixgbe_mac_X550EM_a_vf:
7167                 return ETH_RSS_RETA_SIZE_64;
7168         default:
7169                 return ETH_RSS_RETA_SIZE_128;
7170         }
7171 }
7172
7173 uint32_t
7174 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7175         switch (mac_type) {
7176         case ixgbe_mac_X550:
7177         case ixgbe_mac_X550EM_x:
7178         case ixgbe_mac_X550EM_a:
7179                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7180                         return IXGBE_RETA(reta_idx >> 2);
7181                 else
7182                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7183         case ixgbe_mac_X550_vf:
7184         case ixgbe_mac_X550EM_x_vf:
7185         case ixgbe_mac_X550EM_a_vf:
7186                 return IXGBE_VFRETA(reta_idx >> 2);
7187         default:
7188                 return IXGBE_RETA(reta_idx >> 2);
7189         }
7190 }
7191
7192 uint32_t
7193 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7194         switch (mac_type) {
7195         case ixgbe_mac_X550_vf:
7196         case ixgbe_mac_X550EM_x_vf:
7197         case ixgbe_mac_X550EM_a_vf:
7198                 return IXGBE_VFMRQC;
7199         default:
7200                 return IXGBE_MRQC;
7201         }
7202 }
7203
7204 uint32_t
7205 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7206         switch (mac_type) {
7207         case ixgbe_mac_X550_vf:
7208         case ixgbe_mac_X550EM_x_vf:
7209         case ixgbe_mac_X550EM_a_vf:
7210                 return IXGBE_VFRSSRK(i);
7211         default:
7212                 return IXGBE_RSSRK(i);
7213         }
7214 }
7215
7216 bool
7217 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7218         switch (mac_type) {
7219         case ixgbe_mac_82599_vf:
7220         case ixgbe_mac_X540_vf:
7221                 return 0;
7222         default:
7223                 return 1;
7224         }
7225 }
7226
7227 static int
7228 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7229                         struct rte_eth_dcb_info *dcb_info)
7230 {
7231         struct ixgbe_dcb_config *dcb_config =
7232                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7233         struct ixgbe_dcb_tc_config *tc;
7234         uint8_t i, j;
7235
7236         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7237                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7238         else
7239                 dcb_info->nb_tcs = 1;
7240
7241         if (dcb_config->vt_mode) { /* vt is enabled*/
7242                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7243                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7244                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7245                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7246                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7247                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7248                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7249                                                 i * dcb_info->nb_tcs + j;
7250                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7251                                 dcb_info->tc_queue.tc_txq[i][j].base =
7252                                                 i * dcb_info->nb_tcs + j;
7253                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7254                         }
7255                 }
7256         } else { /* vt is disabled*/
7257                 struct rte_eth_dcb_rx_conf *rx_conf =
7258                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7259                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7260                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7261                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7262                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7263                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7264                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7265                         }
7266                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7267                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7268                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7269                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7270                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7271                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7272                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7273                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7274                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7275                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7276                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7277                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7278                         }
7279                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7280                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7281                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7282                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7283                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7284                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7285                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7286                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7287                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7288                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7289                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7290                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7291                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7292                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7293                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7294                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7295                 }
7296         }
7297         for (i = 0; i < dcb_info->nb_tcs; i++) {
7298                 tc = &dcb_config->tc_config[i];
7299                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7300         }
7301         return 0;
7302 }
7303
7304 /* Update e-tag ether type */
7305 static int
7306 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7307                             uint16_t ether_type)
7308 {
7309         uint32_t etag_etype;
7310
7311         if (hw->mac.type != ixgbe_mac_X550 &&
7312             hw->mac.type != ixgbe_mac_X550EM_x &&
7313             hw->mac.type != ixgbe_mac_X550EM_a) {
7314                 return -ENOTSUP;
7315         }
7316
7317         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7318         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7319         etag_etype |= ether_type;
7320         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7321         IXGBE_WRITE_FLUSH(hw);
7322
7323         return 0;
7324 }
7325
7326 /* Config l2 tunnel ether type */
7327 static int
7328 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7329                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7330 {
7331         int ret = 0;
7332         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7333
7334         if (l2_tunnel == NULL)
7335                 return -EINVAL;
7336
7337         switch (l2_tunnel->l2_tunnel_type) {
7338         case RTE_L2_TUNNEL_TYPE_E_TAG:
7339                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7340                 break;
7341         default:
7342                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7343                 ret = -EINVAL;
7344                 break;
7345         }
7346
7347         return ret;
7348 }
7349
7350 /* Enable e-tag tunnel */
7351 static int
7352 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7353 {
7354         uint32_t etag_etype;
7355
7356         if (hw->mac.type != ixgbe_mac_X550 &&
7357             hw->mac.type != ixgbe_mac_X550EM_x &&
7358             hw->mac.type != ixgbe_mac_X550EM_a) {
7359                 return -ENOTSUP;
7360         }
7361
7362         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7363         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7364         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7365         IXGBE_WRITE_FLUSH(hw);
7366
7367         return 0;
7368 }
7369
7370 /* Enable l2 tunnel */
7371 static int
7372 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7373                            enum rte_eth_tunnel_type l2_tunnel_type)
7374 {
7375         int ret = 0;
7376         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7377
7378         switch (l2_tunnel_type) {
7379         case RTE_L2_TUNNEL_TYPE_E_TAG:
7380                 ret = ixgbe_e_tag_enable(hw);
7381                 break;
7382         default:
7383                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7384                 ret = -EINVAL;
7385                 break;
7386         }
7387
7388         return ret;
7389 }
7390
7391 /* Disable e-tag tunnel */
7392 static int
7393 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7394 {
7395         uint32_t etag_etype;
7396
7397         if (hw->mac.type != ixgbe_mac_X550 &&
7398             hw->mac.type != ixgbe_mac_X550EM_x &&
7399             hw->mac.type != ixgbe_mac_X550EM_a) {
7400                 return -ENOTSUP;
7401         }
7402
7403         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7404         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7405         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7406         IXGBE_WRITE_FLUSH(hw);
7407
7408         return 0;
7409 }
7410
7411 /* Disable l2 tunnel */
7412 static int
7413 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7414                             enum rte_eth_tunnel_type l2_tunnel_type)
7415 {
7416         int ret = 0;
7417         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7418
7419         switch (l2_tunnel_type) {
7420         case RTE_L2_TUNNEL_TYPE_E_TAG:
7421                 ret = ixgbe_e_tag_disable(hw);
7422                 break;
7423         default:
7424                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7425                 ret = -EINVAL;
7426                 break;
7427         }
7428
7429         return ret;
7430 }
7431
7432 static int
7433 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7434                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7435 {
7436         int ret = 0;
7437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7438         uint32_t i, rar_entries;
7439         uint32_t rar_low, rar_high;
7440
7441         if (hw->mac.type != ixgbe_mac_X550 &&
7442             hw->mac.type != ixgbe_mac_X550EM_x &&
7443             hw->mac.type != ixgbe_mac_X550EM_a) {
7444                 return -ENOTSUP;
7445         }
7446
7447         rar_entries = ixgbe_get_num_rx_addrs(hw);
7448
7449         for (i = 1; i < rar_entries; i++) {
7450                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7451                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7452                 if ((rar_high & IXGBE_RAH_AV) &&
7453                     (rar_high & IXGBE_RAH_ADTYPE) &&
7454                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7455                      l2_tunnel->tunnel_id)) {
7456                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7457                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7458
7459                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7460
7461                         return ret;
7462                 }
7463         }
7464
7465         return ret;
7466 }
7467
7468 static int
7469 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7470                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7471 {
7472         int ret = 0;
7473         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7474         uint32_t i, rar_entries;
7475         uint32_t rar_low, rar_high;
7476
7477         if (hw->mac.type != ixgbe_mac_X550 &&
7478             hw->mac.type != ixgbe_mac_X550EM_x &&
7479             hw->mac.type != ixgbe_mac_X550EM_a) {
7480                 return -ENOTSUP;
7481         }
7482
7483         /* One entry for one tunnel. Try to remove potential existing entry. */
7484         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7485
7486         rar_entries = ixgbe_get_num_rx_addrs(hw);
7487
7488         for (i = 1; i < rar_entries; i++) {
7489                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7490                 if (rar_high & IXGBE_RAH_AV) {
7491                         continue;
7492                 } else {
7493                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7494                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7495                         rar_low = l2_tunnel->tunnel_id;
7496
7497                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7498                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7499
7500                         return ret;
7501                 }
7502         }
7503
7504         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7505                      " Please remove a rule before adding a new one.");
7506         return -EINVAL;
7507 }
7508
7509 /* Add l2 tunnel filter */
7510 static int
7511 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7512                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7513 {
7514         int ret = 0;
7515
7516         switch (l2_tunnel->l2_tunnel_type) {
7517         case RTE_L2_TUNNEL_TYPE_E_TAG:
7518                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7519                 break;
7520         default:
7521                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7522                 ret = -EINVAL;
7523                 break;
7524         }
7525
7526         return ret;
7527 }
7528
7529 /* Delete l2 tunnel filter */
7530 static int
7531 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7532                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7533 {
7534         int ret = 0;
7535
7536         switch (l2_tunnel->l2_tunnel_type) {
7537         case RTE_L2_TUNNEL_TYPE_E_TAG:
7538                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7539                 break;
7540         default:
7541                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7542                 ret = -EINVAL;
7543                 break;
7544         }
7545
7546         return ret;
7547 }
7548
7549 /**
7550  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7551  * @dev: pointer to rte_eth_dev structure
7552  * @filter_op:operation will be taken.
7553  * @arg: a pointer to specific structure corresponding to the filter_op
7554  */
7555 static int
7556 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7557                                   enum rte_filter_op filter_op,
7558                                   void *arg)
7559 {
7560         int ret = 0;
7561
7562         if (filter_op == RTE_ETH_FILTER_NOP)
7563                 return 0;
7564
7565         if (arg == NULL) {
7566                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7567                             filter_op);
7568                 return -EINVAL;
7569         }
7570
7571         switch (filter_op) {
7572         case RTE_ETH_FILTER_ADD:
7573                 ret = ixgbe_dev_l2_tunnel_filter_add
7574                         (dev,
7575                          (struct rte_eth_l2_tunnel_conf *)arg);
7576                 break;
7577         case RTE_ETH_FILTER_DELETE:
7578                 ret = ixgbe_dev_l2_tunnel_filter_del
7579                         (dev,
7580                          (struct rte_eth_l2_tunnel_conf *)arg);
7581                 break;
7582         default:
7583                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7584                 ret = -EINVAL;
7585                 break;
7586         }
7587         return ret;
7588 }
7589
7590 static int
7591 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7592 {
7593         int ret = 0;
7594         uint32_t ctrl;
7595         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7596
7597         if (hw->mac.type != ixgbe_mac_X550 &&
7598             hw->mac.type != ixgbe_mac_X550EM_x &&
7599             hw->mac.type != ixgbe_mac_X550EM_a) {
7600                 return -ENOTSUP;
7601         }
7602
7603         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7604         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7605         if (en)
7606                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7607         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7608
7609         return ret;
7610 }
7611
7612 /* Enable l2 tunnel forwarding */
7613 static int
7614 ixgbe_dev_l2_tunnel_forwarding_enable
7615         (struct rte_eth_dev *dev,
7616          enum rte_eth_tunnel_type l2_tunnel_type)
7617 {
7618         int ret = 0;
7619
7620         switch (l2_tunnel_type) {
7621         case RTE_L2_TUNNEL_TYPE_E_TAG:
7622                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7623                 break;
7624         default:
7625                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7626                 ret = -EINVAL;
7627                 break;
7628         }
7629
7630         return ret;
7631 }
7632
7633 /* Disable l2 tunnel forwarding */
7634 static int
7635 ixgbe_dev_l2_tunnel_forwarding_disable
7636         (struct rte_eth_dev *dev,
7637          enum rte_eth_tunnel_type l2_tunnel_type)
7638 {
7639         int ret = 0;
7640
7641         switch (l2_tunnel_type) {
7642         case RTE_L2_TUNNEL_TYPE_E_TAG:
7643                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7644                 break;
7645         default:
7646                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7647                 ret = -EINVAL;
7648                 break;
7649         }
7650
7651         return ret;
7652 }
7653
7654 static int
7655 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7656                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7657                              bool en)
7658 {
7659         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7660         int ret = 0;
7661         uint32_t vmtir, vmvir;
7662         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7663
7664         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7665                 PMD_DRV_LOG(ERR,
7666                             "VF id %u should be less than %u",
7667                             l2_tunnel->vf_id,
7668                             pci_dev->max_vfs);
7669                 return -EINVAL;
7670         }
7671
7672         if (hw->mac.type != ixgbe_mac_X550 &&
7673             hw->mac.type != ixgbe_mac_X550EM_x &&
7674             hw->mac.type != ixgbe_mac_X550EM_a) {
7675                 return -ENOTSUP;
7676         }
7677
7678         if (en)
7679                 vmtir = l2_tunnel->tunnel_id;
7680         else
7681                 vmtir = 0;
7682
7683         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7684
7685         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7686         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7687         if (en)
7688                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7689         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7690
7691         return ret;
7692 }
7693
7694 /* Enable l2 tunnel tag insertion */
7695 static int
7696 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7697                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7698 {
7699         int ret = 0;
7700
7701         switch (l2_tunnel->l2_tunnel_type) {
7702         case RTE_L2_TUNNEL_TYPE_E_TAG:
7703                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7704                 break;
7705         default:
7706                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7707                 ret = -EINVAL;
7708                 break;
7709         }
7710
7711         return ret;
7712 }
7713
7714 /* Disable l2 tunnel tag insertion */
7715 static int
7716 ixgbe_dev_l2_tunnel_insertion_disable
7717         (struct rte_eth_dev *dev,
7718          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7719 {
7720         int ret = 0;
7721
7722         switch (l2_tunnel->l2_tunnel_type) {
7723         case RTE_L2_TUNNEL_TYPE_E_TAG:
7724                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7725                 break;
7726         default:
7727                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7728                 ret = -EINVAL;
7729                 break;
7730         }
7731
7732         return ret;
7733 }
7734
7735 static int
7736 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7737                              bool en)
7738 {
7739         int ret = 0;
7740         uint32_t qde;
7741         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7742
7743         if (hw->mac.type != ixgbe_mac_X550 &&
7744             hw->mac.type != ixgbe_mac_X550EM_x &&
7745             hw->mac.type != ixgbe_mac_X550EM_a) {
7746                 return -ENOTSUP;
7747         }
7748
7749         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7750         if (en)
7751                 qde |= IXGBE_QDE_STRIP_TAG;
7752         else
7753                 qde &= ~IXGBE_QDE_STRIP_TAG;
7754         qde &= ~IXGBE_QDE_READ;
7755         qde |= IXGBE_QDE_WRITE;
7756         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7757
7758         return ret;
7759 }
7760
7761 /* Enable l2 tunnel tag stripping */
7762 static int
7763 ixgbe_dev_l2_tunnel_stripping_enable
7764         (struct rte_eth_dev *dev,
7765          enum rte_eth_tunnel_type l2_tunnel_type)
7766 {
7767         int ret = 0;
7768
7769         switch (l2_tunnel_type) {
7770         case RTE_L2_TUNNEL_TYPE_E_TAG:
7771                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7772                 break;
7773         default:
7774                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7775                 ret = -EINVAL;
7776                 break;
7777         }
7778
7779         return ret;
7780 }
7781
7782 /* Disable l2 tunnel tag stripping */
7783 static int
7784 ixgbe_dev_l2_tunnel_stripping_disable
7785         (struct rte_eth_dev *dev,
7786          enum rte_eth_tunnel_type l2_tunnel_type)
7787 {
7788         int ret = 0;
7789
7790         switch (l2_tunnel_type) {
7791         case RTE_L2_TUNNEL_TYPE_E_TAG:
7792                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7793                 break;
7794         default:
7795                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7796                 ret = -EINVAL;
7797                 break;
7798         }
7799
7800         return ret;
7801 }
7802
7803 /* Enable/disable l2 tunnel offload functions */
7804 static int
7805 ixgbe_dev_l2_tunnel_offload_set
7806         (struct rte_eth_dev *dev,
7807          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7808          uint32_t mask,
7809          uint8_t en)
7810 {
7811         int ret = 0;
7812
7813         if (l2_tunnel == NULL)
7814                 return -EINVAL;
7815
7816         ret = -EINVAL;
7817         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7818                 if (en)
7819                         ret = ixgbe_dev_l2_tunnel_enable(
7820                                 dev,
7821                                 l2_tunnel->l2_tunnel_type);
7822                 else
7823                         ret = ixgbe_dev_l2_tunnel_disable(
7824                                 dev,
7825                                 l2_tunnel->l2_tunnel_type);
7826         }
7827
7828         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7829                 if (en)
7830                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7831                                 dev,
7832                                 l2_tunnel);
7833                 else
7834                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7835                                 dev,
7836                                 l2_tunnel);
7837         }
7838
7839         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7840                 if (en)
7841                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7842                                 dev,
7843                                 l2_tunnel->l2_tunnel_type);
7844                 else
7845                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7846                                 dev,
7847                                 l2_tunnel->l2_tunnel_type);
7848         }
7849
7850         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7851                 if (en)
7852                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7853                                 dev,
7854                                 l2_tunnel->l2_tunnel_type);
7855                 else
7856                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7857                                 dev,
7858                                 l2_tunnel->l2_tunnel_type);
7859         }
7860
7861         return ret;
7862 }
7863
7864 static int
7865 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7866                         uint16_t port)
7867 {
7868         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7869         IXGBE_WRITE_FLUSH(hw);
7870
7871         return 0;
7872 }
7873
7874 /* There's only one register for VxLAN UDP port.
7875  * So, we cannot add several ports. Will update it.
7876  */
7877 static int
7878 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7879                      uint16_t port)
7880 {
7881         if (port == 0) {
7882                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7883                 return -EINVAL;
7884         }
7885
7886         return ixgbe_update_vxlan_port(hw, port);
7887 }
7888
7889 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7890  * UDP port, it must have a value.
7891  * So, will reset it to the original value 0.
7892  */
7893 static int
7894 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7895                      uint16_t port)
7896 {
7897         uint16_t cur_port;
7898
7899         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7900
7901         if (cur_port != port) {
7902                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7903                 return -EINVAL;
7904         }
7905
7906         return ixgbe_update_vxlan_port(hw, 0);
7907 }
7908
7909 /* Add UDP tunneling port */
7910 static int
7911 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7912                               struct rte_eth_udp_tunnel *udp_tunnel)
7913 {
7914         int ret = 0;
7915         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7916
7917         if (hw->mac.type != ixgbe_mac_X550 &&
7918             hw->mac.type != ixgbe_mac_X550EM_x &&
7919             hw->mac.type != ixgbe_mac_X550EM_a) {
7920                 return -ENOTSUP;
7921         }
7922
7923         if (udp_tunnel == NULL)
7924                 return -EINVAL;
7925
7926         switch (udp_tunnel->prot_type) {
7927         case RTE_TUNNEL_TYPE_VXLAN:
7928                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7929                 break;
7930
7931         case RTE_TUNNEL_TYPE_GENEVE:
7932         case RTE_TUNNEL_TYPE_TEREDO:
7933                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7934                 ret = -EINVAL;
7935                 break;
7936
7937         default:
7938                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7939                 ret = -EINVAL;
7940                 break;
7941         }
7942
7943         return ret;
7944 }
7945
7946 /* Remove UDP tunneling port */
7947 static int
7948 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7949                               struct rte_eth_udp_tunnel *udp_tunnel)
7950 {
7951         int ret = 0;
7952         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7953
7954         if (hw->mac.type != ixgbe_mac_X550 &&
7955             hw->mac.type != ixgbe_mac_X550EM_x &&
7956             hw->mac.type != ixgbe_mac_X550EM_a) {
7957                 return -ENOTSUP;
7958         }
7959
7960         if (udp_tunnel == NULL)
7961                 return -EINVAL;
7962
7963         switch (udp_tunnel->prot_type) {
7964         case RTE_TUNNEL_TYPE_VXLAN:
7965                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7966                 break;
7967         case RTE_TUNNEL_TYPE_GENEVE:
7968         case RTE_TUNNEL_TYPE_TEREDO:
7969                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7970                 ret = -EINVAL;
7971                 break;
7972         default:
7973                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7974                 ret = -EINVAL;
7975                 break;
7976         }
7977
7978         return ret;
7979 }
7980
7981 static void
7982 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7983 {
7984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7985
7986         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7987 }
7988
7989 static void
7990 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7991 {
7992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7993
7994         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
7995 }
7996
7997 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7998 {
7999         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8000         u32 in_msg = 0;
8001
8002         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8003                 return;
8004
8005         /* PF reset VF event */
8006         if (in_msg == IXGBE_PF_CONTROL_MSG)
8007                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8008 }
8009
8010 static int
8011 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8012 {
8013         uint32_t eicr;
8014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015         struct ixgbe_interrupt *intr =
8016                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8017         ixgbevf_intr_disable(hw);
8018
8019         /* read-on-clear nic registers here */
8020         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8021         intr->flags = 0;
8022
8023         /* only one misc vector supported - mailbox */
8024         eicr &= IXGBE_VTEICR_MASK;
8025         if (eicr == IXGBE_MISC_VEC_ID)
8026                 intr->flags |= IXGBE_FLAG_MAILBOX;
8027
8028         return 0;
8029 }
8030
8031 static int
8032 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8033 {
8034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8035         struct ixgbe_interrupt *intr =
8036                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8037
8038         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8039                 ixgbevf_mbx_process(dev);
8040                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8041         }
8042
8043         ixgbevf_intr_enable(hw);
8044
8045         return 0;
8046 }
8047
8048 static void
8049 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8050                               void *param)
8051 {
8052         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8053
8054         ixgbevf_dev_interrupt_get_status(dev);
8055         ixgbevf_dev_interrupt_action(dev);
8056 }
8057
8058 /**
8059  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8060  *  @hw: pointer to hardware structure
8061  *
8062  *  Stops the transmit data path and waits for the HW to internally empty
8063  *  the Tx security block
8064  **/
8065 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8066 {
8067 #define IXGBE_MAX_SECTX_POLL 40
8068
8069         int i;
8070         int sectxreg;
8071
8072         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8073         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8074         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8075         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8076                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8077                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8078                         break;
8079                 /* Use interrupt-safe sleep just in case */
8080                 usec_delay(1000);
8081         }
8082
8083         /* For informational purposes only */
8084         if (i >= IXGBE_MAX_SECTX_POLL)
8085                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8086                          "path fully disabled.  Continuing with init.\n");
8087
8088         return IXGBE_SUCCESS;
8089 }
8090
8091 /**
8092  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8093  *  @hw: pointer to hardware structure
8094  *
8095  *  Enables the transmit data path.
8096  **/
8097 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8098 {
8099         uint32_t sectxreg;
8100
8101         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8102         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8103         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8104         IXGBE_WRITE_FLUSH(hw);
8105
8106         return IXGBE_SUCCESS;
8107 }
8108
8109 int
8110 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8111 {
8112         struct ixgbe_hw *hw;
8113         struct rte_eth_dev *dev;
8114         uint32_t ctrl;
8115
8116         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8117
8118         dev = &rte_eth_devices[port];
8119         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120
8121         /* Stop the data paths */
8122         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8123                 return -ENOTSUP;
8124         /*
8125          * Workaround:
8126          * As no ixgbe_disable_sec_rx_path equivalent is
8127          * implemented for tx in the base code, and we are
8128          * not allowed to modify the base code in DPDK, so
8129          * just call the hand-written one directly for now.
8130          * The hardware support has been checked by
8131          * ixgbe_disable_sec_rx_path().
8132          */
8133         ixgbe_disable_sec_tx_path_generic(hw);
8134
8135         /* Enable Ethernet CRC (required by MACsec offload) */
8136         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8137         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8138         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8139
8140         /* Enable the TX and RX crypto engines */
8141         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8142         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8143         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8144
8145         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8146         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8147         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8148
8149         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8150         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8151         ctrl |= 0x3;
8152         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8153
8154         /* Enable SA lookup */
8155         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8156         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8157         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8158                      IXGBE_LSECTXCTRL_AUTH;
8159         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8160         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8161         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8162         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8163
8164         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8165         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8166         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8167         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8168         if (rp)
8169                 ctrl |= IXGBE_LSECRXCTRL_RP;
8170         else
8171                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8172         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8173
8174         /* Start the data paths */
8175         ixgbe_enable_sec_rx_path(hw);
8176         /*
8177          * Workaround:
8178          * As no ixgbe_enable_sec_rx_path equivalent is
8179          * implemented for tx in the base code, and we are
8180          * not allowed to modify the base code in DPDK, so
8181          * just call the hand-written one directly for now.
8182          */
8183         ixgbe_enable_sec_tx_path_generic(hw);
8184
8185         return 0;
8186 }
8187
8188 int
8189 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8190 {
8191         struct ixgbe_hw *hw;
8192         struct rte_eth_dev *dev;
8193         uint32_t ctrl;
8194
8195         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8196
8197         dev = &rte_eth_devices[port];
8198         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8199
8200         /* Stop the data paths */
8201         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8202                 return -ENOTSUP;
8203         /*
8204          * Workaround:
8205          * As no ixgbe_disable_sec_rx_path equivalent is
8206          * implemented for tx in the base code, and we are
8207          * not allowed to modify the base code in DPDK, so
8208          * just call the hand-written one directly for now.
8209          * The hardware support has been checked by
8210          * ixgbe_disable_sec_rx_path().
8211          */
8212         ixgbe_disable_sec_tx_path_generic(hw);
8213
8214         /* Disable the TX and RX crypto engines */
8215         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8216         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8217         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8218
8219         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8220         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8221         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8222
8223         /* Disable SA lookup */
8224         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8225         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8226         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8227         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8228
8229         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8230         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8231         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8232         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8233
8234         /* Start the data paths */
8235         ixgbe_enable_sec_rx_path(hw);
8236         /*
8237          * Workaround:
8238          * As no ixgbe_enable_sec_rx_path equivalent is
8239          * implemented for tx in the base code, and we are
8240          * not allowed to modify the base code in DPDK, so
8241          * just call the hand-written one directly for now.
8242          */
8243         ixgbe_enable_sec_tx_path_generic(hw);
8244
8245         return 0;
8246 }
8247
8248 int
8249 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8250 {
8251         struct ixgbe_hw *hw;
8252         struct rte_eth_dev *dev;
8253         uint32_t ctrl;
8254
8255         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8256
8257         dev = &rte_eth_devices[port];
8258         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8259
8260         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8261         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8262
8263         ctrl = mac[4] | (mac[5] << 8);
8264         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8265
8266         return 0;
8267 }
8268
8269 int
8270 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8271 {
8272         struct ixgbe_hw *hw;
8273         struct rte_eth_dev *dev;
8274         uint32_t ctrl;
8275
8276         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8277
8278         dev = &rte_eth_devices[port];
8279         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8280
8281         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8282         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8283
8284         pi = rte_cpu_to_be_16(pi);
8285         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8286         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8287
8288         return 0;
8289 }
8290
8291 int
8292 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8293                                  uint32_t pn, uint8_t *key)
8294 {
8295         struct ixgbe_hw *hw;
8296         struct rte_eth_dev *dev;
8297         uint32_t ctrl, i;
8298
8299         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8300
8301         dev = &rte_eth_devices[port];
8302         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8303
8304         if (idx != 0 && idx != 1)
8305                 return -EINVAL;
8306
8307         if (an >= 4)
8308                 return -EINVAL;
8309
8310         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8311
8312         /* Set the PN and key */
8313         pn = rte_cpu_to_be_32(pn);
8314         if (idx == 0) {
8315                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8316
8317                 for (i = 0; i < 4; i++) {
8318                         ctrl = (key[i * 4 + 0] <<  0) |
8319                                (key[i * 4 + 1] <<  8) |
8320                                (key[i * 4 + 2] << 16) |
8321                                (key[i * 4 + 3] << 24);
8322                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8323                 }
8324         } else {
8325                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8326
8327                 for (i = 0; i < 4; i++) {
8328                         ctrl = (key[i * 4 + 0] <<  0) |
8329                                (key[i * 4 + 1] <<  8) |
8330                                (key[i * 4 + 2] << 16) |
8331                                (key[i * 4 + 3] << 24);
8332                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8333                 }
8334         }
8335
8336         /* Set AN and select the SA */
8337         ctrl = (an << idx * 2) | (idx << 4);
8338         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8339
8340         return 0;
8341 }
8342
8343 int
8344 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8345                                  uint32_t pn, uint8_t *key)
8346 {
8347         struct ixgbe_hw *hw;
8348         struct rte_eth_dev *dev;
8349         uint32_t ctrl, i;
8350
8351         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8352
8353         dev = &rte_eth_devices[port];
8354         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8355
8356         if (idx != 0 && idx != 1)
8357                 return -EINVAL;
8358
8359         if (an >= 4)
8360                 return -EINVAL;
8361
8362         /* Set the PN */
8363         pn = rte_cpu_to_be_32(pn);
8364         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8365
8366         /* Set the key */
8367         for (i = 0; i < 4; i++) {
8368                 ctrl = (key[i * 4 + 0] <<  0) |
8369                        (key[i * 4 + 1] <<  8) |
8370                        (key[i * 4 + 2] << 16) |
8371                        (key[i * 4 + 3] << 24);
8372                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8373         }
8374
8375         /* Set the AN and validate the SA */
8376         ctrl = an | (1 << 2);
8377         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8378
8379         return 0;
8380 }
8381
8382 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8383 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8384 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8385 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8386 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8387 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");