drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 159 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 160
 161 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 162 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 163 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 164 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 165 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 166 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 167 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 168 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 169 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 170 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 171 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 172 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 173 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 174 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 175 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 178 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 179                                 int wait_to_complete);
 180 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 181                                 struct rte_eth_stats *stats);
 182 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 183                                 struct rte_eth_xstat *xstats, unsigned n);
 184 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 185                                   struct rte_eth_xstat *xstats, unsigned n);
 186 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 187 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 188 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 189         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 190 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 191         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 192 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 193                                              uint16_t queue_id,
 194                                              uint8_t stat_idx,
 195                                              uint8_t is_rx);
 196 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 197                                  size_t fw_size);
 198 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 199                                struct rte_eth_dev_info *dev_info);
 200 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 201 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 202                                  struct rte_eth_dev_info *dev_info);
 203 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 204
 205 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 206                 uint16_t vlan_id, int on);
 207 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 208                                enum rte_vlan_type vlan_type,
 209                                uint16_t tpid_id);
 210 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 211                 uint16_t queue, bool on);
 212 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 213                 int on);
 214 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 215 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 216 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 217 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 218 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 219
 220 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 221 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 222 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 223                                struct rte_eth_fc_conf *fc_conf);
 224 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 225                                struct rte_eth_fc_conf *fc_conf);
 226 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 227                 struct rte_eth_pfc_conf *pfc_conf);
 228 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 229                         struct rte_eth_rss_reta_entry64 *reta_conf,
 230                         uint16_t reta_size);
 231 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 232                         struct rte_eth_rss_reta_entry64 *reta_conf,
 233                         uint16_t reta_size);
 234 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 235 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 236 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 237 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 238 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 239 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 240                                       struct rte_intr_handle *handle);
 241 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 242                 void *param);
 243 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 244 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 245                 uint32_t index, uint32_t pool);
 246 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 247 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 248                                            struct ether_addr *mac_addr);
 249 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 250 static bool is_device_supported(struct rte_eth_dev *dev,
 251                                 struct eth_driver *drv);
 252
 253 /* For Virtual Function support */
 254 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 255 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 256 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 257 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 258 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 259 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 260 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 261 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 262 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 263                 struct rte_eth_stats *stats);
 264 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 265 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 266                 uint16_t vlan_id, int on);
 267 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 268                 uint16_t queue, int on);
 269 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 270 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 271 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 272                                             uint16_t queue_id);
 273 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 274                                              uint16_t queue_id);
 275 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 276                                  uint8_t queue, uint8_t msix_vector);
 277 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 278 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 279 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 280
 281 /* For Eth VMDQ APIs support */
 282 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 283                 ether_addr * mac_addr, uint8_t on);
 284 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 285 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 286                 struct rte_eth_mirror_conf *mirror_conf,
 287                 uint8_t rule_id, uint8_t on);
 288 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 289                 uint8_t rule_id);
 290 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 291                                           uint16_t queue_id);
 292 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 293                                            uint16_t queue_id);
 294 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 295                                uint8_t queue, uint8_t msix_vector);
 296 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 297
 298 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 299                 uint16_t queue_idx, uint16_t tx_rate);
 300
 301 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 302                                  struct ether_addr *mac_addr,
 303                                  uint32_t index, uint32_t pool);
 304 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 305 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 306                                              struct ether_addr *mac_addr);
 307 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 308                         struct rte_eth_syn_filter *filter);
 309 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 310                         enum rte_filter_op filter_op,
 311                         void *arg);
 312 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 313                         struct ixgbe_5tuple_filter *filter);
 314 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 315                         struct ixgbe_5tuple_filter *filter);
 316 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 317                                 enum rte_filter_op filter_op,
 318                                 void *arg);
 319 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 320                         struct rte_eth_ntuple_filter *filter);
 321 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ethertype_filter *filter);
 326 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                      enum rte_filter_type filter_type,
 328                      enum rte_filter_op filter_op,
 329                      void *arg);
 330 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 331
 332 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 333                                       struct ether_addr *mc_addr_set,
 334                                       uint32_t nb_mc_addr);
 335 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 336                                    struct rte_eth_dcb_info *dcb_info);
 337
 338 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 339 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 340                             struct rte_dev_reg_info *regs);
 341 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 342 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 343                                 struct rte_dev_eeprom_info *eeprom);
 344 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 345                                 struct rte_dev_eeprom_info *eeprom);
 346
 347 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 348 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 349                                 struct rte_dev_reg_info *regs);
 350
 351 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 352 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                             struct timespec *timestamp,
 355                                             uint32_t flags);
 356 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                             struct timespec *timestamp);
 358 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 359 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 360                                    struct timespec *timestamp);
 361 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 362                                    const struct timespec *timestamp);
 363 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 364                                           void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383
 384 /*
 385  * Define VF Stats MACRO for Non "cleared on read" register
 386  */
 387 #define UPDATE_VF_STAT(reg, last, cur)                          \
 388 {                                                               \
 389         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 390         cur += (latest - last) & UINT_MAX;                      \
 391         last = latest;                                          \
 392 }
 393
 394 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 395 {                                                                \
 396         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 397         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 398         u64 latest = ((new_msb << 32) | new_lsb);                \
 399         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 400         last = latest;                                           \
 401 }
 402
 403 #define IXGBE_SET_HWSTRIP(h, q) do {\
 404                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 405                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 406                 (h)->bitmap[idx] |= 1 << bit;\
 407         } while (0)
 408
 409 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 410                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 411                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 412                 (h)->bitmap[idx] &= ~(1 << bit);\
 413         } while (0)
 414
 415 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 416                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 417                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 418                 (r) = (h)->bitmap[idx] >> bit & 1;\
 419         } while (0)
 420
 421 /*
 422  * The set of PCI devices this driver supports
 423  */
 424 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 478 #ifdef RTE_NIC_BYPASS
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 480 #endif
 481         { .vendor_id = 0, /* sentinel */ },
 482 };
 483
 484 /*
 485  * The set of PCI devices this driver supports (for 82599 VF)
 486  */
 487 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 498         { .vendor_id = 0, /* sentinel */ },
 499 };
 500
 501 static const struct rte_eth_desc_lim rx_desc_lim = {
 502         .nb_max = IXGBE_MAX_RING_DESC,
 503         .nb_min = IXGBE_MIN_RING_DESC,
 504         .nb_align = IXGBE_RXD_ALIGN,
 505 };
 506
 507 static const struct rte_eth_desc_lim tx_desc_lim = {
 508         .nb_max = IXGBE_MAX_RING_DESC,
 509         .nb_min = IXGBE_MIN_RING_DESC,
 510         .nb_align = IXGBE_TXD_ALIGN,
 511         .nb_seg_max = IXGBE_TX_MAX_SEG,
 512         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 513 };
 514
 515 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 516         .dev_configure        = ixgbe_dev_configure,
 517         .dev_start            = ixgbe_dev_start,
 518         .dev_stop             = ixgbe_dev_stop,
 519         .dev_set_link_up    = ixgbe_dev_set_link_up,
 520         .dev_set_link_down  = ixgbe_dev_set_link_down,
 521         .dev_close            = ixgbe_dev_close,
 522         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 523         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 524         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 525         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 526         .link_update          = ixgbe_dev_link_update,
 527         .stats_get            = ixgbe_dev_stats_get,
 528         .xstats_get           = ixgbe_dev_xstats_get,
 529         .stats_reset          = ixgbe_dev_stats_reset,
 530         .xstats_reset         = ixgbe_dev_xstats_reset,
 531         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 532         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 533         .fw_version_get       = ixgbe_fw_version_get,
 534         .dev_infos_get        = ixgbe_dev_info_get,
 535         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 536         .mtu_set              = ixgbe_dev_mtu_set,
 537         .vlan_filter_set      = ixgbe_vlan_filter_set,
 538         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 539         .vlan_offload_set     = ixgbe_vlan_offload_set,
 540         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 541         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 542         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 543         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 544         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 545         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 546         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 547         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 548         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 549         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 550         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 551         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 552         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 553         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 554         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 555         .dev_led_on           = ixgbe_dev_led_on,
 556         .dev_led_off          = ixgbe_dev_led_off,
 557         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 558         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 559         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 560         .mac_addr_add         = ixgbe_add_rar,
 561         .mac_addr_remove      = ixgbe_remove_rar,
 562         .mac_addr_set         = ixgbe_set_default_mac_addr,
 563         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 564         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 565         .mirror_rule_set      = ixgbe_mirror_rule_set,
 566         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 567         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 568         .reta_update          = ixgbe_dev_rss_reta_update,
 569         .reta_query           = ixgbe_dev_rss_reta_query,
 570 #ifdef RTE_NIC_BYPASS
 571         .bypass_init          = ixgbe_bypass_init,
 572         .bypass_state_set     = ixgbe_bypass_state_store,
 573         .bypass_state_show    = ixgbe_bypass_state_show,
 574         .bypass_event_set     = ixgbe_bypass_event_store,
 575         .bypass_event_show    = ixgbe_bypass_event_show,
 576         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 577         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 578         .bypass_ver_show      = ixgbe_bypass_ver_show,
 579         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 580 #endif /* RTE_NIC_BYPASS */
 581         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 582         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 583         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 584         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 585         .rxq_info_get         = ixgbe_rxq_info_get,
 586         .txq_info_get         = ixgbe_txq_info_get,
 587         .timesync_enable      = ixgbe_timesync_enable,
 588         .timesync_disable     = ixgbe_timesync_disable,
 589         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 590         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 591         .get_reg              = ixgbe_get_regs,
 592         .get_eeprom_length    = ixgbe_get_eeprom_length,
 593         .get_eeprom           = ixgbe_get_eeprom,
 594         .set_eeprom           = ixgbe_set_eeprom,
 595         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 596         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 597         .timesync_read_time   = ixgbe_timesync_read_time,
 598         .timesync_write_time  = ixgbe_timesync_write_time,
 599         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 600         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 601         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 602         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 603 };
 604
 605 /*
 606  * dev_ops for virtual function, bare necessities for basic vf
 607  * operation have been implemented
 608  */
 609 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 610         .dev_configure        = ixgbevf_dev_configure,
 611         .dev_start            = ixgbevf_dev_start,
 612         .dev_stop             = ixgbevf_dev_stop,
 613         .link_update          = ixgbe_dev_link_update,
 614         .stats_get            = ixgbevf_dev_stats_get,
 615         .xstats_get           = ixgbevf_dev_xstats_get,
 616         .stats_reset          = ixgbevf_dev_stats_reset,
 617         .xstats_reset         = ixgbevf_dev_stats_reset,
 618         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 619         .dev_close            = ixgbevf_dev_close,
 620         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 621         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 622         .dev_infos_get        = ixgbevf_dev_info_get,
 623         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 624         .mtu_set              = ixgbevf_dev_set_mtu,
 625         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 626         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 627         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 628         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 629         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 630         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 631         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 632         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 633         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 634         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 635         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 636         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 637         .mac_addr_add         = ixgbevf_add_mac_addr,
 638         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 639         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 640         .rxq_info_get         = ixgbe_rxq_info_get,
 641         .txq_info_get         = ixgbe_txq_info_get,
 642         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 643         .get_reg              = ixgbevf_get_regs,
 644         .reta_update          = ixgbe_dev_rss_reta_update,
 645         .reta_query           = ixgbe_dev_rss_reta_query,
 646         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 647         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 648 };
 649
 650 /* store statistics names and its offset in stats structure */
 651 struct rte_ixgbe_xstats_name_off {
 652         char name[RTE_ETH_XSTATS_NAME_SIZE];
 653         unsigned offset;
 654 };
 655
 656 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 657         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 658         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 659         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 660         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 661         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 662         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 663         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 664         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 665         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 666         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 667         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 668         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 669         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 670         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 671         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 672                 prc1023)},
 673         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 674                 prc1522)},
 675         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 676         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 677         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 678         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 679         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 680         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 681         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 682         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 683         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 684         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 685         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 686         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 687         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 688         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 689         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 690         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 691         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 692                 ptc1023)},
 693         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 694                 ptc1522)},
 695         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 696         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 697         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 698         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 699
 700         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 701                 fdirustat_add)},
 702         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 703                 fdirustat_remove)},
 704         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 705                 fdirfstat_fadd)},
 706         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 707                 fdirfstat_fremove)},
 708         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 709                 fdirmatch)},
 710         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 711                 fdirmiss)},
 712
 713         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 714         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 715         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 716                 fclast)},
 717         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 718         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 719         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 720         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 721         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 722                 fcoe_noddp)},
 723         {"rx_fcoe_no_direct_data_placement_ext_buff",
 724                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 725
 726         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxontxc)},
 728         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxonrxc)},
 730         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 731                 lxofftxc)},
 732         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 733                 lxoffrxc)},
 734         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 735 };
 736
 737 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 738                            sizeof(rte_ixgbe_stats_strings[0]))
 739
 740 /* MACsec statistics */
 741 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 742         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_untagged)},
 744         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_pkts_encrypted)},
 746         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_pkts_protected)},
 748         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 749                 out_octets_encrypted)},
 750         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 751                 out_octets_protected)},
 752         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_untagged)},
 754         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_badtag)},
 756         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 757                 in_pkts_nosci)},
 758         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 759                 in_pkts_unknownsci)},
 760         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 761                 in_octets_decrypted)},
 762         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 763                 in_octets_validated)},
 764         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_unchecked)},
 766         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_delayed)},
 768         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_late)},
 770         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_ok)},
 772         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_invalid)},
 774         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notvalid)},
 776         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 777                 in_pkts_unusedsa)},
 778         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 779                 in_pkts_notusingsa)},
 780 };
 781
 782 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 783                            sizeof(rte_ixgbe_macsec_strings[0]))
 784
 785 /* Per-queue statistics */
 786 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 787         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 788         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 789         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 790         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 791 };
 792
 793 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 794                            sizeof(rte_ixgbe_rxq_strings[0]))
 795 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 796
 797 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 798         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 799         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 800         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 801                 pxon2offc)},
 802 };
 803
 804 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 805                            sizeof(rte_ixgbe_txq_strings[0]))
 806 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 807
 808 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 809         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 810 };
 811
 812 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 813                 sizeof(rte_ixgbevf_stats_strings[0]))
 814
 815 /**
 816  * Atomically reads the link status information from global
 817  * structure rte_eth_dev.
 818  *
 819  * @param dev
 820  *   - Pointer to the structure rte_eth_dev to read from.
 821  *   - Pointer to the buffer to be saved with the link status.
 822  *
 823  * @return
 824  *   - On success, zero.
 825  *   - On failure, negative value.
 826  */
 827 static inline int
 828 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 829                                 struct rte_eth_link *link)
 830 {
 831         struct rte_eth_link *dst = link;
 832         struct rte_eth_link *src = &(dev->data->dev_link);
 833
 834         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 835                                         *(uint64_t *)src) == 0)
 836                 return -1;
 837
 838         return 0;
 839 }
 840
 841 /**
 842  * Atomically writes the link status information into global
 843  * structure rte_eth_dev.
 844  *
 845  * @param dev
 846  *   - Pointer to the structure rte_eth_dev to read from.
 847  *   - Pointer to the buffer to be saved with the link status.
 848  *
 849  * @return
 850  *   - On success, zero.
 851  *   - On failure, negative value.
 852  */
 853 static inline int
 854 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 855                                 struct rte_eth_link *link)
 856 {
 857         struct rte_eth_link *dst = &(dev->data->dev_link);
 858         struct rte_eth_link *src = link;
 859
 860         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 861                                         *(uint64_t *)src) == 0)
 862                 return -1;
 863
 864         return 0;
 865 }
 866
 867 /*
 868  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 869  */
 870 static inline int
 871 ixgbe_is_sfp(struct ixgbe_hw *hw)
 872 {
 873         switch (hw->phy.type) {
 874         case ixgbe_phy_sfp_avago:
 875         case ixgbe_phy_sfp_ftl:
 876         case ixgbe_phy_sfp_intel:
 877         case ixgbe_phy_sfp_unknown:
 878         case ixgbe_phy_sfp_passive_tyco:
 879         case ixgbe_phy_sfp_passive_unknown:
 880                 return 1;
 881         default:
 882                 return 0;
 883         }
 884 }
 885
 886 static inline int32_t
 887 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 888 {
 889         uint32_t ctrl_ext;
 890         int32_t status;
 891
 892         status = ixgbe_reset_hw(hw);
 893
 894         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 895         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 896         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 897         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 898         IXGBE_WRITE_FLUSH(hw);
 899
 900         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 901                 status = IXGBE_SUCCESS;
 902         return status;
 903 }
 904
 905 static inline void
 906 ixgbe_enable_intr(struct rte_eth_dev *dev)
 907 {
 908         struct ixgbe_interrupt *intr =
 909                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 910         struct ixgbe_hw *hw =
 911                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 912
 913         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 914         IXGBE_WRITE_FLUSH(hw);
 915 }
 916
 917 /*
 918  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 919  */
 920 static void
 921 ixgbe_disable_intr(struct ixgbe_hw *hw)
 922 {
 923         PMD_INIT_FUNC_TRACE();
 924
 925         if (hw->mac.type == ixgbe_mac_82598EB) {
 926                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 927         } else {
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 930                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 931         }
 932         IXGBE_WRITE_FLUSH(hw);
 933 }
 934
 935 /*
 936  * This function resets queue statistics mapping registers.
 937  * From Niantic datasheet, Initialization of Statistics section:
 938  * "...if software requires the queue counters, the RQSMR and TQSM registers
 939  * must be re-programmed following a device reset.
 940  */
 941 static void
 942 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 943 {
 944         uint32_t i;
 945
 946         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 947                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 948                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 949         }
 950 }
 951
 952
 953 static int
 954 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 955                                   uint16_t queue_id,
 956                                   uint8_t stat_idx,
 957                                   uint8_t is_rx)
 958 {
 959 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 960 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 961 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 962
 963         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 964         struct ixgbe_stat_mapping_registers *stat_mappings =
 965                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 966         uint32_t qsmr_mask = 0;
 967         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 968         uint32_t q_map;
 969         uint8_t n, offset;
 970
 971         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 972                 (hw->mac.type != ixgbe_mac_X540) &&
 973                 (hw->mac.type != ixgbe_mac_X550) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 975                 (hw->mac.type != ixgbe_mac_X550EM_a))
 976                 return -ENOSYS;
 977
 978         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 979                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 980                      queue_id, stat_idx);
 981
 982         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 983         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 984                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 985                 return -EIO;
 986         }
 987         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 988
 989         /* Now clear any previous stat_idx set */
 990         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 991         if (!is_rx)
 992                 stat_mappings->tqsm[n] &= ~clearing_mask;
 993         else
 994                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 995
 996         q_map = (uint32_t)stat_idx;
 997         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 998         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 999         if (!is_rx)
1000                 stat_mappings->tqsm[n] |= qsmr_mask;
1001         else
1002                 stat_mappings->rqsmr[n] |= qsmr_mask;
1003
1004         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1005                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1006                      queue_id, stat_idx);
1007         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1008                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1009
1010         /* Now write the mapping in the appropriate register */
1011         if (is_rx) {
1012                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1013                              stat_mappings->rqsmr[n], n);
1014                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1015         } else {
1016                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1017                              stat_mappings->tqsm[n], n);
1018                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1019         }
1020         return 0;
1021 }
1022
1023 static void
1024 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1025 {
1026         struct ixgbe_stat_mapping_registers *stat_mappings =
1027                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1028         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029         int i;
1030
1031         /* write whatever was in stat mapping table to the NIC */
1032         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1033                 /* rx */
1034                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035
1036                 /* tx */
1037                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038         }
1039 }
1040
1041 static void
1042 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 {
1044         uint8_t i;
1045         struct ixgbe_dcb_tc_config *tc;
1046         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1047
1048         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1049         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1050         for (i = 0; i < dcb_max_tc; i++) {
1051                 tc = &dcb_config->tc_config[i];
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1053                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1054                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1056                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1057                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1058                 tc->pfc = ixgbe_dcb_pfc_disabled;
1059         }
1060
1061         /* Initialize default user to priority mapping, UPx->TC0 */
1062         tc = &dcb_config->tc_config[0];
1063         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1065         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1066                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1067                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1068         }
1069         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1070         dcb_config->pfc_mode_enable = false;
1071         dcb_config->vt_mode = true;
1072         dcb_config->round_robin_enable = false;
1073         /* support all DCB capabilities in 82599 */
1074         dcb_config->support.capabilities = 0xFF;
1075
1076         /*we only support 4 Tcs for X540, X550 */
1077         if (hw->mac.type == ixgbe_mac_X540 ||
1078                 hw->mac.type == ixgbe_mac_X550 ||
1079                 hw->mac.type == ixgbe_mac_X550EM_x ||
1080                 hw->mac.type == ixgbe_mac_X550EM_a) {
1081                 dcb_config->num_tcs.pg_tcs = 4;
1082                 dcb_config->num_tcs.pfc_tcs = 4;
1083         }
1084 }
1085
1086 /*
1087  * Ensure that all locks are released before first NVM or PHY access
1088  */
1089 static void
1090 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 {
1092         uint16_t mask;
1093
1094         /*
1095          * Phy lock should not fail in this early stage. If this is the case,
1096          * it is due to an improper exit of the application.
1097          * So force the release of the faulty lock. Release of common lock
1098          * is done automatically by swfw_sync function.
1099          */
1100         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1101         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1102                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1103         }
1104         ixgbe_release_swfw_semaphore(hw, mask);
1105
1106         /*
1107          * These ones are more tricky since they are common to all ports; but
1108          * swfw_sync retries last long enough (1s) to be almost sure that if
1109          * lock can not be taken it is due to an improper lock of the
1110          * semaphore.
1111          */
1112         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1113         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1114                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1115         }
1116         ixgbe_release_swfw_semaphore(hw, mask);
1117 }
1118
1119 /*
1120  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1121  * It returns 0 on success.
1122  */
1123 static int
1124 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1125 {
1126         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1127         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1128         struct ixgbe_hw *hw =
1129                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1130         struct ixgbe_vfta *shadow_vfta =
1131                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1132         struct ixgbe_hwstrip *hwstrip =
1133                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1134         struct ixgbe_dcb_config *dcb_config =
1135                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1136         struct ixgbe_filter_info *filter_info =
1137                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1138         uint32_t ctrl_ext;
1139         uint16_t csum;
1140         int diag, i;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148
1149         /*
1150          * For secondary processes, we don't initialise any further as primary
1151          * has already done this work. Only check we don't need a different
1152          * RX and TX function.
1153          */
1154         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155                 struct ixgbe_tx_queue *txq;
1156                 /* TX queue function in primary, set by last queue initialized
1157                  * Tx queue may not initialized by primary process
1158                  */
1159                 if (eth_dev->data->tx_queues) {
1160                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161                         ixgbe_set_tx_function(eth_dev, txq);
1162                 } else {
1163                         /* Use default TX function if we get here */
1164                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165                                      "Using default TX function.");
1166                 }
1167
1168                 ixgbe_set_rx_function(eth_dev);
1169
1170                 return 0;
1171         }
1172
1173         rte_eth_copy_pci_info(eth_dev, pci_dev);
1174         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1175
1176         /* Vendor and Device ID need to be set before init of shared code */
1177         hw->device_id = pci_dev->id.device_id;
1178         hw->vendor_id = pci_dev->id.vendor_id;
1179         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1180         hw->allow_unsupported_sfp = 1;
1181
1182         /* Initialize the shared code (base driver) */
1183 #ifdef RTE_NIC_BYPASS
1184         diag = ixgbe_bypass_init_shared_code(hw);
1185 #else
1186         diag = ixgbe_init_shared_code(hw);
1187 #endif /* RTE_NIC_BYPASS */
1188
1189         if (diag != IXGBE_SUCCESS) {
1190                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1191                 return -EIO;
1192         }
1193
1194         /* pick up the PCI bus settings for reporting later */
1195         ixgbe_get_bus_info(hw);
1196
1197         /* Unlock any pending hardware semaphore */
1198         ixgbe_swfw_lock_reset(hw);
1199
1200         /* Initialize DCB configuration*/
1201         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1202         ixgbe_dcb_init(hw, dcb_config);
1203         /* Get Hardware Flow Control setting */
1204         hw->fc.requested_mode = ixgbe_fc_full;
1205         hw->fc.current_mode = ixgbe_fc_full;
1206         hw->fc.pause_time = IXGBE_FC_PAUSE;
1207         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1208                 hw->fc.low_water[i] = IXGBE_FC_LO;
1209                 hw->fc.high_water[i] = IXGBE_FC_HI;
1210         }
1211         hw->fc.send_xon = 1;
1212
1213         /* Make sure we have a good EEPROM before we read from it */
1214         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1215         if (diag != IXGBE_SUCCESS) {
1216                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1217                 return -EIO;
1218         }
1219
1220 #ifdef RTE_NIC_BYPASS
1221         diag = ixgbe_bypass_init_hw(hw);
1222 #else
1223         diag = ixgbe_init_hw(hw);
1224 #endif /* RTE_NIC_BYPASS */
1225
1226         /*
1227          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1228          * is called too soon after the kernel driver unbinding/binding occurs.
1229          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1230          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1231          * also called. See ixgbe_identify_phy_82599(). The reason for the
1232          * failure is not known, and only occuts when virtualisation features
1233          * are disabled in the bios. A delay of 100ms  was found to be enough by
1234          * trial-and-error, and is doubled to be safe.
1235          */
1236         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237                 rte_delay_ms(200);
1238                 diag = ixgbe_init_hw(hw);
1239         }
1240
1241         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1242                 diag = IXGBE_SUCCESS;
1243
1244         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1245                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1246                              "LOM.  Please be aware there may be issues associated "
1247                              "with your hardware.");
1248                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1249                              "please contact your Intel or hardware representative "
1250                              "who provided you with this hardware.");
1251         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1252                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1253         if (diag) {
1254                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1255                 return -EIO;
1256         }
1257
1258         /* Reset the hw statistics */
1259         ixgbe_dev_stats_reset(eth_dev);
1260
1261         /* disable interrupt */
1262         ixgbe_disable_intr(hw);
1263
1264         /* reset mappings for queue statistics hw counters*/
1265         ixgbe_reset_qstat_mappings(hw);
1266
1267         /* Allocate memory for storing MAC addresses */
1268         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1269                                                hw->mac.num_rar_entries, 0);
1270         if (eth_dev->data->mac_addrs == NULL) {
1271                 PMD_INIT_LOG(ERR,
1272                              "Failed to allocate %u bytes needed to store "
1273                              "MAC addresses",
1274                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1275                 return -ENOMEM;
1276         }
1277         /* Copy the permanent MAC address */
1278         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1279                         &eth_dev->data->mac_addrs[0]);
1280
1281         /* Allocate memory for storing hash filter MAC addresses */
1282         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1283                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1284         if (eth_dev->data->hash_mac_addrs == NULL) {
1285                 PMD_INIT_LOG(ERR,
1286                              "Failed to allocate %d bytes needed to store MAC addresses",
1287                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1288                 return -ENOMEM;
1289         }
1290
1291         /* initialize the vfta */
1292         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1293
1294         /* initialize the hw strip bitmap*/
1295         memset(hwstrip, 0, sizeof(*hwstrip));
1296
1297         /* initialize PF if max_vfs not zero */
1298         ixgbe_pf_host_init(eth_dev);
1299
1300         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1301         /* let hardware know driver is loaded */
1302         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1303         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1304         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1305         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1306         IXGBE_WRITE_FLUSH(hw);
1307
1308         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type,
1311                              (int) hw->phy.sfp_type);
1312         else
1313                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1314                              (int) hw->mac.type, (int) hw->phy.type);
1315
1316         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1317                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1318                      pci_dev->id.device_id);
1319
1320         rte_intr_callback_register(intr_handle,
1321                                    ixgbe_dev_interrupt_handler, eth_dev);
1322
1323         /* enable uio/vfio intr/eventfd mapping */
1324         rte_intr_enable(intr_handle);
1325
1326         /* enable support intr */
1327         ixgbe_enable_intr(eth_dev);
1328
1329         /* initialize filter info */
1330         memset(filter_info, 0,
1331                sizeof(struct ixgbe_filter_info));
1332
1333         /* initialize 5tuple filter list */
1334         TAILQ_INIT(&filter_info->fivetuple_list);
1335
1336         /* initialize flow director filter list & hash */
1337         ixgbe_fdir_filter_init(eth_dev);
1338
1339         /* initialize l2 tunnel filter list & hash */
1340         ixgbe_l2_tn_filter_init(eth_dev);
1341
1342         TAILQ_INIT(&filter_ntuple_list);
1343         TAILQ_INIT(&filter_ethertype_list);
1344         TAILQ_INIT(&filter_syn_list);
1345         TAILQ_INIT(&filter_fdir_list);
1346         TAILQ_INIT(&filter_l2_tunnel_list);
1347         TAILQ_INIT(&ixgbe_flow_list);
1348
1349         return 0;
1350 }
1351
1352 static int
1353 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1356         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1357         struct ixgbe_hw *hw;
1358
1359         PMD_INIT_FUNC_TRACE();
1360
1361         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1362                 return -EPERM;
1363
1364         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1365
1366         if (hw->adapter_stopped == 0)
1367                 ixgbe_dev_close(eth_dev);
1368
1369         eth_dev->dev_ops = NULL;
1370         eth_dev->rx_pkt_burst = NULL;
1371         eth_dev->tx_pkt_burst = NULL;
1372
1373         /* Unlock any pending hardware semaphore */
1374         ixgbe_swfw_lock_reset(hw);
1375
1376         /* disable uio intr before callback unregister */
1377         rte_intr_disable(intr_handle);
1378         rte_intr_callback_unregister(intr_handle,
1379                                      ixgbe_dev_interrupt_handler, eth_dev);
1380
1381         /* uninitialize PF if max_vfs not zero */
1382         ixgbe_pf_host_uninit(eth_dev);
1383
1384         rte_free(eth_dev->data->mac_addrs);
1385         eth_dev->data->mac_addrs = NULL;
1386
1387         rte_free(eth_dev->data->hash_mac_addrs);
1388         eth_dev->data->hash_mac_addrs = NULL;
1389
1390         /* remove all the fdir filters & hash */
1391         ixgbe_fdir_filter_uninit(eth_dev);
1392
1393         /* remove all the L2 tunnel filters & hash */
1394         ixgbe_l2_tn_filter_uninit(eth_dev);
1395
1396         /* Remove all ntuple filters of the device */
1397         ixgbe_ntuple_filter_uninit(eth_dev);
1398
1399         /* clear all the filters list */
1400         ixgbe_filterlist_flush();
1401
1402         return 0;
1403 }
1404
1405 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1406 {
1407         struct ixgbe_filter_info *filter_info =
1408                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1409         struct ixgbe_5tuple_filter *p_5tuple;
1410
1411         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1412                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1413                              p_5tuple,
1414                              entries);
1415                 rte_free(p_5tuple);
1416         }
1417         memset(filter_info->fivetuple_mask, 0,
1418                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1419
1420         return 0;
1421 }
1422
1423 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1424 {
1425         struct ixgbe_hw_fdir_info *fdir_info =
1426                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1427         struct ixgbe_fdir_filter *fdir_filter;
1428
1429                 if (fdir_info->hash_map)
1430                 rte_free(fdir_info->hash_map);
1431         if (fdir_info->hash_handle)
1432                 rte_hash_free(fdir_info->hash_handle);
1433
1434         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1435                 TAILQ_REMOVE(&fdir_info->fdir_list,
1436                              fdir_filter,
1437                              entries);
1438                 rte_free(fdir_filter);
1439         }
1440
1441         return 0;
1442 }
1443
1444 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1445 {
1446         struct ixgbe_l2_tn_info *l2_tn_info =
1447                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1448         struct ixgbe_l2_tn_filter *l2_tn_filter;
1449
1450         if (l2_tn_info->hash_map)
1451                 rte_free(l2_tn_info->hash_map);
1452         if (l2_tn_info->hash_handle)
1453                 rte_hash_free(l2_tn_info->hash_handle);
1454
1455         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1456                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1457                              l2_tn_filter,
1458                              entries);
1459                 rte_free(l2_tn_filter);
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1466 {
1467         struct ixgbe_hw_fdir_info *fdir_info =
1468                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1469         char fdir_hash_name[RTE_HASH_NAMESIZE];
1470         struct rte_hash_parameters fdir_hash_params = {
1471                 .name = fdir_hash_name,
1472                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1473                 .key_len = sizeof(union ixgbe_atr_input),
1474                 .hash_func = rte_hash_crc,
1475                 .hash_func_init_val = 0,
1476                 .socket_id = rte_socket_id(),
1477         };
1478
1479         TAILQ_INIT(&fdir_info->fdir_list);
1480         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1481                  "fdir_%s", eth_dev->data->name);
1482         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1483         if (!fdir_info->hash_handle) {
1484                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1485                 return -EINVAL;
1486         }
1487         fdir_info->hash_map = rte_zmalloc("ixgbe",
1488                                           sizeof(struct ixgbe_fdir_filter *) *
1489                                           IXGBE_MAX_FDIR_FILTER_NUM,
1490                                           0);
1491         if (!fdir_info->hash_map) {
1492                 PMD_INIT_LOG(ERR,
1493                              "Failed to allocate memory for fdir hash map!");
1494                 return -ENOMEM;
1495         }
1496         fdir_info->mask_added = FALSE;
1497
1498         return 0;
1499 }
1500
1501 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1502 {
1503         struct ixgbe_l2_tn_info *l2_tn_info =
1504                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1505         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1506         struct rte_hash_parameters l2_tn_hash_params = {
1507                 .name = l2_tn_hash_name,
1508                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1509                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1510                 .hash_func = rte_hash_crc,
1511                 .hash_func_init_val = 0,
1512                 .socket_id = rte_socket_id(),
1513         };
1514
1515         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1516         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1517                  "l2_tn_%s", eth_dev->data->name);
1518         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1519         if (!l2_tn_info->hash_handle) {
1520                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1521                 return -EINVAL;
1522         }
1523         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1524                                    sizeof(struct ixgbe_l2_tn_filter *) *
1525                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1526                                    0);
1527         if (!l2_tn_info->hash_map) {
1528                 PMD_INIT_LOG(ERR,
1529                         "Failed to allocate memory for L2 TN hash map!");
1530                 return -ENOMEM;
1531         }
1532         l2_tn_info->e_tag_en = FALSE;
1533         l2_tn_info->e_tag_fwd_en = FALSE;
1534         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1535
1536         return 0;
1537 }
1538 /*
1539  * Negotiate mailbox API version with the PF.
1540  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1541  * Then we try to negotiate starting with the most recent one.
1542  * If all negotiation attempts fail, then we will proceed with
1543  * the default one (ixgbe_mbox_api_10).
1544  */
1545 static void
1546 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1547 {
1548         int32_t i;
1549
1550         /* start with highest supported, proceed down */
1551         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1552                 ixgbe_mbox_api_12,
1553                 ixgbe_mbox_api_11,
1554                 ixgbe_mbox_api_10,
1555         };
1556
1557         for (i = 0;
1558                         i != RTE_DIM(sup_ver) &&
1559                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1560                         i++)
1561                 ;
1562 }
1563
1564 static void
1565 generate_random_mac_addr(struct ether_addr *mac_addr)
1566 {
1567         uint64_t random;
1568
1569         /* Set Organizationally Unique Identifier (OUI) prefix. */
1570         mac_addr->addr_bytes[0] = 0x00;
1571         mac_addr->addr_bytes[1] = 0x09;
1572         mac_addr->addr_bytes[2] = 0xC0;
1573         /* Force indication of locally assigned MAC address. */
1574         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1575         /* Generate the last 3 bytes of the MAC address with a random number. */
1576         random = rte_rand();
1577         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1578 }
1579
1580 /*
1581  * Virtual Function device init
1582  */
1583 static int
1584 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1585 {
1586         int diag;
1587         uint32_t tc, tcs;
1588         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1589         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1590         struct ixgbe_hw *hw =
1591                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1592         struct ixgbe_vfta *shadow_vfta =
1593                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1594         struct ixgbe_hwstrip *hwstrip =
1595                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1596         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1597
1598         PMD_INIT_FUNC_TRACE();
1599
1600         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1601         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1602         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1603
1604         /* for secondary processes, we don't initialise any further as primary
1605          * has already done this work. Only check we don't need a different
1606          * RX function
1607          */
1608         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1609                 struct ixgbe_tx_queue *txq;
1610                 /* TX queue function in primary, set by last queue initialized
1611                  * Tx queue may not initialized by primary process
1612                  */
1613                 if (eth_dev->data->tx_queues) {
1614                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1615                         ixgbe_set_tx_function(eth_dev, txq);
1616                 } else {
1617                         /* Use default TX function if we get here */
1618                         PMD_INIT_LOG(NOTICE,
1619                                      "No TX queues configured yet. Using default TX function.");
1620                 }
1621
1622                 ixgbe_set_rx_function(eth_dev);
1623
1624                 return 0;
1625         }
1626
1627         rte_eth_copy_pci_info(eth_dev, pci_dev);
1628         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1629
1630         hw->device_id = pci_dev->id.device_id;
1631         hw->vendor_id = pci_dev->id.vendor_id;
1632         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1633
1634         /* initialize the vfta */
1635         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1636
1637         /* initialize the hw strip bitmap*/
1638         memset(hwstrip, 0, sizeof(*hwstrip));
1639
1640         /* Initialize the shared code (base driver) */
1641         diag = ixgbe_init_shared_code(hw);
1642         if (diag != IXGBE_SUCCESS) {
1643                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1644                 return -EIO;
1645         }
1646
1647         /* init_mailbox_params */
1648         hw->mbx.ops.init_params(hw);
1649
1650         /* Reset the hw statistics */
1651         ixgbevf_dev_stats_reset(eth_dev);
1652
1653         /* Disable the interrupts for VF */
1654         ixgbevf_intr_disable(hw);
1655
1656         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1657         diag = hw->mac.ops.reset_hw(hw);
1658
1659         /*
1660          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1661          * the underlying PF driver has not assigned a MAC address to the VF.
1662          * In this case, assign a random MAC address.
1663          */
1664         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1665                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1666                 return diag;
1667         }
1668
1669         /* negotiate mailbox API version to use with the PF. */
1670         ixgbevf_negotiate_api(hw);
1671
1672         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1673         ixgbevf_get_queues(hw, &tcs, &tc);
1674
1675         /* Allocate memory for storing MAC addresses */
1676         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1677                                                hw->mac.num_rar_entries, 0);
1678         if (eth_dev->data->mac_addrs == NULL) {
1679                 PMD_INIT_LOG(ERR,
1680                              "Failed to allocate %u bytes needed to store "
1681                              "MAC addresses",
1682                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1683                 return -ENOMEM;
1684         }
1685
1686         /* Generate a random MAC address, if none was assigned by PF. */
1687         if (is_zero_ether_addr(perm_addr)) {
1688                 generate_random_mac_addr(perm_addr);
1689                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1690                 if (diag) {
1691                         rte_free(eth_dev->data->mac_addrs);
1692                         eth_dev->data->mac_addrs = NULL;
1693                         return diag;
1694                 }
1695                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1696                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1697                              "%02x:%02x:%02x:%02x:%02x:%02x",
1698                              perm_addr->addr_bytes[0],
1699                              perm_addr->addr_bytes[1],
1700                              perm_addr->addr_bytes[2],
1701                              perm_addr->addr_bytes[3],
1702                              perm_addr->addr_bytes[4],
1703                              perm_addr->addr_bytes[5]);
1704         }
1705
1706         /* Copy the permanent MAC address */
1707         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1708
1709         /* reset the hardware with the new settings */
1710         diag = hw->mac.ops.start_hw(hw);
1711         switch (diag) {
1712         case  0:
1713                 break;
1714
1715         default:
1716                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1717                 return -EIO;
1718         }
1719
1720         rte_intr_callback_register(intr_handle,
1721                                    ixgbevf_dev_interrupt_handler, eth_dev);
1722         rte_intr_enable(intr_handle);
1723         ixgbevf_intr_enable(hw);
1724
1725         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1726                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1727                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1728
1729         return 0;
1730 }
1731
1732 /* Virtual Function device uninit */
1733
1734 static int
1735 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1736 {
1737         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1738         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1739         struct ixgbe_hw *hw;
1740
1741         PMD_INIT_FUNC_TRACE();
1742
1743         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1744                 return -EPERM;
1745
1746         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1747
1748         if (hw->adapter_stopped == 0)
1749                 ixgbevf_dev_close(eth_dev);
1750
1751         eth_dev->dev_ops = NULL;
1752         eth_dev->rx_pkt_burst = NULL;
1753         eth_dev->tx_pkt_burst = NULL;
1754
1755         /* Disable the interrupts for VF */
1756         ixgbevf_intr_disable(hw);
1757
1758         rte_free(eth_dev->data->mac_addrs);
1759         eth_dev->data->mac_addrs = NULL;
1760
1761         rte_intr_disable(intr_handle);
1762         rte_intr_callback_unregister(intr_handle,
1763                                      ixgbevf_dev_interrupt_handler, eth_dev);
1764
1765         return 0;
1766 }
1767
1768 static struct eth_driver rte_ixgbe_pmd = {
1769         .pci_drv = {
1770                 .id_table = pci_id_ixgbe_map,
1771                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1772                 .probe = rte_eth_dev_pci_probe,
1773                 .remove = rte_eth_dev_pci_remove,
1774         },
1775         .eth_dev_init = eth_ixgbe_dev_init,
1776         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1777         .dev_private_size = sizeof(struct ixgbe_adapter),
1778 };
1779
1780 /*
1781  * virtual function driver struct
1782  */
1783 static struct eth_driver rte_ixgbevf_pmd = {
1784         .pci_drv = {
1785                 .id_table = pci_id_ixgbevf_map,
1786                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1787                 .probe = rte_eth_dev_pci_probe,
1788                 .remove = rte_eth_dev_pci_remove,
1789         },
1790         .eth_dev_init = eth_ixgbevf_dev_init,
1791         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1792         .dev_private_size = sizeof(struct ixgbe_adapter),
1793 };
1794
1795 static int
1796 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1797 {
1798         struct ixgbe_hw *hw =
1799                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1800         struct ixgbe_vfta *shadow_vfta =
1801                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1802         uint32_t vfta;
1803         uint32_t vid_idx;
1804         uint32_t vid_bit;
1805
1806         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1807         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1808         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1809         if (on)
1810                 vfta |= vid_bit;
1811         else
1812                 vfta &= ~vid_bit;
1813         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1814
1815         /* update local VFTA copy */
1816         shadow_vfta->vfta[vid_idx] = vfta;
1817
1818         return 0;
1819 }
1820
1821 static void
1822 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1823 {
1824         if (on)
1825                 ixgbe_vlan_hw_strip_enable(dev, queue);
1826         else
1827                 ixgbe_vlan_hw_strip_disable(dev, queue);
1828 }
1829
1830 static int
1831 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1832                     enum rte_vlan_type vlan_type,
1833                     uint16_t tpid)
1834 {
1835         struct ixgbe_hw *hw =
1836                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1837         int ret = 0;
1838         uint32_t reg;
1839         uint32_t qinq;
1840
1841         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1842         qinq &= IXGBE_DMATXCTL_GDV;
1843
1844         switch (vlan_type) {
1845         case ETH_VLAN_TYPE_INNER:
1846                 if (qinq) {
1847                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1848                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1849                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1850                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1851                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1852                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1853                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1854                 } else {
1855                         ret = -ENOTSUP;
1856                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1857                                     " by single VLAN");
1858                 }
1859                 break;
1860         case ETH_VLAN_TYPE_OUTER:
1861                 if (qinq) {
1862                         /* Only the high 16-bits is valid */
1863                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1864                                         IXGBE_EXVET_VET_EXT_SHIFT);
1865                 } else {
1866                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1867                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1868                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1869                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1870                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1871                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1872                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1873                 }
1874
1875                 break;
1876         default:
1877                 ret = -EINVAL;
1878                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1879                 break;
1880         }
1881
1882         return ret;
1883 }
1884
1885 void
1886 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1887 {
1888         struct ixgbe_hw *hw =
1889                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         uint32_t vlnctrl;
1891
1892         PMD_INIT_FUNC_TRACE();
1893
1894         /* Filter Table Disable */
1895         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1897
1898         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1899 }
1900
1901 void
1902 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1903 {
1904         struct ixgbe_hw *hw =
1905                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1906         struct ixgbe_vfta *shadow_vfta =
1907                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1908         uint32_t vlnctrl;
1909         uint16_t i;
1910
1911         PMD_INIT_FUNC_TRACE();
1912
1913         /* Filter Table Enable */
1914         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1915         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1916         vlnctrl |= IXGBE_VLNCTRL_VFE;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1919
1920         /* write whatever is in local vfta copy */
1921         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1922                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1923 }
1924
1925 static void
1926 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1927 {
1928         struct ixgbe_hwstrip *hwstrip =
1929                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1930         struct ixgbe_rx_queue *rxq;
1931
1932         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1933                 return;
1934
1935         if (on)
1936                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1937         else
1938                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1939
1940         if (queue >= dev->data->nb_rx_queues)
1941                 return;
1942
1943         rxq = dev->data->rx_queues[queue];
1944
1945         if (on)
1946                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1947         else
1948                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1949 }
1950
1951 static void
1952 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1953 {
1954         struct ixgbe_hw *hw =
1955                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1956         uint32_t ctrl;
1957
1958         PMD_INIT_FUNC_TRACE();
1959
1960         if (hw->mac.type == ixgbe_mac_82598EB) {
1961                 /* No queue level support */
1962                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1963                 return;
1964         }
1965
1966         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1967         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1968         ctrl &= ~IXGBE_RXDCTL_VME;
1969         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1970
1971         /* record those setting for HW strip per queue */
1972         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1973 }
1974
1975 static void
1976 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1977 {
1978         struct ixgbe_hw *hw =
1979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1980         uint32_t ctrl;
1981
1982         PMD_INIT_FUNC_TRACE();
1983
1984         if (hw->mac.type == ixgbe_mac_82598EB) {
1985                 /* No queue level supported */
1986                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1987                 return;
1988         }
1989
1990         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1991         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1992         ctrl |= IXGBE_RXDCTL_VME;
1993         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1994
1995         /* record those setting for HW strip per queue */
1996         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1997 }
1998
1999 void
2000 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005         uint16_t i;
2006         struct ixgbe_rx_queue *rxq;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2012                 ctrl &= ~IXGBE_VLNCTRL_VME;
2013                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2014         } else {
2015                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2016                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2017                         rxq = dev->data->rx_queues[i];
2018                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2019                         ctrl &= ~IXGBE_RXDCTL_VME;
2020                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2021
2022                         /* record those setting for HW strip per queue */
2023                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2024                 }
2025         }
2026 }
2027
2028 void
2029 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2030 {
2031         struct ixgbe_hw *hw =
2032                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         uint32_t ctrl;
2034         uint16_t i;
2035         struct ixgbe_rx_queue *rxq;
2036
2037         PMD_INIT_FUNC_TRACE();
2038
2039         if (hw->mac.type == ixgbe_mac_82598EB) {
2040                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2041                 ctrl |= IXGBE_VLNCTRL_VME;
2042                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2043         } else {
2044                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2045                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2046                         rxq = dev->data->rx_queues[i];
2047                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2048                         ctrl |= IXGBE_RXDCTL_VME;
2049                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2050
2051                         /* record those setting for HW strip per queue */
2052                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2053                 }
2054         }
2055 }
2056
2057 static void
2058 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2059 {
2060         struct ixgbe_hw *hw =
2061                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2062         uint32_t ctrl;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         /* DMATXCTRL: Geric Double VLAN Disable */
2067         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2068         ctrl &= ~IXGBE_DMATXCTL_GDV;
2069         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2070
2071         /* CTRL_EXT: Global Double VLAN Disable */
2072         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2073         ctrl &= ~IXGBE_EXTENDED_VLAN;
2074         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2075
2076 }
2077
2078 static void
2079 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2080 {
2081         struct ixgbe_hw *hw =
2082                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083         uint32_t ctrl;
2084
2085         PMD_INIT_FUNC_TRACE();
2086
2087         /* DMATXCTRL: Geric Double VLAN Enable */
2088         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089         ctrl |= IXGBE_DMATXCTL_GDV;
2090         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2091
2092         /* CTRL_EXT: Global Double VLAN Enable */
2093         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094         ctrl |= IXGBE_EXTENDED_VLAN;
2095         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2096
2097         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2098         if (hw->mac.type == ixgbe_mac_X550 ||
2099             hw->mac.type == ixgbe_mac_X550EM_x ||
2100             hw->mac.type == ixgbe_mac_X550EM_a) {
2101                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2102                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2103                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2104         }
2105
2106         /*
2107          * VET EXT field in the EXVET register = 0x8100 by default
2108          * So no need to change. Same to VT field of DMATXCTL register
2109          */
2110 }
2111
2112 static void
2113 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2114 {
2115         if (mask & ETH_VLAN_STRIP_MASK) {
2116                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2117                         ixgbe_vlan_hw_strip_enable_all(dev);
2118                 else
2119                         ixgbe_vlan_hw_strip_disable_all(dev);
2120         }
2121
2122         if (mask & ETH_VLAN_FILTER_MASK) {
2123                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2124                         ixgbe_vlan_hw_filter_enable(dev);
2125                 else
2126                         ixgbe_vlan_hw_filter_disable(dev);
2127         }
2128
2129         if (mask & ETH_VLAN_EXTEND_MASK) {
2130                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2131                         ixgbe_vlan_hw_extend_enable(dev);
2132                 else
2133                         ixgbe_vlan_hw_extend_disable(dev);
2134         }
2135 }
2136
2137 static void
2138 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2139 {
2140         struct ixgbe_hw *hw =
2141                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2142         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2143         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2144
2145         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2146         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2147 }
2148
2149 static int
2150 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2151 {
2152         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2153
2154         switch (nb_rx_q) {
2155         case 1:
2156         case 2:
2157                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2158                 break;
2159         case 4:
2160                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2161                 break;
2162         default:
2163                 return -EINVAL;
2164         }
2165
2166         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2167         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2168
2169         return 0;
2170 }
2171
2172 static int
2173 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2174 {
2175         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2176         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2177         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2178         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2179
2180         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2181                 /* check multi-queue mode */
2182                 switch (dev_conf->rxmode.mq_mode) {
2183                 case ETH_MQ_RX_VMDQ_DCB:
2184                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2185                         break;
2186                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2187                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2188                         PMD_INIT_LOG(ERR, "SRIOV active,"
2189                                         " unsupported mq_mode rx %d.",
2190                                         dev_conf->rxmode.mq_mode);
2191                         return -EINVAL;
2192                 case ETH_MQ_RX_RSS:
2193                 case ETH_MQ_RX_VMDQ_RSS:
2194                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2195                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2196                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2197                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2198                                                 " invalid queue number"
2199                                                 " for VMDQ RSS, allowed"
2200                                                 " value are 1, 2 or 4.");
2201                                         return -EINVAL;
2202                                 }
2203                         break;
2204                 case ETH_MQ_RX_VMDQ_ONLY:
2205                 case ETH_MQ_RX_NONE:
2206                         /* if nothing mq mode configure, use default scheme */
2207                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2208                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2209                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2210                         break;
2211                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2212                         /* SRIOV only works in VMDq enable mode */
2213                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2214                                         " wrong mq_mode rx %d.",
2215                                         dev_conf->rxmode.mq_mode);
2216                         return -EINVAL;
2217                 }
2218
2219                 switch (dev_conf->txmode.mq_mode) {
2220                 case ETH_MQ_TX_VMDQ_DCB:
2221                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2222                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2223                         break;
2224                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2225                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2226                         break;
2227                 }
2228
2229                 /* check valid queue number */
2230                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2231                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2232                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2233                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2234                                         " must be less than or equal to %d.",
2235                                         nb_rx_q, nb_tx_q,
2236                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2237                         return -EINVAL;
2238                 }
2239         } else {
2240                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2241                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2242                                           " not supported.");
2243                         return -EINVAL;
2244                 }
2245                 /* check configuration for vmdb+dcb mode */
2246                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2247                         const struct rte_eth_vmdq_dcb_conf *conf;
2248
2249                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2250                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2251                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2252                                 return -EINVAL;
2253                         }
2254                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2255                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2256                                conf->nb_queue_pools == ETH_32_POOLS)) {
2257                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2258                                                 " nb_queue_pools must be %d or %d.",
2259                                                 ETH_16_POOLS, ETH_32_POOLS);
2260                                 return -EINVAL;
2261                         }
2262                 }
2263                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2264                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2265
2266                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2267                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2268                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2269                                 return -EINVAL;
2270                         }
2271                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2272                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2273                                conf->nb_queue_pools == ETH_32_POOLS)) {
2274                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2275                                                 " nb_queue_pools != %d and"
2276                                                 " nb_queue_pools != %d.",
2277                                                 ETH_16_POOLS, ETH_32_POOLS);
2278                                 return -EINVAL;
2279                         }
2280                 }
2281
2282                 /* For DCB mode check our configuration before we go further */
2283                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2284                         const struct rte_eth_dcb_rx_conf *conf;
2285
2286                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2287                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2288                                                  IXGBE_DCB_NB_QUEUES);
2289                                 return -EINVAL;
2290                         }
2291                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2292                         if (!(conf->nb_tcs == ETH_4_TCS ||
2293                                conf->nb_tcs == ETH_8_TCS)) {
2294                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2295                                                 " and nb_tcs != %d.",
2296                                                 ETH_4_TCS, ETH_8_TCS);
2297                                 return -EINVAL;
2298                         }
2299                 }
2300
2301                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2302                         const struct rte_eth_dcb_tx_conf *conf;
2303
2304                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2305                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2306                                                  IXGBE_DCB_NB_QUEUES);
2307                                 return -EINVAL;
2308                         }
2309                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2310                         if (!(conf->nb_tcs == ETH_4_TCS ||
2311                                conf->nb_tcs == ETH_8_TCS)) {
2312                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2313                                                 " and nb_tcs != %d.",
2314                                                 ETH_4_TCS, ETH_8_TCS);
2315                                 return -EINVAL;
2316                         }
2317                 }
2318
2319                 /*
2320                  * When DCB/VT is off, maximum number of queues changes,
2321                  * except for 82598EB, which remains constant.
2322                  */
2323                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2324                                 hw->mac.type != ixgbe_mac_82598EB) {
2325                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2326                                 PMD_INIT_LOG(ERR,
2327                                              "Neither VT nor DCB are enabled, "
2328                                              "nb_tx_q > %d.",
2329                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2330                                 return -EINVAL;
2331                         }
2332                 }
2333         }
2334         return 0;
2335 }
2336
2337 static int
2338 ixgbe_dev_configure(struct rte_eth_dev *dev)
2339 {
2340         struct ixgbe_interrupt *intr =
2341                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2342         struct ixgbe_adapter *adapter =
2343                 (struct ixgbe_adapter *)dev->data->dev_private;
2344         int ret;
2345
2346         PMD_INIT_FUNC_TRACE();
2347         /* multipe queue mode checking */
2348         ret  = ixgbe_check_mq_mode(dev);
2349         if (ret != 0) {
2350                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2351                             ret);
2352                 return ret;
2353         }
2354
2355         /* set flag to update link status after init */
2356         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2357
2358         /*
2359          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2360          * allocation or vector Rx preconditions we will reset it.
2361          */
2362         adapter->rx_bulk_alloc_allowed = true;
2363         adapter->rx_vec_allowed = true;
2364
2365         return 0;
2366 }
2367
2368 static void
2369 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2370 {
2371         struct ixgbe_hw *hw =
2372                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2373         struct ixgbe_interrupt *intr =
2374                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2375         uint32_t gpie;
2376
2377         /* only set up it on X550EM_X */
2378         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2379                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2380                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2381                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2382                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2383                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2384         }
2385 }
2386
2387 /*
2388  * Configure device link speed and setup link.
2389  * It returns 0 on success.
2390  */
2391 static int
2392 ixgbe_dev_start(struct rte_eth_dev *dev)
2393 {
2394         struct ixgbe_hw *hw =
2395                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396         struct ixgbe_vf_info *vfinfo =
2397                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2398         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2399         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2400         uint32_t intr_vector = 0;
2401         int err, link_up = 0, negotiate = 0;
2402         uint32_t speed = 0;
2403         int mask = 0;
2404         int status;
2405         uint16_t vf, idx;
2406         uint32_t *link_speeds;
2407
2408         PMD_INIT_FUNC_TRACE();
2409
2410         /* IXGBE devices don't support:
2411         *    - half duplex (checked afterwards for valid speeds)
2412         *    - fixed speed: TODO implement
2413         */
2414         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2415                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2416                              dev->data->port_id);
2417                 return -EINVAL;
2418         }
2419
2420         /* disable uio/vfio intr/eventfd mapping */
2421         rte_intr_disable(intr_handle);
2422
2423         /* stop adapter */
2424         hw->adapter_stopped = 0;
2425         ixgbe_stop_adapter(hw);
2426
2427         /* reinitialize adapter
2428          * this calls reset and start
2429          */
2430         status = ixgbe_pf_reset_hw(hw);
2431         if (status != 0)
2432                 return -1;
2433         hw->mac.ops.start_hw(hw);
2434         hw->mac.get_link_status = true;
2435
2436         /* configure PF module if SRIOV enabled */
2437         ixgbe_pf_host_configure(dev);
2438
2439         ixgbe_dev_phy_intr_setup(dev);
2440
2441         /* check and configure queue intr-vector mapping */
2442         if ((rte_intr_cap_multiple(intr_handle) ||
2443              !RTE_ETH_DEV_SRIOV(dev).active) &&
2444             dev->data->dev_conf.intr_conf.rxq != 0) {
2445                 intr_vector = dev->data->nb_rx_queues;
2446                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2447                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2448                                         IXGBE_MAX_INTR_QUEUE_NUM);
2449                         return -ENOTSUP;
2450                 }
2451                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2452                         return -1;
2453         }
2454
2455         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2456                 intr_handle->intr_vec =
2457                         rte_zmalloc("intr_vec",
2458                                     dev->data->nb_rx_queues * sizeof(int), 0);
2459                 if (intr_handle->intr_vec == NULL) {
2460                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2461                                      " intr_vec", dev->data->nb_rx_queues);
2462                         return -ENOMEM;
2463                 }
2464         }
2465
2466         /* confiugre msix for sleep until rx interrupt */
2467         ixgbe_configure_msix(dev);
2468
2469         /* initialize transmission unit */
2470         ixgbe_dev_tx_init(dev);
2471
2472         /* This can fail when allocating mbufs for descriptor rings */
2473         err = ixgbe_dev_rx_init(dev);
2474         if (err) {
2475                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2476                 goto error;
2477         }
2478
2479     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2480                 ETH_VLAN_EXTEND_MASK;
2481         ixgbe_vlan_offload_set(dev, mask);
2482
2483         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2484                 /* Enable vlan filtering for VMDq */
2485                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2486         }
2487
2488         /* Configure DCB hw */
2489         ixgbe_configure_dcb(dev);
2490
2491         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2492                 err = ixgbe_fdir_configure(dev);
2493                 if (err)
2494                         goto error;
2495         }
2496
2497         /* Restore vf rate limit */
2498         if (vfinfo != NULL) {
2499                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2500                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2501                                 if (vfinfo[vf].tx_rate[idx] != 0)
2502                                         rte_pmd_ixgbe_set_vf_rate_limit(
2503                                                 dev->data->port_id, vf,
2504                                                 vfinfo[vf].tx_rate[idx],
2505                                                 1 << idx);
2506         }
2507
2508         ixgbe_restore_statistics_mapping(dev);
2509
2510         err = ixgbe_dev_rxtx_start(dev);
2511         if (err < 0) {
2512                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2513                 goto error;
2514         }
2515
2516         /* Skip link setup if loopback mode is enabled for 82599. */
2517         if (hw->mac.type == ixgbe_mac_82599EB &&
2518                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2519                 goto skip_link_setup;
2520
2521         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2522                 err = hw->mac.ops.setup_sfp(hw);
2523                 if (err)
2524                         goto error;
2525         }
2526
2527         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2528                 /* Turn on the copper */
2529                 ixgbe_set_phy_power(hw, true);
2530         } else {
2531                 /* Turn on the laser */
2532                 ixgbe_enable_tx_laser(hw);
2533         }
2534
2535         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2536         if (err)
2537                 goto error;
2538         dev->data->dev_link.link_status = link_up;
2539
2540         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2541         if (err)
2542                 goto error;
2543
2544         link_speeds = &dev->data->dev_conf.link_speeds;
2545         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2546                         ETH_LINK_SPEED_10G)) {
2547                 PMD_INIT_LOG(ERR, "Invalid link setting");
2548                 goto error;
2549         }
2550
2551         speed = 0x0;
2552         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2553                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2554                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2555                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2556         } else {
2557                 if (*link_speeds & ETH_LINK_SPEED_10G)
2558                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2559                 if (*link_speeds & ETH_LINK_SPEED_1G)
2560                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2561                 if (*link_speeds & ETH_LINK_SPEED_100M)
2562                         speed |= IXGBE_LINK_SPEED_100_FULL;
2563         }
2564
2565         err = ixgbe_setup_link(hw, speed, link_up);
2566         if (err)
2567                 goto error;
2568
2569 skip_link_setup:
2570
2571         if (rte_intr_allow_others(intr_handle)) {
2572                 /* check if lsc interrupt is enabled */
2573                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2574                         ixgbe_dev_lsc_interrupt_setup(dev);
2575                 ixgbe_dev_macsec_interrupt_setup(dev);
2576         } else {
2577                 rte_intr_callback_unregister(intr_handle,
2578                                              ixgbe_dev_interrupt_handler, dev);
2579                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2580                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2581                                      " no intr multiplex");
2582         }
2583
2584         /* check if rxq interrupt is enabled */
2585         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2586             rte_intr_dp_is_en(intr_handle))
2587                 ixgbe_dev_rxq_interrupt_setup(dev);
2588
2589         /* enable uio/vfio intr/eventfd mapping */
2590         rte_intr_enable(intr_handle);
2591
2592         /* resume enabled intr since hw reset */
2593         ixgbe_enable_intr(dev);
2594         ixgbe_l2_tunnel_conf(dev);
2595         ixgbe_filter_restore(dev);
2596
2597         return 0;
2598
2599 error:
2600         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2601         ixgbe_dev_clear_queues(dev);
2602         return -EIO;
2603 }
2604
2605 /*
2606  * Stop device: disable rx and tx functions to allow for reconfiguring.
2607  */
2608 static void
2609 ixgbe_dev_stop(struct rte_eth_dev *dev)
2610 {
2611         struct rte_eth_link link;
2612         struct ixgbe_hw *hw =
2613                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2614         struct ixgbe_vf_info *vfinfo =
2615                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2616         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2617         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2618         int vf;
2619
2620         PMD_INIT_FUNC_TRACE();
2621
2622         /* disable interrupts */
2623         ixgbe_disable_intr(hw);
2624
2625         /* reset the NIC */
2626         ixgbe_pf_reset_hw(hw);
2627         hw->adapter_stopped = 0;
2628
2629         /* stop adapter */
2630         ixgbe_stop_adapter(hw);
2631
2632         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2633                 vfinfo[vf].clear_to_send = false;
2634
2635         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2636                 /* Turn off the copper */
2637                 ixgbe_set_phy_power(hw, false);
2638         } else {
2639                 /* Turn off the laser */
2640                 ixgbe_disable_tx_laser(hw);
2641         }
2642
2643         ixgbe_dev_clear_queues(dev);
2644
2645         /* Clear stored conf */
2646         dev->data->scattered_rx = 0;
2647         dev->data->lro = 0;
2648
2649         /* Clear recorded link status */
2650         memset(&link, 0, sizeof(link));
2651         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2652
2653         if (!rte_intr_allow_others(intr_handle))
2654                 /* resume to the default handler */
2655                 rte_intr_callback_register(intr_handle,
2656                                            ixgbe_dev_interrupt_handler,
2657                                            (void *)dev);
2658
2659         /* Clean datapath event and queue/vec mapping */
2660         rte_intr_efd_disable(intr_handle);
2661         if (intr_handle->intr_vec != NULL) {
2662                 rte_free(intr_handle->intr_vec);
2663                 intr_handle->intr_vec = NULL;
2664         }
2665 }
2666
2667 /*
2668  * Set device link up: enable tx.
2669  */
2670 static int
2671 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2672 {
2673         struct ixgbe_hw *hw =
2674                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2675         if (hw->mac.type == ixgbe_mac_82599EB) {
2676 #ifdef RTE_NIC_BYPASS
2677                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2678                         /* Not suported in bypass mode */
2679                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2680                                      "by device id 0x%x", hw->device_id);
2681                         return -ENOTSUP;
2682                 }
2683 #endif
2684         }
2685
2686         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2687                 /* Turn on the copper */
2688                 ixgbe_set_phy_power(hw, true);
2689         } else {
2690                 /* Turn on the laser */
2691                 ixgbe_enable_tx_laser(hw);
2692         }
2693
2694         return 0;
2695 }
2696
2697 /*
2698  * Set device link down: disable tx.
2699  */
2700 static int
2701 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2702 {
2703         struct ixgbe_hw *hw =
2704                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2705         if (hw->mac.type == ixgbe_mac_82599EB) {
2706 #ifdef RTE_NIC_BYPASS
2707                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2708                         /* Not suported in bypass mode */
2709                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2710                                      "by device id 0x%x", hw->device_id);
2711                         return -ENOTSUP;
2712                 }
2713 #endif
2714         }
2715
2716         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2717                 /* Turn off the copper */
2718                 ixgbe_set_phy_power(hw, false);
2719         } else {
2720                 /* Turn off the laser */
2721                 ixgbe_disable_tx_laser(hw);
2722         }
2723
2724         return 0;
2725 }
2726
2727 /*
2728  * Reest and stop device.
2729  */
2730 static void
2731 ixgbe_dev_close(struct rte_eth_dev *dev)
2732 {
2733         struct ixgbe_hw *hw =
2734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735
2736         PMD_INIT_FUNC_TRACE();
2737
2738         ixgbe_pf_reset_hw(hw);
2739
2740         ixgbe_dev_stop(dev);
2741         hw->adapter_stopped = 1;
2742
2743         ixgbe_dev_free_queues(dev);
2744
2745         ixgbe_disable_pcie_master(hw);
2746
2747         /* reprogram the RAR[0] in case user changed it. */
2748         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2749 }
2750
2751 static void
2752 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2753                            struct ixgbe_hw_stats *hw_stats,
2754                            struct ixgbe_macsec_stats *macsec_stats,
2755                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2756                            uint64_t *total_qprc, uint64_t *total_qprdc)
2757 {
2758         uint32_t bprc, lxon, lxoff, total;
2759         uint32_t delta_gprc = 0;
2760         unsigned i;
2761         /* Workaround for RX byte count not including CRC bytes when CRC
2762          * strip is enabled. CRC bytes are removed from counters when crc_strip
2763          * is disabled.
2764          */
2765         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2766                         IXGBE_HLREG0_RXCRCSTRP);
2767
2768         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2769         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2770         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2771         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2772
2773         for (i = 0; i < 8; i++) {
2774                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2775
2776                 /* global total per queue */
2777                 hw_stats->mpc[i] += mp;
2778                 /* Running comprehensive total for stats display */
2779                 *total_missed_rx += hw_stats->mpc[i];
2780                 if (hw->mac.type == ixgbe_mac_82598EB) {
2781                         hw_stats->rnbc[i] +=
2782                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2783                         hw_stats->pxonrxc[i] +=
2784                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2785                         hw_stats->pxoffrxc[i] +=
2786                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2787                 } else {
2788                         hw_stats->pxonrxc[i] +=
2789                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2790                         hw_stats->pxoffrxc[i] +=
2791                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2792                         hw_stats->pxon2offc[i] +=
2793                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2794                 }
2795                 hw_stats->pxontxc[i] +=
2796                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2797                 hw_stats->pxofftxc[i] +=
2798                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2799         }
2800         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2801                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2802                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2803                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2804
2805                 delta_gprc += delta_qprc;
2806
2807                 hw_stats->qprc[i] += delta_qprc;
2808                 hw_stats->qptc[i] += delta_qptc;
2809
2810                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2811                 hw_stats->qbrc[i] +=
2812                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2813                 if (crc_strip == 0)
2814                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2815
2816                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2817                 hw_stats->qbtc[i] +=
2818                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2819
2820                 hw_stats->qprdc[i] += delta_qprdc;
2821                 *total_qprdc += hw_stats->qprdc[i];
2822
2823                 *total_qprc += hw_stats->qprc[i];
2824                 *total_qbrc += hw_stats->qbrc[i];
2825         }
2826         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2827         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2828         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2829
2830         /*
2831          * An errata states that gprc actually counts good + missed packets:
2832          * Workaround to set gprc to summated queue packet receives
2833          */
2834         hw_stats->gprc = *total_qprc;
2835
2836         if (hw->mac.type != ixgbe_mac_82598EB) {
2837                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2838                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2839                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2840                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2841                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2842                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2843                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2844                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2845         } else {
2846                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2847                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2848                 /* 82598 only has a counter in the high register */
2849                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2850                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2851                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2852         }
2853         uint64_t old_tpr = hw_stats->tpr;
2854
2855         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2856         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2857
2858         if (crc_strip == 0)
2859                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2860
2861         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2862         hw_stats->gptc += delta_gptc;
2863         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2864         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2865
2866         /*
2867          * Workaround: mprc hardware is incorrectly counting
2868          * broadcasts, so for now we subtract those.
2869          */
2870         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2871         hw_stats->bprc += bprc;
2872         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2873         if (hw->mac.type == ixgbe_mac_82598EB)
2874                 hw_stats->mprc -= bprc;
2875
2876         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2877         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2878         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2879         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2880         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2881         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2882
2883         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2884         hw_stats->lxontxc += lxon;
2885         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2886         hw_stats->lxofftxc += lxoff;
2887         total = lxon + lxoff;
2888
2889         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2890         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2891         hw_stats->gptc -= total;
2892         hw_stats->mptc -= total;
2893         hw_stats->ptc64 -= total;
2894         hw_stats->gotc -= total * ETHER_MIN_LEN;
2895
2896         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2897         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2898         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2899         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2900         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2901         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2902         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2903         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2904         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2905         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2906         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2907         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2908         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2909         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2910         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2911         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2912         /* Only read FCOE on 82599 */
2913         if (hw->mac.type != ixgbe_mac_82598EB) {
2914                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2915                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2916                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2917                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2918                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2919         }
2920
2921         /* Flow Director Stats registers */
2922         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2923         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2924
2925         /* MACsec Stats registers */
2926         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2927         macsec_stats->out_pkts_encrypted +=
2928                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2929         macsec_stats->out_pkts_protected +=
2930                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2931         macsec_stats->out_octets_encrypted +=
2932                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2933         macsec_stats->out_octets_protected +=
2934                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2935         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2936         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2937         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2938         macsec_stats->in_pkts_unknownsci +=
2939                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2940         macsec_stats->in_octets_decrypted +=
2941                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2942         macsec_stats->in_octets_validated +=
2943                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2944         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2945         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2946         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2947         for (i = 0; i < 2; i++) {
2948                 macsec_stats->in_pkts_ok +=
2949                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2950                 macsec_stats->in_pkts_invalid +=
2951                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2952                 macsec_stats->in_pkts_notvalid +=
2953                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2954         }
2955         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2956         macsec_stats->in_pkts_notusingsa +=
2957                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2958 }
2959
2960 /*
2961  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2962  */
2963 static void
2964 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2965 {
2966         struct ixgbe_hw *hw =
2967                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2968         struct ixgbe_hw_stats *hw_stats =
2969                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2970         struct ixgbe_macsec_stats *macsec_stats =
2971                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2972                                 dev->data->dev_private);
2973         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2974         unsigned i;
2975
2976         total_missed_rx = 0;
2977         total_qbrc = 0;
2978         total_qprc = 0;
2979         total_qprdc = 0;
2980
2981         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2982                         &total_qbrc, &total_qprc, &total_qprdc);
2983
2984         if (stats == NULL)
2985                 return;
2986
2987         /* Fill out the rte_eth_stats statistics structure */
2988         stats->ipackets = total_qprc;
2989         stats->ibytes = total_qbrc;
2990         stats->opackets = hw_stats->gptc;
2991         stats->obytes = hw_stats->gotc;
2992
2993         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2994                 stats->q_ipackets[i] = hw_stats->qprc[i];
2995                 stats->q_opackets[i] = hw_stats->qptc[i];
2996                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2997                 stats->q_obytes[i] = hw_stats->qbtc[i];
2998                 stats->q_errors[i] = hw_stats->qprdc[i];
2999         }
3000
3001         /* Rx Errors */
3002         stats->imissed  = total_missed_rx;
3003         stats->ierrors  = hw_stats->crcerrs +
3004                           hw_stats->mspdc +
3005                           hw_stats->rlec +
3006                           hw_stats->ruc +
3007                           hw_stats->roc +
3008                           hw_stats->illerrc +
3009                           hw_stats->errbc +
3010                           hw_stats->rfc +
3011                           hw_stats->fccrc +
3012                           hw_stats->fclast;
3013
3014         /* Tx Errors */
3015         stats->oerrors  = 0;
3016 }
3017
3018 static void
3019 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3020 {
3021         struct ixgbe_hw_stats *stats =
3022                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3023
3024         /* HW registers are cleared on read */
3025         ixgbe_dev_stats_get(dev, NULL);
3026
3027         /* Reset software totals */
3028         memset(stats, 0, sizeof(*stats));
3029 }
3030
3031 /* This function calculates the number of xstats based on the current config */
3032 static unsigned
3033 ixgbe_xstats_calc_num(void) {
3034         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3035                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3036                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3037 }
3038
3039 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3040         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3041 {
3042         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3043         unsigned stat, i, count;
3044
3045         if (xstats_names != NULL) {
3046                 count = 0;
3047
3048                 /* Note: limit >= cnt_stats checked upstream
3049                  * in rte_eth_xstats_names()
3050                  */
3051
3052                 /* Extended stats from ixgbe_hw_stats */
3053                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3054                         snprintf(xstats_names[count].name,
3055                                 sizeof(xstats_names[count].name),
3056                                 "%s",
3057                                 rte_ixgbe_stats_strings[i].name);
3058                         count++;
3059                 }
3060
3061                 /* MACsec Stats */
3062                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3063                         snprintf(xstats_names[count].name,
3064                                 sizeof(xstats_names[count].name),
3065                                 "%s",
3066                                 rte_ixgbe_macsec_strings[i].name);
3067                         count++;
3068                 }
3069
3070                 /* RX Priority Stats */
3071                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3072                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3073                                 snprintf(xstats_names[count].name,
3074                                         sizeof(xstats_names[count].name),
3075                                         "rx_priority%u_%s", i,
3076                                         rte_ixgbe_rxq_strings[stat].name);
3077                                 count++;
3078                         }
3079                 }
3080
3081                 /* TX Priority Stats */
3082                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3083                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3084                                 snprintf(xstats_names[count].name,
3085                                         sizeof(xstats_names[count].name),
3086                                         "tx_priority%u_%s", i,
3087                                         rte_ixgbe_txq_strings[stat].name);
3088                                 count++;
3089                         }
3090                 }
3091         }
3092         return cnt_stats;
3093 }
3094
3095 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3096         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3097 {
3098         unsigned i;
3099
3100         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3101                 return -ENOMEM;
3102
3103         if (xstats_names != NULL)
3104                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3105                         snprintf(xstats_names[i].name,
3106                                 sizeof(xstats_names[i].name),
3107                                 "%s", rte_ixgbevf_stats_strings[i].name);
3108         return IXGBEVF_NB_XSTATS;
3109 }
3110
3111 static int
3112 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3113                                          unsigned n)
3114 {
3115         struct ixgbe_hw *hw =
3116                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3117         struct ixgbe_hw_stats *hw_stats =
3118                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3119         struct ixgbe_macsec_stats *macsec_stats =
3120                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3121                                 dev->data->dev_private);
3122         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3123         unsigned i, stat, count = 0;
3124
3125         count = ixgbe_xstats_calc_num();
3126
3127         if (n < count)
3128                 return count;
3129
3130         total_missed_rx = 0;
3131         total_qbrc = 0;
3132         total_qprc = 0;
3133         total_qprdc = 0;
3134
3135         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3136                         &total_qbrc, &total_qprc, &total_qprdc);
3137
3138         /* If this is a reset xstats is NULL, and we have cleared the
3139          * registers by reading them.
3140          */
3141         if (!xstats)
3142                 return 0;
3143
3144         /* Extended stats from ixgbe_hw_stats */
3145         count = 0;
3146         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3147                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3148                                 rte_ixgbe_stats_strings[i].offset);
3149                 xstats[count].id = count;
3150                 count++;
3151         }
3152
3153         /* MACsec Stats */
3154         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3155                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3156                                 rte_ixgbe_macsec_strings[i].offset);
3157                 xstats[count].id = count;
3158                 count++;
3159         }
3160
3161         /* RX Priority Stats */
3162         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3163                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3164                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3165                                         rte_ixgbe_rxq_strings[stat].offset +
3166                                         (sizeof(uint64_t) * i));
3167                         xstats[count].id = count;
3168                         count++;
3169                 }
3170         }
3171
3172         /* TX Priority Stats */
3173         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3174                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3175                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3176                                         rte_ixgbe_txq_strings[stat].offset +
3177                                         (sizeof(uint64_t) * i));
3178                         xstats[count].id = count;
3179                         count++;
3180                 }
3181         }
3182         return count;
3183 }
3184
3185 static void
3186 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3187 {
3188         struct ixgbe_hw_stats *stats =
3189                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3190         struct ixgbe_macsec_stats *macsec_stats =
3191                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3192                                 dev->data->dev_private);
3193
3194         unsigned count = ixgbe_xstats_calc_num();
3195
3196         /* HW registers are cleared on read */
3197         ixgbe_dev_xstats_get(dev, NULL, count);
3198
3199         /* Reset software totals */
3200         memset(stats, 0, sizeof(*stats));
3201         memset(macsec_stats, 0, sizeof(*macsec_stats));
3202 }
3203
3204 static void
3205 ixgbevf_update_stats(struct rte_eth_dev *dev)
3206 {
3207         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3208         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3209                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3210
3211         /* Good Rx packet, include VF loopback */
3212         UPDATE_VF_STAT(IXGBE_VFGPRC,
3213             hw_stats->last_vfgprc, hw_stats->vfgprc);
3214
3215         /* Good Rx octets, include VF loopback */
3216         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3217             hw_stats->last_vfgorc, hw_stats->vfgorc);
3218
3219         /* Good Tx packet, include VF loopback */
3220         UPDATE_VF_STAT(IXGBE_VFGPTC,
3221             hw_stats->last_vfgptc, hw_stats->vfgptc);
3222
3223         /* Good Tx octets, include VF loopback */
3224         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3225             hw_stats->last_vfgotc, hw_stats->vfgotc);
3226
3227         /* Rx Multicst Packet */
3228         UPDATE_VF_STAT(IXGBE_VFMPRC,
3229             hw_stats->last_vfmprc, hw_stats->vfmprc);
3230 }
3231
3232 static int
3233 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3234                        unsigned n)
3235 {
3236         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3237                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3238         unsigned i;
3239
3240         if (n < IXGBEVF_NB_XSTATS)
3241                 return IXGBEVF_NB_XSTATS;
3242
3243         ixgbevf_update_stats(dev);
3244
3245         if (!xstats)
3246                 return 0;
3247
3248         /* Extended stats */
3249         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3250                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3251                         rte_ixgbevf_stats_strings[i].offset);
3252         }
3253
3254         return IXGBEVF_NB_XSTATS;
3255 }
3256
3257 static void
3258 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3259 {
3260         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3261                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3262
3263         ixgbevf_update_stats(dev);
3264
3265         if (stats == NULL)
3266                 return;
3267
3268         stats->ipackets = hw_stats->vfgprc;
3269         stats->ibytes = hw_stats->vfgorc;
3270         stats->opackets = hw_stats->vfgptc;
3271         stats->obytes = hw_stats->vfgotc;
3272 }
3273
3274 static void
3275 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3276 {
3277         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3278                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3279
3280         /* Sync HW register to the last stats */
3281         ixgbevf_dev_stats_get(dev, NULL);
3282
3283         /* reset HW current stats*/
3284         hw_stats->vfgprc = 0;
3285         hw_stats->vfgorc = 0;
3286         hw_stats->vfgptc = 0;
3287         hw_stats->vfgotc = 0;
3288 }
3289
3290 static int
3291 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3292 {
3293         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294         u16 eeprom_verh, eeprom_verl;
3295         u32 etrack_id;
3296         int ret;
3297
3298         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3299         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3300
3301         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3302         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3303
3304         ret += 1; /* add the size of '\0' */
3305         if (fw_size < (u32)ret)
3306                 return ret;
3307         else
3308                 return 0;
3309 }
3310
3311 static void
3312 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3313 {
3314         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3315         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3316         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3317
3318         dev_info->pci_dev = pci_dev;
3319         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3320         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3321         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3322                 /*
3323                  * When DCB/VT is off, maximum number of queues changes,
3324                  * except for 82598EB, which remains constant.
3325                  */
3326                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3327                                 hw->mac.type != ixgbe_mac_82598EB)
3328                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3329         }
3330         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3331         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3332         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3333         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3334         dev_info->max_vfs = pci_dev->max_vfs;
3335         if (hw->mac.type == ixgbe_mac_82598EB)
3336                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3337         else
3338                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3339         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3340         dev_info->rx_offload_capa =
3341                 DEV_RX_OFFLOAD_VLAN_STRIP |
3342                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3343                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3344                 DEV_RX_OFFLOAD_TCP_CKSUM;
3345
3346         /*
3347          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3348          * mode.
3349          */
3350         if ((hw->mac.type == ixgbe_mac_82599EB ||
3351              hw->mac.type == ixgbe_mac_X540) &&
3352             !RTE_ETH_DEV_SRIOV(dev).active)
3353                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3354
3355         if (hw->mac.type == ixgbe_mac_82599EB ||
3356             hw->mac.type == ixgbe_mac_X540)
3357                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3358
3359         if (hw->mac.type == ixgbe_mac_X550 ||
3360             hw->mac.type == ixgbe_mac_X550EM_x ||
3361             hw->mac.type == ixgbe_mac_X550EM_a)
3362                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3363
3364         dev_info->tx_offload_capa =
3365                 DEV_TX_OFFLOAD_VLAN_INSERT |
3366                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3367                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3368                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3369                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3370                 DEV_TX_OFFLOAD_TCP_TSO;
3371
3372         if (hw->mac.type == ixgbe_mac_82599EB ||
3373             hw->mac.type == ixgbe_mac_X540)
3374                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3375
3376         if (hw->mac.type == ixgbe_mac_X550 ||
3377             hw->mac.type == ixgbe_mac_X550EM_x ||
3378             hw->mac.type == ixgbe_mac_X550EM_a)
3379                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3380
3381         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3382                 .rx_thresh = {
3383                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3384                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3385                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3386                 },
3387                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3388                 .rx_drop_en = 0,
3389         };
3390
3391         dev_info->default_txconf = (struct rte_eth_txconf) {
3392                 .tx_thresh = {
3393                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3394                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3395                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3396                 },
3397                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3398                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3399                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3400                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3401         };
3402
3403         dev_info->rx_desc_lim = rx_desc_lim;
3404         dev_info->tx_desc_lim = tx_desc_lim;
3405
3406         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3407         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3408         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3409
3410         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3411         if (hw->mac.type == ixgbe_mac_X540 ||
3412             hw->mac.type == ixgbe_mac_X540_vf ||
3413             hw->mac.type == ixgbe_mac_X550 ||
3414             hw->mac.type == ixgbe_mac_X550_vf) {
3415                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3416         }
3417 }
3418
3419 static const uint32_t *
3420 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3421 {
3422         static const uint32_t ptypes[] = {
3423                 /* For non-vec functions,
3424                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3425                  * for vec functions,
3426                  * refers to _recv_raw_pkts_vec().
3427                  */
3428                 RTE_PTYPE_L2_ETHER,
3429                 RTE_PTYPE_L3_IPV4,
3430                 RTE_PTYPE_L3_IPV4_EXT,
3431                 RTE_PTYPE_L3_IPV6,
3432                 RTE_PTYPE_L3_IPV6_EXT,
3433                 RTE_PTYPE_L4_SCTP,
3434                 RTE_PTYPE_L4_TCP,
3435                 RTE_PTYPE_L4_UDP,
3436                 RTE_PTYPE_TUNNEL_IP,
3437                 RTE_PTYPE_INNER_L3_IPV6,
3438                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3439                 RTE_PTYPE_INNER_L4_TCP,
3440                 RTE_PTYPE_INNER_L4_UDP,
3441                 RTE_PTYPE_UNKNOWN
3442         };
3443
3444         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3445             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3446             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3447             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3448                 return ptypes;
3449         return NULL;
3450 }
3451
3452 static void
3453 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3454                      struct rte_eth_dev_info *dev_info)
3455 {
3456         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3457         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3458
3459         dev_info->pci_dev = pci_dev;
3460         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3461         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3462         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3463         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3464         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3465         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3466         dev_info->max_vfs = pci_dev->max_vfs;
3467         if (hw->mac.type == ixgbe_mac_82598EB)
3468                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3469         else
3470                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3471         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3472                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3473                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3474                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3475         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3476                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3477                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3478                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3479                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3480                                 DEV_TX_OFFLOAD_TCP_TSO;
3481
3482         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3483                 .rx_thresh = {
3484                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3485                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3486                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3487                 },
3488                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3489                 .rx_drop_en = 0,
3490         };
3491
3492         dev_info->default_txconf = (struct rte_eth_txconf) {
3493                 .tx_thresh = {
3494                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3495                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3496                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3497                 },
3498                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3499                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3500                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3501                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3502         };
3503
3504         dev_info->rx_desc_lim = rx_desc_lim;
3505         dev_info->tx_desc_lim = tx_desc_lim;
3506 }
3507
3508 /* return 0 means link status changed, -1 means not changed */
3509 static int
3510 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3511 {
3512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3513         struct rte_eth_link link, old;
3514         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3515         int link_up;
3516         int diag;
3517
3518         link.link_status = ETH_LINK_DOWN;
3519         link.link_speed = 0;
3520         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3521         memset(&old, 0, sizeof(old));
3522         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3523
3524         hw->mac.get_link_status = true;
3525
3526         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3527         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3528                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3529         else
3530                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3531
3532         if (diag != 0) {
3533                 link.link_speed = ETH_SPEED_NUM_100M;
3534                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3535                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3536                 if (link.link_status == old.link_status)
3537                         return -1;
3538                 return 0;
3539         }
3540
3541         if (link_up == 0) {
3542                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3543                 if (link.link_status == old.link_status)
3544                         return -1;
3545                 return 0;
3546         }
3547         link.link_status = ETH_LINK_UP;
3548         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3549
3550         switch (link_speed) {
3551         default:
3552         case IXGBE_LINK_SPEED_UNKNOWN:
3553                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3554                 link.link_speed = ETH_SPEED_NUM_100M;
3555                 break;
3556
3557         case IXGBE_LINK_SPEED_100_FULL:
3558                 link.link_speed = ETH_SPEED_NUM_100M;
3559                 break;
3560
3561         case IXGBE_LINK_SPEED_1GB_FULL:
3562                 link.link_speed = ETH_SPEED_NUM_1G;
3563                 break;
3564
3565         case IXGBE_LINK_SPEED_10GB_FULL:
3566                 link.link_speed = ETH_SPEED_NUM_10G;
3567                 break;
3568         }
3569         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3570
3571         if (link.link_status == old.link_status)
3572                 return -1;
3573
3574         return 0;
3575 }
3576
3577 static void
3578 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3579 {
3580         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3581         uint32_t fctrl;
3582
3583         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3584         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3585         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3586 }
3587
3588 static void
3589 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3590 {
3591         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592         uint32_t fctrl;
3593
3594         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3595         fctrl &= (~IXGBE_FCTRL_UPE);
3596         if (dev->data->all_multicast == 1)
3597                 fctrl |= IXGBE_FCTRL_MPE;
3598         else
3599                 fctrl &= (~IXGBE_FCTRL_MPE);
3600         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3601 }
3602
3603 static void
3604 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3605 {
3606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3607         uint32_t fctrl;
3608
3609         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3610         fctrl |= IXGBE_FCTRL_MPE;
3611         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3612 }
3613
3614 static void
3615 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3616 {
3617         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3618         uint32_t fctrl;
3619
3620         if (dev->data->promiscuous == 1)
3621                 return; /* must remain in all_multicast mode */
3622
3623         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3624         fctrl &= (~IXGBE_FCTRL_MPE);
3625         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3626 }
3627
3628 /**
3629  * It clears the interrupt causes and enables the interrupt.
3630  * It will be called once only during nic initialized.
3631  *
3632  * @param dev
3633  *  Pointer to struct rte_eth_dev.
3634  *
3635  * @return
3636  *  - On success, zero.
3637  *  - On failure, a negative value.
3638  */
3639 static int
3640 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3641 {
3642         struct ixgbe_interrupt *intr =
3643                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3644
3645         ixgbe_dev_link_status_print(dev);
3646         intr->mask |= IXGBE_EICR_LSC;
3647
3648         return 0;
3649 }
3650
3651 /**
3652  * It clears the interrupt causes and enables the interrupt.
3653  * It will be called once only during nic initialized.
3654  *
3655  * @param dev
3656  *  Pointer to struct rte_eth_dev.
3657  *
3658  * @return
3659  *  - On success, zero.
3660  *  - On failure, a negative value.
3661  */
3662 static int
3663 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3664 {
3665         struct ixgbe_interrupt *intr =
3666                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3667
3668         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3669
3670         return 0;
3671 }
3672
3673 /**
3674  * It clears the interrupt causes and enables the interrupt.
3675  * It will be called once only during nic initialized.
3676  *
3677  * @param dev
3678  *  Pointer to struct rte_eth_dev.
3679  *
3680  * @return
3681  *  - On success, zero.
3682  *  - On failure, a negative value.
3683  */
3684 static int
3685 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3686 {
3687         struct ixgbe_interrupt *intr =
3688                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3689
3690         intr->mask |= IXGBE_EICR_LINKSEC;
3691
3692         return 0;
3693 }
3694
3695 /*
3696  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3697  *
3698  * @param dev
3699  *  Pointer to struct rte_eth_dev.
3700  *
3701  * @return
3702  *  - On success, zero.
3703  *  - On failure, a negative value.
3704  */
3705 static int
3706 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3707 {
3708         uint32_t eicr;
3709         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710         struct ixgbe_interrupt *intr =
3711                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3712
3713         /* clear all cause mask */
3714         ixgbe_disable_intr(hw);
3715
3716         /* read-on-clear nic registers here */
3717         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3718         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3719
3720         intr->flags = 0;
3721
3722         /* set flag for async link update */
3723         if (eicr & IXGBE_EICR_LSC)
3724                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3725
3726         if (eicr & IXGBE_EICR_MAILBOX)
3727                 intr->flags |= IXGBE_FLAG_MAILBOX;
3728
3729         if (eicr & IXGBE_EICR_LINKSEC)
3730                 intr->flags |= IXGBE_FLAG_MACSEC;
3731
3732         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3733             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3734             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3735                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3736
3737         return 0;
3738 }
3739
3740 /**
3741  * It gets and then prints the link status.
3742  *
3743  * @param dev
3744  *  Pointer to struct rte_eth_dev.
3745  *
3746  * @return
3747  *  - On success, zero.
3748  *  - On failure, a negative value.
3749  */
3750 static void
3751 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3752 {
3753         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3754         struct rte_eth_link link;
3755
3756         memset(&link, 0, sizeof(link));
3757         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3758         if (link.link_status) {
3759                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3760                                         (int)(dev->data->port_id),
3761                                         (unsigned)link.link_speed,
3762                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3763                                         "full-duplex" : "half-duplex");
3764         } else {
3765                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3766                                 (int)(dev->data->port_id));
3767         }
3768         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3769                                 pci_dev->addr.domain,
3770                                 pci_dev->addr.bus,
3771                                 pci_dev->addr.devid,
3772                                 pci_dev->addr.function);
3773 }
3774
3775 /*
3776  * It executes link_update after knowing an interrupt occurred.
3777  *
3778  * @param dev
3779  *  Pointer to struct rte_eth_dev.
3780  *
3781  * @return
3782  *  - On success, zero.
3783  *  - On failure, a negative value.
3784  */
3785 static int
3786 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3787                            struct rte_intr_handle *intr_handle)
3788 {
3789         struct ixgbe_interrupt *intr =
3790                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3791         int64_t timeout;
3792         struct rte_eth_link link;
3793         struct ixgbe_hw *hw =
3794                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3795
3796         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3797
3798         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3799                 ixgbe_pf_mbx_process(dev);
3800                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3801         }
3802
3803         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3804                 ixgbe_handle_lasi(hw);
3805                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3806         }
3807
3808         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3809                 /* get the link status before link update, for predicting later */
3810                 memset(&link, 0, sizeof(link));
3811                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3812
3813                 ixgbe_dev_link_update(dev, 0);
3814
3815                 /* likely to up */
3816                 if (!link.link_status)
3817                         /* handle it 1 sec later, wait it being stable */
3818                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3819                 /* likely to down */
3820                 else
3821                         /* handle it 4 sec later, wait it being stable */
3822                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3823
3824                 ixgbe_dev_link_status_print(dev);
3825                 intr->mask_original = intr->mask;
3826                 /* only disable lsc interrupt */
3827                 intr->mask &= ~IXGBE_EIMS_LSC;
3828                 if (rte_eal_alarm_set(timeout * 1000,
3829                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3830                         PMD_DRV_LOG(ERR, "Error setting alarm");
3831                 else
3832                         intr->mask = intr->mask_original;
3833         }
3834
3835         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3836         ixgbe_enable_intr(dev);
3837         rte_intr_enable(intr_handle);
3838
3839         return 0;
3840 }
3841
3842 /**
3843  * Interrupt handler which shall be registered for alarm callback for delayed
3844  * handling specific interrupt to wait for the stable nic state. As the
3845  * NIC interrupt state is not stable for ixgbe after link is just down,
3846  * it needs to wait 4 seconds to get the stable status.
3847  *
3848  * @param handle
3849  *  Pointer to interrupt handle.
3850  * @param param
3851  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3852  *
3853  * @return
3854  *  void
3855  */
3856 static void
3857 ixgbe_dev_interrupt_delayed_handler(void *param)
3858 {
3859         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3860         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3861         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3862         struct ixgbe_interrupt *intr =
3863                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3864         struct ixgbe_hw *hw =
3865                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3866         uint32_t eicr;
3867
3868         ixgbe_disable_intr(hw);
3869
3870         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3871         if (eicr & IXGBE_EICR_MAILBOX)
3872                 ixgbe_pf_mbx_process(dev);
3873
3874         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3875                 ixgbe_handle_lasi(hw);
3876                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3877         }
3878
3879         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3880                 ixgbe_dev_link_update(dev, 0);
3881                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3882                 ixgbe_dev_link_status_print(dev);
3883                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3884         }
3885
3886         if (intr->flags & IXGBE_FLAG_MACSEC) {
3887                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3888                                               NULL);
3889                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3890         }
3891
3892         /* restore original mask */
3893         intr->mask = intr->mask_original;
3894         intr->mask_original = 0;
3895
3896         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3897         ixgbe_enable_intr(dev);
3898         rte_intr_enable(intr_handle);
3899 }
3900
3901 /**
3902  * Interrupt handler triggered by NIC  for handling
3903  * specific interrupt.
3904  *
3905  * @param handle
3906  *  Pointer to interrupt handle.
3907  * @param param
3908  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3909  *
3910  * @return
3911  *  void
3912  */
3913 static void
3914 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3915                             void *param)
3916 {
3917         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3918
3919         ixgbe_dev_interrupt_get_status(dev);
3920         ixgbe_dev_interrupt_action(dev, handle);
3921 }
3922
3923 static int
3924 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3925 {
3926         struct ixgbe_hw *hw;
3927
3928         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3930 }
3931
3932 static int
3933 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3934 {
3935         struct ixgbe_hw *hw;
3936
3937         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3938         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3939 }
3940
3941 static int
3942 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3943 {
3944         struct ixgbe_hw *hw;
3945         uint32_t mflcn_reg;
3946         uint32_t fccfg_reg;
3947         int rx_pause;
3948         int tx_pause;
3949
3950         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3951
3952         fc_conf->pause_time = hw->fc.pause_time;
3953         fc_conf->high_water = hw->fc.high_water[0];
3954         fc_conf->low_water = hw->fc.low_water[0];
3955         fc_conf->send_xon = hw->fc.send_xon;
3956         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3957
3958         /*
3959          * Return rx_pause status according to actual setting of
3960          * MFLCN register.
3961          */
3962         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3963         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3964                 rx_pause = 1;
3965         else
3966                 rx_pause = 0;
3967
3968         /*
3969          * Return tx_pause status according to actual setting of
3970          * FCCFG register.
3971          */
3972         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3973         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3974                 tx_pause = 1;
3975         else
3976                 tx_pause = 0;
3977
3978         if (rx_pause && tx_pause)
3979                 fc_conf->mode = RTE_FC_FULL;
3980         else if (rx_pause)
3981                 fc_conf->mode = RTE_FC_RX_PAUSE;
3982         else if (tx_pause)
3983                 fc_conf->mode = RTE_FC_TX_PAUSE;
3984         else
3985                 fc_conf->mode = RTE_FC_NONE;
3986
3987         return 0;
3988 }
3989
3990 static int
3991 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3992 {
3993         struct ixgbe_hw *hw;
3994         int err;
3995         uint32_t rx_buf_size;
3996         uint32_t max_high_water;
3997         uint32_t mflcn;
3998         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3999                 ixgbe_fc_none,
4000                 ixgbe_fc_rx_pause,
4001                 ixgbe_fc_tx_pause,
4002                 ixgbe_fc_full
4003         };
4004
4005         PMD_INIT_FUNC_TRACE();
4006
4007         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4008         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4009         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4010
4011         /*
4012          * At least reserve one Ethernet frame for watermark
4013          * high_water/low_water in kilo bytes for ixgbe
4014          */
4015         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4016         if ((fc_conf->high_water > max_high_water) ||
4017                 (fc_conf->high_water < fc_conf->low_water)) {
4018                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4019                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4020                 return -EINVAL;
4021         }
4022
4023         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4024         hw->fc.pause_time     = fc_conf->pause_time;
4025         hw->fc.high_water[0]  = fc_conf->high_water;
4026         hw->fc.low_water[0]   = fc_conf->low_water;
4027         hw->fc.send_xon       = fc_conf->send_xon;
4028         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4029
4030         err = ixgbe_fc_enable(hw);
4031
4032         /* Not negotiated is not an error case */
4033         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4034
4035                 /* check if we want to forward MAC frames - driver doesn't have native
4036                  * capability to do that, so we'll write the registers ourselves */
4037
4038                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4039
4040                 /* set or clear MFLCN.PMCF bit depending on configuration */
4041                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4042                         mflcn |= IXGBE_MFLCN_PMCF;
4043                 else
4044                         mflcn &= ~IXGBE_MFLCN_PMCF;
4045
4046                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4047                 IXGBE_WRITE_FLUSH(hw);
4048
4049                 return 0;
4050         }
4051
4052         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4053         return -EIO;
4054 }
4055
4056 /**
4057  *  ixgbe_pfc_enable_generic - Enable flow control
4058  *  @hw: pointer to hardware structure
4059  *  @tc_num: traffic class number
4060  *  Enable flow control according to the current settings.
4061  */
4062 static int
4063 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4064 {
4065         int ret_val = 0;
4066         uint32_t mflcn_reg, fccfg_reg;
4067         uint32_t reg;
4068         uint32_t fcrtl, fcrth;
4069         uint8_t i;
4070         uint8_t nb_rx_en;
4071
4072         /* Validate the water mark configuration */
4073         if (!hw->fc.pause_time) {
4074                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4075                 goto out;
4076         }
4077
4078         /* Low water mark of zero causes XOFF floods */
4079         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4080                  /* High/Low water can not be 0 */
4081                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4082                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4083                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4084                         goto out;
4085                 }
4086
4087                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4088                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4089                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4090                         goto out;
4091                 }
4092         }
4093         /* Negotiate the fc mode to use */
4094         ixgbe_fc_autoneg(hw);
4095
4096         /* Disable any previous flow control settings */
4097         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4098         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4099
4100         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4101         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4102
4103         switch (hw->fc.current_mode) {
4104         case ixgbe_fc_none:
4105                 /*
4106                  * If the count of enabled RX Priority Flow control >1,
4107                  * and the TX pause can not be disabled
4108                  */
4109                 nb_rx_en = 0;
4110                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4111                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4112                         if (reg & IXGBE_FCRTH_FCEN)
4113                                 nb_rx_en++;
4114                 }
4115                 if (nb_rx_en > 1)
4116                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4117                 break;
4118         case ixgbe_fc_rx_pause:
4119                 /*
4120                  * Rx Flow control is enabled and Tx Flow control is
4121                  * disabled by software override. Since there really
4122                  * isn't a way to advertise that we are capable of RX
4123                  * Pause ONLY, we will advertise that we support both
4124                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4125                  * disable the adapter's ability to send PAUSE frames.
4126                  */
4127                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4128                 /*
4129                  * If the count of enabled RX Priority Flow control >1,
4130                  * and the TX pause can not be disabled
4131                  */
4132                 nb_rx_en = 0;
4133                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4134                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4135                         if (reg & IXGBE_FCRTH_FCEN)
4136                                 nb_rx_en++;
4137                 }
4138                 if (nb_rx_en > 1)
4139                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4140                 break;
4141         case ixgbe_fc_tx_pause:
4142                 /*
4143                  * Tx Flow control is enabled, and Rx Flow control is
4144                  * disabled by software override.
4145                  */
4146                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4147                 break;
4148         case ixgbe_fc_full:
4149                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4150                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4151                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4152                 break;
4153         default:
4154                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4155                 ret_val = IXGBE_ERR_CONFIG;
4156                 goto out;
4157         }
4158
4159         /* Set 802.3x based flow control settings. */
4160         mflcn_reg |= IXGBE_MFLCN_DPF;
4161         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4162         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4163
4164         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4165         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4166                 hw->fc.high_water[tc_num]) {
4167                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4168                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4169                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4170         } else {
4171                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4172                 /*
4173                  * In order to prevent Tx hangs when the internal Tx
4174                  * switch is enabled we must set the high water mark
4175                  * to the maximum FCRTH value.  This allows the Tx
4176                  * switch to function even under heavy Rx workloads.
4177                  */
4178                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4179         }
4180         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4181
4182         /* Configure pause time (2 TCs per register) */
4183         reg = hw->fc.pause_time * 0x00010001;
4184         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4185                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4186
4187         /* Configure flow control refresh threshold value */
4188         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4189
4190 out:
4191         return ret_val;
4192 }
4193
4194 static int
4195 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4196 {
4197         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4198         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4199
4200         if (hw->mac.type != ixgbe_mac_82598EB) {
4201                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4202         }
4203         return ret_val;
4204 }
4205
4206 static int
4207 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4208 {
4209         int err;
4210         uint32_t rx_buf_size;
4211         uint32_t max_high_water;
4212         uint8_t tc_num;
4213         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4214         struct ixgbe_hw *hw =
4215                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4216         struct ixgbe_dcb_config *dcb_config =
4217                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4218
4219         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4220                 ixgbe_fc_none,
4221                 ixgbe_fc_rx_pause,
4222                 ixgbe_fc_tx_pause,
4223                 ixgbe_fc_full
4224         };
4225
4226         PMD_INIT_FUNC_TRACE();
4227
4228         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4229         tc_num = map[pfc_conf->priority];
4230         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4231         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4232         /*
4233          * At least reserve one Ethernet frame for watermark
4234          * high_water/low_water in kilo bytes for ixgbe
4235          */
4236         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4237         if ((pfc_conf->fc.high_water > max_high_water) ||
4238             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4239                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4240                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4241                 return -EINVAL;
4242         }
4243
4244         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4245         hw->fc.pause_time = pfc_conf->fc.pause_time;
4246         hw->fc.send_xon = pfc_conf->fc.send_xon;
4247         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4248         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4249
4250         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4251
4252         /* Not negotiated is not an error case */
4253         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4254                 return 0;
4255
4256         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4257         return -EIO;
4258 }
4259
4260 static int
4261 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4262                           struct rte_eth_rss_reta_entry64 *reta_conf,
4263                           uint16_t reta_size)
4264 {
4265         uint16_t i, sp_reta_size;
4266         uint8_t j, mask;
4267         uint32_t reta, r;
4268         uint16_t idx, shift;
4269         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4270         uint32_t reta_reg;
4271
4272         PMD_INIT_FUNC_TRACE();
4273
4274         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4275                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4276                         "NIC.");
4277                 return -ENOTSUP;
4278         }
4279
4280         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4281         if (reta_size != sp_reta_size) {
4282                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4283                         "(%d) doesn't match the number hardware can supported "
4284                         "(%d)", reta_size, sp_reta_size);
4285                 return -EINVAL;
4286         }
4287
4288         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4289                 idx = i / RTE_RETA_GROUP_SIZE;
4290                 shift = i % RTE_RETA_GROUP_SIZE;
4291                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4292                                                 IXGBE_4_BIT_MASK);
4293                 if (!mask)
4294                         continue;
4295                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4296                 if (mask == IXGBE_4_BIT_MASK)
4297                         r = 0;
4298                 else
4299                         r = IXGBE_READ_REG(hw, reta_reg);
4300                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4301                         if (mask & (0x1 << j))
4302                                 reta |= reta_conf[idx].reta[shift + j] <<
4303                                                         (CHAR_BIT * j);
4304                         else
4305                                 reta |= r & (IXGBE_8_BIT_MASK <<
4306                                                 (CHAR_BIT * j));
4307                 }
4308                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4309         }
4310
4311         return 0;
4312 }
4313
4314 static int
4315 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4316                          struct rte_eth_rss_reta_entry64 *reta_conf,
4317                          uint16_t reta_size)
4318 {
4319         uint16_t i, sp_reta_size;
4320         uint8_t j, mask;
4321         uint32_t reta;
4322         uint16_t idx, shift;
4323         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4324         uint32_t reta_reg;
4325
4326         PMD_INIT_FUNC_TRACE();
4327         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4328         if (reta_size != sp_reta_size) {
4329                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4330                         "(%d) doesn't match the number hardware can supported "
4331                         "(%d)", reta_size, sp_reta_size);
4332                 return -EINVAL;
4333         }
4334
4335         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4336                 idx = i / RTE_RETA_GROUP_SIZE;
4337                 shift = i % RTE_RETA_GROUP_SIZE;
4338                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4339                                                 IXGBE_4_BIT_MASK);
4340                 if (!mask)
4341                         continue;
4342
4343                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4344                 reta = IXGBE_READ_REG(hw, reta_reg);
4345                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4346                         if (mask & (0x1 << j))
4347                                 reta_conf[idx].reta[shift + j] =
4348                                         ((reta >> (CHAR_BIT * j)) &
4349                                                 IXGBE_8_BIT_MASK);
4350                 }
4351         }
4352
4353         return 0;
4354 }
4355
4356 static void
4357 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4358                                 uint32_t index, uint32_t pool)
4359 {
4360         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4361         uint32_t enable_addr = 1;
4362
4363         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4364 }
4365
4366 static void
4367 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4368 {
4369         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370
4371         ixgbe_clear_rar(hw, index);
4372 }
4373
4374 static void
4375 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4376 {
4377         ixgbe_remove_rar(dev, 0);
4378
4379         ixgbe_add_rar(dev, addr, 0, 0);
4380 }
4381
4382 static bool
4383 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
4384 {
4385         if (strcmp(dev->driver->pci_drv.driver.name,
4386                    drv->pci_drv.driver.name))
4387                 return false;
4388
4389         return true;
4390 }
4391
4392 int
4393 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4394                 struct ether_addr *mac_addr)
4395 {
4396         struct ixgbe_hw *hw;
4397         struct ixgbe_vf_info *vfinfo;
4398         int rar_entry;
4399         uint8_t *new_mac = (uint8_t *)(mac_addr);
4400         struct rte_eth_dev *dev;
4401         struct rte_pci_device *pci_dev;
4402
4403         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4404
4405         dev = &rte_eth_devices[port];
4406         pci_dev = IXGBE_DEV_TO_PCI(dev);
4407
4408         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4409                 return -ENOTSUP;
4410
4411         if (vf >= pci_dev->max_vfs)
4412                 return -EINVAL;
4413
4414         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4415         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4416         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4417
4418         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4419                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4420                                 ETHER_ADDR_LEN);
4421                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4422                                 IXGBE_RAH_AV);
4423         }
4424         return -EINVAL;
4425 }
4426
4427 static int
4428 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4429 {
4430         uint32_t hlreg0;
4431         uint32_t maxfrs;
4432         struct ixgbe_hw *hw;
4433         struct rte_eth_dev_info dev_info;
4434         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4435
4436         ixgbe_dev_info_get(dev, &dev_info);
4437
4438         /* check that mtu is within the allowed range */
4439         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4440                 return -EINVAL;
4441
4442         /* refuse mtu that requires the support of scattered packets when this
4443          * feature has not been enabled before.
4444          */
4445         if (!dev->data->scattered_rx &&
4446             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4447              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4448                 return -EINVAL;
4449
4450         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4451         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4452
4453         /* switch to jumbo mode if needed */
4454         if (frame_size > ETHER_MAX_LEN) {
4455                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4456                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4457         } else {
4458                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4459                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4460         }
4461         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4462
4463         /* update max frame size */
4464         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4465
4466         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4467         maxfrs &= 0x0000FFFF;
4468         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4469         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4470
4471         return 0;
4472 }
4473
4474 /*
4475  * Virtual Function operations
4476  */
4477 static void
4478 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4479 {
4480         PMD_INIT_FUNC_TRACE();
4481
4482         /* Clear interrupt mask to stop from interrupts being generated */
4483         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4484
4485         IXGBE_WRITE_FLUSH(hw);
4486 }
4487
4488 static void
4489 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4490 {
4491         PMD_INIT_FUNC_TRACE();
4492
4493         /* VF enable interrupt autoclean */
4494         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4495         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4496         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4497
4498         IXGBE_WRITE_FLUSH(hw);
4499 }
4500
4501 static int
4502 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4503 {
4504         struct rte_eth_conf *conf = &dev->data->dev_conf;
4505         struct ixgbe_adapter *adapter =
4506                         (struct ixgbe_adapter *)dev->data->dev_private;
4507
4508         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4509                      dev->data->port_id);
4510
4511         /*
4512          * VF has no ability to enable/disable HW CRC
4513          * Keep the persistent behavior the same as Host PF
4514          */
4515 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4516         if (!conf->rxmode.hw_strip_crc) {
4517                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4518                 conf->rxmode.hw_strip_crc = 1;
4519         }
4520 #else
4521         if (conf->rxmode.hw_strip_crc) {
4522                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4523                 conf->rxmode.hw_strip_crc = 0;
4524         }
4525 #endif
4526
4527         /*
4528          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4529          * allocation or vector Rx preconditions we will reset it.
4530          */
4531         adapter->rx_bulk_alloc_allowed = true;
4532         adapter->rx_vec_allowed = true;
4533
4534         return 0;
4535 }
4536
4537 static int
4538 ixgbevf_dev_start(struct rte_eth_dev *dev)
4539 {
4540         struct ixgbe_hw *hw =
4541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4542         uint32_t intr_vector = 0;
4543         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4544         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4545
4546         int err, mask = 0;
4547
4548         PMD_INIT_FUNC_TRACE();
4549
4550         hw->mac.ops.reset_hw(hw);
4551         hw->mac.get_link_status = true;
4552
4553         /* negotiate mailbox API version to use with the PF. */
4554         ixgbevf_negotiate_api(hw);
4555
4556         ixgbevf_dev_tx_init(dev);
4557
4558         /* This can fail when allocating mbufs for descriptor rings */
4559         err = ixgbevf_dev_rx_init(dev);
4560         if (err) {
4561                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4562                 ixgbe_dev_clear_queues(dev);
4563                 return err;
4564         }
4565
4566         /* Set vfta */
4567         ixgbevf_set_vfta_all(dev, 1);
4568
4569         /* Set HW strip */
4570         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4571                 ETH_VLAN_EXTEND_MASK;
4572         ixgbevf_vlan_offload_set(dev, mask);
4573
4574         ixgbevf_dev_rxtx_start(dev);
4575
4576         /* check and configure queue intr-vector mapping */
4577         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4578                 intr_vector = dev->data->nb_rx_queues;
4579                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4580                         return -1;
4581         }
4582
4583         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4584                 intr_handle->intr_vec =
4585                         rte_zmalloc("intr_vec",
4586                                     dev->data->nb_rx_queues * sizeof(int), 0);
4587                 if (intr_handle->intr_vec == NULL) {
4588                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4589                                      " intr_vec", dev->data->nb_rx_queues);
4590                         return -ENOMEM;
4591                 }
4592         }
4593         ixgbevf_configure_msix(dev);
4594
4595         rte_intr_enable(intr_handle);
4596
4597         /* Re-enable interrupt for VF */
4598         ixgbevf_intr_enable(hw);
4599
4600         return 0;
4601 }
4602
4603 static void
4604 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4605 {
4606         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4608         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4609
4610         PMD_INIT_FUNC_TRACE();
4611
4612         ixgbevf_intr_disable(hw);
4613
4614         hw->adapter_stopped = 1;
4615         ixgbe_stop_adapter(hw);
4616
4617         /*
4618           * Clear what we set, but we still keep shadow_vfta to
4619           * restore after device starts
4620           */
4621         ixgbevf_set_vfta_all(dev, 0);
4622
4623         /* Clear stored conf */
4624         dev->data->scattered_rx = 0;
4625
4626         ixgbe_dev_clear_queues(dev);
4627
4628         /* Clean datapath event and queue/vec mapping */
4629         rte_intr_efd_disable(intr_handle);
4630         if (intr_handle->intr_vec != NULL) {
4631                 rte_free(intr_handle->intr_vec);
4632                 intr_handle->intr_vec = NULL;
4633         }
4634 }
4635
4636 static void
4637 ixgbevf_dev_close(struct rte_eth_dev *dev)
4638 {
4639         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4640
4641         PMD_INIT_FUNC_TRACE();
4642
4643         ixgbe_reset_hw(hw);
4644
4645         ixgbevf_dev_stop(dev);
4646
4647         ixgbe_dev_free_queues(dev);
4648
4649         /**
4650          * Remove the VF MAC address ro ensure
4651          * that the VF traffic goes to the PF
4652          * after stop, close and detach of the VF
4653          **/
4654         ixgbevf_remove_mac_addr(dev, 0);
4655 }
4656
4657 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4658 {
4659         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4660         struct ixgbe_vfta *shadow_vfta =
4661                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4662         int i = 0, j = 0, vfta = 0, mask = 1;
4663
4664         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4665                 vfta = shadow_vfta->vfta[i];
4666                 if (vfta) {
4667                         mask = 1;
4668                         for (j = 0; j < 32; j++) {
4669                                 if (vfta & mask)
4670                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4671                                                        on, false);
4672                                 mask <<= 1;
4673                         }
4674                 }
4675         }
4676
4677 }
4678
4679 static int
4680 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4681 {
4682         struct ixgbe_hw *hw =
4683                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4684         struct ixgbe_vfta *shadow_vfta =
4685                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4686         uint32_t vid_idx = 0;
4687         uint32_t vid_bit = 0;
4688         int ret = 0;
4689
4690         PMD_INIT_FUNC_TRACE();
4691
4692         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4693         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4694         if (ret) {
4695                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4696                 return ret;
4697         }
4698         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4699         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4700
4701         /* Save what we set and retore it after device reset */
4702         if (on)
4703                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4704         else
4705                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4706
4707         return 0;
4708 }
4709
4710 static void
4711 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4712 {
4713         struct ixgbe_hw *hw =
4714                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4715         uint32_t ctrl;
4716
4717         PMD_INIT_FUNC_TRACE();
4718
4719         if (queue >= hw->mac.max_rx_queues)
4720                 return;
4721
4722         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4723         if (on)
4724                 ctrl |= IXGBE_RXDCTL_VME;
4725         else
4726                 ctrl &= ~IXGBE_RXDCTL_VME;
4727         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4728
4729         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4730 }
4731
4732 static void
4733 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4734 {
4735         struct ixgbe_hw *hw =
4736                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4737         uint16_t i;
4738         int on = 0;
4739
4740         /* VF function only support hw strip feature, others are not support */
4741         if (mask & ETH_VLAN_STRIP_MASK) {
4742                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4743
4744                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4745                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4746         }
4747 }
4748
4749 static int
4750 ixgbe_vt_check(struct ixgbe_hw *hw)
4751 {
4752         uint32_t reg_val;
4753
4754         /* if Virtualization Technology is enabled */
4755         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4756         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4757                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4758                 return -1;
4759         }
4760
4761         return 0;
4762 }
4763
4764 static uint32_t
4765 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4766 {
4767         uint32_t vector = 0;
4768
4769         switch (hw->mac.mc_filter_type) {
4770         case 0:   /* use bits [47:36] of the address */
4771                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4772                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4773                 break;
4774         case 1:   /* use bits [46:35] of the address */
4775                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4776                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4777                 break;
4778         case 2:   /* use bits [45:34] of the address */
4779                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4780                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4781                 break;
4782         case 3:   /* use bits [43:32] of the address */
4783                 vector = ((uc_addr->addr_bytes[4]) |
4784                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4785                 break;
4786         default:  /* Invalid mc_filter_type */
4787                 break;
4788         }
4789
4790         /* vector can only be 12-bits or boundary will be exceeded */
4791         vector &= 0xFFF;
4792         return vector;
4793 }
4794
4795 static int
4796 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4797                         uint8_t on)
4798 {
4799         uint32_t vector;
4800         uint32_t uta_idx;
4801         uint32_t reg_val;
4802         uint32_t uta_shift;
4803         uint32_t rc;
4804         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4805         const uint32_t ixgbe_uta_bit_shift = 5;
4806         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4807         const uint32_t bit1 = 0x1;
4808
4809         struct ixgbe_hw *hw =
4810                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4811         struct ixgbe_uta_info *uta_info =
4812                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4813
4814         /* The UTA table only exists on 82599 hardware and newer */
4815         if (hw->mac.type < ixgbe_mac_82599EB)
4816                 return -ENOTSUP;
4817
4818         vector = ixgbe_uta_vector(hw, mac_addr);
4819         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4820         uta_shift = vector & ixgbe_uta_bit_mask;
4821
4822         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4823         if (rc == on)
4824                 return 0;
4825
4826         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4827         if (on) {
4828                 uta_info->uta_in_use++;
4829                 reg_val |= (bit1 << uta_shift);
4830                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4831         } else {
4832                 uta_info->uta_in_use--;
4833                 reg_val &= ~(bit1 << uta_shift);
4834                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4835         }
4836
4837         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4838
4839         if (uta_info->uta_in_use > 0)
4840                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4841                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4842         else
4843                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4844
4845         return 0;
4846 }
4847
4848 static int
4849 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4850 {
4851         int i;
4852         struct ixgbe_hw *hw =
4853                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4854         struct ixgbe_uta_info *uta_info =
4855                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4856
4857         /* The UTA table only exists on 82599 hardware and newer */
4858         if (hw->mac.type < ixgbe_mac_82599EB)
4859                 return -ENOTSUP;
4860
4861         if (on) {
4862                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4863                         uta_info->uta_shadow[i] = ~0;
4864                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4865                 }
4866         } else {
4867                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4868                         uta_info->uta_shadow[i] = 0;
4869                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4870                 }
4871         }
4872         return 0;
4873
4874 }
4875
4876 uint32_t
4877 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4878 {
4879         uint32_t new_val = orig_val;
4880
4881         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4882                 new_val |= IXGBE_VMOLR_AUPE;
4883         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4884                 new_val |= IXGBE_VMOLR_ROMPE;
4885         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4886                 new_val |= IXGBE_VMOLR_ROPE;
4887         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4888                 new_val |= IXGBE_VMOLR_BAM;
4889         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4890                 new_val |= IXGBE_VMOLR_MPE;
4891
4892         return new_val;
4893 }
4894
4895
4896 int
4897 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4898 {
4899         struct ixgbe_hw *hw;
4900         struct ixgbe_mac_info *mac;
4901         struct rte_eth_dev *dev;
4902         struct rte_pci_device *pci_dev;
4903
4904         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4905
4906         dev = &rte_eth_devices[port];
4907         pci_dev = IXGBE_DEV_TO_PCI(dev);
4908
4909         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4910                 return -ENOTSUP;
4911
4912         if (vf >= pci_dev->max_vfs)
4913                 return -EINVAL;
4914
4915         if (on > 1)
4916                 return -EINVAL;
4917
4918         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4919         mac = &hw->mac;
4920
4921         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4922
4923         return 0;
4924 }
4925
4926 int
4927 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4928 {
4929         struct ixgbe_hw *hw;
4930         struct ixgbe_mac_info *mac;
4931         struct rte_eth_dev *dev;
4932         struct rte_pci_device *pci_dev;
4933
4934         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4935
4936         dev = &rte_eth_devices[port];
4937         pci_dev = IXGBE_DEV_TO_PCI(dev);
4938
4939         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4940                 return -ENOTSUP;
4941
4942         if (vf >= pci_dev->max_vfs)
4943                 return -EINVAL;
4944
4945         if (on > 1)
4946                 return -EINVAL;
4947
4948         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4949         mac = &hw->mac;
4950         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4951
4952         return 0;
4953 }
4954
4955 int
4956 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4957 {
4958         struct ixgbe_hw *hw;
4959         uint32_t ctrl;
4960         struct rte_eth_dev *dev;
4961         struct rte_pci_device *pci_dev;
4962
4963         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4964
4965         dev = &rte_eth_devices[port];
4966         pci_dev = IXGBE_DEV_TO_PCI(dev);
4967
4968         if (!is_device_supported(dev, &rte_ixgbe_pmd))
4969                 return -ENOTSUP;
4970
4971         if (vf >= pci_dev->max_vfs)
4972                 return -EINVAL;
4973
4974         if (vlan_id > ETHER_MAX_VLAN_ID)
4975                 return -EINVAL;
4976
4977         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4978         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4979         if (vlan_id) {
4980                 ctrl = vlan_id;
4981                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4982         } else {
4983                 ctrl = 0;
4984         }
4985
4986         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4987
4988         return 0;
4989 }
4990
4991 int
4992 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4993 {
4994         struct ixgbe_hw *hw;
4995         uint32_t ctrl;
4996         struct rte_eth_dev *dev;
4997
4998         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4999
5000         dev = &rte_eth_devices[port];
5001
5002         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5003                 return -ENOTSUP;
5004
5005         if (on > 1)
5006                 return -EINVAL;
5007
5008         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5010         /* enable or disable VMDQ loopback */
5011         if (on)
5012                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5013         else
5014                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5015
5016         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5017
5018         return 0;
5019 }
5020
5021 int
5022 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5023 {
5024         struct ixgbe_hw *hw;
5025         uint32_t reg_value;
5026         int i;
5027         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5028         struct rte_eth_dev *dev;
5029
5030         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5031
5032         dev = &rte_eth_devices[port];
5033
5034         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5035                 return -ENOTSUP;
5036
5037         if (on > 1)
5038                 return -EINVAL;
5039
5040         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5041         for (i = 0; i <= num_queues; i++) {
5042                 reg_value = IXGBE_QDE_WRITE |
5043                                 (i << IXGBE_QDE_IDX_SHIFT) |
5044                                 (on & IXGBE_QDE_ENABLE);
5045                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5046         }
5047
5048         return 0;
5049 }
5050
5051 int
5052 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5053 {
5054         struct ixgbe_hw *hw;
5055         uint32_t reg_value;
5056         struct rte_eth_dev *dev;
5057         struct rte_pci_device *pci_dev;
5058
5059         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5060
5061         dev = &rte_eth_devices[port];
5062         pci_dev = IXGBE_DEV_TO_PCI(dev);
5063
5064         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5065                 return -ENOTSUP;
5066
5067         /* only support VF's 0 to 63 */
5068         if ((vf >= pci_dev->max_vfs) || (vf > 63))
5069                 return -EINVAL;
5070
5071         if (on > 1)
5072                 return -EINVAL;
5073
5074         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5075         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5076         if (on)
5077                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5078         else
5079                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5080
5081         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5082
5083         return 0;
5084 }
5085
5086 int
5087 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5088 {
5089         struct rte_eth_dev *dev;
5090         struct rte_pci_device *pci_dev;
5091         struct ixgbe_hw *hw;
5092         uint16_t queues_per_pool;
5093         uint32_t q;
5094
5095         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5096
5097         dev = &rte_eth_devices[port];
5098         pci_dev = IXGBE_DEV_TO_PCI(dev);
5099         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5100
5101         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5102                 return -ENOTSUP;
5103
5104         if (vf >= pci_dev->max_vfs)
5105                 return -EINVAL;
5106
5107         if (on > 1)
5108                 return -EINVAL;
5109
5110         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5111
5112         /* The PF has 128 queue pairs and in SRIOV configuration
5113          * those queues will be assigned to VF's, so RXDCTL
5114          * registers will be dealing with queues which will be
5115          * assigned to VF's.
5116          * Let's say we have SRIOV configured with 31 VF's then the
5117          * first 124 queues 0-123 will be allocated to VF's and only
5118          * the last 4 queues 123-127 will be assigned to the PF.
5119          */
5120         if (hw->mac.type == ixgbe_mac_82598EB)
5121                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5122                                   ETH_16_POOLS;
5123         else
5124                 queues_per_pool = (uint16_t)hw->mac.max_rx_queues /
5125                                   ETH_64_POOLS;
5126
5127         for (q = 0; q < queues_per_pool; q++)
5128                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5129                                 q + vf * queues_per_pool, on);
5130         return 0;
5131 }
5132
5133 int
5134 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5135 {
5136         int val = 0;
5137         struct rte_eth_dev *dev;
5138         struct rte_pci_device *pci_dev;
5139         struct ixgbe_hw *hw;
5140         uint32_t vmolr;
5141
5142         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5143
5144         dev = &rte_eth_devices[port];
5145         pci_dev = IXGBE_DEV_TO_PCI(dev);
5146
5147         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5148                 return -ENOTSUP;
5149
5150         if (vf >= pci_dev->max_vfs)
5151                 return -EINVAL;
5152
5153         if (on > 1)
5154                 return -EINVAL;
5155
5156         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5157         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5158
5159         if (hw->mac.type == ixgbe_mac_82598EB) {
5160                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5161                              " on 82599 hardware and newer");
5162                 return -ENOTSUP;
5163         }
5164         if (ixgbe_vt_check(hw) < 0)
5165                 return -ENOTSUP;
5166
5167         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5168
5169         if (on)
5170                 vmolr |= val;
5171         else
5172                 vmolr &= ~val;
5173
5174         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5175
5176         return 0;
5177 }
5178
5179 int
5180 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5181 {
5182         struct rte_eth_dev *dev;
5183         struct rte_pci_device *pci_dev;
5184         uint32_t reg, addr;
5185         uint32_t val;
5186         const uint8_t bit1 = 0x1;
5187         struct ixgbe_hw *hw;
5188
5189         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5190
5191         dev = &rte_eth_devices[port];
5192         pci_dev = IXGBE_DEV_TO_PCI(dev);
5193
5194         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5195                 return -ENOTSUP;
5196
5197         if (vf >= pci_dev->max_vfs)
5198                 return -EINVAL;
5199
5200         if (on > 1)
5201                 return -EINVAL;
5202
5203         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5204
5205         if (ixgbe_vt_check(hw) < 0)
5206                 return -ENOTSUP;
5207
5208         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5209         if (vf >= 32) {
5210                 addr = IXGBE_VFRE(1);
5211                 val = bit1 << (vf - 32);
5212         } else {
5213                 addr = IXGBE_VFRE(0);
5214                 val = bit1 << vf;
5215         }
5216
5217         reg = IXGBE_READ_REG(hw, addr);
5218
5219         if (on)
5220                 reg |= val;
5221         else
5222                 reg &= ~val;
5223
5224         IXGBE_WRITE_REG(hw, addr, reg);
5225
5226         return 0;
5227 }
5228
5229 int
5230 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5231 {
5232         struct rte_eth_dev *dev;
5233         struct rte_pci_device *pci_dev;
5234         uint32_t reg, addr;
5235         uint32_t val;
5236         const uint8_t bit1 = 0x1;
5237
5238         struct ixgbe_hw *hw;
5239
5240         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5241
5242         dev = &rte_eth_devices[port];
5243         pci_dev = IXGBE_DEV_TO_PCI(dev);
5244
5245         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5246                 return -ENOTSUP;
5247
5248         if (vf >= pci_dev->max_vfs)
5249                 return -EINVAL;
5250
5251         if (on > 1)
5252                 return -EINVAL;
5253
5254         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255         if (ixgbe_vt_check(hw) < 0)
5256                 return -ENOTSUP;
5257
5258         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5259         if (vf >= 32) {
5260                 addr = IXGBE_VFTE(1);
5261                 val = bit1 << (vf - 32);
5262         } else {
5263                 addr = IXGBE_VFTE(0);
5264                 val = bit1 << vf;
5265         }
5266
5267         reg = IXGBE_READ_REG(hw, addr);
5268
5269         if (on)
5270                 reg |= val;
5271         else
5272                 reg &= ~val;
5273
5274         IXGBE_WRITE_REG(hw, addr, reg);
5275
5276         return 0;
5277 }
5278
5279 int
5280 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5281                         uint64_t vf_mask, uint8_t vlan_on)
5282 {
5283         struct rte_eth_dev *dev;
5284         int ret = 0;
5285         uint16_t vf_idx;
5286         struct ixgbe_hw *hw;
5287
5288         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5289
5290         dev = &rte_eth_devices[port];
5291
5292         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5293                 return -ENOTSUP;
5294
5295         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5296                 return -EINVAL;
5297
5298         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5299         if (ixgbe_vt_check(hw) < 0)
5300                 return -ENOTSUP;
5301
5302         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5303                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5304                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5305                                                    vlan_on, false);
5306                         if (ret < 0)
5307                                 return ret;
5308                 }
5309         }
5310
5311         return ret;
5312 }
5313
5314 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5315         uint16_t tx_rate, uint64_t q_msk)
5316 {
5317         struct rte_eth_dev *dev;
5318         struct ixgbe_hw *hw;
5319         struct ixgbe_vf_info *vfinfo;
5320         struct rte_eth_link link;
5321         uint8_t  nb_q_per_pool;
5322         uint32_t queue_stride;
5323         uint32_t queue_idx, idx = 0, vf_idx;
5324         uint32_t queue_end;
5325         uint16_t total_rate = 0;
5326         struct rte_pci_device *pci_dev;
5327
5328         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5329
5330         dev = &rte_eth_devices[port];
5331         pci_dev = IXGBE_DEV_TO_PCI(dev);
5332         rte_eth_link_get_nowait(port, &link);
5333
5334         if (!is_device_supported(dev, &rte_ixgbe_pmd))
5335                 return -ENOTSUP;
5336
5337         if (vf >= pci_dev->max_vfs)
5338                 return -EINVAL;
5339
5340         if (tx_rate > link.link_speed)
5341                 return -EINVAL;
5342
5343         if (q_msk == 0)
5344                 return 0;
5345
5346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5348         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5349         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5350         queue_idx = vf * queue_stride;
5351         queue_end = queue_idx + nb_q_per_pool - 1;
5352         if (queue_end >= hw->mac.max_tx_queues)
5353                 return -EINVAL;
5354
5355         if (vfinfo) {
5356                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5357                         if (vf_idx == vf)
5358                                 continue;
5359                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5360                                 idx++)
5361                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5362                 }
5363         } else {
5364                 return -EINVAL;
5365         }
5366
5367         /* Store tx_rate for this vf. */
5368         for (idx = 0; idx < nb_q_per_pool; idx++) {
5369                 if (((uint64_t)0x1 << idx) & q_msk) {
5370                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5371                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5372                         total_rate += tx_rate;
5373                 }
5374         }
5375
5376         if (total_rate > dev->data->dev_link.link_speed) {
5377                 /* Reset stored TX rate of the VF if it causes exceed
5378                  * link speed.
5379                  */
5380                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5381                 return -EINVAL;
5382         }
5383
5384         /* Set RTTBCNRC of each queue/pool for vf X  */
5385         for (; queue_idx <= queue_end; queue_idx++) {
5386                 if (0x1 & q_msk)
5387                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5388                 q_msk = q_msk >> 1;
5389         }
5390
5391         return 0;
5392 }
5393
5394 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5395 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5396 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5397 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5398 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5399         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5400         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5401
5402 static int
5403 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5404                         struct rte_eth_mirror_conf *mirror_conf,
5405                         uint8_t rule_id, uint8_t on)
5406 {
5407         uint32_t mr_ctl, vlvf;
5408         uint32_t mp_lsb = 0;
5409         uint32_t mv_msb = 0;
5410         uint32_t mv_lsb = 0;
5411         uint32_t mp_msb = 0;
5412         uint8_t i = 0;
5413         int reg_index = 0;
5414         uint64_t vlan_mask = 0;
5415
5416         const uint8_t pool_mask_offset = 32;
5417         const uint8_t vlan_mask_offset = 32;
5418         const uint8_t dst_pool_offset = 8;
5419         const uint8_t rule_mr_offset  = 4;
5420         const uint8_t mirror_rule_mask = 0x0F;
5421
5422         struct ixgbe_mirror_info *mr_info =
5423                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5424         struct ixgbe_hw *hw =
5425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426         uint8_t mirror_type = 0;
5427
5428         if (ixgbe_vt_check(hw) < 0)
5429                 return -ENOTSUP;
5430
5431         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5432                 return -EINVAL;
5433
5434         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5435                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5436                         mirror_conf->rule_type);
5437                 return -EINVAL;
5438         }
5439
5440         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5441                 mirror_type |= IXGBE_MRCTL_VLME;
5442                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5443                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5444                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5445                                 /* search vlan id related pool vlan filter index */
5446                                 reg_index = ixgbe_find_vlvf_slot(hw,
5447                                                  mirror_conf->vlan.vlan_id[i],
5448                                                  false);
5449                                 if (reg_index < 0)
5450                                         return -EINVAL;
5451                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5452                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5453                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5454                                       mirror_conf->vlan.vlan_id[i]))
5455                                         vlan_mask |= (1ULL << reg_index);
5456                                 else
5457                                         return -EINVAL;
5458                         }
5459                 }
5460
5461                 if (on) {
5462                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5463                         mv_msb = vlan_mask >> vlan_mask_offset;
5464
5465                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5466                                                 mirror_conf->vlan.vlan_mask;
5467                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5468                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5469                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5470                                                 mirror_conf->vlan.vlan_id[i];
5471                         }
5472                 } else {
5473                         mv_lsb = 0;
5474                         mv_msb = 0;
5475                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5476                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5477                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5478                 }
5479         }
5480
5481         /*
5482          * if enable pool mirror, write related pool mask register,if disable
5483          * pool mirror, clear PFMRVM register
5484          */
5485         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5486                 mirror_type |= IXGBE_MRCTL_VPME;
5487                 if (on) {
5488                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5489                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5490                         mr_info->mr_conf[rule_id].pool_mask =
5491                                         mirror_conf->pool_mask;
5492
5493                 } else {
5494                         mp_lsb = 0;
5495                         mp_msb = 0;
5496                         mr_info->mr_conf[rule_id].pool_mask = 0;
5497                 }
5498         }
5499         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5500                 mirror_type |= IXGBE_MRCTL_UPME;
5501         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5502                 mirror_type |= IXGBE_MRCTL_DPME;
5503
5504         /* read  mirror control register and recalculate it */
5505         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5506
5507         if (on) {
5508                 mr_ctl |= mirror_type;
5509                 mr_ctl &= mirror_rule_mask;
5510                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5511         } else
5512                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5513
5514         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5515         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5516
5517         /* write mirrror control  register */
5518         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5519
5520         /* write pool mirrror control  register */
5521         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5524                                 mp_msb);
5525         }
5526         /* write VLAN mirrror control  register */
5527         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5529                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5530                                 mv_msb);
5531         }
5532
5533         return 0;
5534 }
5535
5536 static int
5537 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5538 {
5539         int mr_ctl = 0;
5540         uint32_t lsb_val = 0;
5541         uint32_t msb_val = 0;
5542         const uint8_t rule_mr_offset = 4;
5543
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct ixgbe_mirror_info *mr_info =
5547                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5548
5549         if (ixgbe_vt_check(hw) < 0)
5550                 return -ENOTSUP;
5551
5552         memset(&mr_info->mr_conf[rule_id], 0,
5553                 sizeof(struct rte_eth_mirror_conf));
5554
5555         /* clear PFVMCTL register */
5556         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5557
5558         /* clear pool mask register */
5559         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5560         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5561
5562         /* clear vlan mask register */
5563         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5564         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5565
5566         return 0;
5567 }
5568
5569 static int
5570 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5571 {
5572         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5574         uint32_t mask;
5575         struct ixgbe_hw *hw =
5576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577
5578         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5579         mask |= (1 << IXGBE_MISC_VEC_ID);
5580         RTE_SET_USED(queue_id);
5581         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5582
5583         rte_intr_enable(intr_handle);
5584
5585         return 0;
5586 }
5587
5588 static int
5589 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5590 {
5591         uint32_t mask;
5592         struct ixgbe_hw *hw =
5593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594
5595         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5596         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5597         RTE_SET_USED(queue_id);
5598         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5599
5600         return 0;
5601 }
5602
5603 static int
5604 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5605 {
5606         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5608         uint32_t mask;
5609         struct ixgbe_hw *hw =
5610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611         struct ixgbe_interrupt *intr =
5612                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5613
5614         if (queue_id < 16) {
5615                 ixgbe_disable_intr(hw);
5616                 intr->mask |= (1 << queue_id);
5617                 ixgbe_enable_intr(dev);
5618         } else if (queue_id < 32) {
5619                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5620                 mask &= (1 << queue_id);
5621                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5622         } else if (queue_id < 64) {
5623                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5624                 mask &= (1 << (queue_id - 32));
5625                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5626         }
5627         rte_intr_enable(intr_handle);
5628
5629         return 0;
5630 }
5631
5632 static int
5633 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5634 {
5635         uint32_t mask;
5636         struct ixgbe_hw *hw =
5637                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5638         struct ixgbe_interrupt *intr =
5639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5640
5641         if (queue_id < 16) {
5642                 ixgbe_disable_intr(hw);
5643                 intr->mask &= ~(1 << queue_id);
5644                 ixgbe_enable_intr(dev);
5645         } else if (queue_id < 32) {
5646                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5647                 mask &= ~(1 << queue_id);
5648                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5649         } else if (queue_id < 64) {
5650                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5651                 mask &= ~(1 << (queue_id - 32));
5652                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5653         }
5654
5655         return 0;
5656 }
5657
5658 static void
5659 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5660                      uint8_t queue, uint8_t msix_vector)
5661 {
5662         uint32_t tmp, idx;
5663
5664         if (direction == -1) {
5665                 /* other causes */
5666                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5667                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5668                 tmp &= ~0xFF;
5669                 tmp |= msix_vector;
5670                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5671         } else {
5672                 /* rx or tx cause */
5673                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5674                 idx = ((16 * (queue & 1)) + (8 * direction));
5675                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5676                 tmp &= ~(0xFF << idx);
5677                 tmp |= (msix_vector << idx);
5678                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5679         }
5680 }
5681
5682 /**
5683  * set the IVAR registers, mapping interrupt causes to vectors
5684  * @param hw
5685  *  pointer to ixgbe_hw struct
5686  * @direction
5687  *  0 for Rx, 1 for Tx, -1 for other causes
5688  * @queue
5689  *  queue to map the corresponding interrupt to
5690  * @msix_vector
5691  *  the vector to map to the corresponding queue
5692  */
5693 static void
5694 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5695                    uint8_t queue, uint8_t msix_vector)
5696 {
5697         uint32_t tmp, idx;
5698
5699         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5700         if (hw->mac.type == ixgbe_mac_82598EB) {
5701                 if (direction == -1)
5702                         direction = 0;
5703                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5704                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5705                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5706                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5707                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5708         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5709                         (hw->mac.type == ixgbe_mac_X540)) {
5710                 if (direction == -1) {
5711                         /* other causes */
5712                         idx = ((queue & 1) * 8);
5713                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5714                         tmp &= ~(0xFF << idx);
5715                         tmp |= (msix_vector << idx);
5716                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5717                 } else {
5718                         /* rx or tx causes */
5719                         idx = ((16 * (queue & 1)) + (8 * direction));
5720                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5721                         tmp &= ~(0xFF << idx);
5722                         tmp |= (msix_vector << idx);
5723                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5724                 }
5725         }
5726 }
5727
5728 static void
5729 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5730 {
5731         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5733         struct ixgbe_hw *hw =
5734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735         uint32_t q_idx;
5736         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5737
5738         /* Configure VF other cause ivar */
5739         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5740
5741         /* won't configure msix register if no mapping is done
5742          * between intr vector and event fd.
5743          */
5744         if (!rte_intr_dp_is_en(intr_handle))
5745                 return;
5746
5747         /* Configure all RX queues of VF */
5748         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5749                 /* Force all queue use vector 0,
5750                  * as IXGBE_VF_MAXMSIVECOTR = 1
5751                  */
5752                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5753                 intr_handle->intr_vec[q_idx] = vector_idx;
5754         }
5755 }
5756
5757 /**
5758  * Sets up the hardware to properly generate MSI-X interrupts
5759  * @hw
5760  *  board private structure
5761  */
5762 static void
5763 ixgbe_configure_msix(struct rte_eth_dev *dev)
5764 {
5765         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5767         struct ixgbe_hw *hw =
5768                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5770         uint32_t vec = IXGBE_MISC_VEC_ID;
5771         uint32_t mask;
5772         uint32_t gpie;
5773
5774         /* won't configure msix register if no mapping is done
5775          * between intr vector and event fd
5776          */
5777         if (!rte_intr_dp_is_en(intr_handle))
5778                 return;
5779
5780         if (rte_intr_allow_others(intr_handle))
5781                 vec = base = IXGBE_RX_VEC_START;
5782
5783         /* setup GPIE for MSI-x mode */
5784         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5785         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5786                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5787         /* auto clearing and auto setting corresponding bits in EIMS
5788          * when MSI-X interrupt is triggered
5789          */
5790         if (hw->mac.type == ixgbe_mac_82598EB) {
5791                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5792         } else {
5793                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5794                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5795         }
5796         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5797
5798         /* Populate the IVAR table and set the ITR values to the
5799          * corresponding register.
5800          */
5801         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5802              queue_id++) {
5803                 /* by default, 1:1 mapping */
5804                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5805                 intr_handle->intr_vec[queue_id] = vec;
5806                 if (vec < base + intr_handle->nb_efd - 1)
5807                         vec++;
5808         }
5809
5810         switch (hw->mac.type) {
5811         case ixgbe_mac_82598EB:
5812                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5813                                    IXGBE_MISC_VEC_ID);
5814                 break;
5815         case ixgbe_mac_82599EB:
5816         case ixgbe_mac_X540:
5817                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5818                 break;
5819         default:
5820                 break;
5821         }
5822         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5823                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5824
5825         /* set up to autoclear timer, and the vectors */
5826         mask = IXGBE_EIMS_ENABLE_MASK;
5827         mask &= ~(IXGBE_EIMS_OTHER |
5828                   IXGBE_EIMS_MAILBOX |
5829                   IXGBE_EIMS_LSC);
5830
5831         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5832 }
5833
5834 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5835         uint16_t queue_idx, uint16_t tx_rate)
5836 {
5837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5838         uint32_t rf_dec, rf_int;
5839         uint32_t bcnrc_val;
5840         uint16_t link_speed = dev->data->dev_link.link_speed;
5841
5842         if (queue_idx >= hw->mac.max_tx_queues)
5843                 return -EINVAL;
5844
5845         if (tx_rate != 0) {
5846                 /* Calculate the rate factor values to set */
5847                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5848                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5849                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5850
5851                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5852                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5853                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5854                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5855         } else {
5856                 bcnrc_val = 0;
5857         }
5858
5859         /*
5860          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5861          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5862          * set as 0x4.
5863          */
5864         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5865                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5866                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5867                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5868                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5869         else
5870                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5871                         IXGBE_MMW_SIZE_DEFAULT);
5872
5873         /* Set RTTBCNRC of queue X */
5874         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5875         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5876         IXGBE_WRITE_FLUSH(hw);
5877
5878         return 0;
5879 }
5880
5881 static void
5882 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5883                      __attribute__((unused)) uint32_t index,
5884                      __attribute__((unused)) uint32_t pool)
5885 {
5886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5887         int diag;
5888
5889         /*
5890          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5891          * operation. Trap this case to avoid exhausting the [very limited]
5892          * set of PF resources used to store VF MAC addresses.
5893          */
5894         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5895                 return;
5896         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5897         if (diag == 0)
5898                 return;
5899         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5900 }
5901
5902 static void
5903 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5904 {
5905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5907         struct ether_addr *mac_addr;
5908         uint32_t i;
5909         int diag;
5910
5911         /*
5912          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5913          * not support the deletion of a given MAC address.
5914          * Instead, it imposes to delete all MAC addresses, then to add again
5915          * all MAC addresses with the exception of the one to be deleted.
5916          */
5917         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5918
5919         /*
5920          * Add again all MAC addresses, with the exception of the deleted one
5921          * and of the permanent MAC address.
5922          */
5923         for (i = 0, mac_addr = dev->data->mac_addrs;
5924              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5925                 /* Skip the deleted MAC address */
5926                 if (i == index)
5927                         continue;
5928                 /* Skip NULL MAC addresses */
5929                 if (is_zero_ether_addr(mac_addr))
5930                         continue;
5931                 /* Skip the permanent MAC address */
5932                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5933                         continue;
5934                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5935                 if (diag != 0)
5936                         PMD_DRV_LOG(ERR,
5937                                     "Adding again MAC address "
5938                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5939                                     "diag=%d",
5940                                     mac_addr->addr_bytes[0],
5941                                     mac_addr->addr_bytes[1],
5942                                     mac_addr->addr_bytes[2],
5943                                     mac_addr->addr_bytes[3],
5944                                     mac_addr->addr_bytes[4],
5945                                     mac_addr->addr_bytes[5],
5946                                     diag);
5947         }
5948 }
5949
5950 static void
5951 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5952 {
5953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954
5955         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5956 }
5957
5958 #define MAC_TYPE_FILTER_SUP(type)    do {\
5959         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5960                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5961                 (type) != ixgbe_mac_X550EM_a)\
5962                 return -ENOTSUP;\
5963 } while (0)
5964
5965 int
5966 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5967                         struct rte_eth_syn_filter *filter,
5968                         bool add)
5969 {
5970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         struct ixgbe_filter_info *filter_info =
5972                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5973         uint32_t syn_info;
5974         uint32_t synqf;
5975
5976         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5977                 return -EINVAL;
5978
5979         syn_info = filter_info->syn_info;
5980
5981         if (add) {
5982                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5983                         return -EINVAL;
5984                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5985                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5986
5987                 if (filter->hig_pri)
5988                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5989                 else
5990                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5991         } else {
5992                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5993                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5994                         return -ENOENT;
5995                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5996         }
5997
5998         filter_info->syn_info = synqf;
5999         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6000         IXGBE_WRITE_FLUSH(hw);
6001         return 0;
6002 }
6003
6004 static int
6005 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6006                         struct rte_eth_syn_filter *filter)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6010
6011         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6012                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6013                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6014                 return 0;
6015         }
6016         return -ENOENT;
6017 }
6018
6019 static int
6020 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6021                         enum rte_filter_op filter_op,
6022                         void *arg)
6023 {
6024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025         int ret;
6026
6027         MAC_TYPE_FILTER_SUP(hw->mac.type);
6028
6029         if (filter_op == RTE_ETH_FILTER_NOP)
6030                 return 0;
6031
6032         if (arg == NULL) {
6033                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6034                             filter_op);
6035                 return -EINVAL;
6036         }
6037
6038         switch (filter_op) {
6039         case RTE_ETH_FILTER_ADD:
6040                 ret = ixgbe_syn_filter_set(dev,
6041                                 (struct rte_eth_syn_filter *)arg,
6042                                 TRUE);
6043                 break;
6044         case RTE_ETH_FILTER_DELETE:
6045                 ret = ixgbe_syn_filter_set(dev,
6046                                 (struct rte_eth_syn_filter *)arg,
6047                                 FALSE);
6048                 break;
6049         case RTE_ETH_FILTER_GET:
6050                 ret = ixgbe_syn_filter_get(dev,
6051                                 (struct rte_eth_syn_filter *)arg);
6052                 break;
6053         default:
6054                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6055                 ret = -EINVAL;
6056                 break;
6057         }
6058
6059         return ret;
6060 }
6061
6062
6063 static inline enum ixgbe_5tuple_protocol
6064 convert_protocol_type(uint8_t protocol_value)
6065 {
6066         if (protocol_value == IPPROTO_TCP)
6067                 return IXGBE_FILTER_PROTOCOL_TCP;
6068         else if (protocol_value == IPPROTO_UDP)
6069                 return IXGBE_FILTER_PROTOCOL_UDP;
6070         else if (protocol_value == IPPROTO_SCTP)
6071                 return IXGBE_FILTER_PROTOCOL_SCTP;
6072         else
6073                 return IXGBE_FILTER_PROTOCOL_NONE;
6074 }
6075
6076 /* inject a 5-tuple filter to HW */
6077 static inline void
6078 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6079                            struct ixgbe_5tuple_filter *filter)
6080 {
6081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082         int i;
6083         uint32_t ftqf, sdpqf;
6084         uint32_t l34timir = 0;
6085         uint8_t mask = 0xff;
6086
6087         i = filter->index;
6088
6089         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6090                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6091         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6092
6093         ftqf = (uint32_t)(filter->filter_info.proto &
6094                 IXGBE_FTQF_PROTOCOL_MASK);
6095         ftqf |= (uint32_t)((filter->filter_info.priority &
6096                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6097         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6098                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6099         if (filter->filter_info.dst_ip_mask == 0)
6100                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6101         if (filter->filter_info.src_port_mask == 0)
6102                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6103         if (filter->filter_info.dst_port_mask == 0)
6104                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6105         if (filter->filter_info.proto_mask == 0)
6106                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6107         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6108         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6109         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6110
6111         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6112         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6113         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6114         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6115
6116         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6117         l34timir |= (uint32_t)(filter->queue <<
6118                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6119         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6120 }
6121
6122 /*
6123  * add a 5tuple filter
6124  *
6125  * @param
6126  * dev: Pointer to struct rte_eth_dev.
6127  * index: the index the filter allocates.
6128  * filter: ponter to the filter that will be added.
6129  * rx_queue: the queue id the filter assigned to.
6130  *
6131  * @return
6132  *    - On success, zero.
6133  *    - On failure, a negative value.
6134  */
6135 static int
6136 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6137                         struct ixgbe_5tuple_filter *filter)
6138 {
6139         struct ixgbe_filter_info *filter_info =
6140                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6141         int i, idx, shift;
6142
6143         /*
6144          * look for an unused 5tuple filter index,
6145          * and insert the filter to list.
6146          */
6147         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6148                 idx = i / (sizeof(uint32_t) * NBBY);
6149                 shift = i % (sizeof(uint32_t) * NBBY);
6150                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6151                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6152                         filter->index = i;
6153                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6154                                           filter,
6155                                           entries);
6156                         break;
6157                 }
6158         }
6159         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6160                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6161                 return -ENOSYS;
6162         }
6163
6164         ixgbe_inject_5tuple_filter(dev, filter);
6165
6166         return 0;
6167 }
6168
6169 /*
6170  * remove a 5tuple filter
6171  *
6172  * @param
6173  * dev: Pointer to struct rte_eth_dev.
6174  * filter: the pointer of the filter will be removed.
6175  */
6176 static void
6177 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6178                         struct ixgbe_5tuple_filter *filter)
6179 {
6180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181         struct ixgbe_filter_info *filter_info =
6182                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6183         uint16_t index = filter->index;
6184
6185         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6186                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6187         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6188         rte_free(filter);
6189
6190         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6191         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6192         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6193         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6194         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6195 }
6196
6197 static int
6198 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6199 {
6200         struct ixgbe_hw *hw;
6201         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6202
6203         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6204
6205         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6206                 return -EINVAL;
6207
6208         /* refuse mtu that requires the support of scattered packets when this
6209          * feature has not been enabled before.
6210          */
6211         if (!dev->data->scattered_rx &&
6212             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6213              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6214                 return -EINVAL;
6215
6216         /*
6217          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6218          * request of the version 2.0 of the mailbox API.
6219          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6220          * of the mailbox API.
6221          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6222          * prior to 3.11.33 which contains the following change:
6223          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6224          */
6225         ixgbevf_rlpml_set_vf(hw, max_frame);
6226
6227         /* update max frame size */
6228         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6229         return 0;
6230 }
6231
6232 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6233         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6234                 return -ENOTSUP;\
6235 } while (0)
6236
6237 static inline struct ixgbe_5tuple_filter *
6238 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6239                         struct ixgbe_5tuple_filter_info *key)
6240 {
6241         struct ixgbe_5tuple_filter *it;
6242
6243         TAILQ_FOREACH(it, filter_list, entries) {
6244                 if (memcmp(key, &it->filter_info,
6245                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6246                         return it;
6247                 }
6248         }
6249         return NULL;
6250 }
6251
6252 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6253 static inline int
6254 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6255                         struct ixgbe_5tuple_filter_info *filter_info)
6256 {
6257         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6258                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6259                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6260                 return -EINVAL;
6261
6262         switch (filter->dst_ip_mask) {
6263         case UINT32_MAX:
6264                 filter_info->dst_ip_mask = 0;
6265                 filter_info->dst_ip = filter->dst_ip;
6266                 break;
6267         case 0:
6268                 filter_info->dst_ip_mask = 1;
6269                 break;
6270         default:
6271                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6272                 return -EINVAL;
6273         }
6274
6275         switch (filter->src_ip_mask) {
6276         case UINT32_MAX:
6277                 filter_info->src_ip_mask = 0;
6278                 filter_info->src_ip = filter->src_ip;
6279                 break;
6280         case 0:
6281                 filter_info->src_ip_mask = 1;
6282                 break;
6283         default:
6284                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6285                 return -EINVAL;
6286         }
6287
6288         switch (filter->dst_port_mask) {
6289         case UINT16_MAX:
6290                 filter_info->dst_port_mask = 0;
6291                 filter_info->dst_port = filter->dst_port;
6292                 break;
6293         case 0:
6294                 filter_info->dst_port_mask = 1;
6295                 break;
6296         default:
6297                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6298                 return -EINVAL;
6299         }
6300
6301         switch (filter->src_port_mask) {
6302         case UINT16_MAX:
6303                 filter_info->src_port_mask = 0;
6304                 filter_info->src_port = filter->src_port;
6305                 break;
6306         case 0:
6307                 filter_info->src_port_mask = 1;
6308                 break;
6309         default:
6310                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6311                 return -EINVAL;
6312         }
6313
6314         switch (filter->proto_mask) {
6315         case UINT8_MAX:
6316                 filter_info->proto_mask = 0;
6317                 filter_info->proto =
6318                         convert_protocol_type(filter->proto);
6319                 break;
6320         case 0:
6321                 filter_info->proto_mask = 1;
6322                 break;
6323         default:
6324                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6325                 return -EINVAL;
6326         }
6327
6328         filter_info->priority = (uint8_t)filter->priority;
6329         return 0;
6330 }
6331
6332 /*
6333  * add or delete a ntuple filter
6334  *
6335  * @param
6336  * dev: Pointer to struct rte_eth_dev.
6337  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6338  * add: if true, add filter, if false, remove filter
6339  *
6340  * @return
6341  *    - On success, zero.
6342  *    - On failure, a negative value.
6343  */
6344 int
6345 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6346                         struct rte_eth_ntuple_filter *ntuple_filter,
6347                         bool add)
6348 {
6349         struct ixgbe_filter_info *filter_info =
6350                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6351         struct ixgbe_5tuple_filter_info filter_5tuple;
6352         struct ixgbe_5tuple_filter *filter;
6353         int ret;
6354
6355         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6356                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6357                 return -EINVAL;
6358         }
6359
6360         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6361         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6362         if (ret < 0)
6363                 return ret;
6364
6365         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6366                                          &filter_5tuple);
6367         if (filter != NULL && add) {
6368                 PMD_DRV_LOG(ERR, "filter exists.");
6369                 return -EEXIST;
6370         }
6371         if (filter == NULL && !add) {
6372                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6373                 return -ENOENT;
6374         }
6375
6376         if (add) {
6377                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6378                                 sizeof(struct ixgbe_5tuple_filter), 0);
6379                 if (filter == NULL)
6380                         return -ENOMEM;
6381                 (void)rte_memcpy(&filter->filter_info,
6382                                  &filter_5tuple,
6383                                  sizeof(struct ixgbe_5tuple_filter_info));
6384                 filter->queue = ntuple_filter->queue;
6385                 ret = ixgbe_add_5tuple_filter(dev, filter);
6386                 if (ret < 0) {
6387                         rte_free(filter);
6388                         return ret;
6389                 }
6390         } else
6391                 ixgbe_remove_5tuple_filter(dev, filter);
6392
6393         return 0;
6394 }
6395
6396 /*
6397  * get a ntuple filter
6398  *
6399  * @param
6400  * dev: Pointer to struct rte_eth_dev.
6401  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6402  *
6403  * @return
6404  *    - On success, zero.
6405  *    - On failure, a negative value.
6406  */
6407 static int
6408 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6409                         struct rte_eth_ntuple_filter *ntuple_filter)
6410 {
6411         struct ixgbe_filter_info *filter_info =
6412                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6413         struct ixgbe_5tuple_filter_info filter_5tuple;
6414         struct ixgbe_5tuple_filter *filter;
6415         int ret;
6416
6417         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6418                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6419                 return -EINVAL;
6420         }
6421
6422         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6423         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6424         if (ret < 0)
6425                 return ret;
6426
6427         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6428                                          &filter_5tuple);
6429         if (filter == NULL) {
6430                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6431                 return -ENOENT;
6432         }
6433         ntuple_filter->queue = filter->queue;
6434         return 0;
6435 }
6436
6437 /*
6438  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6439  * @dev: pointer to rte_eth_dev structure
6440  * @filter_op:operation will be taken.
6441  * @arg: a pointer to specific structure corresponding to the filter_op
6442  *
6443  * @return
6444  *    - On success, zero.
6445  *    - On failure, a negative value.
6446  */
6447 static int
6448 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6449                                 enum rte_filter_op filter_op,
6450                                 void *arg)
6451 {
6452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6453         int ret;
6454
6455         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6456
6457         if (filter_op == RTE_ETH_FILTER_NOP)
6458                 return 0;
6459
6460         if (arg == NULL) {
6461                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6462                             filter_op);
6463                 return -EINVAL;
6464         }
6465
6466         switch (filter_op) {
6467         case RTE_ETH_FILTER_ADD:
6468                 ret = ixgbe_add_del_ntuple_filter(dev,
6469                         (struct rte_eth_ntuple_filter *)arg,
6470                         TRUE);
6471                 break;
6472         case RTE_ETH_FILTER_DELETE:
6473                 ret = ixgbe_add_del_ntuple_filter(dev,
6474                         (struct rte_eth_ntuple_filter *)arg,
6475                         FALSE);
6476                 break;
6477         case RTE_ETH_FILTER_GET:
6478                 ret = ixgbe_get_ntuple_filter(dev,
6479                         (struct rte_eth_ntuple_filter *)arg);
6480                 break;
6481         default:
6482                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6483                 ret = -EINVAL;
6484                 break;
6485         }
6486         return ret;
6487 }
6488
6489 int
6490 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6491                         struct rte_eth_ethertype_filter *filter,
6492                         bool add)
6493 {
6494         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495         struct ixgbe_filter_info *filter_info =
6496                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6497         uint32_t etqf = 0;
6498         uint32_t etqs = 0;
6499         int ret;
6500         struct ixgbe_ethertype_filter ethertype_filter;
6501
6502         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6503                 return -EINVAL;
6504
6505         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6506                 filter->ether_type == ETHER_TYPE_IPv6) {
6507                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6508                         " ethertype filter.", filter->ether_type);
6509                 return -EINVAL;
6510         }
6511
6512         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6513                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6514                 return -EINVAL;
6515         }
6516         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6517                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6518                 return -EINVAL;
6519         }
6520
6521         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6522         if (ret >= 0 && add) {
6523                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6524                             filter->ether_type);
6525                 return -EEXIST;
6526         }
6527         if (ret < 0 && !add) {
6528                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6529                             filter->ether_type);
6530                 return -ENOENT;
6531         }
6532
6533         if (add) {
6534                 etqf = IXGBE_ETQF_FILTER_EN;
6535                 etqf |= (uint32_t)filter->ether_type;
6536                 etqs |= (uint32_t)((filter->queue <<
6537                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6538                                     IXGBE_ETQS_RX_QUEUE);
6539                 etqs |= IXGBE_ETQS_QUEUE_EN;
6540
6541                 ethertype_filter.ethertype = filter->ether_type;
6542                 ethertype_filter.etqf = etqf;
6543                 ethertype_filter.etqs = etqs;
6544                 ethertype_filter.conf = FALSE;
6545                 ret = ixgbe_ethertype_filter_insert(filter_info,
6546                                                     &ethertype_filter);
6547                 if (ret < 0) {
6548                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6549                         return -ENOSPC;
6550                 }
6551         } else {
6552                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6553                 if (ret < 0)
6554                         return -ENOSYS;
6555         }
6556         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6557         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6558         IXGBE_WRITE_FLUSH(hw);
6559
6560         return 0;
6561 }
6562
6563 static int
6564 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6565                         struct rte_eth_ethertype_filter *filter)
6566 {
6567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6568         struct ixgbe_filter_info *filter_info =
6569                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6570         uint32_t etqf, etqs;
6571         int ret;
6572
6573         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6574         if (ret < 0) {
6575                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6576                             filter->ether_type);
6577                 return -ENOENT;
6578         }
6579
6580         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6581         if (etqf & IXGBE_ETQF_FILTER_EN) {
6582                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6583                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6584                 filter->flags = 0;
6585                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6586                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6587                 return 0;
6588         }
6589         return -ENOENT;
6590 }
6591
6592 /*
6593  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6594  * @dev: pointer to rte_eth_dev structure
6595  * @filter_op:operation will be taken.
6596  * @arg: a pointer to specific structure corresponding to the filter_op
6597  */
6598 static int
6599 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6600                                 enum rte_filter_op filter_op,
6601                                 void *arg)
6602 {
6603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         int ret;
6605
6606         MAC_TYPE_FILTER_SUP(hw->mac.type);
6607
6608         if (filter_op == RTE_ETH_FILTER_NOP)
6609                 return 0;
6610
6611         if (arg == NULL) {
6612                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6613                             filter_op);
6614                 return -EINVAL;
6615         }
6616
6617         switch (filter_op) {
6618         case RTE_ETH_FILTER_ADD:
6619                 ret = ixgbe_add_del_ethertype_filter(dev,
6620                         (struct rte_eth_ethertype_filter *)arg,
6621                         TRUE);
6622                 break;
6623         case RTE_ETH_FILTER_DELETE:
6624                 ret = ixgbe_add_del_ethertype_filter(dev,
6625                         (struct rte_eth_ethertype_filter *)arg,
6626                         FALSE);
6627                 break;
6628         case RTE_ETH_FILTER_GET:
6629                 ret = ixgbe_get_ethertype_filter(dev,
6630                         (struct rte_eth_ethertype_filter *)arg);
6631                 break;
6632         default:
6633                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6634                 ret = -EINVAL;
6635                 break;
6636         }
6637         return ret;
6638 }
6639
6640 static int
6641 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6642                      enum rte_filter_type filter_type,
6643                      enum rte_filter_op filter_op,
6644                      void *arg)
6645 {
6646         int ret = 0;
6647
6648         switch (filter_type) {
6649         case RTE_ETH_FILTER_NTUPLE:
6650                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_ETHERTYPE:
6653                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6654                 break;
6655         case RTE_ETH_FILTER_SYN:
6656                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6657                 break;
6658         case RTE_ETH_FILTER_FDIR:
6659                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6660                 break;
6661         case RTE_ETH_FILTER_L2_TUNNEL:
6662                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6663                 break;
6664         case RTE_ETH_FILTER_GENERIC:
6665                 if (filter_op != RTE_ETH_FILTER_GET)
6666                         return -EINVAL;
6667                 *(const void **)arg = &ixgbe_flow_ops;
6668                 break;
6669         default:
6670                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6671                                                         filter_type);
6672                 ret = -EINVAL;
6673                 break;
6674         }
6675
6676         return ret;
6677 }
6678
6679 static u8 *
6680 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6681                         u8 **mc_addr_ptr, u32 *vmdq)
6682 {
6683         u8 *mc_addr;
6684
6685         *vmdq = 0;
6686         mc_addr = *mc_addr_ptr;
6687         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6688         return mc_addr;
6689 }
6690
6691 static int
6692 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6693                           struct ether_addr *mc_addr_set,
6694                           uint32_t nb_mc_addr)
6695 {
6696         struct ixgbe_hw *hw;
6697         u8 *mc_addr_list;
6698
6699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         mc_addr_list = (u8 *)mc_addr_set;
6701         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6702                                          ixgbe_dev_addr_list_itr, TRUE);
6703 }
6704
6705 static uint64_t
6706 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6707 {
6708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709         uint64_t systime_cycles;
6710
6711         switch (hw->mac.type) {
6712         case ixgbe_mac_X550:
6713         case ixgbe_mac_X550EM_x:
6714         case ixgbe_mac_X550EM_a:
6715                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6716                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6717                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6718                                 * NSEC_PER_SEC;
6719                 break;
6720         default:
6721                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6722                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6723                                 << 32;
6724         }
6725
6726         return systime_cycles;
6727 }
6728
6729 static uint64_t
6730 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6731 {
6732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733         uint64_t rx_tstamp_cycles;
6734
6735         switch (hw->mac.type) {
6736         case ixgbe_mac_X550:
6737         case ixgbe_mac_X550EM_x:
6738         case ixgbe_mac_X550EM_a:
6739                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6740                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6741                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6742                                 * NSEC_PER_SEC;
6743                 break;
6744         default:
6745                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6746                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6747                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6748                                 << 32;
6749         }
6750
6751         return rx_tstamp_cycles;
6752 }
6753
6754 static uint64_t
6755 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6756 {
6757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758         uint64_t tx_tstamp_cycles;
6759
6760         switch (hw->mac.type) {
6761         case ixgbe_mac_X550:
6762         case ixgbe_mac_X550EM_x:
6763         case ixgbe_mac_X550EM_a:
6764                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6765                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6766                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6767                                 * NSEC_PER_SEC;
6768                 break;
6769         default:
6770                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6771                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6772                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6773                                 << 32;
6774         }
6775
6776         return tx_tstamp_cycles;
6777 }
6778
6779 static void
6780 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         struct ixgbe_adapter *adapter =
6784                 (struct ixgbe_adapter *)dev->data->dev_private;
6785         struct rte_eth_link link;
6786         uint32_t incval = 0;
6787         uint32_t shift = 0;
6788
6789         /* Get current link speed. */
6790         memset(&link, 0, sizeof(link));
6791         ixgbe_dev_link_update(dev, 1);
6792         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6793
6794         switch (link.link_speed) {
6795         case ETH_SPEED_NUM_100M:
6796                 incval = IXGBE_INCVAL_100;
6797                 shift = IXGBE_INCVAL_SHIFT_100;
6798                 break;
6799         case ETH_SPEED_NUM_1G:
6800                 incval = IXGBE_INCVAL_1GB;
6801                 shift = IXGBE_INCVAL_SHIFT_1GB;
6802                 break;
6803         case ETH_SPEED_NUM_10G:
6804         default:
6805                 incval = IXGBE_INCVAL_10GB;
6806                 shift = IXGBE_INCVAL_SHIFT_10GB;
6807                 break;
6808         }
6809
6810         switch (hw->mac.type) {
6811         case ixgbe_mac_X550:
6812         case ixgbe_mac_X550EM_x:
6813         case ixgbe_mac_X550EM_a:
6814                 /* Independent of link speed. */
6815                 incval = 1;
6816                 /* Cycles read will be interpreted as ns. */
6817                 shift = 0;
6818                 /* Fall-through */
6819         case ixgbe_mac_X540:
6820                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6821                 break;
6822         case ixgbe_mac_82599EB:
6823                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6824                 shift -= IXGBE_INCVAL_SHIFT_82599;
6825                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6826                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6827                 break;
6828         default:
6829                 /* Not supported. */
6830                 return;
6831         }
6832
6833         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6834         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6835         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6836
6837         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6838         adapter->systime_tc.cc_shift = shift;
6839         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6840
6841         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6842         adapter->rx_tstamp_tc.cc_shift = shift;
6843         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6844
6845         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6846         adapter->tx_tstamp_tc.cc_shift = shift;
6847         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6848 }
6849
6850 static int
6851 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6852 {
6853         struct ixgbe_adapter *adapter =
6854                         (struct ixgbe_adapter *)dev->data->dev_private;
6855
6856         adapter->systime_tc.nsec += delta;
6857         adapter->rx_tstamp_tc.nsec += delta;
6858         adapter->tx_tstamp_tc.nsec += delta;
6859
6860         return 0;
6861 }
6862
6863 static int
6864 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6865 {
6866         uint64_t ns;
6867         struct ixgbe_adapter *adapter =
6868                         (struct ixgbe_adapter *)dev->data->dev_private;
6869
6870         ns = rte_timespec_to_ns(ts);
6871         /* Set the timecounters to a new value. */
6872         adapter->systime_tc.nsec = ns;
6873         adapter->rx_tstamp_tc.nsec = ns;
6874         adapter->tx_tstamp_tc.nsec = ns;
6875
6876         return 0;
6877 }
6878
6879 static int
6880 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6881 {
6882         uint64_t ns, systime_cycles;
6883         struct ixgbe_adapter *adapter =
6884                         (struct ixgbe_adapter *)dev->data->dev_private;
6885
6886         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6887         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6888         *ts = rte_ns_to_timespec(ns);
6889
6890         return 0;
6891 }
6892
6893 static int
6894 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         uint32_t tsync_ctl;
6898         uint32_t tsauxc;
6899
6900         /* Stop the timesync system time. */
6901         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6902         /* Reset the timesync system time value. */
6903         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6904         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6905
6906         /* Enable system time for platforms where it isn't on by default. */
6907         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6908         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6910
6911         ixgbe_start_timecounters(dev);
6912
6913         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6914         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6915                         (ETHER_TYPE_1588 |
6916                          IXGBE_ETQF_FILTER_EN |
6917                          IXGBE_ETQF_1588));
6918
6919         /* Enable timestamping of received PTP packets. */
6920         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6921         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6922         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6923
6924         /* Enable timestamping of transmitted PTP packets. */
6925         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6926         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6927         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6928
6929         IXGBE_WRITE_FLUSH(hw);
6930
6931         return 0;
6932 }
6933
6934 static int
6935 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6936 {
6937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6938         uint32_t tsync_ctl;
6939
6940         /* Disable timestamping of transmitted PTP packets. */
6941         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6942         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6943         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6944
6945         /* Disable timestamping of received PTP packets. */
6946         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6947         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6948         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6949
6950         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6951         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6952
6953         /* Stop incrementating the System Time registers. */
6954         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6955
6956         return 0;
6957 }
6958
6959 static int
6960 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6961                                  struct timespec *timestamp,
6962                                  uint32_t flags __rte_unused)
6963 {
6964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6965         struct ixgbe_adapter *adapter =
6966                 (struct ixgbe_adapter *)dev->data->dev_private;
6967         uint32_t tsync_rxctl;
6968         uint64_t rx_tstamp_cycles;
6969         uint64_t ns;
6970
6971         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6972         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6973                 return -EINVAL;
6974
6975         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6976         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6977         *timestamp = rte_ns_to_timespec(ns);
6978
6979         return  0;
6980 }
6981
6982 static int
6983 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6984                                  struct timespec *timestamp)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         struct ixgbe_adapter *adapter =
6988                 (struct ixgbe_adapter *)dev->data->dev_private;
6989         uint32_t tsync_txctl;
6990         uint64_t tx_tstamp_cycles;
6991         uint64_t ns;
6992
6993         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6994         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6995                 return -EINVAL;
6996
6997         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6998         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6999         *timestamp = rte_ns_to_timespec(ns);
7000
7001         return 0;
7002 }
7003
7004 static int
7005 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7006 {
7007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7008         int count = 0;
7009         int g_ind = 0;
7010         const struct reg_info *reg_group;
7011         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7012                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7013
7014         while ((reg_group = reg_set[g_ind++]))
7015                 count += ixgbe_regs_group_count(reg_group);
7016
7017         return count;
7018 }
7019
7020 static int
7021 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7022 {
7023         int count = 0;
7024         int g_ind = 0;
7025         const struct reg_info *reg_group;
7026
7027         while ((reg_group = ixgbevf_regs[g_ind++]))
7028                 count += ixgbe_regs_group_count(reg_group);
7029
7030         return count;
7031 }
7032
7033 static int
7034 ixgbe_get_regs(struct rte_eth_dev *dev,
7035               struct rte_dev_reg_info *regs)
7036 {
7037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7038         uint32_t *data = regs->data;
7039         int g_ind = 0;
7040         int count = 0;
7041         const struct reg_info *reg_group;
7042         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7043                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7044
7045         if (data == NULL) {
7046                 regs->length = ixgbe_get_reg_length(dev);
7047                 regs->width = sizeof(uint32_t);
7048                 return 0;
7049         }
7050
7051         /* Support only full register dump */
7052         if ((regs->length == 0) ||
7053             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7054                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7055                         hw->device_id;
7056                 while ((reg_group = reg_set[g_ind++]))
7057                         count += ixgbe_read_regs_group(dev, &data[count],
7058                                 reg_group);
7059                 return 0;
7060         }
7061
7062         return -ENOTSUP;
7063 }
7064
7065 static int
7066 ixgbevf_get_regs(struct rte_eth_dev *dev,
7067                 struct rte_dev_reg_info *regs)
7068 {
7069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7070         uint32_t *data = regs->data;
7071         int g_ind = 0;
7072         int count = 0;
7073         const struct reg_info *reg_group;
7074
7075         if (data == NULL) {
7076                 regs->length = ixgbevf_get_reg_length(dev);
7077                 regs->width = sizeof(uint32_t);
7078                 return 0;
7079         }
7080
7081         /* Support only full register dump */
7082         if ((regs->length == 0) ||
7083             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7084                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7085                         hw->device_id;
7086                 while ((reg_group = ixgbevf_regs[g_ind++]))
7087                         count += ixgbe_read_regs_group(dev, &data[count],
7088                                                       reg_group);
7089                 return 0;
7090         }
7091
7092         return -ENOTSUP;
7093 }
7094
7095 static int
7096 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7097 {
7098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099
7100         /* Return unit is byte count */
7101         return hw->eeprom.word_size * 2;
7102 }
7103
7104 static int
7105 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7106                 struct rte_dev_eeprom_info *in_eeprom)
7107 {
7108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7110         uint16_t *data = in_eeprom->data;
7111         int first, length;
7112
7113         first = in_eeprom->offset >> 1;
7114         length = in_eeprom->length >> 1;
7115         if ((first > hw->eeprom.word_size) ||
7116             ((first + length) > hw->eeprom.word_size))
7117                 return -EINVAL;
7118
7119         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7120
7121         return eeprom->ops.read_buffer(hw, first, length, data);
7122 }
7123
7124 static int
7125 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7126                 struct rte_dev_eeprom_info *in_eeprom)
7127 {
7128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7130         uint16_t *data = in_eeprom->data;
7131         int first, length;
7132
7133         first = in_eeprom->offset >> 1;
7134         length = in_eeprom->length >> 1;
7135         if ((first > hw->eeprom.word_size) ||
7136             ((first + length) > hw->eeprom.word_size))
7137                 return -EINVAL;
7138
7139         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7140
7141         return eeprom->ops.write_buffer(hw,  first, length, data);
7142 }
7143
7144 uint16_t
7145 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7146         switch (mac_type) {
7147         case ixgbe_mac_X550:
7148         case ixgbe_mac_X550EM_x:
7149         case ixgbe_mac_X550EM_a:
7150                 return ETH_RSS_RETA_SIZE_512;
7151         case ixgbe_mac_X550_vf:
7152         case ixgbe_mac_X550EM_x_vf:
7153         case ixgbe_mac_X550EM_a_vf:
7154                 return ETH_RSS_RETA_SIZE_64;
7155         default:
7156                 return ETH_RSS_RETA_SIZE_128;
7157         }
7158 }
7159
7160 uint32_t
7161 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7162         switch (mac_type) {
7163         case ixgbe_mac_X550:
7164         case ixgbe_mac_X550EM_x:
7165         case ixgbe_mac_X550EM_a:
7166                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7167                         return IXGBE_RETA(reta_idx >> 2);
7168                 else
7169                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7170         case ixgbe_mac_X550_vf:
7171         case ixgbe_mac_X550EM_x_vf:
7172         case ixgbe_mac_X550EM_a_vf:
7173                 return IXGBE_VFRETA(reta_idx >> 2);
7174         default:
7175                 return IXGBE_RETA(reta_idx >> 2);
7176         }
7177 }
7178
7179 uint32_t
7180 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7181         switch (mac_type) {
7182         case ixgbe_mac_X550_vf:
7183         case ixgbe_mac_X550EM_x_vf:
7184         case ixgbe_mac_X550EM_a_vf:
7185                 return IXGBE_VFMRQC;
7186         default:
7187                 return IXGBE_MRQC;
7188         }
7189 }
7190
7191 uint32_t
7192 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7193         switch (mac_type) {
7194         case ixgbe_mac_X550_vf:
7195         case ixgbe_mac_X550EM_x_vf:
7196         case ixgbe_mac_X550EM_a_vf:
7197                 return IXGBE_VFRSSRK(i);
7198         default:
7199                 return IXGBE_RSSRK(i);
7200         }
7201 }
7202
7203 bool
7204 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7205         switch (mac_type) {
7206         case ixgbe_mac_82599_vf:
7207         case ixgbe_mac_X540_vf:
7208                 return 0;
7209         default:
7210                 return 1;
7211         }
7212 }
7213
7214 static int
7215 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7216                         struct rte_eth_dcb_info *dcb_info)
7217 {
7218         struct ixgbe_dcb_config *dcb_config =
7219                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7220         struct ixgbe_dcb_tc_config *tc;
7221         uint8_t i, j;
7222
7223         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7224                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7225         else
7226                 dcb_info->nb_tcs = 1;
7227
7228         if (dcb_config->vt_mode) { /* vt is enabled*/
7229                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7230                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7231                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7232                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7233                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7234                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7235                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7236                                                 i * dcb_info->nb_tcs + j;
7237                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7238                                 dcb_info->tc_queue.tc_txq[i][j].base =
7239                                                 i * dcb_info->nb_tcs + j;
7240                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7241                         }
7242                 }
7243         } else { /* vt is disabled*/
7244                 struct rte_eth_dcb_rx_conf *rx_conf =
7245                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7246                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7247                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7248                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7249                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7250                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7251                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7252                         }
7253                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7254                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7255                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7256                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7257                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7258                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7259                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7260                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7261                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7262                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7263                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7264                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7265                         }
7266                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7267                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7268                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7269                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7270                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7271                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7272                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7273                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7274                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7275                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7276                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7277                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7278                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7279                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7280                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7281                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7282                 }
7283         }
7284         for (i = 0; i < dcb_info->nb_tcs; i++) {
7285                 tc = &dcb_config->tc_config[i];
7286                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7287         }
7288         return 0;
7289 }
7290
7291 /* Update e-tag ether type */
7292 static int
7293 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7294                             uint16_t ether_type)
7295 {
7296         uint32_t etag_etype;
7297
7298         if (hw->mac.type != ixgbe_mac_X550 &&
7299             hw->mac.type != ixgbe_mac_X550EM_x &&
7300             hw->mac.type != ixgbe_mac_X550EM_a) {
7301                 return -ENOTSUP;
7302         }
7303
7304         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7305         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7306         etag_etype |= ether_type;
7307         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7308         IXGBE_WRITE_FLUSH(hw);
7309
7310         return 0;
7311 }
7312
7313 /* Config l2 tunnel ether type */
7314 static int
7315 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7316                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7317 {
7318         int ret = 0;
7319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7320         struct ixgbe_l2_tn_info *l2_tn_info =
7321                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7322
7323         if (l2_tunnel == NULL)
7324                 return -EINVAL;
7325
7326         switch (l2_tunnel->l2_tunnel_type) {
7327         case RTE_L2_TUNNEL_TYPE_E_TAG:
7328                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7329                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7330                 break;
7331         default:
7332                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7333                 ret = -EINVAL;
7334                 break;
7335         }
7336
7337         return ret;
7338 }
7339
7340 /* Enable e-tag tunnel */
7341 static int
7342 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7343 {
7344         uint32_t etag_etype;
7345
7346         if (hw->mac.type != ixgbe_mac_X550 &&
7347             hw->mac.type != ixgbe_mac_X550EM_x &&
7348             hw->mac.type != ixgbe_mac_X550EM_a) {
7349                 return -ENOTSUP;
7350         }
7351
7352         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7353         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7354         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7355         IXGBE_WRITE_FLUSH(hw);
7356
7357         return 0;
7358 }
7359
7360 /* Enable l2 tunnel */
7361 static int
7362 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7363                            enum rte_eth_tunnel_type l2_tunnel_type)
7364 {
7365         int ret = 0;
7366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7367         struct ixgbe_l2_tn_info *l2_tn_info =
7368                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7369
7370         switch (l2_tunnel_type) {
7371         case RTE_L2_TUNNEL_TYPE_E_TAG:
7372                 l2_tn_info->e_tag_en = TRUE;
7373                 ret = ixgbe_e_tag_enable(hw);
7374                 break;
7375         default:
7376                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7377                 ret = -EINVAL;
7378                 break;
7379         }
7380
7381         return ret;
7382 }
7383
7384 /* Disable e-tag tunnel */
7385 static int
7386 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7387 {
7388         uint32_t etag_etype;
7389
7390         if (hw->mac.type != ixgbe_mac_X550 &&
7391             hw->mac.type != ixgbe_mac_X550EM_x &&
7392             hw->mac.type != ixgbe_mac_X550EM_a) {
7393                 return -ENOTSUP;
7394         }
7395
7396         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7397         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7398         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7399         IXGBE_WRITE_FLUSH(hw);
7400
7401         return 0;
7402 }
7403
7404 /* Disable l2 tunnel */
7405 static int
7406 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7407                             enum rte_eth_tunnel_type l2_tunnel_type)
7408 {
7409         int ret = 0;
7410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7411         struct ixgbe_l2_tn_info *l2_tn_info =
7412                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7413
7414         switch (l2_tunnel_type) {
7415         case RTE_L2_TUNNEL_TYPE_E_TAG:
7416                 l2_tn_info->e_tag_en = FALSE;
7417                 ret = ixgbe_e_tag_disable(hw);
7418                 break;
7419         default:
7420                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7421                 ret = -EINVAL;
7422                 break;
7423         }
7424
7425         return ret;
7426 }
7427
7428 static int
7429 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7430                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7431 {
7432         int ret = 0;
7433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7434         uint32_t i, rar_entries;
7435         uint32_t rar_low, rar_high;
7436
7437         if (hw->mac.type != ixgbe_mac_X550 &&
7438             hw->mac.type != ixgbe_mac_X550EM_x &&
7439             hw->mac.type != ixgbe_mac_X550EM_a) {
7440                 return -ENOTSUP;
7441         }
7442
7443         rar_entries = ixgbe_get_num_rx_addrs(hw);
7444
7445         for (i = 1; i < rar_entries; i++) {
7446                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7447                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7448                 if ((rar_high & IXGBE_RAH_AV) &&
7449                     (rar_high & IXGBE_RAH_ADTYPE) &&
7450                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7451                      l2_tunnel->tunnel_id)) {
7452                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7453                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7454
7455                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7456
7457                         return ret;
7458                 }
7459         }
7460
7461         return ret;
7462 }
7463
7464 static int
7465 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7466                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7467 {
7468         int ret = 0;
7469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint32_t i, rar_entries;
7471         uint32_t rar_low, rar_high;
7472
7473         if (hw->mac.type != ixgbe_mac_X550 &&
7474             hw->mac.type != ixgbe_mac_X550EM_x &&
7475             hw->mac.type != ixgbe_mac_X550EM_a) {
7476                 return -ENOTSUP;
7477         }
7478
7479         /* One entry for one tunnel. Try to remove potential existing entry. */
7480         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7481
7482         rar_entries = ixgbe_get_num_rx_addrs(hw);
7483
7484         for (i = 1; i < rar_entries; i++) {
7485                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7486                 if (rar_high & IXGBE_RAH_AV) {
7487                         continue;
7488                 } else {
7489                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7490                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7491                         rar_low = l2_tunnel->tunnel_id;
7492
7493                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7494                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7495
7496                         return ret;
7497                 }
7498         }
7499
7500         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7501                      " Please remove a rule before adding a new one.");
7502         return -EINVAL;
7503 }
7504
7505 static inline struct ixgbe_l2_tn_filter *
7506 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7507                           struct ixgbe_l2_tn_key *key)
7508 {
7509         int ret;
7510
7511         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7512         if (ret < 0)
7513                 return NULL;
7514
7515         return l2_tn_info->hash_map[ret];
7516 }
7517
7518 static inline int
7519 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7520                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7521 {
7522         int ret;
7523
7524         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7525                                &l2_tn_filter->key);
7526
7527         if (ret < 0) {
7528                 PMD_DRV_LOG(ERR,
7529                             "Failed to insert L2 tunnel filter"
7530                             " to hash table %d!",
7531                             ret);
7532                 return ret;
7533         }
7534
7535         l2_tn_info->hash_map[ret] = l2_tn_filter;
7536
7537         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7538
7539         return 0;
7540 }
7541
7542 static inline int
7543 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7544                           struct ixgbe_l2_tn_key *key)
7545 {
7546         int ret;
7547         struct ixgbe_l2_tn_filter *l2_tn_filter;
7548
7549         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7550
7551         if (ret < 0) {
7552                 PMD_DRV_LOG(ERR,
7553                             "No such L2 tunnel filter to delete %d!",
7554                             ret);
7555                 return ret;
7556         }
7557
7558         l2_tn_filter = l2_tn_info->hash_map[ret];
7559         l2_tn_info->hash_map[ret] = NULL;
7560
7561         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7562         rte_free(l2_tn_filter);
7563
7564         return 0;
7565 }
7566
7567 /* Add l2 tunnel filter */
7568 int
7569 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7570                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7571                                bool restore)
7572 {
7573         int ret;
7574         struct ixgbe_l2_tn_info *l2_tn_info =
7575                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7576         struct ixgbe_l2_tn_key key;
7577         struct ixgbe_l2_tn_filter *node;
7578
7579         if (!restore) {
7580                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7581                 key.tn_id = l2_tunnel->tunnel_id;
7582
7583                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7584
7585                 if (node) {
7586                         PMD_DRV_LOG(ERR,
7587                                     "The L2 tunnel filter already exists!");
7588                         return -EINVAL;
7589                 }
7590
7591                 node = rte_zmalloc("ixgbe_l2_tn",
7592                                    sizeof(struct ixgbe_l2_tn_filter),
7593                                    0);
7594                 if (!node)
7595                         return -ENOMEM;
7596
7597                 (void)rte_memcpy(&node->key,
7598                                  &key,
7599                                  sizeof(struct ixgbe_l2_tn_key));
7600                 node->pool = l2_tunnel->pool;
7601                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7602                 if (ret < 0) {
7603                         rte_free(node);
7604                         return ret;
7605                 }
7606         }
7607
7608         switch (l2_tunnel->l2_tunnel_type) {
7609         case RTE_L2_TUNNEL_TYPE_E_TAG:
7610                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7611                 break;
7612         default:
7613                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7614                 ret = -EINVAL;
7615                 break;
7616         }
7617
7618         if ((!restore) && (ret < 0))
7619                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7620
7621         return ret;
7622 }
7623
7624 /* Delete l2 tunnel filter */
7625 int
7626 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7627                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7628 {
7629         int ret;
7630         struct ixgbe_l2_tn_info *l2_tn_info =
7631                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7632         struct ixgbe_l2_tn_key key;
7633
7634         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7635         key.tn_id = l2_tunnel->tunnel_id;
7636         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7637         if (ret < 0)
7638                 return ret;
7639
7640         switch (l2_tunnel->l2_tunnel_type) {
7641         case RTE_L2_TUNNEL_TYPE_E_TAG:
7642                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 /**
7654  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7655  * @dev: pointer to rte_eth_dev structure
7656  * @filter_op:operation will be taken.
7657  * @arg: a pointer to specific structure corresponding to the filter_op
7658  */
7659 static int
7660 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7661                                   enum rte_filter_op filter_op,
7662                                   void *arg)
7663 {
7664         int ret;
7665
7666         if (filter_op == RTE_ETH_FILTER_NOP)
7667                 return 0;
7668
7669         if (arg == NULL) {
7670                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7671                             filter_op);
7672                 return -EINVAL;
7673         }
7674
7675         switch (filter_op) {
7676         case RTE_ETH_FILTER_ADD:
7677                 ret = ixgbe_dev_l2_tunnel_filter_add
7678                         (dev,
7679                          (struct rte_eth_l2_tunnel_conf *)arg,
7680                          FALSE);
7681                 break;
7682         case RTE_ETH_FILTER_DELETE:
7683                 ret = ixgbe_dev_l2_tunnel_filter_del
7684                         (dev,
7685                          (struct rte_eth_l2_tunnel_conf *)arg);
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7689                 ret = -EINVAL;
7690                 break;
7691         }
7692         return ret;
7693 }
7694
7695 static int
7696 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7697 {
7698         int ret = 0;
7699         uint32_t ctrl;
7700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7701
7702         if (hw->mac.type != ixgbe_mac_X550 &&
7703             hw->mac.type != ixgbe_mac_X550EM_x &&
7704             hw->mac.type != ixgbe_mac_X550EM_a) {
7705                 return -ENOTSUP;
7706         }
7707
7708         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7709         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7710         if (en)
7711                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7712         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7713
7714         return ret;
7715 }
7716
7717 /* Enable l2 tunnel forwarding */
7718 static int
7719 ixgbe_dev_l2_tunnel_forwarding_enable
7720         (struct rte_eth_dev *dev,
7721          enum rte_eth_tunnel_type l2_tunnel_type)
7722 {
7723         struct ixgbe_l2_tn_info *l2_tn_info =
7724                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7725         int ret = 0;
7726
7727         switch (l2_tunnel_type) {
7728         case RTE_L2_TUNNEL_TYPE_E_TAG:
7729                 l2_tn_info->e_tag_fwd_en = TRUE;
7730                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7731                 break;
7732         default:
7733                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734                 ret = -EINVAL;
7735                 break;
7736         }
7737
7738         return ret;
7739 }
7740
7741 /* Disable l2 tunnel forwarding */
7742 static int
7743 ixgbe_dev_l2_tunnel_forwarding_disable
7744         (struct rte_eth_dev *dev,
7745          enum rte_eth_tunnel_type l2_tunnel_type)
7746 {
7747         struct ixgbe_l2_tn_info *l2_tn_info =
7748                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7749         int ret = 0;
7750
7751         switch (l2_tunnel_type) {
7752         case RTE_L2_TUNNEL_TYPE_E_TAG:
7753                 l2_tn_info->e_tag_fwd_en = FALSE;
7754                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7755                 break;
7756         default:
7757                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7758                 ret = -EINVAL;
7759                 break;
7760         }
7761
7762         return ret;
7763 }
7764
7765 static int
7766 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7767                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7768                              bool en)
7769 {
7770         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7771         int ret = 0;
7772         uint32_t vmtir, vmvir;
7773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7774
7775         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7776                 PMD_DRV_LOG(ERR,
7777                             "VF id %u should be less than %u",
7778                             l2_tunnel->vf_id,
7779                             pci_dev->max_vfs);
7780                 return -EINVAL;
7781         }
7782
7783         if (hw->mac.type != ixgbe_mac_X550 &&
7784             hw->mac.type != ixgbe_mac_X550EM_x &&
7785             hw->mac.type != ixgbe_mac_X550EM_a) {
7786                 return -ENOTSUP;
7787         }
7788
7789         if (en)
7790                 vmtir = l2_tunnel->tunnel_id;
7791         else
7792                 vmtir = 0;
7793
7794         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7795
7796         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7797         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7798         if (en)
7799                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7800         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7801
7802         return ret;
7803 }
7804
7805 /* Enable l2 tunnel tag insertion */
7806 static int
7807 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7808                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7809 {
7810         int ret = 0;
7811
7812         switch (l2_tunnel->l2_tunnel_type) {
7813         case RTE_L2_TUNNEL_TYPE_E_TAG:
7814                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7815                 break;
7816         default:
7817                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7818                 ret = -EINVAL;
7819                 break;
7820         }
7821
7822         return ret;
7823 }
7824
7825 /* Disable l2 tunnel tag insertion */
7826 static int
7827 ixgbe_dev_l2_tunnel_insertion_disable
7828         (struct rte_eth_dev *dev,
7829          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7830 {
7831         int ret = 0;
7832
7833         switch (l2_tunnel->l2_tunnel_type) {
7834         case RTE_L2_TUNNEL_TYPE_E_TAG:
7835                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7836                 break;
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -EINVAL;
7840                 break;
7841         }
7842
7843         return ret;
7844 }
7845
7846 static int
7847 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7848                              bool en)
7849 {
7850         int ret = 0;
7851         uint32_t qde;
7852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7853
7854         if (hw->mac.type != ixgbe_mac_X550 &&
7855             hw->mac.type != ixgbe_mac_X550EM_x &&
7856             hw->mac.type != ixgbe_mac_X550EM_a) {
7857                 return -ENOTSUP;
7858         }
7859
7860         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7861         if (en)
7862                 qde |= IXGBE_QDE_STRIP_TAG;
7863         else
7864                 qde &= ~IXGBE_QDE_STRIP_TAG;
7865         qde &= ~IXGBE_QDE_READ;
7866         qde |= IXGBE_QDE_WRITE;
7867         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7868
7869         return ret;
7870 }
7871
7872 /* Enable l2 tunnel tag stripping */
7873 static int
7874 ixgbe_dev_l2_tunnel_stripping_enable
7875         (struct rte_eth_dev *dev,
7876          enum rte_eth_tunnel_type l2_tunnel_type)
7877 {
7878         int ret = 0;
7879
7880         switch (l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 /* Disable l2 tunnel tag stripping */
7894 static int
7895 ixgbe_dev_l2_tunnel_stripping_disable
7896         (struct rte_eth_dev *dev,
7897          enum rte_eth_tunnel_type l2_tunnel_type)
7898 {
7899         int ret = 0;
7900
7901         switch (l2_tunnel_type) {
7902         case RTE_L2_TUNNEL_TYPE_E_TAG:
7903                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7904                 break;
7905         default:
7906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7907                 ret = -EINVAL;
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 /* Enable/disable l2 tunnel offload functions */
7915 static int
7916 ixgbe_dev_l2_tunnel_offload_set
7917         (struct rte_eth_dev *dev,
7918          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7919          uint32_t mask,
7920          uint8_t en)
7921 {
7922         int ret = 0;
7923
7924         if (l2_tunnel == NULL)
7925                 return -EINVAL;
7926
7927         ret = -EINVAL;
7928         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7929                 if (en)
7930                         ret = ixgbe_dev_l2_tunnel_enable(
7931                                 dev,
7932                                 l2_tunnel->l2_tunnel_type);
7933                 else
7934                         ret = ixgbe_dev_l2_tunnel_disable(
7935                                 dev,
7936                                 l2_tunnel->l2_tunnel_type);
7937         }
7938
7939         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7940                 if (en)
7941                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7942                                 dev,
7943                                 l2_tunnel);
7944                 else
7945                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7946                                 dev,
7947                                 l2_tunnel);
7948         }
7949
7950         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7951                 if (en)
7952                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955                 else
7956                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7957                                 dev,
7958                                 l2_tunnel->l2_tunnel_type);
7959         }
7960
7961         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7962                 if (en)
7963                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966                 else
7967                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7968                                 dev,
7969                                 l2_tunnel->l2_tunnel_type);
7970         }
7971
7972         return ret;
7973 }
7974
7975 static int
7976 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7977                         uint16_t port)
7978 {
7979         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7980         IXGBE_WRITE_FLUSH(hw);
7981
7982         return 0;
7983 }
7984
7985 /* There's only one register for VxLAN UDP port.
7986  * So, we cannot add several ports. Will update it.
7987  */
7988 static int
7989 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7990                      uint16_t port)
7991 {
7992         if (port == 0) {
7993                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7994                 return -EINVAL;
7995         }
7996
7997         return ixgbe_update_vxlan_port(hw, port);
7998 }
7999
8000 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8001  * UDP port, it must have a value.
8002  * So, will reset it to the original value 0.
8003  */
8004 static int
8005 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8006                      uint16_t port)
8007 {
8008         uint16_t cur_port;
8009
8010         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8011
8012         if (cur_port != port) {
8013                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8014                 return -EINVAL;
8015         }
8016
8017         return ixgbe_update_vxlan_port(hw, 0);
8018 }
8019
8020 /* Add UDP tunneling port */
8021 static int
8022 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8023                               struct rte_eth_udp_tunnel *udp_tunnel)
8024 {
8025         int ret = 0;
8026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8027
8028         if (hw->mac.type != ixgbe_mac_X550 &&
8029             hw->mac.type != ixgbe_mac_X550EM_x &&
8030             hw->mac.type != ixgbe_mac_X550EM_a) {
8031                 return -ENOTSUP;
8032         }
8033
8034         if (udp_tunnel == NULL)
8035                 return -EINVAL;
8036
8037         switch (udp_tunnel->prot_type) {
8038         case RTE_TUNNEL_TYPE_VXLAN:
8039                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8040                 break;
8041
8042         case RTE_TUNNEL_TYPE_GENEVE:
8043         case RTE_TUNNEL_TYPE_TEREDO:
8044                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8045                 ret = -EINVAL;
8046                 break;
8047
8048         default:
8049                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8050                 ret = -EINVAL;
8051                 break;
8052         }
8053
8054         return ret;
8055 }
8056
8057 /* Remove UDP tunneling port */
8058 static int
8059 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8060                               struct rte_eth_udp_tunnel *udp_tunnel)
8061 {
8062         int ret = 0;
8063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         if (hw->mac.type != ixgbe_mac_X550 &&
8066             hw->mac.type != ixgbe_mac_X550EM_x &&
8067             hw->mac.type != ixgbe_mac_X550EM_a) {
8068                 return -ENOTSUP;
8069         }
8070
8071         if (udp_tunnel == NULL)
8072                 return -EINVAL;
8073
8074         switch (udp_tunnel->prot_type) {
8075         case RTE_TUNNEL_TYPE_VXLAN:
8076                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8077                 break;
8078         case RTE_TUNNEL_TYPE_GENEVE:
8079         case RTE_TUNNEL_TYPE_TEREDO:
8080                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8081                 ret = -EINVAL;
8082                 break;
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -EINVAL;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 static void
8093 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8094 {
8095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8096
8097         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8098 }
8099
8100 static void
8101 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8102 {
8103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8104
8105         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8106 }
8107
8108 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8109 {
8110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8111         u32 in_msg = 0;
8112
8113         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8114                 return;
8115
8116         /* PF reset VF event */
8117         if (in_msg == IXGBE_PF_CONTROL_MSG)
8118                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8119 }
8120
8121 static int
8122 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8123 {
8124         uint32_t eicr;
8125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8126         struct ixgbe_interrupt *intr =
8127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8128         ixgbevf_intr_disable(hw);
8129
8130         /* read-on-clear nic registers here */
8131         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8132         intr->flags = 0;
8133
8134         /* only one misc vector supported - mailbox */
8135         eicr &= IXGBE_VTEICR_MASK;
8136         if (eicr == IXGBE_MISC_VEC_ID)
8137                 intr->flags |= IXGBE_FLAG_MAILBOX;
8138
8139         return 0;
8140 }
8141
8142 static int
8143 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8144 {
8145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8146         struct ixgbe_interrupt *intr =
8147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8148
8149         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8150                 ixgbevf_mbx_process(dev);
8151                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8152         }
8153
8154         ixgbevf_intr_enable(hw);
8155
8156         return 0;
8157 }
8158
8159 static void
8160 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8161                               void *param)
8162 {
8163         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8164
8165         ixgbevf_dev_interrupt_get_status(dev);
8166         ixgbevf_dev_interrupt_action(dev);
8167 }
8168
8169 /**
8170  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8171  *  @hw: pointer to hardware structure
8172  *
8173  *  Stops the transmit data path and waits for the HW to internally empty
8174  *  the Tx security block
8175  **/
8176 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8177 {
8178 #define IXGBE_MAX_SECTX_POLL 40
8179
8180         int i;
8181         int sectxreg;
8182
8183         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8184         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8185         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8186         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8187                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8188                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8189                         break;
8190                 /* Use interrupt-safe sleep just in case */
8191                 usec_delay(1000);
8192         }
8193
8194         /* For informational purposes only */
8195         if (i >= IXGBE_MAX_SECTX_POLL)
8196                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8197                          "path fully disabled.  Continuing with init.");
8198
8199         return IXGBE_SUCCESS;
8200 }
8201
8202 /**
8203  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8204  *  @hw: pointer to hardware structure
8205  *
8206  *  Enables the transmit data path.
8207  **/
8208 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8209 {
8210         uint32_t sectxreg;
8211
8212         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8213         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8214         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8215         IXGBE_WRITE_FLUSH(hw);
8216
8217         return IXGBE_SUCCESS;
8218 }
8219
8220 int
8221 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8222 {
8223         struct ixgbe_hw *hw;
8224         struct rte_eth_dev *dev;
8225         uint32_t ctrl;
8226
8227         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8228
8229         dev = &rte_eth_devices[port];
8230
8231         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8232                 return -ENOTSUP;
8233
8234         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8235
8236         /* Stop the data paths */
8237         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8238                 return -ENOTSUP;
8239         /*
8240          * Workaround:
8241          * As no ixgbe_disable_sec_rx_path equivalent is
8242          * implemented for tx in the base code, and we are
8243          * not allowed to modify the base code in DPDK, so
8244          * just call the hand-written one directly for now.
8245          * The hardware support has been checked by
8246          * ixgbe_disable_sec_rx_path().
8247          */
8248         ixgbe_disable_sec_tx_path_generic(hw);
8249
8250         /* Enable Ethernet CRC (required by MACsec offload) */
8251         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8252         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8253         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8254
8255         /* Enable the TX and RX crypto engines */
8256         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8257         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8258         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8259
8260         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8261         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8262         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8263
8264         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8265         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8266         ctrl |= 0x3;
8267         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8268
8269         /* Enable SA lookup */
8270         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8271         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8272         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8273                      IXGBE_LSECTXCTRL_AUTH;
8274         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8275         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8276         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8277         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8278
8279         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8280         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8281         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8282         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8283         if (rp)
8284                 ctrl |= IXGBE_LSECRXCTRL_RP;
8285         else
8286                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8287         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8288
8289         /* Start the data paths */
8290         ixgbe_enable_sec_rx_path(hw);
8291         /*
8292          * Workaround:
8293          * As no ixgbe_enable_sec_rx_path equivalent is
8294          * implemented for tx in the base code, and we are
8295          * not allowed to modify the base code in DPDK, so
8296          * just call the hand-written one directly for now.
8297          */
8298         ixgbe_enable_sec_tx_path_generic(hw);
8299
8300         return 0;
8301 }
8302
8303 int
8304 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8305 {
8306         struct ixgbe_hw *hw;
8307         struct rte_eth_dev *dev;
8308         uint32_t ctrl;
8309
8310         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8311
8312         dev = &rte_eth_devices[port];
8313
8314         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8315                 return -ENOTSUP;
8316
8317         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8318
8319         /* Stop the data paths */
8320         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8321                 return -ENOTSUP;
8322         /*
8323          * Workaround:
8324          * As no ixgbe_disable_sec_rx_path equivalent is
8325          * implemented for tx in the base code, and we are
8326          * not allowed to modify the base code in DPDK, so
8327          * just call the hand-written one directly for now.
8328          * The hardware support has been checked by
8329          * ixgbe_disable_sec_rx_path().
8330          */
8331         ixgbe_disable_sec_tx_path_generic(hw);
8332
8333         /* Disable the TX and RX crypto engines */
8334         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8335         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8336         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8337
8338         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8339         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8340         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8341
8342         /* Disable SA lookup */
8343         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8344         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8345         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8346         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8347
8348         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8349         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8350         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8351         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8352
8353         /* Start the data paths */
8354         ixgbe_enable_sec_rx_path(hw);
8355         /*
8356          * Workaround:
8357          * As no ixgbe_enable_sec_rx_path equivalent is
8358          * implemented for tx in the base code, and we are
8359          * not allowed to modify the base code in DPDK, so
8360          * just call the hand-written one directly for now.
8361          */
8362         ixgbe_enable_sec_tx_path_generic(hw);
8363
8364         return 0;
8365 }
8366
8367 int
8368 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8369 {
8370         struct ixgbe_hw *hw;
8371         struct rte_eth_dev *dev;
8372         uint32_t ctrl;
8373
8374         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8375
8376         dev = &rte_eth_devices[port];
8377
8378         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8379                 return -ENOTSUP;
8380
8381         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8382
8383         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8384         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8385
8386         ctrl = mac[4] | (mac[5] << 8);
8387         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8388
8389         return 0;
8390 }
8391
8392 int
8393 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8394 {
8395         struct ixgbe_hw *hw;
8396         struct rte_eth_dev *dev;
8397         uint32_t ctrl;
8398
8399         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8400
8401         dev = &rte_eth_devices[port];
8402
8403         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8404                 return -ENOTSUP;
8405
8406         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8407
8408         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8409         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8410
8411         pi = rte_cpu_to_be_16(pi);
8412         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8413         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8414
8415         return 0;
8416 }
8417
8418 int
8419 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8420                                  uint32_t pn, uint8_t *key)
8421 {
8422         struct ixgbe_hw *hw;
8423         struct rte_eth_dev *dev;
8424         uint32_t ctrl, i;
8425
8426         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8427
8428         dev = &rte_eth_devices[port];
8429
8430         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8431                 return -ENOTSUP;
8432
8433         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8434
8435         if (idx != 0 && idx != 1)
8436                 return -EINVAL;
8437
8438         if (an >= 4)
8439                 return -EINVAL;
8440
8441         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8442
8443         /* Set the PN and key */
8444         pn = rte_cpu_to_be_32(pn);
8445         if (idx == 0) {
8446                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8447
8448                 for (i = 0; i < 4; i++) {
8449                         ctrl = (key[i * 4 + 0] <<  0) |
8450                                (key[i * 4 + 1] <<  8) |
8451                                (key[i * 4 + 2] << 16) |
8452                                (key[i * 4 + 3] << 24);
8453                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8454                 }
8455         } else {
8456                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8457
8458                 for (i = 0; i < 4; i++) {
8459                         ctrl = (key[i * 4 + 0] <<  0) |
8460                                (key[i * 4 + 1] <<  8) |
8461                                (key[i * 4 + 2] << 16) |
8462                                (key[i * 4 + 3] << 24);
8463                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8464                 }
8465         }
8466
8467         /* Set AN and select the SA */
8468         ctrl = (an << idx * 2) | (idx << 4);
8469         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8470
8471         return 0;
8472 }
8473
8474 int
8475 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8476                                  uint32_t pn, uint8_t *key)
8477 {
8478         struct ixgbe_hw *hw;
8479         struct rte_eth_dev *dev;
8480         uint32_t ctrl, i;
8481
8482         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8483
8484         dev = &rte_eth_devices[port];
8485
8486         if (!is_device_supported(dev, &rte_ixgbe_pmd))
8487                 return -ENOTSUP;
8488
8489         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8490
8491         if (idx != 0 && idx != 1)
8492                 return -EINVAL;
8493
8494         if (an >= 4)
8495                 return -EINVAL;
8496
8497         /* Set the PN */
8498         pn = rte_cpu_to_be_32(pn);
8499         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8500
8501         /* Set the key */
8502         for (i = 0; i < 4; i++) {
8503                 ctrl = (key[i * 4 + 0] <<  0) |
8504                        (key[i * 4 + 1] <<  8) |
8505                        (key[i * 4 + 2] << 16) |
8506                        (key[i * 4 + 3] << 24);
8507                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8508         }
8509
8510         /* Set the AN and validate the SA */
8511         ctrl = an | (1 << 2);
8512         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8513
8514         return 0;
8515 }
8516
8517 /* restore n-tuple filter */
8518 static inline void
8519 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8520 {
8521         struct ixgbe_filter_info *filter_info =
8522                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8523         struct ixgbe_5tuple_filter *node;
8524
8525         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8526                 ixgbe_inject_5tuple_filter(dev, node);
8527         }
8528 }
8529
8530 /* restore ethernet type filter */
8531 static inline void
8532 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8533 {
8534         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8535         struct ixgbe_filter_info *filter_info =
8536                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8537         int i;
8538
8539         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8540                 if (filter_info->ethertype_mask & (1 << i)) {
8541                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8542                                         filter_info->ethertype_filters[i].etqf);
8543                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8544                                         filter_info->ethertype_filters[i].etqs);
8545                         IXGBE_WRITE_FLUSH(hw);
8546                 }
8547         }
8548 }
8549
8550 /* restore SYN filter */
8551 static inline void
8552 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8553 {
8554         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8555         struct ixgbe_filter_info *filter_info =
8556                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8557         uint32_t synqf;
8558
8559         synqf = filter_info->syn_info;
8560
8561         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8562                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8563                 IXGBE_WRITE_FLUSH(hw);
8564         }
8565 }
8566
8567 /* restore L2 tunnel filter */
8568 static inline void
8569 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8570 {
8571         struct ixgbe_l2_tn_info *l2_tn_info =
8572                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8573         struct ixgbe_l2_tn_filter *node;
8574         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8575
8576         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8577                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8578                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8579                 l2_tn_conf.pool           = node->pool;
8580                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8581         }
8582 }
8583
8584 static int
8585 ixgbe_filter_restore(struct rte_eth_dev *dev)
8586 {
8587         ixgbe_ntuple_filter_restore(dev);
8588         ixgbe_ethertype_filter_restore(dev);
8589         ixgbe_syn_filter_restore(dev);
8590         ixgbe_fdir_filter_restore(dev);
8591         ixgbe_l2_tn_filter_restore(dev);
8592
8593         return 0;
8594 }
8595
8596 static void
8597 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8598 {
8599         struct ixgbe_l2_tn_info *l2_tn_info =
8600                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8601         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8602
8603         if (l2_tn_info->e_tag_en)
8604                 (void)ixgbe_e_tag_enable(hw);
8605
8606         if (l2_tn_info->e_tag_fwd_en)
8607                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8608
8609         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8610 }
8611
8612 /* remove all the n-tuple filters */
8613 void
8614 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8615 {
8616         struct ixgbe_filter_info *filter_info =
8617                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8618         struct ixgbe_5tuple_filter *p_5tuple;
8619
8620         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8621                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8622 }
8623
8624 /* remove all the ether type filters */
8625 void
8626 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8627 {
8628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8629         struct ixgbe_filter_info *filter_info =
8630                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8631         int i;
8632
8633         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8634                 if (filter_info->ethertype_mask & (1 << i) &&
8635                     !filter_info->ethertype_filters[i].conf) {
8636                         (void)ixgbe_ethertype_filter_remove(filter_info,
8637                                                             (uint8_t)i);
8638                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8639                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8640                         IXGBE_WRITE_FLUSH(hw);
8641                 }
8642         }
8643 }
8644
8645 /* remove the SYN filter */
8646 void
8647 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8648 {
8649         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8650         struct ixgbe_filter_info *filter_info =
8651                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8652
8653         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8654                 filter_info->syn_info = 0;
8655
8656                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8657                 IXGBE_WRITE_FLUSH(hw);
8658         }
8659 }
8660
8661 /* remove all the L2 tunnel filters */
8662 int
8663 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8664 {
8665         struct ixgbe_l2_tn_info *l2_tn_info =
8666                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8667         struct ixgbe_l2_tn_filter *l2_tn_filter;
8668         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8669         int ret = 0;
8670
8671         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8672                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8673                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8674                 l2_tn_conf.pool           = l2_tn_filter->pool;
8675                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8676                 if (ret < 0)
8677                         return ret;
8678         }
8679
8680         return 0;
8681 }
8682
8683 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8684 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8685 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8686 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8687 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8688 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");