4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
64 #ifdef RTE_LIBRTE_SECURITY
65 #include <rte_security_driver.h>
68 #include "ixgbe_logs.h"
69 #include "base/ixgbe_api.h"
70 #include "base/ixgbe_vf.h"
71 #include "base/ixgbe_common.h"
72 #include "ixgbe_ethdev.h"
73 #include "ixgbe_bypass.h"
74 #include "ixgbe_rxtx.h"
75 #include "base/ixgbe_type.h"
76 #include "base/ixgbe_phy.h"
77 #include "ixgbe_regs.h"
80 * High threshold controlling when to start sending XOFF frames. Must be at
81 * least 8 bytes less than receive packet buffer size. This value is in units
84 #define IXGBE_FC_HI 0x80
87 * Low threshold controlling when to start sending XON frames. This value is
88 * in units of 1024 bytes.
90 #define IXGBE_FC_LO 0x40
92 /* Default minimum inter-interrupt interval for EITR configuration */
93 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
95 /* Timer value included in XOFF frames. */
96 #define IXGBE_FC_PAUSE 0x680
98 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
99 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
100 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
102 #define IXGBE_MMW_SIZE_DEFAULT 0x4
103 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
104 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
107 * Default values for RX/TX configuration
109 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
110 #define IXGBE_DEFAULT_RX_PTHRESH 8
111 #define IXGBE_DEFAULT_RX_HTHRESH 8
112 #define IXGBE_DEFAULT_RX_WTHRESH 0
114 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
115 #define IXGBE_DEFAULT_TX_PTHRESH 32
116 #define IXGBE_DEFAULT_TX_HTHRESH 0
117 #define IXGBE_DEFAULT_TX_WTHRESH 0
118 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
120 /* Bit shift and mask */
121 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
122 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
123 #define IXGBE_8_BIT_WIDTH CHAR_BIT
124 #define IXGBE_8_BIT_MASK UINT8_MAX
126 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
128 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
130 #define IXGBE_HKEY_MAX_INDEX 10
132 /* Additional timesync values. */
133 #define NSEC_PER_SEC 1000000000L
134 #define IXGBE_INCVAL_10GB 0x66666666
135 #define IXGBE_INCVAL_1GB 0x40000000
136 #define IXGBE_INCVAL_100 0x50000000
137 #define IXGBE_INCVAL_SHIFT_10GB 28
138 #define IXGBE_INCVAL_SHIFT_1GB 24
139 #define IXGBE_INCVAL_SHIFT_100 21
140 #define IXGBE_INCVAL_SHIFT_82599 7
141 #define IXGBE_INCPER_SHIFT_82599 24
143 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
145 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
146 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
147 #define DEFAULT_ETAG_ETYPE 0x893f
148 #define IXGBE_ETAG_ETYPE 0x00005084
149 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
150 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
151 #define IXGBE_RAH_ADTYPE 0x40000000
152 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
153 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
154 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
155 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
156 #define IXGBE_QDE_STRIP_TAG 0x00000004
157 #define IXGBE_VTEICR_MASK 0x07
159 #define IXGBE_EXVET_VET_EXT_SHIFT 16
160 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
162 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
163 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
167 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
168 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
169 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
170 static int ixgbe_dev_start(struct rte_eth_dev *dev);
171 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
172 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
173 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
174 static void ixgbe_dev_close(struct rte_eth_dev *dev);
175 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
176 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
177 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
178 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
179 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
180 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
181 int wait_to_complete);
182 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
183 struct rte_eth_stats *stats);
184 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
185 struct rte_eth_xstat *xstats, unsigned n);
186 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
187 struct rte_eth_xstat *xstats, unsigned n);
189 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
190 uint64_t *values, unsigned int n);
191 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
192 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
193 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names,
196 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names, unsigned limit);
198 static int ixgbe_dev_xstats_get_names_by_id(
199 struct rte_eth_dev *dev,
200 struct rte_eth_xstat_name *xstats_names,
203 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
207 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
209 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
212 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
213 struct rte_eth_dev_info *dev_info);
214 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
216 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
217 uint16_t vlan_id, int on);
218 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
219 enum rte_vlan_type vlan_type,
221 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
222 uint16_t queue, bool on);
223 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
225 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
226 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
227 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
228 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
229 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
231 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
232 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
233 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
234 struct rte_eth_fc_conf *fc_conf);
235 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
236 struct rte_eth_fc_conf *fc_conf);
237 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
238 struct rte_eth_pfc_conf *pfc_conf);
239 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
243 struct rte_eth_rss_reta_entry64 *reta_conf,
245 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
246 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
247 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
248 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
249 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
250 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
251 struct rte_intr_handle *handle);
252 static void ixgbe_dev_interrupt_handler(void *param);
253 static void ixgbe_dev_interrupt_delayed_handler(void *param);
254 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
255 uint32_t index, uint32_t pool);
256 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
257 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
258 struct ether_addr *mac_addr);
259 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
260 static bool is_device_supported(struct rte_eth_dev *dev,
261 struct rte_pci_driver *drv);
263 /* For Virtual Function support */
264 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
265 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
266 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
267 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
268 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
269 int wait_to_complete);
270 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
271 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
272 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
273 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
274 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
275 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
276 struct rte_eth_stats *stats);
277 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
278 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
279 uint16_t vlan_id, int on);
280 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
281 uint16_t queue, int on);
282 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
283 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
284 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
286 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
288 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
289 uint8_t queue, uint8_t msix_vector);
290 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
291 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
292 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
294 /* For Eth VMDQ APIs support */
295 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
296 ether_addr * mac_addr, uint8_t on);
297 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
298 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
299 struct rte_eth_mirror_conf *mirror_conf,
300 uint8_t rule_id, uint8_t on);
301 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
303 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
305 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
307 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
308 uint8_t queue, uint8_t msix_vector);
309 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
311 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
312 struct ether_addr *mac_addr,
313 uint32_t index, uint32_t pool);
314 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
315 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
316 struct ether_addr *mac_addr);
317 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
318 struct rte_eth_syn_filter *filter);
319 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
323 struct ixgbe_5tuple_filter *filter);
324 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
325 struct ixgbe_5tuple_filter *filter);
326 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
327 enum rte_filter_op filter_op,
329 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ntuple_filter *filter);
331 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
332 enum rte_filter_op filter_op,
334 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
335 struct rte_eth_ethertype_filter *filter);
336 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
337 enum rte_filter_type filter_type,
338 enum rte_filter_op filter_op,
340 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
342 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
343 struct ether_addr *mc_addr_set,
344 uint32_t nb_mc_addr);
345 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
346 struct rte_eth_dcb_info *dcb_info);
348 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_regs(struct rte_eth_dev *dev,
350 struct rte_dev_reg_info *regs);
351 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
352 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
353 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
355 struct rte_dev_eeprom_info *eeprom);
357 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
358 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
359 struct rte_dev_reg_info *regs);
361 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
362 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
363 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp,
366 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
369 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
370 struct timespec *timestamp);
371 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
372 const struct timespec *timestamp);
373 static void ixgbevf_dev_interrupt_handler(void *param);
375 static int ixgbe_dev_l2_tunnel_eth_type_conf
376 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
377 static int ixgbe_dev_l2_tunnel_offload_set
378 (struct rte_eth_dev *dev,
379 struct rte_eth_l2_tunnel_conf *l2_tunnel,
382 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
383 enum rte_filter_op filter_op,
386 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
387 struct rte_eth_udp_tunnel *udp_tunnel);
388 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
389 struct rte_eth_udp_tunnel *udp_tunnel);
390 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
391 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
394 * Define VF Stats MACRO for Non "cleared on read" register
396 #define UPDATE_VF_STAT(reg, last, cur) \
398 uint32_t latest = IXGBE_READ_REG(hw, reg); \
399 cur += (latest - last) & UINT_MAX; \
403 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
405 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
406 u64 new_msb = IXGBE_READ_REG(hw, msb); \
407 u64 latest = ((new_msb << 32) | new_lsb); \
408 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
412 #define IXGBE_SET_HWSTRIP(h, q) do {\
413 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
414 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
415 (h)->bitmap[idx] |= 1 << bit;\
418 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
419 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
420 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
421 (h)->bitmap[idx] &= ~(1 << bit);\
424 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
425 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
426 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
427 (r) = (h)->bitmap[idx] >> bit & 1;\
431 * The set of PCI devices this driver supports
433 static const struct rte_pci_id pci_id_ixgbe_map[] = {
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
482 #ifdef RTE_LIBRTE_IXGBE_BYPASS
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
485 { .vendor_id = 0, /* sentinel */ },
489 * The set of PCI devices this driver supports (for 82599 VF)
491 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
502 { .vendor_id = 0, /* sentinel */ },
505 static const struct rte_eth_desc_lim rx_desc_lim = {
506 .nb_max = IXGBE_MAX_RING_DESC,
507 .nb_min = IXGBE_MIN_RING_DESC,
508 .nb_align = IXGBE_RXD_ALIGN,
511 static const struct rte_eth_desc_lim tx_desc_lim = {
512 .nb_max = IXGBE_MAX_RING_DESC,
513 .nb_min = IXGBE_MIN_RING_DESC,
514 .nb_align = IXGBE_TXD_ALIGN,
515 .nb_seg_max = IXGBE_TX_MAX_SEG,
516 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
519 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
520 .dev_configure = ixgbe_dev_configure,
521 .dev_start = ixgbe_dev_start,
522 .dev_stop = ixgbe_dev_stop,
523 .dev_set_link_up = ixgbe_dev_set_link_up,
524 .dev_set_link_down = ixgbe_dev_set_link_down,
525 .dev_close = ixgbe_dev_close,
526 .dev_reset = ixgbe_dev_reset,
527 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
528 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
529 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
530 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
531 .link_update = ixgbe_dev_link_update,
532 .stats_get = ixgbe_dev_stats_get,
533 .xstats_get = ixgbe_dev_xstats_get,
534 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
535 .stats_reset = ixgbe_dev_stats_reset,
536 .xstats_reset = ixgbe_dev_xstats_reset,
537 .xstats_get_names = ixgbe_dev_xstats_get_names,
538 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
539 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
540 .fw_version_get = ixgbe_fw_version_get,
541 .dev_infos_get = ixgbe_dev_info_get,
542 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
543 .mtu_set = ixgbe_dev_mtu_set,
544 .vlan_filter_set = ixgbe_vlan_filter_set,
545 .vlan_tpid_set = ixgbe_vlan_tpid_set,
546 .vlan_offload_set = ixgbe_vlan_offload_set,
547 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
548 .rx_queue_start = ixgbe_dev_rx_queue_start,
549 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
550 .tx_queue_start = ixgbe_dev_tx_queue_start,
551 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
552 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
553 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
554 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
555 .rx_queue_release = ixgbe_dev_rx_queue_release,
556 .rx_queue_count = ixgbe_dev_rx_queue_count,
557 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
558 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
559 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
560 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
561 .tx_queue_release = ixgbe_dev_tx_queue_release,
562 .dev_led_on = ixgbe_dev_led_on,
563 .dev_led_off = ixgbe_dev_led_off,
564 .flow_ctrl_get = ixgbe_flow_ctrl_get,
565 .flow_ctrl_set = ixgbe_flow_ctrl_set,
566 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
567 .mac_addr_add = ixgbe_add_rar,
568 .mac_addr_remove = ixgbe_remove_rar,
569 .mac_addr_set = ixgbe_set_default_mac_addr,
570 .uc_hash_table_set = ixgbe_uc_hash_table_set,
571 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
572 .mirror_rule_set = ixgbe_mirror_rule_set,
573 .mirror_rule_reset = ixgbe_mirror_rule_reset,
574 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
575 .reta_update = ixgbe_dev_rss_reta_update,
576 .reta_query = ixgbe_dev_rss_reta_query,
577 .rss_hash_update = ixgbe_dev_rss_hash_update,
578 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
579 .filter_ctrl = ixgbe_dev_filter_ctrl,
580 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
581 .rxq_info_get = ixgbe_rxq_info_get,
582 .txq_info_get = ixgbe_txq_info_get,
583 .timesync_enable = ixgbe_timesync_enable,
584 .timesync_disable = ixgbe_timesync_disable,
585 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
586 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
587 .get_reg = ixgbe_get_regs,
588 .get_eeprom_length = ixgbe_get_eeprom_length,
589 .get_eeprom = ixgbe_get_eeprom,
590 .set_eeprom = ixgbe_set_eeprom,
591 .get_dcb_info = ixgbe_dev_get_dcb_info,
592 .timesync_adjust_time = ixgbe_timesync_adjust_time,
593 .timesync_read_time = ixgbe_timesync_read_time,
594 .timesync_write_time = ixgbe_timesync_write_time,
595 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
596 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
597 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
598 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
599 .tm_ops_get = ixgbe_tm_ops_get,
603 * dev_ops for virtual function, bare necessities for basic vf
604 * operation have been implemented
606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
607 .dev_configure = ixgbevf_dev_configure,
608 .dev_start = ixgbevf_dev_start,
609 .dev_stop = ixgbevf_dev_stop,
610 .link_update = ixgbevf_dev_link_update,
611 .stats_get = ixgbevf_dev_stats_get,
612 .xstats_get = ixgbevf_dev_xstats_get,
613 .stats_reset = ixgbevf_dev_stats_reset,
614 .xstats_reset = ixgbevf_dev_stats_reset,
615 .xstats_get_names = ixgbevf_dev_xstats_get_names,
616 .dev_close = ixgbevf_dev_close,
617 .dev_reset = ixgbevf_dev_reset,
618 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
619 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
620 .dev_infos_get = ixgbevf_dev_info_get,
621 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
622 .mtu_set = ixgbevf_dev_set_mtu,
623 .vlan_filter_set = ixgbevf_vlan_filter_set,
624 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
625 .vlan_offload_set = ixgbevf_vlan_offload_set,
626 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
627 .rx_queue_release = ixgbe_dev_rx_queue_release,
628 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
629 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
630 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
631 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
632 .tx_queue_release = ixgbe_dev_tx_queue_release,
633 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
634 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
635 .mac_addr_add = ixgbevf_add_mac_addr,
636 .mac_addr_remove = ixgbevf_remove_mac_addr,
637 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
638 .rxq_info_get = ixgbe_rxq_info_get,
639 .txq_info_get = ixgbe_txq_info_get,
640 .mac_addr_set = ixgbevf_set_default_mac_addr,
641 .get_reg = ixgbevf_get_regs,
642 .reta_update = ixgbe_dev_rss_reta_update,
643 .reta_query = ixgbe_dev_rss_reta_query,
644 .rss_hash_update = ixgbe_dev_rss_hash_update,
645 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
648 /* store statistics names and its offset in stats structure */
649 struct rte_ixgbe_xstats_name_off {
650 char name[RTE_ETH_XSTATS_NAME_SIZE];
654 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
655 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
656 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
657 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
658 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
659 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
660 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
661 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
662 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
663 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
664 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
665 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
666 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
667 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
668 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
669 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
673 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
674 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
675 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
676 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
677 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
678 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
679 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
680 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
681 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
682 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
683 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
684 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
685 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
686 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
687 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
688 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
689 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
693 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
694 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
695 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
696 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
698 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
708 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
711 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
712 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
713 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
715 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
716 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
717 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
718 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
719 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
721 {"rx_fcoe_no_direct_data_placement_ext_buff",
722 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
724 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
728 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
732 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
735 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
736 sizeof(rte_ixgbe_stats_strings[0]))
738 /* MACsec statistics */
739 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
740 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
742 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_encrypted)},
744 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
745 out_pkts_protected)},
746 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
747 out_octets_encrypted)},
748 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
749 out_octets_protected)},
750 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
756 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
757 in_pkts_unknownsci)},
758 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
759 in_octets_decrypted)},
760 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
761 in_octets_validated)},
762 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
776 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
777 in_pkts_notusingsa)},
780 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
781 sizeof(rte_ixgbe_macsec_strings[0]))
783 /* Per-queue statistics */
784 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
785 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
786 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
787 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
788 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
791 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
792 sizeof(rte_ixgbe_rxq_strings[0]))
793 #define IXGBE_NB_RXQ_PRIO_VALUES 8
795 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
796 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
797 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
798 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
802 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
803 sizeof(rte_ixgbe_txq_strings[0]))
804 #define IXGBE_NB_TXQ_PRIO_VALUES 8
806 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
807 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
810 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
811 sizeof(rte_ixgbevf_stats_strings[0]))
814 * Atomically reads the link status information from global
815 * structure rte_eth_dev.
818 * - Pointer to the structure rte_eth_dev to read from.
819 * - Pointer to the buffer to be saved with the link status.
822 * - On success, zero.
823 * - On failure, negative value.
826 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
827 struct rte_eth_link *link)
829 struct rte_eth_link *dst = link;
830 struct rte_eth_link *src = &(dev->data->dev_link);
832 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
833 *(uint64_t *)src) == 0)
840 * Atomically writes the link status information into global
841 * structure rte_eth_dev.
844 * - Pointer to the structure rte_eth_dev to read from.
845 * - Pointer to the buffer to be saved with the link status.
848 * - On success, zero.
849 * - On failure, negative value.
852 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
853 struct rte_eth_link *link)
855 struct rte_eth_link *dst = &(dev->data->dev_link);
856 struct rte_eth_link *src = link;
858 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
859 *(uint64_t *)src) == 0)
866 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
869 ixgbe_is_sfp(struct ixgbe_hw *hw)
871 switch (hw->phy.type) {
872 case ixgbe_phy_sfp_avago:
873 case ixgbe_phy_sfp_ftl:
874 case ixgbe_phy_sfp_intel:
875 case ixgbe_phy_sfp_unknown:
876 case ixgbe_phy_sfp_passive_tyco:
877 case ixgbe_phy_sfp_passive_unknown:
884 static inline int32_t
885 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
890 status = ixgbe_reset_hw(hw);
892 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
893 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
894 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
895 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
896 IXGBE_WRITE_FLUSH(hw);
898 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
899 status = IXGBE_SUCCESS;
904 ixgbe_enable_intr(struct rte_eth_dev *dev)
906 struct ixgbe_interrupt *intr =
907 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
908 struct ixgbe_hw *hw =
909 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
911 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
912 IXGBE_WRITE_FLUSH(hw);
916 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
919 ixgbe_disable_intr(struct ixgbe_hw *hw)
921 PMD_INIT_FUNC_TRACE();
923 if (hw->mac.type == ixgbe_mac_82598EB) {
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
928 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
930 IXGBE_WRITE_FLUSH(hw);
934 * This function resets queue statistics mapping registers.
935 * From Niantic datasheet, Initialization of Statistics section:
936 * "...if software requires the queue counters, the RQSMR and TQSM registers
937 * must be re-programmed following a device reset.
940 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
944 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
945 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
946 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
952 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
957 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
958 #define NB_QMAP_FIELDS_PER_QSM_REG 4
959 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
961 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
962 struct ixgbe_stat_mapping_registers *stat_mappings =
963 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
964 uint32_t qsmr_mask = 0;
965 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
969 if ((hw->mac.type != ixgbe_mac_82599EB) &&
970 (hw->mac.type != ixgbe_mac_X540) &&
971 (hw->mac.type != ixgbe_mac_X550) &&
972 (hw->mac.type != ixgbe_mac_X550EM_x) &&
973 (hw->mac.type != ixgbe_mac_X550EM_a))
976 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
977 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
980 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
981 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
982 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
985 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
987 /* Now clear any previous stat_idx set */
988 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
990 stat_mappings->tqsm[n] &= ~clearing_mask;
992 stat_mappings->rqsmr[n] &= ~clearing_mask;
994 q_map = (uint32_t)stat_idx;
995 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
996 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
998 stat_mappings->tqsm[n] |= qsmr_mask;
1000 stat_mappings->rqsmr[n] |= qsmr_mask;
1002 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1003 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1004 queue_id, stat_idx);
1005 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1006 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1008 /* Now write the mapping in the appropriate register */
1010 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1011 stat_mappings->rqsmr[n], n);
1012 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1014 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1015 stat_mappings->tqsm[n], n);
1016 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1022 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1024 struct ixgbe_stat_mapping_registers *stat_mappings =
1025 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1026 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1029 /* write whatever was in stat mapping table to the NIC */
1030 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1032 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1035 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1040 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1043 struct ixgbe_dcb_tc_config *tc;
1044 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1046 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1047 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1048 for (i = 0; i < dcb_max_tc; i++) {
1049 tc = &dcb_config->tc_config[i];
1050 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1051 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1052 (uint8_t)(100/dcb_max_tc + (i & 1));
1053 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1054 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1055 (uint8_t)(100/dcb_max_tc + (i & 1));
1056 tc->pfc = ixgbe_dcb_pfc_disabled;
1059 /* Initialize default user to priority mapping, UPx->TC0 */
1060 tc = &dcb_config->tc_config[0];
1061 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1062 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1063 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1064 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1065 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1067 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1068 dcb_config->pfc_mode_enable = false;
1069 dcb_config->vt_mode = true;
1070 dcb_config->round_robin_enable = false;
1071 /* support all DCB capabilities in 82599 */
1072 dcb_config->support.capabilities = 0xFF;
1074 /*we only support 4 Tcs for X540, X550 */
1075 if (hw->mac.type == ixgbe_mac_X540 ||
1076 hw->mac.type == ixgbe_mac_X550 ||
1077 hw->mac.type == ixgbe_mac_X550EM_x ||
1078 hw->mac.type == ixgbe_mac_X550EM_a) {
1079 dcb_config->num_tcs.pg_tcs = 4;
1080 dcb_config->num_tcs.pfc_tcs = 4;
1085 * Ensure that all locks are released before first NVM or PHY access
1088 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1093 * Phy lock should not fail in this early stage. If this is the case,
1094 * it is due to an improper exit of the application.
1095 * So force the release of the faulty lock. Release of common lock
1096 * is done automatically by swfw_sync function.
1098 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1099 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1100 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1102 ixgbe_release_swfw_semaphore(hw, mask);
1105 * These ones are more tricky since they are common to all ports; but
1106 * swfw_sync retries last long enough (1s) to be almost sure that if
1107 * lock can not be taken it is due to an improper lock of the
1110 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1111 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1112 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1114 ixgbe_release_swfw_semaphore(hw, mask);
1118 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1119 * It returns 0 on success.
1122 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1124 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1126 struct ixgbe_hw *hw =
1127 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1128 struct ixgbe_vfta *shadow_vfta =
1129 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1130 struct ixgbe_hwstrip *hwstrip =
1131 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1132 struct ixgbe_dcb_config *dcb_config =
1133 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1134 struct ixgbe_filter_info *filter_info =
1135 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1136 struct ixgbe_bw_conf *bw_conf =
1137 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1142 PMD_INIT_FUNC_TRACE();
1144 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1145 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1146 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1147 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1150 * For secondary processes, we don't initialise any further as primary
1151 * has already done this work. Only check we don't need a different
1152 * RX and TX function.
1154 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1155 struct ixgbe_tx_queue *txq;
1156 /* TX queue function in primary, set by last queue initialized
1157 * Tx queue may not initialized by primary process
1159 if (eth_dev->data->tx_queues) {
1160 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1161 ixgbe_set_tx_function(eth_dev, txq);
1163 /* Use default TX function if we get here */
1164 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1165 "Using default TX function.");
1168 ixgbe_set_rx_function(eth_dev);
1173 #ifdef RTE_LIBRTE_SECURITY
1174 /* Initialize security_ctx only for primary process*/
1175 eth_dev->security_ctx = ixgbe_ipsec_ctx_create(eth_dev);
1176 if (eth_dev->security_ctx == NULL)
1180 rte_eth_copy_pci_info(eth_dev, pci_dev);
1182 /* Vendor and Device ID need to be set before init of shared code */
1183 hw->device_id = pci_dev->id.device_id;
1184 hw->vendor_id = pci_dev->id.vendor_id;
1185 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1186 hw->allow_unsupported_sfp = 1;
1188 /* Initialize the shared code (base driver) */
1189 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1190 diag = ixgbe_bypass_init_shared_code(hw);
1192 diag = ixgbe_init_shared_code(hw);
1193 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1195 if (diag != IXGBE_SUCCESS) {
1196 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1200 /* pick up the PCI bus settings for reporting later */
1201 ixgbe_get_bus_info(hw);
1203 /* Unlock any pending hardware semaphore */
1204 ixgbe_swfw_lock_reset(hw);
1206 /* Initialize DCB configuration*/
1207 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1208 ixgbe_dcb_init(hw, dcb_config);
1209 /* Get Hardware Flow Control setting */
1210 hw->fc.requested_mode = ixgbe_fc_full;
1211 hw->fc.current_mode = ixgbe_fc_full;
1212 hw->fc.pause_time = IXGBE_FC_PAUSE;
1213 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1214 hw->fc.low_water[i] = IXGBE_FC_LO;
1215 hw->fc.high_water[i] = IXGBE_FC_HI;
1217 hw->fc.send_xon = 1;
1219 /* Make sure we have a good EEPROM before we read from it */
1220 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1221 if (diag != IXGBE_SUCCESS) {
1222 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1226 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1227 diag = ixgbe_bypass_init_hw(hw);
1229 diag = ixgbe_init_hw(hw);
1230 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1233 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1234 * is called too soon after the kernel driver unbinding/binding occurs.
1235 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1236 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1237 * also called. See ixgbe_identify_phy_82599(). The reason for the
1238 * failure is not known, and only occuts when virtualisation features
1239 * are disabled in the bios. A delay of 100ms was found to be enough by
1240 * trial-and-error, and is doubled to be safe.
1242 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1244 diag = ixgbe_init_hw(hw);
1247 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1248 diag = IXGBE_SUCCESS;
1250 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1251 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1252 "LOM. Please be aware there may be issues associated "
1253 "with your hardware.");
1254 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1255 "please contact your Intel or hardware representative "
1256 "who provided you with this hardware.");
1257 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1258 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1260 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1264 /* Reset the hw statistics */
1265 ixgbe_dev_stats_reset(eth_dev);
1267 /* disable interrupt */
1268 ixgbe_disable_intr(hw);
1270 /* reset mappings for queue statistics hw counters*/
1271 ixgbe_reset_qstat_mappings(hw);
1273 /* Allocate memory for storing MAC addresses */
1274 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1275 hw->mac.num_rar_entries, 0);
1276 if (eth_dev->data->mac_addrs == NULL) {
1278 "Failed to allocate %u bytes needed to store "
1280 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1283 /* Copy the permanent MAC address */
1284 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1285 ð_dev->data->mac_addrs[0]);
1287 /* Allocate memory for storing hash filter MAC addresses */
1288 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1289 IXGBE_VMDQ_NUM_UC_MAC, 0);
1290 if (eth_dev->data->hash_mac_addrs == NULL) {
1292 "Failed to allocate %d bytes needed to store MAC addresses",
1293 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1297 /* initialize the vfta */
1298 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1300 /* initialize the hw strip bitmap*/
1301 memset(hwstrip, 0, sizeof(*hwstrip));
1303 /* initialize PF if max_vfs not zero */
1304 ixgbe_pf_host_init(eth_dev);
1306 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1307 /* let hardware know driver is loaded */
1308 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1309 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1310 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1311 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1312 IXGBE_WRITE_FLUSH(hw);
1314 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1315 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1316 (int) hw->mac.type, (int) hw->phy.type,
1317 (int) hw->phy.sfp_type);
1319 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1320 (int) hw->mac.type, (int) hw->phy.type);
1322 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1323 eth_dev->data->port_id, pci_dev->id.vendor_id,
1324 pci_dev->id.device_id);
1326 rte_intr_callback_register(intr_handle,
1327 ixgbe_dev_interrupt_handler, eth_dev);
1329 /* enable uio/vfio intr/eventfd mapping */
1330 rte_intr_enable(intr_handle);
1332 /* enable support intr */
1333 ixgbe_enable_intr(eth_dev);
1335 /* initialize filter info */
1336 memset(filter_info, 0,
1337 sizeof(struct ixgbe_filter_info));
1339 /* initialize 5tuple filter list */
1340 TAILQ_INIT(&filter_info->fivetuple_list);
1342 /* initialize flow director filter list & hash */
1343 ixgbe_fdir_filter_init(eth_dev);
1345 /* initialize l2 tunnel filter list & hash */
1346 ixgbe_l2_tn_filter_init(eth_dev);
1348 /* initialize flow filter lists */
1349 ixgbe_filterlist_init();
1351 /* initialize bandwidth configuration info */
1352 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1354 /* initialize Traffic Manager configuration */
1355 ixgbe_tm_conf_init(eth_dev);
1361 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1363 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1364 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1365 struct ixgbe_hw *hw;
1367 PMD_INIT_FUNC_TRACE();
1369 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1372 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1374 if (hw->adapter_stopped == 0)
1375 ixgbe_dev_close(eth_dev);
1377 eth_dev->dev_ops = NULL;
1378 eth_dev->rx_pkt_burst = NULL;
1379 eth_dev->tx_pkt_burst = NULL;
1381 /* Unlock any pending hardware semaphore */
1382 ixgbe_swfw_lock_reset(hw);
1384 /* disable uio intr before callback unregister */
1385 rte_intr_disable(intr_handle);
1386 rte_intr_callback_unregister(intr_handle,
1387 ixgbe_dev_interrupt_handler, eth_dev);
1389 /* uninitialize PF if max_vfs not zero */
1390 ixgbe_pf_host_uninit(eth_dev);
1392 rte_free(eth_dev->data->mac_addrs);
1393 eth_dev->data->mac_addrs = NULL;
1395 rte_free(eth_dev->data->hash_mac_addrs);
1396 eth_dev->data->hash_mac_addrs = NULL;
1398 /* remove all the fdir filters & hash */
1399 ixgbe_fdir_filter_uninit(eth_dev);
1401 /* remove all the L2 tunnel filters & hash */
1402 ixgbe_l2_tn_filter_uninit(eth_dev);
1404 /* Remove all ntuple filters of the device */
1405 ixgbe_ntuple_filter_uninit(eth_dev);
1407 /* clear all the filters list */
1408 ixgbe_filterlist_flush();
1410 /* Remove all Traffic Manager configuration */
1411 ixgbe_tm_conf_uninit(eth_dev);
1413 #ifdef RTE_LIBRTE_SECURITY
1414 rte_free(eth_dev->security_ctx);
1420 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1422 struct ixgbe_filter_info *filter_info =
1423 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1424 struct ixgbe_5tuple_filter *p_5tuple;
1426 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1427 TAILQ_REMOVE(&filter_info->fivetuple_list,
1432 memset(filter_info->fivetuple_mask, 0,
1433 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1438 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1440 struct ixgbe_hw_fdir_info *fdir_info =
1441 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1442 struct ixgbe_fdir_filter *fdir_filter;
1444 if (fdir_info->hash_map)
1445 rte_free(fdir_info->hash_map);
1446 if (fdir_info->hash_handle)
1447 rte_hash_free(fdir_info->hash_handle);
1449 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1450 TAILQ_REMOVE(&fdir_info->fdir_list,
1453 rte_free(fdir_filter);
1459 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1461 struct ixgbe_l2_tn_info *l2_tn_info =
1462 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1463 struct ixgbe_l2_tn_filter *l2_tn_filter;
1465 if (l2_tn_info->hash_map)
1466 rte_free(l2_tn_info->hash_map);
1467 if (l2_tn_info->hash_handle)
1468 rte_hash_free(l2_tn_info->hash_handle);
1470 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1471 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1474 rte_free(l2_tn_filter);
1480 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1482 struct ixgbe_hw_fdir_info *fdir_info =
1483 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1484 char fdir_hash_name[RTE_HASH_NAMESIZE];
1485 struct rte_hash_parameters fdir_hash_params = {
1486 .name = fdir_hash_name,
1487 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1488 .key_len = sizeof(union ixgbe_atr_input),
1489 .hash_func = rte_hash_crc,
1490 .hash_func_init_val = 0,
1491 .socket_id = rte_socket_id(),
1494 TAILQ_INIT(&fdir_info->fdir_list);
1495 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1496 "fdir_%s", eth_dev->device->name);
1497 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1498 if (!fdir_info->hash_handle) {
1499 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1502 fdir_info->hash_map = rte_zmalloc("ixgbe",
1503 sizeof(struct ixgbe_fdir_filter *) *
1504 IXGBE_MAX_FDIR_FILTER_NUM,
1506 if (!fdir_info->hash_map) {
1508 "Failed to allocate memory for fdir hash map!");
1511 fdir_info->mask_added = FALSE;
1516 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1518 struct ixgbe_l2_tn_info *l2_tn_info =
1519 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1520 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1521 struct rte_hash_parameters l2_tn_hash_params = {
1522 .name = l2_tn_hash_name,
1523 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1524 .key_len = sizeof(struct ixgbe_l2_tn_key),
1525 .hash_func = rte_hash_crc,
1526 .hash_func_init_val = 0,
1527 .socket_id = rte_socket_id(),
1530 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1531 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1532 "l2_tn_%s", eth_dev->device->name);
1533 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1534 if (!l2_tn_info->hash_handle) {
1535 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1538 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1539 sizeof(struct ixgbe_l2_tn_filter *) *
1540 IXGBE_MAX_L2_TN_FILTER_NUM,
1542 if (!l2_tn_info->hash_map) {
1544 "Failed to allocate memory for L2 TN hash map!");
1547 l2_tn_info->e_tag_en = FALSE;
1548 l2_tn_info->e_tag_fwd_en = FALSE;
1549 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1554 * Negotiate mailbox API version with the PF.
1555 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1556 * Then we try to negotiate starting with the most recent one.
1557 * If all negotiation attempts fail, then we will proceed with
1558 * the default one (ixgbe_mbox_api_10).
1561 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1565 /* start with highest supported, proceed down */
1566 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1573 i != RTE_DIM(sup_ver) &&
1574 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1580 generate_random_mac_addr(struct ether_addr *mac_addr)
1584 /* Set Organizationally Unique Identifier (OUI) prefix. */
1585 mac_addr->addr_bytes[0] = 0x00;
1586 mac_addr->addr_bytes[1] = 0x09;
1587 mac_addr->addr_bytes[2] = 0xC0;
1588 /* Force indication of locally assigned MAC address. */
1589 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1590 /* Generate the last 3 bytes of the MAC address with a random number. */
1591 random = rte_rand();
1592 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1596 * Virtual Function device init
1599 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1603 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1604 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1605 struct ixgbe_hw *hw =
1606 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1607 struct ixgbe_vfta *shadow_vfta =
1608 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1609 struct ixgbe_hwstrip *hwstrip =
1610 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1611 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1613 PMD_INIT_FUNC_TRACE();
1615 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1616 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1617 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1619 /* for secondary processes, we don't initialise any further as primary
1620 * has already done this work. Only check we don't need a different
1623 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1624 struct ixgbe_tx_queue *txq;
1625 /* TX queue function in primary, set by last queue initialized
1626 * Tx queue may not initialized by primary process
1628 if (eth_dev->data->tx_queues) {
1629 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1630 ixgbe_set_tx_function(eth_dev, txq);
1632 /* Use default TX function if we get here */
1633 PMD_INIT_LOG(NOTICE,
1634 "No TX queues configured yet. Using default TX function.");
1637 ixgbe_set_rx_function(eth_dev);
1642 rte_eth_copy_pci_info(eth_dev, pci_dev);
1644 hw->device_id = pci_dev->id.device_id;
1645 hw->vendor_id = pci_dev->id.vendor_id;
1646 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1648 /* initialize the vfta */
1649 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1651 /* initialize the hw strip bitmap*/
1652 memset(hwstrip, 0, sizeof(*hwstrip));
1654 /* Initialize the shared code (base driver) */
1655 diag = ixgbe_init_shared_code(hw);
1656 if (diag != IXGBE_SUCCESS) {
1657 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1661 /* init_mailbox_params */
1662 hw->mbx.ops.init_params(hw);
1664 /* Reset the hw statistics */
1665 ixgbevf_dev_stats_reset(eth_dev);
1667 /* Disable the interrupts for VF */
1668 ixgbevf_intr_disable(hw);
1670 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1671 diag = hw->mac.ops.reset_hw(hw);
1674 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1675 * the underlying PF driver has not assigned a MAC address to the VF.
1676 * In this case, assign a random MAC address.
1678 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1679 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1683 /* negotiate mailbox API version to use with the PF. */
1684 ixgbevf_negotiate_api(hw);
1686 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1687 ixgbevf_get_queues(hw, &tcs, &tc);
1689 /* Allocate memory for storing MAC addresses */
1690 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1691 hw->mac.num_rar_entries, 0);
1692 if (eth_dev->data->mac_addrs == NULL) {
1694 "Failed to allocate %u bytes needed to store "
1696 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1700 /* Generate a random MAC address, if none was assigned by PF. */
1701 if (is_zero_ether_addr(perm_addr)) {
1702 generate_random_mac_addr(perm_addr);
1703 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1705 rte_free(eth_dev->data->mac_addrs);
1706 eth_dev->data->mac_addrs = NULL;
1709 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1710 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1711 "%02x:%02x:%02x:%02x:%02x:%02x",
1712 perm_addr->addr_bytes[0],
1713 perm_addr->addr_bytes[1],
1714 perm_addr->addr_bytes[2],
1715 perm_addr->addr_bytes[3],
1716 perm_addr->addr_bytes[4],
1717 perm_addr->addr_bytes[5]);
1720 /* Copy the permanent MAC address */
1721 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1723 /* reset the hardware with the new settings */
1724 diag = hw->mac.ops.start_hw(hw);
1730 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1734 rte_intr_callback_register(intr_handle,
1735 ixgbevf_dev_interrupt_handler, eth_dev);
1736 rte_intr_enable(intr_handle);
1737 ixgbevf_intr_enable(hw);
1739 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1740 eth_dev->data->port_id, pci_dev->id.vendor_id,
1741 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1746 /* Virtual Function device uninit */
1749 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1752 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1753 struct ixgbe_hw *hw;
1755 PMD_INIT_FUNC_TRACE();
1757 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1760 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1762 if (hw->adapter_stopped == 0)
1763 ixgbevf_dev_close(eth_dev);
1765 eth_dev->dev_ops = NULL;
1766 eth_dev->rx_pkt_burst = NULL;
1767 eth_dev->tx_pkt_burst = NULL;
1769 /* Disable the interrupts for VF */
1770 ixgbevf_intr_disable(hw);
1772 rte_free(eth_dev->data->mac_addrs);
1773 eth_dev->data->mac_addrs = NULL;
1775 rte_intr_disable(intr_handle);
1776 rte_intr_callback_unregister(intr_handle,
1777 ixgbevf_dev_interrupt_handler, eth_dev);
1782 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1783 struct rte_pci_device *pci_dev)
1785 return rte_eth_dev_pci_generic_probe(pci_dev,
1786 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1789 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1791 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1794 static struct rte_pci_driver rte_ixgbe_pmd = {
1795 .id_table = pci_id_ixgbe_map,
1796 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1797 RTE_PCI_DRV_IOVA_AS_VA,
1798 .probe = eth_ixgbe_pci_probe,
1799 .remove = eth_ixgbe_pci_remove,
1802 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1803 struct rte_pci_device *pci_dev)
1805 return rte_eth_dev_pci_generic_probe(pci_dev,
1806 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1809 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1811 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1815 * virtual function driver struct
1817 static struct rte_pci_driver rte_ixgbevf_pmd = {
1818 .id_table = pci_id_ixgbevf_map,
1819 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1820 .probe = eth_ixgbevf_pci_probe,
1821 .remove = eth_ixgbevf_pci_remove,
1825 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1827 struct ixgbe_hw *hw =
1828 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829 struct ixgbe_vfta *shadow_vfta =
1830 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1835 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1836 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1837 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1842 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1844 /* update local VFTA copy */
1845 shadow_vfta->vfta[vid_idx] = vfta;
1851 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1854 ixgbe_vlan_hw_strip_enable(dev, queue);
1856 ixgbe_vlan_hw_strip_disable(dev, queue);
1860 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1861 enum rte_vlan_type vlan_type,
1864 struct ixgbe_hw *hw =
1865 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1871 qinq &= IXGBE_DMATXCTL_GDV;
1873 switch (vlan_type) {
1874 case ETH_VLAN_TYPE_INNER:
1876 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1877 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1878 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1879 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1880 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1881 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1882 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1885 PMD_DRV_LOG(ERR, "Inner type is not supported"
1889 case ETH_VLAN_TYPE_OUTER:
1891 /* Only the high 16-bits is valid */
1892 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1893 IXGBE_EXVET_VET_EXT_SHIFT);
1895 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1896 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1897 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1898 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1899 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1900 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1901 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1907 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1915 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1917 struct ixgbe_hw *hw =
1918 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1921 PMD_INIT_FUNC_TRACE();
1923 /* Filter Table Disable */
1924 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1925 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1927 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1931 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1933 struct ixgbe_hw *hw =
1934 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935 struct ixgbe_vfta *shadow_vfta =
1936 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1940 PMD_INIT_FUNC_TRACE();
1942 /* Filter Table Enable */
1943 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1944 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1945 vlnctrl |= IXGBE_VLNCTRL_VFE;
1947 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1949 /* write whatever is in local vfta copy */
1950 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1951 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1955 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1957 struct ixgbe_hwstrip *hwstrip =
1958 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1959 struct ixgbe_rx_queue *rxq;
1961 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1965 IXGBE_SET_HWSTRIP(hwstrip, queue);
1967 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1969 if (queue >= dev->data->nb_rx_queues)
1972 rxq = dev->data->rx_queues[queue];
1975 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1977 rxq->vlan_flags = PKT_RX_VLAN;
1981 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1983 struct ixgbe_hw *hw =
1984 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987 PMD_INIT_FUNC_TRACE();
1989 if (hw->mac.type == ixgbe_mac_82598EB) {
1990 /* No queue level support */
1991 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1995 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1996 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1997 ctrl &= ~IXGBE_RXDCTL_VME;
1998 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2000 /* record those setting for HW strip per queue */
2001 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2005 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2007 struct ixgbe_hw *hw =
2008 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2011 PMD_INIT_FUNC_TRACE();
2013 if (hw->mac.type == ixgbe_mac_82598EB) {
2014 /* No queue level supported */
2015 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2019 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2020 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2021 ctrl |= IXGBE_RXDCTL_VME;
2022 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2024 /* record those setting for HW strip per queue */
2025 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2029 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2031 struct ixgbe_hw *hw =
2032 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035 struct ixgbe_rx_queue *rxq;
2037 PMD_INIT_FUNC_TRACE();
2039 if (hw->mac.type == ixgbe_mac_82598EB) {
2040 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2041 ctrl &= ~IXGBE_VLNCTRL_VME;
2042 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2044 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2045 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2046 rxq = dev->data->rx_queues[i];
2047 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2048 ctrl &= ~IXGBE_RXDCTL_VME;
2049 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2051 /* record those setting for HW strip per queue */
2052 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2058 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2060 struct ixgbe_hw *hw =
2061 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2064 struct ixgbe_rx_queue *rxq;
2066 PMD_INIT_FUNC_TRACE();
2068 if (hw->mac.type == ixgbe_mac_82598EB) {
2069 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2070 ctrl |= IXGBE_VLNCTRL_VME;
2071 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2073 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2074 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2075 rxq = dev->data->rx_queues[i];
2076 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2077 ctrl |= IXGBE_RXDCTL_VME;
2078 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2080 /* record those setting for HW strip per queue */
2081 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2087 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2089 struct ixgbe_hw *hw =
2090 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093 PMD_INIT_FUNC_TRACE();
2095 /* DMATXCTRL: Geric Double VLAN Disable */
2096 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2097 ctrl &= ~IXGBE_DMATXCTL_GDV;
2098 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2100 /* CTRL_EXT: Global Double VLAN Disable */
2101 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2102 ctrl &= ~IXGBE_EXTENDED_VLAN;
2103 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2108 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2110 struct ixgbe_hw *hw =
2111 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2114 PMD_INIT_FUNC_TRACE();
2116 /* DMATXCTRL: Geric Double VLAN Enable */
2117 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2118 ctrl |= IXGBE_DMATXCTL_GDV;
2119 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2121 /* CTRL_EXT: Global Double VLAN Enable */
2122 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2123 ctrl |= IXGBE_EXTENDED_VLAN;
2124 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2126 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2127 if (hw->mac.type == ixgbe_mac_X550 ||
2128 hw->mac.type == ixgbe_mac_X550EM_x ||
2129 hw->mac.type == ixgbe_mac_X550EM_a) {
2130 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2131 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2132 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2136 * VET EXT field in the EXVET register = 0x8100 by default
2137 * So no need to change. Same to VT field of DMATXCTL register
2142 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2144 if (mask & ETH_VLAN_STRIP_MASK) {
2145 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2146 ixgbe_vlan_hw_strip_enable_all(dev);
2148 ixgbe_vlan_hw_strip_disable_all(dev);
2151 if (mask & ETH_VLAN_FILTER_MASK) {
2152 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2153 ixgbe_vlan_hw_filter_enable(dev);
2155 ixgbe_vlan_hw_filter_disable(dev);
2158 if (mask & ETH_VLAN_EXTEND_MASK) {
2159 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2160 ixgbe_vlan_hw_extend_enable(dev);
2162 ixgbe_vlan_hw_extend_disable(dev);
2169 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2171 struct ixgbe_hw *hw =
2172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2174 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2176 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2177 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2181 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2183 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2188 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2191 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2197 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2198 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2204 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2206 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2207 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2209 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2211 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2212 /* check multi-queue mode */
2213 switch (dev_conf->rxmode.mq_mode) {
2214 case ETH_MQ_RX_VMDQ_DCB:
2215 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2217 case ETH_MQ_RX_VMDQ_DCB_RSS:
2218 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2219 PMD_INIT_LOG(ERR, "SRIOV active,"
2220 " unsupported mq_mode rx %d.",
2221 dev_conf->rxmode.mq_mode);
2224 case ETH_MQ_RX_VMDQ_RSS:
2225 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2226 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2227 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2228 PMD_INIT_LOG(ERR, "SRIOV is active,"
2229 " invalid queue number"
2230 " for VMDQ RSS, allowed"
2231 " value are 1, 2 or 4.");
2235 case ETH_MQ_RX_VMDQ_ONLY:
2236 case ETH_MQ_RX_NONE:
2237 /* if nothing mq mode configure, use default scheme */
2238 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2239 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2240 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2242 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2243 /* SRIOV only works in VMDq enable mode */
2244 PMD_INIT_LOG(ERR, "SRIOV is active,"
2245 " wrong mq_mode rx %d.",
2246 dev_conf->rxmode.mq_mode);
2250 switch (dev_conf->txmode.mq_mode) {
2251 case ETH_MQ_TX_VMDQ_DCB:
2252 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2253 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2255 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2256 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2260 /* check valid queue number */
2261 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2262 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2263 PMD_INIT_LOG(ERR, "SRIOV is active,"
2264 " nb_rx_q=%d nb_tx_q=%d queue number"
2265 " must be less than or equal to %d.",
2267 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2271 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2272 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2276 /* check configuration for vmdb+dcb mode */
2277 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2278 const struct rte_eth_vmdq_dcb_conf *conf;
2280 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2281 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2282 IXGBE_VMDQ_DCB_NB_QUEUES);
2285 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2286 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2287 conf->nb_queue_pools == ETH_32_POOLS)) {
2288 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2289 " nb_queue_pools must be %d or %d.",
2290 ETH_16_POOLS, ETH_32_POOLS);
2294 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2295 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2297 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2298 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2299 IXGBE_VMDQ_DCB_NB_QUEUES);
2302 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2303 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2304 conf->nb_queue_pools == ETH_32_POOLS)) {
2305 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2306 " nb_queue_pools != %d and"
2307 " nb_queue_pools != %d.",
2308 ETH_16_POOLS, ETH_32_POOLS);
2313 /* For DCB mode check our configuration before we go further */
2314 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2315 const struct rte_eth_dcb_rx_conf *conf;
2317 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2318 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2319 IXGBE_DCB_NB_QUEUES);
2322 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2323 if (!(conf->nb_tcs == ETH_4_TCS ||
2324 conf->nb_tcs == ETH_8_TCS)) {
2325 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2326 " and nb_tcs != %d.",
2327 ETH_4_TCS, ETH_8_TCS);
2332 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2333 const struct rte_eth_dcb_tx_conf *conf;
2335 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2336 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2337 IXGBE_DCB_NB_QUEUES);
2340 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2341 if (!(conf->nb_tcs == ETH_4_TCS ||
2342 conf->nb_tcs == ETH_8_TCS)) {
2343 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2344 " and nb_tcs != %d.",
2345 ETH_4_TCS, ETH_8_TCS);
2351 * When DCB/VT is off, maximum number of queues changes,
2352 * except for 82598EB, which remains constant.
2354 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2355 hw->mac.type != ixgbe_mac_82598EB) {
2356 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2358 "Neither VT nor DCB are enabled, "
2360 IXGBE_NONE_MODE_TX_NB_QUEUES);
2369 ixgbe_dev_configure(struct rte_eth_dev *dev)
2371 struct ixgbe_interrupt *intr =
2372 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2373 struct ixgbe_adapter *adapter =
2374 (struct ixgbe_adapter *)dev->data->dev_private;
2377 PMD_INIT_FUNC_TRACE();
2378 /* multipe queue mode checking */
2379 ret = ixgbe_check_mq_mode(dev);
2381 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2386 /* set flag to update link status after init */
2387 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2390 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2391 * allocation or vector Rx preconditions we will reset it.
2393 adapter->rx_bulk_alloc_allowed = true;
2394 adapter->rx_vec_allowed = true;
2400 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2402 struct ixgbe_hw *hw =
2403 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct ixgbe_interrupt *intr =
2405 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2408 /* only set up it on X550EM_X */
2409 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2410 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2411 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2412 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2413 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2414 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2419 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2420 uint16_t tx_rate, uint64_t q_msk)
2422 struct ixgbe_hw *hw;
2423 struct ixgbe_vf_info *vfinfo;
2424 struct rte_eth_link link;
2425 uint8_t nb_q_per_pool;
2426 uint32_t queue_stride;
2427 uint32_t queue_idx, idx = 0, vf_idx;
2429 uint16_t total_rate = 0;
2430 struct rte_pci_device *pci_dev;
2432 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2433 rte_eth_link_get_nowait(dev->data->port_id, &link);
2435 if (vf >= pci_dev->max_vfs)
2438 if (tx_rate > link.link_speed)
2444 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2445 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2446 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2447 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2448 queue_idx = vf * queue_stride;
2449 queue_end = queue_idx + nb_q_per_pool - 1;
2450 if (queue_end >= hw->mac.max_tx_queues)
2454 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2457 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2459 total_rate += vfinfo[vf_idx].tx_rate[idx];
2465 /* Store tx_rate for this vf. */
2466 for (idx = 0; idx < nb_q_per_pool; idx++) {
2467 if (((uint64_t)0x1 << idx) & q_msk) {
2468 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2469 vfinfo[vf].tx_rate[idx] = tx_rate;
2470 total_rate += tx_rate;
2474 if (total_rate > dev->data->dev_link.link_speed) {
2475 /* Reset stored TX rate of the VF if it causes exceed
2478 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2482 /* Set RTTBCNRC of each queue/pool for vf X */
2483 for (; queue_idx <= queue_end; queue_idx++) {
2485 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2493 * Configure device link speed and setup link.
2494 * It returns 0 on success.
2497 ixgbe_dev_start(struct rte_eth_dev *dev)
2499 struct ixgbe_hw *hw =
2500 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2501 struct ixgbe_vf_info *vfinfo =
2502 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2503 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2504 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2505 uint32_t intr_vector = 0;
2506 int err, link_up = 0, negotiate = 0;
2511 uint32_t *link_speeds;
2512 struct ixgbe_tm_conf *tm_conf =
2513 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2515 PMD_INIT_FUNC_TRACE();
2517 /* IXGBE devices don't support:
2518 * - half duplex (checked afterwards for valid speeds)
2519 * - fixed speed: TODO implement
2521 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2523 "Invalid link_speeds for port %u, fix speed not supported",
2524 dev->data->port_id);
2528 /* disable uio/vfio intr/eventfd mapping */
2529 rte_intr_disable(intr_handle);
2532 hw->adapter_stopped = 0;
2533 ixgbe_stop_adapter(hw);
2535 /* reinitialize adapter
2536 * this calls reset and start
2538 status = ixgbe_pf_reset_hw(hw);
2541 hw->mac.ops.start_hw(hw);
2542 hw->mac.get_link_status = true;
2544 /* configure PF module if SRIOV enabled */
2545 ixgbe_pf_host_configure(dev);
2547 ixgbe_dev_phy_intr_setup(dev);
2549 /* check and configure queue intr-vector mapping */
2550 if ((rte_intr_cap_multiple(intr_handle) ||
2551 !RTE_ETH_DEV_SRIOV(dev).active) &&
2552 dev->data->dev_conf.intr_conf.rxq != 0) {
2553 intr_vector = dev->data->nb_rx_queues;
2554 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2555 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2556 IXGBE_MAX_INTR_QUEUE_NUM);
2559 if (rte_intr_efd_enable(intr_handle, intr_vector))
2563 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2564 intr_handle->intr_vec =
2565 rte_zmalloc("intr_vec",
2566 dev->data->nb_rx_queues * sizeof(int), 0);
2567 if (intr_handle->intr_vec == NULL) {
2568 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2569 " intr_vec", dev->data->nb_rx_queues);
2574 /* confiugre msix for sleep until rx interrupt */
2575 ixgbe_configure_msix(dev);
2577 /* initialize transmission unit */
2578 ixgbe_dev_tx_init(dev);
2580 /* This can fail when allocating mbufs for descriptor rings */
2581 err = ixgbe_dev_rx_init(dev);
2583 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2587 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2588 ETH_VLAN_EXTEND_MASK;
2589 err = ixgbe_vlan_offload_set(dev, mask);
2591 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2595 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2596 /* Enable vlan filtering for VMDq */
2597 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2600 /* Configure DCB hw */
2601 ixgbe_configure_dcb(dev);
2603 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2604 err = ixgbe_fdir_configure(dev);
2609 /* Restore vf rate limit */
2610 if (vfinfo != NULL) {
2611 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2612 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2613 if (vfinfo[vf].tx_rate[idx] != 0)
2614 ixgbe_set_vf_rate_limit(
2616 vfinfo[vf].tx_rate[idx],
2620 ixgbe_restore_statistics_mapping(dev);
2622 err = ixgbe_dev_rxtx_start(dev);
2624 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2628 /* Skip link setup if loopback mode is enabled for 82599. */
2629 if (hw->mac.type == ixgbe_mac_82599EB &&
2630 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2631 goto skip_link_setup;
2633 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2634 err = hw->mac.ops.setup_sfp(hw);
2639 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2640 /* Turn on the copper */
2641 ixgbe_set_phy_power(hw, true);
2643 /* Turn on the laser */
2644 ixgbe_enable_tx_laser(hw);
2647 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2650 dev->data->dev_link.link_status = link_up;
2652 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2656 link_speeds = &dev->data->dev_conf.link_speeds;
2657 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2658 ETH_LINK_SPEED_10G)) {
2659 PMD_INIT_LOG(ERR, "Invalid link setting");
2664 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2665 switch (hw->mac.type) {
2666 case ixgbe_mac_82598EB:
2667 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2669 case ixgbe_mac_82599EB:
2670 case ixgbe_mac_X540:
2671 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2673 case ixgbe_mac_X550:
2674 case ixgbe_mac_X550EM_x:
2675 case ixgbe_mac_X550EM_a:
2676 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2679 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2682 if (*link_speeds & ETH_LINK_SPEED_10G)
2683 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2684 if (*link_speeds & ETH_LINK_SPEED_1G)
2685 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2686 if (*link_speeds & ETH_LINK_SPEED_100M)
2687 speed |= IXGBE_LINK_SPEED_100_FULL;
2690 err = ixgbe_setup_link(hw, speed, link_up);
2696 if (rte_intr_allow_others(intr_handle)) {
2697 /* check if lsc interrupt is enabled */
2698 if (dev->data->dev_conf.intr_conf.lsc != 0)
2699 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2701 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2702 ixgbe_dev_macsec_interrupt_setup(dev);
2704 rte_intr_callback_unregister(intr_handle,
2705 ixgbe_dev_interrupt_handler, dev);
2706 if (dev->data->dev_conf.intr_conf.lsc != 0)
2707 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2708 " no intr multiplex");
2711 /* check if rxq interrupt is enabled */
2712 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2713 rte_intr_dp_is_en(intr_handle))
2714 ixgbe_dev_rxq_interrupt_setup(dev);
2716 /* enable uio/vfio intr/eventfd mapping */
2717 rte_intr_enable(intr_handle);
2719 /* resume enabled intr since hw reset */
2720 ixgbe_enable_intr(dev);
2721 ixgbe_l2_tunnel_conf(dev);
2722 ixgbe_filter_restore(dev);
2724 if (tm_conf->root && !tm_conf->committed)
2725 PMD_DRV_LOG(WARNING,
2726 "please call hierarchy_commit() "
2727 "before starting the port");
2732 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2733 ixgbe_dev_clear_queues(dev);
2738 * Stop device: disable rx and tx functions to allow for reconfiguring.
2741 ixgbe_dev_stop(struct rte_eth_dev *dev)
2743 struct rte_eth_link link;
2744 struct ixgbe_hw *hw =
2745 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2746 struct ixgbe_vf_info *vfinfo =
2747 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2748 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2749 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2751 struct ixgbe_tm_conf *tm_conf =
2752 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2754 PMD_INIT_FUNC_TRACE();
2756 /* disable interrupts */
2757 ixgbe_disable_intr(hw);
2760 ixgbe_pf_reset_hw(hw);
2761 hw->adapter_stopped = 0;
2764 ixgbe_stop_adapter(hw);
2766 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2767 vfinfo[vf].clear_to_send = false;
2769 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2770 /* Turn off the copper */
2771 ixgbe_set_phy_power(hw, false);
2773 /* Turn off the laser */
2774 ixgbe_disable_tx_laser(hw);
2777 ixgbe_dev_clear_queues(dev);
2779 /* Clear stored conf */
2780 dev->data->scattered_rx = 0;
2783 /* Clear recorded link status */
2784 memset(&link, 0, sizeof(link));
2785 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2787 if (!rte_intr_allow_others(intr_handle))
2788 /* resume to the default handler */
2789 rte_intr_callback_register(intr_handle,
2790 ixgbe_dev_interrupt_handler,
2793 /* Clean datapath event and queue/vec mapping */
2794 rte_intr_efd_disable(intr_handle);
2795 if (intr_handle->intr_vec != NULL) {
2796 rte_free(intr_handle->intr_vec);
2797 intr_handle->intr_vec = NULL;
2800 /* reset hierarchy commit */
2801 tm_conf->committed = false;
2805 * Set device link up: enable tx.
2808 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2810 struct ixgbe_hw *hw =
2811 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 if (hw->mac.type == ixgbe_mac_82599EB) {
2813 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2814 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2815 /* Not suported in bypass mode */
2816 PMD_INIT_LOG(ERR, "Set link up is not supported "
2817 "by device id 0x%x", hw->device_id);
2823 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2824 /* Turn on the copper */
2825 ixgbe_set_phy_power(hw, true);
2827 /* Turn on the laser */
2828 ixgbe_enable_tx_laser(hw);
2835 * Set device link down: disable tx.
2838 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2840 struct ixgbe_hw *hw =
2841 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 if (hw->mac.type == ixgbe_mac_82599EB) {
2843 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2844 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2845 /* Not suported in bypass mode */
2846 PMD_INIT_LOG(ERR, "Set link down is not supported "
2847 "by device id 0x%x", hw->device_id);
2853 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2854 /* Turn off the copper */
2855 ixgbe_set_phy_power(hw, false);
2857 /* Turn off the laser */
2858 ixgbe_disable_tx_laser(hw);
2865 * Reset and stop device.
2868 ixgbe_dev_close(struct rte_eth_dev *dev)
2870 struct ixgbe_hw *hw =
2871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873 PMD_INIT_FUNC_TRACE();
2875 ixgbe_pf_reset_hw(hw);
2877 ixgbe_dev_stop(dev);
2878 hw->adapter_stopped = 1;
2880 ixgbe_dev_free_queues(dev);
2882 ixgbe_disable_pcie_master(hw);
2884 /* reprogram the RAR[0] in case user changed it. */
2885 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2892 ixgbe_dev_reset(struct rte_eth_dev *dev)
2896 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2897 * its VF to make them align with it. The detailed notification
2898 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2899 * To avoid unexpected behavior in VF, currently reset of PF with
2900 * SR-IOV activation is not supported. It might be supported later.
2902 if (dev->data->sriov.active)
2905 ret = eth_ixgbe_dev_uninit(dev);
2909 ret = eth_ixgbe_dev_init(dev);
2915 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2916 struct ixgbe_hw_stats *hw_stats,
2917 struct ixgbe_macsec_stats *macsec_stats,
2918 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2919 uint64_t *total_qprc, uint64_t *total_qprdc)
2921 uint32_t bprc, lxon, lxoff, total;
2922 uint32_t delta_gprc = 0;
2924 /* Workaround for RX byte count not including CRC bytes when CRC
2925 * strip is enabled. CRC bytes are removed from counters when crc_strip
2928 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2929 IXGBE_HLREG0_RXCRCSTRP);
2931 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2932 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2933 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2934 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2936 for (i = 0; i < 8; i++) {
2937 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2939 /* global total per queue */
2940 hw_stats->mpc[i] += mp;
2941 /* Running comprehensive total for stats display */
2942 *total_missed_rx += hw_stats->mpc[i];
2943 if (hw->mac.type == ixgbe_mac_82598EB) {
2944 hw_stats->rnbc[i] +=
2945 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2946 hw_stats->pxonrxc[i] +=
2947 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2948 hw_stats->pxoffrxc[i] +=
2949 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2951 hw_stats->pxonrxc[i] +=
2952 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2953 hw_stats->pxoffrxc[i] +=
2954 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2955 hw_stats->pxon2offc[i] +=
2956 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2958 hw_stats->pxontxc[i] +=
2959 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2960 hw_stats->pxofftxc[i] +=
2961 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2963 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2964 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2965 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2966 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2968 delta_gprc += delta_qprc;
2970 hw_stats->qprc[i] += delta_qprc;
2971 hw_stats->qptc[i] += delta_qptc;
2973 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2974 hw_stats->qbrc[i] +=
2975 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2977 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2979 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2980 hw_stats->qbtc[i] +=
2981 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2983 hw_stats->qprdc[i] += delta_qprdc;
2984 *total_qprdc += hw_stats->qprdc[i];
2986 *total_qprc += hw_stats->qprc[i];
2987 *total_qbrc += hw_stats->qbrc[i];
2989 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2990 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2991 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2994 * An errata states that gprc actually counts good + missed packets:
2995 * Workaround to set gprc to summated queue packet receives
2997 hw_stats->gprc = *total_qprc;
2999 if (hw->mac.type != ixgbe_mac_82598EB) {
3000 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3001 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3002 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3003 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3004 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3005 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3006 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3007 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3009 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3010 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3011 /* 82598 only has a counter in the high register */
3012 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3013 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3014 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3016 uint64_t old_tpr = hw_stats->tpr;
3018 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3019 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3022 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
3024 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3025 hw_stats->gptc += delta_gptc;
3026 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
3027 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
3030 * Workaround: mprc hardware is incorrectly counting
3031 * broadcasts, so for now we subtract those.
3033 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3034 hw_stats->bprc += bprc;
3035 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3036 if (hw->mac.type == ixgbe_mac_82598EB)
3037 hw_stats->mprc -= bprc;
3039 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3040 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3041 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3042 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3043 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3044 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3046 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3047 hw_stats->lxontxc += lxon;
3048 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3049 hw_stats->lxofftxc += lxoff;
3050 total = lxon + lxoff;
3052 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3053 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3054 hw_stats->gptc -= total;
3055 hw_stats->mptc -= total;
3056 hw_stats->ptc64 -= total;
3057 hw_stats->gotc -= total * ETHER_MIN_LEN;
3059 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3060 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3061 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3062 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3063 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3064 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3065 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3066 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3067 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3068 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3069 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3070 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3071 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3072 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3073 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3074 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3075 /* Only read FCOE on 82599 */
3076 if (hw->mac.type != ixgbe_mac_82598EB) {
3077 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3078 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3079 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3080 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3081 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3084 /* Flow Director Stats registers */
3085 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3086 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3088 /* MACsec Stats registers */
3089 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3090 macsec_stats->out_pkts_encrypted +=
3091 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3092 macsec_stats->out_pkts_protected +=
3093 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3094 macsec_stats->out_octets_encrypted +=
3095 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3096 macsec_stats->out_octets_protected +=
3097 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3098 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3099 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3100 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3101 macsec_stats->in_pkts_unknownsci +=
3102 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3103 macsec_stats->in_octets_decrypted +=
3104 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3105 macsec_stats->in_octets_validated +=
3106 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3107 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3108 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3109 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3110 for (i = 0; i < 2; i++) {
3111 macsec_stats->in_pkts_ok +=
3112 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3113 macsec_stats->in_pkts_invalid +=
3114 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3115 macsec_stats->in_pkts_notvalid +=
3116 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3118 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3119 macsec_stats->in_pkts_notusingsa +=
3120 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3124 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3127 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3129 struct ixgbe_hw *hw =
3130 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3131 struct ixgbe_hw_stats *hw_stats =
3132 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3133 struct ixgbe_macsec_stats *macsec_stats =
3134 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3135 dev->data->dev_private);
3136 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3139 total_missed_rx = 0;
3144 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3145 &total_qbrc, &total_qprc, &total_qprdc);
3150 /* Fill out the rte_eth_stats statistics structure */
3151 stats->ipackets = total_qprc;
3152 stats->ibytes = total_qbrc;
3153 stats->opackets = hw_stats->gptc;
3154 stats->obytes = hw_stats->gotc;
3156 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3157 stats->q_ipackets[i] = hw_stats->qprc[i];
3158 stats->q_opackets[i] = hw_stats->qptc[i];
3159 stats->q_ibytes[i] = hw_stats->qbrc[i];
3160 stats->q_obytes[i] = hw_stats->qbtc[i];
3161 stats->q_errors[i] = hw_stats->qprdc[i];
3165 stats->imissed = total_missed_rx;
3166 stats->ierrors = hw_stats->crcerrs +
3183 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3185 struct ixgbe_hw_stats *stats =
3186 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3188 /* HW registers are cleared on read */
3189 ixgbe_dev_stats_get(dev, NULL);
3191 /* Reset software totals */
3192 memset(stats, 0, sizeof(*stats));
3195 /* This function calculates the number of xstats based on the current config */
3197 ixgbe_xstats_calc_num(void) {
3198 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3199 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3200 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3203 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3204 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3206 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3207 unsigned stat, i, count;
3209 if (xstats_names != NULL) {
3212 /* Note: limit >= cnt_stats checked upstream
3213 * in rte_eth_xstats_names()
3216 /* Extended stats from ixgbe_hw_stats */
3217 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3218 snprintf(xstats_names[count].name,
3219 sizeof(xstats_names[count].name),
3221 rte_ixgbe_stats_strings[i].name);
3226 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3227 snprintf(xstats_names[count].name,
3228 sizeof(xstats_names[count].name),
3230 rte_ixgbe_macsec_strings[i].name);
3234 /* RX Priority Stats */
3235 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3236 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3237 snprintf(xstats_names[count].name,
3238 sizeof(xstats_names[count].name),
3239 "rx_priority%u_%s", i,
3240 rte_ixgbe_rxq_strings[stat].name);
3245 /* TX Priority Stats */
3246 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3247 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3248 snprintf(xstats_names[count].name,
3249 sizeof(xstats_names[count].name),
3250 "tx_priority%u_%s", i,
3251 rte_ixgbe_txq_strings[stat].name);
3259 static int ixgbe_dev_xstats_get_names_by_id(
3260 struct rte_eth_dev *dev,
3261 struct rte_eth_xstat_name *xstats_names,
3262 const uint64_t *ids,
3266 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3267 unsigned int stat, i, count;
3269 if (xstats_names != NULL) {
3272 /* Note: limit >= cnt_stats checked upstream
3273 * in rte_eth_xstats_names()
3276 /* Extended stats from ixgbe_hw_stats */
3277 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3278 snprintf(xstats_names[count].name,
3279 sizeof(xstats_names[count].name),
3281 rte_ixgbe_stats_strings[i].name);
3286 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3287 snprintf(xstats_names[count].name,
3288 sizeof(xstats_names[count].name),
3290 rte_ixgbe_macsec_strings[i].name);
3294 /* RX Priority Stats */
3295 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3296 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3297 snprintf(xstats_names[count].name,
3298 sizeof(xstats_names[count].name),
3299 "rx_priority%u_%s", i,
3300 rte_ixgbe_rxq_strings[stat].name);
3305 /* TX Priority Stats */
3306 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3307 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3308 snprintf(xstats_names[count].name,
3309 sizeof(xstats_names[count].name),
3310 "tx_priority%u_%s", i,
3311 rte_ixgbe_txq_strings[stat].name);
3320 uint16_t size = ixgbe_xstats_calc_num();
3321 struct rte_eth_xstat_name xstats_names_copy[size];
3323 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3326 for (i = 0; i < limit; i++) {
3327 if (ids[i] >= size) {
3328 PMD_INIT_LOG(ERR, "id value isn't valid");
3331 strcpy(xstats_names[i].name,
3332 xstats_names_copy[ids[i]].name);
3337 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3338 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3342 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3345 if (xstats_names != NULL)
3346 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3347 snprintf(xstats_names[i].name,
3348 sizeof(xstats_names[i].name),
3349 "%s", rte_ixgbevf_stats_strings[i].name);
3350 return IXGBEVF_NB_XSTATS;
3354 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3357 struct ixgbe_hw *hw =
3358 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359 struct ixgbe_hw_stats *hw_stats =
3360 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3361 struct ixgbe_macsec_stats *macsec_stats =
3362 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3363 dev->data->dev_private);
3364 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3365 unsigned i, stat, count = 0;
3367 count = ixgbe_xstats_calc_num();
3372 total_missed_rx = 0;
3377 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3378 &total_qbrc, &total_qprc, &total_qprdc);
3380 /* If this is a reset xstats is NULL, and we have cleared the
3381 * registers by reading them.
3386 /* Extended stats from ixgbe_hw_stats */
3388 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3389 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3390 rte_ixgbe_stats_strings[i].offset);
3391 xstats[count].id = count;
3396 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3397 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3398 rte_ixgbe_macsec_strings[i].offset);
3399 xstats[count].id = count;
3403 /* RX Priority Stats */
3404 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3405 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3406 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3407 rte_ixgbe_rxq_strings[stat].offset +
3408 (sizeof(uint64_t) * i));
3409 xstats[count].id = count;
3414 /* TX Priority Stats */
3415 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3416 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3417 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3418 rte_ixgbe_txq_strings[stat].offset +
3419 (sizeof(uint64_t) * i));
3420 xstats[count].id = count;
3428 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3429 uint64_t *values, unsigned int n)
3432 struct ixgbe_hw *hw =
3433 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434 struct ixgbe_hw_stats *hw_stats =
3435 IXGBE_DEV_PRIVATE_TO_STATS(
3436 dev->data->dev_private);
3437 struct ixgbe_macsec_stats *macsec_stats =
3438 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3439 dev->data->dev_private);
3440 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3441 unsigned int i, stat, count = 0;
3443 count = ixgbe_xstats_calc_num();
3445 if (!ids && n < count)
3448 total_missed_rx = 0;
3453 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3454 &total_missed_rx, &total_qbrc, &total_qprc,
3457 /* If this is a reset xstats is NULL, and we have cleared the
3458 * registers by reading them.
3460 if (!ids && !values)
3463 /* Extended stats from ixgbe_hw_stats */
3465 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3466 values[count] = *(uint64_t *)(((char *)hw_stats) +
3467 rte_ixgbe_stats_strings[i].offset);
3472 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3473 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3474 rte_ixgbe_macsec_strings[i].offset);
3478 /* RX Priority Stats */
3479 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3480 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3482 *(uint64_t *)(((char *)hw_stats) +
3483 rte_ixgbe_rxq_strings[stat].offset +
3484 (sizeof(uint64_t) * i));
3489 /* TX Priority Stats */
3490 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3491 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3493 *(uint64_t *)(((char *)hw_stats) +
3494 rte_ixgbe_txq_strings[stat].offset +
3495 (sizeof(uint64_t) * i));
3503 uint16_t size = ixgbe_xstats_calc_num();
3504 uint64_t values_copy[size];
3506 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3508 for (i = 0; i < n; i++) {
3509 if (ids[i] >= size) {
3510 PMD_INIT_LOG(ERR, "id value isn't valid");
3513 values[i] = values_copy[ids[i]];
3519 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3521 struct ixgbe_hw_stats *stats =
3522 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3523 struct ixgbe_macsec_stats *macsec_stats =
3524 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3525 dev->data->dev_private);
3527 unsigned count = ixgbe_xstats_calc_num();
3529 /* HW registers are cleared on read */
3530 ixgbe_dev_xstats_get(dev, NULL, count);
3532 /* Reset software totals */
3533 memset(stats, 0, sizeof(*stats));
3534 memset(macsec_stats, 0, sizeof(*macsec_stats));
3538 ixgbevf_update_stats(struct rte_eth_dev *dev)
3540 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3541 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3542 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3544 /* Good Rx packet, include VF loopback */
3545 UPDATE_VF_STAT(IXGBE_VFGPRC,
3546 hw_stats->last_vfgprc, hw_stats->vfgprc);
3548 /* Good Rx octets, include VF loopback */
3549 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3550 hw_stats->last_vfgorc, hw_stats->vfgorc);
3552 /* Good Tx packet, include VF loopback */
3553 UPDATE_VF_STAT(IXGBE_VFGPTC,
3554 hw_stats->last_vfgptc, hw_stats->vfgptc);
3556 /* Good Tx octets, include VF loopback */
3557 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3558 hw_stats->last_vfgotc, hw_stats->vfgotc);
3560 /* Rx Multicst Packet */
3561 UPDATE_VF_STAT(IXGBE_VFMPRC,
3562 hw_stats->last_vfmprc, hw_stats->vfmprc);
3566 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3569 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3570 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3573 if (n < IXGBEVF_NB_XSTATS)
3574 return IXGBEVF_NB_XSTATS;
3576 ixgbevf_update_stats(dev);
3581 /* Extended stats */
3582 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3584 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3585 rte_ixgbevf_stats_strings[i].offset);
3588 return IXGBEVF_NB_XSTATS;
3592 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3594 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3595 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3597 ixgbevf_update_stats(dev);
3602 stats->ipackets = hw_stats->vfgprc;
3603 stats->ibytes = hw_stats->vfgorc;
3604 stats->opackets = hw_stats->vfgptc;
3605 stats->obytes = hw_stats->vfgotc;
3610 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3612 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3613 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3615 /* Sync HW register to the last stats */
3616 ixgbevf_dev_stats_get(dev, NULL);
3618 /* reset HW current stats*/
3619 hw_stats->vfgprc = 0;
3620 hw_stats->vfgorc = 0;
3621 hw_stats->vfgptc = 0;
3622 hw_stats->vfgotc = 0;
3626 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3628 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3629 u16 eeprom_verh, eeprom_verl;
3633 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3634 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3636 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3637 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3639 ret += 1; /* add the size of '\0' */
3640 if (fw_size < (u32)ret)
3647 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3649 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3650 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3653 dev_info->pci_dev = pci_dev;
3654 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3655 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3656 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3658 * When DCB/VT is off, maximum number of queues changes,
3659 * except for 82598EB, which remains constant.
3661 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3662 hw->mac.type != ixgbe_mac_82598EB)
3663 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3665 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3666 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3667 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3668 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3669 dev_info->max_vfs = pci_dev->max_vfs;
3670 if (hw->mac.type == ixgbe_mac_82598EB)
3671 dev_info->max_vmdq_pools = ETH_16_POOLS;
3673 dev_info->max_vmdq_pools = ETH_64_POOLS;
3674 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3675 dev_info->rx_offload_capa =
3676 DEV_RX_OFFLOAD_VLAN_STRIP |
3677 DEV_RX_OFFLOAD_IPV4_CKSUM |
3678 DEV_RX_OFFLOAD_UDP_CKSUM |
3679 DEV_RX_OFFLOAD_TCP_CKSUM;
3682 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3685 if ((hw->mac.type == ixgbe_mac_82599EB ||
3686 hw->mac.type == ixgbe_mac_X540) &&
3687 !RTE_ETH_DEV_SRIOV(dev).active)
3688 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3690 if (hw->mac.type == ixgbe_mac_82599EB ||
3691 hw->mac.type == ixgbe_mac_X540)
3692 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3694 if (hw->mac.type == ixgbe_mac_X550 ||
3695 hw->mac.type == ixgbe_mac_X550EM_x ||
3696 hw->mac.type == ixgbe_mac_X550EM_a)
3697 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3699 dev_info->tx_offload_capa =
3700 DEV_TX_OFFLOAD_VLAN_INSERT |
3701 DEV_TX_OFFLOAD_IPV4_CKSUM |
3702 DEV_TX_OFFLOAD_UDP_CKSUM |
3703 DEV_TX_OFFLOAD_TCP_CKSUM |
3704 DEV_TX_OFFLOAD_SCTP_CKSUM |
3705 DEV_TX_OFFLOAD_TCP_TSO;
3707 if (hw->mac.type == ixgbe_mac_82599EB ||
3708 hw->mac.type == ixgbe_mac_X540)
3709 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3711 if (hw->mac.type == ixgbe_mac_X550 ||
3712 hw->mac.type == ixgbe_mac_X550EM_x ||
3713 hw->mac.type == ixgbe_mac_X550EM_a)
3714 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3716 #ifdef RTE_LIBRTE_SECURITY
3717 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_SECURITY;
3718 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3721 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3723 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3724 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3725 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3727 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3731 dev_info->default_txconf = (struct rte_eth_txconf) {
3733 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3734 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3735 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3737 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3738 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3739 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3740 ETH_TXQ_FLAGS_NOOFFLOADS,
3743 dev_info->rx_desc_lim = rx_desc_lim;
3744 dev_info->tx_desc_lim = tx_desc_lim;
3746 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3747 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3748 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3750 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3751 if (hw->mac.type == ixgbe_mac_X540 ||
3752 hw->mac.type == ixgbe_mac_X540_vf ||
3753 hw->mac.type == ixgbe_mac_X550 ||
3754 hw->mac.type == ixgbe_mac_X550_vf) {
3755 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3757 if (hw->mac.type == ixgbe_mac_X550) {
3758 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3759 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3763 static const uint32_t *
3764 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3766 static const uint32_t ptypes[] = {
3767 /* For non-vec functions,
3768 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3769 * for vec functions,
3770 * refers to _recv_raw_pkts_vec().
3774 RTE_PTYPE_L3_IPV4_EXT,
3776 RTE_PTYPE_L3_IPV6_EXT,
3780 RTE_PTYPE_TUNNEL_IP,
3781 RTE_PTYPE_INNER_L3_IPV6,
3782 RTE_PTYPE_INNER_L3_IPV6_EXT,
3783 RTE_PTYPE_INNER_L4_TCP,
3784 RTE_PTYPE_INNER_L4_UDP,
3788 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3789 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3790 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3791 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3794 #if defined(RTE_ARCH_X86)
3795 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3796 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3803 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3804 struct rte_eth_dev_info *dev_info)
3806 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 dev_info->pci_dev = pci_dev;
3810 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3811 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3812 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3813 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3814 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3815 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3816 dev_info->max_vfs = pci_dev->max_vfs;
3817 if (hw->mac.type == ixgbe_mac_82598EB)
3818 dev_info->max_vmdq_pools = ETH_16_POOLS;
3820 dev_info->max_vmdq_pools = ETH_64_POOLS;
3821 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3822 DEV_RX_OFFLOAD_IPV4_CKSUM |
3823 DEV_RX_OFFLOAD_UDP_CKSUM |
3824 DEV_RX_OFFLOAD_TCP_CKSUM;
3825 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3826 DEV_TX_OFFLOAD_IPV4_CKSUM |
3827 DEV_TX_OFFLOAD_UDP_CKSUM |
3828 DEV_TX_OFFLOAD_TCP_CKSUM |
3829 DEV_TX_OFFLOAD_SCTP_CKSUM |
3830 DEV_TX_OFFLOAD_TCP_TSO;
3832 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3834 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3835 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3836 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3838 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3842 dev_info->default_txconf = (struct rte_eth_txconf) {
3844 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3845 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3846 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3848 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3849 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3850 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3851 ETH_TXQ_FLAGS_NOOFFLOADS,
3854 dev_info->rx_desc_lim = rx_desc_lim;
3855 dev_info->tx_desc_lim = tx_desc_lim;
3859 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3860 int *link_up, int wait_to_complete)
3863 * for a quick link status checking, wait_to_compelet == 0,
3864 * skip PF link status checking
3866 bool no_pflink_check = wait_to_complete == 0;
3867 struct ixgbe_mbx_info *mbx = &hw->mbx;
3868 struct ixgbe_mac_info *mac = &hw->mac;
3869 uint32_t links_reg, in_msg;
3872 /* If we were hit with a reset drop the link */
3873 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3874 mac->get_link_status = true;
3876 if (!mac->get_link_status)
3879 /* if link status is down no point in checking to see if pf is up */
3880 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3881 if (!(links_reg & IXGBE_LINKS_UP))
3884 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3885 * before the link status is correct
3887 if (mac->type == ixgbe_mac_82599_vf) {
3890 for (i = 0; i < 5; i++) {
3892 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3894 if (!(links_reg & IXGBE_LINKS_UP))
3899 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3900 case IXGBE_LINKS_SPEED_10G_82599:
3901 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3902 if (hw->mac.type >= ixgbe_mac_X550) {
3903 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3904 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3907 case IXGBE_LINKS_SPEED_1G_82599:
3908 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3910 case IXGBE_LINKS_SPEED_100_82599:
3911 *speed = IXGBE_LINK_SPEED_100_FULL;
3912 if (hw->mac.type == ixgbe_mac_X550) {
3913 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3914 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3917 case IXGBE_LINKS_SPEED_10_X550EM_A:
3918 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3919 /* Since Reserved in older MAC's */
3920 if (hw->mac.type >= ixgbe_mac_X550)
3921 *speed = IXGBE_LINK_SPEED_10_FULL;
3924 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3927 if (no_pflink_check) {
3928 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3929 mac->get_link_status = true;
3931 mac->get_link_status = false;
3935 /* if the read failed it could just be a mailbox collision, best wait
3936 * until we are called again and don't report an error
3938 if (mbx->ops.read(hw, &in_msg, 1, 0))
3941 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3942 /* msg is not CTS and is NACK we must have lost CTS status */
3943 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3948 /* the pf is talking, if we timed out in the past we reinit */
3949 if (!mbx->timeout) {
3954 /* if we passed all the tests above then the link is up and we no
3955 * longer need to check for link
3957 mac->get_link_status = false;
3960 *link_up = !mac->get_link_status;
3964 /* return 0 means link status changed, -1 means not changed */
3966 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3967 int wait_to_complete, int vf)
3969 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3970 struct rte_eth_link link, old;
3971 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3972 struct ixgbe_interrupt *intr =
3973 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3978 bool autoneg = false;
3980 link.link_status = ETH_LINK_DOWN;
3981 link.link_speed = 0;
3982 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3983 link.link_autoneg = ETH_LINK_AUTONEG;
3984 memset(&old, 0, sizeof(old));
3985 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3987 hw->mac.get_link_status = true;
3989 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3990 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3991 speed = hw->phy.autoneg_advertised;
3993 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3994 ixgbe_setup_link(hw, speed, true);
3997 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3998 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4002 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4004 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4007 link.link_speed = ETH_SPEED_NUM_100M;
4008 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4009 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4010 if (link.link_status == old.link_status)
4016 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4017 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4018 if (link.link_status == old.link_status)
4022 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4023 link.link_status = ETH_LINK_UP;
4024 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4026 switch (link_speed) {
4028 case IXGBE_LINK_SPEED_UNKNOWN:
4029 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4030 link.link_speed = ETH_SPEED_NUM_100M;
4033 case IXGBE_LINK_SPEED_100_FULL:
4034 link.link_speed = ETH_SPEED_NUM_100M;
4037 case IXGBE_LINK_SPEED_1GB_FULL:
4038 link.link_speed = ETH_SPEED_NUM_1G;
4041 case IXGBE_LINK_SPEED_2_5GB_FULL:
4042 link.link_speed = ETH_SPEED_NUM_2_5G;
4045 case IXGBE_LINK_SPEED_5GB_FULL:
4046 link.link_speed = ETH_SPEED_NUM_5G;
4049 case IXGBE_LINK_SPEED_10GB_FULL:
4050 link.link_speed = ETH_SPEED_NUM_10G;
4053 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
4055 if (link.link_status == old.link_status)
4062 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4064 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4068 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4070 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4074 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4079 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4080 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4081 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4085 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4087 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4090 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4091 fctrl &= (~IXGBE_FCTRL_UPE);
4092 if (dev->data->all_multicast == 1)
4093 fctrl |= IXGBE_FCTRL_MPE;
4095 fctrl &= (~IXGBE_FCTRL_MPE);
4096 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4100 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4102 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4105 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4106 fctrl |= IXGBE_FCTRL_MPE;
4107 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4111 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4113 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4116 if (dev->data->promiscuous == 1)
4117 return; /* must remain in all_multicast mode */
4119 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4120 fctrl &= (~IXGBE_FCTRL_MPE);
4121 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4125 * It clears the interrupt causes and enables the interrupt.
4126 * It will be called once only during nic initialized.
4129 * Pointer to struct rte_eth_dev.
4131 * Enable or Disable.
4134 * - On success, zero.
4135 * - On failure, a negative value.
4138 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4140 struct ixgbe_interrupt *intr =
4141 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4143 ixgbe_dev_link_status_print(dev);
4145 intr->mask |= IXGBE_EICR_LSC;
4147 intr->mask &= ~IXGBE_EICR_LSC;
4153 * It clears the interrupt causes and enables the interrupt.
4154 * It will be called once only during nic initialized.
4157 * Pointer to struct rte_eth_dev.
4160 * - On success, zero.
4161 * - On failure, a negative value.
4164 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4166 struct ixgbe_interrupt *intr =
4167 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4169 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4175 * It clears the interrupt causes and enables the interrupt.
4176 * It will be called once only during nic initialized.
4179 * Pointer to struct rte_eth_dev.
4182 * - On success, zero.
4183 * - On failure, a negative value.
4186 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4188 struct ixgbe_interrupt *intr =
4189 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4191 intr->mask |= IXGBE_EICR_LINKSEC;
4197 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4200 * Pointer to struct rte_eth_dev.
4203 * - On success, zero.
4204 * - On failure, a negative value.
4207 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4210 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4211 struct ixgbe_interrupt *intr =
4212 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4214 /* clear all cause mask */
4215 ixgbe_disable_intr(hw);
4217 /* read-on-clear nic registers here */
4218 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4219 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4223 /* set flag for async link update */
4224 if (eicr & IXGBE_EICR_LSC)
4225 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4227 if (eicr & IXGBE_EICR_MAILBOX)
4228 intr->flags |= IXGBE_FLAG_MAILBOX;
4230 if (eicr & IXGBE_EICR_LINKSEC)
4231 intr->flags |= IXGBE_FLAG_MACSEC;
4233 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4234 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4235 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4236 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4242 * It gets and then prints the link status.
4245 * Pointer to struct rte_eth_dev.
4248 * - On success, zero.
4249 * - On failure, a negative value.
4252 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4254 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4255 struct rte_eth_link link;
4257 memset(&link, 0, sizeof(link));
4258 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4259 if (link.link_status) {
4260 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4261 (int)(dev->data->port_id),
4262 (unsigned)link.link_speed,
4263 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4264 "full-duplex" : "half-duplex");
4266 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4267 (int)(dev->data->port_id));
4269 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4270 pci_dev->addr.domain,
4272 pci_dev->addr.devid,
4273 pci_dev->addr.function);
4277 * It executes link_update after knowing an interrupt occurred.
4280 * Pointer to struct rte_eth_dev.
4283 * - On success, zero.
4284 * - On failure, a negative value.
4287 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4288 struct rte_intr_handle *intr_handle)
4290 struct ixgbe_interrupt *intr =
4291 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4293 struct rte_eth_link link;
4294 struct ixgbe_hw *hw =
4295 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4297 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4299 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4300 ixgbe_pf_mbx_process(dev);
4301 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4304 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4305 ixgbe_handle_lasi(hw);
4306 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4309 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4310 /* get the link status before link update, for predicting later */
4311 memset(&link, 0, sizeof(link));
4312 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4314 ixgbe_dev_link_update(dev, 0);
4317 if (!link.link_status)
4318 /* handle it 1 sec later, wait it being stable */
4319 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4320 /* likely to down */
4322 /* handle it 4 sec later, wait it being stable */
4323 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4325 ixgbe_dev_link_status_print(dev);
4326 if (rte_eal_alarm_set(timeout * 1000,
4327 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4328 PMD_DRV_LOG(ERR, "Error setting alarm");
4330 /* remember original mask */
4331 intr->mask_original = intr->mask;
4332 /* only disable lsc interrupt */
4333 intr->mask &= ~IXGBE_EIMS_LSC;
4337 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4338 ixgbe_enable_intr(dev);
4339 rte_intr_enable(intr_handle);
4345 * Interrupt handler which shall be registered for alarm callback for delayed
4346 * handling specific interrupt to wait for the stable nic state. As the
4347 * NIC interrupt state is not stable for ixgbe after link is just down,
4348 * it needs to wait 4 seconds to get the stable status.
4351 * Pointer to interrupt handle.
4353 * The address of parameter (struct rte_eth_dev *) regsitered before.
4359 ixgbe_dev_interrupt_delayed_handler(void *param)
4361 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4362 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4363 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4364 struct ixgbe_interrupt *intr =
4365 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4366 struct ixgbe_hw *hw =
4367 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4370 ixgbe_disable_intr(hw);
4372 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4373 if (eicr & IXGBE_EICR_MAILBOX)
4374 ixgbe_pf_mbx_process(dev);
4376 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4377 ixgbe_handle_lasi(hw);
4378 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4381 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4382 ixgbe_dev_link_update(dev, 0);
4383 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4384 ixgbe_dev_link_status_print(dev);
4385 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4389 if (intr->flags & IXGBE_FLAG_MACSEC) {
4390 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4392 intr->flags &= ~IXGBE_FLAG_MACSEC;
4395 /* restore original mask */
4396 intr->mask = intr->mask_original;
4397 intr->mask_original = 0;
4399 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4400 ixgbe_enable_intr(dev);
4401 rte_intr_enable(intr_handle);
4405 * Interrupt handler triggered by NIC for handling
4406 * specific interrupt.
4409 * Pointer to interrupt handle.
4411 * The address of parameter (struct rte_eth_dev *) regsitered before.
4417 ixgbe_dev_interrupt_handler(void *param)
4419 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4421 ixgbe_dev_interrupt_get_status(dev);
4422 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4426 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4428 struct ixgbe_hw *hw;
4430 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4431 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4435 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4437 struct ixgbe_hw *hw;
4439 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4440 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4444 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4446 struct ixgbe_hw *hw;
4452 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4454 fc_conf->pause_time = hw->fc.pause_time;
4455 fc_conf->high_water = hw->fc.high_water[0];
4456 fc_conf->low_water = hw->fc.low_water[0];
4457 fc_conf->send_xon = hw->fc.send_xon;
4458 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4461 * Return rx_pause status according to actual setting of
4464 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4465 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4471 * Return tx_pause status according to actual setting of
4474 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4475 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4480 if (rx_pause && tx_pause)
4481 fc_conf->mode = RTE_FC_FULL;
4483 fc_conf->mode = RTE_FC_RX_PAUSE;
4485 fc_conf->mode = RTE_FC_TX_PAUSE;
4487 fc_conf->mode = RTE_FC_NONE;
4493 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4495 struct ixgbe_hw *hw;
4497 uint32_t rx_buf_size;
4498 uint32_t max_high_water;
4500 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4507 PMD_INIT_FUNC_TRACE();
4509 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4511 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4514 * At least reserve one Ethernet frame for watermark
4515 * high_water/low_water in kilo bytes for ixgbe
4517 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4518 if ((fc_conf->high_water > max_high_water) ||
4519 (fc_conf->high_water < fc_conf->low_water)) {
4520 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4521 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4525 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4526 hw->fc.pause_time = fc_conf->pause_time;
4527 hw->fc.high_water[0] = fc_conf->high_water;
4528 hw->fc.low_water[0] = fc_conf->low_water;
4529 hw->fc.send_xon = fc_conf->send_xon;
4530 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4532 err = ixgbe_fc_enable(hw);
4534 /* Not negotiated is not an error case */
4535 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4537 /* check if we want to forward MAC frames - driver doesn't have native
4538 * capability to do that, so we'll write the registers ourselves */
4540 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4542 /* set or clear MFLCN.PMCF bit depending on configuration */
4543 if (fc_conf->mac_ctrl_frame_fwd != 0)
4544 mflcn |= IXGBE_MFLCN_PMCF;
4546 mflcn &= ~IXGBE_MFLCN_PMCF;
4548 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4549 IXGBE_WRITE_FLUSH(hw);
4554 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4559 * ixgbe_pfc_enable_generic - Enable flow control
4560 * @hw: pointer to hardware structure
4561 * @tc_num: traffic class number
4562 * Enable flow control according to the current settings.
4565 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4568 uint32_t mflcn_reg, fccfg_reg;
4570 uint32_t fcrtl, fcrth;
4574 /* Validate the water mark configuration */
4575 if (!hw->fc.pause_time) {
4576 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4580 /* Low water mark of zero causes XOFF floods */
4581 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4582 /* High/Low water can not be 0 */
4583 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4584 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4585 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4589 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4590 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4591 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4595 /* Negotiate the fc mode to use */
4596 ixgbe_fc_autoneg(hw);
4598 /* Disable any previous flow control settings */
4599 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4600 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4602 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4603 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4605 switch (hw->fc.current_mode) {
4608 * If the count of enabled RX Priority Flow control >1,
4609 * and the TX pause can not be disabled
4612 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4613 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4614 if (reg & IXGBE_FCRTH_FCEN)
4618 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4620 case ixgbe_fc_rx_pause:
4622 * Rx Flow control is enabled and Tx Flow control is
4623 * disabled by software override. Since there really
4624 * isn't a way to advertise that we are capable of RX
4625 * Pause ONLY, we will advertise that we support both
4626 * symmetric and asymmetric Rx PAUSE. Later, we will
4627 * disable the adapter's ability to send PAUSE frames.
4629 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4631 * If the count of enabled RX Priority Flow control >1,
4632 * and the TX pause can not be disabled
4635 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4636 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4637 if (reg & IXGBE_FCRTH_FCEN)
4641 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4643 case ixgbe_fc_tx_pause:
4645 * Tx Flow control is enabled, and Rx Flow control is
4646 * disabled by software override.
4648 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4651 /* Flow control (both Rx and Tx) is enabled by SW override. */
4652 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4653 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4656 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4657 ret_val = IXGBE_ERR_CONFIG;
4661 /* Set 802.3x based flow control settings. */
4662 mflcn_reg |= IXGBE_MFLCN_DPF;
4663 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4664 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4666 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4667 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4668 hw->fc.high_water[tc_num]) {
4669 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4670 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4671 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4673 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4675 * In order to prevent Tx hangs when the internal Tx
4676 * switch is enabled we must set the high water mark
4677 * to the maximum FCRTH value. This allows the Tx
4678 * switch to function even under heavy Rx workloads.
4680 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4682 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4684 /* Configure pause time (2 TCs per register) */
4685 reg = hw->fc.pause_time * 0x00010001;
4686 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4687 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4689 /* Configure flow control refresh threshold value */
4690 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4697 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4699 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4702 if (hw->mac.type != ixgbe_mac_82598EB) {
4703 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4709 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4712 uint32_t rx_buf_size;
4713 uint32_t max_high_water;
4715 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4716 struct ixgbe_hw *hw =
4717 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4718 struct ixgbe_dcb_config *dcb_config =
4719 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4721 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4728 PMD_INIT_FUNC_TRACE();
4730 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4731 tc_num = map[pfc_conf->priority];
4732 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4733 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4735 * At least reserve one Ethernet frame for watermark
4736 * high_water/low_water in kilo bytes for ixgbe
4738 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4739 if ((pfc_conf->fc.high_water > max_high_water) ||
4740 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4741 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4742 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4746 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4747 hw->fc.pause_time = pfc_conf->fc.pause_time;
4748 hw->fc.send_xon = pfc_conf->fc.send_xon;
4749 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4750 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4752 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4754 /* Not negotiated is not an error case */
4755 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4758 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4763 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4764 struct rte_eth_rss_reta_entry64 *reta_conf,
4767 uint16_t i, sp_reta_size;
4770 uint16_t idx, shift;
4771 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4774 PMD_INIT_FUNC_TRACE();
4776 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4777 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4782 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4783 if (reta_size != sp_reta_size) {
4784 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4785 "(%d) doesn't match the number hardware can supported "
4786 "(%d)", reta_size, sp_reta_size);
4790 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4791 idx = i / RTE_RETA_GROUP_SIZE;
4792 shift = i % RTE_RETA_GROUP_SIZE;
4793 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4797 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4798 if (mask == IXGBE_4_BIT_MASK)
4801 r = IXGBE_READ_REG(hw, reta_reg);
4802 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4803 if (mask & (0x1 << j))
4804 reta |= reta_conf[idx].reta[shift + j] <<
4807 reta |= r & (IXGBE_8_BIT_MASK <<
4810 IXGBE_WRITE_REG(hw, reta_reg, reta);
4817 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4818 struct rte_eth_rss_reta_entry64 *reta_conf,
4821 uint16_t i, sp_reta_size;
4824 uint16_t idx, shift;
4825 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4828 PMD_INIT_FUNC_TRACE();
4829 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4830 if (reta_size != sp_reta_size) {
4831 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4832 "(%d) doesn't match the number hardware can supported "
4833 "(%d)", reta_size, sp_reta_size);
4837 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4838 idx = i / RTE_RETA_GROUP_SIZE;
4839 shift = i % RTE_RETA_GROUP_SIZE;
4840 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4845 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4846 reta = IXGBE_READ_REG(hw, reta_reg);
4847 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4848 if (mask & (0x1 << j))
4849 reta_conf[idx].reta[shift + j] =
4850 ((reta >> (CHAR_BIT * j)) &
4859 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4860 uint32_t index, uint32_t pool)
4862 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4863 uint32_t enable_addr = 1;
4865 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4870 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4872 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4874 ixgbe_clear_rar(hw, index);
4878 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4880 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4882 ixgbe_remove_rar(dev, 0);
4884 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4888 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4890 if (strcmp(dev->device->driver->name, drv->driver.name))
4897 is_ixgbe_supported(struct rte_eth_dev *dev)
4899 return is_device_supported(dev, &rte_ixgbe_pmd);
4903 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4907 struct ixgbe_hw *hw;
4908 struct rte_eth_dev_info dev_info;
4909 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4910 struct rte_eth_dev_data *dev_data = dev->data;
4912 ixgbe_dev_info_get(dev, &dev_info);
4914 /* check that mtu is within the allowed range */
4915 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4918 /* If device is started, refuse mtu that requires the support of
4919 * scattered packets when this feature has not been enabled before.
4921 if (dev_data->dev_started && !dev_data->scattered_rx &&
4922 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4923 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4924 PMD_INIT_LOG(ERR, "Stop port first.");
4928 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4929 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4931 /* switch to jumbo mode if needed */
4932 if (frame_size > ETHER_MAX_LEN) {
4933 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4934 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4936 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4937 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4939 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4941 /* update max frame size */
4942 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4944 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4945 maxfrs &= 0x0000FFFF;
4946 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4947 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4953 * Virtual Function operations
4956 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4958 PMD_INIT_FUNC_TRACE();
4960 /* Clear interrupt mask to stop from interrupts being generated */
4961 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4963 IXGBE_WRITE_FLUSH(hw);
4967 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4969 PMD_INIT_FUNC_TRACE();
4971 /* VF enable interrupt autoclean */
4972 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4973 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4974 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4976 IXGBE_WRITE_FLUSH(hw);
4980 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4982 struct rte_eth_conf *conf = &dev->data->dev_conf;
4983 struct ixgbe_adapter *adapter =
4984 (struct ixgbe_adapter *)dev->data->dev_private;
4986 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4987 dev->data->port_id);
4990 * VF has no ability to enable/disable HW CRC
4991 * Keep the persistent behavior the same as Host PF
4993 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4994 if (!conf->rxmode.hw_strip_crc) {
4995 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4996 conf->rxmode.hw_strip_crc = 1;
4999 if (conf->rxmode.hw_strip_crc) {
5000 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5001 conf->rxmode.hw_strip_crc = 0;
5006 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5007 * allocation or vector Rx preconditions we will reset it.
5009 adapter->rx_bulk_alloc_allowed = true;
5010 adapter->rx_vec_allowed = true;
5016 ixgbevf_dev_start(struct rte_eth_dev *dev)
5018 struct ixgbe_hw *hw =
5019 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5020 uint32_t intr_vector = 0;
5021 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5022 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5026 PMD_INIT_FUNC_TRACE();
5028 hw->mac.ops.reset_hw(hw);
5029 hw->mac.get_link_status = true;
5031 /* negotiate mailbox API version to use with the PF. */
5032 ixgbevf_negotiate_api(hw);
5034 ixgbevf_dev_tx_init(dev);
5036 /* This can fail when allocating mbufs for descriptor rings */
5037 err = ixgbevf_dev_rx_init(dev);
5039 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5040 ixgbe_dev_clear_queues(dev);
5045 ixgbevf_set_vfta_all(dev, 1);
5048 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5049 ETH_VLAN_EXTEND_MASK;
5050 err = ixgbevf_vlan_offload_set(dev, mask);
5052 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5053 ixgbe_dev_clear_queues(dev);
5057 ixgbevf_dev_rxtx_start(dev);
5059 /* check and configure queue intr-vector mapping */
5060 if (dev->data->dev_conf.intr_conf.rxq != 0) {
5061 /* According to datasheet, only vector 0/1/2 can be used,
5062 * now only one vector is used for Rx queue
5065 if (rte_intr_efd_enable(intr_handle, intr_vector))
5069 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5070 intr_handle->intr_vec =
5071 rte_zmalloc("intr_vec",
5072 dev->data->nb_rx_queues * sizeof(int), 0);
5073 if (intr_handle->intr_vec == NULL) {
5074 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5075 " intr_vec", dev->data->nb_rx_queues);
5079 ixgbevf_configure_msix(dev);
5081 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5082 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5083 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5084 * is not cleared, it will fail when following rte_intr_enable( ) tries
5085 * to map Rx queue interrupt to other VFIO vectors.
5086 * So clear uio/vfio intr/evevnfd first to avoid failure.
5088 rte_intr_disable(intr_handle);
5090 rte_intr_enable(intr_handle);
5092 /* Re-enable interrupt for VF */
5093 ixgbevf_intr_enable(hw);
5099 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5101 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5102 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5103 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5105 PMD_INIT_FUNC_TRACE();
5107 ixgbevf_intr_disable(hw);
5109 hw->adapter_stopped = 1;
5110 ixgbe_stop_adapter(hw);
5113 * Clear what we set, but we still keep shadow_vfta to
5114 * restore after device starts
5116 ixgbevf_set_vfta_all(dev, 0);
5118 /* Clear stored conf */
5119 dev->data->scattered_rx = 0;
5121 ixgbe_dev_clear_queues(dev);
5123 /* Clean datapath event and queue/vec mapping */
5124 rte_intr_efd_disable(intr_handle);
5125 if (intr_handle->intr_vec != NULL) {
5126 rte_free(intr_handle->intr_vec);
5127 intr_handle->intr_vec = NULL;
5132 ixgbevf_dev_close(struct rte_eth_dev *dev)
5134 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5136 PMD_INIT_FUNC_TRACE();
5140 ixgbevf_dev_stop(dev);
5142 ixgbe_dev_free_queues(dev);
5145 * Remove the VF MAC address ro ensure
5146 * that the VF traffic goes to the PF
5147 * after stop, close and detach of the VF
5149 ixgbevf_remove_mac_addr(dev, 0);
5156 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5160 ret = eth_ixgbevf_dev_uninit(dev);
5164 ret = eth_ixgbevf_dev_init(dev);
5169 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5171 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5172 struct ixgbe_vfta *shadow_vfta =
5173 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5174 int i = 0, j = 0, vfta = 0, mask = 1;
5176 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5177 vfta = shadow_vfta->vfta[i];
5180 for (j = 0; j < 32; j++) {
5182 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5192 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5194 struct ixgbe_hw *hw =
5195 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5196 struct ixgbe_vfta *shadow_vfta =
5197 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5198 uint32_t vid_idx = 0;
5199 uint32_t vid_bit = 0;
5202 PMD_INIT_FUNC_TRACE();
5204 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5205 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5207 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5210 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5211 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5213 /* Save what we set and retore it after device reset */
5215 shadow_vfta->vfta[vid_idx] |= vid_bit;
5217 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5223 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5225 struct ixgbe_hw *hw =
5226 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5229 PMD_INIT_FUNC_TRACE();
5231 if (queue >= hw->mac.max_rx_queues)
5234 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5236 ctrl |= IXGBE_RXDCTL_VME;
5238 ctrl &= ~IXGBE_RXDCTL_VME;
5239 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5241 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5245 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5247 struct ixgbe_hw *hw =
5248 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5252 /* VF function only support hw strip feature, others are not support */
5253 if (mask & ETH_VLAN_STRIP_MASK) {
5254 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5256 for (i = 0; i < hw->mac.max_rx_queues; i++)
5257 ixgbevf_vlan_strip_queue_set(dev, i, on);
5264 ixgbe_vt_check(struct ixgbe_hw *hw)
5268 /* if Virtualization Technology is enabled */
5269 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5270 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5271 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5279 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5281 uint32_t vector = 0;
5283 switch (hw->mac.mc_filter_type) {
5284 case 0: /* use bits [47:36] of the address */
5285 vector = ((uc_addr->addr_bytes[4] >> 4) |
5286 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5288 case 1: /* use bits [46:35] of the address */
5289 vector = ((uc_addr->addr_bytes[4] >> 3) |
5290 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5292 case 2: /* use bits [45:34] of the address */
5293 vector = ((uc_addr->addr_bytes[4] >> 2) |
5294 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5296 case 3: /* use bits [43:32] of the address */
5297 vector = ((uc_addr->addr_bytes[4]) |
5298 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5300 default: /* Invalid mc_filter_type */
5304 /* vector can only be 12-bits or boundary will be exceeded */
5310 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5318 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5319 const uint32_t ixgbe_uta_bit_shift = 5;
5320 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5321 const uint32_t bit1 = 0x1;
5323 struct ixgbe_hw *hw =
5324 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5325 struct ixgbe_uta_info *uta_info =
5326 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5328 /* The UTA table only exists on 82599 hardware and newer */
5329 if (hw->mac.type < ixgbe_mac_82599EB)
5332 vector = ixgbe_uta_vector(hw, mac_addr);
5333 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5334 uta_shift = vector & ixgbe_uta_bit_mask;
5336 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5340 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5342 uta_info->uta_in_use++;
5343 reg_val |= (bit1 << uta_shift);
5344 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5346 uta_info->uta_in_use--;
5347 reg_val &= ~(bit1 << uta_shift);
5348 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5351 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5353 if (uta_info->uta_in_use > 0)
5354 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5355 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5357 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5363 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5366 struct ixgbe_hw *hw =
5367 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5368 struct ixgbe_uta_info *uta_info =
5369 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5371 /* The UTA table only exists on 82599 hardware and newer */
5372 if (hw->mac.type < ixgbe_mac_82599EB)
5376 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5377 uta_info->uta_shadow[i] = ~0;
5378 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5381 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5382 uta_info->uta_shadow[i] = 0;
5383 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5391 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5393 uint32_t new_val = orig_val;
5395 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5396 new_val |= IXGBE_VMOLR_AUPE;
5397 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5398 new_val |= IXGBE_VMOLR_ROMPE;
5399 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5400 new_val |= IXGBE_VMOLR_ROPE;
5401 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5402 new_val |= IXGBE_VMOLR_BAM;
5403 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5404 new_val |= IXGBE_VMOLR_MPE;
5409 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5410 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5411 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5412 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5413 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5414 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5415 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5418 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5419 struct rte_eth_mirror_conf *mirror_conf,
5420 uint8_t rule_id, uint8_t on)
5422 uint32_t mr_ctl, vlvf;
5423 uint32_t mp_lsb = 0;
5424 uint32_t mv_msb = 0;
5425 uint32_t mv_lsb = 0;
5426 uint32_t mp_msb = 0;
5429 uint64_t vlan_mask = 0;
5431 const uint8_t pool_mask_offset = 32;
5432 const uint8_t vlan_mask_offset = 32;
5433 const uint8_t dst_pool_offset = 8;
5434 const uint8_t rule_mr_offset = 4;
5435 const uint8_t mirror_rule_mask = 0x0F;
5437 struct ixgbe_mirror_info *mr_info =
5438 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5439 struct ixgbe_hw *hw =
5440 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5441 uint8_t mirror_type = 0;
5443 if (ixgbe_vt_check(hw) < 0)
5446 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5449 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5450 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5451 mirror_conf->rule_type);
5455 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5456 mirror_type |= IXGBE_MRCTL_VLME;
5457 /* Check if vlan id is valid and find conresponding VLAN ID
5460 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5461 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5462 /* search vlan id related pool vlan filter
5465 reg_index = ixgbe_find_vlvf_slot(
5467 mirror_conf->vlan.vlan_id[i],
5471 vlvf = IXGBE_READ_REG(hw,
5472 IXGBE_VLVF(reg_index));
5473 if ((vlvf & IXGBE_VLVF_VIEN) &&
5474 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5475 mirror_conf->vlan.vlan_id[i]))
5476 vlan_mask |= (1ULL << reg_index);
5483 mv_lsb = vlan_mask & 0xFFFFFFFF;
5484 mv_msb = vlan_mask >> vlan_mask_offset;
5486 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5487 mirror_conf->vlan.vlan_mask;
5488 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5489 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5490 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5491 mirror_conf->vlan.vlan_id[i];
5496 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5497 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5498 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5503 * if enable pool mirror, write related pool mask register,if disable
5504 * pool mirror, clear PFMRVM register
5506 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5507 mirror_type |= IXGBE_MRCTL_VPME;
5509 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5510 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5511 mr_info->mr_conf[rule_id].pool_mask =
5512 mirror_conf->pool_mask;
5517 mr_info->mr_conf[rule_id].pool_mask = 0;
5520 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5521 mirror_type |= IXGBE_MRCTL_UPME;
5522 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5523 mirror_type |= IXGBE_MRCTL_DPME;
5525 /* read mirror control register and recalculate it */
5526 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5529 mr_ctl |= mirror_type;
5530 mr_ctl &= mirror_rule_mask;
5531 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5533 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5536 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5537 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5539 /* write mirrror control register */
5540 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5542 /* write pool mirrror control register */
5543 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5544 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5545 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5548 /* write VLAN mirrror control register */
5549 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5550 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5551 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5559 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5562 uint32_t lsb_val = 0;
5563 uint32_t msb_val = 0;
5564 const uint8_t rule_mr_offset = 4;
5566 struct ixgbe_hw *hw =
5567 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5568 struct ixgbe_mirror_info *mr_info =
5569 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5571 if (ixgbe_vt_check(hw) < 0)
5574 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5577 memset(&mr_info->mr_conf[rule_id], 0,
5578 sizeof(struct rte_eth_mirror_conf));
5580 /* clear PFVMCTL register */
5581 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5583 /* clear pool mask register */
5584 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5585 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5587 /* clear vlan mask register */
5588 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5589 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5595 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5597 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5598 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5600 struct ixgbe_hw *hw =
5601 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5602 uint32_t vec = IXGBE_MISC_VEC_ID;
5604 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5605 if (rte_intr_allow_others(intr_handle))
5606 vec = IXGBE_RX_VEC_START;
5608 RTE_SET_USED(queue_id);
5609 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5611 rte_intr_enable(intr_handle);
5617 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5620 struct ixgbe_hw *hw =
5621 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5622 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5623 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5624 uint32_t vec = IXGBE_MISC_VEC_ID;
5626 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5627 if (rte_intr_allow_others(intr_handle))
5628 vec = IXGBE_RX_VEC_START;
5629 mask &= ~(1 << vec);
5630 RTE_SET_USED(queue_id);
5631 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5637 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5639 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5640 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5642 struct ixgbe_hw *hw =
5643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5644 struct ixgbe_interrupt *intr =
5645 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5647 if (queue_id < 16) {
5648 ixgbe_disable_intr(hw);
5649 intr->mask |= (1 << queue_id);
5650 ixgbe_enable_intr(dev);
5651 } else if (queue_id < 32) {
5652 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5653 mask &= (1 << queue_id);
5654 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5655 } else if (queue_id < 64) {
5656 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5657 mask &= (1 << (queue_id - 32));
5658 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5660 rte_intr_enable(intr_handle);
5666 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5669 struct ixgbe_hw *hw =
5670 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5671 struct ixgbe_interrupt *intr =
5672 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5674 if (queue_id < 16) {
5675 ixgbe_disable_intr(hw);
5676 intr->mask &= ~(1 << queue_id);
5677 ixgbe_enable_intr(dev);
5678 } else if (queue_id < 32) {
5679 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5680 mask &= ~(1 << queue_id);
5681 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5682 } else if (queue_id < 64) {
5683 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5684 mask &= ~(1 << (queue_id - 32));
5685 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5692 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5693 uint8_t queue, uint8_t msix_vector)
5697 if (direction == -1) {
5699 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5700 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5703 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5705 /* rx or tx cause */
5706 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5707 idx = ((16 * (queue & 1)) + (8 * direction));
5708 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5709 tmp &= ~(0xFF << idx);
5710 tmp |= (msix_vector << idx);
5711 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5716 * set the IVAR registers, mapping interrupt causes to vectors
5718 * pointer to ixgbe_hw struct
5720 * 0 for Rx, 1 for Tx, -1 for other causes
5722 * queue to map the corresponding interrupt to
5724 * the vector to map to the corresponding queue
5727 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5728 uint8_t queue, uint8_t msix_vector)
5732 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5733 if (hw->mac.type == ixgbe_mac_82598EB) {
5734 if (direction == -1)
5736 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5737 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5738 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5739 tmp |= (msix_vector << (8 * (queue & 0x3)));
5740 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5741 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5742 (hw->mac.type == ixgbe_mac_X540) ||
5743 (hw->mac.type == ixgbe_mac_X550)) {
5744 if (direction == -1) {
5746 idx = ((queue & 1) * 8);
5747 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5748 tmp &= ~(0xFF << idx);
5749 tmp |= (msix_vector << idx);
5750 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5752 /* rx or tx causes */
5753 idx = ((16 * (queue & 1)) + (8 * direction));
5754 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5755 tmp &= ~(0xFF << idx);
5756 tmp |= (msix_vector << idx);
5757 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5763 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5765 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5766 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5767 struct ixgbe_hw *hw =
5768 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5770 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5771 uint32_t base = IXGBE_MISC_VEC_ID;
5773 /* Configure VF other cause ivar */
5774 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5776 /* won't configure msix register if no mapping is done
5777 * between intr vector and event fd.
5779 if (!rte_intr_dp_is_en(intr_handle))
5782 if (rte_intr_allow_others(intr_handle)) {
5783 base = IXGBE_RX_VEC_START;
5784 vector_idx = IXGBE_RX_VEC_START;
5787 /* Configure all RX queues of VF */
5788 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5789 /* Force all queue use vector 0,
5790 * as IXGBE_VF_MAXMSIVECOTR = 1
5792 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5793 intr_handle->intr_vec[q_idx] = vector_idx;
5794 if (vector_idx < base + intr_handle->nb_efd - 1)
5800 * Sets up the hardware to properly generate MSI-X interrupts
5802 * board private structure
5805 ixgbe_configure_msix(struct rte_eth_dev *dev)
5807 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5808 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5809 struct ixgbe_hw *hw =
5810 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5811 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5812 uint32_t vec = IXGBE_MISC_VEC_ID;
5816 /* won't configure msix register if no mapping is done
5817 * between intr vector and event fd
5819 if (!rte_intr_dp_is_en(intr_handle))
5822 if (rte_intr_allow_others(intr_handle))
5823 vec = base = IXGBE_RX_VEC_START;
5825 /* setup GPIE for MSI-x mode */
5826 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5827 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5828 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5829 /* auto clearing and auto setting corresponding bits in EIMS
5830 * when MSI-X interrupt is triggered
5832 if (hw->mac.type == ixgbe_mac_82598EB) {
5833 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5835 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5836 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5838 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5840 /* Populate the IVAR table and set the ITR values to the
5841 * corresponding register.
5843 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5845 /* by default, 1:1 mapping */
5846 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5847 intr_handle->intr_vec[queue_id] = vec;
5848 if (vec < base + intr_handle->nb_efd - 1)
5852 switch (hw->mac.type) {
5853 case ixgbe_mac_82598EB:
5854 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5857 case ixgbe_mac_82599EB:
5858 case ixgbe_mac_X540:
5859 case ixgbe_mac_X550:
5860 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5865 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5866 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5868 /* set up to autoclear timer, and the vectors */
5869 mask = IXGBE_EIMS_ENABLE_MASK;
5870 mask &= ~(IXGBE_EIMS_OTHER |
5871 IXGBE_EIMS_MAILBOX |
5874 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5878 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5879 uint16_t queue_idx, uint16_t tx_rate)
5881 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5882 uint32_t rf_dec, rf_int;
5884 uint16_t link_speed = dev->data->dev_link.link_speed;
5886 if (queue_idx >= hw->mac.max_tx_queues)
5890 /* Calculate the rate factor values to set */
5891 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5892 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5893 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5895 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5896 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5897 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5898 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5904 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5905 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5908 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5909 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5910 IXGBE_MAX_JUMBO_FRAME_SIZE))
5911 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5912 IXGBE_MMW_SIZE_JUMBO_FRAME);
5914 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5915 IXGBE_MMW_SIZE_DEFAULT);
5917 /* Set RTTBCNRC of queue X */
5918 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5919 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5920 IXGBE_WRITE_FLUSH(hw);
5926 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5927 __attribute__((unused)) uint32_t index,
5928 __attribute__((unused)) uint32_t pool)
5930 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5934 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5935 * operation. Trap this case to avoid exhausting the [very limited]
5936 * set of PF resources used to store VF MAC addresses.
5938 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5940 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5942 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5943 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5944 mac_addr->addr_bytes[0],
5945 mac_addr->addr_bytes[1],
5946 mac_addr->addr_bytes[2],
5947 mac_addr->addr_bytes[3],
5948 mac_addr->addr_bytes[4],
5949 mac_addr->addr_bytes[5],
5955 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5957 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5958 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5959 struct ether_addr *mac_addr;
5964 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5965 * not support the deletion of a given MAC address.
5966 * Instead, it imposes to delete all MAC addresses, then to add again
5967 * all MAC addresses with the exception of the one to be deleted.
5969 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5972 * Add again all MAC addresses, with the exception of the deleted one
5973 * and of the permanent MAC address.
5975 for (i = 0, mac_addr = dev->data->mac_addrs;
5976 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5977 /* Skip the deleted MAC address */
5980 /* Skip NULL MAC addresses */
5981 if (is_zero_ether_addr(mac_addr))
5983 /* Skip the permanent MAC address */
5984 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5986 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5989 "Adding again MAC address "
5990 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5992 mac_addr->addr_bytes[0],
5993 mac_addr->addr_bytes[1],
5994 mac_addr->addr_bytes[2],
5995 mac_addr->addr_bytes[3],
5996 mac_addr->addr_bytes[4],
5997 mac_addr->addr_bytes[5],
6003 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
6005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6011 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6012 struct rte_eth_syn_filter *filter,
6015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6016 struct ixgbe_filter_info *filter_info =
6017 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6021 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6024 syn_info = filter_info->syn_info;
6027 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6029 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6030 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6032 if (filter->hig_pri)
6033 synqf |= IXGBE_SYN_FILTER_SYNQFP;
6035 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6037 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6038 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6040 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6043 filter_info->syn_info = synqf;
6044 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6045 IXGBE_WRITE_FLUSH(hw);
6050 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6051 struct rte_eth_syn_filter *filter)
6053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6054 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6056 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6057 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6058 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6065 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6066 enum rte_filter_op filter_op,
6069 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6072 MAC_TYPE_FILTER_SUP(hw->mac.type);
6074 if (filter_op == RTE_ETH_FILTER_NOP)
6078 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6083 switch (filter_op) {
6084 case RTE_ETH_FILTER_ADD:
6085 ret = ixgbe_syn_filter_set(dev,
6086 (struct rte_eth_syn_filter *)arg,
6089 case RTE_ETH_FILTER_DELETE:
6090 ret = ixgbe_syn_filter_set(dev,
6091 (struct rte_eth_syn_filter *)arg,
6094 case RTE_ETH_FILTER_GET:
6095 ret = ixgbe_syn_filter_get(dev,
6096 (struct rte_eth_syn_filter *)arg);
6099 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6108 static inline enum ixgbe_5tuple_protocol
6109 convert_protocol_type(uint8_t protocol_value)
6111 if (protocol_value == IPPROTO_TCP)
6112 return IXGBE_FILTER_PROTOCOL_TCP;
6113 else if (protocol_value == IPPROTO_UDP)
6114 return IXGBE_FILTER_PROTOCOL_UDP;
6115 else if (protocol_value == IPPROTO_SCTP)
6116 return IXGBE_FILTER_PROTOCOL_SCTP;
6118 return IXGBE_FILTER_PROTOCOL_NONE;
6121 /* inject a 5-tuple filter to HW */
6123 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6124 struct ixgbe_5tuple_filter *filter)
6126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6128 uint32_t ftqf, sdpqf;
6129 uint32_t l34timir = 0;
6130 uint8_t mask = 0xff;
6134 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6135 IXGBE_SDPQF_DSTPORT_SHIFT);
6136 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6138 ftqf = (uint32_t)(filter->filter_info.proto &
6139 IXGBE_FTQF_PROTOCOL_MASK);
6140 ftqf |= (uint32_t)((filter->filter_info.priority &
6141 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6142 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6143 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6144 if (filter->filter_info.dst_ip_mask == 0)
6145 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6146 if (filter->filter_info.src_port_mask == 0)
6147 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6148 if (filter->filter_info.dst_port_mask == 0)
6149 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6150 if (filter->filter_info.proto_mask == 0)
6151 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6152 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6153 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6154 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6156 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6157 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6158 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6159 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6161 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6162 l34timir |= (uint32_t)(filter->queue <<
6163 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6164 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6168 * add a 5tuple filter
6171 * dev: Pointer to struct rte_eth_dev.
6172 * index: the index the filter allocates.
6173 * filter: ponter to the filter that will be added.
6174 * rx_queue: the queue id the filter assigned to.
6177 * - On success, zero.
6178 * - On failure, a negative value.
6181 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6182 struct ixgbe_5tuple_filter *filter)
6184 struct ixgbe_filter_info *filter_info =
6185 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6189 * look for an unused 5tuple filter index,
6190 * and insert the filter to list.
6192 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6193 idx = i / (sizeof(uint32_t) * NBBY);
6194 shift = i % (sizeof(uint32_t) * NBBY);
6195 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6196 filter_info->fivetuple_mask[idx] |= 1 << shift;
6198 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6204 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6205 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6209 ixgbe_inject_5tuple_filter(dev, filter);
6215 * remove a 5tuple filter
6218 * dev: Pointer to struct rte_eth_dev.
6219 * filter: the pointer of the filter will be removed.
6222 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6223 struct ixgbe_5tuple_filter *filter)
6225 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6226 struct ixgbe_filter_info *filter_info =
6227 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6228 uint16_t index = filter->index;
6230 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6231 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6232 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6235 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6236 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6237 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6238 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6239 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6243 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6245 struct ixgbe_hw *hw;
6246 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6247 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6249 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6251 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6254 /* refuse mtu that requires the support of scattered packets when this
6255 * feature has not been enabled before.
6257 if (!rx_conf->enable_scatter &&
6258 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6259 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6263 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6264 * request of the version 2.0 of the mailbox API.
6265 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6266 * of the mailbox API.
6267 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6268 * prior to 3.11.33 which contains the following change:
6269 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6271 ixgbevf_rlpml_set_vf(hw, max_frame);
6273 /* update max frame size */
6274 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6278 static inline struct ixgbe_5tuple_filter *
6279 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6280 struct ixgbe_5tuple_filter_info *key)
6282 struct ixgbe_5tuple_filter *it;
6284 TAILQ_FOREACH(it, filter_list, entries) {
6285 if (memcmp(key, &it->filter_info,
6286 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6293 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6295 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6296 struct ixgbe_5tuple_filter_info *filter_info)
6298 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6299 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6300 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6303 switch (filter->dst_ip_mask) {
6305 filter_info->dst_ip_mask = 0;
6306 filter_info->dst_ip = filter->dst_ip;
6309 filter_info->dst_ip_mask = 1;
6312 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6316 switch (filter->src_ip_mask) {
6318 filter_info->src_ip_mask = 0;
6319 filter_info->src_ip = filter->src_ip;
6322 filter_info->src_ip_mask = 1;
6325 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6329 switch (filter->dst_port_mask) {
6331 filter_info->dst_port_mask = 0;
6332 filter_info->dst_port = filter->dst_port;
6335 filter_info->dst_port_mask = 1;
6338 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6342 switch (filter->src_port_mask) {
6344 filter_info->src_port_mask = 0;
6345 filter_info->src_port = filter->src_port;
6348 filter_info->src_port_mask = 1;
6351 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6355 switch (filter->proto_mask) {
6357 filter_info->proto_mask = 0;
6358 filter_info->proto =
6359 convert_protocol_type(filter->proto);
6362 filter_info->proto_mask = 1;
6365 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6369 filter_info->priority = (uint8_t)filter->priority;
6374 * add or delete a ntuple filter
6377 * dev: Pointer to struct rte_eth_dev.
6378 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6379 * add: if true, add filter, if false, remove filter
6382 * - On success, zero.
6383 * - On failure, a negative value.
6386 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6387 struct rte_eth_ntuple_filter *ntuple_filter,
6390 struct ixgbe_filter_info *filter_info =
6391 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6392 struct ixgbe_5tuple_filter_info filter_5tuple;
6393 struct ixgbe_5tuple_filter *filter;
6396 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6397 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6401 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6402 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6406 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6408 if (filter != NULL && add) {
6409 PMD_DRV_LOG(ERR, "filter exists.");
6412 if (filter == NULL && !add) {
6413 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6418 filter = rte_zmalloc("ixgbe_5tuple_filter",
6419 sizeof(struct ixgbe_5tuple_filter), 0);
6422 rte_memcpy(&filter->filter_info,
6424 sizeof(struct ixgbe_5tuple_filter_info));
6425 filter->queue = ntuple_filter->queue;
6426 ret = ixgbe_add_5tuple_filter(dev, filter);
6432 ixgbe_remove_5tuple_filter(dev, filter);
6438 * get a ntuple filter
6441 * dev: Pointer to struct rte_eth_dev.
6442 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6445 * - On success, zero.
6446 * - On failure, a negative value.
6449 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6450 struct rte_eth_ntuple_filter *ntuple_filter)
6452 struct ixgbe_filter_info *filter_info =
6453 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6454 struct ixgbe_5tuple_filter_info filter_5tuple;
6455 struct ixgbe_5tuple_filter *filter;
6458 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6459 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6463 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6464 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6468 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6470 if (filter == NULL) {
6471 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6474 ntuple_filter->queue = filter->queue;
6479 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6480 * @dev: pointer to rte_eth_dev structure
6481 * @filter_op:operation will be taken.
6482 * @arg: a pointer to specific structure corresponding to the filter_op
6485 * - On success, zero.
6486 * - On failure, a negative value.
6489 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6490 enum rte_filter_op filter_op,
6493 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6496 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6498 if (filter_op == RTE_ETH_FILTER_NOP)
6502 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6507 switch (filter_op) {
6508 case RTE_ETH_FILTER_ADD:
6509 ret = ixgbe_add_del_ntuple_filter(dev,
6510 (struct rte_eth_ntuple_filter *)arg,
6513 case RTE_ETH_FILTER_DELETE:
6514 ret = ixgbe_add_del_ntuple_filter(dev,
6515 (struct rte_eth_ntuple_filter *)arg,
6518 case RTE_ETH_FILTER_GET:
6519 ret = ixgbe_get_ntuple_filter(dev,
6520 (struct rte_eth_ntuple_filter *)arg);
6523 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6531 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6532 struct rte_eth_ethertype_filter *filter,
6535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536 struct ixgbe_filter_info *filter_info =
6537 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6541 struct ixgbe_ethertype_filter ethertype_filter;
6543 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6546 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6547 filter->ether_type == ETHER_TYPE_IPv6) {
6548 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6549 " ethertype filter.", filter->ether_type);
6553 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6554 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6557 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6558 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6562 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6563 if (ret >= 0 && add) {
6564 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6565 filter->ether_type);
6568 if (ret < 0 && !add) {
6569 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6570 filter->ether_type);
6575 etqf = IXGBE_ETQF_FILTER_EN;
6576 etqf |= (uint32_t)filter->ether_type;
6577 etqs |= (uint32_t)((filter->queue <<
6578 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6579 IXGBE_ETQS_RX_QUEUE);
6580 etqs |= IXGBE_ETQS_QUEUE_EN;
6582 ethertype_filter.ethertype = filter->ether_type;
6583 ethertype_filter.etqf = etqf;
6584 ethertype_filter.etqs = etqs;
6585 ethertype_filter.conf = FALSE;
6586 ret = ixgbe_ethertype_filter_insert(filter_info,
6589 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6593 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6597 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6598 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6599 IXGBE_WRITE_FLUSH(hw);
6605 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6606 struct rte_eth_ethertype_filter *filter)
6608 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6609 struct ixgbe_filter_info *filter_info =
6610 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6611 uint32_t etqf, etqs;
6614 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6616 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6617 filter->ether_type);
6621 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6622 if (etqf & IXGBE_ETQF_FILTER_EN) {
6623 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6624 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6626 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6627 IXGBE_ETQS_RX_QUEUE_SHIFT;
6634 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6635 * @dev: pointer to rte_eth_dev structure
6636 * @filter_op:operation will be taken.
6637 * @arg: a pointer to specific structure corresponding to the filter_op
6640 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6641 enum rte_filter_op filter_op,
6644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6647 MAC_TYPE_FILTER_SUP(hw->mac.type);
6649 if (filter_op == RTE_ETH_FILTER_NOP)
6653 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6658 switch (filter_op) {
6659 case RTE_ETH_FILTER_ADD:
6660 ret = ixgbe_add_del_ethertype_filter(dev,
6661 (struct rte_eth_ethertype_filter *)arg,
6664 case RTE_ETH_FILTER_DELETE:
6665 ret = ixgbe_add_del_ethertype_filter(dev,
6666 (struct rte_eth_ethertype_filter *)arg,
6669 case RTE_ETH_FILTER_GET:
6670 ret = ixgbe_get_ethertype_filter(dev,
6671 (struct rte_eth_ethertype_filter *)arg);
6674 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6682 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6683 enum rte_filter_type filter_type,
6684 enum rte_filter_op filter_op,
6689 switch (filter_type) {
6690 case RTE_ETH_FILTER_NTUPLE:
6691 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6693 case RTE_ETH_FILTER_ETHERTYPE:
6694 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6696 case RTE_ETH_FILTER_SYN:
6697 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6699 case RTE_ETH_FILTER_FDIR:
6700 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6702 case RTE_ETH_FILTER_L2_TUNNEL:
6703 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6705 case RTE_ETH_FILTER_GENERIC:
6706 if (filter_op != RTE_ETH_FILTER_GET)
6708 *(const void **)arg = &ixgbe_flow_ops;
6711 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6721 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6722 u8 **mc_addr_ptr, u32 *vmdq)
6727 mc_addr = *mc_addr_ptr;
6728 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6733 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6734 struct ether_addr *mc_addr_set,
6735 uint32_t nb_mc_addr)
6737 struct ixgbe_hw *hw;
6740 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6741 mc_addr_list = (u8 *)mc_addr_set;
6742 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6743 ixgbe_dev_addr_list_itr, TRUE);
6747 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6749 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6750 uint64_t systime_cycles;
6752 switch (hw->mac.type) {
6753 case ixgbe_mac_X550:
6754 case ixgbe_mac_X550EM_x:
6755 case ixgbe_mac_X550EM_a:
6756 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6757 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6758 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6762 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6763 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6767 return systime_cycles;
6771 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6773 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6774 uint64_t rx_tstamp_cycles;
6776 switch (hw->mac.type) {
6777 case ixgbe_mac_X550:
6778 case ixgbe_mac_X550EM_x:
6779 case ixgbe_mac_X550EM_a:
6780 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6781 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6782 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6786 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6787 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6788 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6792 return rx_tstamp_cycles;
6796 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6799 uint64_t tx_tstamp_cycles;
6801 switch (hw->mac.type) {
6802 case ixgbe_mac_X550:
6803 case ixgbe_mac_X550EM_x:
6804 case ixgbe_mac_X550EM_a:
6805 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6806 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6807 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6811 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6812 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6813 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6817 return tx_tstamp_cycles;
6821 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6824 struct ixgbe_adapter *adapter =
6825 (struct ixgbe_adapter *)dev->data->dev_private;
6826 struct rte_eth_link link;
6827 uint32_t incval = 0;
6830 /* Get current link speed. */
6831 memset(&link, 0, sizeof(link));
6832 ixgbe_dev_link_update(dev, 1);
6833 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6835 switch (link.link_speed) {
6836 case ETH_SPEED_NUM_100M:
6837 incval = IXGBE_INCVAL_100;
6838 shift = IXGBE_INCVAL_SHIFT_100;
6840 case ETH_SPEED_NUM_1G:
6841 incval = IXGBE_INCVAL_1GB;
6842 shift = IXGBE_INCVAL_SHIFT_1GB;
6844 case ETH_SPEED_NUM_10G:
6846 incval = IXGBE_INCVAL_10GB;
6847 shift = IXGBE_INCVAL_SHIFT_10GB;
6851 switch (hw->mac.type) {
6852 case ixgbe_mac_X550:
6853 case ixgbe_mac_X550EM_x:
6854 case ixgbe_mac_X550EM_a:
6855 /* Independent of link speed. */
6857 /* Cycles read will be interpreted as ns. */
6860 case ixgbe_mac_X540:
6861 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6863 case ixgbe_mac_82599EB:
6864 incval >>= IXGBE_INCVAL_SHIFT_82599;
6865 shift -= IXGBE_INCVAL_SHIFT_82599;
6866 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6867 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6870 /* Not supported. */
6874 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6875 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6876 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6878 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6879 adapter->systime_tc.cc_shift = shift;
6880 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6882 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6883 adapter->rx_tstamp_tc.cc_shift = shift;
6884 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6886 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6887 adapter->tx_tstamp_tc.cc_shift = shift;
6888 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6892 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6894 struct ixgbe_adapter *adapter =
6895 (struct ixgbe_adapter *)dev->data->dev_private;
6897 adapter->systime_tc.nsec += delta;
6898 adapter->rx_tstamp_tc.nsec += delta;
6899 adapter->tx_tstamp_tc.nsec += delta;
6905 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6908 struct ixgbe_adapter *adapter =
6909 (struct ixgbe_adapter *)dev->data->dev_private;
6911 ns = rte_timespec_to_ns(ts);
6912 /* Set the timecounters to a new value. */
6913 adapter->systime_tc.nsec = ns;
6914 adapter->rx_tstamp_tc.nsec = ns;
6915 adapter->tx_tstamp_tc.nsec = ns;
6921 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6923 uint64_t ns, systime_cycles;
6924 struct ixgbe_adapter *adapter =
6925 (struct ixgbe_adapter *)dev->data->dev_private;
6927 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6928 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6929 *ts = rte_ns_to_timespec(ns);
6935 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6937 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6941 /* Stop the timesync system time. */
6942 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6943 /* Reset the timesync system time value. */
6944 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6945 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6947 /* Enable system time for platforms where it isn't on by default. */
6948 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6949 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6950 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6952 ixgbe_start_timecounters(dev);
6954 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6955 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6957 IXGBE_ETQF_FILTER_EN |
6960 /* Enable timestamping of received PTP packets. */
6961 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6962 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6963 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6965 /* Enable timestamping of transmitted PTP packets. */
6966 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6967 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6968 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6970 IXGBE_WRITE_FLUSH(hw);
6976 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6978 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6981 /* Disable timestamping of transmitted PTP packets. */
6982 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6983 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6984 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6986 /* Disable timestamping of received PTP packets. */
6987 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6988 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6989 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6991 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6992 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6994 /* Stop incrementating the System Time registers. */
6995 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7001 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7002 struct timespec *timestamp,
7003 uint32_t flags __rte_unused)
7005 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7006 struct ixgbe_adapter *adapter =
7007 (struct ixgbe_adapter *)dev->data->dev_private;
7008 uint32_t tsync_rxctl;
7009 uint64_t rx_tstamp_cycles;
7012 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7013 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7016 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7017 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7018 *timestamp = rte_ns_to_timespec(ns);
7024 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7025 struct timespec *timestamp)
7027 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7028 struct ixgbe_adapter *adapter =
7029 (struct ixgbe_adapter *)dev->data->dev_private;
7030 uint32_t tsync_txctl;
7031 uint64_t tx_tstamp_cycles;
7034 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7035 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7038 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7039 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7040 *timestamp = rte_ns_to_timespec(ns);
7046 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7048 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7051 const struct reg_info *reg_group;
7052 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7053 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7055 while ((reg_group = reg_set[g_ind++]))
7056 count += ixgbe_regs_group_count(reg_group);
7062 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7066 const struct reg_info *reg_group;
7068 while ((reg_group = ixgbevf_regs[g_ind++]))
7069 count += ixgbe_regs_group_count(reg_group);
7075 ixgbe_get_regs(struct rte_eth_dev *dev,
7076 struct rte_dev_reg_info *regs)
7078 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079 uint32_t *data = regs->data;
7082 const struct reg_info *reg_group;
7083 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7084 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7087 regs->length = ixgbe_get_reg_length(dev);
7088 regs->width = sizeof(uint32_t);
7092 /* Support only full register dump */
7093 if ((regs->length == 0) ||
7094 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7095 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7097 while ((reg_group = reg_set[g_ind++]))
7098 count += ixgbe_read_regs_group(dev, &data[count],
7107 ixgbevf_get_regs(struct rte_eth_dev *dev,
7108 struct rte_dev_reg_info *regs)
7110 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7111 uint32_t *data = regs->data;
7114 const struct reg_info *reg_group;
7117 regs->length = ixgbevf_get_reg_length(dev);
7118 regs->width = sizeof(uint32_t);
7122 /* Support only full register dump */
7123 if ((regs->length == 0) ||
7124 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7125 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7127 while ((reg_group = ixgbevf_regs[g_ind++]))
7128 count += ixgbe_read_regs_group(dev, &data[count],
7137 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7139 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7141 /* Return unit is byte count */
7142 return hw->eeprom.word_size * 2;
7146 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7147 struct rte_dev_eeprom_info *in_eeprom)
7149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7150 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7151 uint16_t *data = in_eeprom->data;
7154 first = in_eeprom->offset >> 1;
7155 length = in_eeprom->length >> 1;
7156 if ((first > hw->eeprom.word_size) ||
7157 ((first + length) > hw->eeprom.word_size))
7160 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7162 return eeprom->ops.read_buffer(hw, first, length, data);
7166 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7167 struct rte_dev_eeprom_info *in_eeprom)
7169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7170 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7171 uint16_t *data = in_eeprom->data;
7174 first = in_eeprom->offset >> 1;
7175 length = in_eeprom->length >> 1;
7176 if ((first > hw->eeprom.word_size) ||
7177 ((first + length) > hw->eeprom.word_size))
7180 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7182 return eeprom->ops.write_buffer(hw, first, length, data);
7186 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7188 case ixgbe_mac_X550:
7189 case ixgbe_mac_X550EM_x:
7190 case ixgbe_mac_X550EM_a:
7191 return ETH_RSS_RETA_SIZE_512;
7192 case ixgbe_mac_X550_vf:
7193 case ixgbe_mac_X550EM_x_vf:
7194 case ixgbe_mac_X550EM_a_vf:
7195 return ETH_RSS_RETA_SIZE_64;
7197 return ETH_RSS_RETA_SIZE_128;
7202 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7204 case ixgbe_mac_X550:
7205 case ixgbe_mac_X550EM_x:
7206 case ixgbe_mac_X550EM_a:
7207 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7208 return IXGBE_RETA(reta_idx >> 2);
7210 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7211 case ixgbe_mac_X550_vf:
7212 case ixgbe_mac_X550EM_x_vf:
7213 case ixgbe_mac_X550EM_a_vf:
7214 return IXGBE_VFRETA(reta_idx >> 2);
7216 return IXGBE_RETA(reta_idx >> 2);
7221 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7223 case ixgbe_mac_X550_vf:
7224 case ixgbe_mac_X550EM_x_vf:
7225 case ixgbe_mac_X550EM_a_vf:
7226 return IXGBE_VFMRQC;
7233 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7235 case ixgbe_mac_X550_vf:
7236 case ixgbe_mac_X550EM_x_vf:
7237 case ixgbe_mac_X550EM_a_vf:
7238 return IXGBE_VFRSSRK(i);
7240 return IXGBE_RSSRK(i);
7245 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7247 case ixgbe_mac_82599_vf:
7248 case ixgbe_mac_X540_vf:
7256 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7257 struct rte_eth_dcb_info *dcb_info)
7259 struct ixgbe_dcb_config *dcb_config =
7260 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7261 struct ixgbe_dcb_tc_config *tc;
7262 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7266 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7267 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7269 dcb_info->nb_tcs = 1;
7271 tc_queue = &dcb_info->tc_queue;
7272 nb_tcs = dcb_info->nb_tcs;
7274 if (dcb_config->vt_mode) { /* vt is enabled*/
7275 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7276 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7277 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7278 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7279 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7280 for (j = 0; j < nb_tcs; j++) {
7281 tc_queue->tc_rxq[0][j].base = j;
7282 tc_queue->tc_rxq[0][j].nb_queue = 1;
7283 tc_queue->tc_txq[0][j].base = j;
7284 tc_queue->tc_txq[0][j].nb_queue = 1;
7287 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7288 for (j = 0; j < nb_tcs; j++) {
7289 tc_queue->tc_rxq[i][j].base =
7291 tc_queue->tc_rxq[i][j].nb_queue = 1;
7292 tc_queue->tc_txq[i][j].base =
7294 tc_queue->tc_txq[i][j].nb_queue = 1;
7298 } else { /* vt is disabled*/
7299 struct rte_eth_dcb_rx_conf *rx_conf =
7300 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7301 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7302 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7303 if (dcb_info->nb_tcs == ETH_4_TCS) {
7304 for (i = 0; i < dcb_info->nb_tcs; i++) {
7305 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7306 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7308 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7309 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7310 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7311 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7312 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7313 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7314 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7315 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7316 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7317 for (i = 0; i < dcb_info->nb_tcs; i++) {
7318 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7319 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7321 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7322 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7323 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7324 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7325 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7326 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7327 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7328 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7329 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7330 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7331 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7332 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7333 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7334 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7335 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7336 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7339 for (i = 0; i < dcb_info->nb_tcs; i++) {
7340 tc = &dcb_config->tc_config[i];
7341 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7346 /* Update e-tag ether type */
7348 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7349 uint16_t ether_type)
7351 uint32_t etag_etype;
7353 if (hw->mac.type != ixgbe_mac_X550 &&
7354 hw->mac.type != ixgbe_mac_X550EM_x &&
7355 hw->mac.type != ixgbe_mac_X550EM_a) {
7359 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7360 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7361 etag_etype |= ether_type;
7362 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7363 IXGBE_WRITE_FLUSH(hw);
7368 /* Config l2 tunnel ether type */
7370 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7371 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7374 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7375 struct ixgbe_l2_tn_info *l2_tn_info =
7376 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7378 if (l2_tunnel == NULL)
7381 switch (l2_tunnel->l2_tunnel_type) {
7382 case RTE_L2_TUNNEL_TYPE_E_TAG:
7383 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7384 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7387 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7395 /* Enable e-tag tunnel */
7397 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7399 uint32_t etag_etype;
7401 if (hw->mac.type != ixgbe_mac_X550 &&
7402 hw->mac.type != ixgbe_mac_X550EM_x &&
7403 hw->mac.type != ixgbe_mac_X550EM_a) {
7407 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7408 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7409 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7410 IXGBE_WRITE_FLUSH(hw);
7415 /* Enable l2 tunnel */
7417 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7418 enum rte_eth_tunnel_type l2_tunnel_type)
7421 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7422 struct ixgbe_l2_tn_info *l2_tn_info =
7423 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7425 switch (l2_tunnel_type) {
7426 case RTE_L2_TUNNEL_TYPE_E_TAG:
7427 l2_tn_info->e_tag_en = TRUE;
7428 ret = ixgbe_e_tag_enable(hw);
7431 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7439 /* Disable e-tag tunnel */
7441 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7443 uint32_t etag_etype;
7445 if (hw->mac.type != ixgbe_mac_X550 &&
7446 hw->mac.type != ixgbe_mac_X550EM_x &&
7447 hw->mac.type != ixgbe_mac_X550EM_a) {
7451 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7452 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7453 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7454 IXGBE_WRITE_FLUSH(hw);
7459 /* Disable l2 tunnel */
7461 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7462 enum rte_eth_tunnel_type l2_tunnel_type)
7465 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7466 struct ixgbe_l2_tn_info *l2_tn_info =
7467 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7469 switch (l2_tunnel_type) {
7470 case RTE_L2_TUNNEL_TYPE_E_TAG:
7471 l2_tn_info->e_tag_en = FALSE;
7472 ret = ixgbe_e_tag_disable(hw);
7475 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7484 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7485 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7488 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7489 uint32_t i, rar_entries;
7490 uint32_t rar_low, rar_high;
7492 if (hw->mac.type != ixgbe_mac_X550 &&
7493 hw->mac.type != ixgbe_mac_X550EM_x &&
7494 hw->mac.type != ixgbe_mac_X550EM_a) {
7498 rar_entries = ixgbe_get_num_rx_addrs(hw);
7500 for (i = 1; i < rar_entries; i++) {
7501 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7502 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7503 if ((rar_high & IXGBE_RAH_AV) &&
7504 (rar_high & IXGBE_RAH_ADTYPE) &&
7505 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7506 l2_tunnel->tunnel_id)) {
7507 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7508 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7510 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7520 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7521 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7524 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7525 uint32_t i, rar_entries;
7526 uint32_t rar_low, rar_high;
7528 if (hw->mac.type != ixgbe_mac_X550 &&
7529 hw->mac.type != ixgbe_mac_X550EM_x &&
7530 hw->mac.type != ixgbe_mac_X550EM_a) {
7534 /* One entry for one tunnel. Try to remove potential existing entry. */
7535 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7537 rar_entries = ixgbe_get_num_rx_addrs(hw);
7539 for (i = 1; i < rar_entries; i++) {
7540 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7541 if (rar_high & IXGBE_RAH_AV) {
7544 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7545 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7546 rar_low = l2_tunnel->tunnel_id;
7548 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7549 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7555 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7556 " Please remove a rule before adding a new one.");
7560 static inline struct ixgbe_l2_tn_filter *
7561 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7562 struct ixgbe_l2_tn_key *key)
7566 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7570 return l2_tn_info->hash_map[ret];
7574 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7575 struct ixgbe_l2_tn_filter *l2_tn_filter)
7579 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7580 &l2_tn_filter->key);
7584 "Failed to insert L2 tunnel filter"
7585 " to hash table %d!",
7590 l2_tn_info->hash_map[ret] = l2_tn_filter;
7592 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7598 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7599 struct ixgbe_l2_tn_key *key)
7602 struct ixgbe_l2_tn_filter *l2_tn_filter;
7604 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7608 "No such L2 tunnel filter to delete %d!",
7613 l2_tn_filter = l2_tn_info->hash_map[ret];
7614 l2_tn_info->hash_map[ret] = NULL;
7616 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7617 rte_free(l2_tn_filter);
7622 /* Add l2 tunnel filter */
7624 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7625 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7629 struct ixgbe_l2_tn_info *l2_tn_info =
7630 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7631 struct ixgbe_l2_tn_key key;
7632 struct ixgbe_l2_tn_filter *node;
7635 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7636 key.tn_id = l2_tunnel->tunnel_id;
7638 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7642 "The L2 tunnel filter already exists!");
7646 node = rte_zmalloc("ixgbe_l2_tn",
7647 sizeof(struct ixgbe_l2_tn_filter),
7652 rte_memcpy(&node->key,
7654 sizeof(struct ixgbe_l2_tn_key));
7655 node->pool = l2_tunnel->pool;
7656 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7663 switch (l2_tunnel->l2_tunnel_type) {
7664 case RTE_L2_TUNNEL_TYPE_E_TAG:
7665 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7668 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7673 if ((!restore) && (ret < 0))
7674 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7679 /* Delete l2 tunnel filter */
7681 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7682 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7685 struct ixgbe_l2_tn_info *l2_tn_info =
7686 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7687 struct ixgbe_l2_tn_key key;
7689 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7690 key.tn_id = l2_tunnel->tunnel_id;
7691 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7695 switch (l2_tunnel->l2_tunnel_type) {
7696 case RTE_L2_TUNNEL_TYPE_E_TAG:
7697 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7700 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7709 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7710 * @dev: pointer to rte_eth_dev structure
7711 * @filter_op:operation will be taken.
7712 * @arg: a pointer to specific structure corresponding to the filter_op
7715 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7716 enum rte_filter_op filter_op,
7721 if (filter_op == RTE_ETH_FILTER_NOP)
7725 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7730 switch (filter_op) {
7731 case RTE_ETH_FILTER_ADD:
7732 ret = ixgbe_dev_l2_tunnel_filter_add
7734 (struct rte_eth_l2_tunnel_conf *)arg,
7737 case RTE_ETH_FILTER_DELETE:
7738 ret = ixgbe_dev_l2_tunnel_filter_del
7740 (struct rte_eth_l2_tunnel_conf *)arg);
7743 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7751 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7755 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7757 if (hw->mac.type != ixgbe_mac_X550 &&
7758 hw->mac.type != ixgbe_mac_X550EM_x &&
7759 hw->mac.type != ixgbe_mac_X550EM_a) {
7763 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7764 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7766 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7767 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7772 /* Enable l2 tunnel forwarding */
7774 ixgbe_dev_l2_tunnel_forwarding_enable
7775 (struct rte_eth_dev *dev,
7776 enum rte_eth_tunnel_type l2_tunnel_type)
7778 struct ixgbe_l2_tn_info *l2_tn_info =
7779 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7782 switch (l2_tunnel_type) {
7783 case RTE_L2_TUNNEL_TYPE_E_TAG:
7784 l2_tn_info->e_tag_fwd_en = TRUE;
7785 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7788 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7796 /* Disable l2 tunnel forwarding */
7798 ixgbe_dev_l2_tunnel_forwarding_disable
7799 (struct rte_eth_dev *dev,
7800 enum rte_eth_tunnel_type l2_tunnel_type)
7802 struct ixgbe_l2_tn_info *l2_tn_info =
7803 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7806 switch (l2_tunnel_type) {
7807 case RTE_L2_TUNNEL_TYPE_E_TAG:
7808 l2_tn_info->e_tag_fwd_en = FALSE;
7809 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7812 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7822 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7825 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7827 uint32_t vmtir, vmvir;
7828 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7830 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7832 "VF id %u should be less than %u",
7838 if (hw->mac.type != ixgbe_mac_X550 &&
7839 hw->mac.type != ixgbe_mac_X550EM_x &&
7840 hw->mac.type != ixgbe_mac_X550EM_a) {
7845 vmtir = l2_tunnel->tunnel_id;
7849 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7851 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7852 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7854 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7855 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7860 /* Enable l2 tunnel tag insertion */
7862 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7863 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7867 switch (l2_tunnel->l2_tunnel_type) {
7868 case RTE_L2_TUNNEL_TYPE_E_TAG:
7869 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7872 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7880 /* Disable l2 tunnel tag insertion */
7882 ixgbe_dev_l2_tunnel_insertion_disable
7883 (struct rte_eth_dev *dev,
7884 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7888 switch (l2_tunnel->l2_tunnel_type) {
7889 case RTE_L2_TUNNEL_TYPE_E_TAG:
7890 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7893 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7902 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7907 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7909 if (hw->mac.type != ixgbe_mac_X550 &&
7910 hw->mac.type != ixgbe_mac_X550EM_x &&
7911 hw->mac.type != ixgbe_mac_X550EM_a) {
7915 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7917 qde |= IXGBE_QDE_STRIP_TAG;
7919 qde &= ~IXGBE_QDE_STRIP_TAG;
7920 qde &= ~IXGBE_QDE_READ;
7921 qde |= IXGBE_QDE_WRITE;
7922 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7927 /* Enable l2 tunnel tag stripping */
7929 ixgbe_dev_l2_tunnel_stripping_enable
7930 (struct rte_eth_dev *dev,
7931 enum rte_eth_tunnel_type l2_tunnel_type)
7935 switch (l2_tunnel_type) {
7936 case RTE_L2_TUNNEL_TYPE_E_TAG:
7937 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7940 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7948 /* Disable l2 tunnel tag stripping */
7950 ixgbe_dev_l2_tunnel_stripping_disable
7951 (struct rte_eth_dev *dev,
7952 enum rte_eth_tunnel_type l2_tunnel_type)
7956 switch (l2_tunnel_type) {
7957 case RTE_L2_TUNNEL_TYPE_E_TAG:
7958 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7961 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7969 /* Enable/disable l2 tunnel offload functions */
7971 ixgbe_dev_l2_tunnel_offload_set
7972 (struct rte_eth_dev *dev,
7973 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7979 if (l2_tunnel == NULL)
7983 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7985 ret = ixgbe_dev_l2_tunnel_enable(
7987 l2_tunnel->l2_tunnel_type);
7989 ret = ixgbe_dev_l2_tunnel_disable(
7991 l2_tunnel->l2_tunnel_type);
7994 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7996 ret = ixgbe_dev_l2_tunnel_insertion_enable(
8000 ret = ixgbe_dev_l2_tunnel_insertion_disable(
8005 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8007 ret = ixgbe_dev_l2_tunnel_stripping_enable(
8009 l2_tunnel->l2_tunnel_type);
8011 ret = ixgbe_dev_l2_tunnel_stripping_disable(
8013 l2_tunnel->l2_tunnel_type);
8016 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8018 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8020 l2_tunnel->l2_tunnel_type);
8022 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8024 l2_tunnel->l2_tunnel_type);
8031 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8034 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8035 IXGBE_WRITE_FLUSH(hw);
8040 /* There's only one register for VxLAN UDP port.
8041 * So, we cannot add several ports. Will update it.
8044 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8048 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8052 return ixgbe_update_vxlan_port(hw, port);
8055 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8056 * UDP port, it must have a value.
8057 * So, will reset it to the original value 0.
8060 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8065 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8067 if (cur_port != port) {
8068 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8072 return ixgbe_update_vxlan_port(hw, 0);
8075 /* Add UDP tunneling port */
8077 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8078 struct rte_eth_udp_tunnel *udp_tunnel)
8081 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8083 if (hw->mac.type != ixgbe_mac_X550 &&
8084 hw->mac.type != ixgbe_mac_X550EM_x &&
8085 hw->mac.type != ixgbe_mac_X550EM_a) {
8089 if (udp_tunnel == NULL)
8092 switch (udp_tunnel->prot_type) {
8093 case RTE_TUNNEL_TYPE_VXLAN:
8094 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8097 case RTE_TUNNEL_TYPE_GENEVE:
8098 case RTE_TUNNEL_TYPE_TEREDO:
8099 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8104 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8112 /* Remove UDP tunneling port */
8114 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8115 struct rte_eth_udp_tunnel *udp_tunnel)
8118 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8120 if (hw->mac.type != ixgbe_mac_X550 &&
8121 hw->mac.type != ixgbe_mac_X550EM_x &&
8122 hw->mac.type != ixgbe_mac_X550EM_a) {
8126 if (udp_tunnel == NULL)
8129 switch (udp_tunnel->prot_type) {
8130 case RTE_TUNNEL_TYPE_VXLAN:
8131 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8133 case RTE_TUNNEL_TYPE_GENEVE:
8134 case RTE_TUNNEL_TYPE_TEREDO:
8135 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8139 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8148 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8150 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8152 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8156 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8158 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8160 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8163 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8165 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8168 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8171 /* PF reset VF event */
8172 if (in_msg == IXGBE_PF_CONTROL_MSG)
8173 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8178 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8181 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182 struct ixgbe_interrupt *intr =
8183 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8184 ixgbevf_intr_disable(hw);
8186 /* read-on-clear nic registers here */
8187 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8190 /* only one misc vector supported - mailbox */
8191 eicr &= IXGBE_VTEICR_MASK;
8192 if (eicr == IXGBE_MISC_VEC_ID)
8193 intr->flags |= IXGBE_FLAG_MAILBOX;
8199 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8201 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8202 struct ixgbe_interrupt *intr =
8203 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8205 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8206 ixgbevf_mbx_process(dev);
8207 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8210 ixgbevf_intr_enable(hw);
8216 ixgbevf_dev_interrupt_handler(void *param)
8218 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8220 ixgbevf_dev_interrupt_get_status(dev);
8221 ixgbevf_dev_interrupt_action(dev);
8225 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8226 * @hw: pointer to hardware structure
8228 * Stops the transmit data path and waits for the HW to internally empty
8229 * the Tx security block
8231 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8233 #define IXGBE_MAX_SECTX_POLL 40
8238 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8239 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8240 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8241 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8242 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8243 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8245 /* Use interrupt-safe sleep just in case */
8249 /* For informational purposes only */
8250 if (i >= IXGBE_MAX_SECTX_POLL)
8251 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8252 "path fully disabled. Continuing with init.");
8254 return IXGBE_SUCCESS;
8258 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8259 * @hw: pointer to hardware structure
8261 * Enables the transmit data path.
8263 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8267 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8268 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8269 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8270 IXGBE_WRITE_FLUSH(hw);
8272 return IXGBE_SUCCESS;
8275 /* restore n-tuple filter */
8277 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8279 struct ixgbe_filter_info *filter_info =
8280 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8281 struct ixgbe_5tuple_filter *node;
8283 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8284 ixgbe_inject_5tuple_filter(dev, node);
8288 /* restore ethernet type filter */
8290 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8292 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8293 struct ixgbe_filter_info *filter_info =
8294 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8297 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8298 if (filter_info->ethertype_mask & (1 << i)) {
8299 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8300 filter_info->ethertype_filters[i].etqf);
8301 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8302 filter_info->ethertype_filters[i].etqs);
8303 IXGBE_WRITE_FLUSH(hw);
8308 /* restore SYN filter */
8310 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8312 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8313 struct ixgbe_filter_info *filter_info =
8314 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8317 synqf = filter_info->syn_info;
8319 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8320 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8321 IXGBE_WRITE_FLUSH(hw);
8325 /* restore L2 tunnel filter */
8327 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8329 struct ixgbe_l2_tn_info *l2_tn_info =
8330 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8331 struct ixgbe_l2_tn_filter *node;
8332 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8334 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8335 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8336 l2_tn_conf.tunnel_id = node->key.tn_id;
8337 l2_tn_conf.pool = node->pool;
8338 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8343 ixgbe_filter_restore(struct rte_eth_dev *dev)
8345 ixgbe_ntuple_filter_restore(dev);
8346 ixgbe_ethertype_filter_restore(dev);
8347 ixgbe_syn_filter_restore(dev);
8348 ixgbe_fdir_filter_restore(dev);
8349 ixgbe_l2_tn_filter_restore(dev);
8355 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8357 struct ixgbe_l2_tn_info *l2_tn_info =
8358 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8359 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8361 if (l2_tn_info->e_tag_en)
8362 (void)ixgbe_e_tag_enable(hw);
8364 if (l2_tn_info->e_tag_fwd_en)
8365 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8367 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8370 /* remove all the n-tuple filters */
8372 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8374 struct ixgbe_filter_info *filter_info =
8375 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8376 struct ixgbe_5tuple_filter *p_5tuple;
8378 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8379 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8382 /* remove all the ether type filters */
8384 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8386 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8387 struct ixgbe_filter_info *filter_info =
8388 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8391 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8392 if (filter_info->ethertype_mask & (1 << i) &&
8393 !filter_info->ethertype_filters[i].conf) {
8394 (void)ixgbe_ethertype_filter_remove(filter_info,
8396 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8397 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8398 IXGBE_WRITE_FLUSH(hw);
8403 /* remove the SYN filter */
8405 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8407 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8408 struct ixgbe_filter_info *filter_info =
8409 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8411 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8412 filter_info->syn_info = 0;
8414 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8415 IXGBE_WRITE_FLUSH(hw);
8419 /* remove all the L2 tunnel filters */
8421 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8423 struct ixgbe_l2_tn_info *l2_tn_info =
8424 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8425 struct ixgbe_l2_tn_filter *l2_tn_filter;
8426 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8429 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8430 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8431 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8432 l2_tn_conf.pool = l2_tn_filter->pool;
8433 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8441 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8442 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8443 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8444 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8445 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8446 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");