drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define IXGBE_TIMINCA_16NS_SHIFT 24
 130 #define IXGBE_TIMINCA_INCVALUE   16000000
 131 #define IXGBE_TIMINCA_INIT       ((0x02 << IXGBE_TIMINCA_16NS_SHIFT) \
 132                                   | IXGBE_TIMINCA_INCVALUE)
 133
 134 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 135 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 136 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 137 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 138 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 139 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 140 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 141 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 142 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 143 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 144 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 147                                 int wait_to_complete);
 148 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 149                                 struct rte_eth_stats *stats);
 150 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 151                                 struct rte_eth_xstats *xstats, unsigned n);
 152 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 153                                   struct rte_eth_xstats *xstats, unsigned n);
 154 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 155 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 157                                              uint16_t queue_id,
 158                                              uint8_t stat_idx,
 159                                              uint8_t is_rx);
 160 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_dev_info *dev_info);
 162 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 163                                  struct rte_eth_dev_info *dev_info);
 164 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 165
 166 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 167                 uint16_t vlan_id, int on);
 168 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 169 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 170                 uint16_t queue, bool on);
 171 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 172                 int on);
 173 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 174 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 175 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 176 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 177 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 178
 179 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 180 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 181 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 182                                struct rte_eth_fc_conf *fc_conf);
 183 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 184                                struct rte_eth_fc_conf *fc_conf);
 185 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 186                 struct rte_eth_pfc_conf *pfc_conf);
 187 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 188                         struct rte_eth_rss_reta_entry64 *reta_conf,
 189                         uint16_t reta_size);
 190 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 191                         struct rte_eth_rss_reta_entry64 *reta_conf,
 192                         uint16_t reta_size);
 193 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 195 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 196 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 197 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 198 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 199                 void *param);
 200 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 201 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 202                 uint32_t index, uint32_t pool);
 203 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 204 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 205                                            struct ether_addr *mac_addr);
 206 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 207
 208 /* For Virtual Function support */
 209 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 210 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 211 static int ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev);
 212 static int ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev);
 213 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 214 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 215 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 216 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 217 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 218 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 219 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 220                 struct rte_eth_stats *stats);
 221 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 222 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 223                 uint16_t vlan_id, int on);
 224 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 225                 uint16_t queue, int on);
 226 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 227 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 228 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 229                                           void *param);
 230 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 231                                             uint16_t queue_id);
 232 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 233                                              uint16_t queue_id);
 234 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 235                                  uint8_t queue, uint8_t msix_vector);
 236 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 237
 238 /* For Eth VMDQ APIs support */
 239 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 240                 ether_addr* mac_addr,uint8_t on);
 241 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 242 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 243                 uint16_t rx_mask, uint8_t on);
 244 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 245 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 246 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 247                 uint64_t pool_mask,uint8_t vlan_on);
 248 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 249                 struct rte_eth_mirror_conf *mirror_conf,
 250                 uint8_t rule_id, uint8_t on);
 251 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 252                 uint8_t rule_id);
 253 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 254                                           uint16_t queue_id);
 255 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 256                                            uint16_t queue_id);
 257 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 258                                uint8_t queue, uint8_t msix_vector);
 259 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 260
 261 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 262                 uint16_t queue_idx, uint16_t tx_rate);
 263 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 264                 uint16_t tx_rate, uint64_t q_msk);
 265
 266 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 267                                  struct ether_addr *mac_addr,
 268                                  uint32_t index, uint32_t pool);
 269 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 270 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 271                                              struct ether_addr *mac_addr);
 272 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 273                         struct rte_eth_syn_filter *filter,
 274                         bool add);
 275 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter);
 277 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 278                         enum rte_filter_op filter_op,
 279                         void *arg);
 280 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 281                         struct ixgbe_5tuple_filter *filter);
 282 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 283                         struct ixgbe_5tuple_filter *filter);
 284 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 285                         struct rte_eth_ntuple_filter *filter,
 286                         bool add);
 287 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 288                                 enum rte_filter_op filter_op,
 289                                 void *arg);
 290 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 291                         struct rte_eth_ntuple_filter *filter);
 292 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 293                         struct rte_eth_ethertype_filter *filter,
 294                         bool add);
 295 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 296                                 enum rte_filter_op filter_op,
 297                                 void *arg);
 298 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 299                         struct rte_eth_ethertype_filter *filter);
 300 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 301                      enum rte_filter_type filter_type,
 302                      enum rte_filter_op filter_op,
 303                      void *arg);
 304 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 305
 306 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 307                                       struct ether_addr *mc_addr_set,
 308                                       uint32_t nb_mc_addr);
 309 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 310                                    struct rte_eth_dcb_info *dcb_info);
 311
 312 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 313 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 314                             struct rte_dev_reg_info *regs);
 315 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 317                                 struct rte_dev_eeprom_info *eeprom);
 318 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 319                                 struct rte_dev_eeprom_info *eeprom);
 320
 321 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 322 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 323                                 struct rte_dev_reg_info *regs);
 324
 325 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 326 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 327 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 328                                             struct timespec *timestamp,
 329                                             uint32_t flags);
 330 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp);
 332
 333 /*
 334  * Define VF Stats MACRO for Non "cleared on read" register
 335  */
 336 #define UPDATE_VF_STAT(reg, last, cur)                          \
 337 {                                                               \
 338         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 339         cur += (latest - last) & UINT_MAX;                      \
 340         last = latest;                                          \
 341 }
 342
 343 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 344 {                                                                \
 345         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 346         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 347         u64 latest = ((new_msb << 32) | new_lsb);                \
 348         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 349         last = latest;                                           \
 350 }
 351
 352 #define IXGBE_SET_HWSTRIP(h, q) do{\
 353                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 354                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 355                 (h)->bitmap[idx] |= 1 << bit;\
 356         }while(0)
 357
 358 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 359                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 360                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 361                 (h)->bitmap[idx] &= ~(1 << bit);\
 362         }while(0)
 363
 364 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 365                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 366                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 367                 (r) = (h)->bitmap[idx] >> bit & 1;\
 368         }while(0)
 369
 370 /*
 371  * The set of PCI devices this driver supports
 372  */
 373 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 374
 375 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 376 #include "rte_pci_dev_ids.h"
 377
 378 { .vendor_id = 0, /* sentinel */ },
 379 };
 380
 381
 382 /*
 383  * The set of PCI devices this driver supports (for 82599 VF)
 384  */
 385 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 386
 387 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 388 #include "rte_pci_dev_ids.h"
 389 { .vendor_id = 0, /* sentinel */ },
 390
 391 };
 392
 393 static const struct rte_eth_desc_lim rx_desc_lim = {
 394         .nb_max = IXGBE_MAX_RING_DESC,
 395         .nb_min = IXGBE_MIN_RING_DESC,
 396         .nb_align = IXGBE_RXD_ALIGN,
 397 };
 398
 399 static const struct rte_eth_desc_lim tx_desc_lim = {
 400         .nb_max = IXGBE_MAX_RING_DESC,
 401         .nb_min = IXGBE_MIN_RING_DESC,
 402         .nb_align = IXGBE_TXD_ALIGN,
 403 };
 404
 405 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 406         .dev_configure        = ixgbe_dev_configure,
 407         .dev_start            = ixgbe_dev_start,
 408         .dev_stop             = ixgbe_dev_stop,
 409         .dev_set_link_up    = ixgbe_dev_set_link_up,
 410         .dev_set_link_down  = ixgbe_dev_set_link_down,
 411         .dev_close            = ixgbe_dev_close,
 412         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 413         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 414         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 415         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 416         .link_update          = ixgbe_dev_link_update,
 417         .stats_get            = ixgbe_dev_stats_get,
 418         .xstats_get           = ixgbe_dev_xstats_get,
 419         .stats_reset          = ixgbe_dev_stats_reset,
 420         .xstats_reset         = ixgbe_dev_xstats_reset,
 421         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 422         .dev_infos_get        = ixgbe_dev_info_get,
 423         .mtu_set              = ixgbe_dev_mtu_set,
 424         .vlan_filter_set      = ixgbe_vlan_filter_set,
 425         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 426         .vlan_offload_set     = ixgbe_vlan_offload_set,
 427         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 428         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 429         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 430         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 431         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 432         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 433         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 434         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 435         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 436         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 437         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 438         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 439         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 440         .dev_led_on           = ixgbe_dev_led_on,
 441         .dev_led_off          = ixgbe_dev_led_off,
 442         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 443         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 444         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 445         .mac_addr_add         = ixgbe_add_rar,
 446         .mac_addr_remove      = ixgbe_remove_rar,
 447         .mac_addr_set         = ixgbe_set_default_mac_addr,
 448         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 449         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 450         .mirror_rule_set      = ixgbe_mirror_rule_set,
 451         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 452         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 453         .set_vf_rx            = ixgbe_set_pool_rx,
 454         .set_vf_tx            = ixgbe_set_pool_tx,
 455         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 456         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 457         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 458         .reta_update          = ixgbe_dev_rss_reta_update,
 459         .reta_query           = ixgbe_dev_rss_reta_query,
 460 #ifdef RTE_NIC_BYPASS
 461         .bypass_init          = ixgbe_bypass_init,
 462         .bypass_state_set     = ixgbe_bypass_state_store,
 463         .bypass_state_show    = ixgbe_bypass_state_show,
 464         .bypass_event_set     = ixgbe_bypass_event_store,
 465         .bypass_event_show    = ixgbe_bypass_event_show,
 466         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 467         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 468         .bypass_ver_show      = ixgbe_bypass_ver_show,
 469         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 470 #endif /* RTE_NIC_BYPASS */
 471         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 472         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 473         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 474         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 475         .rxq_info_get         = ixgbe_rxq_info_get,
 476         .txq_info_get         = ixgbe_txq_info_get,
 477         .timesync_enable      = ixgbe_timesync_enable,
 478         .timesync_disable     = ixgbe_timesync_disable,
 479         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 480         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 481         .get_reg_length       = ixgbe_get_reg_length,
 482         .get_reg              = ixgbe_get_regs,
 483         .get_eeprom_length    = ixgbe_get_eeprom_length,
 484         .get_eeprom           = ixgbe_get_eeprom,
 485         .set_eeprom           = ixgbe_set_eeprom,
 486         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 487 };
 488
 489 /*
 490  * dev_ops for virtual function, bare necessities for basic vf
 491  * operation have been implemented
 492  */
 493 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 494         .dev_configure        = ixgbevf_dev_configure,
 495         .dev_start            = ixgbevf_dev_start,
 496         .dev_stop             = ixgbevf_dev_stop,
 497         .link_update          = ixgbe_dev_link_update,
 498         .stats_get            = ixgbevf_dev_stats_get,
 499         .xstats_get           = ixgbevf_dev_xstats_get,
 500         .stats_reset          = ixgbevf_dev_stats_reset,
 501         .xstats_reset         = ixgbevf_dev_stats_reset,
 502         .dev_close            = ixgbevf_dev_close,
 503         .dev_infos_get        = ixgbevf_dev_info_get,
 504         .mtu_set              = ixgbevf_dev_set_mtu,
 505         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 506         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 507         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 508         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 509         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 510         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 511         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 512         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 513         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 514         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 515         .mac_addr_add         = ixgbevf_add_mac_addr,
 516         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 517         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 518         .rxq_info_get         = ixgbe_rxq_info_get,
 519         .txq_info_get         = ixgbe_txq_info_get,
 520         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 521         .get_reg_length       = ixgbevf_get_reg_length,
 522         .get_reg              = ixgbevf_get_regs,
 523         .reta_update          = ixgbe_dev_rss_reta_update,
 524         .reta_query           = ixgbe_dev_rss_reta_query,
 525         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 526         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 527 };
 528
 529 /* store statistics names and its offset in stats structure */
 530 struct rte_ixgbe_xstats_name_off {
 531         char name[RTE_ETH_XSTATS_NAME_SIZE];
 532         unsigned offset;
 533 };
 534
 535 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 536         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 537         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 538         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 539         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 540         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 541         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 542         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 543         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 544         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 545         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 546         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 547         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 548         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 549         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 550         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 551                 prc1023)},
 552         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 553                 prc1522)},
 554         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 555         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 556         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 557         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 558         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 559         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 560         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 561         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 562         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 563         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 564         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 565         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 566         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 567         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 568         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 569         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 570         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 571                 ptc1023)},
 572         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 573                 ptc1522)},
 574         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 575         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 576         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 577         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 578
 579         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 580                 fdirustat_add)},
 581         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 582                 fdirustat_remove)},
 583         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 584                 fdirfstat_fadd)},
 585         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 586                 fdirfstat_fremove)},
 587         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 588                 fdirmatch)},
 589         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 590                 fdirmiss)},
 591
 592         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 593         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 594         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 595                 fclast)},
 596         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 597         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 598         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 599         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 600         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 601                 fcoe_noddp)},
 602         {"rx_fcoe_no_direct_data_placement_ext_buff",
 603                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 604
 605         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 606                 lxontxc)},
 607         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 608                 lxonrxc)},
 609         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 610                 lxofftxc)},
 611         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 612                 lxoffrxc)},
 613         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 614 };
 615
 616 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 617                            sizeof(rte_ixgbe_stats_strings[0]))
 618
 619 /* Per-queue statistics */
 620 #define IXBGE_NB_8_PER_Q_STATS (8 * 7)
 621 #define IXBGE_NB_16_PER_Q_STATS (16 * 5)
 622 #define IXGBE_NB_Q_STATS (IXBGE_NB_8_PER_Q_STATS + IXBGE_NB_16_PER_Q_STATS)
 623
 624 #define IXGBE_NB_XSTATS (IXGBE_NB_HW_STATS + IXGBE_NB_Q_STATS)
 625
 626 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 627         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 628 };
 629
 630 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 631                 sizeof(rte_ixgbevf_stats_strings[0]))
 632
 633 /**
 634  * Atomically reads the link status information from global
 635  * structure rte_eth_dev.
 636  *
 637  * @param dev
 638  *   - Pointer to the structure rte_eth_dev to read from.
 639  *   - Pointer to the buffer to be saved with the link status.
 640  *
 641  * @return
 642  *   - On success, zero.
 643  *   - On failure, negative value.
 644  */
 645 static inline int
 646 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 647                                 struct rte_eth_link *link)
 648 {
 649         struct rte_eth_link *dst = link;
 650         struct rte_eth_link *src = &(dev->data->dev_link);
 651
 652         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 653                                         *(uint64_t *)src) == 0)
 654                 return -1;
 655
 656         return 0;
 657 }
 658
 659 /**
 660  * Atomically writes the link status information into global
 661  * structure rte_eth_dev.
 662  *
 663  * @param dev
 664  *   - Pointer to the structure rte_eth_dev to read from.
 665  *   - Pointer to the buffer to be saved with the link status.
 666  *
 667  * @return
 668  *   - On success, zero.
 669  *   - On failure, negative value.
 670  */
 671 static inline int
 672 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                 struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 687  */
 688 static inline int
 689 ixgbe_is_sfp(struct ixgbe_hw *hw)
 690 {
 691         switch (hw->phy.type) {
 692         case ixgbe_phy_sfp_avago:
 693         case ixgbe_phy_sfp_ftl:
 694         case ixgbe_phy_sfp_intel:
 695         case ixgbe_phy_sfp_unknown:
 696         case ixgbe_phy_sfp_passive_tyco:
 697         case ixgbe_phy_sfp_passive_unknown:
 698                 return 1;
 699         default:
 700                 return 0;
 701         }
 702 }
 703
 704 static inline int32_t
 705 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 706 {
 707         uint32_t ctrl_ext;
 708         int32_t status;
 709
 710         status = ixgbe_reset_hw(hw);
 711
 712         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 713         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 714         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 715         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 716         IXGBE_WRITE_FLUSH(hw);
 717
 718         return status;
 719 }
 720
 721 static inline void
 722 ixgbe_enable_intr(struct rte_eth_dev *dev)
 723 {
 724         struct ixgbe_interrupt *intr =
 725                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 728
 729         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 730         IXGBE_WRITE_FLUSH(hw);
 731 }
 732
 733 /*
 734  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 735  */
 736 static void
 737 ixgbe_disable_intr(struct ixgbe_hw *hw)
 738 {
 739         PMD_INIT_FUNC_TRACE();
 740
 741         if (hw->mac.type == ixgbe_mac_82598EB) {
 742                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 743         } else {
 744                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 745                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 746                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 747         }
 748         IXGBE_WRITE_FLUSH(hw);
 749 }
 750
 751 /*
 752  * This function resets queue statistics mapping registers.
 753  * From Niantic datasheet, Initialization of Statistics section:
 754  * "...if software requires the queue counters, the RQSMR and TQSM registers
 755  * must be re-programmed following a device reset.
 756  */
 757 static void
 758 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 759 {
 760         uint32_t i;
 761
 762         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 763                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 764                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 765         }
 766 }
 767
 768
 769 static int
 770 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 771                                   uint16_t queue_id,
 772                                   uint8_t stat_idx,
 773                                   uint8_t is_rx)
 774 {
 775 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 776 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 777 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 778
 779         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 780         struct ixgbe_stat_mapping_registers *stat_mappings =
 781                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 782         uint32_t qsmr_mask = 0;
 783         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 784         uint32_t q_map;
 785         uint8_t n, offset;
 786
 787         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 788                 (hw->mac.type != ixgbe_mac_X540) &&
 789                 (hw->mac.type != ixgbe_mac_X550) &&
 790                 (hw->mac.type != ixgbe_mac_X550EM_x))
 791                 return -ENOSYS;
 792
 793         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 794                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 795                      queue_id, stat_idx);
 796
 797         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 798         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 799                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 800                 return -EIO;
 801         }
 802         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 803
 804         /* Now clear any previous stat_idx set */
 805         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 806         if (!is_rx)
 807                 stat_mappings->tqsm[n] &= ~clearing_mask;
 808         else
 809                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 810
 811         q_map = (uint32_t)stat_idx;
 812         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 813         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 814         if (!is_rx)
 815                 stat_mappings->tqsm[n] |= qsmr_mask;
 816         else
 817                 stat_mappings->rqsmr[n] |= qsmr_mask;
 818
 819         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 820                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 821                      queue_id, stat_idx);
 822         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 823                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 824
 825         /* Now write the mapping in the appropriate register */
 826         if (is_rx) {
 827                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 828                              stat_mappings->rqsmr[n], n);
 829                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 830         }
 831         else {
 832                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 833                              stat_mappings->tqsm[n], n);
 834                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 835         }
 836         return 0;
 837 }
 838
 839 static void
 840 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 841 {
 842         struct ixgbe_stat_mapping_registers *stat_mappings =
 843                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 844         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 845         int i;
 846
 847         /* write whatever was in stat mapping table to the NIC */
 848         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 849                 /* rx */
 850                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 851
 852                 /* tx */
 853                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 854         }
 855 }
 856
 857 static void
 858 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 859 {
 860         uint8_t i;
 861         struct ixgbe_dcb_tc_config *tc;
 862         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 863
 864         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 865         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 866         for (i = 0; i < dcb_max_tc; i++) {
 867                 tc = &dcb_config->tc_config[i];
 868                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 869                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 870                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 871                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 872                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 873                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 874                 tc->pfc = ixgbe_dcb_pfc_disabled;
 875         }
 876
 877         /* Initialize default user to priority mapping, UPx->TC0 */
 878         tc = &dcb_config->tc_config[0];
 879         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 880         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 881         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 882                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 883                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 884         }
 885         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 886         dcb_config->pfc_mode_enable = false;
 887         dcb_config->vt_mode = true;
 888         dcb_config->round_robin_enable = false;
 889         /* support all DCB capabilities in 82599 */
 890         dcb_config->support.capabilities = 0xFF;
 891
 892         /*we only support 4 Tcs for X540, X550 */
 893         if (hw->mac.type == ixgbe_mac_X540 ||
 894                 hw->mac.type == ixgbe_mac_X550 ||
 895                 hw->mac.type == ixgbe_mac_X550EM_x) {
 896                 dcb_config->num_tcs.pg_tcs = 4;
 897                 dcb_config->num_tcs.pfc_tcs = 4;
 898         }
 899 }
 900
 901 /*
 902  * Ensure that all locks are released before first NVM or PHY access
 903  */
 904 static void
 905 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 906 {
 907         uint16_t mask;
 908
 909         /*
 910          * Phy lock should not fail in this early stage. If this is the case,
 911          * it is due to an improper exit of the application.
 912          * So force the release of the faulty lock. Release of common lock
 913          * is done automatically by swfw_sync function.
 914          */
 915         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 916         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 917                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 918         }
 919         ixgbe_release_swfw_semaphore(hw, mask);
 920
 921         /*
 922          * These ones are more tricky since they are common to all ports; but
 923          * swfw_sync retries last long enough (1s) to be almost sure that if
 924          * lock can not be taken it is due to an improper lock of the
 925          * semaphore.
 926          */
 927         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 928         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 929                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 930         }
 931         ixgbe_release_swfw_semaphore(hw, mask);
 932 }
 933
 934 /*
 935  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 936  * It returns 0 on success.
 937  */
 938 static int
 939 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 940 {
 941         struct rte_pci_device *pci_dev;
 942         struct ixgbe_hw *hw =
 943                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 944         struct ixgbe_vfta * shadow_vfta =
 945                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 946         struct ixgbe_hwstrip *hwstrip =
 947                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 948         struct ixgbe_dcb_config *dcb_config =
 949                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 950         struct ixgbe_filter_info *filter_info =
 951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 952         uint32_t ctrl_ext;
 953         uint16_t csum;
 954         int diag, i;
 955
 956         PMD_INIT_FUNC_TRACE();
 957
 958         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 959         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 960         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 961
 962         /*
 963          * For secondary processes, we don't initialise any further as primary
 964          * has already done this work. Only check we don't need a different
 965          * RX and TX function.
 966          */
 967         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 968                 struct ixgbe_tx_queue *txq;
 969                 /* TX queue function in primary, set by last queue initialized
 970                  * Tx queue may not initialized by primary process */
 971                 if (eth_dev->data->tx_queues) {
 972                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 973                         ixgbe_set_tx_function(eth_dev, txq);
 974                 } else {
 975                         /* Use default TX function if we get here */
 976                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 977                                              "Using default TX function.");
 978                 }
 979
 980                 ixgbe_set_rx_function(eth_dev);
 981
 982                 return 0;
 983         }
 984         pci_dev = eth_dev->pci_dev;
 985
 986         rte_eth_copy_pci_info(eth_dev, pci_dev);
 987
 988         /* Vendor and Device ID need to be set before init of shared code */
 989         hw->device_id = pci_dev->id.device_id;
 990         hw->vendor_id = pci_dev->id.vendor_id;
 991         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 992         hw->allow_unsupported_sfp = 1;
 993
 994         /* Initialize the shared code (base driver) */
 995 #ifdef RTE_NIC_BYPASS
 996         diag = ixgbe_bypass_init_shared_code(hw);
 997 #else
 998         diag = ixgbe_init_shared_code(hw);
 999 #endif /* RTE_NIC_BYPASS */
1000
1001         if (diag != IXGBE_SUCCESS) {
1002                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1003                 return -EIO;
1004         }
1005
1006         /* pick up the PCI bus settings for reporting later */
1007         ixgbe_get_bus_info(hw);
1008
1009         /* Unlock any pending hardware semaphore */
1010         ixgbe_swfw_lock_reset(hw);
1011
1012         /* Initialize DCB configuration*/
1013         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1014         ixgbe_dcb_init(hw,dcb_config);
1015         /* Get Hardware Flow Control setting */
1016         hw->fc.requested_mode = ixgbe_fc_full;
1017         hw->fc.current_mode = ixgbe_fc_full;
1018         hw->fc.pause_time = IXGBE_FC_PAUSE;
1019         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1020                 hw->fc.low_water[i] = IXGBE_FC_LO;
1021                 hw->fc.high_water[i] = IXGBE_FC_HI;
1022         }
1023         hw->fc.send_xon = 1;
1024
1025         /* Make sure we have a good EEPROM before we read from it */
1026         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1027         if (diag != IXGBE_SUCCESS) {
1028                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1029                 return -EIO;
1030         }
1031
1032 #ifdef RTE_NIC_BYPASS
1033         diag = ixgbe_bypass_init_hw(hw);
1034 #else
1035         diag = ixgbe_init_hw(hw);
1036 #endif /* RTE_NIC_BYPASS */
1037
1038         /*
1039          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1040          * is called too soon after the kernel driver unbinding/binding occurs.
1041          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1042          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1043          * also called. See ixgbe_identify_phy_82599(). The reason for the
1044          * failure is not known, and only occuts when virtualisation features
1045          * are disabled in the bios. A delay of 100ms  was found to be enough by
1046          * trial-and-error, and is doubled to be safe.
1047          */
1048         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1049                 rte_delay_ms(200);
1050                 diag = ixgbe_init_hw(hw);
1051         }
1052
1053         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1054                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1055                     "LOM.  Please be aware there may be issues associated "
1056                     "with your hardware.");
1057                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1058                     "please contact your Intel or hardware representative "
1059                     "who provided you with this hardware.");
1060         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1061                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1062         if (diag) {
1063                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1064                 return -EIO;
1065         }
1066
1067         /* Reset the hw statistics */
1068         ixgbe_dev_stats_reset(eth_dev);
1069
1070         /* disable interrupt */
1071         ixgbe_disable_intr(hw);
1072
1073         /* reset mappings for queue statistics hw counters*/
1074         ixgbe_reset_qstat_mappings(hw);
1075
1076         /* Allocate memory for storing MAC addresses */
1077         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1078                         hw->mac.num_rar_entries, 0);
1079         if (eth_dev->data->mac_addrs == NULL) {
1080                 PMD_INIT_LOG(ERR,
1081                         "Failed to allocate %u bytes needed to store "
1082                         "MAC addresses",
1083                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1084                 return -ENOMEM;
1085         }
1086         /* Copy the permanent MAC address */
1087         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1088                         &eth_dev->data->mac_addrs[0]);
1089
1090         /* Allocate memory for storing hash filter MAC addresses */
1091         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1092                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1093         if (eth_dev->data->hash_mac_addrs == NULL) {
1094                 PMD_INIT_LOG(ERR,
1095                         "Failed to allocate %d bytes needed to store MAC addresses",
1096                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1097                 return -ENOMEM;
1098         }
1099
1100         /* initialize the vfta */
1101         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1102
1103         /* initialize the hw strip bitmap*/
1104         memset(hwstrip, 0, sizeof(*hwstrip));
1105
1106         /* initialize PF if max_vfs not zero */
1107         ixgbe_pf_host_init(eth_dev);
1108
1109         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1110         /* let hardware know driver is loaded */
1111         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1112         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1113         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1114         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1115         IXGBE_WRITE_FLUSH(hw);
1116
1117         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1118                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1119                              (int) hw->mac.type, (int) hw->phy.type,
1120                              (int) hw->phy.sfp_type);
1121         else
1122                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1123                              (int) hw->mac.type, (int) hw->phy.type);
1124
1125         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1126                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1127                         pci_dev->id.device_id);
1128
1129         rte_intr_callback_register(&pci_dev->intr_handle,
1130                                    ixgbe_dev_interrupt_handler,
1131                                    (void *)eth_dev);
1132
1133         /* enable uio/vfio intr/eventfd mapping */
1134         rte_intr_enable(&pci_dev->intr_handle);
1135
1136         /* enable support intr */
1137         ixgbe_enable_intr(eth_dev);
1138
1139         /* initialize 5tuple filter list */
1140         TAILQ_INIT(&filter_info->fivetuple_list);
1141         memset(filter_info->fivetuple_mask, 0,
1142                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1143
1144         return 0;
1145 }
1146
1147 static int
1148 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1149 {
1150         struct rte_pci_device *pci_dev;
1151         struct ixgbe_hw *hw;
1152
1153         PMD_INIT_FUNC_TRACE();
1154
1155         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1156                 return -EPERM;
1157
1158         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1159         pci_dev = eth_dev->pci_dev;
1160
1161         if (hw->adapter_stopped == 0)
1162                 ixgbe_dev_close(eth_dev);
1163
1164         eth_dev->dev_ops = NULL;
1165         eth_dev->rx_pkt_burst = NULL;
1166         eth_dev->tx_pkt_burst = NULL;
1167
1168         /* Unlock any pending hardware semaphore */
1169         ixgbe_swfw_lock_reset(hw);
1170
1171         /* disable uio intr before callback unregister */
1172         rte_intr_disable(&(pci_dev->intr_handle));
1173         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1174                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1175
1176         /* uninitialize PF if max_vfs not zero */
1177         ixgbe_pf_host_uninit(eth_dev);
1178
1179         rte_free(eth_dev->data->mac_addrs);
1180         eth_dev->data->mac_addrs = NULL;
1181
1182         rte_free(eth_dev->data->hash_mac_addrs);
1183         eth_dev->data->hash_mac_addrs = NULL;
1184
1185         return 0;
1186 }
1187
1188 /*
1189  * Negotiate mailbox API version with the PF.
1190  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1191  * Then we try to negotiate starting with the most recent one.
1192  * If all negotiation attempts fail, then we will proceed with
1193  * the default one (ixgbe_mbox_api_10).
1194  */
1195 static void
1196 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1197 {
1198         int32_t i;
1199
1200         /* start with highest supported, proceed down */
1201         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1202                 ixgbe_mbox_api_11,
1203                 ixgbe_mbox_api_10,
1204         };
1205
1206         for (i = 0;
1207                         i != RTE_DIM(sup_ver) &&
1208                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1209                         i++)
1210                 ;
1211 }
1212
1213 static void
1214 generate_random_mac_addr(struct ether_addr *mac_addr)
1215 {
1216         uint64_t random;
1217
1218         /* Set Organizationally Unique Identifier (OUI) prefix. */
1219         mac_addr->addr_bytes[0] = 0x00;
1220         mac_addr->addr_bytes[1] = 0x09;
1221         mac_addr->addr_bytes[2] = 0xC0;
1222         /* Force indication of locally assigned MAC address. */
1223         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1224         /* Generate the last 3 bytes of the MAC address with a random number. */
1225         random = rte_rand();
1226         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1227 }
1228
1229 /*
1230  * Virtual Function device init
1231  */
1232 static int
1233 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1234 {
1235         int diag;
1236         uint32_t tc, tcs;
1237         struct rte_pci_device *pci_dev;
1238         struct ixgbe_hw *hw =
1239                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1240         struct ixgbe_vfta * shadow_vfta =
1241                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1242         struct ixgbe_hwstrip *hwstrip =
1243                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1244         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1245
1246         PMD_INIT_FUNC_TRACE();
1247
1248         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1249         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1250         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1251
1252         /* for secondary processes, we don't initialise any further as primary
1253          * has already done this work. Only check we don't need a different
1254          * RX function */
1255         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1256                 if (eth_dev->data->scattered_rx)
1257                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1258                 return 0;
1259         }
1260
1261         pci_dev = eth_dev->pci_dev;
1262
1263         rte_eth_copy_pci_info(eth_dev, pci_dev);
1264
1265         hw->device_id = pci_dev->id.device_id;
1266         hw->vendor_id = pci_dev->id.vendor_id;
1267         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1268
1269         /* initialize the vfta */
1270         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1271
1272         /* initialize the hw strip bitmap*/
1273         memset(hwstrip, 0, sizeof(*hwstrip));
1274
1275         /* Initialize the shared code (base driver) */
1276         diag = ixgbe_init_shared_code(hw);
1277         if (diag != IXGBE_SUCCESS) {
1278                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1279                 return -EIO;
1280         }
1281
1282         /* init_mailbox_params */
1283         hw->mbx.ops.init_params(hw);
1284
1285         /* Reset the hw statistics */
1286         ixgbevf_dev_stats_reset(eth_dev);
1287
1288         /* Disable the interrupts for VF */
1289         ixgbevf_intr_disable(hw);
1290
1291         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1292         diag = hw->mac.ops.reset_hw(hw);
1293
1294         /*
1295          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1296          * the underlying PF driver has not assigned a MAC address to the VF.
1297          * In this case, assign a random MAC address.
1298          */
1299         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1300                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1301                 return (diag);
1302         }
1303
1304         /* negotiate mailbox API version to use with the PF. */
1305         ixgbevf_negotiate_api(hw);
1306
1307         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1308         ixgbevf_get_queues(hw, &tcs, &tc);
1309
1310         /* Allocate memory for storing MAC addresses */
1311         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1312                         hw->mac.num_rar_entries, 0);
1313         if (eth_dev->data->mac_addrs == NULL) {
1314                 PMD_INIT_LOG(ERR,
1315                         "Failed to allocate %u bytes needed to store "
1316                         "MAC addresses",
1317                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1318                 return -ENOMEM;
1319         }
1320
1321         /* Generate a random MAC address, if none was assigned by PF. */
1322         if (is_zero_ether_addr(perm_addr)) {
1323                 generate_random_mac_addr(perm_addr);
1324                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1325                 if (diag) {
1326                         rte_free(eth_dev->data->mac_addrs);
1327                         eth_dev->data->mac_addrs = NULL;
1328                         return diag;
1329                 }
1330                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1331                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1332                              "%02x:%02x:%02x:%02x:%02x:%02x",
1333                              perm_addr->addr_bytes[0],
1334                              perm_addr->addr_bytes[1],
1335                              perm_addr->addr_bytes[2],
1336                              perm_addr->addr_bytes[3],
1337                              perm_addr->addr_bytes[4],
1338                              perm_addr->addr_bytes[5]);
1339         }
1340
1341         /* Copy the permanent MAC address */
1342         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1343
1344         /* reset the hardware with the new settings */
1345         diag = hw->mac.ops.start_hw(hw);
1346         switch (diag) {
1347                 case  0:
1348                         break;
1349
1350                 default:
1351                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1352                         return (-EIO);
1353         }
1354
1355         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1356                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1357                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1358
1359         return 0;
1360 }
1361
1362 /* Virtual Function device uninit */
1363
1364 static int
1365 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1366 {
1367         struct ixgbe_hw *hw;
1368         unsigned i;
1369
1370         PMD_INIT_FUNC_TRACE();
1371
1372         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1373                 return -EPERM;
1374
1375         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1376
1377         if (hw->adapter_stopped == 0)
1378                 ixgbevf_dev_close(eth_dev);
1379
1380         eth_dev->dev_ops = NULL;
1381         eth_dev->rx_pkt_burst = NULL;
1382         eth_dev->tx_pkt_burst = NULL;
1383
1384         /* Disable the interrupts for VF */
1385         ixgbevf_intr_disable(hw);
1386
1387         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1388                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1389                 eth_dev->data->rx_queues[i] = NULL;
1390         }
1391         eth_dev->data->nb_rx_queues = 0;
1392
1393         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1394                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1395                 eth_dev->data->tx_queues[i] = NULL;
1396         }
1397         eth_dev->data->nb_tx_queues = 0;
1398
1399         rte_free(eth_dev->data->mac_addrs);
1400         eth_dev->data->mac_addrs = NULL;
1401
1402         return 0;
1403 }
1404
1405 static struct eth_driver rte_ixgbe_pmd = {
1406         .pci_drv = {
1407                 .name = "rte_ixgbe_pmd",
1408                 .id_table = pci_id_ixgbe_map,
1409                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1410                         RTE_PCI_DRV_DETACHABLE,
1411         },
1412         .eth_dev_init = eth_ixgbe_dev_init,
1413         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1414         .dev_private_size = sizeof(struct ixgbe_adapter),
1415 };
1416
1417 /*
1418  * virtual function driver struct
1419  */
1420 static struct eth_driver rte_ixgbevf_pmd = {
1421         .pci_drv = {
1422                 .name = "rte_ixgbevf_pmd",
1423                 .id_table = pci_id_ixgbevf_map,
1424                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1425         },
1426         .eth_dev_init = eth_ixgbevf_dev_init,
1427         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1428         .dev_private_size = sizeof(struct ixgbe_adapter),
1429 };
1430
1431 /*
1432  * Driver initialization routine.
1433  * Invoked once at EAL init time.
1434  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1435  */
1436 static int
1437 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1438 {
1439         PMD_INIT_FUNC_TRACE();
1440
1441         rte_eth_driver_register(&rte_ixgbe_pmd);
1442         return 0;
1443 }
1444
1445 /*
1446  * VF Driver initialization routine.
1447  * Invoked one at EAL init time.
1448  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1449  */
1450 static int
1451 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1452 {
1453         PMD_INIT_FUNC_TRACE();
1454
1455         rte_eth_driver_register(&rte_ixgbevf_pmd);
1456         return (0);
1457 }
1458
1459 static int
1460 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1461 {
1462         struct ixgbe_hw *hw =
1463                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464         struct ixgbe_vfta * shadow_vfta =
1465                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1466         uint32_t vfta;
1467         uint32_t vid_idx;
1468         uint32_t vid_bit;
1469
1470         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1471         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1472         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1473         if (on)
1474                 vfta |= vid_bit;
1475         else
1476                 vfta &= ~vid_bit;
1477         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1478
1479         /* update local VFTA copy */
1480         shadow_vfta->vfta[vid_idx] = vfta;
1481
1482         return 0;
1483 }
1484
1485 static void
1486 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1487 {
1488         if (on)
1489                 ixgbe_vlan_hw_strip_enable(dev, queue);
1490         else
1491                 ixgbe_vlan_hw_strip_disable(dev, queue);
1492 }
1493
1494 static void
1495 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1496 {
1497         struct ixgbe_hw *hw =
1498                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1499
1500         /* Only the high 16-bits is valid */
1501         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1502 }
1503
1504 void
1505 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1506 {
1507         struct ixgbe_hw *hw =
1508                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1509         uint32_t vlnctrl;
1510
1511         PMD_INIT_FUNC_TRACE();
1512
1513         /* Filter Table Disable */
1514         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1515         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1516
1517         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1518 }
1519
1520 void
1521 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1522 {
1523         struct ixgbe_hw *hw =
1524                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525         struct ixgbe_vfta * shadow_vfta =
1526                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1527         uint32_t vlnctrl;
1528         uint16_t i;
1529
1530         PMD_INIT_FUNC_TRACE();
1531
1532         /* Filter Table Enable */
1533         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1534         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1535         vlnctrl |= IXGBE_VLNCTRL_VFE;
1536
1537         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1538
1539         /* write whatever is in local vfta copy */
1540         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1541                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1542 }
1543
1544 static void
1545 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1546 {
1547         struct ixgbe_hwstrip *hwstrip =
1548                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1549
1550         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1551                 return;
1552
1553         if (on)
1554                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1555         else
1556                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1557 }
1558
1559 static void
1560 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1561 {
1562         struct ixgbe_hw *hw =
1563                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1564         uint32_t ctrl;
1565
1566         PMD_INIT_FUNC_TRACE();
1567
1568         if (hw->mac.type == ixgbe_mac_82598EB) {
1569                 /* No queue level support */
1570                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1571                 return;
1572         }
1573         else {
1574                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1575                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1576                 ctrl &= ~IXGBE_RXDCTL_VME;
1577                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1578         }
1579         /* record those setting for HW strip per queue */
1580         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1581 }
1582
1583 static void
1584 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1585 {
1586         struct ixgbe_hw *hw =
1587                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1588         uint32_t ctrl;
1589
1590         PMD_INIT_FUNC_TRACE();
1591
1592         if (hw->mac.type == ixgbe_mac_82598EB) {
1593                 /* No queue level supported */
1594                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1595                 return;
1596         }
1597         else {
1598                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1599                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1600                 ctrl |= IXGBE_RXDCTL_VME;
1601                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1602         }
1603         /* record those setting for HW strip per queue */
1604         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1605 }
1606
1607 void
1608 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1609 {
1610         struct ixgbe_hw *hw =
1611                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1612         uint32_t ctrl;
1613         uint16_t i;
1614
1615         PMD_INIT_FUNC_TRACE();
1616
1617         if (hw->mac.type == ixgbe_mac_82598EB) {
1618                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1619                 ctrl &= ~IXGBE_VLNCTRL_VME;
1620                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1621         }
1622         else {
1623                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1624                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1625                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1626                         ctrl &= ~IXGBE_RXDCTL_VME;
1627                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1628
1629                         /* record those setting for HW strip per queue */
1630                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1631                 }
1632         }
1633 }
1634
1635 void
1636 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1637 {
1638         struct ixgbe_hw *hw =
1639                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1640         uint32_t ctrl;
1641         uint16_t i;
1642
1643         PMD_INIT_FUNC_TRACE();
1644
1645         if (hw->mac.type == ixgbe_mac_82598EB) {
1646                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1647                 ctrl |= IXGBE_VLNCTRL_VME;
1648                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1649         }
1650         else {
1651                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1652                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1653                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1654                         ctrl |= IXGBE_RXDCTL_VME;
1655                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1656
1657                         /* record those setting for HW strip per queue */
1658                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1659                 }
1660         }
1661 }
1662
1663 static void
1664 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1665 {
1666         struct ixgbe_hw *hw =
1667                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668         uint32_t ctrl;
1669
1670         PMD_INIT_FUNC_TRACE();
1671
1672         /* DMATXCTRL: Geric Double VLAN Disable */
1673         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1674         ctrl &= ~IXGBE_DMATXCTL_GDV;
1675         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1676
1677         /* CTRL_EXT: Global Double VLAN Disable */
1678         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1679         ctrl &= ~IXGBE_EXTENDED_VLAN;
1680         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1681
1682 }
1683
1684 static void
1685 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1686 {
1687         struct ixgbe_hw *hw =
1688                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689         uint32_t ctrl;
1690
1691         PMD_INIT_FUNC_TRACE();
1692
1693         /* DMATXCTRL: Geric Double VLAN Enable */
1694         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1695         ctrl |= IXGBE_DMATXCTL_GDV;
1696         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1697
1698         /* CTRL_EXT: Global Double VLAN Enable */
1699         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1700         ctrl |= IXGBE_EXTENDED_VLAN;
1701         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1702
1703         /*
1704          * VET EXT field in the EXVET register = 0x8100 by default
1705          * So no need to change. Same to VT field of DMATXCTL register
1706          */
1707 }
1708
1709 static void
1710 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1711 {
1712         if(mask & ETH_VLAN_STRIP_MASK){
1713                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1714                         ixgbe_vlan_hw_strip_enable_all(dev);
1715                 else
1716                         ixgbe_vlan_hw_strip_disable_all(dev);
1717         }
1718
1719         if(mask & ETH_VLAN_FILTER_MASK){
1720                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1721                         ixgbe_vlan_hw_filter_enable(dev);
1722                 else
1723                         ixgbe_vlan_hw_filter_disable(dev);
1724         }
1725
1726         if(mask & ETH_VLAN_EXTEND_MASK){
1727                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1728                         ixgbe_vlan_hw_extend_enable(dev);
1729                 else
1730                         ixgbe_vlan_hw_extend_disable(dev);
1731         }
1732 }
1733
1734 static void
1735 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1736 {
1737         struct ixgbe_hw *hw =
1738                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1739         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1740         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1741         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1742         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1743 }
1744
1745 static int
1746 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1747 {
1748         switch (nb_rx_q) {
1749         case 1:
1750         case 2:
1751                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1752                 break;
1753         case 4:
1754                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1755                 break;
1756         default:
1757                 return -EINVAL;
1758         }
1759
1760         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1761         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1762
1763         return 0;
1764 }
1765
1766 static int
1767 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1768 {
1769         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1770         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1771         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1772
1773         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1774                 /* check multi-queue mode */
1775                 switch (dev_conf->rxmode.mq_mode) {
1776                 case ETH_MQ_RX_VMDQ_DCB:
1777                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1778                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1779                         PMD_INIT_LOG(ERR, "SRIOV active,"
1780                                         " unsupported mq_mode rx %d.",
1781                                         dev_conf->rxmode.mq_mode);
1782                         return -EINVAL;
1783                 case ETH_MQ_RX_RSS:
1784                 case ETH_MQ_RX_VMDQ_RSS:
1785                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1786                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1787                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1788                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1789                                                 " invalid queue number"
1790                                                 " for VMDQ RSS, allowed"
1791                                                 " value are 1, 2 or 4.");
1792                                         return -EINVAL;
1793                                 }
1794                         break;
1795                 case ETH_MQ_RX_VMDQ_ONLY:
1796                 case ETH_MQ_RX_NONE:
1797                         /* if nothing mq mode configure, use default scheme */
1798                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1799                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1800                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1801                         break;
1802                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1803                         /* SRIOV only works in VMDq enable mode */
1804                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1805                                         " wrong mq_mode rx %d.",
1806                                         dev_conf->rxmode.mq_mode);
1807                         return -EINVAL;
1808                 }
1809
1810                 switch (dev_conf->txmode.mq_mode) {
1811                 case ETH_MQ_TX_VMDQ_DCB:
1812                         /* DCB VMDQ in SRIOV mode, not implement yet */
1813                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1814                                         " unsupported VMDQ mq_mode tx %d.",
1815                                         dev_conf->txmode.mq_mode);
1816                         return -EINVAL;
1817                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1818                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1819                         break;
1820                 }
1821
1822                 /* check valid queue number */
1823                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1824                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1825                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1826                                         " queue number must less equal to %d.",
1827                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1828                         return -EINVAL;
1829                 }
1830         } else {
1831                 /* check configuration for vmdb+dcb mode */
1832                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1833                         const struct rte_eth_vmdq_dcb_conf *conf;
1834
1835                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1836                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1837                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1838                                 return -EINVAL;
1839                         }
1840                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1841                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1842                                conf->nb_queue_pools == ETH_32_POOLS)) {
1843                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1844                                                 " nb_queue_pools must be %d or %d.",
1845                                                 ETH_16_POOLS, ETH_32_POOLS);
1846                                 return -EINVAL;
1847                         }
1848                 }
1849                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1850                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1851
1852                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1853                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1854                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1855                                 return -EINVAL;
1856                         }
1857                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1858                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1859                                conf->nb_queue_pools == ETH_32_POOLS)) {
1860                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1861                                                 " nb_queue_pools != %d and"
1862                                                 " nb_queue_pools != %d.",
1863                                                 ETH_16_POOLS, ETH_32_POOLS);
1864                                 return -EINVAL;
1865                         }
1866                 }
1867
1868                 /* For DCB mode check our configuration before we go further */
1869                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1870                         const struct rte_eth_dcb_rx_conf *conf;
1871
1872                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1873                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1874                                                  IXGBE_DCB_NB_QUEUES);
1875                                 return -EINVAL;
1876                         }
1877                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1878                         if (!(conf->nb_tcs == ETH_4_TCS ||
1879                                conf->nb_tcs == ETH_8_TCS)) {
1880                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1881                                                 " and nb_tcs != %d.",
1882                                                 ETH_4_TCS, ETH_8_TCS);
1883                                 return -EINVAL;
1884                         }
1885                 }
1886
1887                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1888                         const struct rte_eth_dcb_tx_conf *conf;
1889
1890                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1891                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1892                                                  IXGBE_DCB_NB_QUEUES);
1893                                 return -EINVAL;
1894                         }
1895                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1896                         if (!(conf->nb_tcs == ETH_4_TCS ||
1897                                conf->nb_tcs == ETH_8_TCS)) {
1898                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1899                                                 " and nb_tcs != %d.",
1900                                                 ETH_4_TCS, ETH_8_TCS);
1901                                 return -EINVAL;
1902                         }
1903                 }
1904         }
1905         return 0;
1906 }
1907
1908 static int
1909 ixgbe_dev_configure(struct rte_eth_dev *dev)
1910 {
1911         struct ixgbe_interrupt *intr =
1912                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1913         struct ixgbe_adapter *adapter =
1914                 (struct ixgbe_adapter *)dev->data->dev_private;
1915         int ret;
1916
1917         PMD_INIT_FUNC_TRACE();
1918         /* multipe queue mode checking */
1919         ret  = ixgbe_check_mq_mode(dev);
1920         if (ret != 0) {
1921                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1922                             ret);
1923                 return ret;
1924         }
1925
1926         /* set flag to update link status after init */
1927         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1928
1929         /*
1930          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1931          * allocation or vector Rx preconditions we will reset it.
1932          */
1933         adapter->rx_bulk_alloc_allowed = true;
1934         adapter->rx_vec_allowed = true;
1935
1936         return 0;
1937 }
1938
1939 /*
1940  * Configure device link speed and setup link.
1941  * It returns 0 on success.
1942  */
1943 static int
1944 ixgbe_dev_start(struct rte_eth_dev *dev)
1945 {
1946         struct ixgbe_hw *hw =
1947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948         struct ixgbe_vf_info *vfinfo =
1949                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1950         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1951         uint32_t intr_vector = 0;
1952         int err, link_up = 0, negotiate = 0;
1953         uint32_t speed = 0;
1954         int mask = 0;
1955         int status;
1956         uint16_t vf, idx;
1957
1958         PMD_INIT_FUNC_TRACE();
1959
1960         /* IXGBE devices don't support half duplex */
1961         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1962                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1963                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1964                              dev->data->dev_conf.link_duplex,
1965                              dev->data->port_id);
1966                 return -EINVAL;
1967         }
1968
1969         /* stop adapter */
1970         hw->adapter_stopped = 0;
1971         ixgbe_stop_adapter(hw);
1972
1973         /* reinitialize adapter
1974          * this calls reset and start */
1975         status = ixgbe_pf_reset_hw(hw);
1976         if (status != 0)
1977                 return -1;
1978         hw->mac.ops.start_hw(hw);
1979         hw->mac.get_link_status = true;
1980
1981         /* configure PF module if SRIOV enabled */
1982         ixgbe_pf_host_configure(dev);
1983
1984         /* check and configure queue intr-vector mapping */
1985         if ((rte_intr_cap_multiple(intr_handle) ||
1986              !RTE_ETH_DEV_SRIOV(dev).active) &&
1987             dev->data->dev_conf.intr_conf.rxq != 0) {
1988                 intr_vector = dev->data->nb_rx_queues;
1989                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1990                         return -1;
1991         }
1992
1993         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1994                 intr_handle->intr_vec =
1995                         rte_zmalloc("intr_vec",
1996                                     dev->data->nb_rx_queues * sizeof(int), 0);
1997                 if (intr_handle->intr_vec == NULL) {
1998                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1999                                      " intr_vec\n", dev->data->nb_rx_queues);
2000                         return -ENOMEM;
2001                 }
2002         }
2003
2004         /* confiugre msix for sleep until rx interrupt */
2005         ixgbe_configure_msix(dev);
2006
2007         /* initialize transmission unit */
2008         ixgbe_dev_tx_init(dev);
2009
2010         /* This can fail when allocating mbufs for descriptor rings */
2011         err = ixgbe_dev_rx_init(dev);
2012         if (err) {
2013                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2014                 goto error;
2015         }
2016
2017         err = ixgbe_dev_rxtx_start(dev);
2018         if (err < 0) {
2019                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2020                 goto error;
2021         }
2022
2023         /* Skip link setup if loopback mode is enabled for 82599. */
2024         if (hw->mac.type == ixgbe_mac_82599EB &&
2025                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2026                 goto skip_link_setup;
2027
2028         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2029                 err = hw->mac.ops.setup_sfp(hw);
2030                 if (err)
2031                         goto error;
2032         }
2033
2034         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2035                 /* Turn on the copper */
2036                 ixgbe_set_phy_power(hw, true);
2037         } else {
2038                 /* Turn on the laser */
2039                 ixgbe_enable_tx_laser(hw);
2040         }
2041
2042         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2043         if (err)
2044                 goto error;
2045         dev->data->dev_link.link_status = link_up;
2046
2047         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2048         if (err)
2049                 goto error;
2050
2051         switch(dev->data->dev_conf.link_speed) {
2052         case ETH_LINK_SPEED_AUTONEG:
2053                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2054                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2055                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2056                 break;
2057         case ETH_LINK_SPEED_100:
2058                 /*
2059                  * Invalid for 82598 but error will be detected by
2060                  * ixgbe_setup_link()
2061                  */
2062                 speed = IXGBE_LINK_SPEED_100_FULL;
2063                 break;
2064         case ETH_LINK_SPEED_1000:
2065                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2066                 break;
2067         case ETH_LINK_SPEED_10000:
2068                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2069                 break;
2070         default:
2071                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2072                              dev->data->dev_conf.link_speed,
2073                              dev->data->port_id);
2074                 goto error;
2075         }
2076
2077         err = ixgbe_setup_link(hw, speed, link_up);
2078         if (err)
2079                 goto error;
2080
2081 skip_link_setup:
2082
2083         if (rte_intr_allow_others(intr_handle)) {
2084                 /* check if lsc interrupt is enabled */
2085                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2086                         ixgbe_dev_lsc_interrupt_setup(dev);
2087         } else {
2088                 rte_intr_callback_unregister(intr_handle,
2089                                              ixgbe_dev_interrupt_handler,
2090                                              (void *)dev);
2091                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2092                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2093                                      " no intr multiplex\n");
2094         }
2095
2096         /* check if rxq interrupt is enabled */
2097         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2098             rte_intr_dp_is_en(intr_handle))
2099                 ixgbe_dev_rxq_interrupt_setup(dev);
2100
2101         /* enable uio/vfio intr/eventfd mapping */
2102         rte_intr_enable(intr_handle);
2103
2104         /* resume enabled intr since hw reset */
2105         ixgbe_enable_intr(dev);
2106
2107         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2108                 ETH_VLAN_EXTEND_MASK;
2109         ixgbe_vlan_offload_set(dev, mask);
2110
2111         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2112                 /* Enable vlan filtering for VMDq */
2113                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2114         }
2115
2116         /* Configure DCB hw */
2117         ixgbe_configure_dcb(dev);
2118
2119         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2120                 err = ixgbe_fdir_configure(dev);
2121                 if (err)
2122                         goto error;
2123         }
2124
2125         /* Restore vf rate limit */
2126         if (vfinfo != NULL) {
2127                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2128                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2129                                 if (vfinfo[vf].tx_rate[idx] != 0)
2130                                         ixgbe_set_vf_rate_limit(dev, vf,
2131                                                 vfinfo[vf].tx_rate[idx],
2132                                                 1 << idx);
2133         }
2134
2135         ixgbe_restore_statistics_mapping(dev);
2136
2137         return (0);
2138
2139 error:
2140         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2141         ixgbe_dev_clear_queues(dev);
2142         return -EIO;
2143 }
2144
2145 /*
2146  * Stop device: disable rx and tx functions to allow for reconfiguring.
2147  */
2148 static void
2149 ixgbe_dev_stop(struct rte_eth_dev *dev)
2150 {
2151         struct rte_eth_link link;
2152         struct ixgbe_hw *hw =
2153                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2154         struct ixgbe_vf_info *vfinfo =
2155                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2156         struct ixgbe_filter_info *filter_info =
2157                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2158         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2159         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2160         int vf;
2161
2162         PMD_INIT_FUNC_TRACE();
2163
2164         /* disable interrupts */
2165         ixgbe_disable_intr(hw);
2166
2167         /* disable intr eventfd mapping */
2168         rte_intr_disable(intr_handle);
2169
2170         /* reset the NIC */
2171         ixgbe_pf_reset_hw(hw);
2172         hw->adapter_stopped = 0;
2173
2174         /* stop adapter */
2175         ixgbe_stop_adapter(hw);
2176
2177         for (vf = 0; vfinfo != NULL &&
2178                      vf < dev->pci_dev->max_vfs; vf++)
2179                 vfinfo[vf].clear_to_send = false;
2180
2181         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2182                 /* Turn off the copper */
2183                 ixgbe_set_phy_power(hw, false);
2184         } else {
2185                 /* Turn off the laser */
2186                 ixgbe_disable_tx_laser(hw);
2187         }
2188
2189         ixgbe_dev_clear_queues(dev);
2190
2191         /* Clear stored conf */
2192         dev->data->scattered_rx = 0;
2193         dev->data->lro = 0;
2194
2195         /* Clear recorded link status */
2196         memset(&link, 0, sizeof(link));
2197         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2198
2199         /* Remove all ntuple filters of the device */
2200         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2201              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2202                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2203                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2204                              p_5tuple, entries);
2205                 rte_free(p_5tuple);
2206         }
2207         memset(filter_info->fivetuple_mask, 0,
2208                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2209
2210         if (!rte_intr_allow_others(intr_handle))
2211                 /* resume to the default handler */
2212                 rte_intr_callback_register(intr_handle,
2213                                            ixgbe_dev_interrupt_handler,
2214                                            (void *)dev);
2215
2216         /* Clean datapath event and queue/vec mapping */
2217         rte_intr_efd_disable(intr_handle);
2218         if (intr_handle->intr_vec != NULL) {
2219                 rte_free(intr_handle->intr_vec);
2220                 intr_handle->intr_vec = NULL;
2221         }
2222 }
2223
2224 /*
2225  * Set device link up: enable tx.
2226  */
2227 static int
2228 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2229 {
2230         struct ixgbe_hw *hw =
2231                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232         if (hw->mac.type == ixgbe_mac_82599EB) {
2233 #ifdef RTE_NIC_BYPASS
2234                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2235                         /* Not suported in bypass mode */
2236                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2237                                      "by device id 0x%x", hw->device_id);
2238                         return -ENOTSUP;
2239                 }
2240 #endif
2241         }
2242
2243         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2244                 /* Turn on the copper */
2245                 ixgbe_set_phy_power(hw, true);
2246         } else {
2247                 /* Turn on the laser */
2248                 ixgbe_enable_tx_laser(hw);
2249         }
2250
2251         return 0;
2252 }
2253
2254 /*
2255  * Set device link down: disable tx.
2256  */
2257 static int
2258 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2259 {
2260         struct ixgbe_hw *hw =
2261                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2262         if (hw->mac.type == ixgbe_mac_82599EB) {
2263 #ifdef RTE_NIC_BYPASS
2264                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2265                         /* Not suported in bypass mode */
2266                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2267                                      "by device id 0x%x", hw->device_id);
2268                         return -ENOTSUP;
2269                 }
2270 #endif
2271         }
2272
2273         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2274                 /* Turn off the copper */
2275                 ixgbe_set_phy_power(hw, false);
2276         } else {
2277                 /* Turn off the laser */
2278                 ixgbe_disable_tx_laser(hw);
2279         }
2280
2281         return 0;
2282 }
2283
2284 /*
2285  * Reest and stop device.
2286  */
2287 static void
2288 ixgbe_dev_close(struct rte_eth_dev *dev)
2289 {
2290         struct ixgbe_hw *hw =
2291                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2292
2293         PMD_INIT_FUNC_TRACE();
2294
2295         ixgbe_pf_reset_hw(hw);
2296
2297         ixgbe_dev_stop(dev);
2298         hw->adapter_stopped = 1;
2299
2300         ixgbe_dev_free_queues(dev);
2301
2302         ixgbe_disable_pcie_master(hw);
2303
2304         /* reprogram the RAR[0] in case user changed it. */
2305         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2306 }
2307
2308 static void
2309 ixgbe_read_stats_registers(struct ixgbe_hw *hw, struct ixgbe_hw_stats
2310                                                    *hw_stats, uint64_t *total_missed_rx,
2311                                                    uint64_t *total_qbrc, uint64_t *total_qprc,
2312                                                    uint64_t *total_qprdc)
2313 {
2314         uint32_t bprc, lxon, lxoff, total;
2315         unsigned i;
2316
2317         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2318         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2319         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2320         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2321
2322         for (i = 0; i < 8; i++) {
2323                 uint32_t mp;
2324                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2325                 /* global total per queue */
2326                 hw_stats->mpc[i] += mp;
2327                 /* Running comprehensive total for stats display */
2328                 *total_missed_rx += hw_stats->mpc[i];
2329                 if (hw->mac.type == ixgbe_mac_82598EB) {
2330                         hw_stats->rnbc[i] +=
2331                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2332                         hw_stats->pxonrxc[i] +=
2333                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2334                         hw_stats->pxoffrxc[i] +=
2335                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2336                 } else {
2337                         hw_stats->pxonrxc[i] +=
2338                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2339                         hw_stats->pxoffrxc[i] +=
2340                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2341                         hw_stats->pxon2offc[i] +=
2342                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2343                 }
2344                 hw_stats->pxontxc[i] +=
2345                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2346                 hw_stats->pxofftxc[i] +=
2347                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2348         }
2349         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2350                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2351                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2352                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2353                 hw_stats->qbrc[i] +=
2354                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2355                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2356                 hw_stats->qbtc[i] +=
2357                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2358                 *total_qprdc += hw_stats->qprdc[i] +=
2359                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2360
2361                 *total_qprc += hw_stats->qprc[i];
2362                 *total_qbrc += hw_stats->qbrc[i];
2363         }
2364         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2365         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2366         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2367
2368         /* Note that gprc counts missed packets */
2369         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
2370
2371         if (hw->mac.type != ixgbe_mac_82598EB) {
2372                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2373                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2374                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2375                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2376                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2377                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2378                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2379                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2380         } else {
2381                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2382                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2383                 /* 82598 only has a counter in the high register */
2384                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2385                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2386                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2387         }
2388
2389         /*
2390          * Workaround: mprc hardware is incorrectly counting
2391          * broadcasts, so for now we subtract those.
2392          */
2393         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2394         hw_stats->bprc += bprc;
2395         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2396         if (hw->mac.type == ixgbe_mac_82598EB)
2397                 hw_stats->mprc -= bprc;
2398
2399         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2400         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2401         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2402         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2403         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2404         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2405
2406         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2407         hw_stats->lxontxc += lxon;
2408         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2409         hw_stats->lxofftxc += lxoff;
2410         total = lxon + lxoff;
2411
2412         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2413         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2414         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2415         hw_stats->gptc -= total;
2416         hw_stats->mptc -= total;
2417         hw_stats->ptc64 -= total;
2418         hw_stats->gotc -= total * ETHER_MIN_LEN;
2419
2420         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2421         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2422         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2423         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2424         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2425         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2426         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2427         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2428         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2429         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2430         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2431         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2432         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2433         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2434         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2435         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2436         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2437         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2438         /* Only read FCOE on 82599 */
2439         if (hw->mac.type != ixgbe_mac_82598EB) {
2440                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2441                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2442                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2443                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2444                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2445         }
2446
2447         /* Flow Director Stats registers */
2448         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2449         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2450 }
2451
2452 /*
2453  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2454  */
2455 static void
2456 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2457 {
2458         struct ixgbe_hw *hw =
2459                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2460         struct ixgbe_hw_stats *hw_stats =
2461                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2462         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2463         unsigned i;
2464
2465         total_missed_rx = 0;
2466         total_qbrc = 0;
2467         total_qprc = 0;
2468         total_qprdc = 0;
2469
2470         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2471                         &total_qprc, &total_qprdc);
2472
2473         if (stats == NULL)
2474                 return;
2475
2476         /* Fill out the rte_eth_stats statistics structure */
2477         stats->ipackets = total_qprc;
2478         stats->ibytes = total_qbrc;
2479         stats->opackets = hw_stats->gptc;
2480         stats->obytes = hw_stats->gotc;
2481
2482         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2483                 stats->q_ipackets[i] = hw_stats->qprc[i];
2484                 stats->q_opackets[i] = hw_stats->qptc[i];
2485                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2486                 stats->q_obytes[i] = hw_stats->qbtc[i];
2487                 stats->q_errors[i] = hw_stats->qprdc[i];
2488         }
2489
2490         /* Rx Errors */
2491         stats->ierrors  = hw_stats->crcerrs +
2492                           hw_stats->mspdc +
2493                           hw_stats->rlec +
2494                           hw_stats->ruc +
2495                           hw_stats->roc +
2496                           total_missed_rx +
2497                           hw_stats->illerrc +
2498                           hw_stats->errbc +
2499                           hw_stats->xec +
2500                           hw_stats->rfc +
2501                           hw_stats->fccrc +
2502                           hw_stats->fclast;
2503
2504         /* Tx Errors */
2505         stats->oerrors  = 0;
2506 }
2507
2508 static void
2509 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2510 {
2511         struct ixgbe_hw_stats *stats =
2512                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2513
2514         /* HW registers are cleared on read */
2515         ixgbe_dev_stats_get(dev, NULL);
2516
2517         /* Reset software totals */
2518         memset(stats, 0, sizeof(*stats));
2519 }
2520
2521 static int
2522 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2523                                          unsigned n)
2524 {
2525         struct ixgbe_hw *hw =
2526                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2527         struct ixgbe_hw_stats *hw_stats =
2528                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2529         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2530         unsigned i, count = IXGBE_NB_XSTATS;
2531
2532         if (n < count)
2533                 return count;
2534
2535         total_missed_rx = 0;
2536         total_qbrc = 0;
2537         total_qprc = 0;
2538         total_qprdc = 0;
2539
2540         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2541                                    &total_qprc, &total_qprdc);
2542
2543         /* If this is a reset xstats is NULL, and we have cleared the
2544          * registers by reading them.
2545          */
2546         if (!xstats)
2547                 return 0;
2548
2549         /* Extended stats from ixgbe_hw_stats */
2550         count = 0;
2551         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2552                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2553                          rte_ixgbe_stats_strings[i].name);
2554                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2555                                 rte_ixgbe_stats_strings[i].offset);
2556                 count++;
2557         }
2558
2559         /* Per-Q stats, with 8 queues available */
2560         for (i = 0; i < 8; i++) {
2561                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2562                          "rx_q%u_mbuf_allocation_errors", i);
2563                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2564                                 offsetof(struct ixgbe_hw_stats, rnbc[i]));
2565                 count++;
2566
2567                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2568                          "rx_q%u_missed_packets", i);
2569                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2570                                 offsetof(struct ixgbe_hw_stats, mpc[i]));
2571                 count++;
2572
2573                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2574                          "rx_q%u_xon_priority_packets", i);
2575                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2576                                 offsetof(struct ixgbe_hw_stats, pxonrxc[i]));
2577                 count++;
2578
2579                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2580                          "tx_q%u_xon_priority_packets", i);
2581                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2582                                 offsetof(struct ixgbe_hw_stats, pxontxc[i]));
2583                 count++;
2584
2585                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2586                          "rx_q%u_xoff_priority_packets", i);
2587                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2588                                 offsetof(struct ixgbe_hw_stats, pxoffrxc[i]));
2589                 count++;
2590
2591                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2592                          "tx_q%u_xoff_priority_packets", i);
2593                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2594                                 offsetof(struct ixgbe_hw_stats, pxofftxc[i]));
2595                 count++;
2596
2597                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2598                          "xx_q%u_xon_to_xoff_priority_packets", i);
2599                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2600                                 offsetof(struct ixgbe_hw_stats, pxon2offc[i]));
2601                 count++;
2602         }
2603
2604         for (i = 0; i < 16; i++) {
2605                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2606                          "rx_q%u_packets", i);
2607                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2608                                 offsetof(struct ixgbe_hw_stats, qprc[i]));
2609                 count++;
2610
2611                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2612                          "rx_q%u_bytes", i);
2613                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2614                                 offsetof(struct ixgbe_hw_stats, qbrc[i]));
2615                 count++;
2616
2617                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2618                          "tx_q%u_packets", i);
2619                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2620                                 offsetof(struct ixgbe_hw_stats, qptc[i]));
2621                 count++;
2622
2623                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2624                          "tx_q%u_bytes", i);
2625                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2626                                 offsetof(struct ixgbe_hw_stats, qbtc[i]));
2627                 count++;
2628
2629                 snprintf(xstats[count].name, sizeof(xstats[count].name),
2630                          "rx_q%u_dropped", i);
2631                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2632                                 offsetof(struct ixgbe_hw_stats, qprdc[i]));
2633                 count++;
2634         }
2635
2636         return count;
2637 }
2638
2639 static void
2640 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2641 {
2642         struct ixgbe_hw_stats *stats =
2643                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2644
2645         /* HW registers are cleared on read */
2646         ixgbe_dev_xstats_get(dev, NULL, IXGBE_NB_XSTATS);
2647
2648         /* Reset software totals */
2649         memset(stats, 0, sizeof(*stats));
2650 }
2651
2652 static void
2653 ixgbevf_update_stats(struct rte_eth_dev *dev)
2654 {
2655         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2657                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2658
2659         /* Good Rx packet, include VF loopback */
2660         UPDATE_VF_STAT(IXGBE_VFGPRC,
2661             hw_stats->last_vfgprc, hw_stats->vfgprc);
2662
2663         /* Good Rx octets, include VF loopback */
2664         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2665             hw_stats->last_vfgorc, hw_stats->vfgorc);
2666
2667         /* Good Tx packet, include VF loopback */
2668         UPDATE_VF_STAT(IXGBE_VFGPTC,
2669             hw_stats->last_vfgptc, hw_stats->vfgptc);
2670
2671         /* Good Tx octets, include VF loopback */
2672         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2673             hw_stats->last_vfgotc, hw_stats->vfgotc);
2674
2675         /* Rx Multicst Packet */
2676         UPDATE_VF_STAT(IXGBE_VFMPRC,
2677             hw_stats->last_vfmprc, hw_stats->vfmprc);
2678 }
2679
2680 static int
2681 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2682                        unsigned n)
2683 {
2684         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2685                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2686         unsigned i;
2687
2688         if (n < IXGBEVF_NB_XSTATS)
2689                 return IXGBEVF_NB_XSTATS;
2690
2691         ixgbevf_update_stats(dev);
2692
2693         if (!xstats)
2694                 return 0;
2695
2696         /* Extended stats */
2697         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2698                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2699                          "%s", rte_ixgbevf_stats_strings[i].name);
2700                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2701                         rte_ixgbevf_stats_strings[i].offset);
2702         }
2703
2704         return IXGBEVF_NB_XSTATS;
2705 }
2706
2707 static void
2708 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2709 {
2710         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2711                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2712
2713         ixgbevf_update_stats(dev);
2714
2715         if (stats == NULL)
2716                 return;
2717
2718         stats->ipackets = hw_stats->vfgprc;
2719         stats->ibytes = hw_stats->vfgorc;
2720         stats->opackets = hw_stats->vfgptc;
2721         stats->obytes = hw_stats->vfgotc;
2722         stats->imcasts = hw_stats->vfmprc;
2723         /* stats->imcasts should be removed as imcasts is deprecated */
2724 }
2725
2726 static void
2727 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2728 {
2729         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2730                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2731
2732         /* Sync HW register to the last stats */
2733         ixgbevf_dev_stats_get(dev, NULL);
2734
2735         /* reset HW current stats*/
2736         hw_stats->vfgprc = 0;
2737         hw_stats->vfgorc = 0;
2738         hw_stats->vfgptc = 0;
2739         hw_stats->vfgotc = 0;
2740         hw_stats->vfmprc = 0;
2741
2742 }
2743
2744 static void
2745 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2746 {
2747         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2748
2749         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2750         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2751         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2752         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2753         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2754         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2755         dev_info->max_vfs = dev->pci_dev->max_vfs;
2756         if (hw->mac.type == ixgbe_mac_82598EB)
2757                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2758         else
2759                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2760         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2761         dev_info->rx_offload_capa =
2762                 DEV_RX_OFFLOAD_VLAN_STRIP |
2763                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2764                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2765                 DEV_RX_OFFLOAD_TCP_CKSUM;
2766
2767         /*
2768          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2769          * mode.
2770          */
2771         if ((hw->mac.type == ixgbe_mac_82599EB ||
2772              hw->mac.type == ixgbe_mac_X540) &&
2773             !RTE_ETH_DEV_SRIOV(dev).active)
2774                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2775
2776         dev_info->tx_offload_capa =
2777                 DEV_TX_OFFLOAD_VLAN_INSERT |
2778                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2779                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2780                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2781                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2782                 DEV_TX_OFFLOAD_TCP_TSO;
2783
2784         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2785                 .rx_thresh = {
2786                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2787                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2788                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2789                 },
2790                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2791                 .rx_drop_en = 0,
2792         };
2793
2794         dev_info->default_txconf = (struct rte_eth_txconf) {
2795                 .tx_thresh = {
2796                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2797                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2798                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2799                 },
2800                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2801                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2802                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2803                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2804         };
2805
2806         dev_info->rx_desc_lim = rx_desc_lim;
2807         dev_info->tx_desc_lim = tx_desc_lim;
2808
2809         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2810         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2811         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2812 }
2813
2814 static void
2815 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2816                      struct rte_eth_dev_info *dev_info)
2817 {
2818         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2819
2820         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2821         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2822         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2823         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2824         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2825         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2826         dev_info->max_vfs = dev->pci_dev->max_vfs;
2827         if (hw->mac.type == ixgbe_mac_82598EB)
2828                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2829         else
2830                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2831         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2832                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2833                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2834                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2835         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2836                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2837                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2838                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2839                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2840                                 DEV_TX_OFFLOAD_TCP_TSO;
2841
2842         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2843                 .rx_thresh = {
2844                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2845                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2846                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2847                 },
2848                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2849                 .rx_drop_en = 0,
2850         };
2851
2852         dev_info->default_txconf = (struct rte_eth_txconf) {
2853                 .tx_thresh = {
2854                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2855                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2856                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2857                 },
2858                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2859                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2860                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2861                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2862         };
2863
2864         dev_info->rx_desc_lim = rx_desc_lim;
2865         dev_info->tx_desc_lim = tx_desc_lim;
2866 }
2867
2868 /* return 0 means link status changed, -1 means not changed */
2869 static int
2870 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2871 {
2872         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2873         struct rte_eth_link link, old;
2874         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2875         int link_up;
2876         int diag;
2877
2878         link.link_status = 0;
2879         link.link_speed = 0;
2880         link.link_duplex = 0;
2881         memset(&old, 0, sizeof(old));
2882         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2883
2884         hw->mac.get_link_status = true;
2885
2886         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2887         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2888                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2889         else
2890                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2891
2892         if (diag != 0) {
2893                 link.link_speed = ETH_LINK_SPEED_100;
2894                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2895                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2896                 if (link.link_status == old.link_status)
2897                         return -1;
2898                 return 0;
2899         }
2900
2901         if (link_up == 0) {
2902                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2903                 if (link.link_status == old.link_status)
2904                         return -1;
2905                 return 0;
2906         }
2907         link.link_status = 1;
2908         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2909
2910         switch (link_speed) {
2911         default:
2912         case IXGBE_LINK_SPEED_UNKNOWN:
2913                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2914                 link.link_speed = ETH_LINK_SPEED_100;
2915                 break;
2916
2917         case IXGBE_LINK_SPEED_100_FULL:
2918                 link.link_speed = ETH_LINK_SPEED_100;
2919                 break;
2920
2921         case IXGBE_LINK_SPEED_1GB_FULL:
2922                 link.link_speed = ETH_LINK_SPEED_1000;
2923                 break;
2924
2925         case IXGBE_LINK_SPEED_10GB_FULL:
2926                 link.link_speed = ETH_LINK_SPEED_10000;
2927                 break;
2928         }
2929         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2930
2931         if (link.link_status == old.link_status)
2932                 return -1;
2933
2934         return 0;
2935 }
2936
2937 static void
2938 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2939 {
2940         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2941         uint32_t fctrl;
2942
2943         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2944         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2945         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2946 }
2947
2948 static void
2949 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2950 {
2951         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         uint32_t fctrl;
2953
2954         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2955         fctrl &= (~IXGBE_FCTRL_UPE);
2956         if (dev->data->all_multicast == 1)
2957                 fctrl |= IXGBE_FCTRL_MPE;
2958         else
2959                 fctrl &= (~IXGBE_FCTRL_MPE);
2960         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2961 }
2962
2963 static void
2964 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         uint32_t fctrl;
2968
2969         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2970         fctrl |= IXGBE_FCTRL_MPE;
2971         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2972 }
2973
2974 static void
2975 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2976 {
2977         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2978         uint32_t fctrl;
2979
2980         if (dev->data->promiscuous == 1)
2981                 return; /* must remain in all_multicast mode */
2982
2983         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2984         fctrl &= (~IXGBE_FCTRL_MPE);
2985         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2986 }
2987
2988 /**
2989  * It clears the interrupt causes and enables the interrupt.
2990  * It will be called once only during nic initialized.
2991  *
2992  * @param dev
2993  *  Pointer to struct rte_eth_dev.
2994  *
2995  * @return
2996  *  - On success, zero.
2997  *  - On failure, a negative value.
2998  */
2999 static int
3000 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3001 {
3002         struct ixgbe_interrupt *intr =
3003                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3004
3005         ixgbe_dev_link_status_print(dev);
3006         intr->mask |= IXGBE_EICR_LSC;
3007
3008         return 0;
3009 }
3010
3011 /**
3012  * It clears the interrupt causes and enables the interrupt.
3013  * It will be called once only during nic initialized.
3014  *
3015  * @param dev
3016  *  Pointer to struct rte_eth_dev.
3017  *
3018  * @return
3019  *  - On success, zero.
3020  *  - On failure, a negative value.
3021  */
3022 static int
3023 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3024 {
3025         struct ixgbe_interrupt *intr =
3026                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3027
3028         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3029
3030         return 0;
3031 }
3032
3033 /*
3034  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3035  *
3036  * @param dev
3037  *  Pointer to struct rte_eth_dev.
3038  *
3039  * @return
3040  *  - On success, zero.
3041  *  - On failure, a negative value.
3042  */
3043 static int
3044 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3045 {
3046         uint32_t eicr;
3047         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048         struct ixgbe_interrupt *intr =
3049                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3050
3051         /* clear all cause mask */
3052         ixgbe_disable_intr(hw);
3053
3054         /* read-on-clear nic registers here */
3055         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3056         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3057
3058         intr->flags = 0;
3059
3060         /* set flag for async link update */
3061         if (eicr & IXGBE_EICR_LSC)
3062                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3063
3064         if (eicr & IXGBE_EICR_MAILBOX)
3065                 intr->flags |= IXGBE_FLAG_MAILBOX;
3066
3067         return 0;
3068 }
3069
3070 static int
3071 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
3072 {
3073         uint32_t eicr;
3074         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3075         struct ixgbe_interrupt *intr =
3076                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3077
3078         /* clear all cause mask */
3079         ixgbevf_intr_disable(hw);
3080
3081         /* read-on-clear nic registers here */
3082         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
3083         PMD_DRV_LOG(INFO, "eicr %x", eicr);
3084
3085         intr->flags = 0;
3086
3087         /* set flag for async link update */
3088         if (eicr & IXGBE_EICR_LSC)
3089                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3090
3091         return 0;
3092 }
3093
3094 /**
3095  * It gets and then prints the link status.
3096  *
3097  * @param dev
3098  *  Pointer to struct rte_eth_dev.
3099  *
3100  * @return
3101  *  - On success, zero.
3102  *  - On failure, a negative value.
3103  */
3104 static void
3105 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3106 {
3107         struct rte_eth_link link;
3108
3109         memset(&link, 0, sizeof(link));
3110         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3111         if (link.link_status) {
3112                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3113                                         (int)(dev->data->port_id),
3114                                         (unsigned)link.link_speed,
3115                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3116                                         "full-duplex" : "half-duplex");
3117         } else {
3118                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3119                                 (int)(dev->data->port_id));
3120         }
3121         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3122                                 dev->pci_dev->addr.domain,
3123                                 dev->pci_dev->addr.bus,
3124                                 dev->pci_dev->addr.devid,
3125                                 dev->pci_dev->addr.function);
3126 }
3127
3128 /*
3129  * It executes link_update after knowing an interrupt occurred.
3130  *
3131  * @param dev
3132  *  Pointer to struct rte_eth_dev.
3133  *
3134  * @return
3135  *  - On success, zero.
3136  *  - On failure, a negative value.
3137  */
3138 static int
3139 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3140 {
3141         struct ixgbe_interrupt *intr =
3142                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3143         int64_t timeout;
3144         struct rte_eth_link link;
3145         int intr_enable_delay = false;
3146
3147         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3148
3149         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3150                 ixgbe_pf_mbx_process(dev);
3151                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3152         }
3153
3154         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3155                 /* get the link status before link update, for predicting later */
3156                 memset(&link, 0, sizeof(link));
3157                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3158
3159                 ixgbe_dev_link_update(dev, 0);
3160
3161                 /* likely to up */
3162                 if (!link.link_status)
3163                         /* handle it 1 sec later, wait it being stable */
3164                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3165                 /* likely to down */
3166                 else
3167                         /* handle it 4 sec later, wait it being stable */
3168                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3169
3170                 ixgbe_dev_link_status_print(dev);
3171
3172                 intr_enable_delay = true;
3173         }
3174
3175         if (intr_enable_delay) {
3176                 if (rte_eal_alarm_set(timeout * 1000,
3177                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3178                         PMD_DRV_LOG(ERR, "Error setting alarm");
3179         } else {
3180                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3181                 ixgbe_enable_intr(dev);
3182                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3183         }
3184
3185
3186         return 0;
3187 }
3188
3189 static int
3190 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
3191 {
3192         struct ixgbe_hw *hw =
3193                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3194
3195         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3196         ixgbevf_intr_enable(hw);
3197         rte_intr_enable(&dev->pci_dev->intr_handle);
3198         return 0;
3199 }
3200
3201 /**
3202  * Interrupt handler which shall be registered for alarm callback for delayed
3203  * handling specific interrupt to wait for the stable nic state. As the
3204  * NIC interrupt state is not stable for ixgbe after link is just down,
3205  * it needs to wait 4 seconds to get the stable status.
3206  *
3207  * @param handle
3208  *  Pointer to interrupt handle.
3209  * @param param
3210  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3211  *
3212  * @return
3213  *  void
3214  */
3215 static void
3216 ixgbe_dev_interrupt_delayed_handler(void *param)
3217 {
3218         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3219         struct ixgbe_interrupt *intr =
3220                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3221         struct ixgbe_hw *hw =
3222                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3223         uint32_t eicr;
3224
3225         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3226         if (eicr & IXGBE_EICR_MAILBOX)
3227                 ixgbe_pf_mbx_process(dev);
3228
3229         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3230                 ixgbe_dev_link_update(dev, 0);
3231                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3232                 ixgbe_dev_link_status_print(dev);
3233                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3234         }
3235
3236         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3237         ixgbe_enable_intr(dev);
3238         rte_intr_enable(&(dev->pci_dev->intr_handle));
3239 }
3240
3241 /**
3242  * Interrupt handler triggered by NIC  for handling
3243  * specific interrupt.
3244  *
3245  * @param handle
3246  *  Pointer to interrupt handle.
3247  * @param param
3248  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3249  *
3250  * @return
3251  *  void
3252  */
3253 static void
3254 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3255                             void *param)
3256 {
3257         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3258
3259         ixgbe_dev_interrupt_get_status(dev);
3260         ixgbe_dev_interrupt_action(dev);
3261 }
3262
3263 static void
3264 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3265                               void *param)
3266 {
3267         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3268
3269         ixgbevf_dev_interrupt_get_status(dev);
3270         ixgbevf_dev_interrupt_action(dev);
3271 }
3272
3273 static int
3274 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3275 {
3276         struct ixgbe_hw *hw;
3277
3278         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3279         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3280 }
3281
3282 static int
3283 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3284 {
3285         struct ixgbe_hw *hw;
3286
3287         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3289 }
3290
3291 static int
3292 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3293 {
3294         struct ixgbe_hw *hw;
3295         uint32_t mflcn_reg;
3296         uint32_t fccfg_reg;
3297         int rx_pause;
3298         int tx_pause;
3299
3300         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301
3302         fc_conf->pause_time = hw->fc.pause_time;
3303         fc_conf->high_water = hw->fc.high_water[0];
3304         fc_conf->low_water = hw->fc.low_water[0];
3305         fc_conf->send_xon = hw->fc.send_xon;
3306         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3307
3308         /*
3309          * Return rx_pause status according to actual setting of
3310          * MFLCN register.
3311          */
3312         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3313         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3314                 rx_pause = 1;
3315         else
3316                 rx_pause = 0;
3317
3318         /*
3319          * Return tx_pause status according to actual setting of
3320          * FCCFG register.
3321          */
3322         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3323         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3324                 tx_pause = 1;
3325         else
3326                 tx_pause = 0;
3327
3328         if (rx_pause && tx_pause)
3329                 fc_conf->mode = RTE_FC_FULL;
3330         else if (rx_pause)
3331                 fc_conf->mode = RTE_FC_RX_PAUSE;
3332         else if (tx_pause)
3333                 fc_conf->mode = RTE_FC_TX_PAUSE;
3334         else
3335                 fc_conf->mode = RTE_FC_NONE;
3336
3337         return 0;
3338 }
3339
3340 static int
3341 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3342 {
3343         struct ixgbe_hw *hw;
3344         int err;
3345         uint32_t rx_buf_size;
3346         uint32_t max_high_water;
3347         uint32_t mflcn;
3348         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3349                 ixgbe_fc_none,
3350                 ixgbe_fc_rx_pause,
3351                 ixgbe_fc_tx_pause,
3352                 ixgbe_fc_full
3353         };
3354
3355         PMD_INIT_FUNC_TRACE();
3356
3357         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3358         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3359         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3360
3361         /*
3362          * At least reserve one Ethernet frame for watermark
3363          * high_water/low_water in kilo bytes for ixgbe
3364          */
3365         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3366         if ((fc_conf->high_water > max_high_water) ||
3367                 (fc_conf->high_water < fc_conf->low_water)) {
3368                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3369                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3370                 return (-EINVAL);
3371         }
3372
3373         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3374         hw->fc.pause_time     = fc_conf->pause_time;
3375         hw->fc.high_water[0]  = fc_conf->high_water;
3376         hw->fc.low_water[0]   = fc_conf->low_water;
3377         hw->fc.send_xon       = fc_conf->send_xon;
3378         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3379
3380         err = ixgbe_fc_enable(hw);
3381
3382         /* Not negotiated is not an error case */
3383         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3384
3385                 /* check if we want to forward MAC frames - driver doesn't have native
3386                  * capability to do that, so we'll write the registers ourselves */
3387
3388                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3389
3390                 /* set or clear MFLCN.PMCF bit depending on configuration */
3391                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3392                         mflcn |= IXGBE_MFLCN_PMCF;
3393                 else
3394                         mflcn &= ~IXGBE_MFLCN_PMCF;
3395
3396                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3397                 IXGBE_WRITE_FLUSH(hw);
3398
3399                 return 0;
3400         }
3401
3402         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3403         return -EIO;
3404 }
3405
3406 /**
3407  *  ixgbe_pfc_enable_generic - Enable flow control
3408  *  @hw: pointer to hardware structure
3409  *  @tc_num: traffic class number
3410  *  Enable flow control according to the current settings.
3411  */
3412 static int
3413 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3414 {
3415         int ret_val = 0;
3416         uint32_t mflcn_reg, fccfg_reg;
3417         uint32_t reg;
3418         uint32_t fcrtl, fcrth;
3419         uint8_t i;
3420         uint8_t nb_rx_en;
3421
3422         /* Validate the water mark configuration */
3423         if (!hw->fc.pause_time) {
3424                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3425                 goto out;
3426         }
3427
3428         /* Low water mark of zero causes XOFF floods */
3429         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3430                  /* High/Low water can not be 0 */
3431                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3432                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3433                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3434                         goto out;
3435                 }
3436
3437                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3438                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3439                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3440                         goto out;
3441                 }
3442         }
3443         /* Negotiate the fc mode to use */
3444         ixgbe_fc_autoneg(hw);
3445
3446         /* Disable any previous flow control settings */
3447         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3448         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3449
3450         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3451         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3452
3453         switch (hw->fc.current_mode) {
3454         case ixgbe_fc_none:
3455                 /*
3456                  * If the count of enabled RX Priority Flow control >1,
3457                  * and the TX pause can not be disabled
3458                  */
3459                 nb_rx_en = 0;
3460                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3461                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3462                         if (reg & IXGBE_FCRTH_FCEN)
3463                                 nb_rx_en++;
3464                 }
3465                 if (nb_rx_en > 1)
3466                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3467                 break;
3468         case ixgbe_fc_rx_pause:
3469                 /*
3470                  * Rx Flow control is enabled and Tx Flow control is
3471                  * disabled by software override. Since there really
3472                  * isn't a way to advertise that we are capable of RX
3473                  * Pause ONLY, we will advertise that we support both
3474                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3475                  * disable the adapter's ability to send PAUSE frames.
3476                  */
3477                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3478                 /*
3479                  * If the count of enabled RX Priority Flow control >1,
3480                  * and the TX pause can not be disabled
3481                  */
3482                 nb_rx_en = 0;
3483                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3484                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3485                         if (reg & IXGBE_FCRTH_FCEN)
3486                                 nb_rx_en++;
3487                 }
3488                 if (nb_rx_en > 1)
3489                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3490                 break;
3491         case ixgbe_fc_tx_pause:
3492                 /*
3493                  * Tx Flow control is enabled, and Rx Flow control is
3494                  * disabled by software override.
3495                  */
3496                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3497                 break;
3498         case ixgbe_fc_full:
3499                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3500                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3501                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3502                 break;
3503         default:
3504                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3505                 ret_val = IXGBE_ERR_CONFIG;
3506                 goto out;
3507                 break;
3508         }
3509
3510         /* Set 802.3x based flow control settings. */
3511         mflcn_reg |= IXGBE_MFLCN_DPF;
3512         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3513         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3514
3515         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3516         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3517                 hw->fc.high_water[tc_num]) {
3518                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3519                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3520                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3521         } else {
3522                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3523                 /*
3524                  * In order to prevent Tx hangs when the internal Tx
3525                  * switch is enabled we must set the high water mark
3526                  * to the maximum FCRTH value.  This allows the Tx
3527                  * switch to function even under heavy Rx workloads.
3528                  */
3529                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3530         }
3531         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3532
3533         /* Configure pause time (2 TCs per register) */
3534         reg = hw->fc.pause_time * 0x00010001;
3535         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3536                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3537
3538         /* Configure flow control refresh threshold value */
3539         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3540
3541 out:
3542         return ret_val;
3543 }
3544
3545 static int
3546 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3547 {
3548         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3549         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3550
3551         if(hw->mac.type != ixgbe_mac_82598EB) {
3552                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3553         }
3554         return ret_val;
3555 }
3556
3557 static int
3558 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3559 {
3560         int err;
3561         uint32_t rx_buf_size;
3562         uint32_t max_high_water;
3563         uint8_t tc_num;
3564         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3565         struct ixgbe_hw *hw =
3566                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3567         struct ixgbe_dcb_config *dcb_config =
3568                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3569
3570         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3571                 ixgbe_fc_none,
3572                 ixgbe_fc_rx_pause,
3573                 ixgbe_fc_tx_pause,
3574                 ixgbe_fc_full
3575         };
3576
3577         PMD_INIT_FUNC_TRACE();
3578
3579         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3580         tc_num = map[pfc_conf->priority];
3581         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3582         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3583         /*
3584          * At least reserve one Ethernet frame for watermark
3585          * high_water/low_water in kilo bytes for ixgbe
3586          */
3587         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3588         if ((pfc_conf->fc.high_water > max_high_water) ||
3589             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3590                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3591                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3592                 return (-EINVAL);
3593         }
3594
3595         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3596         hw->fc.pause_time = pfc_conf->fc.pause_time;
3597         hw->fc.send_xon = pfc_conf->fc.send_xon;
3598         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3599         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3600
3601         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3602
3603         /* Not negotiated is not an error case */
3604         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3605                 return 0;
3606
3607         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3608         return -EIO;
3609 }
3610
3611 static int
3612 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3613                           struct rte_eth_rss_reta_entry64 *reta_conf,
3614                           uint16_t reta_size)
3615 {
3616         uint8_t i, j, mask;
3617         uint32_t reta, r;
3618         uint16_t idx, shift;
3619         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620         uint16_t sp_reta_size;
3621         uint32_t reta_reg;
3622
3623         PMD_INIT_FUNC_TRACE();
3624
3625         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3626                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3627                         "NIC.");
3628                 return -ENOTSUP;
3629         }
3630
3631         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3632         if (reta_size != sp_reta_size) {
3633                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3634                         "(%d) doesn't match the number hardware can supported "
3635                         "(%d)\n", reta_size, sp_reta_size);
3636                 return -EINVAL;
3637         }
3638
3639         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3640                 idx = i / RTE_RETA_GROUP_SIZE;
3641                 shift = i % RTE_RETA_GROUP_SIZE;
3642                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3643                                                 IXGBE_4_BIT_MASK);
3644                 if (!mask)
3645                         continue;
3646                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3647                 if (mask == IXGBE_4_BIT_MASK)
3648                         r = 0;
3649                 else
3650                         r = IXGBE_READ_REG(hw, reta_reg);
3651                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3652                         if (mask & (0x1 << j))
3653                                 reta |= reta_conf[idx].reta[shift + j] <<
3654                                                         (CHAR_BIT * j);
3655                         else
3656                                 reta |= r & (IXGBE_8_BIT_MASK <<
3657                                                 (CHAR_BIT * j));
3658                 }
3659                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3660         }
3661
3662         return 0;
3663 }
3664
3665 static int
3666 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3667                          struct rte_eth_rss_reta_entry64 *reta_conf,
3668                          uint16_t reta_size)
3669 {
3670         uint8_t i, j, mask;
3671         uint32_t reta;
3672         uint16_t idx, shift;
3673         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3674         uint16_t sp_reta_size;
3675         uint32_t reta_reg;
3676
3677         PMD_INIT_FUNC_TRACE();
3678         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3679         if (reta_size != sp_reta_size) {
3680                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3681                         "(%d) doesn't match the number hardware can supported "
3682                         "(%d)\n", reta_size, sp_reta_size);
3683                 return -EINVAL;
3684         }
3685
3686         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3687                 idx = i / RTE_RETA_GROUP_SIZE;
3688                 shift = i % RTE_RETA_GROUP_SIZE;
3689                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3690                                                 IXGBE_4_BIT_MASK);
3691                 if (!mask)
3692                         continue;
3693
3694                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3695                 reta = IXGBE_READ_REG(hw, reta_reg);
3696                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3697                         if (mask & (0x1 << j))
3698                                 reta_conf[idx].reta[shift + j] =
3699                                         ((reta >> (CHAR_BIT * j)) &
3700                                                 IXGBE_8_BIT_MASK);
3701                 }
3702         }
3703
3704         return 0;
3705 }
3706
3707 static void
3708 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3709                                 uint32_t index, uint32_t pool)
3710 {
3711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3712         uint32_t enable_addr = 1;
3713
3714         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3715 }
3716
3717 static void
3718 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3719 {
3720         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3721
3722         ixgbe_clear_rar(hw, index);
3723 }
3724
3725 static void
3726 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3727 {
3728         ixgbe_remove_rar(dev, 0);
3729
3730         ixgbe_add_rar(dev, addr, 0, 0);
3731 }
3732
3733 static int
3734 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3735 {
3736         uint32_t hlreg0;
3737         uint32_t maxfrs;
3738         struct ixgbe_hw *hw;
3739         struct rte_eth_dev_info dev_info;
3740         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3741
3742         ixgbe_dev_info_get(dev, &dev_info);
3743
3744         /* check that mtu is within the allowed range */
3745         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3746                 return -EINVAL;
3747
3748         /* refuse mtu that requires the support of scattered packets when this
3749          * feature has not been enabled before. */
3750         if (!dev->data->scattered_rx &&
3751             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3752              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3753                 return -EINVAL;
3754
3755         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3756         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3757
3758         /* switch to jumbo mode if needed */
3759         if (frame_size > ETHER_MAX_LEN) {
3760                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3761                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3762         } else {
3763                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3764                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3765         }
3766         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3767
3768         /* update max frame size */
3769         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3770
3771         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3772         maxfrs &= 0x0000FFFF;
3773         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3774         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3775
3776         return 0;
3777 }
3778
3779 /*
3780  * Virtual Function operations
3781  */
3782 static void
3783 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3784 {
3785         PMD_INIT_FUNC_TRACE();
3786
3787         /* Clear interrupt mask to stop from interrupts being generated */
3788         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3789
3790         IXGBE_WRITE_FLUSH(hw);
3791 }
3792
3793 static void
3794 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3795 {
3796         PMD_INIT_FUNC_TRACE();
3797
3798         /* VF enable interrupt autoclean */
3799         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3800         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3801         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3802
3803         IXGBE_WRITE_FLUSH(hw);
3804 }
3805
3806 static int
3807 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3808 {
3809         struct rte_eth_conf* conf = &dev->data->dev_conf;
3810         struct ixgbe_adapter *adapter =
3811                         (struct ixgbe_adapter *)dev->data->dev_private;
3812
3813         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3814                      dev->data->port_id);
3815
3816         /*
3817          * VF has no ability to enable/disable HW CRC
3818          * Keep the persistent behavior the same as Host PF
3819          */
3820 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3821         if (!conf->rxmode.hw_strip_crc) {
3822                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3823                 conf->rxmode.hw_strip_crc = 1;
3824         }
3825 #else
3826         if (conf->rxmode.hw_strip_crc) {
3827                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3828                 conf->rxmode.hw_strip_crc = 0;
3829         }
3830 #endif
3831
3832         /*
3833          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3834          * allocation or vector Rx preconditions we will reset it.
3835          */
3836         adapter->rx_bulk_alloc_allowed = true;
3837         adapter->rx_vec_allowed = true;
3838
3839         return 0;
3840 }
3841
3842 static int
3843 ixgbevf_dev_start(struct rte_eth_dev *dev)
3844 {
3845         struct ixgbe_hw *hw =
3846                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3847         uint32_t intr_vector = 0;
3848         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3849
3850         int err, mask = 0;
3851
3852         PMD_INIT_FUNC_TRACE();
3853
3854         hw->mac.ops.reset_hw(hw);
3855         hw->mac.get_link_status = true;
3856
3857         /* negotiate mailbox API version to use with the PF. */
3858         ixgbevf_negotiate_api(hw);
3859
3860         ixgbevf_dev_tx_init(dev);
3861
3862         /* This can fail when allocating mbufs for descriptor rings */
3863         err = ixgbevf_dev_rx_init(dev);
3864         if (err) {
3865                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3866                 ixgbe_dev_clear_queues(dev);
3867                 return err;
3868         }
3869
3870         /* Set vfta */
3871         ixgbevf_set_vfta_all(dev,1);
3872
3873         /* Set HW strip */
3874         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3875                 ETH_VLAN_EXTEND_MASK;
3876         ixgbevf_vlan_offload_set(dev, mask);
3877
3878         ixgbevf_dev_rxtx_start(dev);
3879
3880         /* check and configure queue intr-vector mapping */
3881         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3882                 intr_vector = dev->data->nb_rx_queues;
3883                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3884                         return -1;
3885         }
3886
3887         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3888                 intr_handle->intr_vec =
3889                         rte_zmalloc("intr_vec",
3890                                     dev->data->nb_rx_queues * sizeof(int), 0);
3891                 if (intr_handle->intr_vec == NULL) {
3892                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3893                                      " intr_vec\n", dev->data->nb_rx_queues);
3894                         return -ENOMEM;
3895                 }
3896         }
3897         ixgbevf_configure_msix(dev);
3898
3899         if (dev->data->dev_conf.intr_conf.lsc != 0) {
3900                 if (rte_intr_allow_others(intr_handle))
3901                         rte_intr_callback_register(intr_handle,
3902                                         ixgbevf_dev_interrupt_handler,
3903                                         (void *)dev);
3904                 else
3905                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
3906                                      " no intr multiplex\n");
3907         }
3908
3909         rte_intr_enable(intr_handle);
3910
3911         /* Re-enable interrupt for VF */
3912         ixgbevf_intr_enable(hw);
3913
3914         return 0;
3915 }
3916
3917 static void
3918 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3919 {
3920         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3921         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3922
3923         PMD_INIT_FUNC_TRACE();
3924
3925         hw->adapter_stopped = 1;
3926         ixgbe_stop_adapter(hw);
3927
3928         /*
3929           * Clear what we set, but we still keep shadow_vfta to
3930           * restore after device starts
3931           */
3932         ixgbevf_set_vfta_all(dev,0);
3933
3934         /* Clear stored conf */
3935         dev->data->scattered_rx = 0;
3936
3937         ixgbe_dev_clear_queues(dev);
3938
3939         /* disable intr eventfd mapping */
3940         rte_intr_disable(intr_handle);
3941
3942         /* Clean datapath event and queue/vec mapping */
3943         rte_intr_efd_disable(intr_handle);
3944         if (intr_handle->intr_vec != NULL) {
3945                 rte_free(intr_handle->intr_vec);
3946                 intr_handle->intr_vec = NULL;
3947         }
3948 }
3949
3950 static void
3951 ixgbevf_dev_close(struct rte_eth_dev *dev)
3952 {
3953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3954         struct rte_pci_device *pci_dev;
3955
3956         PMD_INIT_FUNC_TRACE();
3957
3958         ixgbe_reset_hw(hw);
3959
3960         ixgbevf_dev_stop(dev);
3961
3962         ixgbe_dev_free_queues(dev);
3963
3964         /* reprogram the RAR[0] in case user changed it. */
3965         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3966
3967         pci_dev = dev->pci_dev;
3968         if (pci_dev->intr_handle.intr_vec) {
3969                 rte_free(pci_dev->intr_handle.intr_vec);
3970                 pci_dev->intr_handle.intr_vec = NULL;
3971         }
3972 }
3973
3974 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3975 {
3976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3977         struct ixgbe_vfta * shadow_vfta =
3978                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3979         int i = 0, j = 0, vfta = 0, mask = 1;
3980
3981         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3982                 vfta = shadow_vfta->vfta[i];
3983                 if(vfta){
3984                         mask = 1;
3985                         for (j = 0; j < 32; j++){
3986                                 if(vfta & mask)
3987                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3988                                 mask<<=1;
3989                         }
3990                 }
3991         }
3992
3993 }
3994
3995 static int
3996 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3997 {
3998         struct ixgbe_hw *hw =
3999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4000         struct ixgbe_vfta * shadow_vfta =
4001                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4002         uint32_t vid_idx = 0;
4003         uint32_t vid_bit = 0;
4004         int ret = 0;
4005
4006         PMD_INIT_FUNC_TRACE();
4007
4008         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4009         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
4010         if(ret){
4011                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4012                 return ret;
4013         }
4014         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4015         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4016
4017         /* Save what we set and retore it after device reset */
4018         if (on)
4019                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4020         else
4021                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4022
4023         return 0;
4024 }
4025
4026 static void
4027 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4028 {
4029         struct ixgbe_hw *hw =
4030                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031         uint32_t ctrl;
4032
4033         PMD_INIT_FUNC_TRACE();
4034
4035         if(queue >= hw->mac.max_rx_queues)
4036                 return;
4037
4038         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4039         if(on)
4040                 ctrl |= IXGBE_RXDCTL_VME;
4041         else
4042                 ctrl &= ~IXGBE_RXDCTL_VME;
4043         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4044
4045         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
4046 }
4047
4048 static void
4049 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4050 {
4051         struct ixgbe_hw *hw =
4052                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4053         uint16_t i;
4054         int on = 0;
4055
4056         /* VF function only support hw strip feature, others are not support */
4057         if(mask & ETH_VLAN_STRIP_MASK){
4058                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4059
4060                 for(i=0; i < hw->mac.max_rx_queues; i++)
4061                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4062         }
4063 }
4064
4065 static int
4066 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4067 {
4068         uint32_t reg_val;
4069
4070         /* we only need to do this if VMDq is enabled */
4071         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4072         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4073                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4074                 return (-1);
4075         }
4076
4077         return 0;
4078 }
4079
4080 static uint32_t
4081 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4082 {
4083         uint32_t vector = 0;
4084         switch (hw->mac.mc_filter_type) {
4085         case 0:   /* use bits [47:36] of the address */
4086                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4087                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4088                 break;
4089         case 1:   /* use bits [46:35] of the address */
4090                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4091                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4092                 break;
4093         case 2:   /* use bits [45:34] of the address */
4094                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4095                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4096                 break;
4097         case 3:   /* use bits [43:32] of the address */
4098                 vector = ((uc_addr->addr_bytes[4]) |
4099                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4100                 break;
4101         default:  /* Invalid mc_filter_type */
4102                 break;
4103         }
4104
4105         /* vector can only be 12-bits or boundary will be exceeded */
4106         vector &= 0xFFF;
4107         return vector;
4108 }
4109
4110 static int
4111 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4112                                uint8_t on)
4113 {
4114         uint32_t vector;
4115         uint32_t uta_idx;
4116         uint32_t reg_val;
4117         uint32_t uta_shift;
4118         uint32_t rc;
4119         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4120         const uint32_t ixgbe_uta_bit_shift = 5;
4121         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4122         const uint32_t bit1 = 0x1;
4123
4124         struct ixgbe_hw *hw =
4125                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct ixgbe_uta_info *uta_info =
4127                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4128
4129         /* The UTA table only exists on 82599 hardware and newer */
4130         if (hw->mac.type < ixgbe_mac_82599EB)
4131                 return (-ENOTSUP);
4132
4133         vector = ixgbe_uta_vector(hw,mac_addr);
4134         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4135         uta_shift = vector & ixgbe_uta_bit_mask;
4136
4137         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4138         if(rc == on)
4139                 return 0;
4140
4141         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4142         if (on) {
4143                 uta_info->uta_in_use++;
4144                 reg_val |= (bit1 << uta_shift);
4145                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4146         } else {
4147                 uta_info->uta_in_use--;
4148                 reg_val &= ~(bit1 << uta_shift);
4149                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4150         }
4151
4152         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4153
4154         if (uta_info->uta_in_use > 0)
4155                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4156                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4157         else
4158                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4159
4160         return 0;
4161 }
4162
4163 static int
4164 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4165 {
4166         int i;
4167         struct ixgbe_hw *hw =
4168                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4169         struct ixgbe_uta_info *uta_info =
4170                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4171
4172         /* The UTA table only exists on 82599 hardware and newer */
4173         if (hw->mac.type < ixgbe_mac_82599EB)
4174                 return (-ENOTSUP);
4175
4176         if(on) {
4177                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4178                         uta_info->uta_shadow[i] = ~0;
4179                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4180                 }
4181         } else {
4182                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4183                         uta_info->uta_shadow[i] = 0;
4184                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4185                 }
4186         }
4187         return 0;
4188
4189 }
4190
4191 uint32_t
4192 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4193 {
4194         uint32_t new_val = orig_val;
4195
4196         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4197                 new_val |= IXGBE_VMOLR_AUPE;
4198         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4199                 new_val |= IXGBE_VMOLR_ROMPE;
4200         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4201                 new_val |= IXGBE_VMOLR_ROPE;
4202         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4203                 new_val |= IXGBE_VMOLR_BAM;
4204         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4205                 new_val |= IXGBE_VMOLR_MPE;
4206
4207         return new_val;
4208 }
4209
4210 static int
4211 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4212                                uint16_t rx_mask, uint8_t on)
4213 {
4214         int val = 0;
4215
4216         struct ixgbe_hw *hw =
4217                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4218         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4219
4220         if (hw->mac.type == ixgbe_mac_82598EB) {
4221                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4222                              " on 82599 hardware and newer");
4223                 return (-ENOTSUP);
4224         }
4225         if (ixgbe_vmdq_mode_check(hw) < 0)
4226                 return (-ENOTSUP);
4227
4228         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4229
4230         if (on)
4231                 vmolr |= val;
4232         else
4233                 vmolr &= ~val;
4234
4235         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4236
4237         return 0;
4238 }
4239
4240 static int
4241 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4242 {
4243         uint32_t reg,addr;
4244         uint32_t val;
4245         const uint8_t bit1 = 0x1;
4246
4247         struct ixgbe_hw *hw =
4248                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4249
4250         if (ixgbe_vmdq_mode_check(hw) < 0)
4251                 return (-ENOTSUP);
4252
4253         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4254         reg = IXGBE_READ_REG(hw, addr);
4255         val = bit1 << pool;
4256
4257         if (on)
4258                 reg |= val;
4259         else
4260                 reg &= ~val;
4261
4262         IXGBE_WRITE_REG(hw, addr,reg);
4263
4264         return 0;
4265 }
4266
4267 static int
4268 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4269 {
4270         uint32_t reg,addr;
4271         uint32_t val;
4272         const uint8_t bit1 = 0x1;
4273
4274         struct ixgbe_hw *hw =
4275                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276
4277         if (ixgbe_vmdq_mode_check(hw) < 0)
4278                 return (-ENOTSUP);
4279
4280         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4281         reg = IXGBE_READ_REG(hw, addr);
4282         val = bit1 << pool;
4283
4284         if (on)
4285                 reg |= val;
4286         else
4287                 reg &= ~val;
4288
4289         IXGBE_WRITE_REG(hw, addr,reg);
4290
4291         return 0;
4292 }
4293
4294 static int
4295 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4296                         uint64_t pool_mask, uint8_t vlan_on)
4297 {
4298         int ret = 0;
4299         uint16_t pool_idx;
4300         struct ixgbe_hw *hw =
4301                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4302
4303         if (ixgbe_vmdq_mode_check(hw) < 0)
4304                 return (-ENOTSUP);
4305         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4306                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4307                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4308                         if (ret < 0)
4309                                 return ret;
4310         }
4311
4312         return ret;
4313 }
4314
4315 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4316 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4317 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4318 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4319 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4320         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4321         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4322
4323 static int
4324 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4325                         struct rte_eth_mirror_conf *mirror_conf,
4326                         uint8_t rule_id, uint8_t on)
4327 {
4328         uint32_t mr_ctl,vlvf;
4329         uint32_t mp_lsb = 0;
4330         uint32_t mv_msb = 0;
4331         uint32_t mv_lsb = 0;
4332         uint32_t mp_msb = 0;
4333         uint8_t i = 0;
4334         int reg_index = 0;
4335         uint64_t vlan_mask = 0;
4336
4337         const uint8_t pool_mask_offset = 32;
4338         const uint8_t vlan_mask_offset = 32;
4339         const uint8_t dst_pool_offset = 8;
4340         const uint8_t rule_mr_offset  = 4;
4341         const uint8_t mirror_rule_mask= 0x0F;
4342
4343         struct ixgbe_mirror_info *mr_info =
4344                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4345         struct ixgbe_hw *hw =
4346                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4347         uint8_t mirror_type = 0;
4348
4349         if (ixgbe_vmdq_mode_check(hw) < 0)
4350                 return -ENOTSUP;
4351
4352         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4353                 return -EINVAL;
4354
4355         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4356                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4357                         mirror_conf->rule_type);
4358                 return -EINVAL;
4359         }
4360
4361         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4362                 mirror_type |= IXGBE_MRCTL_VLME;
4363                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4364                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4365                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4366                                 /* search vlan id related pool vlan filter index */
4367                                 reg_index = ixgbe_find_vlvf_slot(hw,
4368                                                 mirror_conf->vlan.vlan_id[i]);
4369                                 if(reg_index < 0)
4370                                         return -EINVAL;
4371                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4372                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4373                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4374                                       mirror_conf->vlan.vlan_id[i]))
4375                                         vlan_mask |= (1ULL << reg_index);
4376                                 else
4377                                         return -EINVAL;
4378                         }
4379                 }
4380
4381                 if (on) {
4382                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4383                         mv_msb = vlan_mask >> vlan_mask_offset;
4384
4385                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4386                                                 mirror_conf->vlan.vlan_mask;
4387                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4388                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4389                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4390                                                 mirror_conf->vlan.vlan_id[i];
4391                         }
4392                 } else {
4393                         mv_lsb = 0;
4394                         mv_msb = 0;
4395                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4396                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4397                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4398                 }
4399         }
4400
4401         /*
4402          * if enable pool mirror, write related pool mask register,if disable
4403          * pool mirror, clear PFMRVM register
4404          */
4405         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4406                 mirror_type |= IXGBE_MRCTL_VPME;
4407                 if (on) {
4408                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4409                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4410                         mr_info->mr_conf[rule_id].pool_mask =
4411                                         mirror_conf->pool_mask;
4412
4413                 } else {
4414                         mp_lsb = 0;
4415                         mp_msb = 0;
4416                         mr_info->mr_conf[rule_id].pool_mask = 0;
4417                 }
4418         }
4419         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4420                 mirror_type |= IXGBE_MRCTL_UPME;
4421         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4422                 mirror_type |= IXGBE_MRCTL_DPME;
4423
4424         /* read  mirror control register and recalculate it */
4425         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4426
4427         if (on) {
4428                 mr_ctl |= mirror_type;
4429                 mr_ctl &= mirror_rule_mask;
4430                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4431         } else
4432                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4433
4434         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4435         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4436
4437         /* write mirrror control  register */
4438         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4439
4440         /* write pool mirrror control  register */
4441         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4442                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4443                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4444                                 mp_msb);
4445         }
4446         /* write VLAN mirrror control  register */
4447         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4448                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4449                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4450                                 mv_msb);
4451         }
4452
4453         return 0;
4454 }
4455
4456 static int
4457 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4458 {
4459         int mr_ctl = 0;
4460         uint32_t lsb_val = 0;
4461         uint32_t msb_val = 0;
4462         const uint8_t rule_mr_offset = 4;
4463
4464         struct ixgbe_hw *hw =
4465                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466         struct ixgbe_mirror_info *mr_info =
4467                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4468
4469         if (ixgbe_vmdq_mode_check(hw) < 0)
4470                 return (-ENOTSUP);
4471
4472         memset(&mr_info->mr_conf[rule_id], 0,
4473                 sizeof(struct rte_eth_mirror_conf));
4474
4475         /* clear PFVMCTL register */
4476         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4477
4478         /* clear pool mask register */
4479         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4480         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4481
4482         /* clear vlan mask register */
4483         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4484         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4485
4486         return 0;
4487 }
4488
4489 static int
4490 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4491 {
4492         uint32_t mask;
4493         struct ixgbe_hw *hw =
4494                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4495
4496         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4497         mask |= (1 << IXGBE_MISC_VEC_ID);
4498         RTE_SET_USED(queue_id);
4499         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4500
4501         rte_intr_enable(&dev->pci_dev->intr_handle);
4502
4503         return 0;
4504 }
4505
4506 static int
4507 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4508 {
4509         uint32_t mask;
4510         struct ixgbe_hw *hw =
4511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512
4513         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4514         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4515         RTE_SET_USED(queue_id);
4516         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4523 {
4524         uint32_t mask;
4525         struct ixgbe_hw *hw =
4526                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         struct ixgbe_interrupt *intr =
4528                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4529
4530         if (queue_id < 16) {
4531                 ixgbe_disable_intr(hw);
4532                 intr->mask |= (1 << queue_id);
4533                 ixgbe_enable_intr(dev);
4534         } else if (queue_id < 32) {
4535                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4536                 mask &= (1 << queue_id);
4537                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4538         } else if (queue_id < 64) {
4539                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4540                 mask &= (1 << (queue_id - 32));
4541                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4542         }
4543         rte_intr_enable(&dev->pci_dev->intr_handle);
4544
4545         return 0;
4546 }
4547
4548 static int
4549 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4550 {
4551         uint32_t mask;
4552         struct ixgbe_hw *hw =
4553                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         struct ixgbe_interrupt *intr =
4555                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4556
4557         if (queue_id < 16) {
4558                 ixgbe_disable_intr(hw);
4559                 intr->mask &= ~(1 << queue_id);
4560                 ixgbe_enable_intr(dev);
4561         } else if (queue_id < 32) {
4562                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4563                 mask &= ~(1 << queue_id);
4564                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4565         } else if (queue_id < 64) {
4566                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4567                 mask &= ~(1 << (queue_id - 32));
4568                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4569         }
4570
4571         return 0;
4572 }
4573
4574 static void
4575 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4576                      uint8_t queue, uint8_t msix_vector)
4577 {
4578         uint32_t tmp, idx;
4579
4580         if (direction == -1) {
4581                 /* other causes */
4582                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4583                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4584                 tmp &= ~0xFF;
4585                 tmp |= msix_vector;
4586                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4587         } else {
4588                 /* rx or tx cause */
4589                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4590                 idx = ((16 * (queue & 1)) + (8 * direction));
4591                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4592                 tmp &= ~(0xFF << idx);
4593                 tmp |= (msix_vector << idx);
4594                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4595         }
4596 }
4597
4598 /**
4599  * set the IVAR registers, mapping interrupt causes to vectors
4600  * @param hw
4601  *  pointer to ixgbe_hw struct
4602  * @direction
4603  *  0 for Rx, 1 for Tx, -1 for other causes
4604  * @queue
4605  *  queue to map the corresponding interrupt to
4606  * @msix_vector
4607  *  the vector to map to the corresponding queue
4608  */
4609 static void
4610 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4611                    uint8_t queue, uint8_t msix_vector)
4612 {
4613         uint32_t tmp, idx;
4614
4615         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4616         if (hw->mac.type == ixgbe_mac_82598EB) {
4617                 if (direction == -1)
4618                         direction = 0;
4619                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4620                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4621                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4622                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4623                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4624         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4625                         (hw->mac.type == ixgbe_mac_X540)) {
4626                 if (direction == -1) {
4627                         /* other causes */
4628                         idx = ((queue & 1) * 8);
4629                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4630                         tmp &= ~(0xFF << idx);
4631                         tmp |= (msix_vector << idx);
4632                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4633                 } else {
4634                         /* rx or tx causes */
4635                         idx = ((16 * (queue & 1)) + (8 * direction));
4636                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4637                         tmp &= ~(0xFF << idx);
4638                         tmp |= (msix_vector << idx);
4639                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4640                 }
4641         }
4642 }
4643
4644 static void
4645 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4646 {
4647         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4648         struct ixgbe_hw *hw =
4649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4650         uint32_t q_idx;
4651         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4652
4653         /* won't configure msix register if no mapping is done
4654          * between intr vector and event fd.
4655          */
4656         if (!rte_intr_dp_is_en(intr_handle))
4657                 return;
4658
4659         /* Configure all RX queues of VF */
4660         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4661                 /* Force all queue use vector 0,
4662                  * as IXGBE_VF_MAXMSIVECOTR = 1
4663                  */
4664                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4665                 intr_handle->intr_vec[q_idx] = vector_idx;
4666         }
4667
4668         /* Configure VF Rx queue ivar */
4669         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4670 }
4671
4672 /**
4673  * Sets up the hardware to properly generate MSI-X interrupts
4674  * @hw
4675  *  board private structure
4676  */
4677 static void
4678 ixgbe_configure_msix(struct rte_eth_dev *dev)
4679 {
4680         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4681         struct ixgbe_hw *hw =
4682                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4683         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4684         uint32_t vec = IXGBE_MISC_VEC_ID;
4685         uint32_t mask;
4686         uint32_t gpie;
4687
4688         /* won't configure msix register if no mapping is done
4689          * between intr vector and event fd
4690          */
4691         if (!rte_intr_dp_is_en(intr_handle))
4692                 return;
4693
4694         if (rte_intr_allow_others(intr_handle))
4695                 vec = base = IXGBE_RX_VEC_START;
4696
4697         /* setup GPIE for MSI-x mode */
4698         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4699         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4700                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4701         /* auto clearing and auto setting corresponding bits in EIMS
4702          * when MSI-X interrupt is triggered
4703          */
4704         if (hw->mac.type == ixgbe_mac_82598EB) {
4705                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4706         } else {
4707                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4708                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4709         }
4710         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4711
4712         /* Populate the IVAR table and set the ITR values to the
4713          * corresponding register.
4714          */
4715         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4716              queue_id++) {
4717                 /* by default, 1:1 mapping */
4718                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4719                 intr_handle->intr_vec[queue_id] = vec;
4720                 if (vec < base + intr_handle->nb_efd - 1)
4721                         vec++;
4722         }
4723
4724         switch (hw->mac.type) {
4725         case ixgbe_mac_82598EB:
4726                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4727                                    IXGBE_MISC_VEC_ID);
4728                 break;
4729         case ixgbe_mac_82599EB:
4730         case ixgbe_mac_X540:
4731                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4732                 break;
4733         default:
4734                 break;
4735         }
4736         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4737                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4738
4739         /* set up to autoclear timer, and the vectors */
4740         mask = IXGBE_EIMS_ENABLE_MASK;
4741         mask &= ~(IXGBE_EIMS_OTHER |
4742                   IXGBE_EIMS_MAILBOX |
4743                   IXGBE_EIMS_LSC);
4744
4745         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4746 }
4747
4748 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4749         uint16_t queue_idx, uint16_t tx_rate)
4750 {
4751         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4752         uint32_t rf_dec, rf_int;
4753         uint32_t bcnrc_val;
4754         uint16_t link_speed = dev->data->dev_link.link_speed;
4755
4756         if (queue_idx >= hw->mac.max_tx_queues)
4757                 return -EINVAL;
4758
4759         if (tx_rate != 0) {
4760                 /* Calculate the rate factor values to set */
4761                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4762                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4763                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4764
4765                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4766                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4767                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4768                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4769         } else {
4770                 bcnrc_val = 0;
4771         }
4772
4773         /*
4774          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4775          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4776          * set as 0x4.
4777          */
4778         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4779                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4780                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4781                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4782                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4783         else
4784                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4785                         IXGBE_MMW_SIZE_DEFAULT);
4786
4787         /* Set RTTBCNRC of queue X */
4788         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4789         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4790         IXGBE_WRITE_FLUSH(hw);
4791
4792         return 0;
4793 }
4794
4795 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4796         uint16_t tx_rate, uint64_t q_msk)
4797 {
4798         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4799         struct ixgbe_vf_info *vfinfo =
4800                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4801         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4802         uint32_t queue_stride =
4803                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4804         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4805         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4806         uint16_t total_rate = 0;
4807
4808         if (queue_end >= hw->mac.max_tx_queues)
4809                 return -EINVAL;
4810
4811         if (vfinfo != NULL) {
4812                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4813                         if (vf_idx == vf)
4814                                 continue;
4815                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4816                                 idx++)
4817                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4818                 }
4819         } else
4820                 return -EINVAL;
4821
4822         /* Store tx_rate for this vf. */
4823         for (idx = 0; idx < nb_q_per_pool; idx++) {
4824                 if (((uint64_t)0x1 << idx) & q_msk) {
4825                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4826                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4827                         total_rate += tx_rate;
4828                 }
4829         }
4830
4831         if (total_rate > dev->data->dev_link.link_speed) {
4832                 /*
4833                  * Reset stored TX rate of the VF if it causes exceed
4834                  * link speed.
4835                  */
4836                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4837                 return -EINVAL;
4838         }
4839
4840         /* Set RTTBCNRC of each queue/pool for vf X  */
4841         for (; queue_idx <= queue_end; queue_idx++) {
4842                 if (0x1 & q_msk)
4843                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4844                 q_msk = q_msk >> 1;
4845         }
4846
4847         return 0;
4848 }
4849
4850 static void
4851 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4852                      __attribute__((unused)) uint32_t index,
4853                      __attribute__((unused)) uint32_t pool)
4854 {
4855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4856         int diag;
4857
4858         /*
4859          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4860          * operation. Trap this case to avoid exhausting the [very limited]
4861          * set of PF resources used to store VF MAC addresses.
4862          */
4863         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4864                 return;
4865         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4866         if (diag == 0)
4867                 return;
4868         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4869 }
4870
4871 static void
4872 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4873 {
4874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4876         struct ether_addr *mac_addr;
4877         uint32_t i;
4878         int diag;
4879
4880         /*
4881          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4882          * not support the deletion of a given MAC address.
4883          * Instead, it imposes to delete all MAC addresses, then to add again
4884          * all MAC addresses with the exception of the one to be deleted.
4885          */
4886         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4887
4888         /*
4889          * Add again all MAC addresses, with the exception of the deleted one
4890          * and of the permanent MAC address.
4891          */
4892         for (i = 0, mac_addr = dev->data->mac_addrs;
4893              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4894                 /* Skip the deleted MAC address */
4895                 if (i == index)
4896                         continue;
4897                 /* Skip NULL MAC addresses */
4898                 if (is_zero_ether_addr(mac_addr))
4899                         continue;
4900                 /* Skip the permanent MAC address */
4901                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4902                         continue;
4903                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4904                 if (diag != 0)
4905                         PMD_DRV_LOG(ERR,
4906                                     "Adding again MAC address "
4907                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4908                                     "diag=%d",
4909                                     mac_addr->addr_bytes[0],
4910                                     mac_addr->addr_bytes[1],
4911                                     mac_addr->addr_bytes[2],
4912                                     mac_addr->addr_bytes[3],
4913                                     mac_addr->addr_bytes[4],
4914                                     mac_addr->addr_bytes[5],
4915                                     diag);
4916         }
4917 }
4918
4919 static void
4920 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4921 {
4922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4923
4924         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4925 }
4926
4927 #define MAC_TYPE_FILTER_SUP(type)    do {\
4928         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4929                 (type) != ixgbe_mac_X550)\
4930                 return -ENOTSUP;\
4931 } while (0)
4932
4933 static int
4934 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4935                         struct rte_eth_syn_filter *filter,
4936                         bool add)
4937 {
4938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         uint32_t synqf;
4940
4941         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4942                 return -EINVAL;
4943
4944         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4945
4946         if (add) {
4947                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4948                         return -EINVAL;
4949                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4950                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4951
4952                 if (filter->hig_pri)
4953                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4954                 else
4955                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4956         } else {
4957                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4958                         return -ENOENT;
4959                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4960         }
4961         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4962         IXGBE_WRITE_FLUSH(hw);
4963         return 0;
4964 }
4965
4966 static int
4967 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4968                         struct rte_eth_syn_filter *filter)
4969 {
4970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4971         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4972
4973         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4974                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4975                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4976                 return 0;
4977         }
4978         return -ENOENT;
4979 }
4980
4981 static int
4982 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4983                         enum rte_filter_op filter_op,
4984                         void *arg)
4985 {
4986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4987         int ret;
4988
4989         MAC_TYPE_FILTER_SUP(hw->mac.type);
4990
4991         if (filter_op == RTE_ETH_FILTER_NOP)
4992                 return 0;
4993
4994         if (arg == NULL) {
4995                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4996                             filter_op);
4997                 return -EINVAL;
4998         }
4999
5000         switch (filter_op) {
5001         case RTE_ETH_FILTER_ADD:
5002                 ret = ixgbe_syn_filter_set(dev,
5003                                 (struct rte_eth_syn_filter *)arg,
5004                                 TRUE);
5005                 break;
5006         case RTE_ETH_FILTER_DELETE:
5007                 ret = ixgbe_syn_filter_set(dev,
5008                                 (struct rte_eth_syn_filter *)arg,
5009                                 FALSE);
5010                 break;
5011         case RTE_ETH_FILTER_GET:
5012                 ret = ixgbe_syn_filter_get(dev,
5013                                 (struct rte_eth_syn_filter *)arg);
5014                 break;
5015         default:
5016                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5017                 ret = -EINVAL;
5018                 break;
5019         }
5020
5021         return ret;
5022 }
5023
5024
5025 static inline enum ixgbe_5tuple_protocol
5026 convert_protocol_type(uint8_t protocol_value)
5027 {
5028         if (protocol_value == IPPROTO_TCP)
5029                 return IXGBE_FILTER_PROTOCOL_TCP;
5030         else if (protocol_value == IPPROTO_UDP)
5031                 return IXGBE_FILTER_PROTOCOL_UDP;
5032         else if (protocol_value == IPPROTO_SCTP)
5033                 return IXGBE_FILTER_PROTOCOL_SCTP;
5034         else
5035                 return IXGBE_FILTER_PROTOCOL_NONE;
5036 }
5037
5038 /*
5039  * add a 5tuple filter
5040  *
5041  * @param
5042  * dev: Pointer to struct rte_eth_dev.
5043  * index: the index the filter allocates.
5044  * filter: ponter to the filter that will be added.
5045  * rx_queue: the queue id the filter assigned to.
5046  *
5047  * @return
5048  *    - On success, zero.
5049  *    - On failure, a negative value.
5050  */
5051 static int
5052 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5053                         struct ixgbe_5tuple_filter *filter)
5054 {
5055         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5056         struct ixgbe_filter_info *filter_info =
5057                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5058         int i, idx, shift;
5059         uint32_t ftqf, sdpqf;
5060         uint32_t l34timir = 0;
5061         uint8_t mask = 0xff;
5062
5063         /*
5064          * look for an unused 5tuple filter index,
5065          * and insert the filter to list.
5066          */
5067         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5068                 idx = i / (sizeof(uint32_t) * NBBY);
5069                 shift = i % (sizeof(uint32_t) * NBBY);
5070                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5071                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5072                         filter->index = i;
5073                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5074                                           filter,
5075                                           entries);
5076                         break;
5077                 }
5078         }
5079         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5080                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5081                 return -ENOSYS;
5082         }
5083
5084         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5085                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5086         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5087
5088         ftqf = (uint32_t)(filter->filter_info.proto &
5089                 IXGBE_FTQF_PROTOCOL_MASK);
5090         ftqf |= (uint32_t)((filter->filter_info.priority &
5091                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5092         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5093                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5094         if (filter->filter_info.dst_ip_mask == 0)
5095                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5096         if (filter->filter_info.src_port_mask == 0)
5097                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5098         if (filter->filter_info.dst_port_mask == 0)
5099                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5100         if (filter->filter_info.proto_mask == 0)
5101                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5102         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5103         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5104         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5105
5106         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5107         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5108         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5109         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5110
5111         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5112         l34timir |= (uint32_t)(filter->queue <<
5113                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5114         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5115         return 0;
5116 }
5117
5118 /*
5119  * remove a 5tuple filter
5120  *
5121  * @param
5122  * dev: Pointer to struct rte_eth_dev.
5123  * filter: the pointer of the filter will be removed.
5124  */
5125 static void
5126 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5127                         struct ixgbe_5tuple_filter *filter)
5128 {
5129         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5130         struct ixgbe_filter_info *filter_info =
5131                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5132         uint16_t index = filter->index;
5133
5134         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5135                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5136         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5137         rte_free(filter);
5138
5139         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5140         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5141         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5142         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5143         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5144 }
5145
5146 static int
5147 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5148 {
5149         struct ixgbe_hw *hw;
5150         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5151
5152         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153
5154         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5155                 return -EINVAL;
5156
5157         /* refuse mtu that requires the support of scattered packets when this
5158          * feature has not been enabled before. */
5159         if (!dev->data->scattered_rx &&
5160             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5161              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5162                 return -EINVAL;
5163
5164         /*
5165          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5166          * request of the version 2.0 of the mailbox API.
5167          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5168          * of the mailbox API.
5169          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5170          * prior to 3.11.33 which contains the following change:
5171          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5172          */
5173         ixgbevf_rlpml_set_vf(hw, max_frame);
5174
5175         /* update max frame size */
5176         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5177         return 0;
5178 }
5179
5180 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5181         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5182                 return -ENOTSUP;\
5183 } while (0)
5184
5185 static inline struct ixgbe_5tuple_filter *
5186 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5187                         struct ixgbe_5tuple_filter_info *key)
5188 {
5189         struct ixgbe_5tuple_filter *it;
5190
5191         TAILQ_FOREACH(it, filter_list, entries) {
5192                 if (memcmp(key, &it->filter_info,
5193                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5194                         return it;
5195                 }
5196         }
5197         return NULL;
5198 }
5199
5200 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5201 static inline int
5202 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5203                         struct ixgbe_5tuple_filter_info *filter_info)
5204 {
5205         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5206                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5207                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5208                 return -EINVAL;
5209
5210         switch (filter->dst_ip_mask) {
5211         case UINT32_MAX:
5212                 filter_info->dst_ip_mask = 0;
5213                 filter_info->dst_ip = filter->dst_ip;
5214                 break;
5215         case 0:
5216                 filter_info->dst_ip_mask = 1;
5217                 break;
5218         default:
5219                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5220                 return -EINVAL;
5221         }
5222
5223         switch (filter->src_ip_mask) {
5224         case UINT32_MAX:
5225                 filter_info->src_ip_mask = 0;
5226                 filter_info->src_ip = filter->src_ip;
5227                 break;
5228         case 0:
5229                 filter_info->src_ip_mask = 1;
5230                 break;
5231         default:
5232                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5233                 return -EINVAL;
5234         }
5235
5236         switch (filter->dst_port_mask) {
5237         case UINT16_MAX:
5238                 filter_info->dst_port_mask = 0;
5239                 filter_info->dst_port = filter->dst_port;
5240                 break;
5241         case 0:
5242                 filter_info->dst_port_mask = 1;
5243                 break;
5244         default:
5245                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5246                 return -EINVAL;
5247         }
5248
5249         switch (filter->src_port_mask) {
5250         case UINT16_MAX:
5251                 filter_info->src_port_mask = 0;
5252                 filter_info->src_port = filter->src_port;
5253                 break;
5254         case 0:
5255                 filter_info->src_port_mask = 1;
5256                 break;
5257         default:
5258                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5259                 return -EINVAL;
5260         }
5261
5262         switch (filter->proto_mask) {
5263         case UINT8_MAX:
5264                 filter_info->proto_mask = 0;
5265                 filter_info->proto =
5266                         convert_protocol_type(filter->proto);
5267                 break;
5268         case 0:
5269                 filter_info->proto_mask = 1;
5270                 break;
5271         default:
5272                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5273                 return -EINVAL;
5274         }
5275
5276         filter_info->priority = (uint8_t)filter->priority;
5277         return 0;
5278 }
5279
5280 /*
5281  * add or delete a ntuple filter
5282  *
5283  * @param
5284  * dev: Pointer to struct rte_eth_dev.
5285  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5286  * add: if true, add filter, if false, remove filter
5287  *
5288  * @return
5289  *    - On success, zero.
5290  *    - On failure, a negative value.
5291  */
5292 static int
5293 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5294                         struct rte_eth_ntuple_filter *ntuple_filter,
5295                         bool add)
5296 {
5297         struct ixgbe_filter_info *filter_info =
5298                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5299         struct ixgbe_5tuple_filter_info filter_5tuple;
5300         struct ixgbe_5tuple_filter *filter;
5301         int ret;
5302
5303         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5304                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5305                 return -EINVAL;
5306         }
5307
5308         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5309         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5310         if (ret < 0)
5311                 return ret;
5312
5313         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5314                                          &filter_5tuple);
5315         if (filter != NULL && add) {
5316                 PMD_DRV_LOG(ERR, "filter exists.");
5317                 return -EEXIST;
5318         }
5319         if (filter == NULL && !add) {
5320                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5321                 return -ENOENT;
5322         }
5323
5324         if (add) {
5325                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5326                                 sizeof(struct ixgbe_5tuple_filter), 0);
5327                 if (filter == NULL)
5328                         return -ENOMEM;
5329                 (void)rte_memcpy(&filter->filter_info,
5330                                  &filter_5tuple,
5331                                  sizeof(struct ixgbe_5tuple_filter_info));
5332                 filter->queue = ntuple_filter->queue;
5333                 ret = ixgbe_add_5tuple_filter(dev, filter);
5334                 if (ret < 0) {
5335                         rte_free(filter);
5336                         return ret;
5337                 }
5338         } else
5339                 ixgbe_remove_5tuple_filter(dev, filter);
5340
5341         return 0;
5342 }
5343
5344 /*
5345  * get a ntuple filter
5346  *
5347  * @param
5348  * dev: Pointer to struct rte_eth_dev.
5349  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5350  *
5351  * @return
5352  *    - On success, zero.
5353  *    - On failure, a negative value.
5354  */
5355 static int
5356 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5357                         struct rte_eth_ntuple_filter *ntuple_filter)
5358 {
5359         struct ixgbe_filter_info *filter_info =
5360                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5361         struct ixgbe_5tuple_filter_info filter_5tuple;
5362         struct ixgbe_5tuple_filter *filter;
5363         int ret;
5364
5365         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5366                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5367                 return -EINVAL;
5368         }
5369
5370         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5371         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5372         if (ret < 0)
5373                 return ret;
5374
5375         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5376                                          &filter_5tuple);
5377         if (filter == NULL) {
5378                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5379                 return -ENOENT;
5380         }
5381         ntuple_filter->queue = filter->queue;
5382         return 0;
5383 }
5384
5385 /*
5386  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5387  * @dev: pointer to rte_eth_dev structure
5388  * @filter_op:operation will be taken.
5389  * @arg: a pointer to specific structure corresponding to the filter_op
5390  *
5391  * @return
5392  *    - On success, zero.
5393  *    - On failure, a negative value.
5394  */
5395 static int
5396 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5397                                 enum rte_filter_op filter_op,
5398                                 void *arg)
5399 {
5400         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401         int ret;
5402
5403         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5404
5405         if (filter_op == RTE_ETH_FILTER_NOP)
5406                 return 0;
5407
5408         if (arg == NULL) {
5409                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5410                             filter_op);
5411                 return -EINVAL;
5412         }
5413
5414         switch (filter_op) {
5415         case RTE_ETH_FILTER_ADD:
5416                 ret = ixgbe_add_del_ntuple_filter(dev,
5417                         (struct rte_eth_ntuple_filter *)arg,
5418                         TRUE);
5419                 break;
5420         case RTE_ETH_FILTER_DELETE:
5421                 ret = ixgbe_add_del_ntuple_filter(dev,
5422                         (struct rte_eth_ntuple_filter *)arg,
5423                         FALSE);
5424                 break;
5425         case RTE_ETH_FILTER_GET:
5426                 ret = ixgbe_get_ntuple_filter(dev,
5427                         (struct rte_eth_ntuple_filter *)arg);
5428                 break;
5429         default:
5430                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5431                 ret = -EINVAL;
5432                 break;
5433         }
5434         return ret;
5435 }
5436
5437 static inline int
5438 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5439                         uint16_t ethertype)
5440 {
5441         int i;
5442
5443         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5444                 if (filter_info->ethertype_filters[i] == ethertype &&
5445                     (filter_info->ethertype_mask & (1 << i)))
5446                         return i;
5447         }
5448         return -1;
5449 }
5450
5451 static inline int
5452 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5453                         uint16_t ethertype)
5454 {
5455         int i;
5456
5457         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5458                 if (!(filter_info->ethertype_mask & (1 << i))) {
5459                         filter_info->ethertype_mask |= 1 << i;
5460                         filter_info->ethertype_filters[i] = ethertype;
5461                         return i;
5462                 }
5463         }
5464         return -1;
5465 }
5466
5467 static inline int
5468 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5469                         uint8_t idx)
5470 {
5471         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5472                 return -1;
5473         filter_info->ethertype_mask &= ~(1 << idx);
5474         filter_info->ethertype_filters[idx] = 0;
5475         return idx;
5476 }
5477
5478 static int
5479 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5480                         struct rte_eth_ethertype_filter *filter,
5481                         bool add)
5482 {
5483         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5484         struct ixgbe_filter_info *filter_info =
5485                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5486         uint32_t etqf = 0;
5487         uint32_t etqs = 0;
5488         int ret;
5489
5490         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5491                 return -EINVAL;
5492
5493         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5494                 filter->ether_type == ETHER_TYPE_IPv6) {
5495                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5496                         " ethertype filter.", filter->ether_type);
5497                 return -EINVAL;
5498         }
5499
5500         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5501                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5502                 return -EINVAL;
5503         }
5504         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5505                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5506                 return -EINVAL;
5507         }
5508
5509         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5510         if (ret >= 0 && add) {
5511                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5512                             filter->ether_type);
5513                 return -EEXIST;
5514         }
5515         if (ret < 0 && !add) {
5516                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5517                             filter->ether_type);
5518                 return -ENOENT;
5519         }
5520
5521         if (add) {
5522                 ret = ixgbe_ethertype_filter_insert(filter_info,
5523                         filter->ether_type);
5524                 if (ret < 0) {
5525                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5526                         return -ENOSYS;
5527                 }
5528                 etqf = IXGBE_ETQF_FILTER_EN;
5529                 etqf |= (uint32_t)filter->ether_type;
5530                 etqs |= (uint32_t)((filter->queue <<
5531                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5532                                     IXGBE_ETQS_RX_QUEUE);
5533                 etqs |= IXGBE_ETQS_QUEUE_EN;
5534         } else {
5535                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5536                 if (ret < 0)
5537                         return -ENOSYS;
5538         }
5539         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5540         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5541         IXGBE_WRITE_FLUSH(hw);
5542
5543         return 0;
5544 }
5545
5546 static int
5547 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5548                         struct rte_eth_ethertype_filter *filter)
5549 {
5550         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5551         struct ixgbe_filter_info *filter_info =
5552                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5553         uint32_t etqf, etqs;
5554         int ret;
5555
5556         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5557         if (ret < 0) {
5558                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5559                             filter->ether_type);
5560                 return -ENOENT;
5561         }
5562
5563         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5564         if (etqf & IXGBE_ETQF_FILTER_EN) {
5565                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5566                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5567                 filter->flags = 0;
5568                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5569                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5570                 return 0;
5571         }
5572         return -ENOENT;
5573 }
5574
5575 /*
5576  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5577  * @dev: pointer to rte_eth_dev structure
5578  * @filter_op:operation will be taken.
5579  * @arg: a pointer to specific structure corresponding to the filter_op
5580  */
5581 static int
5582 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5583                                 enum rte_filter_op filter_op,
5584                                 void *arg)
5585 {
5586         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5587         int ret;
5588
5589         MAC_TYPE_FILTER_SUP(hw->mac.type);
5590
5591         if (filter_op == RTE_ETH_FILTER_NOP)
5592                 return 0;
5593
5594         if (arg == NULL) {
5595                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5596                             filter_op);
5597                 return -EINVAL;
5598         }
5599
5600         switch (filter_op) {
5601         case RTE_ETH_FILTER_ADD:
5602                 ret = ixgbe_add_del_ethertype_filter(dev,
5603                         (struct rte_eth_ethertype_filter *)arg,
5604                         TRUE);
5605                 break;
5606         case RTE_ETH_FILTER_DELETE:
5607                 ret = ixgbe_add_del_ethertype_filter(dev,
5608                         (struct rte_eth_ethertype_filter *)arg,
5609                         FALSE);
5610                 break;
5611         case RTE_ETH_FILTER_GET:
5612                 ret = ixgbe_get_ethertype_filter(dev,
5613                         (struct rte_eth_ethertype_filter *)arg);
5614                 break;
5615         default:
5616                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5617                 ret = -EINVAL;
5618                 break;
5619         }
5620         return ret;
5621 }
5622
5623 static int
5624 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5625                      enum rte_filter_type filter_type,
5626                      enum rte_filter_op filter_op,
5627                      void *arg)
5628 {
5629         int ret = -EINVAL;
5630
5631         switch (filter_type) {
5632         case RTE_ETH_FILTER_NTUPLE:
5633                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5634                 break;
5635         case RTE_ETH_FILTER_ETHERTYPE:
5636                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5637                 break;
5638         case RTE_ETH_FILTER_SYN:
5639                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5640                 break;
5641         case RTE_ETH_FILTER_FDIR:
5642                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5643                 break;
5644         default:
5645                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5646                                                         filter_type);
5647                 break;
5648         }
5649
5650         return ret;
5651 }
5652
5653 static u8 *
5654 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5655                         u8 **mc_addr_ptr, u32 *vmdq)
5656 {
5657         u8 *mc_addr;
5658
5659         *vmdq = 0;
5660         mc_addr = *mc_addr_ptr;
5661         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5662         return mc_addr;
5663 }
5664
5665 static int
5666 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5667                           struct ether_addr *mc_addr_set,
5668                           uint32_t nb_mc_addr)
5669 {
5670         struct ixgbe_hw *hw;
5671         u8 *mc_addr_list;
5672
5673         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5674         mc_addr_list = (u8 *)mc_addr_set;
5675         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5676                                          ixgbe_dev_addr_list_itr, TRUE);
5677 }
5678
5679 static int
5680 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5681 {
5682         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5683         uint32_t tsync_ctl;
5684         uint32_t tsauxc;
5685
5686         /* Enable system time for platforms where it isn't on by default. */
5687         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5688         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5689         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5690
5691         /* Start incrementing the register used to timestamp PTP packets. */
5692         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, IXGBE_TIMINCA_INIT);
5693
5694         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5695         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5696                         (ETHER_TYPE_1588 |
5697                          IXGBE_ETQF_FILTER_EN |
5698                          IXGBE_ETQF_1588));
5699
5700         /* Enable timestamping of received PTP packets. */
5701         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5702         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5703         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5704
5705         /* Enable timestamping of transmitted PTP packets. */
5706         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5707         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5708         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5709
5710         return 0;
5711 }
5712
5713 static int
5714 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5715 {
5716         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5717         uint32_t tsync_ctl;
5718
5719         /* Disable timestamping of transmitted PTP packets. */
5720         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5721         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5722         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5723
5724         /* Disable timestamping of received PTP packets. */
5725         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5726         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5727         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5728
5729         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5730         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5731
5732         /* Stop incrementating the System Time registers. */
5733         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5734
5735         return 0;
5736 }
5737
5738 static int
5739 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5740                                  struct timespec *timestamp,
5741                                  uint32_t flags __rte_unused)
5742 {
5743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5744         uint32_t tsync_rxctl;
5745         uint32_t rx_stmpl;
5746         uint32_t rx_stmph;
5747
5748         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5749         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5750                 return -EINVAL;
5751
5752         rx_stmpl = IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5753         rx_stmph = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
5754
5755         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
5756         timestamp->tv_nsec = 0;
5757
5758         return  0;
5759 }
5760
5761 static int
5762 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5763                                  struct timespec *timestamp)
5764 {
5765         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         uint32_t tsync_txctl;
5767         uint32_t tx_stmpl;
5768         uint32_t tx_stmph;
5769
5770         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5771         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5772                 return -EINVAL;
5773
5774         tx_stmpl = IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5775         tx_stmph = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
5776
5777         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
5778         timestamp->tv_nsec = 0;
5779
5780         return  0;
5781 }
5782
5783 static int
5784 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5785 {
5786         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5787         int count = 0;
5788         int g_ind = 0;
5789         const struct reg_info *reg_group;
5790         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5791                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5792
5793         while ((reg_group = reg_set[g_ind++]))
5794                 count += ixgbe_regs_group_count(reg_group);
5795
5796         return count;
5797 }
5798
5799 static int
5800 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5801 {
5802         int count = 0;
5803         int g_ind = 0;
5804         const struct reg_info *reg_group;
5805
5806         while ((reg_group = ixgbevf_regs[g_ind++]))
5807                 count += ixgbe_regs_group_count(reg_group);
5808
5809         return count;
5810 }
5811
5812 static int
5813 ixgbe_get_regs(struct rte_eth_dev *dev,
5814               struct rte_dev_reg_info *regs)
5815 {
5816         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t *data = regs->data;
5818         int g_ind = 0;
5819         int count = 0;
5820         const struct reg_info *reg_group;
5821         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5822                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5823
5824         /* Support only full register dump */
5825         if ((regs->length == 0) ||
5826             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5827                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5828                         hw->device_id;
5829                 while ((reg_group = reg_set[g_ind++]))
5830                         count += ixgbe_read_regs_group(dev, &data[count],
5831                                 reg_group);
5832                 return 0;
5833         }
5834
5835         return -ENOTSUP;
5836 }
5837
5838 static int
5839 ixgbevf_get_regs(struct rte_eth_dev *dev,
5840                 struct rte_dev_reg_info *regs)
5841 {
5842         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843         uint32_t *data = regs->data;
5844         int g_ind = 0;
5845         int count = 0;
5846         const struct reg_info *reg_group;
5847
5848         /* Support only full register dump */
5849         if ((regs->length == 0) ||
5850             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5851                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5852                         hw->device_id;
5853                 while ((reg_group = ixgbevf_regs[g_ind++]))
5854                         count += ixgbe_read_regs_group(dev, &data[count],
5855                                                       reg_group);
5856                 return 0;
5857         }
5858
5859         return -ENOTSUP;
5860 }
5861
5862 static int
5863 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
5864 {
5865         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5866
5867         /* Return unit is byte count */
5868         return hw->eeprom.word_size * 2;
5869 }
5870
5871 static int
5872 ixgbe_get_eeprom(struct rte_eth_dev *dev,
5873                 struct rte_dev_eeprom_info *in_eeprom)
5874 {
5875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5876         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5877         uint16_t *data = in_eeprom->data;
5878         int first, length;
5879
5880         first = in_eeprom->offset >> 1;
5881         length = in_eeprom->length >> 1;
5882         if ((first > hw->eeprom.word_size) ||
5883             ((first + length) > hw->eeprom.word_size))
5884                 return -EINVAL;
5885
5886         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5887
5888         return eeprom->ops.read_buffer(hw, first, length, data);
5889 }
5890
5891 static int
5892 ixgbe_set_eeprom(struct rte_eth_dev *dev,
5893                 struct rte_dev_eeprom_info *in_eeprom)
5894 {
5895         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5896         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
5897         uint16_t *data = in_eeprom->data;
5898         int first, length;
5899
5900         first = in_eeprom->offset >> 1;
5901         length = in_eeprom->length >> 1;
5902         if ((first > hw->eeprom.word_size) ||
5903             ((first + length) > hw->eeprom.word_size))
5904                 return -EINVAL;
5905
5906         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
5907
5908         return eeprom->ops.write_buffer(hw,  first, length, data);
5909 }
5910
5911 uint16_t
5912 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
5913         switch (mac_type) {
5914         case ixgbe_mac_X550:
5915         case ixgbe_mac_X550EM_x:
5916                 return ETH_RSS_RETA_SIZE_512;
5917         case ixgbe_mac_X550_vf:
5918         case ixgbe_mac_X550EM_x_vf:
5919                 return ETH_RSS_RETA_SIZE_64;
5920         default:
5921                 return ETH_RSS_RETA_SIZE_128;
5922         }
5923 }
5924
5925 uint32_t
5926 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
5927         switch (mac_type) {
5928         case ixgbe_mac_X550:
5929         case ixgbe_mac_X550EM_x:
5930                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
5931                         return IXGBE_RETA(reta_idx >> 2);
5932                 else
5933                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
5934         case ixgbe_mac_X550_vf:
5935         case ixgbe_mac_X550EM_x_vf:
5936                 return IXGBE_VFRETA(reta_idx >> 2);
5937         default:
5938                 return IXGBE_RETA(reta_idx >> 2);
5939         }
5940 }
5941
5942 uint32_t
5943 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
5944         switch (mac_type) {
5945         case ixgbe_mac_X550_vf:
5946         case ixgbe_mac_X550EM_x_vf:
5947                 return IXGBE_VFMRQC;
5948         default:
5949                 return IXGBE_MRQC;
5950         }
5951 }
5952
5953 uint32_t
5954 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
5955         switch (mac_type) {
5956         case ixgbe_mac_X550_vf:
5957         case ixgbe_mac_X550EM_x_vf:
5958                 return IXGBE_VFRSSRK(i);
5959         default:
5960                 return IXGBE_RSSRK(i);
5961         }
5962 }
5963
5964 bool
5965 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
5966         switch (mac_type) {
5967         case ixgbe_mac_82599_vf:
5968         case ixgbe_mac_X540_vf:
5969                 return 0;
5970         default:
5971                 return 1;
5972         }
5973 }
5974
5975 static int
5976 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
5977                         struct rte_eth_dcb_info *dcb_info)
5978 {
5979         struct ixgbe_dcb_config *dcb_config =
5980                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
5981         struct ixgbe_dcb_tc_config *tc;
5982         uint8_t i, j;
5983
5984         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
5985                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
5986         else
5987                 dcb_info->nb_tcs = 1;
5988
5989         if (dcb_config->vt_mode) { /* vt is enabled*/
5990                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
5991                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
5992                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
5993                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
5994                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
5995                         for (j = 0; j < dcb_info->nb_tcs; j++) {
5996                                 dcb_info->tc_queue.tc_rxq[i][j].base =
5997                                                 i * dcb_info->nb_tcs + j;
5998                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
5999                                 dcb_info->tc_queue.tc_txq[i][j].base =
6000                                                 i * dcb_info->nb_tcs + j;
6001                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6002                         }
6003                 }
6004         } else { /* vt is disabled*/
6005                 struct rte_eth_dcb_rx_conf *rx_conf =
6006                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6007                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6008                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6009                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6010                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6011                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6012                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6013                         }
6014                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6015                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6016                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6017                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6018                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6019                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6020                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6021                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6022                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6023                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6024                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6025                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6026                         }
6027                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6028                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6029                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6030                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6031                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6032                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6033                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6034                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6035                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6036                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6037                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6038                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6039                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6040                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6041                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6042                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6043                 }
6044         }
6045         for (i = 0; i < dcb_info->nb_tcs; i++) {
6046                 tc = &dcb_config->tc_config[i];
6047                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6048         }
6049         return 0;
6050 }
6051
6052 static struct rte_driver rte_ixgbe_driver = {
6053         .type = PMD_PDEV,
6054         .init = rte_ixgbe_pmd_init,
6055 };
6056
6057 static struct rte_driver rte_ixgbevf_driver = {
6058         .type = PMD_PDEV,
6059         .init = rte_ixgbevf_pmd_init,
6060 };
6061
6062 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6063 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);