drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIBRTE_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int  ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 304                         struct rte_eth_syn_filter *filter);
 305 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 306                         enum rte_filter_op filter_op,
 307                         void *arg);
 308 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 309                         struct ixgbe_5tuple_filter *filter);
 310 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 311                         struct ixgbe_5tuple_filter *filter);
 312 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 313                                 enum rte_filter_op filter_op,
 314                                 void *arg);
 315 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 316                         struct rte_eth_ntuple_filter *filter);
 317 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 318                                 enum rte_filter_op filter_op,
 319                                 void *arg);
 320 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 321                         struct rte_eth_ethertype_filter *filter);
 322 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                      enum rte_filter_type filter_type,
 324                      enum rte_filter_op filter_op,
 325                      void *arg);
 326 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 327
 328 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 329                                       struct rte_ether_addr *mc_addr_set,
 330                                       uint32_t nb_mc_addr);
 331 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 332                                    struct rte_eth_dcb_info *dcb_info);
 333
 334 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 335 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 336                             struct rte_dev_reg_info *regs);
 337 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 338 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 339                                 struct rte_dev_eeprom_info *eeprom);
 340 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 341                                 struct rte_dev_eeprom_info *eeprom);
 342
 343 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 344                                  struct rte_eth_dev_module_info *modinfo);
 345 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 346                                    struct rte_dev_eeprom_info *info);
 347
 348 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 349 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 350                                 struct rte_dev_reg_info *regs);
 351
 352 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 353 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 354 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 355                                             struct timespec *timestamp,
 356                                             uint32_t flags);
 357 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 358                                             struct timespec *timestamp);
 359 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 360 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 361                                    struct timespec *timestamp);
 362 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 363                                    const struct timespec *timestamp);
 364 static void ixgbevf_dev_interrupt_handler(void *param);
 365
 366 static int ixgbe_dev_l2_tunnel_eth_type_conf
 367         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 368 static int ixgbe_dev_l2_tunnel_offload_set
 369         (struct rte_eth_dev *dev,
 370          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 371          uint32_t mask,
 372          uint8_t en);
 373 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 374                                              enum rte_filter_op filter_op,
 375                                              void *arg);
 376
 377 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 378                                          struct rte_eth_udp_tunnel *udp_tunnel);
 379 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 380                                          struct rte_eth_udp_tunnel *udp_tunnel);
 381 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 382 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 383 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 384
 385 /*
 386  * Define VF Stats MACRO for Non "cleared on read" register
 387  */
 388 #define UPDATE_VF_STAT(reg, last, cur)                          \
 389 {                                                               \
 390         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 391         cur += (latest - last) & UINT_MAX;                      \
 392         last = latest;                                          \
 393 }
 394
 395 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 396 {                                                                \
 397         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 398         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 399         u64 latest = ((new_msb << 32) | new_lsb);                \
 400         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 401         last = latest;                                           \
 402 }
 403
 404 #define IXGBE_SET_HWSTRIP(h, q) do {\
 405                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 406                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 407                 (h)->bitmap[idx] |= 1 << bit;\
 408         } while (0)
 409
 410 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 411                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 412                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 413                 (h)->bitmap[idx] &= ~(1 << bit);\
 414         } while (0)
 415
 416 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 417                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 418                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 419                 (r) = (h)->bitmap[idx] >> bit & 1;\
 420         } while (0)
 421
 422 /*
 423  * The set of PCI devices this driver supports
 424  */
 425 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 474 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 476 #endif
 477         { .vendor_id = 0, /* sentinel */ },
 478 };
 479
 480 /*
 481  * The set of PCI devices this driver supports (for 82599 VF)
 482  */
 483 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 485         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 486         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 487         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 488         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 489         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 490         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 491         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 492         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 494         { .vendor_id = 0, /* sentinel */ },
 495 };
 496
 497 static const struct rte_eth_desc_lim rx_desc_lim = {
 498         .nb_max = IXGBE_MAX_RING_DESC,
 499         .nb_min = IXGBE_MIN_RING_DESC,
 500         .nb_align = IXGBE_RXD_ALIGN,
 501 };
 502
 503 static const struct rte_eth_desc_lim tx_desc_lim = {
 504         .nb_max = IXGBE_MAX_RING_DESC,
 505         .nb_min = IXGBE_MIN_RING_DESC,
 506         .nb_align = IXGBE_TXD_ALIGN,
 507         .nb_seg_max = IXGBE_TX_MAX_SEG,
 508         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 509 };
 510
 511 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 512         .dev_configure        = ixgbe_dev_configure,
 513         .dev_start            = ixgbe_dev_start,
 514         .dev_stop             = ixgbe_dev_stop,
 515         .dev_set_link_up    = ixgbe_dev_set_link_up,
 516         .dev_set_link_down  = ixgbe_dev_set_link_down,
 517         .dev_close            = ixgbe_dev_close,
 518         .dev_reset            = ixgbe_dev_reset,
 519         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 520         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 521         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 522         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 523         .link_update          = ixgbe_dev_link_update,
 524         .stats_get            = ixgbe_dev_stats_get,
 525         .xstats_get           = ixgbe_dev_xstats_get,
 526         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 527         .stats_reset          = ixgbe_dev_stats_reset,
 528         .xstats_reset         = ixgbe_dev_xstats_reset,
 529         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 530         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 531         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 532         .fw_version_get       = ixgbe_fw_version_get,
 533         .dev_infos_get        = ixgbe_dev_info_get,
 534         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 535         .mtu_set              = ixgbe_dev_mtu_set,
 536         .vlan_filter_set      = ixgbe_vlan_filter_set,
 537         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 538         .vlan_offload_set     = ixgbe_vlan_offload_set,
 539         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 540         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 541         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 542         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 543         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 544         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 545         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 546         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 547         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 548         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 549         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 550         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 551         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 552         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 553         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 554         .dev_led_on           = ixgbe_dev_led_on,
 555         .dev_led_off          = ixgbe_dev_led_off,
 556         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 557         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 558         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 559         .mac_addr_add         = ixgbe_add_rar,
 560         .mac_addr_remove      = ixgbe_remove_rar,
 561         .mac_addr_set         = ixgbe_set_default_mac_addr,
 562         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 563         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 564         .mirror_rule_set      = ixgbe_mirror_rule_set,
 565         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 566         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 567         .reta_update          = ixgbe_dev_rss_reta_update,
 568         .reta_query           = ixgbe_dev_rss_reta_query,
 569         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 570         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 571         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 572         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 573         .rxq_info_get         = ixgbe_rxq_info_get,
 574         .txq_info_get         = ixgbe_txq_info_get,
 575         .timesync_enable      = ixgbe_timesync_enable,
 576         .timesync_disable     = ixgbe_timesync_disable,
 577         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 578         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 579         .get_reg              = ixgbe_get_regs,
 580         .get_eeprom_length    = ixgbe_get_eeprom_length,
 581         .get_eeprom           = ixgbe_get_eeprom,
 582         .set_eeprom           = ixgbe_set_eeprom,
 583         .get_module_info      = ixgbe_get_module_info,
 584         .get_module_eeprom    = ixgbe_get_module_eeprom,
 585         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 586         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 587         .timesync_read_time   = ixgbe_timesync_read_time,
 588         .timesync_write_time  = ixgbe_timesync_write_time,
 589         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 590         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 591         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 592         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 593         .tm_ops_get           = ixgbe_tm_ops_get,
 594         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 595 };
 596
 597 /*
 598  * dev_ops for virtual function, bare necessities for basic vf
 599  * operation have been implemented
 600  */
 601 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 602         .dev_configure        = ixgbevf_dev_configure,
 603         .dev_start            = ixgbevf_dev_start,
 604         .dev_stop             = ixgbevf_dev_stop,
 605         .link_update          = ixgbevf_dev_link_update,
 606         .stats_get            = ixgbevf_dev_stats_get,
 607         .xstats_get           = ixgbevf_dev_xstats_get,
 608         .stats_reset          = ixgbevf_dev_stats_reset,
 609         .xstats_reset         = ixgbevf_dev_stats_reset,
 610         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 611         .dev_close            = ixgbevf_dev_close,
 612         .dev_reset            = ixgbevf_dev_reset,
 613         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 614         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 615         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 616         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 617         .dev_infos_get        = ixgbevf_dev_info_get,
 618         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 619         .mtu_set              = ixgbevf_dev_set_mtu,
 620         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 621         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 622         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 623         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 624         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 625         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 626         .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
 627         .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
 628         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 629         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 630         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 631         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 632         .mac_addr_add         = ixgbevf_add_mac_addr,
 633         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 634         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 635         .rxq_info_get         = ixgbe_rxq_info_get,
 636         .txq_info_get         = ixgbe_txq_info_get,
 637         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 638         .get_reg              = ixgbevf_get_regs,
 639         .reta_update          = ixgbe_dev_rss_reta_update,
 640         .reta_query           = ixgbe_dev_rss_reta_query,
 641         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 642         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 643         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 644 };
 645
 646 /* store statistics names and its offset in stats structure */
 647 struct rte_ixgbe_xstats_name_off {
 648         char name[RTE_ETH_XSTATS_NAME_SIZE];
 649         unsigned offset;
 650 };
 651
 652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 653         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 654         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 655         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 656         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 657         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 658         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 659         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 660         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 661         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 662         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 663         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 664         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 665         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 666         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 667         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 668                 prc1023)},
 669         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 670                 prc1522)},
 671         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 672         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 673         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 674         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 675         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 676         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 677         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 678         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 679         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 680         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 681         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 682         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 683         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 684         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 685         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 686         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 687         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 688                 ptc1023)},
 689         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 690                 ptc1522)},
 691         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 692         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 693         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 694         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 695
 696         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 697                 fdirustat_add)},
 698         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 699                 fdirustat_remove)},
 700         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 701                 fdirfstat_fadd)},
 702         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 703                 fdirfstat_fremove)},
 704         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 705                 fdirmatch)},
 706         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 707                 fdirmiss)},
 708
 709         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 710         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 711         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 712                 fclast)},
 713         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 714         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 715         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 716         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 717         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 718                 fcoe_noddp)},
 719         {"rx_fcoe_no_direct_data_placement_ext_buff",
 720                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 721
 722         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 723                 lxontxc)},
 724         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 725                 lxonrxc)},
 726         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 727                 lxofftxc)},
 728         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 729                 lxoffrxc)},
 730         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 731 };
 732
 733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 734                            sizeof(rte_ixgbe_stats_strings[0]))
 735
 736 /* MACsec statistics */
 737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 738         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 739                 out_pkts_untagged)},
 740         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 741                 out_pkts_encrypted)},
 742         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 743                 out_pkts_protected)},
 744         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 745                 out_octets_encrypted)},
 746         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 747                 out_octets_protected)},
 748         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 749                 in_pkts_untagged)},
 750         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 751                 in_pkts_badtag)},
 752         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 753                 in_pkts_nosci)},
 754         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 755                 in_pkts_unknownsci)},
 756         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 757                 in_octets_decrypted)},
 758         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 759                 in_octets_validated)},
 760         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 761                 in_pkts_unchecked)},
 762         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 763                 in_pkts_delayed)},
 764         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 765                 in_pkts_late)},
 766         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 767                 in_pkts_ok)},
 768         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 769                 in_pkts_invalid)},
 770         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 771                 in_pkts_notvalid)},
 772         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 773                 in_pkts_unusedsa)},
 774         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 775                 in_pkts_notusingsa)},
 776 };
 777
 778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 779                            sizeof(rte_ixgbe_macsec_strings[0]))
 780
 781 /* Per-queue statistics */
 782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 783         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 784         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 785         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 786         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 787 };
 788
 789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 790                            sizeof(rte_ixgbe_rxq_strings[0]))
 791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 792
 793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 794         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 795         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 796         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 797                 pxon2offc)},
 798 };
 799
 800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 801                            sizeof(rte_ixgbe_txq_strings[0]))
 802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 803
 804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 805         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 806 };
 807
 808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 809                 sizeof(rte_ixgbevf_stats_strings[0]))
 810
 811 /*
 812  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 813  */
 814 static inline int
 815 ixgbe_is_sfp(struct ixgbe_hw *hw)
 816 {
 817         switch (hw->phy.type) {
 818         case ixgbe_phy_sfp_avago:
 819         case ixgbe_phy_sfp_ftl:
 820         case ixgbe_phy_sfp_intel:
 821         case ixgbe_phy_sfp_unknown:
 822         case ixgbe_phy_sfp_passive_tyco:
 823         case ixgbe_phy_sfp_passive_unknown:
 824                 return 1;
 825         default:
 826                 return 0;
 827         }
 828 }
 829
 830 static inline int32_t
 831 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 832 {
 833         uint32_t ctrl_ext;
 834         int32_t status;
 835
 836         status = ixgbe_reset_hw(hw);
 837
 838         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 839         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 840         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 841         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 842         IXGBE_WRITE_FLUSH(hw);
 843
 844         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 845                 status = IXGBE_SUCCESS;
 846         return status;
 847 }
 848
 849 static inline void
 850 ixgbe_enable_intr(struct rte_eth_dev *dev)
 851 {
 852         struct ixgbe_interrupt *intr =
 853                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 854         struct ixgbe_hw *hw =
 855                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 856
 857         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 858         IXGBE_WRITE_FLUSH(hw);
 859 }
 860
 861 /*
 862  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 863  */
 864 static void
 865 ixgbe_disable_intr(struct ixgbe_hw *hw)
 866 {
 867         PMD_INIT_FUNC_TRACE();
 868
 869         if (hw->mac.type == ixgbe_mac_82598EB) {
 870                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 871         } else {
 872                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 873                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 874                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 875         }
 876         IXGBE_WRITE_FLUSH(hw);
 877 }
 878
 879 /*
 880  * This function resets queue statistics mapping registers.
 881  * From Niantic datasheet, Initialization of Statistics section:
 882  * "...if software requires the queue counters, the RQSMR and TQSM registers
 883  * must be re-programmed following a device reset.
 884  */
 885 static void
 886 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 887 {
 888         uint32_t i;
 889
 890         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 891                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 892                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 893         }
 894 }
 895
 896
 897 static int
 898 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 899                                   uint16_t queue_id,
 900                                   uint8_t stat_idx,
 901                                   uint8_t is_rx)
 902 {
 903 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 904 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 905 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 906
 907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 908         struct ixgbe_stat_mapping_registers *stat_mappings =
 909                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 910         uint32_t qsmr_mask = 0;
 911         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 912         uint32_t q_map;
 913         uint8_t n, offset;
 914
 915         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 916                 (hw->mac.type != ixgbe_mac_X540) &&
 917                 (hw->mac.type != ixgbe_mac_X550) &&
 918                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 919                 (hw->mac.type != ixgbe_mac_X550EM_a))
 920                 return -ENOSYS;
 921
 922         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 923                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 924                      queue_id, stat_idx);
 925
 926         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 927         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 928                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 929                 return -EIO;
 930         }
 931         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 932
 933         /* Now clear any previous stat_idx set */
 934         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 935         if (!is_rx)
 936                 stat_mappings->tqsm[n] &= ~clearing_mask;
 937         else
 938                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 939
 940         q_map = (uint32_t)stat_idx;
 941         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 942         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 943         if (!is_rx)
 944                 stat_mappings->tqsm[n] |= qsmr_mask;
 945         else
 946                 stat_mappings->rqsmr[n] |= qsmr_mask;
 947
 948         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 949                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 950                      queue_id, stat_idx);
 951         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 952                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 953
 954         /* Now write the mapping in the appropriate register */
 955         if (is_rx) {
 956                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 957                              stat_mappings->rqsmr[n], n);
 958                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 959         } else {
 960                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 961                              stat_mappings->tqsm[n], n);
 962                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 963         }
 964         return 0;
 965 }
 966
 967 static void
 968 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 969 {
 970         struct ixgbe_stat_mapping_registers *stat_mappings =
 971                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 972         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         int i;
 974
 975         /* write whatever was in stat mapping table to the NIC */
 976         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 977                 /* rx */
 978                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 979
 980                 /* tx */
 981                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 982         }
 983 }
 984
 985 static void
 986 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 987 {
 988         uint8_t i;
 989         struct ixgbe_dcb_tc_config *tc;
 990         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 991
 992         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 993         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 994         for (i = 0; i < dcb_max_tc; i++) {
 995                 tc = &dcb_config->tc_config[i];
 996                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 997                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 998                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 999                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1000                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1001                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1002                 tc->pfc = ixgbe_dcb_pfc_disabled;
1003         }
1004
1005         /* Initialize default user to priority mapping, UPx->TC0 */
1006         tc = &dcb_config->tc_config[0];
1007         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1008         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1009         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1010                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1011                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1012         }
1013         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1014         dcb_config->pfc_mode_enable = false;
1015         dcb_config->vt_mode = true;
1016         dcb_config->round_robin_enable = false;
1017         /* support all DCB capabilities in 82599 */
1018         dcb_config->support.capabilities = 0xFF;
1019
1020         /*we only support 4 Tcs for X540, X550 */
1021         if (hw->mac.type == ixgbe_mac_X540 ||
1022                 hw->mac.type == ixgbe_mac_X550 ||
1023                 hw->mac.type == ixgbe_mac_X550EM_x ||
1024                 hw->mac.type == ixgbe_mac_X550EM_a) {
1025                 dcb_config->num_tcs.pg_tcs = 4;
1026                 dcb_config->num_tcs.pfc_tcs = 4;
1027         }
1028 }
1029
1030 /*
1031  * Ensure that all locks are released before first NVM or PHY access
1032  */
1033 static void
1034 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1035 {
1036         uint16_t mask;
1037
1038         /*
1039          * Phy lock should not fail in this early stage. If this is the case,
1040          * it is due to an improper exit of the application.
1041          * So force the release of the faulty lock. Release of common lock
1042          * is done automatically by swfw_sync function.
1043          */
1044         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1045         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1046                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1047         }
1048         ixgbe_release_swfw_semaphore(hw, mask);
1049
1050         /*
1051          * These ones are more tricky since they are common to all ports; but
1052          * swfw_sync retries last long enough (1s) to be almost sure that if
1053          * lock can not be taken it is due to an improper lock of the
1054          * semaphore.
1055          */
1056         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1057         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1058                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1059         }
1060         ixgbe_release_swfw_semaphore(hw, mask);
1061 }
1062
1063 /*
1064  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1065  * It returns 0 on success.
1066  */
1067 static int
1068 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1069 {
1070         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1071         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1072         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1073         struct ixgbe_hw *hw =
1074                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1075         struct ixgbe_vfta *shadow_vfta =
1076                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1077         struct ixgbe_hwstrip *hwstrip =
1078                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1079         struct ixgbe_dcb_config *dcb_config =
1080                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1081         struct ixgbe_filter_info *filter_info =
1082                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1083         struct ixgbe_bw_conf *bw_conf =
1084                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1085         uint32_t ctrl_ext;
1086         uint16_t csum;
1087         int diag, i;
1088
1089         PMD_INIT_FUNC_TRACE();
1090
1091         ixgbe_dev_macsec_setting_reset(eth_dev);
1092
1093         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1094         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1095         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1096         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1097
1098         /*
1099          * For secondary processes, we don't initialise any further as primary
1100          * has already done this work. Only check we don't need a different
1101          * RX and TX function.
1102          */
1103         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1104                 struct ixgbe_tx_queue *txq;
1105                 /* TX queue function in primary, set by last queue initialized
1106                  * Tx queue may not initialized by primary process
1107                  */
1108                 if (eth_dev->data->tx_queues) {
1109                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1110                         ixgbe_set_tx_function(eth_dev, txq);
1111                 } else {
1112                         /* Use default TX function if we get here */
1113                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1114                                      "Using default TX function.");
1115                 }
1116
1117                 ixgbe_set_rx_function(eth_dev);
1118
1119                 return 0;
1120         }
1121
1122         rte_atomic32_clear(&ad->link_thread_running);
1123         rte_eth_copy_pci_info(eth_dev, pci_dev);
1124
1125         /* Vendor and Device ID need to be set before init of shared code */
1126         hw->device_id = pci_dev->id.device_id;
1127         hw->vendor_id = pci_dev->id.vendor_id;
1128         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1129         hw->allow_unsupported_sfp = 1;
1130
1131         /* Initialize the shared code (base driver) */
1132 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1133         diag = ixgbe_bypass_init_shared_code(hw);
1134 #else
1135         diag = ixgbe_init_shared_code(hw);
1136 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1137
1138         if (diag != IXGBE_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1140                 return -EIO;
1141         }
1142
1143         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1144                 PMD_INIT_LOG(ERR, "\nERROR: "
1145                         "Firmware recovery mode detected. Limiting functionality.\n"
1146                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1147                         "User Guide for details on firmware recovery mode.");
1148                 return -EIO;
1149         }
1150
1151         /* pick up the PCI bus settings for reporting later */
1152         ixgbe_get_bus_info(hw);
1153
1154         /* Unlock any pending hardware semaphore */
1155         ixgbe_swfw_lock_reset(hw);
1156
1157 #ifdef RTE_LIBRTE_SECURITY
1158         /* Initialize security_ctx only for primary process*/
1159         if (ixgbe_ipsec_ctx_create(eth_dev))
1160                 return -ENOMEM;
1161 #endif
1162
1163         /* Initialize DCB configuration*/
1164         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1165         ixgbe_dcb_init(hw, dcb_config);
1166         /* Get Hardware Flow Control setting */
1167         hw->fc.requested_mode = ixgbe_fc_none;
1168         hw->fc.current_mode = ixgbe_fc_none;
1169         hw->fc.pause_time = IXGBE_FC_PAUSE;
1170         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1171                 hw->fc.low_water[i] = IXGBE_FC_LO;
1172                 hw->fc.high_water[i] = IXGBE_FC_HI;
1173         }
1174         hw->fc.send_xon = 1;
1175
1176         /* Make sure we have a good EEPROM before we read from it */
1177         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1178         if (diag != IXGBE_SUCCESS) {
1179                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1180                 return -EIO;
1181         }
1182
1183 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1184         diag = ixgbe_bypass_init_hw(hw);
1185 #else
1186         diag = ixgbe_init_hw(hw);
1187 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1188
1189         /*
1190          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1191          * is called too soon after the kernel driver unbinding/binding occurs.
1192          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1193          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1194          * also called. See ixgbe_identify_phy_82599(). The reason for the
1195          * failure is not known, and only occuts when virtualisation features
1196          * are disabled in the bios. A delay of 100ms  was found to be enough by
1197          * trial-and-error, and is doubled to be safe.
1198          */
1199         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1200                 rte_delay_ms(200);
1201                 diag = ixgbe_init_hw(hw);
1202         }
1203
1204         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1205                 diag = IXGBE_SUCCESS;
1206
1207         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1208                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1209                              "LOM.  Please be aware there may be issues associated "
1210                              "with your hardware.");
1211                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1212                              "please contact your Intel or hardware representative "
1213                              "who provided you with this hardware.");
1214         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1215                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1216         if (diag) {
1217                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1218                 return -EIO;
1219         }
1220
1221         /* Reset the hw statistics */
1222         ixgbe_dev_stats_reset(eth_dev);
1223
1224         /* disable interrupt */
1225         ixgbe_disable_intr(hw);
1226
1227         /* reset mappings for queue statistics hw counters*/
1228         ixgbe_reset_qstat_mappings(hw);
1229
1230         /* Allocate memory for storing MAC addresses */
1231         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1232                                                hw->mac.num_rar_entries, 0);
1233         if (eth_dev->data->mac_addrs == NULL) {
1234                 PMD_INIT_LOG(ERR,
1235                              "Failed to allocate %u bytes needed to store "
1236                              "MAC addresses",
1237                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1238                 return -ENOMEM;
1239         }
1240         /* Copy the permanent MAC address */
1241         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1242                         &eth_dev->data->mac_addrs[0]);
1243
1244         /* Allocate memory for storing hash filter MAC addresses */
1245         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1246                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1247         if (eth_dev->data->hash_mac_addrs == NULL) {
1248                 PMD_INIT_LOG(ERR,
1249                              "Failed to allocate %d bytes needed to store MAC addresses",
1250                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1251                 return -ENOMEM;
1252         }
1253
1254         /* Pass the information to the rte_eth_dev_close() that it should also
1255          * release the private port resources.
1256          */
1257         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1258
1259         /* initialize the vfta */
1260         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1261
1262         /* initialize the hw strip bitmap*/
1263         memset(hwstrip, 0, sizeof(*hwstrip));
1264
1265         /* initialize PF if max_vfs not zero */
1266         ixgbe_pf_host_init(eth_dev);
1267
1268         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1269         /* let hardware know driver is loaded */
1270         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1271         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1272         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1273         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1274         IXGBE_WRITE_FLUSH(hw);
1275
1276         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1277                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1278                              (int) hw->mac.type, (int) hw->phy.type,
1279                              (int) hw->phy.sfp_type);
1280         else
1281                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1282                              (int) hw->mac.type, (int) hw->phy.type);
1283
1284         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1285                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1286                      pci_dev->id.device_id);
1287
1288         rte_intr_callback_register(intr_handle,
1289                                    ixgbe_dev_interrupt_handler, eth_dev);
1290
1291         /* enable uio/vfio intr/eventfd mapping */
1292         rte_intr_enable(intr_handle);
1293
1294         /* enable support intr */
1295         ixgbe_enable_intr(eth_dev);
1296
1297         /* initialize filter info */
1298         memset(filter_info, 0,
1299                sizeof(struct ixgbe_filter_info));
1300
1301         /* initialize 5tuple filter list */
1302         TAILQ_INIT(&filter_info->fivetuple_list);
1303
1304         /* initialize flow director filter list & hash */
1305         ixgbe_fdir_filter_init(eth_dev);
1306
1307         /* initialize l2 tunnel filter list & hash */
1308         ixgbe_l2_tn_filter_init(eth_dev);
1309
1310         /* initialize flow filter lists */
1311         ixgbe_filterlist_init();
1312
1313         /* initialize bandwidth configuration info */
1314         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1315
1316         /* initialize Traffic Manager configuration */
1317         ixgbe_tm_conf_init(eth_dev);
1318
1319         return 0;
1320 }
1321
1322 static int
1323 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1324 {
1325         PMD_INIT_FUNC_TRACE();
1326
1327         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1328                 return 0;
1329
1330         ixgbe_dev_close(eth_dev);
1331
1332         return 0;
1333 }
1334
1335 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1336 {
1337         struct ixgbe_filter_info *filter_info =
1338                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1339         struct ixgbe_5tuple_filter *p_5tuple;
1340
1341         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1342                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1343                              p_5tuple,
1344                              entries);
1345                 rte_free(p_5tuple);
1346         }
1347         memset(filter_info->fivetuple_mask, 0,
1348                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1349
1350         return 0;
1351 }
1352
1353 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct ixgbe_hw_fdir_info *fdir_info =
1356                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1357         struct ixgbe_fdir_filter *fdir_filter;
1358
1359                 if (fdir_info->hash_map)
1360                 rte_free(fdir_info->hash_map);
1361         if (fdir_info->hash_handle)
1362                 rte_hash_free(fdir_info->hash_handle);
1363
1364         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365                 TAILQ_REMOVE(&fdir_info->fdir_list,
1366                              fdir_filter,
1367                              entries);
1368                 rte_free(fdir_filter);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1375 {
1376         struct ixgbe_l2_tn_info *l2_tn_info =
1377                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1378         struct ixgbe_l2_tn_filter *l2_tn_filter;
1379
1380         if (l2_tn_info->hash_map)
1381                 rte_free(l2_tn_info->hash_map);
1382         if (l2_tn_info->hash_handle)
1383                 rte_hash_free(l2_tn_info->hash_handle);
1384
1385         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1386                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1387                              l2_tn_filter,
1388                              entries);
1389                 rte_free(l2_tn_filter);
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1396 {
1397         struct ixgbe_hw_fdir_info *fdir_info =
1398                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1399         char fdir_hash_name[RTE_HASH_NAMESIZE];
1400         struct rte_hash_parameters fdir_hash_params = {
1401                 .name = fdir_hash_name,
1402                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1403                 .key_len = sizeof(union ixgbe_atr_input),
1404                 .hash_func = rte_hash_crc,
1405                 .hash_func_init_val = 0,
1406                 .socket_id = rte_socket_id(),
1407         };
1408
1409         TAILQ_INIT(&fdir_info->fdir_list);
1410         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1411                  "fdir_%s", eth_dev->device->name);
1412         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1413         if (!fdir_info->hash_handle) {
1414                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1415                 return -EINVAL;
1416         }
1417         fdir_info->hash_map = rte_zmalloc("ixgbe",
1418                                           sizeof(struct ixgbe_fdir_filter *) *
1419                                           IXGBE_MAX_FDIR_FILTER_NUM,
1420                                           0);
1421         if (!fdir_info->hash_map) {
1422                 PMD_INIT_LOG(ERR,
1423                              "Failed to allocate memory for fdir hash map!");
1424                 return -ENOMEM;
1425         }
1426         fdir_info->mask_added = FALSE;
1427
1428         return 0;
1429 }
1430
1431 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1432 {
1433         struct ixgbe_l2_tn_info *l2_tn_info =
1434                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1435         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1436         struct rte_hash_parameters l2_tn_hash_params = {
1437                 .name = l2_tn_hash_name,
1438                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1439                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1440                 .hash_func = rte_hash_crc,
1441                 .hash_func_init_val = 0,
1442                 .socket_id = rte_socket_id(),
1443         };
1444
1445         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1446         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1447                  "l2_tn_%s", eth_dev->device->name);
1448         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1449         if (!l2_tn_info->hash_handle) {
1450                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1451                 return -EINVAL;
1452         }
1453         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1454                                    sizeof(struct ixgbe_l2_tn_filter *) *
1455                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1456                                    0);
1457         if (!l2_tn_info->hash_map) {
1458                 PMD_INIT_LOG(ERR,
1459                         "Failed to allocate memory for L2 TN hash map!");
1460                 return -ENOMEM;
1461         }
1462         l2_tn_info->e_tag_en = FALSE;
1463         l2_tn_info->e_tag_fwd_en = FALSE;
1464         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1465
1466         return 0;
1467 }
1468 /*
1469  * Negotiate mailbox API version with the PF.
1470  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1471  * Then we try to negotiate starting with the most recent one.
1472  * If all negotiation attempts fail, then we will proceed with
1473  * the default one (ixgbe_mbox_api_10).
1474  */
1475 static void
1476 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1477 {
1478         int32_t i;
1479
1480         /* start with highest supported, proceed down */
1481         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1482                 ixgbe_mbox_api_13,
1483                 ixgbe_mbox_api_12,
1484                 ixgbe_mbox_api_11,
1485                 ixgbe_mbox_api_10,
1486         };
1487
1488         for (i = 0;
1489                         i != RTE_DIM(sup_ver) &&
1490                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1491                         i++)
1492                 ;
1493 }
1494
1495 static void
1496 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1497 {
1498         uint64_t random;
1499
1500         /* Set Organizationally Unique Identifier (OUI) prefix. */
1501         mac_addr->addr_bytes[0] = 0x00;
1502         mac_addr->addr_bytes[1] = 0x09;
1503         mac_addr->addr_bytes[2] = 0xC0;
1504         /* Force indication of locally assigned MAC address. */
1505         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1506         /* Generate the last 3 bytes of the MAC address with a random number. */
1507         random = rte_rand();
1508         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1509 }
1510
1511 static int
1512 devarg_handle_int(__rte_unused const char *key, const char *value,
1513                   void *extra_args)
1514 {
1515         uint16_t *n = extra_args;
1516
1517         if (value == NULL || extra_args == NULL)
1518                 return -EINVAL;
1519
1520         *n = (uint16_t)strtoul(value, NULL, 0);
1521         if (*n == USHRT_MAX && errno == ERANGE)
1522                 return -1;
1523
1524         return 0;
1525 }
1526
1527 static void
1528 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1529                       struct rte_devargs *devargs)
1530 {
1531         struct rte_kvargs *kvlist;
1532         uint16_t pflink_fullchk;
1533
1534         if (devargs == NULL)
1535                 return;
1536
1537         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1538         if (kvlist == NULL)
1539                 return;
1540
1541         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1542             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1543                                devarg_handle_int, &pflink_fullchk) == 0 &&
1544             pflink_fullchk == 1)
1545                 adapter->pflink_fullchk = 1;
1546
1547         rte_kvargs_free(kvlist);
1548 }
1549
1550 /*
1551  * Virtual Function device init
1552  */
1553 static int
1554 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1555 {
1556         int diag;
1557         uint32_t tc, tcs;
1558         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1559         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1560         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1561         struct ixgbe_hw *hw =
1562                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1563         struct ixgbe_vfta *shadow_vfta =
1564                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1565         struct ixgbe_hwstrip *hwstrip =
1566                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1567         struct rte_ether_addr *perm_addr =
1568                 (struct rte_ether_addr *)hw->mac.perm_addr;
1569
1570         PMD_INIT_FUNC_TRACE();
1571
1572         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1573         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1574         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1575
1576         /* for secondary processes, we don't initialise any further as primary
1577          * has already done this work. Only check we don't need a different
1578          * RX function
1579          */
1580         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1581                 struct ixgbe_tx_queue *txq;
1582                 /* TX queue function in primary, set by last queue initialized
1583                  * Tx queue may not initialized by primary process
1584                  */
1585                 if (eth_dev->data->tx_queues) {
1586                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1587                         ixgbe_set_tx_function(eth_dev, txq);
1588                 } else {
1589                         /* Use default TX function if we get here */
1590                         PMD_INIT_LOG(NOTICE,
1591                                      "No TX queues configured yet. Using default TX function.");
1592                 }
1593
1594                 ixgbe_set_rx_function(eth_dev);
1595
1596                 return 0;
1597         }
1598
1599         rte_atomic32_clear(&ad->link_thread_running);
1600         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1601                               pci_dev->device.devargs);
1602
1603         rte_eth_copy_pci_info(eth_dev, pci_dev);
1604
1605         hw->device_id = pci_dev->id.device_id;
1606         hw->vendor_id = pci_dev->id.vendor_id;
1607         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1608
1609         /* initialize the vfta */
1610         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1611
1612         /* initialize the hw strip bitmap*/
1613         memset(hwstrip, 0, sizeof(*hwstrip));
1614
1615         /* Initialize the shared code (base driver) */
1616         diag = ixgbe_init_shared_code(hw);
1617         if (diag != IXGBE_SUCCESS) {
1618                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1619                 return -EIO;
1620         }
1621
1622         /* init_mailbox_params */
1623         hw->mbx.ops.init_params(hw);
1624
1625         /* Reset the hw statistics */
1626         ixgbevf_dev_stats_reset(eth_dev);
1627
1628         /* Disable the interrupts for VF */
1629         ixgbevf_intr_disable(eth_dev);
1630
1631         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1632         diag = hw->mac.ops.reset_hw(hw);
1633
1634         /*
1635          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1636          * the underlying PF driver has not assigned a MAC address to the VF.
1637          * In this case, assign a random MAC address.
1638          */
1639         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1640                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1641                 /*
1642                  * This error code will be propagated to the app by
1643                  * rte_eth_dev_reset, so use a public error code rather than
1644                  * the internal-only IXGBE_ERR_RESET_FAILED
1645                  */
1646                 return -EAGAIN;
1647         }
1648
1649         /* negotiate mailbox API version to use with the PF. */
1650         ixgbevf_negotiate_api(hw);
1651
1652         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1653         ixgbevf_get_queues(hw, &tcs, &tc);
1654
1655         /* Allocate memory for storing MAC addresses */
1656         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1657                                                hw->mac.num_rar_entries, 0);
1658         if (eth_dev->data->mac_addrs == NULL) {
1659                 PMD_INIT_LOG(ERR,
1660                              "Failed to allocate %u bytes needed to store "
1661                              "MAC addresses",
1662                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1663                 return -ENOMEM;
1664         }
1665
1666         /* Pass the information to the rte_eth_dev_close() that it should also
1667          * release the private port resources.
1668          */
1669         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1670
1671         /* Generate a random MAC address, if none was assigned by PF. */
1672         if (rte_is_zero_ether_addr(perm_addr)) {
1673                 generate_random_mac_addr(perm_addr);
1674                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1675                 if (diag) {
1676                         rte_free(eth_dev->data->mac_addrs);
1677                         eth_dev->data->mac_addrs = NULL;
1678                         return diag;
1679                 }
1680                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1681                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1682                              "%02x:%02x:%02x:%02x:%02x:%02x",
1683                              perm_addr->addr_bytes[0],
1684                              perm_addr->addr_bytes[1],
1685                              perm_addr->addr_bytes[2],
1686                              perm_addr->addr_bytes[3],
1687                              perm_addr->addr_bytes[4],
1688                              perm_addr->addr_bytes[5]);
1689         }
1690
1691         /* Copy the permanent MAC address */
1692         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1693
1694         /* reset the hardware with the new settings */
1695         diag = hw->mac.ops.start_hw(hw);
1696         switch (diag) {
1697         case  0:
1698                 break;
1699
1700         default:
1701                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1702                 return -EIO;
1703         }
1704
1705         rte_intr_callback_register(intr_handle,
1706                                    ixgbevf_dev_interrupt_handler, eth_dev);
1707         rte_intr_enable(intr_handle);
1708         ixgbevf_intr_enable(eth_dev);
1709
1710         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1711                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1712                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1713
1714         return 0;
1715 }
1716
1717 /* Virtual Function device uninit */
1718
1719 static int
1720 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1721 {
1722         PMD_INIT_FUNC_TRACE();
1723
1724         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1725                 return 0;
1726
1727         ixgbevf_dev_close(eth_dev);
1728
1729         return 0;
1730 }
1731
1732 static int
1733 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1734                 struct rte_pci_device *pci_dev)
1735 {
1736         char name[RTE_ETH_NAME_MAX_LEN];
1737         struct rte_eth_dev *pf_ethdev;
1738         struct rte_eth_devargs eth_da;
1739         int i, retval;
1740
1741         if (pci_dev->device.devargs) {
1742                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1743                                 &eth_da);
1744                 if (retval)
1745                         return retval;
1746         } else
1747                 memset(&eth_da, 0, sizeof(eth_da));
1748
1749         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1750                 sizeof(struct ixgbe_adapter),
1751                 eth_dev_pci_specific_init, pci_dev,
1752                 eth_ixgbe_dev_init, NULL);
1753
1754         if (retval || eth_da.nb_representor_ports < 1)
1755                 return retval;
1756
1757         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1758         if (pf_ethdev == NULL)
1759                 return -ENODEV;
1760
1761         /* probe VF representor ports */
1762         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1763                 struct ixgbe_vf_info *vfinfo;
1764                 struct ixgbe_vf_representor representor;
1765
1766                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1767                         pf_ethdev->data->dev_private);
1768                 if (vfinfo == NULL) {
1769                         PMD_DRV_LOG(ERR,
1770                                 "no virtual functions supported by PF");
1771                         break;
1772                 }
1773
1774                 representor.vf_id = eth_da.representor_ports[i];
1775                 representor.switch_domain_id = vfinfo->switch_domain_id;
1776                 representor.pf_ethdev = pf_ethdev;
1777
1778                 /* representor port net_bdf_port */
1779                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1780                         pci_dev->device.name,
1781                         eth_da.representor_ports[i]);
1782
1783                 retval = rte_eth_dev_create(&pci_dev->device, name,
1784                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1785                         ixgbe_vf_representor_init, &representor);
1786
1787                 if (retval)
1788                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1789                                 "representor %s.", name);
1790         }
1791
1792         return 0;
1793 }
1794
1795 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1796 {
1797         struct rte_eth_dev *ethdev;
1798
1799         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1800         if (!ethdev)
1801                 return 0;
1802
1803         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1804                 return rte_eth_dev_pci_generic_remove(pci_dev,
1805                                         ixgbe_vf_representor_uninit);
1806         else
1807                 return rte_eth_dev_pci_generic_remove(pci_dev,
1808                                                 eth_ixgbe_dev_uninit);
1809 }
1810
1811 static struct rte_pci_driver rte_ixgbe_pmd = {
1812         .id_table = pci_id_ixgbe_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1814         .probe = eth_ixgbe_pci_probe,
1815         .remove = eth_ixgbe_pci_remove,
1816 };
1817
1818 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1819         struct rte_pci_device *pci_dev)
1820 {
1821         return rte_eth_dev_pci_generic_probe(pci_dev,
1822                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1823 }
1824
1825 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1826 {
1827         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1828 }
1829
1830 /*
1831  * virtual function driver struct
1832  */
1833 static struct rte_pci_driver rte_ixgbevf_pmd = {
1834         .id_table = pci_id_ixgbevf_map,
1835         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1836         .probe = eth_ixgbevf_pci_probe,
1837         .remove = eth_ixgbevf_pci_remove,
1838 };
1839
1840 static int
1841 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1842 {
1843         struct ixgbe_hw *hw =
1844                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct ixgbe_vfta *shadow_vfta =
1846                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1847         uint32_t vfta;
1848         uint32_t vid_idx;
1849         uint32_t vid_bit;
1850
1851         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1852         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1853         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1854         if (on)
1855                 vfta |= vid_bit;
1856         else
1857                 vfta &= ~vid_bit;
1858         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1859
1860         /* update local VFTA copy */
1861         shadow_vfta->vfta[vid_idx] = vfta;
1862
1863         return 0;
1864 }
1865
1866 static void
1867 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1868 {
1869         if (on)
1870                 ixgbe_vlan_hw_strip_enable(dev, queue);
1871         else
1872                 ixgbe_vlan_hw_strip_disable(dev, queue);
1873 }
1874
1875 static int
1876 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1877                     enum rte_vlan_type vlan_type,
1878                     uint16_t tpid)
1879 {
1880         struct ixgbe_hw *hw =
1881                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882         int ret = 0;
1883         uint32_t reg;
1884         uint32_t qinq;
1885
1886         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1887         qinq &= IXGBE_DMATXCTL_GDV;
1888
1889         switch (vlan_type) {
1890         case ETH_VLAN_TYPE_INNER:
1891                 if (qinq) {
1892                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1893                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1894                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1895                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1896                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1897                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1898                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899                 } else {
1900                         ret = -ENOTSUP;
1901                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1902                                     " by single VLAN");
1903                 }
1904                 break;
1905         case ETH_VLAN_TYPE_OUTER:
1906                 if (qinq) {
1907                         /* Only the high 16-bits is valid */
1908                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1909                                         IXGBE_EXVET_VET_EXT_SHIFT);
1910                 } else {
1911                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1913                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1914                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1915                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1916                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1917                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1918                 }
1919
1920                 break;
1921         default:
1922                 ret = -EINVAL;
1923                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1924                 break;
1925         }
1926
1927         return ret;
1928 }
1929
1930 void
1931 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1932 {
1933         struct ixgbe_hw *hw =
1934                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1935         uint32_t vlnctrl;
1936
1937         PMD_INIT_FUNC_TRACE();
1938
1939         /* Filter Table Disable */
1940         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1941         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1942
1943         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1944 }
1945
1946 void
1947 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1948 {
1949         struct ixgbe_hw *hw =
1950                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1951         struct ixgbe_vfta *shadow_vfta =
1952                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1953         uint32_t vlnctrl;
1954         uint16_t i;
1955
1956         PMD_INIT_FUNC_TRACE();
1957
1958         /* Filter Table Enable */
1959         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1960         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1961         vlnctrl |= IXGBE_VLNCTRL_VFE;
1962
1963         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1964
1965         /* write whatever is in local vfta copy */
1966         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1967                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1968 }
1969
1970 static void
1971 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1972 {
1973         struct ixgbe_hwstrip *hwstrip =
1974                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1975         struct ixgbe_rx_queue *rxq;
1976
1977         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1978                 return;
1979
1980         if (on)
1981                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1982         else
1983                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1984
1985         if (queue >= dev->data->nb_rx_queues)
1986                 return;
1987
1988         rxq = dev->data->rx_queues[queue];
1989
1990         if (on) {
1991                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1992                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1993         } else {
1994                 rxq->vlan_flags = PKT_RX_VLAN;
1995                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1996         }
1997 }
1998
1999 static void
2000 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
2001 {
2002         struct ixgbe_hw *hw =
2003                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2004         uint32_t ctrl;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         if (hw->mac.type == ixgbe_mac_82598EB) {
2009                 /* No queue level support */
2010                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011                 return;
2012         }
2013
2014         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2015         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2016         ctrl &= ~IXGBE_RXDCTL_VME;
2017         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2018
2019         /* record those setting for HW strip per queue */
2020         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
2021 }
2022
2023 static void
2024 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2025 {
2026         struct ixgbe_hw *hw =
2027                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028         uint32_t ctrl;
2029
2030         PMD_INIT_FUNC_TRACE();
2031
2032         if (hw->mac.type == ixgbe_mac_82598EB) {
2033                 /* No queue level supported */
2034                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2035                 return;
2036         }
2037
2038         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2039         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2040         ctrl |= IXGBE_RXDCTL_VME;
2041         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2042
2043         /* record those setting for HW strip per queue */
2044         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2045 }
2046
2047 static void
2048 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2049 {
2050         struct ixgbe_hw *hw =
2051                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2052         uint32_t ctrl;
2053
2054         PMD_INIT_FUNC_TRACE();
2055
2056         /* DMATXCTRL: Geric Double VLAN Disable */
2057         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2058         ctrl &= ~IXGBE_DMATXCTL_GDV;
2059         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2060
2061         /* CTRL_EXT: Global Double VLAN Disable */
2062         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2063         ctrl &= ~IXGBE_EXTENDED_VLAN;
2064         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2065
2066 }
2067
2068 static void
2069 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2070 {
2071         struct ixgbe_hw *hw =
2072                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2073         uint32_t ctrl;
2074
2075         PMD_INIT_FUNC_TRACE();
2076
2077         /* DMATXCTRL: Geric Double VLAN Enable */
2078         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2079         ctrl |= IXGBE_DMATXCTL_GDV;
2080         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2081
2082         /* CTRL_EXT: Global Double VLAN Enable */
2083         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2084         ctrl |= IXGBE_EXTENDED_VLAN;
2085         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2086
2087         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2088         if (hw->mac.type == ixgbe_mac_X550 ||
2089             hw->mac.type == ixgbe_mac_X550EM_x ||
2090             hw->mac.type == ixgbe_mac_X550EM_a) {
2091                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2092                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2093                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2094         }
2095
2096         /*
2097          * VET EXT field in the EXVET register = 0x8100 by default
2098          * So no need to change. Same to VT field of DMATXCTL register
2099          */
2100 }
2101
2102 void
2103 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2104 {
2105         struct ixgbe_hw *hw =
2106                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2108         uint32_t ctrl;
2109         uint16_t i;
2110         struct ixgbe_rx_queue *rxq;
2111         bool on;
2112
2113         PMD_INIT_FUNC_TRACE();
2114
2115         if (hw->mac.type == ixgbe_mac_82598EB) {
2116                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2117                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2118                         ctrl |= IXGBE_VLNCTRL_VME;
2119                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2120                 } else {
2121                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2122                         ctrl &= ~IXGBE_VLNCTRL_VME;
2123                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2124                 }
2125         } else {
2126                 /*
2127                  * Other 10G NIC, the VLAN strip can be setup
2128                  * per queue in RXDCTL
2129                  */
2130                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2131                         rxq = dev->data->rx_queues[i];
2132                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2133                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2134                                 ctrl |= IXGBE_RXDCTL_VME;
2135                                 on = TRUE;
2136                         } else {
2137                                 ctrl &= ~IXGBE_RXDCTL_VME;
2138                                 on = FALSE;
2139                         }
2140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2141
2142                         /* record those setting for HW strip per queue */
2143                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2144                 }
2145         }
2146 }
2147
2148 static void
2149 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2150 {
2151         uint16_t i;
2152         struct rte_eth_rxmode *rxmode;
2153         struct ixgbe_rx_queue *rxq;
2154
2155         if (mask & ETH_VLAN_STRIP_MASK) {
2156                 rxmode = &dev->data->dev_conf.rxmode;
2157                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2158                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                                 rxq = dev->data->rx_queues[i];
2160                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2161                         }
2162                 else
2163                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2164                                 rxq = dev->data->rx_queues[i];
2165                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2166                         }
2167         }
2168 }
2169
2170 static int
2171 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2172 {
2173         struct rte_eth_rxmode *rxmode;
2174         rxmode = &dev->data->dev_conf.rxmode;
2175
2176         if (mask & ETH_VLAN_STRIP_MASK) {
2177                 ixgbe_vlan_hw_strip_config(dev);
2178         }
2179
2180         if (mask & ETH_VLAN_FILTER_MASK) {
2181                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2182                         ixgbe_vlan_hw_filter_enable(dev);
2183                 else
2184                         ixgbe_vlan_hw_filter_disable(dev);
2185         }
2186
2187         if (mask & ETH_VLAN_EXTEND_MASK) {
2188                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2189                         ixgbe_vlan_hw_extend_enable(dev);
2190                 else
2191                         ixgbe_vlan_hw_extend_disable(dev);
2192         }
2193
2194         return 0;
2195 }
2196
2197 static int
2198 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2199 {
2200         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2201
2202         ixgbe_vlan_offload_config(dev, mask);
2203
2204         return 0;
2205 }
2206
2207 static void
2208 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2209 {
2210         struct ixgbe_hw *hw =
2211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2212         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2213         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2214
2215         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2216         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2217 }
2218
2219 static int
2220 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2221 {
2222         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2223
2224         switch (nb_rx_q) {
2225         case 1:
2226         case 2:
2227                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2228                 break;
2229         case 4:
2230                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2231                 break;
2232         default:
2233                 return -EINVAL;
2234         }
2235
2236         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2237                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2238         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2239                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2240         return 0;
2241 }
2242
2243 static int
2244 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2245 {
2246         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2247         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2248         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2249         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2250
2251         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2252                 /* check multi-queue mode */
2253                 switch (dev_conf->rxmode.mq_mode) {
2254                 case ETH_MQ_RX_VMDQ_DCB:
2255                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2256                         break;
2257                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2258                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2259                         PMD_INIT_LOG(ERR, "SRIOV active,"
2260                                         " unsupported mq_mode rx %d.",
2261                                         dev_conf->rxmode.mq_mode);
2262                         return -EINVAL;
2263                 case ETH_MQ_RX_RSS:
2264                 case ETH_MQ_RX_VMDQ_RSS:
2265                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2266                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2267                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2268                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2269                                                 " invalid queue number"
2270                                                 " for VMDQ RSS, allowed"
2271                                                 " value are 1, 2 or 4.");
2272                                         return -EINVAL;
2273                                 }
2274                         break;
2275                 case ETH_MQ_RX_VMDQ_ONLY:
2276                 case ETH_MQ_RX_NONE:
2277                         /* if nothing mq mode configure, use default scheme */
2278                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2279                         break;
2280                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2281                         /* SRIOV only works in VMDq enable mode */
2282                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2283                                         " wrong mq_mode rx %d.",
2284                                         dev_conf->rxmode.mq_mode);
2285                         return -EINVAL;
2286                 }
2287
2288                 switch (dev_conf->txmode.mq_mode) {
2289                 case ETH_MQ_TX_VMDQ_DCB:
2290                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2291                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2292                         break;
2293                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2294                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2295                         break;
2296                 }
2297
2298                 /* check valid queue number */
2299                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2300                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2301                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2302                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2303                                         " must be less than or equal to %d.",
2304                                         nb_rx_q, nb_tx_q,
2305                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2306                         return -EINVAL;
2307                 }
2308         } else {
2309                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2310                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2311                                           " not supported.");
2312                         return -EINVAL;
2313                 }
2314                 /* check configuration for vmdb+dcb mode */
2315                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2316                         const struct rte_eth_vmdq_dcb_conf *conf;
2317
2318                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2319                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2320                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2321                                 return -EINVAL;
2322                         }
2323                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2324                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2325                                conf->nb_queue_pools == ETH_32_POOLS)) {
2326                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2327                                                 " nb_queue_pools must be %d or %d.",
2328                                                 ETH_16_POOLS, ETH_32_POOLS);
2329                                 return -EINVAL;
2330                         }
2331                 }
2332                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2333                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2334
2335                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2336                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2337                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2338                                 return -EINVAL;
2339                         }
2340                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2341                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2342                                conf->nb_queue_pools == ETH_32_POOLS)) {
2343                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2344                                                 " nb_queue_pools != %d and"
2345                                                 " nb_queue_pools != %d.",
2346                                                 ETH_16_POOLS, ETH_32_POOLS);
2347                                 return -EINVAL;
2348                         }
2349                 }
2350
2351                 /* For DCB mode check our configuration before we go further */
2352                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2353                         const struct rte_eth_dcb_rx_conf *conf;
2354
2355                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2356                         if (!(conf->nb_tcs == ETH_4_TCS ||
2357                                conf->nb_tcs == ETH_8_TCS)) {
2358                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2359                                                 " and nb_tcs != %d.",
2360                                                 ETH_4_TCS, ETH_8_TCS);
2361                                 return -EINVAL;
2362                         }
2363                 }
2364
2365                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2366                         const struct rte_eth_dcb_tx_conf *conf;
2367
2368                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2369                         if (!(conf->nb_tcs == ETH_4_TCS ||
2370                                conf->nb_tcs == ETH_8_TCS)) {
2371                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2372                                                 " and nb_tcs != %d.",
2373                                                 ETH_4_TCS, ETH_8_TCS);
2374                                 return -EINVAL;
2375                         }
2376                 }
2377
2378                 /*
2379                  * When DCB/VT is off, maximum number of queues changes,
2380                  * except for 82598EB, which remains constant.
2381                  */
2382                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2383                                 hw->mac.type != ixgbe_mac_82598EB) {
2384                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2385                                 PMD_INIT_LOG(ERR,
2386                                              "Neither VT nor DCB are enabled, "
2387                                              "nb_tx_q > %d.",
2388                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2389                                 return -EINVAL;
2390                         }
2391                 }
2392         }
2393         return 0;
2394 }
2395
2396 static int
2397 ixgbe_dev_configure(struct rte_eth_dev *dev)
2398 {
2399         struct ixgbe_interrupt *intr =
2400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2401         struct ixgbe_adapter *adapter = dev->data->dev_private;
2402         int ret;
2403
2404         PMD_INIT_FUNC_TRACE();
2405
2406         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2407                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2408
2409         /* multipe queue mode checking */
2410         ret  = ixgbe_check_mq_mode(dev);
2411         if (ret != 0) {
2412                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2413                             ret);
2414                 return ret;
2415         }
2416
2417         /* set flag to update link status after init */
2418         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2419
2420         /*
2421          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2422          * allocation or vector Rx preconditions we will reset it.
2423          */
2424         adapter->rx_bulk_alloc_allowed = true;
2425         adapter->rx_vec_allowed = true;
2426
2427         return 0;
2428 }
2429
2430 static void
2431 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2432 {
2433         struct ixgbe_hw *hw =
2434                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435         struct ixgbe_interrupt *intr =
2436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2437         uint32_t gpie;
2438
2439         /* only set up it on X550EM_X */
2440         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2441                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2442                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2443                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2444                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2445                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2446         }
2447 }
2448
2449 int
2450 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2451                         uint16_t tx_rate, uint64_t q_msk)
2452 {
2453         struct ixgbe_hw *hw;
2454         struct ixgbe_vf_info *vfinfo;
2455         struct rte_eth_link link;
2456         uint8_t  nb_q_per_pool;
2457         uint32_t queue_stride;
2458         uint32_t queue_idx, idx = 0, vf_idx;
2459         uint32_t queue_end;
2460         uint16_t total_rate = 0;
2461         struct rte_pci_device *pci_dev;
2462         int ret;
2463
2464         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2465         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2466         if (ret < 0)
2467                 return ret;
2468
2469         if (vf >= pci_dev->max_vfs)
2470                 return -EINVAL;
2471
2472         if (tx_rate > link.link_speed)
2473                 return -EINVAL;
2474
2475         if (q_msk == 0)
2476                 return 0;
2477
2478         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2479         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2480         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2481         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2482         queue_idx = vf * queue_stride;
2483         queue_end = queue_idx + nb_q_per_pool - 1;
2484         if (queue_end >= hw->mac.max_tx_queues)
2485                 return -EINVAL;
2486
2487         if (vfinfo) {
2488                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2489                         if (vf_idx == vf)
2490                                 continue;
2491                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2492                                 idx++)
2493                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2494                 }
2495         } else {
2496                 return -EINVAL;
2497         }
2498
2499         /* Store tx_rate for this vf. */
2500         for (idx = 0; idx < nb_q_per_pool; idx++) {
2501                 if (((uint64_t)0x1 << idx) & q_msk) {
2502                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2503                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2504                         total_rate += tx_rate;
2505                 }
2506         }
2507
2508         if (total_rate > dev->data->dev_link.link_speed) {
2509                 /* Reset stored TX rate of the VF if it causes exceed
2510                  * link speed.
2511                  */
2512                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2513                 return -EINVAL;
2514         }
2515
2516         /* Set RTTBCNRC of each queue/pool for vf X  */
2517         for (; queue_idx <= queue_end; queue_idx++) {
2518                 if (0x1 & q_msk)
2519                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2520                 q_msk = q_msk >> 1;
2521         }
2522
2523         return 0;
2524 }
2525
2526 static int
2527 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2528 {
2529         struct ixgbe_adapter *adapter = dev->data->dev_private;
2530         int err;
2531         uint32_t mflcn;
2532
2533         ixgbe_setup_fc(hw);
2534
2535         err = ixgbe_fc_enable(hw);
2536
2537         /* Not negotiated is not an error case */
2538         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2539                 /*
2540                  *check if we want to forward MAC frames - driver doesn't
2541                  *have native capability to do that,
2542                  *so we'll write the registers ourselves
2543                  */
2544
2545                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2546
2547                 /* set or clear MFLCN.PMCF bit depending on configuration */
2548                 if (adapter->mac_ctrl_frame_fwd != 0)
2549                         mflcn |= IXGBE_MFLCN_PMCF;
2550                 else
2551                         mflcn &= ~IXGBE_MFLCN_PMCF;
2552
2553                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2554                 IXGBE_WRITE_FLUSH(hw);
2555
2556                 return 0;
2557         }
2558         return err;
2559 }
2560
2561 /*
2562  * Configure device link speed and setup link.
2563  * It returns 0 on success.
2564  */
2565 static int
2566 ixgbe_dev_start(struct rte_eth_dev *dev)
2567 {
2568         struct ixgbe_hw *hw =
2569                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570         struct ixgbe_vf_info *vfinfo =
2571                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2572         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2574         uint32_t intr_vector = 0;
2575         int err;
2576         bool link_up = false, negotiate = 0;
2577         uint32_t speed = 0;
2578         uint32_t allowed_speeds = 0;
2579         int mask = 0;
2580         int status;
2581         uint16_t vf, idx;
2582         uint32_t *link_speeds;
2583         struct ixgbe_tm_conf *tm_conf =
2584                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2585         struct ixgbe_macsec_setting *macsec_setting =
2586                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2587
2588         PMD_INIT_FUNC_TRACE();
2589
2590         /* Stop the link setup handler before resetting the HW. */
2591         ixgbe_dev_wait_setup_link_complete(dev, 0);
2592
2593         /* disable uio/vfio intr/eventfd mapping */
2594         rte_intr_disable(intr_handle);
2595
2596         /* stop adapter */
2597         hw->adapter_stopped = 0;
2598         ixgbe_stop_adapter(hw);
2599
2600         /* reinitialize adapter
2601          * this calls reset and start
2602          */
2603         status = ixgbe_pf_reset_hw(hw);
2604         if (status != 0)
2605                 return -1;
2606         hw->mac.ops.start_hw(hw);
2607         hw->mac.get_link_status = true;
2608
2609         /* configure PF module if SRIOV enabled */
2610         ixgbe_pf_host_configure(dev);
2611
2612         ixgbe_dev_phy_intr_setup(dev);
2613
2614         /* check and configure queue intr-vector mapping */
2615         if ((rte_intr_cap_multiple(intr_handle) ||
2616              !RTE_ETH_DEV_SRIOV(dev).active) &&
2617             dev->data->dev_conf.intr_conf.rxq != 0) {
2618                 intr_vector = dev->data->nb_rx_queues;
2619                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2620                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2621                                         IXGBE_MAX_INTR_QUEUE_NUM);
2622                         return -ENOTSUP;
2623                 }
2624                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2625                         return -1;
2626         }
2627
2628         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2629                 intr_handle->intr_vec =
2630                         rte_zmalloc("intr_vec",
2631                                     dev->data->nb_rx_queues * sizeof(int), 0);
2632                 if (intr_handle->intr_vec == NULL) {
2633                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2634                                      " intr_vec", dev->data->nb_rx_queues);
2635                         return -ENOMEM;
2636                 }
2637         }
2638
2639         /* confiugre msix for sleep until rx interrupt */
2640         ixgbe_configure_msix(dev);
2641
2642         /* initialize transmission unit */
2643         ixgbe_dev_tx_init(dev);
2644
2645         /* This can fail when allocating mbufs for descriptor rings */
2646         err = ixgbe_dev_rx_init(dev);
2647         if (err) {
2648                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2649                 goto error;
2650         }
2651
2652         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2653                 ETH_VLAN_EXTEND_MASK;
2654         err = ixgbe_vlan_offload_config(dev, mask);
2655         if (err) {
2656                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2657                 goto error;
2658         }
2659
2660         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2661                 /* Enable vlan filtering for VMDq */
2662                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2663         }
2664
2665         /* Configure DCB hw */
2666         ixgbe_configure_dcb(dev);
2667
2668         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2669                 err = ixgbe_fdir_configure(dev);
2670                 if (err)
2671                         goto error;
2672         }
2673
2674         /* Restore vf rate limit */
2675         if (vfinfo != NULL) {
2676                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2677                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2678                                 if (vfinfo[vf].tx_rate[idx] != 0)
2679                                         ixgbe_set_vf_rate_limit(
2680                                                 dev, vf,
2681                                                 vfinfo[vf].tx_rate[idx],
2682                                                 1 << idx);
2683         }
2684
2685         ixgbe_restore_statistics_mapping(dev);
2686
2687         err = ixgbe_flow_ctrl_enable(dev, hw);
2688         if (err < 0) {
2689                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2690                 goto error;
2691         }
2692
2693         err = ixgbe_dev_rxtx_start(dev);
2694         if (err < 0) {
2695                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2696                 goto error;
2697         }
2698
2699         /* Skip link setup if loopback mode is enabled. */
2700         if (dev->data->dev_conf.lpbk_mode != 0) {
2701                 err = ixgbe_check_supported_loopback_mode(dev);
2702                 if (err < 0) {
2703                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2704                         goto error;
2705                 } else {
2706                         goto skip_link_setup;
2707                 }
2708         }
2709
2710         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2711                 err = hw->mac.ops.setup_sfp(hw);
2712                 if (err)
2713                         goto error;
2714         }
2715
2716         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2717                 /* Turn on the copper */
2718                 ixgbe_set_phy_power(hw, true);
2719         } else {
2720                 /* Turn on the laser */
2721                 ixgbe_enable_tx_laser(hw);
2722         }
2723
2724         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2725         if (err)
2726                 goto error;
2727         dev->data->dev_link.link_status = link_up;
2728
2729         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2730         if (err)
2731                 goto error;
2732
2733         switch (hw->mac.type) {
2734         case ixgbe_mac_X550:
2735         case ixgbe_mac_X550EM_x:
2736         case ixgbe_mac_X550EM_a:
2737                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2738                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2739                         ETH_LINK_SPEED_10G;
2740                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2741                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2742                         allowed_speeds = ETH_LINK_SPEED_10M |
2743                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2744                 break;
2745         default:
2746                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2747                         ETH_LINK_SPEED_10G;
2748         }
2749
2750         link_speeds = &dev->data->dev_conf.link_speeds;
2751
2752         /* Ignore autoneg flag bit and check the validity of
2753          * link_speed
2754          */
2755         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2756                 PMD_INIT_LOG(ERR, "Invalid link setting");
2757                 goto error;
2758         }
2759
2760         speed = 0x0;
2761         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2762                 switch (hw->mac.type) {
2763                 case ixgbe_mac_82598EB:
2764                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2765                         break;
2766                 case ixgbe_mac_82599EB:
2767                 case ixgbe_mac_X540:
2768                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2769                         break;
2770                 case ixgbe_mac_X550:
2771                 case ixgbe_mac_X550EM_x:
2772                 case ixgbe_mac_X550EM_a:
2773                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2774                         break;
2775                 default:
2776                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2777                 }
2778         } else {
2779                 if (*link_speeds & ETH_LINK_SPEED_10G)
2780                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2781                 if (*link_speeds & ETH_LINK_SPEED_5G)
2782                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2783                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2784                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2785                 if (*link_speeds & ETH_LINK_SPEED_1G)
2786                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2787                 if (*link_speeds & ETH_LINK_SPEED_100M)
2788                         speed |= IXGBE_LINK_SPEED_100_FULL;
2789                 if (*link_speeds & ETH_LINK_SPEED_10M)
2790                         speed |= IXGBE_LINK_SPEED_10_FULL;
2791         }
2792
2793         err = ixgbe_setup_link(hw, speed, link_up);
2794         if (err)
2795                 goto error;
2796
2797 skip_link_setup:
2798
2799         if (rte_intr_allow_others(intr_handle)) {
2800                 /* check if lsc interrupt is enabled */
2801                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2802                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2803                 else
2804                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2805                 ixgbe_dev_macsec_interrupt_setup(dev);
2806         } else {
2807                 rte_intr_callback_unregister(intr_handle,
2808                                              ixgbe_dev_interrupt_handler, dev);
2809                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2810                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2811                                      " no intr multiplex");
2812         }
2813
2814         /* check if rxq interrupt is enabled */
2815         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2816             rte_intr_dp_is_en(intr_handle))
2817                 ixgbe_dev_rxq_interrupt_setup(dev);
2818
2819         /* enable uio/vfio intr/eventfd mapping */
2820         rte_intr_enable(intr_handle);
2821
2822         /* resume enabled intr since hw reset */
2823         ixgbe_enable_intr(dev);
2824         ixgbe_l2_tunnel_conf(dev);
2825         ixgbe_filter_restore(dev);
2826
2827         if (tm_conf->root && !tm_conf->committed)
2828                 PMD_DRV_LOG(WARNING,
2829                             "please call hierarchy_commit() "
2830                             "before starting the port");
2831
2832         /* wait for the controller to acquire link */
2833         err = ixgbe_wait_for_link_up(hw);
2834         if (err)
2835                 goto error;
2836
2837         /*
2838          * Update link status right before return, because it may
2839          * start link configuration process in a separate thread.
2840          */
2841         ixgbe_dev_link_update(dev, 0);
2842
2843         /* setup the macsec setting register */
2844         if (macsec_setting->offload_en)
2845                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2846
2847         return 0;
2848
2849 error:
2850         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2851         ixgbe_dev_clear_queues(dev);
2852         return -EIO;
2853 }
2854
2855 /*
2856  * Stop device: disable rx and tx functions to allow for reconfiguring.
2857  */
2858 static void
2859 ixgbe_dev_stop(struct rte_eth_dev *dev)
2860 {
2861         struct rte_eth_link link;
2862         struct ixgbe_adapter *adapter = dev->data->dev_private;
2863         struct ixgbe_hw *hw =
2864                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865         struct ixgbe_vf_info *vfinfo =
2866                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2869         int vf;
2870         struct ixgbe_tm_conf *tm_conf =
2871                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2872
2873         if (hw->adapter_stopped)
2874                 return;
2875
2876         PMD_INIT_FUNC_TRACE();
2877
2878         ixgbe_dev_wait_setup_link_complete(dev, 0);
2879
2880         /* disable interrupts */
2881         ixgbe_disable_intr(hw);
2882
2883         /* reset the NIC */
2884         ixgbe_pf_reset_hw(hw);
2885         hw->adapter_stopped = 0;
2886
2887         /* stop adapter */
2888         ixgbe_stop_adapter(hw);
2889
2890         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2891                 vfinfo[vf].clear_to_send = false;
2892
2893         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2894                 /* Turn off the copper */
2895                 ixgbe_set_phy_power(hw, false);
2896         } else {
2897                 /* Turn off the laser */
2898                 ixgbe_disable_tx_laser(hw);
2899         }
2900
2901         ixgbe_dev_clear_queues(dev);
2902
2903         /* Clear stored conf */
2904         dev->data->scattered_rx = 0;
2905         dev->data->lro = 0;
2906
2907         /* Clear recorded link status */
2908         memset(&link, 0, sizeof(link));
2909         rte_eth_linkstatus_set(dev, &link);
2910
2911         if (!rte_intr_allow_others(intr_handle))
2912                 /* resume to the default handler */
2913                 rte_intr_callback_register(intr_handle,
2914                                            ixgbe_dev_interrupt_handler,
2915                                            (void *)dev);
2916
2917         /* Clean datapath event and queue/vec mapping */
2918         rte_intr_efd_disable(intr_handle);
2919         if (intr_handle->intr_vec != NULL) {
2920                 rte_free(intr_handle->intr_vec);
2921                 intr_handle->intr_vec = NULL;
2922         }
2923
2924         /* reset hierarchy commit */
2925         tm_conf->committed = false;
2926
2927         adapter->rss_reta_updated = 0;
2928
2929         hw->adapter_stopped = true;
2930 }
2931
2932 /*
2933  * Set device link up: enable tx.
2934  */
2935 static int
2936 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2937 {
2938         struct ixgbe_hw *hw =
2939                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940         if (hw->mac.type == ixgbe_mac_82599EB) {
2941 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2942                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2943                         /* Not suported in bypass mode */
2944                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2945                                      "by device id 0x%x", hw->device_id);
2946                         return -ENOTSUP;
2947                 }
2948 #endif
2949         }
2950
2951         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2952                 /* Turn on the copper */
2953                 ixgbe_set_phy_power(hw, true);
2954         } else {
2955                 /* Turn on the laser */
2956                 ixgbe_enable_tx_laser(hw);
2957                 ixgbe_dev_link_update(dev, 0);
2958         }
2959
2960         return 0;
2961 }
2962
2963 /*
2964  * Set device link down: disable tx.
2965  */
2966 static int
2967 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2968 {
2969         struct ixgbe_hw *hw =
2970                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2971         if (hw->mac.type == ixgbe_mac_82599EB) {
2972 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2973                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2974                         /* Not suported in bypass mode */
2975                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2976                                      "by device id 0x%x", hw->device_id);
2977                         return -ENOTSUP;
2978                 }
2979 #endif
2980         }
2981
2982         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2983                 /* Turn off the copper */
2984                 ixgbe_set_phy_power(hw, false);
2985         } else {
2986                 /* Turn off the laser */
2987                 ixgbe_disable_tx_laser(hw);
2988                 ixgbe_dev_link_update(dev, 0);
2989         }
2990
2991         return 0;
2992 }
2993
2994 /*
2995  * Reset and stop device.
2996  */
2997 static void
2998 ixgbe_dev_close(struct rte_eth_dev *dev)
2999 {
3000         struct ixgbe_hw *hw =
3001                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3002         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3003         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3004         int retries = 0;
3005         int ret;
3006
3007         PMD_INIT_FUNC_TRACE();
3008
3009         ixgbe_pf_reset_hw(hw);
3010
3011         ixgbe_dev_stop(dev);
3012
3013         ixgbe_dev_free_queues(dev);
3014
3015         ixgbe_disable_pcie_master(hw);
3016
3017         /* reprogram the RAR[0] in case user changed it. */
3018         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3019
3020         dev->dev_ops = NULL;
3021         dev->rx_pkt_burst = NULL;
3022         dev->tx_pkt_burst = NULL;
3023
3024         /* Unlock any pending hardware semaphore */
3025         ixgbe_swfw_lock_reset(hw);
3026
3027         /* disable uio intr before callback unregister */
3028         rte_intr_disable(intr_handle);
3029
3030         do {
3031                 ret = rte_intr_callback_unregister(intr_handle,
3032                                 ixgbe_dev_interrupt_handler, dev);
3033                 if (ret >= 0 || ret == -ENOENT) {
3034                         break;
3035                 } else if (ret != -EAGAIN) {
3036                         PMD_INIT_LOG(ERR,
3037                                 "intr callback unregister failed: %d",
3038                                 ret);
3039                 }
3040                 rte_delay_ms(100);
3041         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3042
3043         /* cancel the delay handler before remove dev */
3044         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3045
3046         /* uninitialize PF if max_vfs not zero */
3047         ixgbe_pf_host_uninit(dev);
3048
3049         /* remove all the fdir filters & hash */
3050         ixgbe_fdir_filter_uninit(dev);
3051
3052         /* remove all the L2 tunnel filters & hash */
3053         ixgbe_l2_tn_filter_uninit(dev);
3054
3055         /* Remove all ntuple filters of the device */
3056         ixgbe_ntuple_filter_uninit(dev);
3057
3058         /* clear all the filters list */
3059         ixgbe_filterlist_flush();
3060
3061         /* Remove all Traffic Manager configuration */
3062         ixgbe_tm_conf_uninit(dev);
3063
3064 #ifdef RTE_LIBRTE_SECURITY
3065         rte_free(dev->security_ctx);
3066 #endif
3067
3068 }
3069
3070 /*
3071  * Reset PF device.
3072  */
3073 static int
3074 ixgbe_dev_reset(struct rte_eth_dev *dev)
3075 {
3076         int ret;
3077
3078         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3079          * its VF to make them align with it. The detailed notification
3080          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3081          * To avoid unexpected behavior in VF, currently reset of PF with
3082          * SR-IOV activation is not supported. It might be supported later.
3083          */
3084         if (dev->data->sriov.active)
3085                 return -ENOTSUP;
3086
3087         ret = eth_ixgbe_dev_uninit(dev);
3088         if (ret)
3089                 return ret;
3090
3091         ret = eth_ixgbe_dev_init(dev, NULL);
3092
3093         return ret;
3094 }
3095
3096 static void
3097 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3098                            struct ixgbe_hw_stats *hw_stats,
3099                            struct ixgbe_macsec_stats *macsec_stats,
3100                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3101                            uint64_t *total_qprc, uint64_t *total_qprdc)
3102 {
3103         uint32_t bprc, lxon, lxoff, total;
3104         uint32_t delta_gprc = 0;
3105         unsigned i;
3106         /* Workaround for RX byte count not including CRC bytes when CRC
3107          * strip is enabled. CRC bytes are removed from counters when crc_strip
3108          * is disabled.
3109          */
3110         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3111                         IXGBE_HLREG0_RXCRCSTRP);
3112
3113         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3114         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3115         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3116         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3117
3118         for (i = 0; i < 8; i++) {
3119                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3120
3121                 /* global total per queue */
3122                 hw_stats->mpc[i] += mp;
3123                 /* Running comprehensive total for stats display */
3124                 *total_missed_rx += hw_stats->mpc[i];
3125                 if (hw->mac.type == ixgbe_mac_82598EB) {
3126                         hw_stats->rnbc[i] +=
3127                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3128                         hw_stats->pxonrxc[i] +=
3129                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3130                         hw_stats->pxoffrxc[i] +=
3131                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3132                 } else {
3133                         hw_stats->pxonrxc[i] +=
3134                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3135                         hw_stats->pxoffrxc[i] +=
3136                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3137                         hw_stats->pxon2offc[i] +=
3138                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3139                 }
3140                 hw_stats->pxontxc[i] +=
3141                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3142                 hw_stats->pxofftxc[i] +=
3143                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3144         }
3145         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3146                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3147                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3148                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3149
3150                 delta_gprc += delta_qprc;
3151
3152                 hw_stats->qprc[i] += delta_qprc;
3153                 hw_stats->qptc[i] += delta_qptc;
3154
3155                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3156                 hw_stats->qbrc[i] +=
3157                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3158                 if (crc_strip == 0)
3159                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3160
3161                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3162                 hw_stats->qbtc[i] +=
3163                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3164
3165                 hw_stats->qprdc[i] += delta_qprdc;
3166                 *total_qprdc += hw_stats->qprdc[i];
3167
3168                 *total_qprc += hw_stats->qprc[i];
3169                 *total_qbrc += hw_stats->qbrc[i];
3170         }
3171         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3172         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3173         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3174
3175         /*
3176          * An errata states that gprc actually counts good + missed packets:
3177          * Workaround to set gprc to summated queue packet receives
3178          */
3179         hw_stats->gprc = *total_qprc;
3180
3181         if (hw->mac.type != ixgbe_mac_82598EB) {
3182                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3183                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3184                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3185                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3186                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3187                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3188                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3189                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3190         } else {
3191                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3192                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3193                 /* 82598 only has a counter in the high register */
3194                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3195                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3196                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3197         }
3198         uint64_t old_tpr = hw_stats->tpr;
3199
3200         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3201         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3202
3203         if (crc_strip == 0)
3204                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3205
3206         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3207         hw_stats->gptc += delta_gptc;
3208         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3209         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3210
3211         /*
3212          * Workaround: mprc hardware is incorrectly counting
3213          * broadcasts, so for now we subtract those.
3214          */
3215         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3216         hw_stats->bprc += bprc;
3217         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3218         if (hw->mac.type == ixgbe_mac_82598EB)
3219                 hw_stats->mprc -= bprc;
3220
3221         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3222         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3223         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3224         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3225         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3226         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3227
3228         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3229         hw_stats->lxontxc += lxon;
3230         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3231         hw_stats->lxofftxc += lxoff;
3232         total = lxon + lxoff;
3233
3234         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3235         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3236         hw_stats->gptc -= total;
3237         hw_stats->mptc -= total;
3238         hw_stats->ptc64 -= total;
3239         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3240
3241         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3242         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3243         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3244         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3245         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3246         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3247         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3248         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3249         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3250         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3251         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3252         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3253         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3254         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3255         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3256         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3257         /* Only read FCOE on 82599 */
3258         if (hw->mac.type != ixgbe_mac_82598EB) {
3259                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3260                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3261                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3262                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3263                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3264         }
3265
3266         /* Flow Director Stats registers */
3267         if (hw->mac.type != ixgbe_mac_82598EB) {
3268                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3269                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3270                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3271                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3272                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3273                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3274                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3275                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3276                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3277                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3278         }
3279         /* MACsec Stats registers */
3280         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3281         macsec_stats->out_pkts_encrypted +=
3282                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3283         macsec_stats->out_pkts_protected +=
3284                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3285         macsec_stats->out_octets_encrypted +=
3286                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3287         macsec_stats->out_octets_protected +=
3288                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3289         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3290         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3291         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3292         macsec_stats->in_pkts_unknownsci +=
3293                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3294         macsec_stats->in_octets_decrypted +=
3295                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3296         macsec_stats->in_octets_validated +=
3297                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3298         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3299         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3300         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3301         for (i = 0; i < 2; i++) {
3302                 macsec_stats->in_pkts_ok +=
3303                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3304                 macsec_stats->in_pkts_invalid +=
3305                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3306                 macsec_stats->in_pkts_notvalid +=
3307                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3308         }
3309         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3310         macsec_stats->in_pkts_notusingsa +=
3311                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3312 }
3313
3314 /*
3315  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3316  */
3317 static int
3318 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3319 {
3320         struct ixgbe_hw *hw =
3321                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322         struct ixgbe_hw_stats *hw_stats =
3323                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3324         struct ixgbe_macsec_stats *macsec_stats =
3325                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3326                                 dev->data->dev_private);
3327         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3328         unsigned i;
3329
3330         total_missed_rx = 0;
3331         total_qbrc = 0;
3332         total_qprc = 0;
3333         total_qprdc = 0;
3334
3335         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3336                         &total_qbrc, &total_qprc, &total_qprdc);
3337
3338         if (stats == NULL)
3339                 return -EINVAL;
3340
3341         /* Fill out the rte_eth_stats statistics structure */
3342         stats->ipackets = total_qprc;
3343         stats->ibytes = total_qbrc;
3344         stats->opackets = hw_stats->gptc;
3345         stats->obytes = hw_stats->gotc;
3346
3347         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3348                 stats->q_ipackets[i] = hw_stats->qprc[i];
3349                 stats->q_opackets[i] = hw_stats->qptc[i];
3350                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3351                 stats->q_obytes[i] = hw_stats->qbtc[i];
3352                 stats->q_errors[i] = hw_stats->qprdc[i];
3353         }
3354
3355         /* Rx Errors */
3356         stats->imissed  = total_missed_rx;
3357         stats->ierrors  = hw_stats->crcerrs +
3358                           hw_stats->mspdc +
3359                           hw_stats->rlec +
3360                           hw_stats->ruc +
3361                           hw_stats->roc +
3362                           hw_stats->illerrc +
3363                           hw_stats->errbc +
3364                           hw_stats->rfc +
3365                           hw_stats->fccrc +
3366                           hw_stats->fclast;
3367
3368         /* Tx Errors */
3369         stats->oerrors  = 0;
3370         return 0;
3371 }
3372
3373 static int
3374 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3375 {
3376         struct ixgbe_hw_stats *stats =
3377                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3378
3379         /* HW registers are cleared on read */
3380         ixgbe_dev_stats_get(dev, NULL);
3381
3382         /* Reset software totals */
3383         memset(stats, 0, sizeof(*stats));
3384
3385         return 0;
3386 }
3387
3388 /* This function calculates the number of xstats based on the current config */
3389 static unsigned
3390 ixgbe_xstats_calc_num(void) {
3391         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3392                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3393                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3394 }
3395
3396 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3397         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3398 {
3399         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3400         unsigned stat, i, count;
3401
3402         if (xstats_names != NULL) {
3403                 count = 0;
3404
3405                 /* Note: limit >= cnt_stats checked upstream
3406                  * in rte_eth_xstats_names()
3407                  */
3408
3409                 /* Extended stats from ixgbe_hw_stats */
3410                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3411                         strlcpy(xstats_names[count].name,
3412                                 rte_ixgbe_stats_strings[i].name,
3413                                 sizeof(xstats_names[count].name));
3414                         count++;
3415                 }
3416
3417                 /* MACsec Stats */
3418                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3419                         strlcpy(xstats_names[count].name,
3420                                 rte_ixgbe_macsec_strings[i].name,
3421                                 sizeof(xstats_names[count].name));
3422                         count++;
3423                 }
3424
3425                 /* RX Priority Stats */
3426                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3427                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3428                                 snprintf(xstats_names[count].name,
3429                                         sizeof(xstats_names[count].name),
3430                                         "rx_priority%u_%s", i,
3431                                         rte_ixgbe_rxq_strings[stat].name);
3432                                 count++;
3433                         }
3434                 }
3435
3436                 /* TX Priority Stats */
3437                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3438                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3439                                 snprintf(xstats_names[count].name,
3440                                         sizeof(xstats_names[count].name),
3441                                         "tx_priority%u_%s", i,
3442                                         rte_ixgbe_txq_strings[stat].name);
3443                                 count++;
3444                         }
3445                 }
3446         }
3447         return cnt_stats;
3448 }
3449
3450 static int ixgbe_dev_xstats_get_names_by_id(
3451         struct rte_eth_dev *dev,
3452         struct rte_eth_xstat_name *xstats_names,
3453         const uint64_t *ids,
3454         unsigned int limit)
3455 {
3456         if (!ids) {
3457                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3458                 unsigned int stat, i, count;
3459
3460                 if (xstats_names != NULL) {
3461                         count = 0;
3462
3463                         /* Note: limit >= cnt_stats checked upstream
3464                          * in rte_eth_xstats_names()
3465                          */
3466
3467                         /* Extended stats from ixgbe_hw_stats */
3468                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3469                                 strlcpy(xstats_names[count].name,
3470                                         rte_ixgbe_stats_strings[i].name,
3471                                         sizeof(xstats_names[count].name));
3472                                 count++;
3473                         }
3474
3475                         /* MACsec Stats */
3476                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3477                                 strlcpy(xstats_names[count].name,
3478                                         rte_ixgbe_macsec_strings[i].name,
3479                                         sizeof(xstats_names[count].name));
3480                                 count++;
3481                         }
3482
3483                         /* RX Priority Stats */
3484                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3485                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3486                                         snprintf(xstats_names[count].name,
3487                                             sizeof(xstats_names[count].name),
3488                                             "rx_priority%u_%s", i,
3489                                             rte_ixgbe_rxq_strings[stat].name);
3490                                         count++;
3491                                 }
3492                         }
3493
3494                         /* TX Priority Stats */
3495                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3496                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3497                                         snprintf(xstats_names[count].name,
3498                                             sizeof(xstats_names[count].name),
3499                                             "tx_priority%u_%s", i,
3500                                             rte_ixgbe_txq_strings[stat].name);
3501                                         count++;
3502                                 }
3503                         }
3504                 }
3505                 return cnt_stats;
3506         }
3507
3508         uint16_t i;
3509         uint16_t size = ixgbe_xstats_calc_num();
3510         struct rte_eth_xstat_name xstats_names_copy[size];
3511
3512         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3513                         size);
3514
3515         for (i = 0; i < limit; i++) {
3516                 if (ids[i] >= size) {
3517                         PMD_INIT_LOG(ERR, "id value isn't valid");
3518                         return -1;
3519                 }
3520                 strcpy(xstats_names[i].name,
3521                                 xstats_names_copy[ids[i]].name);
3522         }
3523         return limit;
3524 }
3525
3526 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3527         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3528 {
3529         unsigned i;
3530
3531         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3532                 return -ENOMEM;
3533
3534         if (xstats_names != NULL)
3535                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3536                         strlcpy(xstats_names[i].name,
3537                                 rte_ixgbevf_stats_strings[i].name,
3538                                 sizeof(xstats_names[i].name));
3539         return IXGBEVF_NB_XSTATS;
3540 }
3541
3542 static int
3543 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3544                                          unsigned n)
3545 {
3546         struct ixgbe_hw *hw =
3547                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548         struct ixgbe_hw_stats *hw_stats =
3549                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550         struct ixgbe_macsec_stats *macsec_stats =
3551                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3552                                 dev->data->dev_private);
3553         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3554         unsigned i, stat, count = 0;
3555
3556         count = ixgbe_xstats_calc_num();
3557
3558         if (n < count)
3559                 return count;
3560
3561         total_missed_rx = 0;
3562         total_qbrc = 0;
3563         total_qprc = 0;
3564         total_qprdc = 0;
3565
3566         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3567                         &total_qbrc, &total_qprc, &total_qprdc);
3568
3569         /* If this is a reset xstats is NULL, and we have cleared the
3570          * registers by reading them.
3571          */
3572         if (!xstats)
3573                 return 0;
3574
3575         /* Extended stats from ixgbe_hw_stats */
3576         count = 0;
3577         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3578                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3579                                 rte_ixgbe_stats_strings[i].offset);
3580                 xstats[count].id = count;
3581                 count++;
3582         }
3583
3584         /* MACsec Stats */
3585         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3586                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3587                                 rte_ixgbe_macsec_strings[i].offset);
3588                 xstats[count].id = count;
3589                 count++;
3590         }
3591
3592         /* RX Priority Stats */
3593         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3594                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3595                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3596                                         rte_ixgbe_rxq_strings[stat].offset +
3597                                         (sizeof(uint64_t) * i));
3598                         xstats[count].id = count;
3599                         count++;
3600                 }
3601         }
3602
3603         /* TX Priority Stats */
3604         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3605                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3606                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3607                                         rte_ixgbe_txq_strings[stat].offset +
3608                                         (sizeof(uint64_t) * i));
3609                         xstats[count].id = count;
3610                         count++;
3611                 }
3612         }
3613         return count;
3614 }
3615
3616 static int
3617 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3618                 uint64_t *values, unsigned int n)
3619 {
3620         if (!ids) {
3621                 struct ixgbe_hw *hw =
3622                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3623                 struct ixgbe_hw_stats *hw_stats =
3624                                 IXGBE_DEV_PRIVATE_TO_STATS(
3625                                                 dev->data->dev_private);
3626                 struct ixgbe_macsec_stats *macsec_stats =
3627                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3628                                         dev->data->dev_private);
3629                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3630                 unsigned int i, stat, count = 0;
3631
3632                 count = ixgbe_xstats_calc_num();
3633
3634                 if (!ids && n < count)
3635                         return count;
3636
3637                 total_missed_rx = 0;
3638                 total_qbrc = 0;
3639                 total_qprc = 0;
3640                 total_qprdc = 0;
3641
3642                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3643                                 &total_missed_rx, &total_qbrc, &total_qprc,
3644                                 &total_qprdc);
3645
3646                 /* If this is a reset xstats is NULL, and we have cleared the
3647                  * registers by reading them.
3648                  */
3649                 if (!ids && !values)
3650                         return 0;
3651
3652                 /* Extended stats from ixgbe_hw_stats */
3653                 count = 0;
3654                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3655                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3656                                         rte_ixgbe_stats_strings[i].offset);
3657                         count++;
3658                 }
3659
3660                 /* MACsec Stats */
3661                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3662                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3663                                         rte_ixgbe_macsec_strings[i].offset);
3664                         count++;
3665                 }
3666
3667                 /* RX Priority Stats */
3668                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3669                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3670                                 values[count] =
3671                                         *(uint64_t *)(((char *)hw_stats) +
3672                                         rte_ixgbe_rxq_strings[stat].offset +
3673                                         (sizeof(uint64_t) * i));
3674                                 count++;
3675                         }
3676                 }
3677
3678                 /* TX Priority Stats */
3679                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3680                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3681                                 values[count] =
3682                                         *(uint64_t *)(((char *)hw_stats) +
3683                                         rte_ixgbe_txq_strings[stat].offset +
3684                                         (sizeof(uint64_t) * i));
3685                                 count++;
3686                         }
3687                 }
3688                 return count;
3689         }
3690
3691         uint16_t i;
3692         uint16_t size = ixgbe_xstats_calc_num();
3693         uint64_t values_copy[size];
3694
3695         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3696
3697         for (i = 0; i < n; i++) {
3698                 if (ids[i] >= size) {
3699                         PMD_INIT_LOG(ERR, "id value isn't valid");
3700                         return -1;
3701                 }
3702                 values[i] = values_copy[ids[i]];
3703         }
3704         return n;
3705 }
3706
3707 static int
3708 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3709 {
3710         struct ixgbe_hw_stats *stats =
3711                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3712         struct ixgbe_macsec_stats *macsec_stats =
3713                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3714                                 dev->data->dev_private);
3715
3716         unsigned count = ixgbe_xstats_calc_num();
3717
3718         /* HW registers are cleared on read */
3719         ixgbe_dev_xstats_get(dev, NULL, count);
3720
3721         /* Reset software totals */
3722         memset(stats, 0, sizeof(*stats));
3723         memset(macsec_stats, 0, sizeof(*macsec_stats));
3724
3725         return 0;
3726 }
3727
3728 static void
3729 ixgbevf_update_stats(struct rte_eth_dev *dev)
3730 {
3731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3733                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3734
3735         /* Good Rx packet, include VF loopback */
3736         UPDATE_VF_STAT(IXGBE_VFGPRC,
3737             hw_stats->last_vfgprc, hw_stats->vfgprc);
3738
3739         /* Good Rx octets, include VF loopback */
3740         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3741             hw_stats->last_vfgorc, hw_stats->vfgorc);
3742
3743         /* Good Tx packet, include VF loopback */
3744         UPDATE_VF_STAT(IXGBE_VFGPTC,
3745             hw_stats->last_vfgptc, hw_stats->vfgptc);
3746
3747         /* Good Tx octets, include VF loopback */
3748         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3749             hw_stats->last_vfgotc, hw_stats->vfgotc);
3750
3751         /* Rx Multicst Packet */
3752         UPDATE_VF_STAT(IXGBE_VFMPRC,
3753             hw_stats->last_vfmprc, hw_stats->vfmprc);
3754 }
3755
3756 static int
3757 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3758                        unsigned n)
3759 {
3760         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3761                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3762         unsigned i;
3763
3764         if (n < IXGBEVF_NB_XSTATS)
3765                 return IXGBEVF_NB_XSTATS;
3766
3767         ixgbevf_update_stats(dev);
3768
3769         if (!xstats)
3770                 return 0;
3771
3772         /* Extended stats */
3773         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3774                 xstats[i].id = i;
3775                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3776                         rte_ixgbevf_stats_strings[i].offset);
3777         }
3778
3779         return IXGBEVF_NB_XSTATS;
3780 }
3781
3782 static int
3783 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3784 {
3785         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3786                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3787
3788         ixgbevf_update_stats(dev);
3789
3790         if (stats == NULL)
3791                 return -EINVAL;
3792
3793         stats->ipackets = hw_stats->vfgprc;
3794         stats->ibytes = hw_stats->vfgorc;
3795         stats->opackets = hw_stats->vfgptc;
3796         stats->obytes = hw_stats->vfgotc;
3797         return 0;
3798 }
3799
3800 static int
3801 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3802 {
3803         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3804                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3805
3806         /* Sync HW register to the last stats */
3807         ixgbevf_dev_stats_get(dev, NULL);
3808
3809         /* reset HW current stats*/
3810         hw_stats->vfgprc = 0;
3811         hw_stats->vfgorc = 0;
3812         hw_stats->vfgptc = 0;
3813         hw_stats->vfgotc = 0;
3814
3815         return 0;
3816 }
3817
3818 static int
3819 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3820 {
3821         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3822         u16 eeprom_verh, eeprom_verl;
3823         u32 etrack_id;
3824         int ret;
3825
3826         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3827         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3828
3829         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3830         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3831
3832         ret += 1; /* add the size of '\0' */
3833         if (fw_size < (u32)ret)
3834                 return ret;
3835         else
3836                 return 0;
3837 }
3838
3839 static int
3840 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3841 {
3842         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3843         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3844         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3845
3846         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3847         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3848         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3849                 /*
3850                  * When DCB/VT is off, maximum number of queues changes,
3851                  * except for 82598EB, which remains constant.
3852                  */
3853                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3854                                 hw->mac.type != ixgbe_mac_82598EB)
3855                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3856         }
3857         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3858         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3859         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3860         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3861         dev_info->max_vfs = pci_dev->max_vfs;
3862         if (hw->mac.type == ixgbe_mac_82598EB)
3863                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3864         else
3865                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3866         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3867         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3868         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3869         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3870         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3871                                      dev_info->rx_queue_offload_capa);
3872         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3873         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3874
3875         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3876                 .rx_thresh = {
3877                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3878                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3879                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3880                 },
3881                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3882                 .rx_drop_en = 0,
3883                 .offloads = 0,
3884         };
3885
3886         dev_info->default_txconf = (struct rte_eth_txconf) {
3887                 .tx_thresh = {
3888                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3889                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3890                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3891                 },
3892                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3893                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3894                 .offloads = 0,
3895         };
3896
3897         dev_info->rx_desc_lim = rx_desc_lim;
3898         dev_info->tx_desc_lim = tx_desc_lim;
3899
3900         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3901         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3902         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3903
3904         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3905         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3906                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3907                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3908                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3909
3910         if (hw->mac.type == ixgbe_mac_X540 ||
3911             hw->mac.type == ixgbe_mac_X540_vf ||
3912             hw->mac.type == ixgbe_mac_X550 ||
3913             hw->mac.type == ixgbe_mac_X550_vf) {
3914                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3915         }
3916         if (hw->mac.type == ixgbe_mac_X550) {
3917                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3918                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3919         }
3920
3921         /* Driver-preferred Rx/Tx parameters */
3922         dev_info->default_rxportconf.burst_size = 32;
3923         dev_info->default_txportconf.burst_size = 32;
3924         dev_info->default_rxportconf.nb_queues = 1;
3925         dev_info->default_txportconf.nb_queues = 1;
3926         dev_info->default_rxportconf.ring_size = 256;
3927         dev_info->default_txportconf.ring_size = 256;
3928
3929         return 0;
3930 }
3931
3932 static const uint32_t *
3933 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3934 {
3935         static const uint32_t ptypes[] = {
3936                 /* For non-vec functions,
3937                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3938                  * for vec functions,
3939                  * refers to _recv_raw_pkts_vec().
3940                  */
3941                 RTE_PTYPE_L2_ETHER,
3942                 RTE_PTYPE_L3_IPV4,
3943                 RTE_PTYPE_L3_IPV4_EXT,
3944                 RTE_PTYPE_L3_IPV6,
3945                 RTE_PTYPE_L3_IPV6_EXT,
3946                 RTE_PTYPE_L4_SCTP,
3947                 RTE_PTYPE_L4_TCP,
3948                 RTE_PTYPE_L4_UDP,
3949                 RTE_PTYPE_TUNNEL_IP,
3950                 RTE_PTYPE_INNER_L3_IPV6,
3951                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3952                 RTE_PTYPE_INNER_L4_TCP,
3953                 RTE_PTYPE_INNER_L4_UDP,
3954                 RTE_PTYPE_UNKNOWN
3955         };
3956
3957         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3958             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3959             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3960             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3961                 return ptypes;
3962
3963 #if defined(RTE_ARCH_X86) || defined(RTE_MACHINE_CPUFLAG_NEON)
3964         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3965             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3966                 return ptypes;
3967 #endif
3968         return NULL;
3969 }
3970
3971 static int
3972 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3973                      struct rte_eth_dev_info *dev_info)
3974 {
3975         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3976         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3977
3978         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3979         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3980         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3981         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3982         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3983         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3984         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3985         dev_info->max_vfs = pci_dev->max_vfs;
3986         if (hw->mac.type == ixgbe_mac_82598EB)
3987                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3988         else
3989                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3990         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3991         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3992                                      dev_info->rx_queue_offload_capa);
3993         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3994         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3995         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3996         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3997         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3998
3999         dev_info->default_rxconf = (struct rte_eth_rxconf) {
4000                 .rx_thresh = {
4001                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
4002                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
4003                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
4004                 },
4005                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
4006                 .rx_drop_en = 0,
4007                 .offloads = 0,
4008         };
4009
4010         dev_info->default_txconf = (struct rte_eth_txconf) {
4011                 .tx_thresh = {
4012                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
4013                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
4014                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
4015                 },
4016                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
4017                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
4018                 .offloads = 0,
4019         };
4020
4021         dev_info->rx_desc_lim = rx_desc_lim;
4022         dev_info->tx_desc_lim = tx_desc_lim;
4023
4024         return 0;
4025 }
4026
4027 static int
4028 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4029                    bool *link_up, int wait_to_complete)
4030 {
4031         struct ixgbe_adapter *adapter = container_of(hw,
4032                                                      struct ixgbe_adapter, hw);
4033         struct ixgbe_mbx_info *mbx = &hw->mbx;
4034         struct ixgbe_mac_info *mac = &hw->mac;
4035         uint32_t links_reg, in_msg;
4036         int ret_val = 0;
4037
4038         /* If we were hit with a reset drop the link */
4039         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4040                 mac->get_link_status = true;
4041
4042         if (!mac->get_link_status)
4043                 goto out;
4044
4045         /* if link status is down no point in checking to see if pf is up */
4046         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4047         if (!(links_reg & IXGBE_LINKS_UP))
4048                 goto out;
4049
4050         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4051          * before the link status is correct
4052          */
4053         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4054                 int i;
4055
4056                 for (i = 0; i < 5; i++) {
4057                         rte_delay_us(100);
4058                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4059
4060                         if (!(links_reg & IXGBE_LINKS_UP))
4061                                 goto out;
4062                 }
4063         }
4064
4065         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4066         case IXGBE_LINKS_SPEED_10G_82599:
4067                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4068                 if (hw->mac.type >= ixgbe_mac_X550) {
4069                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4070                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4071                 }
4072                 break;
4073         case IXGBE_LINKS_SPEED_1G_82599:
4074                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4075                 break;
4076         case IXGBE_LINKS_SPEED_100_82599:
4077                 *speed = IXGBE_LINK_SPEED_100_FULL;
4078                 if (hw->mac.type == ixgbe_mac_X550) {
4079                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4080                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4081                 }
4082                 break;
4083         case IXGBE_LINKS_SPEED_10_X550EM_A:
4084                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4085                 /* Since Reserved in older MAC's */
4086                 if (hw->mac.type >= ixgbe_mac_X550)
4087                         *speed = IXGBE_LINK_SPEED_10_FULL;
4088                 break;
4089         default:
4090                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4091         }
4092
4093         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4094                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4095                         mac->get_link_status = true;
4096                 else
4097                         mac->get_link_status = false;
4098
4099                 goto out;
4100         }
4101
4102         /* if the read failed it could just be a mailbox collision, best wait
4103          * until we are called again and don't report an error
4104          */
4105         if (mbx->ops.read(hw, &in_msg, 1, 0))
4106                 goto out;
4107
4108         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4109                 /* msg is not CTS and is NACK we must have lost CTS status */
4110                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4111                         mac->get_link_status = false;
4112                 goto out;
4113         }
4114
4115         /* the pf is talking, if we timed out in the past we reinit */
4116         if (!mbx->timeout) {
4117                 ret_val = -1;
4118                 goto out;
4119         }
4120
4121         /* if we passed all the tests above then the link is up and we no
4122          * longer need to check for link
4123          */
4124         mac->get_link_status = false;
4125
4126 out:
4127         *link_up = !mac->get_link_status;
4128         return ret_val;
4129 }
4130
4131 /*
4132  * If @timeout_ms was 0, it means that it will not return until link complete.
4133  * It returns 1 on complete, return 0 on timeout.
4134  */
4135 static int
4136 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4137 {
4138 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4139         struct ixgbe_adapter *ad = dev->data->dev_private;
4140         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4141
4142         while (rte_atomic32_read(&ad->link_thread_running)) {
4143                 msec_delay(1);
4144                 timeout--;
4145
4146                 if (timeout_ms) {
4147                         if (!timeout)
4148                                 return 0;
4149                 } else if (!timeout) {
4150                         /* It will not return until link complete */
4151                         timeout = WARNING_TIMEOUT;
4152                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4153                 }
4154         }
4155
4156         return 1;
4157 }
4158
4159 static void *
4160 ixgbe_dev_setup_link_thread_handler(void *param)
4161 {
4162         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4163         struct ixgbe_adapter *ad = dev->data->dev_private;
4164         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4165         struct ixgbe_interrupt *intr =
4166                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4167         u32 speed;
4168         bool autoneg = false;
4169
4170         pthread_detach(pthread_self());
4171         speed = hw->phy.autoneg_advertised;
4172         if (!speed)
4173                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4174
4175         ixgbe_setup_link(hw, speed, true);
4176
4177         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4178         rte_atomic32_clear(&ad->link_thread_running);
4179         return NULL;
4180 }
4181
4182 /*
4183  * In freebsd environment, nic_uio drivers do not support interrupts,
4184  * rte_intr_callback_register() will fail to register interrupts.
4185  * We can not make link status to change from down to up by interrupt
4186  * callback. So we need to wait for the controller to acquire link
4187  * when ports start.
4188  * It returns 0 on link up.
4189  */
4190 static int
4191 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4192 {
4193 #ifdef RTE_EXEC_ENV_FREEBSD
4194         int err, i;
4195         bool link_up = false;
4196         uint32_t speed = 0;
4197         const int nb_iter = 25;
4198
4199         for (i = 0; i < nb_iter; i++) {
4200                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4201                 if (err)
4202                         return err;
4203                 if (link_up)
4204                         return 0;
4205                 msec_delay(200);
4206         }
4207
4208         return 0;
4209 #else
4210         RTE_SET_USED(hw);
4211         return 0;
4212 #endif
4213 }
4214
4215 /* return 0 means link status changed, -1 means not changed */
4216 int
4217 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4218                             int wait_to_complete, int vf)
4219 {
4220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4221         struct ixgbe_adapter *ad = dev->data->dev_private;
4222         struct rte_eth_link link;
4223         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4224         struct ixgbe_interrupt *intr =
4225                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4226         bool link_up;
4227         int diag;
4228         int wait = 1;
4229         u32 esdp_reg;
4230
4231         memset(&link, 0, sizeof(link));
4232         link.link_status = ETH_LINK_DOWN;
4233         link.link_speed = ETH_SPEED_NUM_NONE;
4234         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4235         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4236                         ETH_LINK_SPEED_FIXED);
4237
4238         hw->mac.get_link_status = true;
4239
4240         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4241                 return rte_eth_linkstatus_set(dev, &link);
4242
4243         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4244         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4245                 wait = 0;
4246
4247 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4248 #ifdef RTE_EXEC_ENV_FREEBSD
4249         wait = 1;
4250 #endif
4251
4252         if (vf)
4253                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4254         else
4255                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4256
4257         if (diag != 0) {
4258                 link.link_speed = ETH_SPEED_NUM_100M;
4259                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4260                 return rte_eth_linkstatus_set(dev, &link);
4261         }
4262
4263         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4264                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4265                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4266                         link_up = 0;
4267         }
4268
4269         if (link_up == 0) {
4270                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4271                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4272                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4273                                 /* To avoid race condition between threads, set
4274                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4275                                  * when there is no link thread running.
4276                                  */
4277                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4278                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4279                                         "ixgbe-link-handler",
4280                                         NULL,
4281                                         ixgbe_dev_setup_link_thread_handler,
4282                                         dev) < 0) {
4283                                         PMD_DRV_LOG(ERR,
4284                                                 "Create link thread failed!");
4285                                         rte_atomic32_clear(&ad->link_thread_running);
4286                                 }
4287                         } else {
4288                                 PMD_DRV_LOG(ERR,
4289                                         "Other link thread is running now!");
4290                         }
4291                 }
4292                 return rte_eth_linkstatus_set(dev, &link);
4293         }
4294
4295         link.link_status = ETH_LINK_UP;
4296         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4297
4298         switch (link_speed) {
4299         default:
4300         case IXGBE_LINK_SPEED_UNKNOWN:
4301                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
4302                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
4303                         link.link_speed = ETH_SPEED_NUM_10M;
4304                 else
4305                         link.link_speed = ETH_SPEED_NUM_100M;
4306                 break;
4307
4308         case IXGBE_LINK_SPEED_10_FULL:
4309                 link.link_speed = ETH_SPEED_NUM_10M;
4310                 break;
4311
4312         case IXGBE_LINK_SPEED_100_FULL:
4313                 link.link_speed = ETH_SPEED_NUM_100M;
4314                 break;
4315
4316         case IXGBE_LINK_SPEED_1GB_FULL:
4317                 link.link_speed = ETH_SPEED_NUM_1G;
4318                 break;
4319
4320         case IXGBE_LINK_SPEED_2_5GB_FULL:
4321                 link.link_speed = ETH_SPEED_NUM_2_5G;
4322                 break;
4323
4324         case IXGBE_LINK_SPEED_5GB_FULL:
4325                 link.link_speed = ETH_SPEED_NUM_5G;
4326                 break;
4327
4328         case IXGBE_LINK_SPEED_10GB_FULL:
4329                 link.link_speed = ETH_SPEED_NUM_10G;
4330                 break;
4331         }
4332
4333         return rte_eth_linkstatus_set(dev, &link);
4334 }
4335
4336 static int
4337 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4338 {
4339         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4340 }
4341
4342 static int
4343 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4344 {
4345         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4346 }
4347
4348 static int
4349 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4350 {
4351         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4352         uint32_t fctrl;
4353
4354         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4355         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4356         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4357
4358         return 0;
4359 }
4360
4361 static int
4362 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4363 {
4364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4365         uint32_t fctrl;
4366
4367         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4368         fctrl &= (~IXGBE_FCTRL_UPE);
4369         if (dev->data->all_multicast == 1)
4370                 fctrl |= IXGBE_FCTRL_MPE;
4371         else
4372                 fctrl &= (~IXGBE_FCTRL_MPE);
4373         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4374
4375         return 0;
4376 }
4377
4378 static int
4379 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4380 {
4381         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4382         uint32_t fctrl;
4383
4384         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4385         fctrl |= IXGBE_FCTRL_MPE;
4386         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4387
4388         return 0;
4389 }
4390
4391 static int
4392 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4393 {
4394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395         uint32_t fctrl;
4396
4397         if (dev->data->promiscuous == 1)
4398                 return 0; /* must remain in all_multicast mode */
4399
4400         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4401         fctrl &= (~IXGBE_FCTRL_MPE);
4402         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4403
4404         return 0;
4405 }
4406
4407 /**
4408  * It clears the interrupt causes and enables the interrupt.
4409  * It will be called once only during nic initialized.
4410  *
4411  * @param dev
4412  *  Pointer to struct rte_eth_dev.
4413  * @param on
4414  *  Enable or Disable.
4415  *
4416  * @return
4417  *  - On success, zero.
4418  *  - On failure, a negative value.
4419  */
4420 static int
4421 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4422 {
4423         struct ixgbe_interrupt *intr =
4424                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4425
4426         ixgbe_dev_link_status_print(dev);
4427         if (on)
4428                 intr->mask |= IXGBE_EICR_LSC;
4429         else
4430                 intr->mask &= ~IXGBE_EICR_LSC;
4431
4432         return 0;
4433 }
4434
4435 /**
4436  * It clears the interrupt causes and enables the interrupt.
4437  * It will be called once only during nic initialized.
4438  *
4439  * @param dev
4440  *  Pointer to struct rte_eth_dev.
4441  *
4442  * @return
4443  *  - On success, zero.
4444  *  - On failure, a negative value.
4445  */
4446 static int
4447 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4448 {
4449         struct ixgbe_interrupt *intr =
4450                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4451
4452         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4453
4454         return 0;
4455 }
4456
4457 /**
4458  * It clears the interrupt causes and enables the interrupt.
4459  * It will be called once only during nic initialized.
4460  *
4461  * @param dev
4462  *  Pointer to struct rte_eth_dev.
4463  *
4464  * @return
4465  *  - On success, zero.
4466  *  - On failure, a negative value.
4467  */
4468 static int
4469 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4470 {
4471         struct ixgbe_interrupt *intr =
4472                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4473
4474         intr->mask |= IXGBE_EICR_LINKSEC;
4475
4476         return 0;
4477 }
4478
4479 /*
4480  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4481  *
4482  * @param dev
4483  *  Pointer to struct rte_eth_dev.
4484  *
4485  * @return
4486  *  - On success, zero.
4487  *  - On failure, a negative value.
4488  */
4489 static int
4490 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4491 {
4492         uint32_t eicr;
4493         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494         struct ixgbe_interrupt *intr =
4495                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4496
4497         /* clear all cause mask */
4498         ixgbe_disable_intr(hw);
4499
4500         /* read-on-clear nic registers here */
4501         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4502         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4503
4504         intr->flags = 0;
4505
4506         /* set flag for async link update */
4507         if (eicr & IXGBE_EICR_LSC)
4508                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4509
4510         if (eicr & IXGBE_EICR_MAILBOX)
4511                 intr->flags |= IXGBE_FLAG_MAILBOX;
4512
4513         if (eicr & IXGBE_EICR_LINKSEC)
4514                 intr->flags |= IXGBE_FLAG_MACSEC;
4515
4516         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4517             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4518             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4519                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4520
4521         return 0;
4522 }
4523
4524 /**
4525  * It gets and then prints the link status.
4526  *
4527  * @param dev
4528  *  Pointer to struct rte_eth_dev.
4529  *
4530  * @return
4531  *  - On success, zero.
4532  *  - On failure, a negative value.
4533  */
4534 static void
4535 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4536 {
4537         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4538         struct rte_eth_link link;
4539
4540         rte_eth_linkstatus_get(dev, &link);
4541
4542         if (link.link_status) {
4543                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4544                                         (int)(dev->data->port_id),
4545                                         (unsigned)link.link_speed,
4546                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4547                                         "full-duplex" : "half-duplex");
4548         } else {
4549                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4550                                 (int)(dev->data->port_id));
4551         }
4552         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4553                                 pci_dev->addr.domain,
4554                                 pci_dev->addr.bus,
4555                                 pci_dev->addr.devid,
4556                                 pci_dev->addr.function);
4557 }
4558
4559 /*
4560  * It executes link_update after knowing an interrupt occurred.
4561  *
4562  * @param dev
4563  *  Pointer to struct rte_eth_dev.
4564  *
4565  * @return
4566  *  - On success, zero.
4567  *  - On failure, a negative value.
4568  */
4569 static int
4570 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4571 {
4572         struct ixgbe_interrupt *intr =
4573                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4574         int64_t timeout;
4575         struct ixgbe_hw *hw =
4576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4577
4578         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4579
4580         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4581                 ixgbe_pf_mbx_process(dev);
4582                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4583         }
4584
4585         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4586                 ixgbe_handle_lasi(hw);
4587                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4588         }
4589
4590         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4591                 struct rte_eth_link link;
4592
4593                 /* get the link status before link update, for predicting later */
4594                 rte_eth_linkstatus_get(dev, &link);
4595
4596                 ixgbe_dev_link_update(dev, 0);
4597
4598                 /* likely to up */
4599                 if (!link.link_status)
4600                         /* handle it 1 sec later, wait it being stable */
4601                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4602                 /* likely to down */
4603                 else
4604                         /* handle it 4 sec later, wait it being stable */
4605                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4606
4607                 ixgbe_dev_link_status_print(dev);
4608                 if (rte_eal_alarm_set(timeout * 1000,
4609                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4610                         PMD_DRV_LOG(ERR, "Error setting alarm");
4611                 else {
4612                         /* remember original mask */
4613                         intr->mask_original = intr->mask;
4614                         /* only disable lsc interrupt */
4615                         intr->mask &= ~IXGBE_EIMS_LSC;
4616                 }
4617         }
4618
4619         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4620         ixgbe_enable_intr(dev);
4621
4622         return 0;
4623 }
4624
4625 /**
4626  * Interrupt handler which shall be registered for alarm callback for delayed
4627  * handling specific interrupt to wait for the stable nic state. As the
4628  * NIC interrupt state is not stable for ixgbe after link is just down,
4629  * it needs to wait 4 seconds to get the stable status.
4630  *
4631  * @param handle
4632  *  Pointer to interrupt handle.
4633  * @param param
4634  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4635  *
4636  * @return
4637  *  void
4638  */
4639 static void
4640 ixgbe_dev_interrupt_delayed_handler(void *param)
4641 {
4642         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4643         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4644         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4645         struct ixgbe_interrupt *intr =
4646                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4647         struct ixgbe_hw *hw =
4648                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4649         uint32_t eicr;
4650
4651         ixgbe_disable_intr(hw);
4652
4653         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4654         if (eicr & IXGBE_EICR_MAILBOX)
4655                 ixgbe_pf_mbx_process(dev);
4656
4657         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4658                 ixgbe_handle_lasi(hw);
4659                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4660         }
4661
4662         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4663                 ixgbe_dev_link_update(dev, 0);
4664                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4665                 ixgbe_dev_link_status_print(dev);
4666                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4667                                               NULL);
4668         }
4669
4670         if (intr->flags & IXGBE_FLAG_MACSEC) {
4671                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4672                                               NULL);
4673                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4674         }
4675
4676         /* restore original mask */
4677         intr->mask = intr->mask_original;
4678         intr->mask_original = 0;
4679
4680         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4681         ixgbe_enable_intr(dev);
4682         rte_intr_ack(intr_handle);
4683 }
4684
4685 /**
4686  * Interrupt handler triggered by NIC  for handling
4687  * specific interrupt.
4688  *
4689  * @param handle
4690  *  Pointer to interrupt handle.
4691  * @param param
4692  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4693  *
4694  * @return
4695  *  void
4696  */
4697 static void
4698 ixgbe_dev_interrupt_handler(void *param)
4699 {
4700         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4701
4702         ixgbe_dev_interrupt_get_status(dev);
4703         ixgbe_dev_interrupt_action(dev);
4704 }
4705
4706 static int
4707 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4708 {
4709         struct ixgbe_hw *hw;
4710
4711         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4712         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4713 }
4714
4715 static int
4716 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4717 {
4718         struct ixgbe_hw *hw;
4719
4720         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4721         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4722 }
4723
4724 static int
4725 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4726 {
4727         struct ixgbe_hw *hw;
4728         uint32_t mflcn_reg;
4729         uint32_t fccfg_reg;
4730         int rx_pause;
4731         int tx_pause;
4732
4733         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734
4735         fc_conf->pause_time = hw->fc.pause_time;
4736         fc_conf->high_water = hw->fc.high_water[0];
4737         fc_conf->low_water = hw->fc.low_water[0];
4738         fc_conf->send_xon = hw->fc.send_xon;
4739         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4740
4741         /*
4742          * Return rx_pause status according to actual setting of
4743          * MFLCN register.
4744          */
4745         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4746         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4747                 rx_pause = 1;
4748         else
4749                 rx_pause = 0;
4750
4751         /*
4752          * Return tx_pause status according to actual setting of
4753          * FCCFG register.
4754          */
4755         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4756         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4757                 tx_pause = 1;
4758         else
4759                 tx_pause = 0;
4760
4761         if (rx_pause && tx_pause)
4762                 fc_conf->mode = RTE_FC_FULL;
4763         else if (rx_pause)
4764                 fc_conf->mode = RTE_FC_RX_PAUSE;
4765         else if (tx_pause)
4766                 fc_conf->mode = RTE_FC_TX_PAUSE;
4767         else
4768                 fc_conf->mode = RTE_FC_NONE;
4769
4770         return 0;
4771 }
4772
4773 static int
4774 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4775 {
4776         struct ixgbe_hw *hw;
4777         struct ixgbe_adapter *adapter = dev->data->dev_private;
4778         int err;
4779         uint32_t rx_buf_size;
4780         uint32_t max_high_water;
4781         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4782                 ixgbe_fc_none,
4783                 ixgbe_fc_rx_pause,
4784                 ixgbe_fc_tx_pause,
4785                 ixgbe_fc_full
4786         };
4787
4788         PMD_INIT_FUNC_TRACE();
4789
4790         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4791         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4792         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4793
4794         /*
4795          * At least reserve one Ethernet frame for watermark
4796          * high_water/low_water in kilo bytes for ixgbe
4797          */
4798         max_high_water = (rx_buf_size -
4799                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4800         if ((fc_conf->high_water > max_high_water) ||
4801                 (fc_conf->high_water < fc_conf->low_water)) {
4802                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4803                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4804                 return -EINVAL;
4805         }
4806
4807         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4808         hw->fc.pause_time     = fc_conf->pause_time;
4809         hw->fc.high_water[0]  = fc_conf->high_water;
4810         hw->fc.low_water[0]   = fc_conf->low_water;
4811         hw->fc.send_xon       = fc_conf->send_xon;
4812         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4813         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4814
4815         err = ixgbe_flow_ctrl_enable(dev, hw);
4816         if (err < 0) {
4817                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4818                 return -EIO;
4819         }
4820         return err;
4821 }
4822
4823 /**
4824  *  ixgbe_pfc_enable_generic - Enable flow control
4825  *  @hw: pointer to hardware structure
4826  *  @tc_num: traffic class number
4827  *  Enable flow control according to the current settings.
4828  */
4829 static int
4830 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4831 {
4832         int ret_val = 0;
4833         uint32_t mflcn_reg, fccfg_reg;
4834         uint32_t reg;
4835         uint32_t fcrtl, fcrth;
4836         uint8_t i;
4837         uint8_t nb_rx_en;
4838
4839         /* Validate the water mark configuration */
4840         if (!hw->fc.pause_time) {
4841                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4842                 goto out;
4843         }
4844
4845         /* Low water mark of zero causes XOFF floods */
4846         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4847                  /* High/Low water can not be 0 */
4848                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4849                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4850                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4851                         goto out;
4852                 }
4853
4854                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4855                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4856                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4857                         goto out;
4858                 }
4859         }
4860         /* Negotiate the fc mode to use */
4861         ixgbe_fc_autoneg(hw);
4862
4863         /* Disable any previous flow control settings */
4864         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4865         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4866
4867         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4868         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4869
4870         switch (hw->fc.current_mode) {
4871         case ixgbe_fc_none:
4872                 /*
4873                  * If the count of enabled RX Priority Flow control >1,
4874                  * and the TX pause can not be disabled
4875                  */
4876                 nb_rx_en = 0;
4877                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4878                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4879                         if (reg & IXGBE_FCRTH_FCEN)
4880                                 nb_rx_en++;
4881                 }
4882                 if (nb_rx_en > 1)
4883                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4884                 break;
4885         case ixgbe_fc_rx_pause:
4886                 /*
4887                  * Rx Flow control is enabled and Tx Flow control is
4888                  * disabled by software override. Since there really
4889                  * isn't a way to advertise that we are capable of RX
4890                  * Pause ONLY, we will advertise that we support both
4891                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4892                  * disable the adapter's ability to send PAUSE frames.
4893                  */
4894                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4895                 /*
4896                  * If the count of enabled RX Priority Flow control >1,
4897                  * and the TX pause can not be disabled
4898                  */
4899                 nb_rx_en = 0;
4900                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4901                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4902                         if (reg & IXGBE_FCRTH_FCEN)
4903                                 nb_rx_en++;
4904                 }
4905                 if (nb_rx_en > 1)
4906                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4907                 break;
4908         case ixgbe_fc_tx_pause:
4909                 /*
4910                  * Tx Flow control is enabled, and Rx Flow control is
4911                  * disabled by software override.
4912                  */
4913                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4914                 break;
4915         case ixgbe_fc_full:
4916                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4917                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4918                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4919                 break;
4920         default:
4921                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4922                 ret_val = IXGBE_ERR_CONFIG;
4923                 goto out;
4924         }
4925
4926         /* Set 802.3x based flow control settings. */
4927         mflcn_reg |= IXGBE_MFLCN_DPF;
4928         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4929         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4930
4931         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4932         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4933                 hw->fc.high_water[tc_num]) {
4934                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4935                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4936                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4937         } else {
4938                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4939                 /*
4940                  * In order to prevent Tx hangs when the internal Tx
4941                  * switch is enabled we must set the high water mark
4942                  * to the maximum FCRTH value.  This allows the Tx
4943                  * switch to function even under heavy Rx workloads.
4944                  */
4945                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4946         }
4947         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4948
4949         /* Configure pause time (2 TCs per register) */
4950         reg = hw->fc.pause_time * 0x00010001;
4951         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4952                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4953
4954         /* Configure flow control refresh threshold value */
4955         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4956
4957 out:
4958         return ret_val;
4959 }
4960
4961 static int
4962 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4963 {
4964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4965         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4966
4967         if (hw->mac.type != ixgbe_mac_82598EB) {
4968                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4969         }
4970         return ret_val;
4971 }
4972
4973 static int
4974 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4975 {
4976         int err;
4977         uint32_t rx_buf_size;
4978         uint32_t max_high_water;
4979         uint8_t tc_num;
4980         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4981         struct ixgbe_hw *hw =
4982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4983         struct ixgbe_dcb_config *dcb_config =
4984                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4985
4986         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4987                 ixgbe_fc_none,
4988                 ixgbe_fc_rx_pause,
4989                 ixgbe_fc_tx_pause,
4990                 ixgbe_fc_full
4991         };
4992
4993         PMD_INIT_FUNC_TRACE();
4994
4995         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4996         tc_num = map[pfc_conf->priority];
4997         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4998         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4999         /*
5000          * At least reserve one Ethernet frame for watermark
5001          * high_water/low_water in kilo bytes for ixgbe
5002          */
5003         max_high_water = (rx_buf_size -
5004                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
5005         if ((pfc_conf->fc.high_water > max_high_water) ||
5006             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
5007                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
5008                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
5009                 return -EINVAL;
5010         }
5011
5012         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
5013         hw->fc.pause_time = pfc_conf->fc.pause_time;
5014         hw->fc.send_xon = pfc_conf->fc.send_xon;
5015         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
5016         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
5017
5018         err = ixgbe_dcb_pfc_enable(dev, tc_num);
5019
5020         /* Not negotiated is not an error case */
5021         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5022                 return 0;
5023
5024         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5025         return -EIO;
5026 }
5027
5028 static int
5029 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5030                           struct rte_eth_rss_reta_entry64 *reta_conf,
5031                           uint16_t reta_size)
5032 {
5033         uint16_t i, sp_reta_size;
5034         uint8_t j, mask;
5035         uint32_t reta, r;
5036         uint16_t idx, shift;
5037         struct ixgbe_adapter *adapter = dev->data->dev_private;
5038         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5039         uint32_t reta_reg;
5040
5041         PMD_INIT_FUNC_TRACE();
5042
5043         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5044                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5045                         "NIC.");
5046                 return -ENOTSUP;
5047         }
5048
5049         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5050         if (reta_size != sp_reta_size) {
5051                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5052                         "(%d) doesn't match the number hardware can supported "
5053                         "(%d)", reta_size, sp_reta_size);
5054                 return -EINVAL;
5055         }
5056
5057         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5058                 idx = i / RTE_RETA_GROUP_SIZE;
5059                 shift = i % RTE_RETA_GROUP_SIZE;
5060                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5061                                                 IXGBE_4_BIT_MASK);
5062                 if (!mask)
5063                         continue;
5064                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5065                 if (mask == IXGBE_4_BIT_MASK)
5066                         r = 0;
5067                 else
5068                         r = IXGBE_READ_REG(hw, reta_reg);
5069                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5070                         if (mask & (0x1 << j))
5071                                 reta |= reta_conf[idx].reta[shift + j] <<
5072                                                         (CHAR_BIT * j);
5073                         else
5074                                 reta |= r & (IXGBE_8_BIT_MASK <<
5075                                                 (CHAR_BIT * j));
5076                 }
5077                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5078         }
5079         adapter->rss_reta_updated = 1;
5080
5081         return 0;
5082 }
5083
5084 static int
5085 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5086                          struct rte_eth_rss_reta_entry64 *reta_conf,
5087                          uint16_t reta_size)
5088 {
5089         uint16_t i, sp_reta_size;
5090         uint8_t j, mask;
5091         uint32_t reta;
5092         uint16_t idx, shift;
5093         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5094         uint32_t reta_reg;
5095
5096         PMD_INIT_FUNC_TRACE();
5097         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5098         if (reta_size != sp_reta_size) {
5099                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5100                         "(%d) doesn't match the number hardware can supported "
5101                         "(%d)", reta_size, sp_reta_size);
5102                 return -EINVAL;
5103         }
5104
5105         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5106                 idx = i / RTE_RETA_GROUP_SIZE;
5107                 shift = i % RTE_RETA_GROUP_SIZE;
5108                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5109                                                 IXGBE_4_BIT_MASK);
5110                 if (!mask)
5111                         continue;
5112
5113                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5114                 reta = IXGBE_READ_REG(hw, reta_reg);
5115                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5116                         if (mask & (0x1 << j))
5117                                 reta_conf[idx].reta[shift + j] =
5118                                         ((reta >> (CHAR_BIT * j)) &
5119                                                 IXGBE_8_BIT_MASK);
5120                 }
5121         }
5122
5123         return 0;
5124 }
5125
5126 static int
5127 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5128                                 uint32_t index, uint32_t pool)
5129 {
5130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5131         uint32_t enable_addr = 1;
5132
5133         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5134                              pool, enable_addr);
5135 }
5136
5137 static void
5138 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5139 {
5140         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5141
5142         ixgbe_clear_rar(hw, index);
5143 }
5144
5145 static int
5146 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5147 {
5148         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5149
5150         ixgbe_remove_rar(dev, 0);
5151         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5152
5153         return 0;
5154 }
5155
5156 static bool
5157 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5158 {
5159         if (strcmp(dev->device->driver->name, drv->driver.name))
5160                 return false;
5161
5162         return true;
5163 }
5164
5165 bool
5166 is_ixgbe_supported(struct rte_eth_dev *dev)
5167 {
5168         return is_device_supported(dev, &rte_ixgbe_pmd);
5169 }
5170
5171 static int
5172 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5173 {
5174         uint32_t hlreg0;
5175         uint32_t maxfrs;
5176         struct ixgbe_hw *hw;
5177         struct rte_eth_dev_info dev_info;
5178         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5179         struct rte_eth_dev_data *dev_data = dev->data;
5180         int ret;
5181
5182         ret = ixgbe_dev_info_get(dev, &dev_info);
5183         if (ret != 0)
5184                 return ret;
5185
5186         /* check that mtu is within the allowed range */
5187         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5188                 return -EINVAL;
5189
5190         /* If device is started, refuse mtu that requires the support of
5191          * scattered packets when this feature has not been enabled before.
5192          */
5193         if (dev_data->dev_started && !dev_data->scattered_rx &&
5194             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5195              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5196                 PMD_INIT_LOG(ERR, "Stop port first.");
5197                 return -EINVAL;
5198         }
5199
5200         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5201         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5202
5203         /* switch to jumbo mode if needed */
5204         if (frame_size > RTE_ETHER_MAX_LEN) {
5205                 dev->data->dev_conf.rxmode.offloads |=
5206                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5207                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5208         } else {
5209                 dev->data->dev_conf.rxmode.offloads &=
5210                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5211                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5212         }
5213         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5214
5215         /* update max frame size */
5216         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5217
5218         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5219         maxfrs &= 0x0000FFFF;
5220         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5221         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5222
5223         return 0;
5224 }
5225
5226 /*
5227  * Virtual Function operations
5228  */
5229 static void
5230 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5231 {
5232         struct ixgbe_interrupt *intr =
5233                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5234         struct ixgbe_hw *hw =
5235                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5236
5237         PMD_INIT_FUNC_TRACE();
5238
5239         /* Clear interrupt mask to stop from interrupts being generated */
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5241
5242         IXGBE_WRITE_FLUSH(hw);
5243
5244         /* Clear mask value. */
5245         intr->mask = 0;
5246 }
5247
5248 static void
5249 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5250 {
5251         struct ixgbe_interrupt *intr =
5252                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5253         struct ixgbe_hw *hw =
5254                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5255
5256         PMD_INIT_FUNC_TRACE();
5257
5258         /* VF enable interrupt autoclean */
5259         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5260         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5261         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5262
5263         IXGBE_WRITE_FLUSH(hw);
5264
5265         /* Save IXGBE_VTEIMS value to mask. */
5266         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5267 }
5268
5269 static int
5270 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5271 {
5272         struct rte_eth_conf *conf = &dev->data->dev_conf;
5273         struct ixgbe_adapter *adapter = dev->data->dev_private;
5274
5275         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5276                      dev->data->port_id);
5277
5278         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5279                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5280
5281         /*
5282          * VF has no ability to enable/disable HW CRC
5283          * Keep the persistent behavior the same as Host PF
5284          */
5285 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5286         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5287                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5288                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5289         }
5290 #else
5291         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5292                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5293                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5294         }
5295 #endif
5296
5297         /*
5298          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5299          * allocation or vector Rx preconditions we will reset it.
5300          */
5301         adapter->rx_bulk_alloc_allowed = true;
5302         adapter->rx_vec_allowed = true;
5303
5304         return 0;
5305 }
5306
5307 static int
5308 ixgbevf_dev_start(struct rte_eth_dev *dev)
5309 {
5310         struct ixgbe_hw *hw =
5311                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5312         uint32_t intr_vector = 0;
5313         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5314         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5315
5316         int err, mask = 0;
5317
5318         PMD_INIT_FUNC_TRACE();
5319
5320         /* Stop the link setup handler before resetting the HW. */
5321         ixgbe_dev_wait_setup_link_complete(dev, 0);
5322
5323         err = hw->mac.ops.reset_hw(hw);
5324         if (err) {
5325                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5326                 return err;
5327         }
5328         hw->mac.get_link_status = true;
5329
5330         /* negotiate mailbox API version to use with the PF. */
5331         ixgbevf_negotiate_api(hw);
5332
5333         ixgbevf_dev_tx_init(dev);
5334
5335         /* This can fail when allocating mbufs for descriptor rings */
5336         err = ixgbevf_dev_rx_init(dev);
5337         if (err) {
5338                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5339                 ixgbe_dev_clear_queues(dev);
5340                 return err;
5341         }
5342
5343         /* Set vfta */
5344         ixgbevf_set_vfta_all(dev, 1);
5345
5346         /* Set HW strip */
5347         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5348                 ETH_VLAN_EXTEND_MASK;
5349         err = ixgbevf_vlan_offload_config(dev, mask);
5350         if (err) {
5351                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5352                 ixgbe_dev_clear_queues(dev);
5353                 return err;
5354         }
5355
5356         ixgbevf_dev_rxtx_start(dev);
5357
5358         /* check and configure queue intr-vector mapping */
5359         if (rte_intr_cap_multiple(intr_handle) &&
5360             dev->data->dev_conf.intr_conf.rxq) {
5361                 /* According to datasheet, only vector 0/1/2 can be used,
5362                  * now only one vector is used for Rx queue
5363                  */
5364                 intr_vector = 1;
5365                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5366                         return -1;
5367         }
5368
5369         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5370                 intr_handle->intr_vec =
5371                         rte_zmalloc("intr_vec",
5372                                     dev->data->nb_rx_queues * sizeof(int), 0);
5373                 if (intr_handle->intr_vec == NULL) {
5374                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5375                                      " intr_vec", dev->data->nb_rx_queues);
5376                         return -ENOMEM;
5377                 }
5378         }
5379         ixgbevf_configure_msix(dev);
5380
5381         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5382          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5383          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5384          * is not cleared, it will fail when following rte_intr_enable( ) tries
5385          * to map Rx queue interrupt to other VFIO vectors.
5386          * So clear uio/vfio intr/evevnfd first to avoid failure.
5387          */
5388         rte_intr_disable(intr_handle);
5389
5390         rte_intr_enable(intr_handle);
5391
5392         /* Re-enable interrupt for VF */
5393         ixgbevf_intr_enable(dev);
5394
5395         /*
5396          * Update link status right before return, because it may
5397          * start link configuration process in a separate thread.
5398          */
5399         ixgbevf_dev_link_update(dev, 0);
5400
5401         hw->adapter_stopped = false;
5402
5403         return 0;
5404 }
5405
5406 static void
5407 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5408 {
5409         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5410         struct ixgbe_adapter *adapter = dev->data->dev_private;
5411         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5412         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5413
5414         if (hw->adapter_stopped)
5415                 return;
5416
5417         PMD_INIT_FUNC_TRACE();
5418
5419         ixgbe_dev_wait_setup_link_complete(dev, 0);
5420
5421         ixgbevf_intr_disable(dev);
5422
5423         hw->adapter_stopped = 1;
5424         ixgbe_stop_adapter(hw);
5425
5426         /*
5427           * Clear what we set, but we still keep shadow_vfta to
5428           * restore after device starts
5429           */
5430         ixgbevf_set_vfta_all(dev, 0);
5431
5432         /* Clear stored conf */
5433         dev->data->scattered_rx = 0;
5434
5435         ixgbe_dev_clear_queues(dev);
5436
5437         /* Clean datapath event and queue/vec mapping */
5438         rte_intr_efd_disable(intr_handle);
5439         if (intr_handle->intr_vec != NULL) {
5440                 rte_free(intr_handle->intr_vec);
5441                 intr_handle->intr_vec = NULL;
5442         }
5443
5444         adapter->rss_reta_updated = 0;
5445 }
5446
5447 static void
5448 ixgbevf_dev_close(struct rte_eth_dev *dev)
5449 {
5450         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5451         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5452         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5453
5454         PMD_INIT_FUNC_TRACE();
5455
5456         ixgbe_reset_hw(hw);
5457
5458         ixgbevf_dev_stop(dev);
5459
5460         ixgbe_dev_free_queues(dev);
5461
5462         /**
5463          * Remove the VF MAC address ro ensure
5464          * that the VF traffic goes to the PF
5465          * after stop, close and detach of the VF
5466          **/
5467         ixgbevf_remove_mac_addr(dev, 0);
5468
5469         dev->dev_ops = NULL;
5470         dev->rx_pkt_burst = NULL;
5471         dev->tx_pkt_burst = NULL;
5472
5473         rte_intr_disable(intr_handle);
5474         rte_intr_callback_unregister(intr_handle,
5475                                      ixgbevf_dev_interrupt_handler, dev);
5476 }
5477
5478 /*
5479  * Reset VF device
5480  */
5481 static int
5482 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5483 {
5484         int ret;
5485
5486         ret = eth_ixgbevf_dev_uninit(dev);
5487         if (ret)
5488                 return ret;
5489
5490         ret = eth_ixgbevf_dev_init(dev);
5491
5492         return ret;
5493 }
5494
5495 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5496 {
5497         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5498         struct ixgbe_vfta *shadow_vfta =
5499                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5500         int i = 0, j = 0, vfta = 0, mask = 1;
5501
5502         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5503                 vfta = shadow_vfta->vfta[i];
5504                 if (vfta) {
5505                         mask = 1;
5506                         for (j = 0; j < 32; j++) {
5507                                 if (vfta & mask)
5508                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5509                                                        on, false);
5510                                 mask <<= 1;
5511                         }
5512                 }
5513         }
5514
5515 }
5516
5517 static int
5518 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5519 {
5520         struct ixgbe_hw *hw =
5521                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5522         struct ixgbe_vfta *shadow_vfta =
5523                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5524         uint32_t vid_idx = 0;
5525         uint32_t vid_bit = 0;
5526         int ret = 0;
5527
5528         PMD_INIT_FUNC_TRACE();
5529
5530         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5531         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5532         if (ret) {
5533                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5534                 return ret;
5535         }
5536         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5537         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5538
5539         /* Save what we set and retore it after device reset */
5540         if (on)
5541                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5542         else
5543                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5544
5545         return 0;
5546 }
5547
5548 static void
5549 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5550 {
5551         struct ixgbe_hw *hw =
5552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5553         uint32_t ctrl;
5554
5555         PMD_INIT_FUNC_TRACE();
5556
5557         if (queue >= hw->mac.max_rx_queues)
5558                 return;
5559
5560         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5561         if (on)
5562                 ctrl |= IXGBE_RXDCTL_VME;
5563         else
5564                 ctrl &= ~IXGBE_RXDCTL_VME;
5565         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5566
5567         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5568 }
5569
5570 static int
5571 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5572 {
5573         struct ixgbe_rx_queue *rxq;
5574         uint16_t i;
5575         int on = 0;
5576
5577         /* VF function only support hw strip feature, others are not support */
5578         if (mask & ETH_VLAN_STRIP_MASK) {
5579                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5580                         rxq = dev->data->rx_queues[i];
5581                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5582                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5583                 }
5584         }
5585
5586         return 0;
5587 }
5588
5589 static int
5590 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5591 {
5592         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5593
5594         ixgbevf_vlan_offload_config(dev, mask);
5595
5596         return 0;
5597 }
5598
5599 int
5600 ixgbe_vt_check(struct ixgbe_hw *hw)
5601 {
5602         uint32_t reg_val;
5603
5604         /* if Virtualization Technology is enabled */
5605         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5606         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5607                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5608                 return -1;
5609         }
5610
5611         return 0;
5612 }
5613
5614 static uint32_t
5615 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5616 {
5617         uint32_t vector = 0;
5618
5619         switch (hw->mac.mc_filter_type) {
5620         case 0:   /* use bits [47:36] of the address */
5621                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5622                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5623                 break;
5624         case 1:   /* use bits [46:35] of the address */
5625                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5626                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5627                 break;
5628         case 2:   /* use bits [45:34] of the address */
5629                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5630                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5631                 break;
5632         case 3:   /* use bits [43:32] of the address */
5633                 vector = ((uc_addr->addr_bytes[4]) |
5634                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5635                 break;
5636         default:  /* Invalid mc_filter_type */
5637                 break;
5638         }
5639
5640         /* vector can only be 12-bits or boundary will be exceeded */
5641         vector &= 0xFFF;
5642         return vector;
5643 }
5644
5645 static int
5646 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5647                         struct rte_ether_addr *mac_addr, uint8_t on)
5648 {
5649         uint32_t vector;
5650         uint32_t uta_idx;
5651         uint32_t reg_val;
5652         uint32_t uta_shift;
5653         uint32_t rc;
5654         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5655         const uint32_t ixgbe_uta_bit_shift = 5;
5656         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5657         const uint32_t bit1 = 0x1;
5658
5659         struct ixgbe_hw *hw =
5660                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5661         struct ixgbe_uta_info *uta_info =
5662                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5663
5664         /* The UTA table only exists on 82599 hardware and newer */
5665         if (hw->mac.type < ixgbe_mac_82599EB)
5666                 return -ENOTSUP;
5667
5668         vector = ixgbe_uta_vector(hw, mac_addr);
5669         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5670         uta_shift = vector & ixgbe_uta_bit_mask;
5671
5672         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5673         if (rc == on)
5674                 return 0;
5675
5676         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5677         if (on) {
5678                 uta_info->uta_in_use++;
5679                 reg_val |= (bit1 << uta_shift);
5680                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5681         } else {
5682                 uta_info->uta_in_use--;
5683                 reg_val &= ~(bit1 << uta_shift);
5684                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5685         }
5686
5687         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5688
5689         if (uta_info->uta_in_use > 0)
5690                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5691                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5692         else
5693                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5694
5695         return 0;
5696 }
5697
5698 static int
5699 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5700 {
5701         int i;
5702         struct ixgbe_hw *hw =
5703                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5704         struct ixgbe_uta_info *uta_info =
5705                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5706
5707         /* The UTA table only exists on 82599 hardware and newer */
5708         if (hw->mac.type < ixgbe_mac_82599EB)
5709                 return -ENOTSUP;
5710
5711         if (on) {
5712                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5713                         uta_info->uta_shadow[i] = ~0;
5714                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5715                 }
5716         } else {
5717                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5718                         uta_info->uta_shadow[i] = 0;
5719                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5720                 }
5721         }
5722         return 0;
5723
5724 }
5725
5726 uint32_t
5727 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5728 {
5729         uint32_t new_val = orig_val;
5730
5731         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5732                 new_val |= IXGBE_VMOLR_AUPE;
5733         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5734                 new_val |= IXGBE_VMOLR_ROMPE;
5735         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5736                 new_val |= IXGBE_VMOLR_ROPE;
5737         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5738                 new_val |= IXGBE_VMOLR_BAM;
5739         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5740                 new_val |= IXGBE_VMOLR_MPE;
5741
5742         return new_val;
5743 }
5744
5745 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5746 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5747 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5748 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5749 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5750         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5751         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5752
5753 static int
5754 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5755                       struct rte_eth_mirror_conf *mirror_conf,
5756                       uint8_t rule_id, uint8_t on)
5757 {
5758         uint32_t mr_ctl, vlvf;
5759         uint32_t mp_lsb = 0;
5760         uint32_t mv_msb = 0;
5761         uint32_t mv_lsb = 0;
5762         uint32_t mp_msb = 0;
5763         uint8_t i = 0;
5764         int reg_index = 0;
5765         uint64_t vlan_mask = 0;
5766
5767         const uint8_t pool_mask_offset = 32;
5768         const uint8_t vlan_mask_offset = 32;
5769         const uint8_t dst_pool_offset = 8;
5770         const uint8_t rule_mr_offset  = 4;
5771         const uint8_t mirror_rule_mask = 0x0F;
5772
5773         struct ixgbe_mirror_info *mr_info =
5774                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5775         struct ixgbe_hw *hw =
5776                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5777         uint8_t mirror_type = 0;
5778
5779         if (ixgbe_vt_check(hw) < 0)
5780                 return -ENOTSUP;
5781
5782         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5783                 return -EINVAL;
5784
5785         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5786                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5787                             mirror_conf->rule_type);
5788                 return -EINVAL;
5789         }
5790
5791         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5792                 mirror_type |= IXGBE_MRCTL_VLME;
5793                 /* Check if vlan id is valid and find conresponding VLAN ID
5794                  * index in VLVF
5795                  */
5796                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5797                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5798                                 /* search vlan id related pool vlan filter
5799                                  * index
5800                                  */
5801                                 reg_index = ixgbe_find_vlvf_slot(
5802                                                 hw,
5803                                                 mirror_conf->vlan.vlan_id[i],
5804                                                 false);
5805                                 if (reg_index < 0)
5806                                         return -EINVAL;
5807                                 vlvf = IXGBE_READ_REG(hw,
5808                                                       IXGBE_VLVF(reg_index));
5809                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5810                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5811                                       mirror_conf->vlan.vlan_id[i]))
5812                                         vlan_mask |= (1ULL << reg_index);
5813                                 else
5814                                         return -EINVAL;
5815                         }
5816                 }
5817
5818                 if (on) {
5819                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5820                         mv_msb = vlan_mask >> vlan_mask_offset;
5821
5822                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5823                                                 mirror_conf->vlan.vlan_mask;
5824                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5825                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5826                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5827                                                 mirror_conf->vlan.vlan_id[i];
5828                         }
5829                 } else {
5830                         mv_lsb = 0;
5831                         mv_msb = 0;
5832                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5833                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5834                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5835                 }
5836         }
5837
5838         /**
5839          * if enable pool mirror, write related pool mask register,if disable
5840          * pool mirror, clear PFMRVM register
5841          */
5842         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5843                 mirror_type |= IXGBE_MRCTL_VPME;
5844                 if (on) {
5845                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5846                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5847                         mr_info->mr_conf[rule_id].pool_mask =
5848                                         mirror_conf->pool_mask;
5849
5850                 } else {
5851                         mp_lsb = 0;
5852                         mp_msb = 0;
5853                         mr_info->mr_conf[rule_id].pool_mask = 0;
5854                 }
5855         }
5856         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5857                 mirror_type |= IXGBE_MRCTL_UPME;
5858         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5859                 mirror_type |= IXGBE_MRCTL_DPME;
5860
5861         /* read  mirror control register and recalculate it */
5862         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5863
5864         if (on) {
5865                 mr_ctl |= mirror_type;
5866                 mr_ctl &= mirror_rule_mask;
5867                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5868         } else {
5869                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5870         }
5871
5872         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5873         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5874
5875         /* write mirrror control  register */
5876         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5877
5878         /* write pool mirrror control  register */
5879         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5880                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5881                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5882                                 mp_msb);
5883         }
5884         /* write VLAN mirrror control  register */
5885         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5886                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5887                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5888                                 mv_msb);
5889         }
5890
5891         return 0;
5892 }
5893
5894 static int
5895 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5896 {
5897         int mr_ctl = 0;
5898         uint32_t lsb_val = 0;
5899         uint32_t msb_val = 0;
5900         const uint8_t rule_mr_offset = 4;
5901
5902         struct ixgbe_hw *hw =
5903                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5904         struct ixgbe_mirror_info *mr_info =
5905                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5906
5907         if (ixgbe_vt_check(hw) < 0)
5908                 return -ENOTSUP;
5909
5910         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5911                 return -EINVAL;
5912
5913         memset(&mr_info->mr_conf[rule_id], 0,
5914                sizeof(struct rte_eth_mirror_conf));
5915
5916         /* clear PFVMCTL register */
5917         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5918
5919         /* clear pool mask register */
5920         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5921         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5922
5923         /* clear vlan mask register */
5924         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5925         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5926
5927         return 0;
5928 }
5929
5930 static int
5931 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5932 {
5933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5934         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5935         struct ixgbe_interrupt *intr =
5936                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5937         struct ixgbe_hw *hw =
5938                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5939         uint32_t vec = IXGBE_MISC_VEC_ID;
5940
5941         if (rte_intr_allow_others(intr_handle))
5942                 vec = IXGBE_RX_VEC_START;
5943         intr->mask |= (1 << vec);
5944         RTE_SET_USED(queue_id);
5945         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5946
5947         rte_intr_ack(intr_handle);
5948
5949         return 0;
5950 }
5951
5952 static int
5953 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5954 {
5955         struct ixgbe_interrupt *intr =
5956                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5957         struct ixgbe_hw *hw =
5958                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5961         uint32_t vec = IXGBE_MISC_VEC_ID;
5962
5963         if (rte_intr_allow_others(intr_handle))
5964                 vec = IXGBE_RX_VEC_START;
5965         intr->mask &= ~(1 << vec);
5966         RTE_SET_USED(queue_id);
5967         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5968
5969         return 0;
5970 }
5971
5972 static int
5973 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5974 {
5975         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5976         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5977         uint32_t mask;
5978         struct ixgbe_hw *hw =
5979                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5980         struct ixgbe_interrupt *intr =
5981                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5982
5983         if (queue_id < 16) {
5984                 ixgbe_disable_intr(hw);
5985                 intr->mask |= (1 << queue_id);
5986                 ixgbe_enable_intr(dev);
5987         } else if (queue_id < 32) {
5988                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5989                 mask &= (1 << queue_id);
5990                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5991         } else if (queue_id < 64) {
5992                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5993                 mask &= (1 << (queue_id - 32));
5994                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5995         }
5996         rte_intr_ack(intr_handle);
5997
5998         return 0;
5999 }
6000
6001 static int
6002 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
6003 {
6004         uint32_t mask;
6005         struct ixgbe_hw *hw =
6006                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6007         struct ixgbe_interrupt *intr =
6008                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
6009
6010         if (queue_id < 16) {
6011                 ixgbe_disable_intr(hw);
6012                 intr->mask &= ~(1 << queue_id);
6013                 ixgbe_enable_intr(dev);
6014         } else if (queue_id < 32) {
6015                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6016                 mask &= ~(1 << queue_id);
6017                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6018         } else if (queue_id < 64) {
6019                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6020                 mask &= ~(1 << (queue_id - 32));
6021                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6022         }
6023
6024         return 0;
6025 }
6026
6027 static void
6028 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6029                      uint8_t queue, uint8_t msix_vector)
6030 {
6031         uint32_t tmp, idx;
6032
6033         if (direction == -1) {
6034                 /* other causes */
6035                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6036                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6037                 tmp &= ~0xFF;
6038                 tmp |= msix_vector;
6039                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6040         } else {
6041                 /* rx or tx cause */
6042                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6043                 idx = ((16 * (queue & 1)) + (8 * direction));
6044                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6045                 tmp &= ~(0xFF << idx);
6046                 tmp |= (msix_vector << idx);
6047                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6048         }
6049 }
6050
6051 /**
6052  * set the IVAR registers, mapping interrupt causes to vectors
6053  * @param hw
6054  *  pointer to ixgbe_hw struct
6055  * @direction
6056  *  0 for Rx, 1 for Tx, -1 for other causes
6057  * @queue
6058  *  queue to map the corresponding interrupt to
6059  * @msix_vector
6060  *  the vector to map to the corresponding queue
6061  */
6062 static void
6063 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6064                    uint8_t queue, uint8_t msix_vector)
6065 {
6066         uint32_t tmp, idx;
6067
6068         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6069         if (hw->mac.type == ixgbe_mac_82598EB) {
6070                 if (direction == -1)
6071                         direction = 0;
6072                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6073                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6074                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6075                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6076                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6077         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6078                         (hw->mac.type == ixgbe_mac_X540) ||
6079                         (hw->mac.type == ixgbe_mac_X550) ||
6080                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6081                 if (direction == -1) {
6082                         /* other causes */
6083                         idx = ((queue & 1) * 8);
6084                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6085                         tmp &= ~(0xFF << idx);
6086                         tmp |= (msix_vector << idx);
6087                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6088                 } else {
6089                         /* rx or tx causes */
6090                         idx = ((16 * (queue & 1)) + (8 * direction));
6091                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6092                         tmp &= ~(0xFF << idx);
6093                         tmp |= (msix_vector << idx);
6094                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6095                 }
6096         }
6097 }
6098
6099 static void
6100 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6101 {
6102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6103         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6104         struct ixgbe_hw *hw =
6105                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6106         uint32_t q_idx;
6107         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6108         uint32_t base = IXGBE_MISC_VEC_ID;
6109
6110         /* Configure VF other cause ivar */
6111         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6112
6113         /* won't configure msix register if no mapping is done
6114          * between intr vector and event fd.
6115          */
6116         if (!rte_intr_dp_is_en(intr_handle))
6117                 return;
6118
6119         if (rte_intr_allow_others(intr_handle)) {
6120                 base = IXGBE_RX_VEC_START;
6121                 vector_idx = IXGBE_RX_VEC_START;
6122         }
6123
6124         /* Configure all RX queues of VF */
6125         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6126                 /* Force all queue use vector 0,
6127                  * as IXGBE_VF_MAXMSIVECOTR = 1
6128                  */
6129                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6130                 intr_handle->intr_vec[q_idx] = vector_idx;
6131                 if (vector_idx < base + intr_handle->nb_efd - 1)
6132                         vector_idx++;
6133         }
6134
6135         /* As RX queue setting above show, all queues use the vector 0.
6136          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6137          */
6138         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6139                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6140                         | IXGBE_EITR_CNT_WDIS);
6141 }
6142
6143 /**
6144  * Sets up the hardware to properly generate MSI-X interrupts
6145  * @hw
6146  *  board private structure
6147  */
6148 static void
6149 ixgbe_configure_msix(struct rte_eth_dev *dev)
6150 {
6151         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6152         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6153         struct ixgbe_hw *hw =
6154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6155         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6156         uint32_t vec = IXGBE_MISC_VEC_ID;
6157         uint32_t mask;
6158         uint32_t gpie;
6159
6160         /* won't configure msix register if no mapping is done
6161          * between intr vector and event fd
6162          * but if misx has been enabled already, need to configure
6163          * auto clean, auto mask and throttling.
6164          */
6165         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6166         if (!rte_intr_dp_is_en(intr_handle) &&
6167             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6168                 return;
6169
6170         if (rte_intr_allow_others(intr_handle))
6171                 vec = base = IXGBE_RX_VEC_START;
6172
6173         /* setup GPIE for MSI-x mode */
6174         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6175         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6176                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6177         /* auto clearing and auto setting corresponding bits in EIMS
6178          * when MSI-X interrupt is triggered
6179          */
6180         if (hw->mac.type == ixgbe_mac_82598EB) {
6181                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6182         } else {
6183                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6184                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6185         }
6186         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6187
6188         /* Populate the IVAR table and set the ITR values to the
6189          * corresponding register.
6190          */
6191         if (rte_intr_dp_is_en(intr_handle)) {
6192                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6193                         queue_id++) {
6194                         /* by default, 1:1 mapping */
6195                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6196                         intr_handle->intr_vec[queue_id] = vec;
6197                         if (vec < base + intr_handle->nb_efd - 1)
6198                                 vec++;
6199                 }
6200
6201                 switch (hw->mac.type) {
6202                 case ixgbe_mac_82598EB:
6203                         ixgbe_set_ivar_map(hw, -1,
6204                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6205                                            IXGBE_MISC_VEC_ID);
6206                         break;
6207                 case ixgbe_mac_82599EB:
6208                 case ixgbe_mac_X540:
6209                 case ixgbe_mac_X550:
6210                 case ixgbe_mac_X550EM_x:
6211                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6212                         break;
6213                 default:
6214                         break;
6215                 }
6216         }
6217         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6218                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6219                         | IXGBE_EITR_CNT_WDIS);
6220
6221         /* set up to autoclear timer, and the vectors */
6222         mask = IXGBE_EIMS_ENABLE_MASK;
6223         mask &= ~(IXGBE_EIMS_OTHER |
6224                   IXGBE_EIMS_MAILBOX |
6225                   IXGBE_EIMS_LSC);
6226
6227         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6228 }
6229
6230 int
6231 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6232                            uint16_t queue_idx, uint16_t tx_rate)
6233 {
6234         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6235         struct rte_eth_rxmode *rxmode;
6236         uint32_t rf_dec, rf_int;
6237         uint32_t bcnrc_val;
6238         uint16_t link_speed = dev->data->dev_link.link_speed;
6239
6240         if (queue_idx >= hw->mac.max_tx_queues)
6241                 return -EINVAL;
6242
6243         if (tx_rate != 0) {
6244                 /* Calculate the rate factor values to set */
6245                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6246                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6247                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6248
6249                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6250                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6251                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6252                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6253         } else {
6254                 bcnrc_val = 0;
6255         }
6256
6257         rxmode = &dev->data->dev_conf.rxmode;
6258         /*
6259          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6260          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6261          * set as 0x4.
6262          */
6263         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6264             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6265                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6266                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6267         else
6268                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6269                         IXGBE_MMW_SIZE_DEFAULT);
6270
6271         /* Set RTTBCNRC of queue X */
6272         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6273         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6274         IXGBE_WRITE_FLUSH(hw);
6275
6276         return 0;
6277 }
6278
6279 static int
6280 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6281                      __rte_unused uint32_t index,
6282                      __rte_unused uint32_t pool)
6283 {
6284         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6285         int diag;
6286
6287         /*
6288          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6289          * operation. Trap this case to avoid exhausting the [very limited]
6290          * set of PF resources used to store VF MAC addresses.
6291          */
6292         if (memcmp(hw->mac.perm_addr, mac_addr,
6293                         sizeof(struct rte_ether_addr)) == 0)
6294                 return -1;
6295         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6296         if (diag != 0)
6297                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6298                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6299                             mac_addr->addr_bytes[0],
6300                             mac_addr->addr_bytes[1],
6301                             mac_addr->addr_bytes[2],
6302                             mac_addr->addr_bytes[3],
6303                             mac_addr->addr_bytes[4],
6304                             mac_addr->addr_bytes[5],
6305                             diag);
6306         return diag;
6307 }
6308
6309 static void
6310 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6311 {
6312         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6313         struct rte_ether_addr *perm_addr =
6314                 (struct rte_ether_addr *)hw->mac.perm_addr;
6315         struct rte_ether_addr *mac_addr;
6316         uint32_t i;
6317         int diag;
6318
6319         /*
6320          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6321          * not support the deletion of a given MAC address.
6322          * Instead, it imposes to delete all MAC addresses, then to add again
6323          * all MAC addresses with the exception of the one to be deleted.
6324          */
6325         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6326
6327         /*
6328          * Add again all MAC addresses, with the exception of the deleted one
6329          * and of the permanent MAC address.
6330          */
6331         for (i = 0, mac_addr = dev->data->mac_addrs;
6332              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6333                 /* Skip the deleted MAC address */
6334                 if (i == index)
6335                         continue;
6336                 /* Skip NULL MAC addresses */
6337                 if (rte_is_zero_ether_addr(mac_addr))
6338                         continue;
6339                 /* Skip the permanent MAC address */
6340                 if (memcmp(perm_addr, mac_addr,
6341                                 sizeof(struct rte_ether_addr)) == 0)
6342                         continue;
6343                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6344                 if (diag != 0)
6345                         PMD_DRV_LOG(ERR,
6346                                     "Adding again MAC address "
6347                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6348                                     "diag=%d",
6349                                     mac_addr->addr_bytes[0],
6350                                     mac_addr->addr_bytes[1],
6351                                     mac_addr->addr_bytes[2],
6352                                     mac_addr->addr_bytes[3],
6353                                     mac_addr->addr_bytes[4],
6354                                     mac_addr->addr_bytes[5],
6355                                     diag);
6356         }
6357 }
6358
6359 static int
6360 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6361                         struct rte_ether_addr *addr)
6362 {
6363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6364
6365         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6366
6367         return 0;
6368 }
6369
6370 int
6371 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6372                         struct rte_eth_syn_filter *filter,
6373                         bool add)
6374 {
6375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376         struct ixgbe_filter_info *filter_info =
6377                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6378         uint32_t syn_info;
6379         uint32_t synqf;
6380
6381         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6382                 return -EINVAL;
6383
6384         syn_info = filter_info->syn_info;
6385
6386         if (add) {
6387                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6388                         return -EINVAL;
6389                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6390                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6391
6392                 if (filter->hig_pri)
6393                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6394                 else
6395                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6396         } else {
6397                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6398                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6399                         return -ENOENT;
6400                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6401         }
6402
6403         filter_info->syn_info = synqf;
6404         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6405         IXGBE_WRITE_FLUSH(hw);
6406         return 0;
6407 }
6408
6409 static int
6410 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6411                         struct rte_eth_syn_filter *filter)
6412 {
6413         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6414         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6415
6416         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6417                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6418                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6419                 return 0;
6420         }
6421         return -ENOENT;
6422 }
6423
6424 static int
6425 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6426                         enum rte_filter_op filter_op,
6427                         void *arg)
6428 {
6429         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6430         int ret;
6431
6432         MAC_TYPE_FILTER_SUP(hw->mac.type);
6433
6434         if (filter_op == RTE_ETH_FILTER_NOP)
6435                 return 0;
6436
6437         if (arg == NULL) {
6438                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6439                             filter_op);
6440                 return -EINVAL;
6441         }
6442
6443         switch (filter_op) {
6444         case RTE_ETH_FILTER_ADD:
6445                 ret = ixgbe_syn_filter_set(dev,
6446                                 (struct rte_eth_syn_filter *)arg,
6447                                 TRUE);
6448                 break;
6449         case RTE_ETH_FILTER_DELETE:
6450                 ret = ixgbe_syn_filter_set(dev,
6451                                 (struct rte_eth_syn_filter *)arg,
6452                                 FALSE);
6453                 break;
6454         case RTE_ETH_FILTER_GET:
6455                 ret = ixgbe_syn_filter_get(dev,
6456                                 (struct rte_eth_syn_filter *)arg);
6457                 break;
6458         default:
6459                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6460                 ret = -EINVAL;
6461                 break;
6462         }
6463
6464         return ret;
6465 }
6466
6467
6468 static inline enum ixgbe_5tuple_protocol
6469 convert_protocol_type(uint8_t protocol_value)
6470 {
6471         if (protocol_value == IPPROTO_TCP)
6472                 return IXGBE_FILTER_PROTOCOL_TCP;
6473         else if (protocol_value == IPPROTO_UDP)
6474                 return IXGBE_FILTER_PROTOCOL_UDP;
6475         else if (protocol_value == IPPROTO_SCTP)
6476                 return IXGBE_FILTER_PROTOCOL_SCTP;
6477         else
6478                 return IXGBE_FILTER_PROTOCOL_NONE;
6479 }
6480
6481 /* inject a 5-tuple filter to HW */
6482 static inline void
6483 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6484                            struct ixgbe_5tuple_filter *filter)
6485 {
6486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6487         int i;
6488         uint32_t ftqf, sdpqf;
6489         uint32_t l34timir = 0;
6490         uint8_t mask = 0xff;
6491
6492         i = filter->index;
6493
6494         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6495                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6496         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6497
6498         ftqf = (uint32_t)(filter->filter_info.proto &
6499                 IXGBE_FTQF_PROTOCOL_MASK);
6500         ftqf |= (uint32_t)((filter->filter_info.priority &
6501                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6502         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6503                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6504         if (filter->filter_info.dst_ip_mask == 0)
6505                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6506         if (filter->filter_info.src_port_mask == 0)
6507                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6508         if (filter->filter_info.dst_port_mask == 0)
6509                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6510         if (filter->filter_info.proto_mask == 0)
6511                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6512         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6513         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6514         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6515
6516         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6517         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6518         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6519         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6520
6521         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6522         l34timir |= (uint32_t)(filter->queue <<
6523                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6524         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6525 }
6526
6527 /*
6528  * add a 5tuple filter
6529  *
6530  * @param
6531  * dev: Pointer to struct rte_eth_dev.
6532  * index: the index the filter allocates.
6533  * filter: ponter to the filter that will be added.
6534  * rx_queue: the queue id the filter assigned to.
6535  *
6536  * @return
6537  *    - On success, zero.
6538  *    - On failure, a negative value.
6539  */
6540 static int
6541 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6542                         struct ixgbe_5tuple_filter *filter)
6543 {
6544         struct ixgbe_filter_info *filter_info =
6545                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6546         int i, idx, shift;
6547
6548         /*
6549          * look for an unused 5tuple filter index,
6550          * and insert the filter to list.
6551          */
6552         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6553                 idx = i / (sizeof(uint32_t) * NBBY);
6554                 shift = i % (sizeof(uint32_t) * NBBY);
6555                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6556                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6557                         filter->index = i;
6558                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6559                                           filter,
6560                                           entries);
6561                         break;
6562                 }
6563         }
6564         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6565                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6566                 return -ENOSYS;
6567         }
6568
6569         ixgbe_inject_5tuple_filter(dev, filter);
6570
6571         return 0;
6572 }
6573
6574 /*
6575  * remove a 5tuple filter
6576  *
6577  * @param
6578  * dev: Pointer to struct rte_eth_dev.
6579  * filter: the pointer of the filter will be removed.
6580  */
6581 static void
6582 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6583                         struct ixgbe_5tuple_filter *filter)
6584 {
6585         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6586         struct ixgbe_filter_info *filter_info =
6587                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6588         uint16_t index = filter->index;
6589
6590         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6591                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6592         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6593         rte_free(filter);
6594
6595         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6596         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6597         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6598         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6599         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6600 }
6601
6602 static int
6603 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6604 {
6605         struct ixgbe_hw *hw;
6606         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6607         struct rte_eth_dev_data *dev_data = dev->data;
6608
6609         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6610
6611         if (mtu < RTE_ETHER_MIN_MTU ||
6612                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6613                 return -EINVAL;
6614
6615         /* If device is started, refuse mtu that requires the support of
6616          * scattered packets when this feature has not been enabled before.
6617          */
6618         if (dev_data->dev_started && !dev_data->scattered_rx &&
6619             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6620              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6621                 PMD_INIT_LOG(ERR, "Stop port first.");
6622                 return -EINVAL;
6623         }
6624
6625         /*
6626          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6627          * request of the version 2.0 of the mailbox API.
6628          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6629          * of the mailbox API.
6630          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6631          * prior to 3.11.33 which contains the following change:
6632          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6633          */
6634         ixgbevf_rlpml_set_vf(hw, max_frame);
6635
6636         /* update max frame size */
6637         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6638         return 0;
6639 }
6640
6641 static inline struct ixgbe_5tuple_filter *
6642 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6643                         struct ixgbe_5tuple_filter_info *key)
6644 {
6645         struct ixgbe_5tuple_filter *it;
6646
6647         TAILQ_FOREACH(it, filter_list, entries) {
6648                 if (memcmp(key, &it->filter_info,
6649                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6650                         return it;
6651                 }
6652         }
6653         return NULL;
6654 }
6655
6656 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6657 static inline int
6658 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6659                         struct ixgbe_5tuple_filter_info *filter_info)
6660 {
6661         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6662                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6663                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6664                 return -EINVAL;
6665
6666         switch (filter->dst_ip_mask) {
6667         case UINT32_MAX:
6668                 filter_info->dst_ip_mask = 0;
6669                 filter_info->dst_ip = filter->dst_ip;
6670                 break;
6671         case 0:
6672                 filter_info->dst_ip_mask = 1;
6673                 break;
6674         default:
6675                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6676                 return -EINVAL;
6677         }
6678
6679         switch (filter->src_ip_mask) {
6680         case UINT32_MAX:
6681                 filter_info->src_ip_mask = 0;
6682                 filter_info->src_ip = filter->src_ip;
6683                 break;
6684         case 0:
6685                 filter_info->src_ip_mask = 1;
6686                 break;
6687         default:
6688                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6689                 return -EINVAL;
6690         }
6691
6692         switch (filter->dst_port_mask) {
6693         case UINT16_MAX:
6694                 filter_info->dst_port_mask = 0;
6695                 filter_info->dst_port = filter->dst_port;
6696                 break;
6697         case 0:
6698                 filter_info->dst_port_mask = 1;
6699                 break;
6700         default:
6701                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6702                 return -EINVAL;
6703         }
6704
6705         switch (filter->src_port_mask) {
6706         case UINT16_MAX:
6707                 filter_info->src_port_mask = 0;
6708                 filter_info->src_port = filter->src_port;
6709                 break;
6710         case 0:
6711                 filter_info->src_port_mask = 1;
6712                 break;
6713         default:
6714                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6715                 return -EINVAL;
6716         }
6717
6718         switch (filter->proto_mask) {
6719         case UINT8_MAX:
6720                 filter_info->proto_mask = 0;
6721                 filter_info->proto =
6722                         convert_protocol_type(filter->proto);
6723                 break;
6724         case 0:
6725                 filter_info->proto_mask = 1;
6726                 break;
6727         default:
6728                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6729                 return -EINVAL;
6730         }
6731
6732         filter_info->priority = (uint8_t)filter->priority;
6733         return 0;
6734 }
6735
6736 /*
6737  * add or delete a ntuple filter
6738  *
6739  * @param
6740  * dev: Pointer to struct rte_eth_dev.
6741  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6742  * add: if true, add filter, if false, remove filter
6743  *
6744  * @return
6745  *    - On success, zero.
6746  *    - On failure, a negative value.
6747  */
6748 int
6749 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6750                         struct rte_eth_ntuple_filter *ntuple_filter,
6751                         bool add)
6752 {
6753         struct ixgbe_filter_info *filter_info =
6754                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6755         struct ixgbe_5tuple_filter_info filter_5tuple;
6756         struct ixgbe_5tuple_filter *filter;
6757         int ret;
6758
6759         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6760                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6761                 return -EINVAL;
6762         }
6763
6764         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6765         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6766         if (ret < 0)
6767                 return ret;
6768
6769         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6770                                          &filter_5tuple);
6771         if (filter != NULL && add) {
6772                 PMD_DRV_LOG(ERR, "filter exists.");
6773                 return -EEXIST;
6774         }
6775         if (filter == NULL && !add) {
6776                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6777                 return -ENOENT;
6778         }
6779
6780         if (add) {
6781                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6782                                 sizeof(struct ixgbe_5tuple_filter), 0);
6783                 if (filter == NULL)
6784                         return -ENOMEM;
6785                 rte_memcpy(&filter->filter_info,
6786                                  &filter_5tuple,
6787                                  sizeof(struct ixgbe_5tuple_filter_info));
6788                 filter->queue = ntuple_filter->queue;
6789                 ret = ixgbe_add_5tuple_filter(dev, filter);
6790                 if (ret < 0) {
6791                         rte_free(filter);
6792                         return ret;
6793                 }
6794         } else
6795                 ixgbe_remove_5tuple_filter(dev, filter);
6796
6797         return 0;
6798 }
6799
6800 /*
6801  * get a ntuple filter
6802  *
6803  * @param
6804  * dev: Pointer to struct rte_eth_dev.
6805  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6806  *
6807  * @return
6808  *    - On success, zero.
6809  *    - On failure, a negative value.
6810  */
6811 static int
6812 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6813                         struct rte_eth_ntuple_filter *ntuple_filter)
6814 {
6815         struct ixgbe_filter_info *filter_info =
6816                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6817         struct ixgbe_5tuple_filter_info filter_5tuple;
6818         struct ixgbe_5tuple_filter *filter;
6819         int ret;
6820
6821         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6822                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6823                 return -EINVAL;
6824         }
6825
6826         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6827         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6828         if (ret < 0)
6829                 return ret;
6830
6831         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6832                                          &filter_5tuple);
6833         if (filter == NULL) {
6834                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6835                 return -ENOENT;
6836         }
6837         ntuple_filter->queue = filter->queue;
6838         return 0;
6839 }
6840
6841 /*
6842  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6843  * @dev: pointer to rte_eth_dev structure
6844  * @filter_op:operation will be taken.
6845  * @arg: a pointer to specific structure corresponding to the filter_op
6846  *
6847  * @return
6848  *    - On success, zero.
6849  *    - On failure, a negative value.
6850  */
6851 static int
6852 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6853                                 enum rte_filter_op filter_op,
6854                                 void *arg)
6855 {
6856         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6857         int ret;
6858
6859         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6860
6861         if (filter_op == RTE_ETH_FILTER_NOP)
6862                 return 0;
6863
6864         if (arg == NULL) {
6865                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6866                             filter_op);
6867                 return -EINVAL;
6868         }
6869
6870         switch (filter_op) {
6871         case RTE_ETH_FILTER_ADD:
6872                 ret = ixgbe_add_del_ntuple_filter(dev,
6873                         (struct rte_eth_ntuple_filter *)arg,
6874                         TRUE);
6875                 break;
6876         case RTE_ETH_FILTER_DELETE:
6877                 ret = ixgbe_add_del_ntuple_filter(dev,
6878                         (struct rte_eth_ntuple_filter *)arg,
6879                         FALSE);
6880                 break;
6881         case RTE_ETH_FILTER_GET:
6882                 ret = ixgbe_get_ntuple_filter(dev,
6883                         (struct rte_eth_ntuple_filter *)arg);
6884                 break;
6885         default:
6886                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6887                 ret = -EINVAL;
6888                 break;
6889         }
6890         return ret;
6891 }
6892
6893 int
6894 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6895                         struct rte_eth_ethertype_filter *filter,
6896                         bool add)
6897 {
6898         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6899         struct ixgbe_filter_info *filter_info =
6900                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6901         uint32_t etqf = 0;
6902         uint32_t etqs = 0;
6903         int ret;
6904         struct ixgbe_ethertype_filter ethertype_filter;
6905
6906         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6907                 return -EINVAL;
6908
6909         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6910                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6911                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6912                         " ethertype filter.", filter->ether_type);
6913                 return -EINVAL;
6914         }
6915
6916         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6917                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6918                 return -EINVAL;
6919         }
6920         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6921                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6922                 return -EINVAL;
6923         }
6924
6925         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6926         if (ret >= 0 && add) {
6927                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6928                             filter->ether_type);
6929                 return -EEXIST;
6930         }
6931         if (ret < 0 && !add) {
6932                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6933                             filter->ether_type);
6934                 return -ENOENT;
6935         }
6936
6937         if (add) {
6938                 etqf = IXGBE_ETQF_FILTER_EN;
6939                 etqf |= (uint32_t)filter->ether_type;
6940                 etqs |= (uint32_t)((filter->queue <<
6941                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6942                                     IXGBE_ETQS_RX_QUEUE);
6943                 etqs |= IXGBE_ETQS_QUEUE_EN;
6944
6945                 ethertype_filter.ethertype = filter->ether_type;
6946                 ethertype_filter.etqf = etqf;
6947                 ethertype_filter.etqs = etqs;
6948                 ethertype_filter.conf = FALSE;
6949                 ret = ixgbe_ethertype_filter_insert(filter_info,
6950                                                     &ethertype_filter);
6951                 if (ret < 0) {
6952                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6953                         return -ENOSPC;
6954                 }
6955         } else {
6956                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6957                 if (ret < 0)
6958                         return -ENOSYS;
6959         }
6960         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6961         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6962         IXGBE_WRITE_FLUSH(hw);
6963
6964         return 0;
6965 }
6966
6967 static int
6968 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6969                         struct rte_eth_ethertype_filter *filter)
6970 {
6971         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6972         struct ixgbe_filter_info *filter_info =
6973                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6974         uint32_t etqf, etqs;
6975         int ret;
6976
6977         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6978         if (ret < 0) {
6979                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6980                             filter->ether_type);
6981                 return -ENOENT;
6982         }
6983
6984         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6985         if (etqf & IXGBE_ETQF_FILTER_EN) {
6986                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6987                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6988                 filter->flags = 0;
6989                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6990                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6991                 return 0;
6992         }
6993         return -ENOENT;
6994 }
6995
6996 /*
6997  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6998  * @dev: pointer to rte_eth_dev structure
6999  * @filter_op:operation will be taken.
7000  * @arg: a pointer to specific structure corresponding to the filter_op
7001  */
7002 static int
7003 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
7004                                 enum rte_filter_op filter_op,
7005                                 void *arg)
7006 {
7007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7008         int ret;
7009
7010         MAC_TYPE_FILTER_SUP(hw->mac.type);
7011
7012         if (filter_op == RTE_ETH_FILTER_NOP)
7013                 return 0;
7014
7015         if (arg == NULL) {
7016                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7017                             filter_op);
7018                 return -EINVAL;
7019         }
7020
7021         switch (filter_op) {
7022         case RTE_ETH_FILTER_ADD:
7023                 ret = ixgbe_add_del_ethertype_filter(dev,
7024                         (struct rte_eth_ethertype_filter *)arg,
7025                         TRUE);
7026                 break;
7027         case RTE_ETH_FILTER_DELETE:
7028                 ret = ixgbe_add_del_ethertype_filter(dev,
7029                         (struct rte_eth_ethertype_filter *)arg,
7030                         FALSE);
7031                 break;
7032         case RTE_ETH_FILTER_GET:
7033                 ret = ixgbe_get_ethertype_filter(dev,
7034                         (struct rte_eth_ethertype_filter *)arg);
7035                 break;
7036         default:
7037                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7038                 ret = -EINVAL;
7039                 break;
7040         }
7041         return ret;
7042 }
7043
7044 static int
7045 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
7046                      enum rte_filter_type filter_type,
7047                      enum rte_filter_op filter_op,
7048                      void *arg)
7049 {
7050         int ret = 0;
7051
7052         switch (filter_type) {
7053         case RTE_ETH_FILTER_NTUPLE:
7054                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
7055                 break;
7056         case RTE_ETH_FILTER_ETHERTYPE:
7057                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
7058                 break;
7059         case RTE_ETH_FILTER_SYN:
7060                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
7061                 break;
7062         case RTE_ETH_FILTER_FDIR:
7063                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
7064                 break;
7065         case RTE_ETH_FILTER_L2_TUNNEL:
7066                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
7067                 break;
7068         case RTE_ETH_FILTER_GENERIC:
7069                 if (filter_op != RTE_ETH_FILTER_GET)
7070                         return -EINVAL;
7071                 *(const void **)arg = &ixgbe_flow_ops;
7072                 break;
7073         default:
7074                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7075                                                         filter_type);
7076                 ret = -EINVAL;
7077                 break;
7078         }
7079
7080         return ret;
7081 }
7082
7083 static u8 *
7084 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
7085                         u8 **mc_addr_ptr, u32 *vmdq)
7086 {
7087         u8 *mc_addr;
7088
7089         *vmdq = 0;
7090         mc_addr = *mc_addr_ptr;
7091         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
7092         return mc_addr;
7093 }
7094
7095 static int
7096 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
7097                           struct rte_ether_addr *mc_addr_set,
7098                           uint32_t nb_mc_addr)
7099 {
7100         struct ixgbe_hw *hw;
7101         u8 *mc_addr_list;
7102
7103         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7104         mc_addr_list = (u8 *)mc_addr_set;
7105         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
7106                                          ixgbe_dev_addr_list_itr, TRUE);
7107 }
7108
7109 static uint64_t
7110 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
7111 {
7112         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7113         uint64_t systime_cycles;
7114
7115         switch (hw->mac.type) {
7116         case ixgbe_mac_X550:
7117         case ixgbe_mac_X550EM_x:
7118         case ixgbe_mac_X550EM_a:
7119                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
7120                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7121                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7122                                 * NSEC_PER_SEC;
7123                 break;
7124         default:
7125                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
7126                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
7127                                 << 32;
7128         }
7129
7130         return systime_cycles;
7131 }
7132
7133 static uint64_t
7134 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7135 {
7136         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7137         uint64_t rx_tstamp_cycles;
7138
7139         switch (hw->mac.type) {
7140         case ixgbe_mac_X550:
7141         case ixgbe_mac_X550EM_x:
7142         case ixgbe_mac_X550EM_a:
7143                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7144                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7145                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7146                                 * NSEC_PER_SEC;
7147                 break;
7148         default:
7149                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
7150                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
7151                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
7152                                 << 32;
7153         }
7154
7155         return rx_tstamp_cycles;
7156 }
7157
7158 static uint64_t
7159 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
7160 {
7161         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7162         uint64_t tx_tstamp_cycles;
7163
7164         switch (hw->mac.type) {
7165         case ixgbe_mac_X550:
7166         case ixgbe_mac_X550EM_x:
7167         case ixgbe_mac_X550EM_a:
7168                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7169                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7170                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7171                                 * NSEC_PER_SEC;
7172                 break;
7173         default:
7174                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
7175                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
7176                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
7177                                 << 32;
7178         }
7179
7180         return tx_tstamp_cycles;
7181 }
7182
7183 static void
7184 ixgbe_start_timecounters(struct rte_eth_dev *dev)
7185 {
7186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7187         struct ixgbe_adapter *adapter = dev->data->dev_private;
7188         struct rte_eth_link link;
7189         uint32_t incval = 0;
7190         uint32_t shift = 0;
7191
7192         /* Get current link speed. */
7193         ixgbe_dev_link_update(dev, 1);
7194         rte_eth_linkstatus_get(dev, &link);
7195
7196         switch (link.link_speed) {
7197         case ETH_SPEED_NUM_100M:
7198                 incval = IXGBE_INCVAL_100;
7199                 shift = IXGBE_INCVAL_SHIFT_100;
7200                 break;
7201         case ETH_SPEED_NUM_1G:
7202                 incval = IXGBE_INCVAL_1GB;
7203                 shift = IXGBE_INCVAL_SHIFT_1GB;
7204                 break;
7205         case ETH_SPEED_NUM_10G:
7206         default:
7207                 incval = IXGBE_INCVAL_10GB;
7208                 shift = IXGBE_INCVAL_SHIFT_10GB;
7209                 break;
7210         }
7211
7212         switch (hw->mac.type) {
7213         case ixgbe_mac_X550:
7214         case ixgbe_mac_X550EM_x:
7215         case ixgbe_mac_X550EM_a:
7216                 /* Independent of link speed. */
7217                 incval = 1;
7218                 /* Cycles read will be interpreted as ns. */
7219                 shift = 0;
7220                 /* Fall-through */
7221         case ixgbe_mac_X540:
7222                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
7223                 break;
7224         case ixgbe_mac_82599EB:
7225                 incval >>= IXGBE_INCVAL_SHIFT_82599;
7226                 shift -= IXGBE_INCVAL_SHIFT_82599;
7227                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
7228                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
7229                 break;
7230         default:
7231                 /* Not supported. */
7232                 return;
7233         }
7234
7235         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
7236         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7237         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
7238
7239         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7240         adapter->systime_tc.cc_shift = shift;
7241         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
7242
7243         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7244         adapter->rx_tstamp_tc.cc_shift = shift;
7245         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7246
7247         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
7248         adapter->tx_tstamp_tc.cc_shift = shift;
7249         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
7250 }
7251
7252 static int
7253 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7254 {
7255         struct ixgbe_adapter *adapter = dev->data->dev_private;
7256
7257         adapter->systime_tc.nsec += delta;
7258         adapter->rx_tstamp_tc.nsec += delta;
7259         adapter->tx_tstamp_tc.nsec += delta;
7260
7261         return 0;
7262 }
7263
7264 static int
7265 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7266 {
7267         uint64_t ns;
7268         struct ixgbe_adapter *adapter = dev->data->dev_private;
7269
7270         ns = rte_timespec_to_ns(ts);
7271         /* Set the timecounters to a new value. */
7272         adapter->systime_tc.nsec = ns;
7273         adapter->rx_tstamp_tc.nsec = ns;
7274         adapter->tx_tstamp_tc.nsec = ns;
7275
7276         return 0;
7277 }
7278
7279 static int
7280 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7281 {
7282         uint64_t ns, systime_cycles;
7283         struct ixgbe_adapter *adapter = dev->data->dev_private;
7284
7285         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7286         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7287         *ts = rte_ns_to_timespec(ns);
7288
7289         return 0;
7290 }
7291
7292 static int
7293 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7294 {
7295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7296         uint32_t tsync_ctl;
7297         uint32_t tsauxc;
7298
7299         /* Stop the timesync system time. */
7300         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7301         /* Reset the timesync system time value. */
7302         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7303         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7304
7305         /* Enable system time for platforms where it isn't on by default. */
7306         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7307         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7308         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7309
7310         ixgbe_start_timecounters(dev);
7311
7312         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7313         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7314                         (RTE_ETHER_TYPE_1588 |
7315                          IXGBE_ETQF_FILTER_EN |
7316                          IXGBE_ETQF_1588));
7317
7318         /* Enable timestamping of received PTP packets. */
7319         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7320         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7321         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7322
7323         /* Enable timestamping of transmitted PTP packets. */
7324         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7325         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7326         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7327
7328         IXGBE_WRITE_FLUSH(hw);
7329
7330         return 0;
7331 }
7332
7333 static int
7334 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7335 {
7336         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7337         uint32_t tsync_ctl;
7338
7339         /* Disable timestamping of transmitted PTP packets. */
7340         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7341         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7342         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7343
7344         /* Disable timestamping of received PTP packets. */
7345         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7346         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7347         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7348
7349         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7350         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7351
7352         /* Stop incrementating the System Time registers. */
7353         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7354
7355         return 0;
7356 }
7357
7358 static int
7359 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7360                                  struct timespec *timestamp,
7361                                  uint32_t flags __rte_unused)
7362 {
7363         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7364         struct ixgbe_adapter *adapter = dev->data->dev_private;
7365         uint32_t tsync_rxctl;
7366         uint64_t rx_tstamp_cycles;
7367         uint64_t ns;
7368
7369         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7370         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7371                 return -EINVAL;
7372
7373         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7374         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7375         *timestamp = rte_ns_to_timespec(ns);
7376
7377         return  0;
7378 }
7379
7380 static int
7381 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7382                                  struct timespec *timestamp)
7383 {
7384         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7385         struct ixgbe_adapter *adapter = dev->data->dev_private;
7386         uint32_t tsync_txctl;
7387         uint64_t tx_tstamp_cycles;
7388         uint64_t ns;
7389
7390         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7391         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7392                 return -EINVAL;
7393
7394         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7395         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7396         *timestamp = rte_ns_to_timespec(ns);
7397
7398         return 0;
7399 }
7400
7401 static int
7402 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7403 {
7404         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7405         int count = 0;
7406         int g_ind = 0;
7407         const struct reg_info *reg_group;
7408         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7409                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7410
7411         while ((reg_group = reg_set[g_ind++]))
7412                 count += ixgbe_regs_group_count(reg_group);
7413
7414         return count;
7415 }
7416
7417 static int
7418 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7419 {
7420         int count = 0;
7421         int g_ind = 0;
7422         const struct reg_info *reg_group;
7423
7424         while ((reg_group = ixgbevf_regs[g_ind++]))
7425                 count += ixgbe_regs_group_count(reg_group);
7426
7427         return count;
7428 }
7429
7430 static int
7431 ixgbe_get_regs(struct rte_eth_dev *dev,
7432               struct rte_dev_reg_info *regs)
7433 {
7434         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7435         uint32_t *data = regs->data;
7436         int g_ind = 0;
7437         int count = 0;
7438         const struct reg_info *reg_group;
7439         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7440                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7441
7442         if (data == NULL) {
7443                 regs->length = ixgbe_get_reg_length(dev);
7444                 regs->width = sizeof(uint32_t);
7445                 return 0;
7446         }
7447
7448         /* Support only full register dump */
7449         if ((regs->length == 0) ||
7450             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7451                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7452                         hw->device_id;
7453                 while ((reg_group = reg_set[g_ind++]))
7454                         count += ixgbe_read_regs_group(dev, &data[count],
7455                                 reg_group);
7456                 return 0;
7457         }
7458
7459         return -ENOTSUP;
7460 }
7461
7462 static int
7463 ixgbevf_get_regs(struct rte_eth_dev *dev,
7464                 struct rte_dev_reg_info *regs)
7465 {
7466         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7467         uint32_t *data = regs->data;
7468         int g_ind = 0;
7469         int count = 0;
7470         const struct reg_info *reg_group;
7471
7472         if (data == NULL) {
7473                 regs->length = ixgbevf_get_reg_length(dev);
7474                 regs->width = sizeof(uint32_t);
7475                 return 0;
7476         }
7477
7478         /* Support only full register dump */
7479         if ((regs->length == 0) ||
7480             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7481                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7482                         hw->device_id;
7483                 while ((reg_group = ixgbevf_regs[g_ind++]))
7484                         count += ixgbe_read_regs_group(dev, &data[count],
7485                                                       reg_group);
7486                 return 0;
7487         }
7488
7489         return -ENOTSUP;
7490 }
7491
7492 static int
7493 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7494 {
7495         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7496
7497         /* Return unit is byte count */
7498         return hw->eeprom.word_size * 2;
7499 }
7500
7501 static int
7502 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7503                 struct rte_dev_eeprom_info *in_eeprom)
7504 {
7505         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7506         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7507         uint16_t *data = in_eeprom->data;
7508         int first, length;
7509
7510         first = in_eeprom->offset >> 1;
7511         length = in_eeprom->length >> 1;
7512         if ((first > hw->eeprom.word_size) ||
7513             ((first + length) > hw->eeprom.word_size))
7514                 return -EINVAL;
7515
7516         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7517
7518         return eeprom->ops.read_buffer(hw, first, length, data);
7519 }
7520
7521 static int
7522 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7523                 struct rte_dev_eeprom_info *in_eeprom)
7524 {
7525         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7526         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7527         uint16_t *data = in_eeprom->data;
7528         int first, length;
7529
7530         first = in_eeprom->offset >> 1;
7531         length = in_eeprom->length >> 1;
7532         if ((first > hw->eeprom.word_size) ||
7533             ((first + length) > hw->eeprom.word_size))
7534                 return -EINVAL;
7535
7536         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7537
7538         return eeprom->ops.write_buffer(hw,  first, length, data);
7539 }
7540
7541 static int
7542 ixgbe_get_module_info(struct rte_eth_dev *dev,
7543                       struct rte_eth_dev_module_info *modinfo)
7544 {
7545         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546         uint32_t status;
7547         uint8_t sff8472_rev, addr_mode;
7548         bool page_swap = false;
7549
7550         /* Check whether we support SFF-8472 or not */
7551         status = hw->phy.ops.read_i2c_eeprom(hw,
7552                                              IXGBE_SFF_SFF_8472_COMP,
7553                                              &sff8472_rev);
7554         if (status != 0)
7555                 return -EIO;
7556
7557         /* addressing mode is not supported */
7558         status = hw->phy.ops.read_i2c_eeprom(hw,
7559                                              IXGBE_SFF_SFF_8472_SWAP,
7560                                              &addr_mode);
7561         if (status != 0)
7562                 return -EIO;
7563
7564         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7565                 PMD_DRV_LOG(ERR,
7566                             "Address change required to access page 0xA2, "
7567                             "but not supported. Please report the module "
7568                             "type to the driver maintainers.");
7569                 page_swap = true;
7570         }
7571
7572         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7573                 /* We have a SFP, but it does not support SFF-8472 */
7574                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7575                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7576         } else {
7577                 /* We have a SFP which supports a revision of SFF-8472. */
7578                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7579                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7580         }
7581
7582         return 0;
7583 }
7584
7585 static int
7586 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7587                         struct rte_dev_eeprom_info *info)
7588 {
7589         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7590         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7591         uint8_t databyte = 0xFF;
7592         uint8_t *data = info->data;
7593         uint32_t i = 0;
7594
7595         if (info->length == 0)
7596                 return -EINVAL;
7597
7598         for (i = info->offset; i < info->offset + info->length; i++) {
7599                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7600                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7601                 else
7602                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7603
7604                 if (status != 0)
7605                         return -EIO;
7606
7607                 data[i - info->offset] = databyte;
7608         }
7609
7610         return 0;
7611 }
7612
7613 uint16_t
7614 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7615         switch (mac_type) {
7616         case ixgbe_mac_X550:
7617         case ixgbe_mac_X550EM_x:
7618         case ixgbe_mac_X550EM_a:
7619                 return ETH_RSS_RETA_SIZE_512;
7620         case ixgbe_mac_X550_vf:
7621         case ixgbe_mac_X550EM_x_vf:
7622         case ixgbe_mac_X550EM_a_vf:
7623                 return ETH_RSS_RETA_SIZE_64;
7624         case ixgbe_mac_X540_vf:
7625         case ixgbe_mac_82599_vf:
7626                 return 0;
7627         default:
7628                 return ETH_RSS_RETA_SIZE_128;
7629         }
7630 }
7631
7632 uint32_t
7633 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7634         switch (mac_type) {
7635         case ixgbe_mac_X550:
7636         case ixgbe_mac_X550EM_x:
7637         case ixgbe_mac_X550EM_a:
7638                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7639                         return IXGBE_RETA(reta_idx >> 2);
7640                 else
7641                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7642         case ixgbe_mac_X550_vf:
7643         case ixgbe_mac_X550EM_x_vf:
7644         case ixgbe_mac_X550EM_a_vf:
7645                 return IXGBE_VFRETA(reta_idx >> 2);
7646         default:
7647                 return IXGBE_RETA(reta_idx >> 2);
7648         }
7649 }
7650
7651 uint32_t
7652 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7653         switch (mac_type) {
7654         case ixgbe_mac_X550_vf:
7655         case ixgbe_mac_X550EM_x_vf:
7656         case ixgbe_mac_X550EM_a_vf:
7657                 return IXGBE_VFMRQC;
7658         default:
7659                 return IXGBE_MRQC;
7660         }
7661 }
7662
7663 uint32_t
7664 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7665         switch (mac_type) {
7666         case ixgbe_mac_X550_vf:
7667         case ixgbe_mac_X550EM_x_vf:
7668         case ixgbe_mac_X550EM_a_vf:
7669                 return IXGBE_VFRSSRK(i);
7670         default:
7671                 return IXGBE_RSSRK(i);
7672         }
7673 }
7674
7675 bool
7676 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7677         switch (mac_type) {
7678         case ixgbe_mac_82599_vf:
7679         case ixgbe_mac_X540_vf:
7680                 return 0;
7681         default:
7682                 return 1;
7683         }
7684 }
7685
7686 static int
7687 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7688                         struct rte_eth_dcb_info *dcb_info)
7689 {
7690         struct ixgbe_dcb_config *dcb_config =
7691                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7692         struct ixgbe_dcb_tc_config *tc;
7693         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7694         uint8_t nb_tcs;
7695         uint8_t i, j;
7696
7697         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7698                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7699         else
7700                 dcb_info->nb_tcs = 1;
7701
7702         tc_queue = &dcb_info->tc_queue;
7703         nb_tcs = dcb_info->nb_tcs;
7704
7705         if (dcb_config->vt_mode) { /* vt is enabled*/
7706                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7707                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7708                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7709                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7710                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7711                         for (j = 0; j < nb_tcs; j++) {
7712                                 tc_queue->tc_rxq[0][j].base = j;
7713                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7714                                 tc_queue->tc_txq[0][j].base = j;
7715                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7716                         }
7717                 } else {
7718                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7719                                 for (j = 0; j < nb_tcs; j++) {
7720                                         tc_queue->tc_rxq[i][j].base =
7721                                                 i * nb_tcs + j;
7722                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7723                                         tc_queue->tc_txq[i][j].base =
7724                                                 i * nb_tcs + j;
7725                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7726                                 }
7727                         }
7728                 }
7729         } else { /* vt is disabled*/
7730                 struct rte_eth_dcb_rx_conf *rx_conf =
7731                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7732                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7733                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7734                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7735                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7736                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7737                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7738                         }
7739                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7740                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7741                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7742                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7743                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7744                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7745                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7746                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7747                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7748                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7749                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7750                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7751                         }
7752                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7753                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7754                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7755                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7756                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7757                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7758                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7759                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7760                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7761                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7762                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7763                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7764                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7765                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7766                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7767                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7768                 }
7769         }
7770         for (i = 0; i < dcb_info->nb_tcs; i++) {
7771                 tc = &dcb_config->tc_config[i];
7772                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7773         }
7774         return 0;
7775 }
7776
7777 /* Update e-tag ether type */
7778 static int
7779 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7780                             uint16_t ether_type)
7781 {
7782         uint32_t etag_etype;
7783
7784         if (hw->mac.type != ixgbe_mac_X550 &&
7785             hw->mac.type != ixgbe_mac_X550EM_x &&
7786             hw->mac.type != ixgbe_mac_X550EM_a) {
7787                 return -ENOTSUP;
7788         }
7789
7790         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7791         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7792         etag_etype |= ether_type;
7793         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7794         IXGBE_WRITE_FLUSH(hw);
7795
7796         return 0;
7797 }
7798
7799 /* Config l2 tunnel ether type */
7800 static int
7801 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7802                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7803 {
7804         int ret = 0;
7805         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7806         struct ixgbe_l2_tn_info *l2_tn_info =
7807                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7808
7809         if (l2_tunnel == NULL)
7810                 return -EINVAL;
7811
7812         switch (l2_tunnel->l2_tunnel_type) {
7813         case RTE_L2_TUNNEL_TYPE_E_TAG:
7814                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7815                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7816                 break;
7817         default:
7818                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7819                 ret = -EINVAL;
7820                 break;
7821         }
7822
7823         return ret;
7824 }
7825
7826 /* Enable e-tag tunnel */
7827 static int
7828 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7829 {
7830         uint32_t etag_etype;
7831
7832         if (hw->mac.type != ixgbe_mac_X550 &&
7833             hw->mac.type != ixgbe_mac_X550EM_x &&
7834             hw->mac.type != ixgbe_mac_X550EM_a) {
7835                 return -ENOTSUP;
7836         }
7837
7838         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7839         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7840         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7841         IXGBE_WRITE_FLUSH(hw);
7842
7843         return 0;
7844 }
7845
7846 /* Enable l2 tunnel */
7847 static int
7848 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7849                            enum rte_eth_tunnel_type l2_tunnel_type)
7850 {
7851         int ret = 0;
7852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7853         struct ixgbe_l2_tn_info *l2_tn_info =
7854                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7855
7856         switch (l2_tunnel_type) {
7857         case RTE_L2_TUNNEL_TYPE_E_TAG:
7858                 l2_tn_info->e_tag_en = TRUE;
7859                 ret = ixgbe_e_tag_enable(hw);
7860                 break;
7861         default:
7862                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7863                 ret = -EINVAL;
7864                 break;
7865         }
7866
7867         return ret;
7868 }
7869
7870 /* Disable e-tag tunnel */
7871 static int
7872 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7873 {
7874         uint32_t etag_etype;
7875
7876         if (hw->mac.type != ixgbe_mac_X550 &&
7877             hw->mac.type != ixgbe_mac_X550EM_x &&
7878             hw->mac.type != ixgbe_mac_X550EM_a) {
7879                 return -ENOTSUP;
7880         }
7881
7882         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7883         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7884         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7885         IXGBE_WRITE_FLUSH(hw);
7886
7887         return 0;
7888 }
7889
7890 /* Disable l2 tunnel */
7891 static int
7892 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7893                             enum rte_eth_tunnel_type l2_tunnel_type)
7894 {
7895         int ret = 0;
7896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7897         struct ixgbe_l2_tn_info *l2_tn_info =
7898                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7899
7900         switch (l2_tunnel_type) {
7901         case RTE_L2_TUNNEL_TYPE_E_TAG:
7902                 l2_tn_info->e_tag_en = FALSE;
7903                 ret = ixgbe_e_tag_disable(hw);
7904                 break;
7905         default:
7906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7907                 ret = -EINVAL;
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 static int
7915 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7916                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7917 {
7918         int ret = 0;
7919         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7920         uint32_t i, rar_entries;
7921         uint32_t rar_low, rar_high;
7922
7923         if (hw->mac.type != ixgbe_mac_X550 &&
7924             hw->mac.type != ixgbe_mac_X550EM_x &&
7925             hw->mac.type != ixgbe_mac_X550EM_a) {
7926                 return -ENOTSUP;
7927         }
7928
7929         rar_entries = ixgbe_get_num_rx_addrs(hw);
7930
7931         for (i = 1; i < rar_entries; i++) {
7932                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7933                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7934                 if ((rar_high & IXGBE_RAH_AV) &&
7935                     (rar_high & IXGBE_RAH_ADTYPE) &&
7936                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7937                      l2_tunnel->tunnel_id)) {
7938                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7939                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7940
7941                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7942
7943                         return ret;
7944                 }
7945         }
7946
7947         return ret;
7948 }
7949
7950 static int
7951 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7952                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7953 {
7954         int ret = 0;
7955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7956         uint32_t i, rar_entries;
7957         uint32_t rar_low, rar_high;
7958
7959         if (hw->mac.type != ixgbe_mac_X550 &&
7960             hw->mac.type != ixgbe_mac_X550EM_x &&
7961             hw->mac.type != ixgbe_mac_X550EM_a) {
7962                 return -ENOTSUP;
7963         }
7964
7965         /* One entry for one tunnel. Try to remove potential existing entry. */
7966         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7967
7968         rar_entries = ixgbe_get_num_rx_addrs(hw);
7969
7970         for (i = 1; i < rar_entries; i++) {
7971                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7972                 if (rar_high & IXGBE_RAH_AV) {
7973                         continue;
7974                 } else {
7975                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7976                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7977                         rar_low = l2_tunnel->tunnel_id;
7978
7979                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7980                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7981
7982                         return ret;
7983                 }
7984         }
7985
7986         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7987                      " Please remove a rule before adding a new one.");
7988         return -EINVAL;
7989 }
7990
7991 static inline struct ixgbe_l2_tn_filter *
7992 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7993                           struct ixgbe_l2_tn_key *key)
7994 {
7995         int ret;
7996
7997         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7998         if (ret < 0)
7999                 return NULL;
8000
8001         return l2_tn_info->hash_map[ret];
8002 }
8003
8004 static inline int
8005 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8006                           struct ixgbe_l2_tn_filter *l2_tn_filter)
8007 {
8008         int ret;
8009
8010         ret = rte_hash_add_key(l2_tn_info->hash_handle,
8011                                &l2_tn_filter->key);
8012
8013         if (ret < 0) {
8014                 PMD_DRV_LOG(ERR,
8015                             "Failed to insert L2 tunnel filter"
8016                             " to hash table %d!",
8017                             ret);
8018                 return ret;
8019         }
8020
8021         l2_tn_info->hash_map[ret] = l2_tn_filter;
8022
8023         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8024
8025         return 0;
8026 }
8027
8028 static inline int
8029 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
8030                           struct ixgbe_l2_tn_key *key)
8031 {
8032         int ret;
8033         struct ixgbe_l2_tn_filter *l2_tn_filter;
8034
8035         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
8036
8037         if (ret < 0) {
8038                 PMD_DRV_LOG(ERR,
8039                             "No such L2 tunnel filter to delete %d!",
8040                             ret);
8041                 return ret;
8042         }
8043
8044         l2_tn_filter = l2_tn_info->hash_map[ret];
8045         l2_tn_info->hash_map[ret] = NULL;
8046
8047         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
8048         rte_free(l2_tn_filter);
8049
8050         return 0;
8051 }
8052
8053 /* Add l2 tunnel filter */
8054 int
8055 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
8056                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
8057                                bool restore)
8058 {
8059         int ret;
8060         struct ixgbe_l2_tn_info *l2_tn_info =
8061                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8062         struct ixgbe_l2_tn_key key;
8063         struct ixgbe_l2_tn_filter *node;
8064
8065         if (!restore) {
8066                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8067                 key.tn_id = l2_tunnel->tunnel_id;
8068
8069                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
8070
8071                 if (node) {
8072                         PMD_DRV_LOG(ERR,
8073                                     "The L2 tunnel filter already exists!");
8074                         return -EINVAL;
8075                 }
8076
8077                 node = rte_zmalloc("ixgbe_l2_tn",
8078                                    sizeof(struct ixgbe_l2_tn_filter),
8079                                    0);
8080                 if (!node)
8081                         return -ENOMEM;
8082
8083                 rte_memcpy(&node->key,
8084                                  &key,
8085                                  sizeof(struct ixgbe_l2_tn_key));
8086                 node->pool = l2_tunnel->pool;
8087                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
8088                 if (ret < 0) {
8089                         rte_free(node);
8090                         return ret;
8091                 }
8092         }
8093
8094         switch (l2_tunnel->l2_tunnel_type) {
8095         case RTE_L2_TUNNEL_TYPE_E_TAG:
8096                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
8097                 break;
8098         default:
8099                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8100                 ret = -EINVAL;
8101                 break;
8102         }
8103
8104         if ((!restore) && (ret < 0))
8105                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8106
8107         return ret;
8108 }
8109
8110 /* Delete l2 tunnel filter */
8111 int
8112 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
8113                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
8114 {
8115         int ret;
8116         struct ixgbe_l2_tn_info *l2_tn_info =
8117                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8118         struct ixgbe_l2_tn_key key;
8119
8120         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
8121         key.tn_id = l2_tunnel->tunnel_id;
8122         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
8123         if (ret < 0)
8124                 return ret;
8125
8126         switch (l2_tunnel->l2_tunnel_type) {
8127         case RTE_L2_TUNNEL_TYPE_E_TAG:
8128                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
8129                 break;
8130         default:
8131                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8132                 ret = -EINVAL;
8133                 break;
8134         }
8135
8136         return ret;
8137 }
8138
8139 /**
8140  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
8141  * @dev: pointer to rte_eth_dev structure
8142  * @filter_op:operation will be taken.
8143  * @arg: a pointer to specific structure corresponding to the filter_op
8144  */
8145 static int
8146 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
8147                                   enum rte_filter_op filter_op,
8148                                   void *arg)
8149 {
8150         int ret;
8151
8152         if (filter_op == RTE_ETH_FILTER_NOP)
8153                 return 0;
8154
8155         if (arg == NULL) {
8156                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
8157                             filter_op);
8158                 return -EINVAL;
8159         }
8160
8161         switch (filter_op) {
8162         case RTE_ETH_FILTER_ADD:
8163                 ret = ixgbe_dev_l2_tunnel_filter_add
8164                         (dev,
8165                          (struct rte_eth_l2_tunnel_conf *)arg,
8166                          FALSE);
8167                 break;
8168         case RTE_ETH_FILTER_DELETE:
8169                 ret = ixgbe_dev_l2_tunnel_filter_del
8170                         (dev,
8171                          (struct rte_eth_l2_tunnel_conf *)arg);
8172                 break;
8173         default:
8174                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
8175                 ret = -EINVAL;
8176                 break;
8177         }
8178         return ret;
8179 }
8180
8181 static int
8182 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
8183 {
8184         int ret = 0;
8185         uint32_t ctrl;
8186         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8187
8188         if (hw->mac.type != ixgbe_mac_X550 &&
8189             hw->mac.type != ixgbe_mac_X550EM_x &&
8190             hw->mac.type != ixgbe_mac_X550EM_a) {
8191                 return -ENOTSUP;
8192         }
8193
8194         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
8195         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
8196         if (en)
8197                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
8198         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
8199
8200         return ret;
8201 }
8202
8203 /* Enable l2 tunnel forwarding */
8204 static int
8205 ixgbe_dev_l2_tunnel_forwarding_enable
8206         (struct rte_eth_dev *dev,
8207          enum rte_eth_tunnel_type l2_tunnel_type)
8208 {
8209         struct ixgbe_l2_tn_info *l2_tn_info =
8210                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8211         int ret = 0;
8212
8213         switch (l2_tunnel_type) {
8214         case RTE_L2_TUNNEL_TYPE_E_TAG:
8215                 l2_tn_info->e_tag_fwd_en = TRUE;
8216                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
8217                 break;
8218         default:
8219                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8220                 ret = -EINVAL;
8221                 break;
8222         }
8223
8224         return ret;
8225 }
8226
8227 /* Disable l2 tunnel forwarding */
8228 static int
8229 ixgbe_dev_l2_tunnel_forwarding_disable
8230         (struct rte_eth_dev *dev,
8231          enum rte_eth_tunnel_type l2_tunnel_type)
8232 {
8233         struct ixgbe_l2_tn_info *l2_tn_info =
8234                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8235         int ret = 0;
8236
8237         switch (l2_tunnel_type) {
8238         case RTE_L2_TUNNEL_TYPE_E_TAG:
8239                 l2_tn_info->e_tag_fwd_en = FALSE;
8240                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
8241                 break;
8242         default:
8243                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8244                 ret = -EINVAL;
8245                 break;
8246         }
8247
8248         return ret;
8249 }
8250
8251 static int
8252 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
8253                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
8254                              bool en)
8255 {
8256         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
8257         int ret = 0;
8258         uint32_t vmtir, vmvir;
8259         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260
8261         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
8262                 PMD_DRV_LOG(ERR,
8263                             "VF id %u should be less than %u",
8264                             l2_tunnel->vf_id,
8265                             pci_dev->max_vfs);
8266                 return -EINVAL;
8267         }
8268
8269         if (hw->mac.type != ixgbe_mac_X550 &&
8270             hw->mac.type != ixgbe_mac_X550EM_x &&
8271             hw->mac.type != ixgbe_mac_X550EM_a) {
8272                 return -ENOTSUP;
8273         }
8274
8275         if (en)
8276                 vmtir = l2_tunnel->tunnel_id;
8277         else
8278                 vmtir = 0;
8279
8280         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
8281
8282         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
8283         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
8284         if (en)
8285                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
8286         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
8287
8288         return ret;
8289 }
8290
8291 /* Enable l2 tunnel tag insertion */
8292 static int
8293 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
8294                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
8295 {
8296         int ret = 0;
8297
8298         switch (l2_tunnel->l2_tunnel_type) {
8299         case RTE_L2_TUNNEL_TYPE_E_TAG:
8300                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
8301                 break;
8302         default:
8303                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8304                 ret = -EINVAL;
8305                 break;
8306         }
8307
8308         return ret;
8309 }
8310
8311 /* Disable l2 tunnel tag insertion */
8312 static int
8313 ixgbe_dev_l2_tunnel_insertion_disable
8314         (struct rte_eth_dev *dev,
8315          struct rte_eth_l2_tunnel_conf *l2_tunnel)
8316 {
8317         int ret = 0;
8318
8319         switch (l2_tunnel->l2_tunnel_type) {
8320         case RTE_L2_TUNNEL_TYPE_E_TAG:
8321                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
8322                 break;
8323         default:
8324                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8325                 ret = -EINVAL;
8326                 break;
8327         }
8328
8329         return ret;
8330 }
8331
8332 static int
8333 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8334                              bool en)
8335 {
8336         int ret = 0;
8337         uint32_t qde;
8338         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8339
8340         if (hw->mac.type != ixgbe_mac_X550 &&
8341             hw->mac.type != ixgbe_mac_X550EM_x &&
8342             hw->mac.type != ixgbe_mac_X550EM_a) {
8343                 return -ENOTSUP;
8344         }
8345
8346         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8347         if (en)
8348                 qde |= IXGBE_QDE_STRIP_TAG;
8349         else
8350                 qde &= ~IXGBE_QDE_STRIP_TAG;
8351         qde &= ~IXGBE_QDE_READ;
8352         qde |= IXGBE_QDE_WRITE;
8353         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8354
8355         return ret;
8356 }
8357
8358 /* Enable l2 tunnel tag stripping */
8359 static int
8360 ixgbe_dev_l2_tunnel_stripping_enable
8361         (struct rte_eth_dev *dev,
8362          enum rte_eth_tunnel_type l2_tunnel_type)
8363 {
8364         int ret = 0;
8365
8366         switch (l2_tunnel_type) {
8367         case RTE_L2_TUNNEL_TYPE_E_TAG:
8368                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8369                 break;
8370         default:
8371                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8372                 ret = -EINVAL;
8373                 break;
8374         }
8375
8376         return ret;
8377 }
8378
8379 /* Disable l2 tunnel tag stripping */
8380 static int
8381 ixgbe_dev_l2_tunnel_stripping_disable
8382         (struct rte_eth_dev *dev,
8383          enum rte_eth_tunnel_type l2_tunnel_type)
8384 {
8385         int ret = 0;
8386
8387         switch (l2_tunnel_type) {
8388         case RTE_L2_TUNNEL_TYPE_E_TAG:
8389                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8390                 break;
8391         default:
8392                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8393                 ret = -EINVAL;
8394                 break;
8395         }
8396
8397         return ret;
8398 }
8399
8400 /* Enable/disable l2 tunnel offload functions */
8401 static int
8402 ixgbe_dev_l2_tunnel_offload_set
8403         (struct rte_eth_dev *dev,
8404          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8405          uint32_t mask,
8406          uint8_t en)
8407 {
8408         int ret = 0;
8409
8410         if (l2_tunnel == NULL)
8411                 return -EINVAL;
8412
8413         ret = -EINVAL;
8414         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8415                 if (en)
8416                         ret = ixgbe_dev_l2_tunnel_enable(
8417                                 dev,
8418                                 l2_tunnel->l2_tunnel_type);
8419                 else
8420                         ret = ixgbe_dev_l2_tunnel_disable(
8421                                 dev,
8422                                 l2_tunnel->l2_tunnel_type);
8423         }
8424
8425         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8426                 if (en)
8427                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8428                                 dev,
8429                                 l2_tunnel);
8430                 else
8431                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8432                                 dev,
8433                                 l2_tunnel);
8434         }
8435
8436         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8437                 if (en)
8438                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8439                                 dev,
8440                                 l2_tunnel->l2_tunnel_type);
8441                 else
8442                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8443                                 dev,
8444                                 l2_tunnel->l2_tunnel_type);
8445         }
8446
8447         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8448                 if (en)
8449                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8450                                 dev,
8451                                 l2_tunnel->l2_tunnel_type);
8452                 else
8453                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8454                                 dev,
8455                                 l2_tunnel->l2_tunnel_type);
8456         }
8457
8458         return ret;
8459 }
8460
8461 static int
8462 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8463                         uint16_t port)
8464 {
8465         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8466         IXGBE_WRITE_FLUSH(hw);
8467
8468         return 0;
8469 }
8470
8471 /* There's only one register for VxLAN UDP port.
8472  * So, we cannot add several ports. Will update it.
8473  */
8474 static int
8475 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8476                      uint16_t port)
8477 {
8478         if (port == 0) {
8479                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8480                 return -EINVAL;
8481         }
8482
8483         return ixgbe_update_vxlan_port(hw, port);
8484 }
8485
8486 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8487  * UDP port, it must have a value.
8488  * So, will reset it to the original value 0.
8489  */
8490 static int
8491 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8492                      uint16_t port)
8493 {
8494         uint16_t cur_port;
8495
8496         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8497
8498         if (cur_port != port) {
8499                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8500                 return -EINVAL;
8501         }
8502
8503         return ixgbe_update_vxlan_port(hw, 0);
8504 }
8505
8506 /* Add UDP tunneling port */
8507 static int
8508 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8509                               struct rte_eth_udp_tunnel *udp_tunnel)
8510 {
8511         int ret = 0;
8512         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8513
8514         if (hw->mac.type != ixgbe_mac_X550 &&
8515             hw->mac.type != ixgbe_mac_X550EM_x &&
8516             hw->mac.type != ixgbe_mac_X550EM_a) {
8517                 return -ENOTSUP;
8518         }
8519
8520         if (udp_tunnel == NULL)
8521                 return -EINVAL;
8522
8523         switch (udp_tunnel->prot_type) {
8524         case RTE_TUNNEL_TYPE_VXLAN:
8525                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8526                 break;
8527
8528         case RTE_TUNNEL_TYPE_GENEVE:
8529         case RTE_TUNNEL_TYPE_TEREDO:
8530                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8531                 ret = -EINVAL;
8532                 break;
8533
8534         default:
8535                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8536                 ret = -EINVAL;
8537                 break;
8538         }
8539
8540         return ret;
8541 }
8542
8543 /* Remove UDP tunneling port */
8544 static int
8545 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8546                               struct rte_eth_udp_tunnel *udp_tunnel)
8547 {
8548         int ret = 0;
8549         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8550
8551         if (hw->mac.type != ixgbe_mac_X550 &&
8552             hw->mac.type != ixgbe_mac_X550EM_x &&
8553             hw->mac.type != ixgbe_mac_X550EM_a) {
8554                 return -ENOTSUP;
8555         }
8556
8557         if (udp_tunnel == NULL)
8558                 return -EINVAL;
8559
8560         switch (udp_tunnel->prot_type) {
8561         case RTE_TUNNEL_TYPE_VXLAN:
8562                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8563                 break;
8564         case RTE_TUNNEL_TYPE_GENEVE:
8565         case RTE_TUNNEL_TYPE_TEREDO:
8566                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8567                 ret = -EINVAL;
8568                 break;
8569         default:
8570                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8571                 ret = -EINVAL;
8572                 break;
8573         }
8574
8575         return ret;
8576 }
8577
8578 static int
8579 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8580 {
8581         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8582         int ret;
8583
8584         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8585         case IXGBE_SUCCESS:
8586                 ret = 0;
8587                 break;
8588         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8589                 ret = -ENOTSUP;
8590                 break;
8591         default:
8592                 ret = -EAGAIN;
8593                 break;
8594         }
8595
8596         return ret;
8597 }
8598
8599 static int
8600 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8601 {
8602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8603         int ret;
8604
8605         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8606         case IXGBE_SUCCESS:
8607                 ret = 0;
8608                 break;
8609         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8610                 ret = -ENOTSUP;
8611                 break;
8612         default:
8613                 ret = -EAGAIN;
8614                 break;
8615         }
8616
8617         return ret;
8618 }
8619
8620 static int
8621 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8622 {
8623         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8624         int ret;
8625         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8626
8627         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8628         case IXGBE_SUCCESS:
8629                 ret = 0;
8630                 break;
8631         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8632                 ret = -ENOTSUP;
8633                 break;
8634         default:
8635                 ret = -EAGAIN;
8636                 break;
8637         }
8638
8639         return ret;
8640 }
8641
8642 static int
8643 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8644 {
8645         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8646         int ret;
8647
8648         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8649         case IXGBE_SUCCESS:
8650                 ret = 0;
8651                 break;
8652         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8653                 ret = -ENOTSUP;
8654                 break;
8655         default:
8656                 ret = -EAGAIN;
8657                 break;
8658         }
8659
8660         return ret;
8661 }
8662
8663 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8664 {
8665         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8666         u32 in_msg = 0;
8667
8668         /* peek the message first */
8669         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8670
8671         /* PF reset VF event */
8672         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8673                 /* dummy mbx read to ack pf */
8674                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8675                         return;
8676                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8677                                               NULL);
8678         }
8679 }
8680
8681 static int
8682 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8683 {
8684         uint32_t eicr;
8685         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8686         struct ixgbe_interrupt *intr =
8687                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8688         ixgbevf_intr_disable(dev);
8689
8690         /* read-on-clear nic registers here */
8691         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8692         intr->flags = 0;
8693
8694         /* only one misc vector supported - mailbox */
8695         eicr &= IXGBE_VTEICR_MASK;
8696         if (eicr == IXGBE_MISC_VEC_ID)
8697                 intr->flags |= IXGBE_FLAG_MAILBOX;
8698
8699         return 0;
8700 }
8701
8702 static int
8703 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8704 {
8705         struct ixgbe_interrupt *intr =
8706                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8707
8708         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8709                 ixgbevf_mbx_process(dev);
8710                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8711         }
8712
8713         ixgbevf_intr_enable(dev);
8714
8715         return 0;
8716 }
8717
8718 static void
8719 ixgbevf_dev_interrupt_handler(void *param)
8720 {
8721         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8722
8723         ixgbevf_dev_interrupt_get_status(dev);
8724         ixgbevf_dev_interrupt_action(dev);
8725 }
8726
8727 /**
8728  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8729  *  @hw: pointer to hardware structure
8730  *
8731  *  Stops the transmit data path and waits for the HW to internally empty
8732  *  the Tx security block
8733  **/
8734 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8735 {
8736 #define IXGBE_MAX_SECTX_POLL 40
8737
8738         int i;
8739         int sectxreg;
8740
8741         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8742         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8743         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8744         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8745                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8746                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8747                         break;
8748                 /* Use interrupt-safe sleep just in case */
8749                 usec_delay(1000);
8750         }
8751
8752         /* For informational purposes only */
8753         if (i >= IXGBE_MAX_SECTX_POLL)
8754                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8755                          "path fully disabled.  Continuing with init.");
8756
8757         return IXGBE_SUCCESS;
8758 }
8759
8760 /**
8761  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8762  *  @hw: pointer to hardware structure
8763  *
8764  *  Enables the transmit data path.
8765  **/
8766 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8767 {
8768         uint32_t sectxreg;
8769
8770         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8771         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8772         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8773         IXGBE_WRITE_FLUSH(hw);
8774
8775         return IXGBE_SUCCESS;
8776 }
8777
8778 /* restore n-tuple filter */
8779 static inline void
8780 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8781 {
8782         struct ixgbe_filter_info *filter_info =
8783                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8784         struct ixgbe_5tuple_filter *node;
8785
8786         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8787                 ixgbe_inject_5tuple_filter(dev, node);
8788         }
8789 }
8790
8791 /* restore ethernet type filter */
8792 static inline void
8793 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8794 {
8795         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8796         struct ixgbe_filter_info *filter_info =
8797                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8798         int i;
8799
8800         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8801                 if (filter_info->ethertype_mask & (1 << i)) {
8802                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8803                                         filter_info->ethertype_filters[i].etqf);
8804                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8805                                         filter_info->ethertype_filters[i].etqs);
8806                         IXGBE_WRITE_FLUSH(hw);
8807                 }
8808         }
8809 }
8810
8811 /* restore SYN filter */
8812 static inline void
8813 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8814 {
8815         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8816         struct ixgbe_filter_info *filter_info =
8817                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8818         uint32_t synqf;
8819
8820         synqf = filter_info->syn_info;
8821
8822         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8823                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8824                 IXGBE_WRITE_FLUSH(hw);
8825         }
8826 }
8827
8828 /* restore L2 tunnel filter */
8829 static inline void
8830 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8831 {
8832         struct ixgbe_l2_tn_info *l2_tn_info =
8833                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8834         struct ixgbe_l2_tn_filter *node;
8835         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8836
8837         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8838                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8839                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8840                 l2_tn_conf.pool           = node->pool;
8841                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8842         }
8843 }
8844
8845 /* restore rss filter */
8846 static inline void
8847 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8848 {
8849         struct ixgbe_filter_info *filter_info =
8850                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8851
8852         if (filter_info->rss_info.conf.queue_num)
8853                 ixgbe_config_rss_filter(dev,
8854                         &filter_info->rss_info, TRUE);
8855 }
8856
8857 static int
8858 ixgbe_filter_restore(struct rte_eth_dev *dev)
8859 {
8860         ixgbe_ntuple_filter_restore(dev);
8861         ixgbe_ethertype_filter_restore(dev);
8862         ixgbe_syn_filter_restore(dev);
8863         ixgbe_fdir_filter_restore(dev);
8864         ixgbe_l2_tn_filter_restore(dev);
8865         ixgbe_rss_filter_restore(dev);
8866
8867         return 0;
8868 }
8869
8870 static void
8871 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8872 {
8873         struct ixgbe_l2_tn_info *l2_tn_info =
8874                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8876
8877         if (l2_tn_info->e_tag_en)
8878                 (void)ixgbe_e_tag_enable(hw);
8879
8880         if (l2_tn_info->e_tag_fwd_en)
8881                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8882
8883         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8884 }
8885
8886 /* remove all the n-tuple filters */
8887 void
8888 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8889 {
8890         struct ixgbe_filter_info *filter_info =
8891                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8892         struct ixgbe_5tuple_filter *p_5tuple;
8893
8894         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8895                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8896 }
8897
8898 /* remove all the ether type filters */
8899 void
8900 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8901 {
8902         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8903         struct ixgbe_filter_info *filter_info =
8904                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8905         int i;
8906
8907         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8908                 if (filter_info->ethertype_mask & (1 << i) &&
8909                     !filter_info->ethertype_filters[i].conf) {
8910                         (void)ixgbe_ethertype_filter_remove(filter_info,
8911                                                             (uint8_t)i);
8912                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8913                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8914                         IXGBE_WRITE_FLUSH(hw);
8915                 }
8916         }
8917 }
8918
8919 /* remove the SYN filter */
8920 void
8921 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8922 {
8923         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8924         struct ixgbe_filter_info *filter_info =
8925                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8926
8927         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8928                 filter_info->syn_info = 0;
8929
8930                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8931                 IXGBE_WRITE_FLUSH(hw);
8932         }
8933 }
8934
8935 /* remove all the L2 tunnel filters */
8936 int
8937 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8938 {
8939         struct ixgbe_l2_tn_info *l2_tn_info =
8940                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8941         struct ixgbe_l2_tn_filter *l2_tn_filter;
8942         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8943         int ret = 0;
8944
8945         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8946                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8947                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8948                 l2_tn_conf.pool           = l2_tn_filter->pool;
8949                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8950                 if (ret < 0)
8951                         return ret;
8952         }
8953
8954         return 0;
8955 }
8956
8957 void
8958 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8959                                 struct ixgbe_macsec_setting *macsec_setting)
8960 {
8961         struct ixgbe_macsec_setting *macsec =
8962                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8963
8964         macsec->offload_en = macsec_setting->offload_en;
8965         macsec->encrypt_en = macsec_setting->encrypt_en;
8966         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8967 }
8968
8969 void
8970 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8971 {
8972         struct ixgbe_macsec_setting *macsec =
8973                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8974
8975         macsec->offload_en = 0;
8976         macsec->encrypt_en = 0;
8977         macsec->replayprotect_en = 0;
8978 }
8979
8980 void
8981 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8982                                 struct ixgbe_macsec_setting *macsec_setting)
8983 {
8984         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8985         uint32_t ctrl;
8986         uint8_t en = macsec_setting->encrypt_en;
8987         uint8_t rp = macsec_setting->replayprotect_en;
8988
8989         /**
8990          * Workaround:
8991          * As no ixgbe_disable_sec_rx_path equivalent is
8992          * implemented for tx in the base code, and we are
8993          * not allowed to modify the base code in DPDK, so
8994          * just call the hand-written one directly for now.
8995          * The hardware support has been checked by
8996          * ixgbe_disable_sec_rx_path().
8997          */
8998         ixgbe_disable_sec_tx_path_generic(hw);
8999
9000         /* Enable Ethernet CRC (required by MACsec offload) */
9001         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
9002         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
9003         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
9004
9005         /* Enable the TX and RX crypto engines */
9006         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9007         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
9008         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9009
9010         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9011         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
9012         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9013
9014         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
9015         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
9016         ctrl |= 0x3;
9017         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
9018
9019         /* Enable SA lookup */
9020         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9021         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9022         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
9023                      IXGBE_LSECTXCTRL_AUTH;
9024         ctrl |= IXGBE_LSECTXCTRL_AISCI;
9025         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9026         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
9027         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9028
9029         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9030         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9031         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
9032         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
9033         if (rp)
9034                 ctrl |= IXGBE_LSECRXCTRL_RP;
9035         else
9036                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
9037         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9038
9039         /* Start the data paths */
9040         ixgbe_enable_sec_rx_path(hw);
9041         /**
9042          * Workaround:
9043          * As no ixgbe_enable_sec_rx_path equivalent is
9044          * implemented for tx in the base code, and we are
9045          * not allowed to modify the base code in DPDK, so
9046          * just call the hand-written one directly for now.
9047          */
9048         ixgbe_enable_sec_tx_path_generic(hw);
9049 }
9050
9051 void
9052 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
9053 {
9054         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9055         uint32_t ctrl;
9056
9057         /**
9058          * Workaround:
9059          * As no ixgbe_disable_sec_rx_path equivalent is
9060          * implemented for tx in the base code, and we are
9061          * not allowed to modify the base code in DPDK, so
9062          * just call the hand-written one directly for now.
9063          * The hardware support has been checked by
9064          * ixgbe_disable_sec_rx_path().
9065          */
9066         ixgbe_disable_sec_tx_path_generic(hw);
9067
9068         /* Disable the TX and RX crypto engines */
9069         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
9070         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
9071         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
9072
9073         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
9074         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
9075         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
9076
9077         /* Disable SA lookup */
9078         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
9079         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
9080         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
9081         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
9082
9083         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
9084         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
9085         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
9086         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
9087
9088         /* Start the data paths */
9089         ixgbe_enable_sec_rx_path(hw);
9090         /**
9091          * Workaround:
9092          * As no ixgbe_enable_sec_rx_path equivalent is
9093          * implemented for tx in the base code, and we are
9094          * not allowed to modify the base code in DPDK, so
9095          * just call the hand-written one directly for now.
9096          */
9097         ixgbe_enable_sec_tx_path_generic(hw);
9098 }
9099
9100 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
9101 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
9102 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
9103 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
9104 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
9105 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
9106 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
9107                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
9108
9109 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
9110 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
9111
9112 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
9113 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
9114 #endif
9115 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
9116 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
9117 #endif
9118 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
9119 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
9120 #endif