drivers/net/ixgbe/ixgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12 #include <inttypes.h>
  13 #include <netinet/in.h>
  14 #include <rte_string_fns.h>
  15 #include <rte_byteorder.h>
  16 #include <rte_common.h>
  17 #include <rte_cycles.h>
  18
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_kvargs.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_dev.h>
  35 #include <rte_hash_crc.h>
  36 #ifdef RTE_LIB_SECURITY
  37 #include <rte_security_driver.h>
  38 #endif
  39
  40 #include "ixgbe_logs.h"
  41 #include "base/ixgbe_api.h"
  42 #include "base/ixgbe_vf.h"
  43 #include "base/ixgbe_common.h"
  44 #include "ixgbe_ethdev.h"
  45 #include "ixgbe_bypass.h"
  46 #include "ixgbe_rxtx.h"
  47 #include "base/ixgbe_type.h"
  48 #include "base/ixgbe_phy.h"
  49 #include "ixgbe_regs.h"
  50
  51 /*
  52  * High threshold controlling when to start sending XOFF frames. Must be at
  53  * least 8 bytes less than receive packet buffer size. This value is in units
  54  * of 1024 bytes.
  55  */
  56 #define IXGBE_FC_HI    0x80
  57
  58 /*
  59  * Low threshold controlling when to start sending XON frames. This value is
  60  * in units of 1024 bytes.
  61  */
  62 #define IXGBE_FC_LO    0x40
  63
  64 /* Timer value included in XOFF frames. */
  65 #define IXGBE_FC_PAUSE 0x680
  66
  67 /*Default value of Max Rx Queue*/
  68 #define IXGBE_MAX_RX_QUEUE_NUM 128
  69
  70 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  71 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  72 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  73
  74 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  75 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  76 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
  77
  78 /*
  79  *  Default values for RX/TX configuration
  80  */
  81 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  82 #define IXGBE_DEFAULT_RX_PTHRESH      8
  83 #define IXGBE_DEFAULT_RX_HTHRESH      8
  84 #define IXGBE_DEFAULT_RX_WTHRESH      0
  85
  86 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
  87 #define IXGBE_DEFAULT_TX_PTHRESH      32
  88 #define IXGBE_DEFAULT_TX_HTHRESH      0
  89 #define IXGBE_DEFAULT_TX_WTHRESH      0
  90 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
  91
  92 /* Bit shift and mask */
  93 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
  94 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
  95 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
  96 #define IXGBE_8_BIT_MASK   UINT8_MAX
  97
  98 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
  99
 100 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 101
 102 /* Additional timesync values. */
 103 #define NSEC_PER_SEC             1000000000L
 104 #define IXGBE_INCVAL_10GB        0x66666666
 105 #define IXGBE_INCVAL_1GB         0x40000000
 106 #define IXGBE_INCVAL_100         0x50000000
 107 #define IXGBE_INCVAL_SHIFT_10GB  28
 108 #define IXGBE_INCVAL_SHIFT_1GB   24
 109 #define IXGBE_INCVAL_SHIFT_100   21
 110 #define IXGBE_INCVAL_SHIFT_82599 7
 111 #define IXGBE_INCPER_SHIFT_82599 24
 112
 113 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 114
 115 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 116 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 117 #define IXGBE_ETAG_ETYPE                       0x00005084
 118 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 119 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 120 #define IXGBE_RAH_ADTYPE                       0x40000000
 121 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 122 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 123 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 124 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 125 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 126 #define IXGBE_VTEICR_MASK                      0x07
 127
 128 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 129 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 130
 131 #define IXGBEVF_DEVARG_PFLINK_FULLCHK           "pflink_fullchk"
 132
 133 static const char * const ixgbevf_valid_arguments[] = {
 134         IXGBEVF_DEVARG_PFLINK_FULLCHK,
 135         NULL
 136 };
 137
 138 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 139 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 140 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 141 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 142 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 143 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 144 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 145 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
 146 static int ixgbe_dev_start(struct rte_eth_dev *dev);
 147 static int ixgbe_dev_stop(struct rte_eth_dev *dev);
 148 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 149 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 150 static int ixgbe_dev_close(struct rte_eth_dev *dev);
 151 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
 152 static int ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 154 static int ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 155 static int ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 156 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 157                                 int wait_to_complete);
 158 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 159                                 struct rte_eth_stats *stats);
 160 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 161                                 struct rte_eth_xstat *xstats, unsigned n);
 162 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 163                                   struct rte_eth_xstat *xstats, unsigned n);
 164 static int
 165 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 166                 uint64_t *values, unsigned int n);
 167 static int ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 168 static int ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 169 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
 170         struct rte_eth_xstat_name *xstats_names,
 171         unsigned int size);
 172 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
 173         struct rte_eth_xstat_name *xstats_names, unsigned limit);
 174 static int ixgbe_dev_xstats_get_names_by_id(
 175         struct rte_eth_dev *dev,
 176         struct rte_eth_xstat_name *xstats_names,
 177         const uint64_t *ids,
 178         unsigned int limit);
 179 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 180                                              uint16_t queue_id,
 181                                              uint8_t stat_idx,
 182                                              uint8_t is_rx);
 183 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 184                                  size_t fw_size);
 185 static int ixgbe_dev_info_get(struct rte_eth_dev *dev,
 186                               struct rte_eth_dev_info *dev_info);
 187 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 188 static int ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_dev_info *dev_info);
 190 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 191
 192 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 193                 uint16_t vlan_id, int on);
 194 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 195                                enum rte_vlan_type vlan_type,
 196                                uint16_t tpid_id);
 197 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 198                 uint16_t queue, bool on);
 199 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 200                 int on);
 201 static void ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev,
 202                                                   int mask);
 203 static int ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 204 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 205 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 206 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 207 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 208 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 209
 210 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 211 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 212 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 213                                struct rte_eth_fc_conf *fc_conf);
 214 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 215                                struct rte_eth_fc_conf *fc_conf);
 216 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 217                 struct rte_eth_pfc_conf *pfc_conf);
 218 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 219                         struct rte_eth_rss_reta_entry64 *reta_conf,
 220                         uint16_t reta_size);
 221 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 222                         struct rte_eth_rss_reta_entry64 *reta_conf,
 223                         uint16_t reta_size);
 224 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 225 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 226 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 228 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 229 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 230 static void ixgbe_dev_interrupt_handler(void *param);
 231 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 232 static void *ixgbe_dev_setup_link_thread_handler(void *param);
 233 static int ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev,
 234                                               uint32_t timeout_ms);
 235
 236 static int ixgbe_add_rar(struct rte_eth_dev *dev,
 237                         struct rte_ether_addr *mac_addr,
 238                         uint32_t index, uint32_t pool);
 239 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 240 static int ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 241                                            struct rte_ether_addr *mac_addr);
 242 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 243 static bool is_device_supported(struct rte_eth_dev *dev,
 244                                 struct rte_pci_driver *drv);
 245
 246 /* For Virtual Function support */
 247 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 248 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 249 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 250 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 251 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
 252                                    int wait_to_complete);
 253 static int ixgbevf_dev_stop(struct rte_eth_dev *dev);
 254 static int ixgbevf_dev_close(struct rte_eth_dev *dev);
 255 static int  ixgbevf_dev_reset(struct rte_eth_dev *dev);
 256 static void ixgbevf_intr_disable(struct rte_eth_dev *dev);
 257 static void ixgbevf_intr_enable(struct rte_eth_dev *dev);
 258 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 259                 struct rte_eth_stats *stats);
 260 static int ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 261 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 262                 uint16_t vlan_id, int on);
 263 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 264                 uint16_t queue, int on);
 265 static int ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
 266 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 267 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 268 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 269                                             uint16_t queue_id);
 270 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 271                                              uint16_t queue_id);
 272 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 273                                  uint8_t queue, uint8_t msix_vector);
 274 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 275 static int ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 276 static int ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 277 static int ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 278 static int ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 279
 280 /* For Eth VMDQ APIs support */
 281 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 282                 rte_ether_addr * mac_addr, uint8_t on);
 283 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 284 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 285                 struct rte_eth_mirror_conf *mirror_conf,
 286                 uint8_t rule_id, uint8_t on);
 287 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 288                 uint8_t rule_id);
 289 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 290                                           uint16_t queue_id);
 291 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 292                                            uint16_t queue_id);
 293 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 294                                uint8_t queue, uint8_t msix_vector);
 295 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 296
 297 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 298                                 struct rte_ether_addr *mac_addr,
 299                                 uint32_t index, uint32_t pool);
 300 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 301 static int ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 302                                              struct rte_ether_addr *mac_addr);
 303 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 304                         struct ixgbe_5tuple_filter *filter);
 305 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 306                         struct ixgbe_5tuple_filter *filter);
 307 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 308                      enum rte_filter_type filter_type,
 309                      enum rte_filter_op filter_op,
 310                      void *arg);
 311 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 312
 313 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 314                                       struct rte_ether_addr *mc_addr_set,
 315                                       uint32_t nb_mc_addr);
 316 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 317                                    struct rte_eth_dcb_info *dcb_info);
 318
 319 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 320 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 321                             struct rte_dev_reg_info *regs);
 322 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 323 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 324                                 struct rte_dev_eeprom_info *eeprom);
 325 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 326                                 struct rte_dev_eeprom_info *eeprom);
 327
 328 static int ixgbe_get_module_info(struct rte_eth_dev *dev,
 329                                  struct rte_eth_dev_module_info *modinfo);
 330 static int ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
 331                                    struct rte_dev_eeprom_info *info);
 332
 333 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 334 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 335                                 struct rte_dev_reg_info *regs);
 336
 337 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 338 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 339 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 340                                             struct timespec *timestamp,
 341                                             uint32_t flags);
 342 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 343                                             struct timespec *timestamp);
 344 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 345 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 346                                    struct timespec *timestamp);
 347 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 348                                    const struct timespec *timestamp);
 349 static void ixgbevf_dev_interrupt_handler(void *param);
 350
 351 static int ixgbe_dev_l2_tunnel_offload_set
 352         (struct rte_eth_dev *dev,
 353          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 354          uint32_t mask,
 355          uint8_t en);
 356
 357 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 358                                          struct rte_eth_udp_tunnel *udp_tunnel);
 359 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 360                                          struct rte_eth_udp_tunnel *udp_tunnel);
 361 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 362 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 363 static int ixgbe_wait_for_link_up(struct ixgbe_hw *hw);
 364
 365 /*
 366  * Define VF Stats MACRO for Non "cleared on read" register
 367  */
 368 #define UPDATE_VF_STAT(reg, last, cur)                          \
 369 {                                                               \
 370         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 371         cur += (latest - last) & UINT_MAX;                      \
 372         last = latest;                                          \
 373 }
 374
 375 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 376 {                                                                \
 377         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 378         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 379         u64 latest = ((new_msb << 32) | new_lsb);                \
 380         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 381         last = latest;                                           \
 382 }
 383
 384 #define IXGBE_SET_HWSTRIP(h, q) do {\
 385                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 386                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 387                 (h)->bitmap[idx] |= 1 << bit;\
 388         } while (0)
 389
 390 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 391                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 392                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 393                 (h)->bitmap[idx] &= ~(1 << bit);\
 394         } while (0)
 395
 396 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 397                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 398                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 399                 (r) = (h)->bitmap[idx] >> bit & 1;\
 400         } while (0)
 401
 402 /*
 403  * The set of PCI devices this driver supports
 404  */
 405 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 406         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 407         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 408         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 409         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 410         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 411         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 412         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 413         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 414         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 415         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 416         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 417         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 418         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 419         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 420         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 421         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 422         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 423         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 424         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 425         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 426         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 427         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 428         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 429         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_XFI) },
 454 #ifdef RTE_LIBRTE_IXGBE_BYPASS
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 456 #endif
 457         { .vendor_id = 0, /* sentinel */ },
 458 };
 459
 460 /*
 461  * The set of PCI devices this driver supports (for 82599 VF)
 462  */
 463 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 474         { .vendor_id = 0, /* sentinel */ },
 475 };
 476
 477 static const struct rte_eth_desc_lim rx_desc_lim = {
 478         .nb_max = IXGBE_MAX_RING_DESC,
 479         .nb_min = IXGBE_MIN_RING_DESC,
 480         .nb_align = IXGBE_RXD_ALIGN,
 481 };
 482
 483 static const struct rte_eth_desc_lim tx_desc_lim = {
 484         .nb_max = IXGBE_MAX_RING_DESC,
 485         .nb_min = IXGBE_MIN_RING_DESC,
 486         .nb_align = IXGBE_TXD_ALIGN,
 487         .nb_seg_max = IXGBE_TX_MAX_SEG,
 488         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 489 };
 490
 491 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 492         .dev_configure        = ixgbe_dev_configure,
 493         .dev_start            = ixgbe_dev_start,
 494         .dev_stop             = ixgbe_dev_stop,
 495         .dev_set_link_up    = ixgbe_dev_set_link_up,
 496         .dev_set_link_down  = ixgbe_dev_set_link_down,
 497         .dev_close            = ixgbe_dev_close,
 498         .dev_reset            = ixgbe_dev_reset,
 499         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 500         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 501         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 502         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 503         .link_update          = ixgbe_dev_link_update,
 504         .stats_get            = ixgbe_dev_stats_get,
 505         .xstats_get           = ixgbe_dev_xstats_get,
 506         .xstats_get_by_id     = ixgbe_dev_xstats_get_by_id,
 507         .stats_reset          = ixgbe_dev_stats_reset,
 508         .xstats_reset         = ixgbe_dev_xstats_reset,
 509         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 510         .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
 511         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 512         .fw_version_get       = ixgbe_fw_version_get,
 513         .dev_infos_get        = ixgbe_dev_info_get,
 514         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 515         .mtu_set              = ixgbe_dev_mtu_set,
 516         .vlan_filter_set      = ixgbe_vlan_filter_set,
 517         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 518         .vlan_offload_set     = ixgbe_vlan_offload_set,
 519         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 520         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 521         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 522         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 523         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 524         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 525         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 526         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 527         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 528         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 529         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 530         .dev_led_on           = ixgbe_dev_led_on,
 531         .dev_led_off          = ixgbe_dev_led_off,
 532         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 533         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 534         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 535         .mac_addr_add         = ixgbe_add_rar,
 536         .mac_addr_remove      = ixgbe_remove_rar,
 537         .mac_addr_set         = ixgbe_set_default_mac_addr,
 538         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 539         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 540         .mirror_rule_set      = ixgbe_mirror_rule_set,
 541         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 542         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 543         .reta_update          = ixgbe_dev_rss_reta_update,
 544         .reta_query           = ixgbe_dev_rss_reta_query,
 545         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 546         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 547         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 548         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 549         .rxq_info_get         = ixgbe_rxq_info_get,
 550         .txq_info_get         = ixgbe_txq_info_get,
 551         .timesync_enable      = ixgbe_timesync_enable,
 552         .timesync_disable     = ixgbe_timesync_disable,
 553         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 554         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 555         .get_reg              = ixgbe_get_regs,
 556         .get_eeprom_length    = ixgbe_get_eeprom_length,
 557         .get_eeprom           = ixgbe_get_eeprom,
 558         .set_eeprom           = ixgbe_set_eeprom,
 559         .get_module_info      = ixgbe_get_module_info,
 560         .get_module_eeprom    = ixgbe_get_module_eeprom,
 561         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 562         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 563         .timesync_read_time   = ixgbe_timesync_read_time,
 564         .timesync_write_time  = ixgbe_timesync_write_time,
 565         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 566         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 567         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 568         .tm_ops_get           = ixgbe_tm_ops_get,
 569         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 570 };
 571
 572 /*
 573  * dev_ops for virtual function, bare necessities for basic vf
 574  * operation have been implemented
 575  */
 576 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 577         .dev_configure        = ixgbevf_dev_configure,
 578         .dev_start            = ixgbevf_dev_start,
 579         .dev_stop             = ixgbevf_dev_stop,
 580         .link_update          = ixgbevf_dev_link_update,
 581         .stats_get            = ixgbevf_dev_stats_get,
 582         .xstats_get           = ixgbevf_dev_xstats_get,
 583         .stats_reset          = ixgbevf_dev_stats_reset,
 584         .xstats_reset         = ixgbevf_dev_stats_reset,
 585         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 586         .dev_close            = ixgbevf_dev_close,
 587         .dev_reset            = ixgbevf_dev_reset,
 588         .promiscuous_enable   = ixgbevf_dev_promiscuous_enable,
 589         .promiscuous_disable  = ixgbevf_dev_promiscuous_disable,
 590         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 591         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 592         .dev_infos_get        = ixgbevf_dev_info_get,
 593         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 594         .mtu_set              = ixgbevf_dev_set_mtu,
 595         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 596         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 597         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 598         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 599         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 600         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 601         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 602         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 603         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 604         .mac_addr_add         = ixgbevf_add_mac_addr,
 605         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 606         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 607         .rxq_info_get         = ixgbe_rxq_info_get,
 608         .txq_info_get         = ixgbe_txq_info_get,
 609         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 610         .get_reg              = ixgbevf_get_regs,
 611         .reta_update          = ixgbe_dev_rss_reta_update,
 612         .reta_query           = ixgbe_dev_rss_reta_query,
 613         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 614         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 615         .tx_done_cleanup      = ixgbe_dev_tx_done_cleanup,
 616 };
 617
 618 /* store statistics names and its offset in stats structure */
 619 struct rte_ixgbe_xstats_name_off {
 620         char name[RTE_ETH_XSTATS_NAME_SIZE];
 621         unsigned offset;
 622 };
 623
 624 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 625         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 626         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 627         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 628         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 629         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 630         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 631         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 632         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 633         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 634         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 635         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 636         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 637         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 638         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 639         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 640                 prc1023)},
 641         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 642                 prc1522)},
 643         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 644         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 645         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 646         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 647         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 648         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 649         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 650         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 651         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 652         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 653         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 654         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 655         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 656         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 657         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 658         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 659         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 660                 ptc1023)},
 661         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 662                 ptc1522)},
 663         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 664         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 665         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 666         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 667
 668         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 669                 fdirustat_add)},
 670         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 671                 fdirustat_remove)},
 672         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 673                 fdirfstat_fadd)},
 674         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 675                 fdirfstat_fremove)},
 676         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 677                 fdirmatch)},
 678         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 679                 fdirmiss)},
 680
 681         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 682         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 683         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 684                 fclast)},
 685         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 686         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 687         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 688         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 689         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 690                 fcoe_noddp)},
 691         {"rx_fcoe_no_direct_data_placement_ext_buff",
 692                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 693
 694         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 695                 lxontxc)},
 696         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 697                 lxonrxc)},
 698         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 699                 lxofftxc)},
 700         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 701                 lxoffrxc)},
 702         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 703 };
 704
 705 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 706                            sizeof(rte_ixgbe_stats_strings[0]))
 707
 708 /* MACsec statistics */
 709 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 710         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 711                 out_pkts_untagged)},
 712         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 713                 out_pkts_encrypted)},
 714         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 715                 out_pkts_protected)},
 716         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 717                 out_octets_encrypted)},
 718         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 719                 out_octets_protected)},
 720         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 721                 in_pkts_untagged)},
 722         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 723                 in_pkts_badtag)},
 724         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 725                 in_pkts_nosci)},
 726         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 727                 in_pkts_unknownsci)},
 728         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 729                 in_octets_decrypted)},
 730         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 731                 in_octets_validated)},
 732         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 733                 in_pkts_unchecked)},
 734         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 735                 in_pkts_delayed)},
 736         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 737                 in_pkts_late)},
 738         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 739                 in_pkts_ok)},
 740         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 741                 in_pkts_invalid)},
 742         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 743                 in_pkts_notvalid)},
 744         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 745                 in_pkts_unusedsa)},
 746         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 747                 in_pkts_notusingsa)},
 748 };
 749
 750 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 751                            sizeof(rte_ixgbe_macsec_strings[0]))
 752
 753 /* Per-queue statistics */
 754 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 755         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 756         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 757         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 758         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 759 };
 760
 761 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 762                            sizeof(rte_ixgbe_rxq_strings[0]))
 763 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 764
 765 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 766         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 767         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 768         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 769                 pxon2offc)},
 770 };
 771
 772 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 773                            sizeof(rte_ixgbe_txq_strings[0]))
 774 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 775
 776 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 777         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 778 };
 779
 780 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 781                 sizeof(rte_ixgbevf_stats_strings[0]))
 782
 783 /*
 784  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 785  */
 786 static inline int
 787 ixgbe_is_sfp(struct ixgbe_hw *hw)
 788 {
 789         switch (hw->phy.type) {
 790         case ixgbe_phy_sfp_avago:
 791         case ixgbe_phy_sfp_ftl:
 792         case ixgbe_phy_sfp_intel:
 793         case ixgbe_phy_sfp_unknown:
 794         case ixgbe_phy_sfp_passive_tyco:
 795         case ixgbe_phy_sfp_passive_unknown:
 796                 return 1;
 797         default:
 798                 return 0;
 799         }
 800 }
 801
 802 static inline int32_t
 803 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 804 {
 805         uint32_t ctrl_ext;
 806         int32_t status;
 807
 808         status = ixgbe_reset_hw(hw);
 809
 810         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 811         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 812         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 813         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 814         IXGBE_WRITE_FLUSH(hw);
 815
 816         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
 817                 status = IXGBE_SUCCESS;
 818         return status;
 819 }
 820
 821 static inline void
 822 ixgbe_enable_intr(struct rte_eth_dev *dev)
 823 {
 824         struct ixgbe_interrupt *intr =
 825                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 826         struct ixgbe_hw *hw =
 827                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 828
 829         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 830         IXGBE_WRITE_FLUSH(hw);
 831 }
 832
 833 /*
 834  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 835  */
 836 static void
 837 ixgbe_disable_intr(struct ixgbe_hw *hw)
 838 {
 839         PMD_INIT_FUNC_TRACE();
 840
 841         if (hw->mac.type == ixgbe_mac_82598EB) {
 842                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 843         } else {
 844                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 845                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 846                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 847         }
 848         IXGBE_WRITE_FLUSH(hw);
 849 }
 850
 851 /*
 852  * This function resets queue statistics mapping registers.
 853  * From Niantic datasheet, Initialization of Statistics section:
 854  * "...if software requires the queue counters, the RQSMR and TQSM registers
 855  * must be re-programmed following a device reset.
 856  */
 857 static void
 858 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 859 {
 860         uint32_t i;
 861
 862         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 863                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 864                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 865         }
 866 }
 867
 868
 869 static int
 870 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 871                                   uint16_t queue_id,
 872                                   uint8_t stat_idx,
 873                                   uint8_t is_rx)
 874 {
 875 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 876 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 877 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 878
 879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 880         struct ixgbe_stat_mapping_registers *stat_mappings =
 881                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 882         uint32_t qsmr_mask = 0;
 883         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 884         uint32_t q_map;
 885         uint8_t n, offset;
 886
 887         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 888                 (hw->mac.type != ixgbe_mac_X540) &&
 889                 (hw->mac.type != ixgbe_mac_X550) &&
 890                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 891                 (hw->mac.type != ixgbe_mac_X550EM_a))
 892                 return -ENOSYS;
 893
 894         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 895                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 896                      queue_id, stat_idx);
 897
 898         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 899         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 900                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 901                 return -EIO;
 902         }
 903         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 904
 905         /* Now clear any previous stat_idx set */
 906         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 907         if (!is_rx)
 908                 stat_mappings->tqsm[n] &= ~clearing_mask;
 909         else
 910                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 911
 912         q_map = (uint32_t)stat_idx;
 913         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 914         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 915         if (!is_rx)
 916                 stat_mappings->tqsm[n] |= qsmr_mask;
 917         else
 918                 stat_mappings->rqsmr[n] |= qsmr_mask;
 919
 920         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 921                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 922                      queue_id, stat_idx);
 923         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 924                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 925
 926         /* Now write the mapping in the appropriate register */
 927         if (is_rx) {
 928                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 929                              stat_mappings->rqsmr[n], n);
 930                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 931         } else {
 932                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 933                              stat_mappings->tqsm[n], n);
 934                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 935         }
 936         return 0;
 937 }
 938
 939 static void
 940 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
 941 {
 942         struct ixgbe_stat_mapping_registers *stat_mappings =
 943                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 944         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945         int i;
 946
 947         /* write whatever was in stat mapping table to the NIC */
 948         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 949                 /* rx */
 950                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 951
 952                 /* tx */
 953                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 954         }
 955 }
 956
 957 static void
 958 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
 959 {
 960         uint8_t i;
 961         struct ixgbe_dcb_tc_config *tc;
 962         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 963
 964         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 965         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 966         for (i = 0; i < dcb_max_tc; i++) {
 967                 tc = &dcb_config->tc_config[i];
 968                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 969                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 970                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 971                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 972                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 973                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 974                 tc->pfc = ixgbe_dcb_pfc_disabled;
 975         }
 976
 977         /* Initialize default user to priority mapping, UPx->TC0 */
 978         tc = &dcb_config->tc_config[0];
 979         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 980         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 981         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
 982                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 983                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 984         }
 985         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 986         dcb_config->pfc_mode_enable = false;
 987         dcb_config->vt_mode = true;
 988         dcb_config->round_robin_enable = false;
 989         /* support all DCB capabilities in 82599 */
 990         dcb_config->support.capabilities = 0xFF;
 991
 992         /*we only support 4 Tcs for X540, X550 */
 993         if (hw->mac.type == ixgbe_mac_X540 ||
 994                 hw->mac.type == ixgbe_mac_X550 ||
 995                 hw->mac.type == ixgbe_mac_X550EM_x ||
 996                 hw->mac.type == ixgbe_mac_X550EM_a) {
 997                 dcb_config->num_tcs.pg_tcs = 4;
 998                 dcb_config->num_tcs.pfc_tcs = 4;
 999         }
1000 }
1001
1002 /*
1003  * Ensure that all locks are released before first NVM or PHY access
1004  */
1005 static void
1006 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1007 {
1008         uint16_t mask;
1009
1010         /*
1011          * Phy lock should not fail in this early stage. If this is the case,
1012          * it is due to an improper exit of the application.
1013          * So force the release of the faulty lock. Release of common lock
1014          * is done automatically by swfw_sync function.
1015          */
1016         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1017         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1018                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1019         }
1020         ixgbe_release_swfw_semaphore(hw, mask);
1021
1022         /*
1023          * These ones are more tricky since they are common to all ports; but
1024          * swfw_sync retries last long enough (1s) to be almost sure that if
1025          * lock can not be taken it is due to an improper lock of the
1026          * semaphore.
1027          */
1028         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1029         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1030                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1031         }
1032         ixgbe_release_swfw_semaphore(hw, mask);
1033 }
1034
1035 /*
1036  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1037  * It returns 0 on success.
1038  */
1039 static int
1040 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
1041 {
1042         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1043         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1044         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1045         struct ixgbe_hw *hw =
1046                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1047         struct ixgbe_vfta *shadow_vfta =
1048                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1049         struct ixgbe_hwstrip *hwstrip =
1050                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1051         struct ixgbe_dcb_config *dcb_config =
1052                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1053         struct ixgbe_filter_info *filter_info =
1054                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1055         struct ixgbe_bw_conf *bw_conf =
1056                 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1057         uint32_t ctrl_ext;
1058         uint16_t csum;
1059         int diag, i, ret;
1060
1061         PMD_INIT_FUNC_TRACE();
1062
1063         ixgbe_dev_macsec_setting_reset(eth_dev);
1064
1065         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1066         eth_dev->rx_queue_count       = ixgbe_dev_rx_queue_count;
1067         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1068         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1069         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1070         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1071         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1072         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1073
1074         /*
1075          * For secondary processes, we don't initialise any further as primary
1076          * has already done this work. Only check we don't need a different
1077          * RX and TX function.
1078          */
1079         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1080                 struct ixgbe_tx_queue *txq;
1081                 /* TX queue function in primary, set by last queue initialized
1082                  * Tx queue may not initialized by primary process
1083                  */
1084                 if (eth_dev->data->tx_queues) {
1085                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1086                         ixgbe_set_tx_function(eth_dev, txq);
1087                 } else {
1088                         /* Use default TX function if we get here */
1089                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1090                                      "Using default TX function.");
1091                 }
1092
1093                 ixgbe_set_rx_function(eth_dev);
1094
1095                 return 0;
1096         }
1097
1098         rte_atomic32_clear(&ad->link_thread_running);
1099         rte_eth_copy_pci_info(eth_dev, pci_dev);
1100         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1101
1102         /* Vendor and Device ID need to be set before init of shared code */
1103         hw->device_id = pci_dev->id.device_id;
1104         hw->vendor_id = pci_dev->id.vendor_id;
1105         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1106         hw->allow_unsupported_sfp = 1;
1107
1108         /* Initialize the shared code (base driver) */
1109 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1110         diag = ixgbe_bypass_init_shared_code(hw);
1111 #else
1112         diag = ixgbe_init_shared_code(hw);
1113 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1114
1115         if (diag != IXGBE_SUCCESS) {
1116                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1117                 return -EIO;
1118         }
1119
1120         if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
1121                 PMD_INIT_LOG(ERR, "\nERROR: "
1122                         "Firmware recovery mode detected. Limiting functionality.\n"
1123                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1124                         "User Guide for details on firmware recovery mode.");
1125                 return -EIO;
1126         }
1127
1128         /* pick up the PCI bus settings for reporting later */
1129         ixgbe_get_bus_info(hw);
1130
1131         /* Unlock any pending hardware semaphore */
1132         ixgbe_swfw_lock_reset(hw);
1133
1134 #ifdef RTE_LIB_SECURITY
1135         /* Initialize security_ctx only for primary process*/
1136         if (ixgbe_ipsec_ctx_create(eth_dev))
1137                 return -ENOMEM;
1138 #endif
1139
1140         /* Initialize DCB configuration*/
1141         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1142         ixgbe_dcb_init(hw, dcb_config);
1143         /* Get Hardware Flow Control setting */
1144         hw->fc.requested_mode = ixgbe_fc_none;
1145         hw->fc.current_mode = ixgbe_fc_none;
1146         hw->fc.pause_time = IXGBE_FC_PAUSE;
1147         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1148                 hw->fc.low_water[i] = IXGBE_FC_LO;
1149                 hw->fc.high_water[i] = IXGBE_FC_HI;
1150         }
1151         hw->fc.send_xon = 1;
1152
1153         /* Make sure we have a good EEPROM before we read from it */
1154         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1155         if (diag != IXGBE_SUCCESS) {
1156                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1157                 return -EIO;
1158         }
1159
1160 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1161         diag = ixgbe_bypass_init_hw(hw);
1162 #else
1163         diag = ixgbe_init_hw(hw);
1164 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1165
1166         /*
1167          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1168          * is called too soon after the kernel driver unbinding/binding occurs.
1169          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1170          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1171          * also called. See ixgbe_identify_phy_82599(). The reason for the
1172          * failure is not known, and only occuts when virtualisation features
1173          * are disabled in the bios. A delay of 100ms  was found to be enough by
1174          * trial-and-error, and is doubled to be safe.
1175          */
1176         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1177                 rte_delay_ms(200);
1178                 diag = ixgbe_init_hw(hw);
1179         }
1180
1181         if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1182                 diag = IXGBE_SUCCESS;
1183
1184         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1185                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1186                              "LOM.  Please be aware there may be issues associated "
1187                              "with your hardware.");
1188                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1189                              "please contact your Intel or hardware representative "
1190                              "who provided you with this hardware.");
1191         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1192                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1193         if (diag) {
1194                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1195                 return -EIO;
1196         }
1197
1198         /* Reset the hw statistics */
1199         ixgbe_dev_stats_reset(eth_dev);
1200
1201         /* disable interrupt */
1202         ixgbe_disable_intr(hw);
1203
1204         /* reset mappings for queue statistics hw counters*/
1205         ixgbe_reset_qstat_mappings(hw);
1206
1207         /* Allocate memory for storing MAC addresses */
1208         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", RTE_ETHER_ADDR_LEN *
1209                                                hw->mac.num_rar_entries, 0);
1210         if (eth_dev->data->mac_addrs == NULL) {
1211                 PMD_INIT_LOG(ERR,
1212                              "Failed to allocate %u bytes needed to store "
1213                              "MAC addresses",
1214                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1215                 return -ENOMEM;
1216         }
1217         /* Copy the permanent MAC address */
1218         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1219                         &eth_dev->data->mac_addrs[0]);
1220
1221         /* Allocate memory for storing hash filter MAC addresses */
1222         eth_dev->data->hash_mac_addrs = rte_zmalloc(
1223                 "ixgbe", RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC, 0);
1224         if (eth_dev->data->hash_mac_addrs == NULL) {
1225                 PMD_INIT_LOG(ERR,
1226                              "Failed to allocate %d bytes needed to store MAC addresses",
1227                              RTE_ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1228                 return -ENOMEM;
1229         }
1230
1231         /* initialize the vfta */
1232         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1233
1234         /* initialize the hw strip bitmap*/
1235         memset(hwstrip, 0, sizeof(*hwstrip));
1236
1237         /* initialize PF if max_vfs not zero */
1238         ret = ixgbe_pf_host_init(eth_dev);
1239         if (ret) {
1240                 rte_free(eth_dev->data->mac_addrs);
1241                 eth_dev->data->mac_addrs = NULL;
1242                 rte_free(eth_dev->data->hash_mac_addrs);
1243                 eth_dev->data->hash_mac_addrs = NULL;
1244                 return ret;
1245         }
1246
1247         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1248         /* let hardware know driver is loaded */
1249         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1250         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1251         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1252         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1253         IXGBE_WRITE_FLUSH(hw);
1254
1255         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1256                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1257                              (int) hw->mac.type, (int) hw->phy.type,
1258                              (int) hw->phy.sfp_type);
1259         else
1260                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1261                              (int) hw->mac.type, (int) hw->phy.type);
1262
1263         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1264                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1265                      pci_dev->id.device_id);
1266
1267         rte_intr_callback_register(intr_handle,
1268                                    ixgbe_dev_interrupt_handler, eth_dev);
1269
1270         /* enable uio/vfio intr/eventfd mapping */
1271         rte_intr_enable(intr_handle);
1272
1273         /* enable support intr */
1274         ixgbe_enable_intr(eth_dev);
1275
1276         /* initialize filter info */
1277         memset(filter_info, 0,
1278                sizeof(struct ixgbe_filter_info));
1279
1280         /* initialize 5tuple filter list */
1281         TAILQ_INIT(&filter_info->fivetuple_list);
1282
1283         /* initialize flow director filter list & hash */
1284         ixgbe_fdir_filter_init(eth_dev);
1285
1286         /* initialize l2 tunnel filter list & hash */
1287         ixgbe_l2_tn_filter_init(eth_dev);
1288
1289         /* initialize flow filter lists */
1290         ixgbe_filterlist_init();
1291
1292         /* initialize bandwidth configuration info */
1293         memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1294
1295         /* initialize Traffic Manager configuration */
1296         ixgbe_tm_conf_init(eth_dev);
1297
1298         return 0;
1299 }
1300
1301 static int
1302 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1303 {
1304         PMD_INIT_FUNC_TRACE();
1305
1306         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1307                 return 0;
1308
1309         ixgbe_dev_close(eth_dev);
1310
1311         return 0;
1312 }
1313
1314 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1315 {
1316         struct ixgbe_filter_info *filter_info =
1317                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1318         struct ixgbe_5tuple_filter *p_5tuple;
1319
1320         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1321                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1322                              p_5tuple,
1323                              entries);
1324                 rte_free(p_5tuple);
1325         }
1326         memset(filter_info->fivetuple_mask, 0,
1327                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1328
1329         return 0;
1330 }
1331
1332 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1333 {
1334         struct ixgbe_hw_fdir_info *fdir_info =
1335                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1336         struct ixgbe_fdir_filter *fdir_filter;
1337
1338                 if (fdir_info->hash_map)
1339                 rte_free(fdir_info->hash_map);
1340         if (fdir_info->hash_handle)
1341                 rte_hash_free(fdir_info->hash_handle);
1342
1343         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1344                 TAILQ_REMOVE(&fdir_info->fdir_list,
1345                              fdir_filter,
1346                              entries);
1347                 rte_free(fdir_filter);
1348         }
1349
1350         return 0;
1351 }
1352
1353 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1354 {
1355         struct ixgbe_l2_tn_info *l2_tn_info =
1356                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1357         struct ixgbe_l2_tn_filter *l2_tn_filter;
1358
1359         if (l2_tn_info->hash_map)
1360                 rte_free(l2_tn_info->hash_map);
1361         if (l2_tn_info->hash_handle)
1362                 rte_hash_free(l2_tn_info->hash_handle);
1363
1364         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1365                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1366                              l2_tn_filter,
1367                              entries);
1368                 rte_free(l2_tn_filter);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1375 {
1376         struct ixgbe_hw_fdir_info *fdir_info =
1377                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1378         char fdir_hash_name[RTE_HASH_NAMESIZE];
1379         struct rte_hash_parameters fdir_hash_params = {
1380                 .name = fdir_hash_name,
1381                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1382                 .key_len = sizeof(union ixgbe_atr_input),
1383                 .hash_func = rte_hash_crc,
1384                 .hash_func_init_val = 0,
1385                 .socket_id = rte_socket_id(),
1386         };
1387
1388         TAILQ_INIT(&fdir_info->fdir_list);
1389         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1390                  "fdir_%s", eth_dev->device->name);
1391         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1392         if (!fdir_info->hash_handle) {
1393                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1394                 return -EINVAL;
1395         }
1396         fdir_info->hash_map = rte_zmalloc("ixgbe",
1397                                           sizeof(struct ixgbe_fdir_filter *) *
1398                                           IXGBE_MAX_FDIR_FILTER_NUM,
1399                                           0);
1400         if (!fdir_info->hash_map) {
1401                 PMD_INIT_LOG(ERR,
1402                              "Failed to allocate memory for fdir hash map!");
1403                 return -ENOMEM;
1404         }
1405         fdir_info->mask_added = FALSE;
1406
1407         return 0;
1408 }
1409
1410 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1411 {
1412         struct ixgbe_l2_tn_info *l2_tn_info =
1413                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1414         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1415         struct rte_hash_parameters l2_tn_hash_params = {
1416                 .name = l2_tn_hash_name,
1417                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1418                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1419                 .hash_func = rte_hash_crc,
1420                 .hash_func_init_val = 0,
1421                 .socket_id = rte_socket_id(),
1422         };
1423
1424         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1425         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1426                  "l2_tn_%s", eth_dev->device->name);
1427         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1428         if (!l2_tn_info->hash_handle) {
1429                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1430                 return -EINVAL;
1431         }
1432         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1433                                    sizeof(struct ixgbe_l2_tn_filter *) *
1434                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1435                                    0);
1436         if (!l2_tn_info->hash_map) {
1437                 PMD_INIT_LOG(ERR,
1438                         "Failed to allocate memory for L2 TN hash map!");
1439                 return -ENOMEM;
1440         }
1441         l2_tn_info->e_tag_en = FALSE;
1442         l2_tn_info->e_tag_fwd_en = FALSE;
1443         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
1444
1445         return 0;
1446 }
1447 /*
1448  * Negotiate mailbox API version with the PF.
1449  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1450  * Then we try to negotiate starting with the most recent one.
1451  * If all negotiation attempts fail, then we will proceed with
1452  * the default one (ixgbe_mbox_api_10).
1453  */
1454 static void
1455 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1456 {
1457         int32_t i;
1458
1459         /* start with highest supported, proceed down */
1460         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1461                 ixgbe_mbox_api_13,
1462                 ixgbe_mbox_api_12,
1463                 ixgbe_mbox_api_11,
1464                 ixgbe_mbox_api_10,
1465         };
1466
1467         for (i = 0;
1468                         i != RTE_DIM(sup_ver) &&
1469                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1470                         i++)
1471                 ;
1472 }
1473
1474 static void
1475 generate_random_mac_addr(struct rte_ether_addr *mac_addr)
1476 {
1477         uint64_t random;
1478
1479         /* Set Organizationally Unique Identifier (OUI) prefix. */
1480         mac_addr->addr_bytes[0] = 0x00;
1481         mac_addr->addr_bytes[1] = 0x09;
1482         mac_addr->addr_bytes[2] = 0xC0;
1483         /* Force indication of locally assigned MAC address. */
1484         mac_addr->addr_bytes[0] |= RTE_ETHER_LOCAL_ADMIN_ADDR;
1485         /* Generate the last 3 bytes of the MAC address with a random number. */
1486         random = rte_rand();
1487         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1488 }
1489
1490 static int
1491 devarg_handle_int(__rte_unused const char *key, const char *value,
1492                   void *extra_args)
1493 {
1494         uint16_t *n = extra_args;
1495
1496         if (value == NULL || extra_args == NULL)
1497                 return -EINVAL;
1498
1499         *n = (uint16_t)strtoul(value, NULL, 0);
1500         if (*n == USHRT_MAX && errno == ERANGE)
1501                 return -1;
1502
1503         return 0;
1504 }
1505
1506 static void
1507 ixgbevf_parse_devargs(struct ixgbe_adapter *adapter,
1508                       struct rte_devargs *devargs)
1509 {
1510         struct rte_kvargs *kvlist;
1511         uint16_t pflink_fullchk;
1512
1513         if (devargs == NULL)
1514                 return;
1515
1516         kvlist = rte_kvargs_parse(devargs->args, ixgbevf_valid_arguments);
1517         if (kvlist == NULL)
1518                 return;
1519
1520         if (rte_kvargs_count(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK) == 1 &&
1521             rte_kvargs_process(kvlist, IXGBEVF_DEVARG_PFLINK_FULLCHK,
1522                                devarg_handle_int, &pflink_fullchk) == 0 &&
1523             pflink_fullchk == 1)
1524                 adapter->pflink_fullchk = 1;
1525
1526         rte_kvargs_free(kvlist);
1527 }
1528
1529 /*
1530  * Virtual Function device init
1531  */
1532 static int
1533 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1534 {
1535         int diag;
1536         uint32_t tc, tcs;
1537         struct ixgbe_adapter *ad = eth_dev->data->dev_private;
1538         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1539         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1540         struct ixgbe_hw *hw =
1541                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1542         struct ixgbe_vfta *shadow_vfta =
1543                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1544         struct ixgbe_hwstrip *hwstrip =
1545                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1546         struct rte_ether_addr *perm_addr =
1547                 (struct rte_ether_addr *)hw->mac.perm_addr;
1548
1549         PMD_INIT_FUNC_TRACE();
1550
1551         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1552         eth_dev->rx_descriptor_done   = ixgbe_dev_rx_descriptor_done;
1553         eth_dev->rx_descriptor_status = ixgbe_dev_rx_descriptor_status;
1554         eth_dev->tx_descriptor_status = ixgbe_dev_tx_descriptor_status;
1555         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1556         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1557
1558         /* for secondary processes, we don't initialise any further as primary
1559          * has already done this work. Only check we don't need a different
1560          * RX function
1561          */
1562         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1563                 struct ixgbe_tx_queue *txq;
1564                 /* TX queue function in primary, set by last queue initialized
1565                  * Tx queue may not initialized by primary process
1566                  */
1567                 if (eth_dev->data->tx_queues) {
1568                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1569                         ixgbe_set_tx_function(eth_dev, txq);
1570                 } else {
1571                         /* Use default TX function if we get here */
1572                         PMD_INIT_LOG(NOTICE,
1573                                      "No TX queues configured yet. Using default TX function.");
1574                 }
1575
1576                 ixgbe_set_rx_function(eth_dev);
1577
1578                 return 0;
1579         }
1580
1581         rte_atomic32_clear(&ad->link_thread_running);
1582         ixgbevf_parse_devargs(eth_dev->data->dev_private,
1583                               pci_dev->device.devargs);
1584
1585         rte_eth_copy_pci_info(eth_dev, pci_dev);
1586         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1587
1588         hw->device_id = pci_dev->id.device_id;
1589         hw->vendor_id = pci_dev->id.vendor_id;
1590         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1591
1592         /* initialize the vfta */
1593         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1594
1595         /* initialize the hw strip bitmap*/
1596         memset(hwstrip, 0, sizeof(*hwstrip));
1597
1598         /* Initialize the shared code (base driver) */
1599         diag = ixgbe_init_shared_code(hw);
1600         if (diag != IXGBE_SUCCESS) {
1601                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1602                 return -EIO;
1603         }
1604
1605         /* init_mailbox_params */
1606         hw->mbx.ops.init_params(hw);
1607
1608         /* Reset the hw statistics */
1609         ixgbevf_dev_stats_reset(eth_dev);
1610
1611         /* Disable the interrupts for VF */
1612         ixgbevf_intr_disable(eth_dev);
1613
1614         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1615         diag = hw->mac.ops.reset_hw(hw);
1616
1617         /*
1618          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1619          * the underlying PF driver has not assigned a MAC address to the VF.
1620          * In this case, assign a random MAC address.
1621          */
1622         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1623                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1624                 /*
1625                  * This error code will be propagated to the app by
1626                  * rte_eth_dev_reset, so use a public error code rather than
1627                  * the internal-only IXGBE_ERR_RESET_FAILED
1628                  */
1629                 return -EAGAIN;
1630         }
1631
1632         /* negotiate mailbox API version to use with the PF. */
1633         ixgbevf_negotiate_api(hw);
1634
1635         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1636         ixgbevf_get_queues(hw, &tcs, &tc);
1637
1638         /* Allocate memory for storing MAC addresses */
1639         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", RTE_ETHER_ADDR_LEN *
1640                                                hw->mac.num_rar_entries, 0);
1641         if (eth_dev->data->mac_addrs == NULL) {
1642                 PMD_INIT_LOG(ERR,
1643                              "Failed to allocate %u bytes needed to store "
1644                              "MAC addresses",
1645                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1646                 return -ENOMEM;
1647         }
1648
1649         /* Generate a random MAC address, if none was assigned by PF. */
1650         if (rte_is_zero_ether_addr(perm_addr)) {
1651                 generate_random_mac_addr(perm_addr);
1652                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1653                 if (diag) {
1654                         rte_free(eth_dev->data->mac_addrs);
1655                         eth_dev->data->mac_addrs = NULL;
1656                         return diag;
1657                 }
1658                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1659                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1660                              "%02x:%02x:%02x:%02x:%02x:%02x",
1661                              perm_addr->addr_bytes[0],
1662                              perm_addr->addr_bytes[1],
1663                              perm_addr->addr_bytes[2],
1664                              perm_addr->addr_bytes[3],
1665                              perm_addr->addr_bytes[4],
1666                              perm_addr->addr_bytes[5]);
1667         }
1668
1669         /* Copy the permanent MAC address */
1670         rte_ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1671
1672         /* reset the hardware with the new settings */
1673         diag = hw->mac.ops.start_hw(hw);
1674         switch (diag) {
1675         case  0:
1676                 break;
1677
1678         default:
1679                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1680                 return -EIO;
1681         }
1682
1683         rte_intr_callback_register(intr_handle,
1684                                    ixgbevf_dev_interrupt_handler, eth_dev);
1685         rte_intr_enable(intr_handle);
1686         ixgbevf_intr_enable(eth_dev);
1687
1688         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1689                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1690                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1691
1692         return 0;
1693 }
1694
1695 /* Virtual Function device uninit */
1696
1697 static int
1698 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1699 {
1700         PMD_INIT_FUNC_TRACE();
1701
1702         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1703                 return 0;
1704
1705         ixgbevf_dev_close(eth_dev);
1706
1707         return 0;
1708 }
1709
1710 static int
1711 eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1712                 struct rte_pci_device *pci_dev)
1713 {
1714         char name[RTE_ETH_NAME_MAX_LEN];
1715         struct rte_eth_dev *pf_ethdev;
1716         struct rte_eth_devargs eth_da;
1717         int i, retval;
1718
1719         if (pci_dev->device.devargs) {
1720                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
1721                                 &eth_da);
1722                 if (retval)
1723                         return retval;
1724         } else
1725                 memset(&eth_da, 0, sizeof(eth_da));
1726
1727         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
1728                 sizeof(struct ixgbe_adapter),
1729                 eth_dev_pci_specific_init, pci_dev,
1730                 eth_ixgbe_dev_init, NULL);
1731
1732         if (retval || eth_da.nb_representor_ports < 1)
1733                 return retval;
1734
1735         pf_ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1736         if (pf_ethdev == NULL)
1737                 return -ENODEV;
1738
1739         /* probe VF representor ports */
1740         for (i = 0; i < eth_da.nb_representor_ports; i++) {
1741                 struct ixgbe_vf_info *vfinfo;
1742                 struct ixgbe_vf_representor representor;
1743
1744                 vfinfo = *IXGBE_DEV_PRIVATE_TO_P_VFDATA(
1745                         pf_ethdev->data->dev_private);
1746                 if (vfinfo == NULL) {
1747                         PMD_DRV_LOG(ERR,
1748                                 "no virtual functions supported by PF");
1749                         break;
1750                 }
1751
1752                 representor.vf_id = eth_da.representor_ports[i];
1753                 representor.switch_domain_id = vfinfo->switch_domain_id;
1754                 representor.pf_ethdev = pf_ethdev;
1755
1756                 /* representor port net_bdf_port */
1757                 snprintf(name, sizeof(name), "net_%s_representor_%d",
1758                         pci_dev->device.name,
1759                         eth_da.representor_ports[i]);
1760
1761                 retval = rte_eth_dev_create(&pci_dev->device, name,
1762                         sizeof(struct ixgbe_vf_representor), NULL, NULL,
1763                         ixgbe_vf_representor_init, &representor);
1764
1765                 if (retval)
1766                         PMD_DRV_LOG(ERR, "failed to create ixgbe vf "
1767                                 "representor %s.", name);
1768         }
1769
1770         return 0;
1771 }
1772
1773 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1774 {
1775         struct rte_eth_dev *ethdev;
1776
1777         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
1778         if (!ethdev)
1779                 return 0;
1780
1781         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
1782                 return rte_eth_dev_pci_generic_remove(pci_dev,
1783                                         ixgbe_vf_representor_uninit);
1784         else
1785                 return rte_eth_dev_pci_generic_remove(pci_dev,
1786                                                 eth_ixgbe_dev_uninit);
1787 }
1788
1789 static struct rte_pci_driver rte_ixgbe_pmd = {
1790         .id_table = pci_id_ixgbe_map,
1791         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1792         .probe = eth_ixgbe_pci_probe,
1793         .remove = eth_ixgbe_pci_remove,
1794 };
1795
1796 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1797         struct rte_pci_device *pci_dev)
1798 {
1799         return rte_eth_dev_pci_generic_probe(pci_dev,
1800                 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1801 }
1802
1803 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1804 {
1805         return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1806 }
1807
1808 /*
1809  * virtual function driver struct
1810  */
1811 static struct rte_pci_driver rte_ixgbevf_pmd = {
1812         .id_table = pci_id_ixgbevf_map,
1813         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1814         .probe = eth_ixgbevf_pci_probe,
1815         .remove = eth_ixgbevf_pci_remove,
1816 };
1817
1818 static int
1819 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1820 {
1821         struct ixgbe_hw *hw =
1822                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         struct ixgbe_vfta *shadow_vfta =
1824                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1825         uint32_t vfta;
1826         uint32_t vid_idx;
1827         uint32_t vid_bit;
1828
1829         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1830         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1831         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1832         if (on)
1833                 vfta |= vid_bit;
1834         else
1835                 vfta &= ~vid_bit;
1836         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1837
1838         /* update local VFTA copy */
1839         shadow_vfta->vfta[vid_idx] = vfta;
1840
1841         return 0;
1842 }
1843
1844 static void
1845 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1846 {
1847         if (on)
1848                 ixgbe_vlan_hw_strip_enable(dev, queue);
1849         else
1850                 ixgbe_vlan_hw_strip_disable(dev, queue);
1851 }
1852
1853 static int
1854 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1855                     enum rte_vlan_type vlan_type,
1856                     uint16_t tpid)
1857 {
1858         struct ixgbe_hw *hw =
1859                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1860         int ret = 0;
1861         uint32_t reg;
1862         uint32_t qinq;
1863
1864         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1865         qinq &= IXGBE_DMATXCTL_GDV;
1866
1867         switch (vlan_type) {
1868         case ETH_VLAN_TYPE_INNER:
1869                 if (qinq) {
1870                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1871                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1872                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1873                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1874                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1875                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1876                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1877                 } else {
1878                         ret = -ENOTSUP;
1879                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1880                                     " by single VLAN");
1881                 }
1882                 break;
1883         case ETH_VLAN_TYPE_OUTER:
1884                 if (qinq) {
1885                         /* Only the high 16-bits is valid */
1886                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1887                                         IXGBE_EXVET_VET_EXT_SHIFT);
1888                 } else {
1889                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1890                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1891                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1892                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1893                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1894                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1895                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1896                 }
1897
1898                 break;
1899         default:
1900                 ret = -EINVAL;
1901                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902                 break;
1903         }
1904
1905         return ret;
1906 }
1907
1908 void
1909 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1910 {
1911         struct ixgbe_hw *hw =
1912                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913         uint32_t vlnctrl;
1914
1915         PMD_INIT_FUNC_TRACE();
1916
1917         /* Filter Table Disable */
1918         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1919         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1920
1921         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1922 }
1923
1924 void
1925 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1926 {
1927         struct ixgbe_hw *hw =
1928                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct ixgbe_vfta *shadow_vfta =
1930                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1931         uint32_t vlnctrl;
1932         uint16_t i;
1933
1934         PMD_INIT_FUNC_TRACE();
1935
1936         /* Filter Table Enable */
1937         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1938         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1939         vlnctrl |= IXGBE_VLNCTRL_VFE;
1940
1941         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1942
1943         /* write whatever is in local vfta copy */
1944         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1945                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1946 }
1947
1948 static void
1949 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1950 {
1951         struct ixgbe_hwstrip *hwstrip =
1952                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1953         struct ixgbe_rx_queue *rxq;
1954
1955         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1956                 return;
1957
1958         if (on)
1959                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1960         else
1961                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1962
1963         if (queue >= dev->data->nb_rx_queues)
1964                 return;
1965
1966         rxq = dev->data->rx_queues[queue];
1967
1968         if (on) {
1969                 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1970                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1971         } else {
1972                 rxq->vlan_flags = PKT_RX_VLAN;
1973                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1974         }
1975 }
1976
1977 static void
1978 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1979 {
1980         struct ixgbe_hw *hw =
1981                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1982         uint32_t ctrl;
1983
1984         PMD_INIT_FUNC_TRACE();
1985
1986         if (hw->mac.type == ixgbe_mac_82598EB) {
1987                 /* No queue level support */
1988                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1989                 return;
1990         }
1991
1992         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1993         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1994         ctrl &= ~IXGBE_RXDCTL_VME;
1995         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1996
1997         /* record those setting for HW strip per queue */
1998         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1999 }
2000
2001 static void
2002 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
2003 {
2004         struct ixgbe_hw *hw =
2005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         uint32_t ctrl;
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         if (hw->mac.type == ixgbe_mac_82598EB) {
2011                 /* No queue level supported */
2012                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2013                 return;
2014         }
2015
2016         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2017         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2018         ctrl |= IXGBE_RXDCTL_VME;
2019         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2020
2021         /* record those setting for HW strip per queue */
2022         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2023 }
2024
2025 static void
2026 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2027 {
2028         struct ixgbe_hw *hw =
2029                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2030         uint32_t ctrl;
2031
2032         PMD_INIT_FUNC_TRACE();
2033
2034         /* DMATXCTRL: Geric Double VLAN Disable */
2035         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2036         ctrl &= ~IXGBE_DMATXCTL_GDV;
2037         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2038
2039         /* CTRL_EXT: Global Double VLAN Disable */
2040         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2041         ctrl &= ~IXGBE_EXTENDED_VLAN;
2042         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2043
2044 }
2045
2046 static void
2047 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2048 {
2049         struct ixgbe_hw *hw =
2050                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051         uint32_t ctrl;
2052
2053         PMD_INIT_FUNC_TRACE();
2054
2055         /* DMATXCTRL: Geric Double VLAN Enable */
2056         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2057         ctrl |= IXGBE_DMATXCTL_GDV;
2058         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2059
2060         /* CTRL_EXT: Global Double VLAN Enable */
2061         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2062         ctrl |= IXGBE_EXTENDED_VLAN;
2063         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2064
2065         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2066         if (hw->mac.type == ixgbe_mac_X550 ||
2067             hw->mac.type == ixgbe_mac_X550EM_x ||
2068             hw->mac.type == ixgbe_mac_X550EM_a) {
2069                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2070                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2071                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2072         }
2073
2074         /*
2075          * VET EXT field in the EXVET register = 0x8100 by default
2076          * So no need to change. Same to VT field of DMATXCTL register
2077          */
2078 }
2079
2080 void
2081 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2082 {
2083         struct ixgbe_hw *hw =
2084                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2086         uint32_t ctrl;
2087         uint16_t i;
2088         struct ixgbe_rx_queue *rxq;
2089         bool on;
2090
2091         PMD_INIT_FUNC_TRACE();
2092
2093         if (hw->mac.type == ixgbe_mac_82598EB) {
2094                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2095                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2096                         ctrl |= IXGBE_VLNCTRL_VME;
2097                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2098                 } else {
2099                         ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2100                         ctrl &= ~IXGBE_VLNCTRL_VME;
2101                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2102                 }
2103         } else {
2104                 /*
2105                  * Other 10G NIC, the VLAN strip can be setup
2106                  * per queue in RXDCTL
2107                  */
2108                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2109                         rxq = dev->data->rx_queues[i];
2110                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2111                         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2112                                 ctrl |= IXGBE_RXDCTL_VME;
2113                                 on = TRUE;
2114                         } else {
2115                                 ctrl &= ~IXGBE_RXDCTL_VME;
2116                                 on = FALSE;
2117                         }
2118                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2119
2120                         /* record those setting for HW strip per queue */
2121                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2122                 }
2123         }
2124 }
2125
2126 static void
2127 ixgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
2128 {
2129         uint16_t i;
2130         struct rte_eth_rxmode *rxmode;
2131         struct ixgbe_rx_queue *rxq;
2132
2133         if (mask & ETH_VLAN_STRIP_MASK) {
2134                 rxmode = &dev->data->dev_conf.rxmode;
2135                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2136                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2137                                 rxq = dev->data->rx_queues[i];
2138                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
2139                         }
2140                 else
2141                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2142                                 rxq = dev->data->rx_queues[i];
2143                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
2144                         }
2145         }
2146 }
2147
2148 static int
2149 ixgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2150 {
2151         struct rte_eth_rxmode *rxmode;
2152         rxmode = &dev->data->dev_conf.rxmode;
2153
2154         if (mask & ETH_VLAN_STRIP_MASK) {
2155                 ixgbe_vlan_hw_strip_config(dev);
2156         }
2157
2158         if (mask & ETH_VLAN_FILTER_MASK) {
2159                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2160                         ixgbe_vlan_hw_filter_enable(dev);
2161                 else
2162                         ixgbe_vlan_hw_filter_disable(dev);
2163         }
2164
2165         if (mask & ETH_VLAN_EXTEND_MASK) {
2166                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2167                         ixgbe_vlan_hw_extend_enable(dev);
2168                 else
2169                         ixgbe_vlan_hw_extend_disable(dev);
2170         }
2171
2172         return 0;
2173 }
2174
2175 static int
2176 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2177 {
2178         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
2179
2180         ixgbe_vlan_offload_config(dev, mask);
2181
2182         return 0;
2183 }
2184
2185 static void
2186 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2187 {
2188         struct ixgbe_hw *hw =
2189                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2191         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2192
2193         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2194         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2195 }
2196
2197 static int
2198 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2199 {
2200         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201
2202         switch (nb_rx_q) {
2203         case 1:
2204         case 2:
2205                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2206                 break;
2207         case 4:
2208                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2209                 break;
2210         default:
2211                 return -EINVAL;
2212         }
2213
2214         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2215                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2216         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2217                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2218         return 0;
2219 }
2220
2221 static int
2222 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2223 {
2224         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2225         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2226         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2227         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2228
2229         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2230                 /* check multi-queue mode */
2231                 switch (dev_conf->rxmode.mq_mode) {
2232                 case ETH_MQ_RX_VMDQ_DCB:
2233                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2234                         break;
2235                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2236                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2237                         PMD_INIT_LOG(ERR, "SRIOV active,"
2238                                         " unsupported mq_mode rx %d.",
2239                                         dev_conf->rxmode.mq_mode);
2240                         return -EINVAL;
2241                 case ETH_MQ_RX_RSS:
2242                 case ETH_MQ_RX_VMDQ_RSS:
2243                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2244                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2245                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2246                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2247                                                 " invalid queue number"
2248                                                 " for VMDQ RSS, allowed"
2249                                                 " value are 1, 2 or 4.");
2250                                         return -EINVAL;
2251                                 }
2252                         break;
2253                 case ETH_MQ_RX_VMDQ_ONLY:
2254                 case ETH_MQ_RX_NONE:
2255                         /* if nothing mq mode configure, use default scheme */
2256                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2257                         break;
2258                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2259                         /* SRIOV only works in VMDq enable mode */
2260                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2261                                         " wrong mq_mode rx %d.",
2262                                         dev_conf->rxmode.mq_mode);
2263                         return -EINVAL;
2264                 }
2265
2266                 switch (dev_conf->txmode.mq_mode) {
2267                 case ETH_MQ_TX_VMDQ_DCB:
2268                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2269                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2270                         break;
2271                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2272                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2273                         break;
2274                 }
2275
2276                 /* check valid queue number */
2277                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2278                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2279                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2280                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2281                                         " must be less than or equal to %d.",
2282                                         nb_rx_q, nb_tx_q,
2283                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2284                         return -EINVAL;
2285                 }
2286         } else {
2287                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2288                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2289                                           " not supported.");
2290                         return -EINVAL;
2291                 }
2292                 /* check configuration for vmdb+dcb mode */
2293                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2294                         const struct rte_eth_vmdq_dcb_conf *conf;
2295
2296                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2297                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2298                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2299                                 return -EINVAL;
2300                         }
2301                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2302                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2303                                conf->nb_queue_pools == ETH_32_POOLS)) {
2304                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2305                                                 " nb_queue_pools must be %d or %d.",
2306                                                 ETH_16_POOLS, ETH_32_POOLS);
2307                                 return -EINVAL;
2308                         }
2309                 }
2310                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2311                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2312
2313                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2314                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2315                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2316                                 return -EINVAL;
2317                         }
2318                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2319                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2320                                conf->nb_queue_pools == ETH_32_POOLS)) {
2321                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2322                                                 " nb_queue_pools != %d and"
2323                                                 " nb_queue_pools != %d.",
2324                                                 ETH_16_POOLS, ETH_32_POOLS);
2325                                 return -EINVAL;
2326                         }
2327                 }
2328
2329                 /* For DCB mode check our configuration before we go further */
2330                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2331                         const struct rte_eth_dcb_rx_conf *conf;
2332
2333                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2334                         if (!(conf->nb_tcs == ETH_4_TCS ||
2335                                conf->nb_tcs == ETH_8_TCS)) {
2336                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2337                                                 " and nb_tcs != %d.",
2338                                                 ETH_4_TCS, ETH_8_TCS);
2339                                 return -EINVAL;
2340                         }
2341                 }
2342
2343                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2344                         const struct rte_eth_dcb_tx_conf *conf;
2345
2346                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2347                         if (!(conf->nb_tcs == ETH_4_TCS ||
2348                                conf->nb_tcs == ETH_8_TCS)) {
2349                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2350                                                 " and nb_tcs != %d.",
2351                                                 ETH_4_TCS, ETH_8_TCS);
2352                                 return -EINVAL;
2353                         }
2354                 }
2355
2356                 /*
2357                  * When DCB/VT is off, maximum number of queues changes,
2358                  * except for 82598EB, which remains constant.
2359                  */
2360                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2361                                 hw->mac.type != ixgbe_mac_82598EB) {
2362                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2363                                 PMD_INIT_LOG(ERR,
2364                                              "Neither VT nor DCB are enabled, "
2365                                              "nb_tx_q > %d.",
2366                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2367                                 return -EINVAL;
2368                         }
2369                 }
2370         }
2371         return 0;
2372 }
2373
2374 static int
2375 ixgbe_dev_configure(struct rte_eth_dev *dev)
2376 {
2377         struct ixgbe_interrupt *intr =
2378                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2379         struct ixgbe_adapter *adapter = dev->data->dev_private;
2380         int ret;
2381
2382         PMD_INIT_FUNC_TRACE();
2383
2384         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
2385                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
2386
2387         /* multipe queue mode checking */
2388         ret  = ixgbe_check_mq_mode(dev);
2389         if (ret != 0) {
2390                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2391                             ret);
2392                 return ret;
2393         }
2394
2395         /* set flag to update link status after init */
2396         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2397
2398         /*
2399          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2400          * allocation or vector Rx preconditions we will reset it.
2401          */
2402         adapter->rx_bulk_alloc_allowed = true;
2403         adapter->rx_vec_allowed = true;
2404
2405         return 0;
2406 }
2407
2408 static void
2409 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2410 {
2411         struct ixgbe_hw *hw =
2412                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2413         struct ixgbe_interrupt *intr =
2414                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2415         uint32_t gpie;
2416
2417         /* only set up it on X550EM_X */
2418         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2419                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2420                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2421                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2422                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2423                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2424         }
2425 }
2426
2427 int
2428 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2429                         uint16_t tx_rate, uint64_t q_msk)
2430 {
2431         struct ixgbe_hw *hw;
2432         struct ixgbe_vf_info *vfinfo;
2433         struct rte_eth_link link;
2434         uint8_t  nb_q_per_pool;
2435         uint32_t queue_stride;
2436         uint32_t queue_idx, idx = 0, vf_idx;
2437         uint32_t queue_end;
2438         uint16_t total_rate = 0;
2439         struct rte_pci_device *pci_dev;
2440         int ret;
2441
2442         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2443         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
2444         if (ret < 0)
2445                 return ret;
2446
2447         if (vf >= pci_dev->max_vfs)
2448                 return -EINVAL;
2449
2450         if (tx_rate > link.link_speed)
2451                 return -EINVAL;
2452
2453         if (q_msk == 0)
2454                 return 0;
2455
2456         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2458         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2459         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2460         queue_idx = vf * queue_stride;
2461         queue_end = queue_idx + nb_q_per_pool - 1;
2462         if (queue_end >= hw->mac.max_tx_queues)
2463                 return -EINVAL;
2464
2465         if (vfinfo) {
2466                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2467                         if (vf_idx == vf)
2468                                 continue;
2469                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2470                                 idx++)
2471                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
2472                 }
2473         } else {
2474                 return -EINVAL;
2475         }
2476
2477         /* Store tx_rate for this vf. */
2478         for (idx = 0; idx < nb_q_per_pool; idx++) {
2479                 if (((uint64_t)0x1 << idx) & q_msk) {
2480                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
2481                                 vfinfo[vf].tx_rate[idx] = tx_rate;
2482                         total_rate += tx_rate;
2483                 }
2484         }
2485
2486         if (total_rate > dev->data->dev_link.link_speed) {
2487                 /* Reset stored TX rate of the VF if it causes exceed
2488                  * link speed.
2489                  */
2490                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2491                 return -EINVAL;
2492         }
2493
2494         /* Set RTTBCNRC of each queue/pool for vf X  */
2495         for (; queue_idx <= queue_end; queue_idx++) {
2496                 if (0x1 & q_msk)
2497                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2498                 q_msk = q_msk >> 1;
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int
2505 ixgbe_flow_ctrl_enable(struct rte_eth_dev *dev, struct ixgbe_hw *hw)
2506 {
2507         struct ixgbe_adapter *adapter = dev->data->dev_private;
2508         int err;
2509         uint32_t mflcn;
2510
2511         ixgbe_setup_fc(hw);
2512
2513         err = ixgbe_fc_enable(hw);
2514
2515         /* Not negotiated is not an error case */
2516         if (err == IXGBE_SUCCESS || err == IXGBE_ERR_FC_NOT_NEGOTIATED) {
2517                 /*
2518                  *check if we want to forward MAC frames - driver doesn't
2519                  *have native capability to do that,
2520                  *so we'll write the registers ourselves
2521                  */
2522
2523                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2524
2525                 /* set or clear MFLCN.PMCF bit depending on configuration */
2526                 if (adapter->mac_ctrl_frame_fwd != 0)
2527                         mflcn |= IXGBE_MFLCN_PMCF;
2528                 else
2529                         mflcn &= ~IXGBE_MFLCN_PMCF;
2530
2531                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2532                 IXGBE_WRITE_FLUSH(hw);
2533
2534                 return 0;
2535         }
2536         return err;
2537 }
2538
2539 /*
2540  * Configure device link speed and setup link.
2541  * It returns 0 on success.
2542  */
2543 static int
2544 ixgbe_dev_start(struct rte_eth_dev *dev)
2545 {
2546         struct ixgbe_hw *hw =
2547                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2548         struct ixgbe_vf_info *vfinfo =
2549                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2551         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2552         uint32_t intr_vector = 0;
2553         int err;
2554         bool link_up = false, negotiate = 0;
2555         uint32_t speed = 0;
2556         uint32_t allowed_speeds = 0;
2557         int mask = 0;
2558         int status;
2559         uint16_t vf, idx;
2560         uint32_t *link_speeds;
2561         struct ixgbe_tm_conf *tm_conf =
2562                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2563         struct ixgbe_macsec_setting *macsec_setting =
2564                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
2565
2566         PMD_INIT_FUNC_TRACE();
2567
2568         /* Stop the link setup handler before resetting the HW. */
2569         ixgbe_dev_wait_setup_link_complete(dev, 0);
2570
2571         /* disable uio/vfio intr/eventfd mapping */
2572         rte_intr_disable(intr_handle);
2573
2574         /* stop adapter */
2575         hw->adapter_stopped = 0;
2576         ixgbe_stop_adapter(hw);
2577
2578         /* reinitialize adapter
2579          * this calls reset and start
2580          */
2581         status = ixgbe_pf_reset_hw(hw);
2582         if (status != 0)
2583                 return -1;
2584         hw->mac.ops.start_hw(hw);
2585         hw->mac.get_link_status = true;
2586
2587         /* configure PF module if SRIOV enabled */
2588         ixgbe_pf_host_configure(dev);
2589
2590         ixgbe_dev_phy_intr_setup(dev);
2591
2592         /* check and configure queue intr-vector mapping */
2593         if ((rte_intr_cap_multiple(intr_handle) ||
2594              !RTE_ETH_DEV_SRIOV(dev).active) &&
2595             dev->data->dev_conf.intr_conf.rxq != 0) {
2596                 intr_vector = dev->data->nb_rx_queues;
2597                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2598                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2599                                         IXGBE_MAX_INTR_QUEUE_NUM);
2600                         return -ENOTSUP;
2601                 }
2602                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2603                         return -1;
2604         }
2605
2606         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2607                 intr_handle->intr_vec =
2608                         rte_zmalloc("intr_vec",
2609                                     dev->data->nb_rx_queues * sizeof(int), 0);
2610                 if (intr_handle->intr_vec == NULL) {
2611                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2612                                      " intr_vec", dev->data->nb_rx_queues);
2613                         return -ENOMEM;
2614                 }
2615         }
2616
2617         /* confiugre msix for sleep until rx interrupt */
2618         ixgbe_configure_msix(dev);
2619
2620         /* initialize transmission unit */
2621         ixgbe_dev_tx_init(dev);
2622
2623         /* This can fail when allocating mbufs for descriptor rings */
2624         err = ixgbe_dev_rx_init(dev);
2625         if (err) {
2626                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2627                 goto error;
2628         }
2629
2630         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2631                 ETH_VLAN_EXTEND_MASK;
2632         err = ixgbe_vlan_offload_config(dev, mask);
2633         if (err) {
2634                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2635                 goto error;
2636         }
2637
2638         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2639                 /* Enable vlan filtering for VMDq */
2640                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2641         }
2642
2643         /* Configure DCB hw */
2644         ixgbe_configure_dcb(dev);
2645
2646         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2647                 err = ixgbe_fdir_configure(dev);
2648                 if (err)
2649                         goto error;
2650         }
2651
2652         /* Restore vf rate limit */
2653         if (vfinfo != NULL) {
2654                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2655                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2656                                 if (vfinfo[vf].tx_rate[idx] != 0)
2657                                         ixgbe_set_vf_rate_limit(
2658                                                 dev, vf,
2659                                                 vfinfo[vf].tx_rate[idx],
2660                                                 1 << idx);
2661         }
2662
2663         ixgbe_restore_statistics_mapping(dev);
2664
2665         err = ixgbe_flow_ctrl_enable(dev, hw);
2666         if (err < 0) {
2667                 PMD_INIT_LOG(ERR, "enable flow ctrl err");
2668                 goto error;
2669         }
2670
2671         err = ixgbe_dev_rxtx_start(dev);
2672         if (err < 0) {
2673                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2674                 goto error;
2675         }
2676
2677         /* Skip link setup if loopback mode is enabled. */
2678         if (dev->data->dev_conf.lpbk_mode != 0) {
2679                 err = ixgbe_check_supported_loopback_mode(dev);
2680                 if (err < 0) {
2681                         PMD_INIT_LOG(ERR, "Unsupported loopback mode");
2682                         goto error;
2683                 } else {
2684                         goto skip_link_setup;
2685                 }
2686         }
2687
2688         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2689                 err = hw->mac.ops.setup_sfp(hw);
2690                 if (err)
2691                         goto error;
2692         }
2693
2694         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2695                 /* Turn on the copper */
2696                 ixgbe_set_phy_power(hw, true);
2697         } else {
2698                 /* Turn on the laser */
2699                 ixgbe_enable_tx_laser(hw);
2700         }
2701
2702         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2703         if (err)
2704                 goto error;
2705         dev->data->dev_link.link_status = link_up;
2706
2707         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2708         if (err)
2709                 goto error;
2710
2711         switch (hw->mac.type) {
2712         case ixgbe_mac_X550:
2713         case ixgbe_mac_X550EM_x:
2714         case ixgbe_mac_X550EM_a:
2715                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2716                         ETH_LINK_SPEED_2_5G |  ETH_LINK_SPEED_5G |
2717                         ETH_LINK_SPEED_10G;
2718                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
2719                                 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
2720                         allowed_speeds = ETH_LINK_SPEED_10M |
2721                                 ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
2722                 break;
2723         default:
2724                 allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2725                         ETH_LINK_SPEED_10G;
2726         }
2727
2728         link_speeds = &dev->data->dev_conf.link_speeds;
2729
2730         /* Ignore autoneg flag bit and check the validity of
2731          * link_speed
2732          */
2733         if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
2734                 PMD_INIT_LOG(ERR, "Invalid link setting");
2735                 goto error;
2736         }
2737
2738         speed = 0x0;
2739         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2740                 switch (hw->mac.type) {
2741                 case ixgbe_mac_82598EB:
2742                         speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2743                         break;
2744                 case ixgbe_mac_82599EB:
2745                 case ixgbe_mac_X540:
2746                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2747                         break;
2748                 case ixgbe_mac_X550:
2749                 case ixgbe_mac_X550EM_x:
2750                 case ixgbe_mac_X550EM_a:
2751                         speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2752                         break;
2753                 default:
2754                         speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2755                 }
2756         } else {
2757                 if (*link_speeds & ETH_LINK_SPEED_10G)
2758                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2759                 if (*link_speeds & ETH_LINK_SPEED_5G)
2760                         speed |= IXGBE_LINK_SPEED_5GB_FULL;
2761                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
2762                         speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
2763                 if (*link_speeds & ETH_LINK_SPEED_1G)
2764                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2765                 if (*link_speeds & ETH_LINK_SPEED_100M)
2766                         speed |= IXGBE_LINK_SPEED_100_FULL;
2767                 if (*link_speeds & ETH_LINK_SPEED_10M)
2768                         speed |= IXGBE_LINK_SPEED_10_FULL;
2769         }
2770
2771         err = ixgbe_setup_link(hw, speed, link_up);
2772         if (err)
2773                 goto error;
2774
2775 skip_link_setup:
2776
2777         if (rte_intr_allow_others(intr_handle)) {
2778                 /* check if lsc interrupt is enabled */
2779                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2780                         ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2781                 else
2782                         ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2783                 ixgbe_dev_macsec_interrupt_setup(dev);
2784         } else {
2785                 rte_intr_callback_unregister(intr_handle,
2786                                              ixgbe_dev_interrupt_handler, dev);
2787                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2788                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2789                                      " no intr multiplex");
2790         }
2791
2792         /* check if rxq interrupt is enabled */
2793         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2794             rte_intr_dp_is_en(intr_handle))
2795                 ixgbe_dev_rxq_interrupt_setup(dev);
2796
2797         /* enable uio/vfio intr/eventfd mapping */
2798         rte_intr_enable(intr_handle);
2799
2800         /* resume enabled intr since hw reset */
2801         ixgbe_enable_intr(dev);
2802         ixgbe_l2_tunnel_conf(dev);
2803         ixgbe_filter_restore(dev);
2804
2805         if (tm_conf->root && !tm_conf->committed)
2806                 PMD_DRV_LOG(WARNING,
2807                             "please call hierarchy_commit() "
2808                             "before starting the port");
2809
2810         /* wait for the controller to acquire link */
2811         err = ixgbe_wait_for_link_up(hw);
2812         if (err)
2813                 goto error;
2814
2815         /*
2816          * Update link status right before return, because it may
2817          * start link configuration process in a separate thread.
2818          */
2819         ixgbe_dev_link_update(dev, 0);
2820
2821         /* setup the macsec setting register */
2822         if (macsec_setting->offload_en)
2823                 ixgbe_dev_macsec_register_enable(dev, macsec_setting);
2824
2825         return 0;
2826
2827 error:
2828         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2829         ixgbe_dev_clear_queues(dev);
2830         return -EIO;
2831 }
2832
2833 /*
2834  * Stop device: disable rx and tx functions to allow for reconfiguring.
2835  */
2836 static int
2837 ixgbe_dev_stop(struct rte_eth_dev *dev)
2838 {
2839         struct rte_eth_link link;
2840         struct ixgbe_adapter *adapter = dev->data->dev_private;
2841         struct ixgbe_hw *hw =
2842                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2843         struct ixgbe_vf_info *vfinfo =
2844                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2847         int vf;
2848         struct ixgbe_tm_conf *tm_conf =
2849                 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2850
2851         if (hw->adapter_stopped)
2852                 return 0;
2853
2854         PMD_INIT_FUNC_TRACE();
2855
2856         ixgbe_dev_wait_setup_link_complete(dev, 0);
2857
2858         /* disable interrupts */
2859         ixgbe_disable_intr(hw);
2860
2861         /* reset the NIC */
2862         ixgbe_pf_reset_hw(hw);
2863         hw->adapter_stopped = 0;
2864
2865         /* stop adapter */
2866         ixgbe_stop_adapter(hw);
2867
2868         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2869                 vfinfo[vf].clear_to_send = false;
2870
2871         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2872                 /* Turn off the copper */
2873                 ixgbe_set_phy_power(hw, false);
2874         } else {
2875                 /* Turn off the laser */
2876                 ixgbe_disable_tx_laser(hw);
2877         }
2878
2879         ixgbe_dev_clear_queues(dev);
2880
2881         /* Clear stored conf */
2882         dev->data->scattered_rx = 0;
2883         dev->data->lro = 0;
2884
2885         /* Clear recorded link status */
2886         memset(&link, 0, sizeof(link));
2887         rte_eth_linkstatus_set(dev, &link);
2888
2889         if (!rte_intr_allow_others(intr_handle))
2890                 /* resume to the default handler */
2891                 rte_intr_callback_register(intr_handle,
2892                                            ixgbe_dev_interrupt_handler,
2893                                            (void *)dev);
2894
2895         /* Clean datapath event and queue/vec mapping */
2896         rte_intr_efd_disable(intr_handle);
2897         if (intr_handle->intr_vec != NULL) {
2898                 rte_free(intr_handle->intr_vec);
2899                 intr_handle->intr_vec = NULL;
2900         }
2901
2902         /* reset hierarchy commit */
2903         tm_conf->committed = false;
2904
2905         adapter->rss_reta_updated = 0;
2906
2907         hw->adapter_stopped = true;
2908         dev->data->dev_started = 0;
2909
2910         return 0;
2911 }
2912
2913 /*
2914  * Set device link up: enable tx.
2915  */
2916 static int
2917 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2918 {
2919         struct ixgbe_hw *hw =
2920                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2921         if (hw->mac.type == ixgbe_mac_82599EB) {
2922 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2923                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2924                         /* Not suported in bypass mode */
2925                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2926                                      "by device id 0x%x", hw->device_id);
2927                         return -ENOTSUP;
2928                 }
2929 #endif
2930         }
2931
2932         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2933                 /* Turn on the copper */
2934                 ixgbe_set_phy_power(hw, true);
2935         } else {
2936                 /* Turn on the laser */
2937                 ixgbe_enable_tx_laser(hw);
2938                 ixgbe_dev_link_update(dev, 0);
2939         }
2940
2941         return 0;
2942 }
2943
2944 /*
2945  * Set device link down: disable tx.
2946  */
2947 static int
2948 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2949 {
2950         struct ixgbe_hw *hw =
2951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2952         if (hw->mac.type == ixgbe_mac_82599EB) {
2953 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2954                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2955                         /* Not suported in bypass mode */
2956                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2957                                      "by device id 0x%x", hw->device_id);
2958                         return -ENOTSUP;
2959                 }
2960 #endif
2961         }
2962
2963         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2964                 /* Turn off the copper */
2965                 ixgbe_set_phy_power(hw, false);
2966         } else {
2967                 /* Turn off the laser */
2968                 ixgbe_disable_tx_laser(hw);
2969                 ixgbe_dev_link_update(dev, 0);
2970         }
2971
2972         return 0;
2973 }
2974
2975 /*
2976  * Reset and stop device.
2977  */
2978 static int
2979 ixgbe_dev_close(struct rte_eth_dev *dev)
2980 {
2981         struct ixgbe_hw *hw =
2982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2984         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2985         int retries = 0;
2986         int ret;
2987
2988         PMD_INIT_FUNC_TRACE();
2989         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2990                 return 0;
2991
2992         ixgbe_pf_reset_hw(hw);
2993
2994         ret = ixgbe_dev_stop(dev);
2995
2996         ixgbe_dev_free_queues(dev);
2997
2998         ixgbe_disable_pcie_master(hw);
2999
3000         /* reprogram the RAR[0] in case user changed it. */
3001         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3002
3003         /* Unlock any pending hardware semaphore */
3004         ixgbe_swfw_lock_reset(hw);
3005
3006         /* disable uio intr before callback unregister */
3007         rte_intr_disable(intr_handle);
3008
3009         do {
3010                 ret = rte_intr_callback_unregister(intr_handle,
3011                                 ixgbe_dev_interrupt_handler, dev);
3012                 if (ret >= 0 || ret == -ENOENT) {
3013                         break;
3014                 } else if (ret != -EAGAIN) {
3015                         PMD_INIT_LOG(ERR,
3016                                 "intr callback unregister failed: %d",
3017                                 ret);
3018                 }
3019                 rte_delay_ms(100);
3020         } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
3021
3022         /* cancel the delay handler before remove dev */
3023         rte_eal_alarm_cancel(ixgbe_dev_interrupt_delayed_handler, dev);
3024
3025         /* uninitialize PF if max_vfs not zero */
3026         ixgbe_pf_host_uninit(dev);
3027
3028         /* remove all the fdir filters & hash */
3029         ixgbe_fdir_filter_uninit(dev);
3030
3031         /* remove all the L2 tunnel filters & hash */
3032         ixgbe_l2_tn_filter_uninit(dev);
3033
3034         /* Remove all ntuple filters of the device */
3035         ixgbe_ntuple_filter_uninit(dev);
3036
3037         /* clear all the filters list */
3038         ixgbe_filterlist_flush();
3039
3040         /* Remove all Traffic Manager configuration */
3041         ixgbe_tm_conf_uninit(dev);
3042
3043 #ifdef RTE_LIB_SECURITY
3044         rte_free(dev->security_ctx);
3045 #endif
3046
3047         return ret;
3048 }
3049
3050 /*
3051  * Reset PF device.
3052  */
3053 static int
3054 ixgbe_dev_reset(struct rte_eth_dev *dev)
3055 {
3056         int ret;
3057
3058         /* When a DPDK PMD PF begin to reset PF port, it should notify all
3059          * its VF to make them align with it. The detailed notification
3060          * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
3061          * To avoid unexpected behavior in VF, currently reset of PF with
3062          * SR-IOV activation is not supported. It might be supported later.
3063          */
3064         if (dev->data->sriov.active)
3065                 return -ENOTSUP;
3066
3067         ret = eth_ixgbe_dev_uninit(dev);
3068         if (ret)
3069                 return ret;
3070
3071         ret = eth_ixgbe_dev_init(dev, NULL);
3072
3073         return ret;
3074 }
3075
3076 static void
3077 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
3078                            struct ixgbe_hw_stats *hw_stats,
3079                            struct ixgbe_macsec_stats *macsec_stats,
3080                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
3081                            uint64_t *total_qprc, uint64_t *total_qprdc)
3082 {
3083         uint32_t bprc, lxon, lxoff, total;
3084         uint32_t delta_gprc = 0;
3085         unsigned i;
3086         /* Workaround for RX byte count not including CRC bytes when CRC
3087          * strip is enabled. CRC bytes are removed from counters when crc_strip
3088          * is disabled.
3089          */
3090         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
3091                         IXGBE_HLREG0_RXCRCSTRP);
3092
3093         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3094         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
3095         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
3096         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
3097
3098         for (i = 0; i < 8; i++) {
3099                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3100
3101                 /* global total per queue */
3102                 hw_stats->mpc[i] += mp;
3103                 /* Running comprehensive total for stats display */
3104                 *total_missed_rx += hw_stats->mpc[i];
3105                 if (hw->mac.type == ixgbe_mac_82598EB) {
3106                         hw_stats->rnbc[i] +=
3107                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3108                         hw_stats->pxonrxc[i] +=
3109                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
3110                         hw_stats->pxoffrxc[i] +=
3111                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
3112                 } else {
3113                         hw_stats->pxonrxc[i] +=
3114                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
3115                         hw_stats->pxoffrxc[i] +=
3116                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
3117                         hw_stats->pxon2offc[i] +=
3118                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
3119                 }
3120                 hw_stats->pxontxc[i] +=
3121                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
3122                 hw_stats->pxofftxc[i] +=
3123                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
3124         }
3125         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3126                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
3127                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
3128                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
3129
3130                 delta_gprc += delta_qprc;
3131
3132                 hw_stats->qprc[i] += delta_qprc;
3133                 hw_stats->qptc[i] += delta_qptc;
3134
3135                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
3136                 hw_stats->qbrc[i] +=
3137                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
3138                 if (crc_strip == 0)
3139                         hw_stats->qbrc[i] -= delta_qprc * RTE_ETHER_CRC_LEN;
3140
3141                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
3142                 hw_stats->qbtc[i] +=
3143                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
3144
3145                 hw_stats->qprdc[i] += delta_qprdc;
3146                 *total_qprdc += hw_stats->qprdc[i];
3147
3148                 *total_qprc += hw_stats->qprc[i];
3149                 *total_qbrc += hw_stats->qbrc[i];
3150         }
3151         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
3152         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
3153         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3154
3155         /*
3156          * An errata states that gprc actually counts good + missed packets:
3157          * Workaround to set gprc to summated queue packet receives
3158          */
3159         hw_stats->gprc = *total_qprc;
3160
3161         if (hw->mac.type != ixgbe_mac_82598EB) {
3162                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
3163                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
3164                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
3165                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
3166                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
3167                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
3168                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
3169                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
3170         } else {
3171                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3172                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3173                 /* 82598 only has a counter in the high register */
3174                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3175                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3176                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3177         }
3178         uint64_t old_tpr = hw_stats->tpr;
3179
3180         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3181         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
3182
3183         if (crc_strip == 0)
3184                 hw_stats->gorc -= delta_gprc * RTE_ETHER_CRC_LEN;
3185
3186         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
3187         hw_stats->gptc += delta_gptc;
3188         hw_stats->gotc -= delta_gptc * RTE_ETHER_CRC_LEN;
3189         hw_stats->tor -= (hw_stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
3190
3191         /*
3192          * Workaround: mprc hardware is incorrectly counting
3193          * broadcasts, so for now we subtract those.
3194          */
3195         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3196         hw_stats->bprc += bprc;
3197         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3198         if (hw->mac.type == ixgbe_mac_82598EB)
3199                 hw_stats->mprc -= bprc;
3200
3201         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3202         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3203         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3204         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3205         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3206         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3207
3208         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3209         hw_stats->lxontxc += lxon;
3210         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3211         hw_stats->lxofftxc += lxoff;
3212         total = lxon + lxoff;
3213
3214         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3215         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3216         hw_stats->gptc -= total;
3217         hw_stats->mptc -= total;
3218         hw_stats->ptc64 -= total;
3219         hw_stats->gotc -= total * RTE_ETHER_MIN_LEN;
3220
3221         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3222         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3223         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3224         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3225         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3226         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3227         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3228         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3229         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3230         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3231         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3232         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3233         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3234         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3235         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3236         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3237         /* Only read FCOE on 82599 */
3238         if (hw->mac.type != ixgbe_mac_82598EB) {
3239                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3240                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3241                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3242                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3243                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3244         }
3245
3246         /* Flow Director Stats registers */
3247         if (hw->mac.type != ixgbe_mac_82598EB) {
3248                 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3249                 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3250                 hw_stats->fdirustat_add += IXGBE_READ_REG(hw,
3251                                         IXGBE_FDIRUSTAT) & 0xFFFF;
3252                 hw_stats->fdirustat_remove += (IXGBE_READ_REG(hw,
3253                                         IXGBE_FDIRUSTAT) >> 16) & 0xFFFF;
3254                 hw_stats->fdirfstat_fadd += IXGBE_READ_REG(hw,
3255                                         IXGBE_FDIRFSTAT) & 0xFFFF;
3256                 hw_stats->fdirfstat_fremove += (IXGBE_READ_REG(hw,
3257                                         IXGBE_FDIRFSTAT) >> 16) & 0xFFFF;
3258         }
3259         /* MACsec Stats registers */
3260         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3261         macsec_stats->out_pkts_encrypted +=
3262                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3263         macsec_stats->out_pkts_protected +=
3264                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3265         macsec_stats->out_octets_encrypted +=
3266                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3267         macsec_stats->out_octets_protected +=
3268                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3269         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3270         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3271         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3272         macsec_stats->in_pkts_unknownsci +=
3273                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3274         macsec_stats->in_octets_decrypted +=
3275                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3276         macsec_stats->in_octets_validated +=
3277                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3278         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3279         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3280         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3281         for (i = 0; i < 2; i++) {
3282                 macsec_stats->in_pkts_ok +=
3283                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3284                 macsec_stats->in_pkts_invalid +=
3285                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3286                 macsec_stats->in_pkts_notvalid +=
3287                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3288         }
3289         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3290         macsec_stats->in_pkts_notusingsa +=
3291                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3292 }
3293
3294 /*
3295  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3296  */
3297 static int
3298 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3299 {
3300         struct ixgbe_hw *hw =
3301                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3302         struct ixgbe_hw_stats *hw_stats =
3303                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3304         struct ixgbe_macsec_stats *macsec_stats =
3305                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3306                                 dev->data->dev_private);
3307         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3308         unsigned i;
3309
3310         total_missed_rx = 0;
3311         total_qbrc = 0;
3312         total_qprc = 0;
3313         total_qprdc = 0;
3314
3315         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3316                         &total_qbrc, &total_qprc, &total_qprdc);
3317
3318         if (stats == NULL)
3319                 return -EINVAL;
3320
3321         /* Fill out the rte_eth_stats statistics structure */
3322         stats->ipackets = total_qprc;
3323         stats->ibytes = total_qbrc;
3324         stats->opackets = hw_stats->gptc;
3325         stats->obytes = hw_stats->gotc;
3326
3327         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3328                 stats->q_ipackets[i] = hw_stats->qprc[i];
3329                 stats->q_opackets[i] = hw_stats->qptc[i];
3330                 stats->q_ibytes[i] = hw_stats->qbrc[i];
3331                 stats->q_obytes[i] = hw_stats->qbtc[i];
3332                 stats->q_errors[i] = hw_stats->qprdc[i];
3333         }
3334
3335         /* Rx Errors */
3336         stats->imissed  = total_missed_rx;
3337         stats->ierrors  = hw_stats->crcerrs +
3338                           hw_stats->mspdc +
3339                           hw_stats->rlec +
3340                           hw_stats->ruc +
3341                           hw_stats->roc +
3342                           hw_stats->illerrc +
3343                           hw_stats->errbc +
3344                           hw_stats->rfc +
3345                           hw_stats->fccrc +
3346                           hw_stats->fclast;
3347
3348         /* Tx Errors */
3349         stats->oerrors  = 0;
3350         return 0;
3351 }
3352
3353 static int
3354 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3355 {
3356         struct ixgbe_hw_stats *stats =
3357                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3358
3359         /* HW registers are cleared on read */
3360         ixgbe_dev_stats_get(dev, NULL);
3361
3362         /* Reset software totals */
3363         memset(stats, 0, sizeof(*stats));
3364
3365         return 0;
3366 }
3367
3368 /* This function calculates the number of xstats based on the current config */
3369 static unsigned
3370 ixgbe_xstats_calc_num(void) {
3371         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3372                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3373                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3374 }
3375
3376 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3377         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3378 {
3379         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3380         unsigned stat, i, count;
3381
3382         if (xstats_names != NULL) {
3383                 count = 0;
3384
3385                 /* Note: limit >= cnt_stats checked upstream
3386                  * in rte_eth_xstats_names()
3387                  */
3388
3389                 /* Extended stats from ixgbe_hw_stats */
3390                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3391                         strlcpy(xstats_names[count].name,
3392                                 rte_ixgbe_stats_strings[i].name,
3393                                 sizeof(xstats_names[count].name));
3394                         count++;
3395                 }
3396
3397                 /* MACsec Stats */
3398                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3399                         strlcpy(xstats_names[count].name,
3400                                 rte_ixgbe_macsec_strings[i].name,
3401                                 sizeof(xstats_names[count].name));
3402                         count++;
3403                 }
3404
3405                 /* RX Priority Stats */
3406                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3407                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3408                                 snprintf(xstats_names[count].name,
3409                                         sizeof(xstats_names[count].name),
3410                                         "rx_priority%u_%s", i,
3411                                         rte_ixgbe_rxq_strings[stat].name);
3412                                 count++;
3413                         }
3414                 }
3415
3416                 /* TX Priority Stats */
3417                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3418                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3419                                 snprintf(xstats_names[count].name,
3420                                         sizeof(xstats_names[count].name),
3421                                         "tx_priority%u_%s", i,
3422                                         rte_ixgbe_txq_strings[stat].name);
3423                                 count++;
3424                         }
3425                 }
3426         }
3427         return cnt_stats;
3428 }
3429
3430 static int ixgbe_dev_xstats_get_names_by_id(
3431         struct rte_eth_dev *dev,
3432         struct rte_eth_xstat_name *xstats_names,
3433         const uint64_t *ids,
3434         unsigned int limit)
3435 {
3436         if (!ids) {
3437                 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3438                 unsigned int stat, i, count;
3439
3440                 if (xstats_names != NULL) {
3441                         count = 0;
3442
3443                         /* Note: limit >= cnt_stats checked upstream
3444                          * in rte_eth_xstats_names()
3445                          */
3446
3447                         /* Extended stats from ixgbe_hw_stats */
3448                         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3449                                 strlcpy(xstats_names[count].name,
3450                                         rte_ixgbe_stats_strings[i].name,
3451                                         sizeof(xstats_names[count].name));
3452                                 count++;
3453                         }
3454
3455                         /* MACsec Stats */
3456                         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3457                                 strlcpy(xstats_names[count].name,
3458                                         rte_ixgbe_macsec_strings[i].name,
3459                                         sizeof(xstats_names[count].name));
3460                                 count++;
3461                         }
3462
3463                         /* RX Priority Stats */
3464                         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3465                                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3466                                         snprintf(xstats_names[count].name,
3467                                             sizeof(xstats_names[count].name),
3468                                             "rx_priority%u_%s", i,
3469                                             rte_ixgbe_rxq_strings[stat].name);
3470                                         count++;
3471                                 }
3472                         }
3473
3474                         /* TX Priority Stats */
3475                         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3476                                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3477                                         snprintf(xstats_names[count].name,
3478                                             sizeof(xstats_names[count].name),
3479                                             "tx_priority%u_%s", i,
3480                                             rte_ixgbe_txq_strings[stat].name);
3481                                         count++;
3482                                 }
3483                         }
3484                 }
3485                 return cnt_stats;
3486         }
3487
3488         uint16_t i;
3489         uint16_t size = ixgbe_xstats_calc_num();
3490         struct rte_eth_xstat_name xstats_names_copy[size];
3491
3492         ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3493                         size);
3494
3495         for (i = 0; i < limit; i++) {
3496                 if (ids[i] >= size) {
3497                         PMD_INIT_LOG(ERR, "id value isn't valid");
3498                         return -1;
3499                 }
3500                 strcpy(xstats_names[i].name,
3501                                 xstats_names_copy[ids[i]].name);
3502         }
3503         return limit;
3504 }
3505
3506 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3507         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3508 {
3509         unsigned i;
3510
3511         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3512                 return -ENOMEM;
3513
3514         if (xstats_names != NULL)
3515                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3516                         strlcpy(xstats_names[i].name,
3517                                 rte_ixgbevf_stats_strings[i].name,
3518                                 sizeof(xstats_names[i].name));
3519         return IXGBEVF_NB_XSTATS;
3520 }
3521
3522 static int
3523 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3524                                          unsigned n)
3525 {
3526         struct ixgbe_hw *hw =
3527                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3528         struct ixgbe_hw_stats *hw_stats =
3529                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3530         struct ixgbe_macsec_stats *macsec_stats =
3531                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3532                                 dev->data->dev_private);
3533         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3534         unsigned i, stat, count = 0;
3535
3536         count = ixgbe_xstats_calc_num();
3537
3538         if (n < count)
3539                 return count;
3540
3541         total_missed_rx = 0;
3542         total_qbrc = 0;
3543         total_qprc = 0;
3544         total_qprdc = 0;
3545
3546         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3547                         &total_qbrc, &total_qprc, &total_qprdc);
3548
3549         /* If this is a reset xstats is NULL, and we have cleared the
3550          * registers by reading them.
3551          */
3552         if (!xstats)
3553                 return 0;
3554
3555         /* Extended stats from ixgbe_hw_stats */
3556         count = 0;
3557         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3558                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3559                                 rte_ixgbe_stats_strings[i].offset);
3560                 xstats[count].id = count;
3561                 count++;
3562         }
3563
3564         /* MACsec Stats */
3565         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3566                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3567                                 rte_ixgbe_macsec_strings[i].offset);
3568                 xstats[count].id = count;
3569                 count++;
3570         }
3571
3572         /* RX Priority Stats */
3573         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3574                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3575                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3576                                         rte_ixgbe_rxq_strings[stat].offset +
3577                                         (sizeof(uint64_t) * i));
3578                         xstats[count].id = count;
3579                         count++;
3580                 }
3581         }
3582
3583         /* TX Priority Stats */
3584         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3585                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3586                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3587                                         rte_ixgbe_txq_strings[stat].offset +
3588                                         (sizeof(uint64_t) * i));
3589                         xstats[count].id = count;
3590                         count++;
3591                 }
3592         }
3593         return count;
3594 }
3595
3596 static int
3597 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3598                 uint64_t *values, unsigned int n)
3599 {
3600         if (!ids) {
3601                 struct ixgbe_hw *hw =
3602                                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603                 struct ixgbe_hw_stats *hw_stats =
3604                                 IXGBE_DEV_PRIVATE_TO_STATS(
3605                                                 dev->data->dev_private);
3606                 struct ixgbe_macsec_stats *macsec_stats =
3607                                 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3608                                         dev->data->dev_private);
3609                 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3610                 unsigned int i, stat, count = 0;
3611
3612                 count = ixgbe_xstats_calc_num();
3613
3614                 if (!ids && n < count)
3615                         return count;
3616
3617                 total_missed_rx = 0;
3618                 total_qbrc = 0;
3619                 total_qprc = 0;
3620                 total_qprdc = 0;
3621
3622                 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3623                                 &total_missed_rx, &total_qbrc, &total_qprc,
3624                                 &total_qprdc);
3625
3626                 /* If this is a reset xstats is NULL, and we have cleared the
3627                  * registers by reading them.
3628                  */
3629                 if (!ids && !values)
3630                         return 0;
3631
3632                 /* Extended stats from ixgbe_hw_stats */
3633                 count = 0;
3634                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3635                         values[count] = *(uint64_t *)(((char *)hw_stats) +
3636                                         rte_ixgbe_stats_strings[i].offset);
3637                         count++;
3638                 }
3639
3640                 /* MACsec Stats */
3641                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3642                         values[count] = *(uint64_t *)(((char *)macsec_stats) +
3643                                         rte_ixgbe_macsec_strings[i].offset);
3644                         count++;
3645                 }
3646
3647                 /* RX Priority Stats */
3648                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3649                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3650                                 values[count] =
3651                                         *(uint64_t *)(((char *)hw_stats) +
3652                                         rte_ixgbe_rxq_strings[stat].offset +
3653                                         (sizeof(uint64_t) * i));
3654                                 count++;
3655                         }
3656                 }
3657
3658                 /* TX Priority Stats */
3659                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3660                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3661                                 values[count] =
3662                                         *(uint64_t *)(((char *)hw_stats) +
3663                                         rte_ixgbe_txq_strings[stat].offset +
3664                                         (sizeof(uint64_t) * i));
3665                                 count++;
3666                         }
3667                 }
3668                 return count;
3669         }
3670
3671         uint16_t i;
3672         uint16_t size = ixgbe_xstats_calc_num();
3673         uint64_t values_copy[size];
3674
3675         ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3676
3677         for (i = 0; i < n; i++) {
3678                 if (ids[i] >= size) {
3679                         PMD_INIT_LOG(ERR, "id value isn't valid");
3680                         return -1;
3681                 }
3682                 values[i] = values_copy[ids[i]];
3683         }
3684         return n;
3685 }
3686
3687 static int
3688 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3689 {
3690         struct ixgbe_hw_stats *stats =
3691                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3692         struct ixgbe_macsec_stats *macsec_stats =
3693                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3694                                 dev->data->dev_private);
3695
3696         unsigned count = ixgbe_xstats_calc_num();
3697
3698         /* HW registers are cleared on read */
3699         ixgbe_dev_xstats_get(dev, NULL, count);
3700
3701         /* Reset software totals */
3702         memset(stats, 0, sizeof(*stats));
3703         memset(macsec_stats, 0, sizeof(*macsec_stats));
3704
3705         return 0;
3706 }
3707
3708 static void
3709 ixgbevf_update_stats(struct rte_eth_dev *dev)
3710 {
3711         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3712         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3713                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3714
3715         /* Good Rx packet, include VF loopback */
3716         UPDATE_VF_STAT(IXGBE_VFGPRC,
3717             hw_stats->last_vfgprc, hw_stats->vfgprc);
3718
3719         /* Good Rx octets, include VF loopback */
3720         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3721             hw_stats->last_vfgorc, hw_stats->vfgorc);
3722
3723         /* Good Tx packet, include VF loopback */
3724         UPDATE_VF_STAT(IXGBE_VFGPTC,
3725             hw_stats->last_vfgptc, hw_stats->vfgptc);
3726
3727         /* Good Tx octets, include VF loopback */
3728         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3729             hw_stats->last_vfgotc, hw_stats->vfgotc);
3730
3731         /* Rx Multicst Packet */
3732         UPDATE_VF_STAT(IXGBE_VFMPRC,
3733             hw_stats->last_vfmprc, hw_stats->vfmprc);
3734 }
3735
3736 static int
3737 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3738                        unsigned n)
3739 {
3740         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3741                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3742         unsigned i;
3743
3744         if (n < IXGBEVF_NB_XSTATS)
3745                 return IXGBEVF_NB_XSTATS;
3746
3747         ixgbevf_update_stats(dev);
3748
3749         if (!xstats)
3750                 return 0;
3751
3752         /* Extended stats */
3753         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3754                 xstats[i].id = i;
3755                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3756                         rte_ixgbevf_stats_strings[i].offset);
3757         }
3758
3759         return IXGBEVF_NB_XSTATS;
3760 }
3761
3762 static int
3763 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3764 {
3765         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3766                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3767
3768         ixgbevf_update_stats(dev);
3769
3770         if (stats == NULL)
3771                 return -EINVAL;
3772
3773         stats->ipackets = hw_stats->vfgprc;
3774         stats->ibytes = hw_stats->vfgorc;
3775         stats->opackets = hw_stats->vfgptc;
3776         stats->obytes = hw_stats->vfgotc;
3777         return 0;
3778 }
3779
3780 static int
3781 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3782 {
3783         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3784                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3785
3786         /* Sync HW register to the last stats */
3787         ixgbevf_dev_stats_get(dev, NULL);
3788
3789         /* reset HW current stats*/
3790         hw_stats->vfgprc = 0;
3791         hw_stats->vfgorc = 0;
3792         hw_stats->vfgptc = 0;
3793         hw_stats->vfgotc = 0;
3794
3795         return 0;
3796 }
3797
3798 static int
3799 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3800 {
3801         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3802         u16 eeprom_verh, eeprom_verl;
3803         u32 etrack_id;
3804         int ret;
3805
3806         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3807         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3808
3809         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3810         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3811
3812         ret += 1; /* add the size of '\0' */
3813         if (fw_size < (u32)ret)
3814                 return ret;
3815         else
3816                 return 0;
3817 }
3818
3819 static int
3820 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3821 {
3822         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3823         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3825
3826         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3827         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3828         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3829                 /*
3830                  * When DCB/VT is off, maximum number of queues changes,
3831                  * except for 82598EB, which remains constant.
3832                  */
3833                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3834                                 hw->mac.type != ixgbe_mac_82598EB)
3835                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3836         }
3837         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3838         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3839         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3840         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3841         dev_info->max_vfs = pci_dev->max_vfs;
3842         if (hw->mac.type == ixgbe_mac_82598EB)
3843                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3844         else
3845                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3846         dev_info->max_mtu =  dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3847         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3848         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3849         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3850         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3851                                      dev_info->rx_queue_offload_capa);
3852         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3853         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3854
3855         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3856                 .rx_thresh = {
3857                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3858                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3859                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3860                 },
3861                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3862                 .rx_drop_en = 0,
3863                 .offloads = 0,
3864         };
3865
3866         dev_info->default_txconf = (struct rte_eth_txconf) {
3867                 .tx_thresh = {
3868                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3869                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3870                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3871                 },
3872                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3873                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3874                 .offloads = 0,
3875         };
3876
3877         dev_info->rx_desc_lim = rx_desc_lim;
3878         dev_info->tx_desc_lim = tx_desc_lim;
3879
3880         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3881         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3882         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3883
3884         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3885         if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T ||
3886                         hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L)
3887                 dev_info->speed_capa = ETH_LINK_SPEED_10M |
3888                         ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G;
3889
3890         if (hw->mac.type == ixgbe_mac_X540 ||
3891             hw->mac.type == ixgbe_mac_X540_vf ||
3892             hw->mac.type == ixgbe_mac_X550 ||
3893             hw->mac.type == ixgbe_mac_X550_vf) {
3894                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3895         }
3896         if (hw->mac.type == ixgbe_mac_X550) {
3897                 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3898                 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3899         }
3900
3901         /* Driver-preferred Rx/Tx parameters */
3902         dev_info->default_rxportconf.burst_size = 32;
3903         dev_info->default_txportconf.burst_size = 32;
3904         dev_info->default_rxportconf.nb_queues = 1;
3905         dev_info->default_txportconf.nb_queues = 1;
3906         dev_info->default_rxportconf.ring_size = 256;
3907         dev_info->default_txportconf.ring_size = 256;
3908
3909         return 0;
3910 }
3911
3912 static const uint32_t *
3913 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3914 {
3915         static const uint32_t ptypes[] = {
3916                 /* For non-vec functions,
3917                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3918                  * for vec functions,
3919                  * refers to _recv_raw_pkts_vec().
3920                  */
3921                 RTE_PTYPE_L2_ETHER,
3922                 RTE_PTYPE_L3_IPV4,
3923                 RTE_PTYPE_L3_IPV4_EXT,
3924                 RTE_PTYPE_L3_IPV6,
3925                 RTE_PTYPE_L3_IPV6_EXT,
3926                 RTE_PTYPE_L4_SCTP,
3927                 RTE_PTYPE_L4_TCP,
3928                 RTE_PTYPE_L4_UDP,
3929                 RTE_PTYPE_TUNNEL_IP,
3930                 RTE_PTYPE_INNER_L3_IPV6,
3931                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3932                 RTE_PTYPE_INNER_L4_TCP,
3933                 RTE_PTYPE_INNER_L4_UDP,
3934                 RTE_PTYPE_UNKNOWN
3935         };
3936
3937         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3938             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3939             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3940             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3941                 return ptypes;
3942
3943 #if defined(RTE_ARCH_X86) || defined(__ARM_NEON)
3944         if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3945             dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3946                 return ptypes;
3947 #endif
3948         return NULL;
3949 }
3950
3951 static int
3952 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3953                      struct rte_eth_dev_info *dev_info)
3954 {
3955         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3956         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957
3958         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3959         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3960         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3961         dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3962         dev_info->max_mtu = dev_info->max_rx_pktlen - IXGBE_ETH_OVERHEAD;
3963         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3964         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3965         dev_info->max_vfs = pci_dev->max_vfs;
3966         if (hw->mac.type == ixgbe_mac_82598EB)
3967                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3968         else
3969                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3970         dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3971         dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3972                                      dev_info->rx_queue_offload_capa);
3973         dev_info->tx_queue_offload_capa = ixgbe_get_tx_queue_offloads(dev);
3974         dev_info->tx_offload_capa = ixgbe_get_tx_port_offloads(dev);
3975         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3976         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3977         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3978
3979         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3980                 .rx_thresh = {
3981                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3982                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3983                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3984                 },
3985                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3986                 .rx_drop_en = 0,
3987                 .offloads = 0,
3988         };
3989
3990         dev_info->default_txconf = (struct rte_eth_txconf) {
3991                 .tx_thresh = {
3992                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3993                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3994                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3995                 },
3996                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3997                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3998                 .offloads = 0,
3999         };
4000
4001         dev_info->rx_desc_lim = rx_desc_lim;
4002         dev_info->tx_desc_lim = tx_desc_lim;
4003
4004         return 0;
4005 }
4006
4007 static int
4008 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4009                    bool *link_up, int wait_to_complete)
4010 {
4011         struct ixgbe_adapter *adapter = container_of(hw,
4012                                                      struct ixgbe_adapter, hw);
4013         struct ixgbe_mbx_info *mbx = &hw->mbx;
4014         struct ixgbe_mac_info *mac = &hw->mac;
4015         uint32_t links_reg, in_msg;
4016         int ret_val = 0;
4017
4018         /* If we were hit with a reset drop the link */
4019         if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
4020                 mac->get_link_status = true;
4021
4022         if (!mac->get_link_status)
4023                 goto out;
4024
4025         /* if link status is down no point in checking to see if pf is up */
4026         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4027         if (!(links_reg & IXGBE_LINKS_UP))
4028                 goto out;
4029
4030         /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
4031          * before the link status is correct
4032          */
4033         if (mac->type == ixgbe_mac_82599_vf && wait_to_complete) {
4034                 int i;
4035
4036                 for (i = 0; i < 5; i++) {
4037                         rte_delay_us(100);
4038                         links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
4039
4040                         if (!(links_reg & IXGBE_LINKS_UP))
4041                                 goto out;
4042                 }
4043         }
4044
4045         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4046         case IXGBE_LINKS_SPEED_10G_82599:
4047                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4048                 if (hw->mac.type >= ixgbe_mac_X550) {
4049                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4050                                 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4051                 }
4052                 break;
4053         case IXGBE_LINKS_SPEED_1G_82599:
4054                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4055                 break;
4056         case IXGBE_LINKS_SPEED_100_82599:
4057                 *speed = IXGBE_LINK_SPEED_100_FULL;
4058                 if (hw->mac.type == ixgbe_mac_X550) {
4059                         if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4060                                 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4061                 }
4062                 break;
4063         case IXGBE_LINKS_SPEED_10_X550EM_A:
4064                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4065                 /* Since Reserved in older MAC's */
4066                 if (hw->mac.type >= ixgbe_mac_X550)
4067                         *speed = IXGBE_LINK_SPEED_10_FULL;
4068                 break;
4069         default:
4070                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4071         }
4072
4073         if (wait_to_complete == 0 && adapter->pflink_fullchk == 0) {
4074                 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
4075                         mac->get_link_status = true;
4076                 else
4077                         mac->get_link_status = false;
4078
4079                 goto out;
4080         }
4081
4082         /* if the read failed it could just be a mailbox collision, best wait
4083          * until we are called again and don't report an error
4084          */
4085         if (mbx->ops.read(hw, &in_msg, 1, 0))
4086                 goto out;
4087
4088         if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
4089                 /* msg is not CTS and is NACK we must have lost CTS status */
4090                 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
4091                         mac->get_link_status = false;
4092                 goto out;
4093         }
4094
4095         /* the pf is talking, if we timed out in the past we reinit */
4096         if (!mbx->timeout) {
4097                 ret_val = -1;
4098                 goto out;
4099         }
4100
4101         /* if we passed all the tests above then the link is up and we no
4102          * longer need to check for link
4103          */
4104         mac->get_link_status = false;
4105
4106 out:
4107         *link_up = !mac->get_link_status;
4108         return ret_val;
4109 }
4110
4111 /*
4112  * If @timeout_ms was 0, it means that it will not return until link complete.
4113  * It returns 1 on complete, return 0 on timeout.
4114  */
4115 static int
4116 ixgbe_dev_wait_setup_link_complete(struct rte_eth_dev *dev, uint32_t timeout_ms)
4117 {
4118 #define WARNING_TIMEOUT    9000 /* 9s  in total */
4119         struct ixgbe_adapter *ad = dev->data->dev_private;
4120         uint32_t timeout = timeout_ms ? timeout_ms : WARNING_TIMEOUT;
4121
4122         while (rte_atomic32_read(&ad->link_thread_running)) {
4123                 msec_delay(1);
4124                 timeout--;
4125
4126                 if (timeout_ms) {
4127                         if (!timeout)
4128                                 return 0;
4129                 } else if (!timeout) {
4130                         /* It will not return until link complete */
4131                         timeout = WARNING_TIMEOUT;
4132                         PMD_DRV_LOG(ERR, "IXGBE link thread not complete too long time!");
4133                 }
4134         }
4135
4136         return 1;
4137 }
4138
4139 static void *
4140 ixgbe_dev_setup_link_thread_handler(void *param)
4141 {
4142         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4143         struct ixgbe_adapter *ad = dev->data->dev_private;
4144         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4145         struct ixgbe_interrupt *intr =
4146                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4147         u32 speed;
4148         bool autoneg = false;
4149
4150         pthread_detach(pthread_self());
4151         speed = hw->phy.autoneg_advertised;
4152         if (!speed)
4153                 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
4154
4155         ixgbe_setup_link(hw, speed, true);
4156
4157         intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4158         rte_atomic32_clear(&ad->link_thread_running);
4159         return NULL;
4160 }
4161
4162 /*
4163  * In freebsd environment, nic_uio drivers do not support interrupts,
4164  * rte_intr_callback_register() will fail to register interrupts.
4165  * We can not make link status to change from down to up by interrupt
4166  * callback. So we need to wait for the controller to acquire link
4167  * when ports start.
4168  * It returns 0 on link up.
4169  */
4170 static int
4171 ixgbe_wait_for_link_up(struct ixgbe_hw *hw)
4172 {
4173 #ifdef RTE_EXEC_ENV_FREEBSD
4174         int err, i;
4175         bool link_up = false;
4176         uint32_t speed = 0;
4177         const int nb_iter = 25;
4178
4179         for (i = 0; i < nb_iter; i++) {
4180                 err = ixgbe_check_link(hw, &speed, &link_up, 0);
4181                 if (err)
4182                         return err;
4183                 if (link_up)
4184                         return 0;
4185                 msec_delay(200);
4186         }
4187
4188         return 0;
4189 #else
4190         RTE_SET_USED(hw);
4191         return 0;
4192 #endif
4193 }
4194
4195 /* return 0 means link status changed, -1 means not changed */
4196 int
4197 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
4198                             int wait_to_complete, int vf)
4199 {
4200         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201         struct ixgbe_adapter *ad = dev->data->dev_private;
4202         struct rte_eth_link link;
4203         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
4204         struct ixgbe_interrupt *intr =
4205                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4206         bool link_up;
4207         int diag;
4208         int wait = 1;
4209         u32 esdp_reg;
4210
4211         memset(&link, 0, sizeof(link));
4212         link.link_status = ETH_LINK_DOWN;
4213         link.link_speed = ETH_SPEED_NUM_NONE;
4214         link.link_duplex = ETH_LINK_HALF_DUPLEX;
4215         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
4216                         ETH_LINK_SPEED_FIXED);
4217
4218         hw->mac.get_link_status = true;
4219
4220         if (intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG)
4221                 return rte_eth_linkstatus_set(dev, &link);
4222
4223         /* check if it needs to wait to complete, if lsc interrupt is enabled */
4224         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
4225                 wait = 0;
4226
4227 /* BSD has no interrupt mechanism, so force NIC status synchronization. */
4228 #ifdef RTE_EXEC_ENV_FREEBSD
4229         wait = 1;
4230 #endif
4231
4232         if (vf)
4233                 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
4234         else
4235                 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
4236
4237         if (diag != 0) {
4238                 link.link_speed = ETH_SPEED_NUM_100M;
4239                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
4240                 return rte_eth_linkstatus_set(dev, &link);
4241         }
4242
4243         if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4244                 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
4245                 if ((esdp_reg & IXGBE_ESDP_SDP3))
4246                         link_up = 0;
4247         }
4248
4249         if (link_up == 0) {
4250                 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
4251                         ixgbe_dev_wait_setup_link_complete(dev, 0);
4252                         if (rte_atomic32_test_and_set(&ad->link_thread_running)) {
4253                                 /* To avoid race condition between threads, set
4254                                  * the IXGBE_FLAG_NEED_LINK_CONFIG flag only
4255                                  * when there is no link thread running.
4256                                  */
4257                                 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
4258                                 if (rte_ctrl_thread_create(&ad->link_thread_tid,
4259                                         "ixgbe-link-handler",
4260                                         NULL,
4261                                         ixgbe_dev_setup_link_thread_handler,
4262                                         dev) < 0) {
4263                                         PMD_DRV_LOG(ERR,
4264                                                 "Create link thread failed!");
4265                                         rte_atomic32_clear(&ad->link_thread_running);
4266                                 }
4267                         } else {
4268                                 PMD_DRV_LOG(ERR,
4269                                         "Other link thread is running now!");
4270                         }
4271                 }
4272                 return rte_eth_linkstatus_set(dev, &link);
4273         }
4274
4275         link.link_status = ETH_LINK_UP;
4276         link.link_duplex = ETH_LINK_FULL_DUPLEX;
4277
4278         switch (link_speed) {
4279         default:
4280         case IXGBE_LINK_SPEED_UNKNOWN:
4281                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
4282                 break;
4283
4284         case IXGBE_LINK_SPEED_10_FULL:
4285                 link.link_speed = ETH_SPEED_NUM_10M;
4286                 break;
4287
4288         case IXGBE_LINK_SPEED_100_FULL:
4289                 link.link_speed = ETH_SPEED_NUM_100M;
4290                 break;
4291
4292         case IXGBE_LINK_SPEED_1GB_FULL:
4293                 link.link_speed = ETH_SPEED_NUM_1G;
4294                 break;
4295
4296         case IXGBE_LINK_SPEED_2_5GB_FULL:
4297                 link.link_speed = ETH_SPEED_NUM_2_5G;
4298                 break;
4299
4300         case IXGBE_LINK_SPEED_5GB_FULL:
4301                 link.link_speed = ETH_SPEED_NUM_5G;
4302                 break;
4303
4304         case IXGBE_LINK_SPEED_10GB_FULL:
4305                 link.link_speed = ETH_SPEED_NUM_10G;
4306                 break;
4307         }
4308
4309         return rte_eth_linkstatus_set(dev, &link);
4310 }
4311
4312 static int
4313 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4314 {
4315         return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
4316 }
4317
4318 static int
4319 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
4320 {
4321         return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4322 }
4323
4324 static int
4325 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4326 {
4327         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4328         uint32_t fctrl;
4329
4330         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4331         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4332         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4333
4334         return 0;
4335 }
4336
4337 static int
4338 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4339 {
4340         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4341         uint32_t fctrl;
4342
4343         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4344         fctrl &= (~IXGBE_FCTRL_UPE);
4345         if (dev->data->all_multicast == 1)
4346                 fctrl |= IXGBE_FCTRL_MPE;
4347         else
4348                 fctrl &= (~IXGBE_FCTRL_MPE);
4349         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4350
4351         return 0;
4352 }
4353
4354 static int
4355 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4356 {
4357         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4358         uint32_t fctrl;
4359
4360         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4361         fctrl |= IXGBE_FCTRL_MPE;
4362         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4363
4364         return 0;
4365 }
4366
4367 static int
4368 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4369 {
4370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371         uint32_t fctrl;
4372
4373         if (dev->data->promiscuous == 1)
4374                 return 0; /* must remain in all_multicast mode */
4375
4376         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4377         fctrl &= (~IXGBE_FCTRL_MPE);
4378         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4379
4380         return 0;
4381 }
4382
4383 /**
4384  * It clears the interrupt causes and enables the interrupt.
4385  * It will be called once only during nic initialized.
4386  *
4387  * @param dev
4388  *  Pointer to struct rte_eth_dev.
4389  * @param on
4390  *  Enable or Disable.
4391  *
4392  * @return
4393  *  - On success, zero.
4394  *  - On failure, a negative value.
4395  */
4396 static int
4397 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4398 {
4399         struct ixgbe_interrupt *intr =
4400                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4401
4402         ixgbe_dev_link_status_print(dev);
4403         if (on)
4404                 intr->mask |= IXGBE_EICR_LSC;
4405         else
4406                 intr->mask &= ~IXGBE_EICR_LSC;
4407
4408         return 0;
4409 }
4410
4411 /**
4412  * It clears the interrupt causes and enables the interrupt.
4413  * It will be called once only during nic initialized.
4414  *
4415  * @param dev
4416  *  Pointer to struct rte_eth_dev.
4417  *
4418  * @return
4419  *  - On success, zero.
4420  *  - On failure, a negative value.
4421  */
4422 static int
4423 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4424 {
4425         struct ixgbe_interrupt *intr =
4426                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4427
4428         intr->mask |= IXGBE_EICR_RTX_QUEUE;
4429
4430         return 0;
4431 }
4432
4433 /**
4434  * It clears the interrupt causes and enables the interrupt.
4435  * It will be called once only during nic initialized.
4436  *
4437  * @param dev
4438  *  Pointer to struct rte_eth_dev.
4439  *
4440  * @return
4441  *  - On success, zero.
4442  *  - On failure, a negative value.
4443  */
4444 static int
4445 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4446 {
4447         struct ixgbe_interrupt *intr =
4448                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4449
4450         intr->mask |= IXGBE_EICR_LINKSEC;
4451
4452         return 0;
4453 }
4454
4455 /*
4456  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4457  *
4458  * @param dev
4459  *  Pointer to struct rte_eth_dev.
4460  *
4461  * @return
4462  *  - On success, zero.
4463  *  - On failure, a negative value.
4464  */
4465 static int
4466 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4467 {
4468         uint32_t eicr;
4469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4470         struct ixgbe_interrupt *intr =
4471                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4472
4473         /* clear all cause mask */
4474         ixgbe_disable_intr(hw);
4475
4476         /* read-on-clear nic registers here */
4477         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4478         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4479
4480         intr->flags = 0;
4481
4482         /* set flag for async link update */
4483         if (eicr & IXGBE_EICR_LSC)
4484                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4485
4486         if (eicr & IXGBE_EICR_MAILBOX)
4487                 intr->flags |= IXGBE_FLAG_MAILBOX;
4488
4489         if (eicr & IXGBE_EICR_LINKSEC)
4490                 intr->flags |= IXGBE_FLAG_MACSEC;
4491
4492         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
4493             hw->phy.type == ixgbe_phy_x550em_ext_t &&
4494             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4495                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4496
4497         return 0;
4498 }
4499
4500 /**
4501  * It gets and then prints the link status.
4502  *
4503  * @param dev
4504  *  Pointer to struct rte_eth_dev.
4505  *
4506  * @return
4507  *  - On success, zero.
4508  *  - On failure, a negative value.
4509  */
4510 static void
4511 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4512 {
4513         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4514         struct rte_eth_link link;
4515
4516         rte_eth_linkstatus_get(dev, &link);
4517
4518         if (link.link_status) {
4519                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4520                                         (int)(dev->data->port_id),
4521                                         (unsigned)link.link_speed,
4522                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4523                                         "full-duplex" : "half-duplex");
4524         } else {
4525                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4526                                 (int)(dev->data->port_id));
4527         }
4528         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4529                                 pci_dev->addr.domain,
4530                                 pci_dev->addr.bus,
4531                                 pci_dev->addr.devid,
4532                                 pci_dev->addr.function);
4533 }
4534
4535 /*
4536  * It executes link_update after knowing an interrupt occurred.
4537  *
4538  * @param dev
4539  *  Pointer to struct rte_eth_dev.
4540  *
4541  * @return
4542  *  - On success, zero.
4543  *  - On failure, a negative value.
4544  */
4545 static int
4546 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
4547 {
4548         struct ixgbe_interrupt *intr =
4549                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4550         int64_t timeout;
4551         struct ixgbe_hw *hw =
4552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553
4554         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4555
4556         if (intr->flags & IXGBE_FLAG_MAILBOX) {
4557                 ixgbe_pf_mbx_process(dev);
4558                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4559         }
4560
4561         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4562                 ixgbe_handle_lasi(hw);
4563                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4564         }
4565
4566         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4567                 struct rte_eth_link link;
4568
4569                 /* get the link status before link update, for predicting later */
4570                 rte_eth_linkstatus_get(dev, &link);
4571
4572                 ixgbe_dev_link_update(dev, 0);
4573
4574                 /* likely to up */
4575                 if (!link.link_status)
4576                         /* handle it 1 sec later, wait it being stable */
4577                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4578                 /* likely to down */
4579                 else
4580                         /* handle it 4 sec later, wait it being stable */
4581                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4582
4583                 ixgbe_dev_link_status_print(dev);
4584                 if (rte_eal_alarm_set(timeout * 1000,
4585                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4586                         PMD_DRV_LOG(ERR, "Error setting alarm");
4587                 else {
4588                         /* remember original mask */
4589                         intr->mask_original = intr->mask;
4590                         /* only disable lsc interrupt */
4591                         intr->mask &= ~IXGBE_EIMS_LSC;
4592                 }
4593         }
4594
4595         PMD_DRV_LOG(DEBUG, "enable intr immediately");
4596         ixgbe_enable_intr(dev);
4597
4598         return 0;
4599 }
4600
4601 /**
4602  * Interrupt handler which shall be registered for alarm callback for delayed
4603  * handling specific interrupt to wait for the stable nic state. As the
4604  * NIC interrupt state is not stable for ixgbe after link is just down,
4605  * it needs to wait 4 seconds to get the stable status.
4606  *
4607  * @param handle
4608  *  Pointer to interrupt handle.
4609  * @param param
4610  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4611  *
4612  * @return
4613  *  void
4614  */
4615 static void
4616 ixgbe_dev_interrupt_delayed_handler(void *param)
4617 {
4618         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4619         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4620         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4621         struct ixgbe_interrupt *intr =
4622                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4623         struct ixgbe_hw *hw =
4624                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4625         uint32_t eicr;
4626
4627         ixgbe_disable_intr(hw);
4628
4629         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4630         if (eicr & IXGBE_EICR_MAILBOX)
4631                 ixgbe_pf_mbx_process(dev);
4632
4633         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4634                 ixgbe_handle_lasi(hw);
4635                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4636         }
4637
4638         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4639                 ixgbe_dev_link_update(dev, 0);
4640                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4641                 ixgbe_dev_link_status_print(dev);
4642                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
4643         }
4644
4645         if (intr->flags & IXGBE_FLAG_MACSEC) {
4646                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC, NULL);
4647                 intr->flags &= ~IXGBE_FLAG_MACSEC;
4648         }
4649
4650         /* restore original mask */
4651         intr->mask = intr->mask_original;
4652         intr->mask_original = 0;
4653
4654         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4655         ixgbe_enable_intr(dev);
4656         rte_intr_ack(intr_handle);
4657 }
4658
4659 /**
4660  * Interrupt handler triggered by NIC  for handling
4661  * specific interrupt.
4662  *
4663  * @param handle
4664  *  Pointer to interrupt handle.
4665  * @param param
4666  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4667  *
4668  * @return
4669  *  void
4670  */
4671 static void
4672 ixgbe_dev_interrupt_handler(void *param)
4673 {
4674         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4675
4676         ixgbe_dev_interrupt_get_status(dev);
4677         ixgbe_dev_interrupt_action(dev);
4678 }
4679
4680 static int
4681 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4682 {
4683         struct ixgbe_hw *hw;
4684
4685         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4686         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4687 }
4688
4689 static int
4690 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4691 {
4692         struct ixgbe_hw *hw;
4693
4694         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4696 }
4697
4698 static int
4699 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4700 {
4701         struct ixgbe_hw *hw;
4702         uint32_t mflcn_reg;
4703         uint32_t fccfg_reg;
4704         int rx_pause;
4705         int tx_pause;
4706
4707         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4708
4709         fc_conf->pause_time = hw->fc.pause_time;
4710         fc_conf->high_water = hw->fc.high_water[0];
4711         fc_conf->low_water = hw->fc.low_water[0];
4712         fc_conf->send_xon = hw->fc.send_xon;
4713         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4714
4715         /*
4716          * Return rx_pause status according to actual setting of
4717          * MFLCN register.
4718          */
4719         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4720         if (mflcn_reg & IXGBE_MFLCN_PMCF)
4721                 fc_conf->mac_ctrl_frame_fwd = 1;
4722         else
4723                 fc_conf->mac_ctrl_frame_fwd = 0;
4724
4725         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4726                 rx_pause = 1;
4727         else
4728                 rx_pause = 0;
4729
4730         /*
4731          * Return tx_pause status according to actual setting of
4732          * FCCFG register.
4733          */
4734         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4735         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4736                 tx_pause = 1;
4737         else
4738                 tx_pause = 0;
4739
4740         if (rx_pause && tx_pause)
4741                 fc_conf->mode = RTE_FC_FULL;
4742         else if (rx_pause)
4743                 fc_conf->mode = RTE_FC_RX_PAUSE;
4744         else if (tx_pause)
4745                 fc_conf->mode = RTE_FC_TX_PAUSE;
4746         else
4747                 fc_conf->mode = RTE_FC_NONE;
4748
4749         return 0;
4750 }
4751
4752 static int
4753 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4754 {
4755         struct ixgbe_hw *hw;
4756         struct ixgbe_adapter *adapter = dev->data->dev_private;
4757         int err;
4758         uint32_t rx_buf_size;
4759         uint32_t max_high_water;
4760         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4761                 ixgbe_fc_none,
4762                 ixgbe_fc_rx_pause,
4763                 ixgbe_fc_tx_pause,
4764                 ixgbe_fc_full
4765         };
4766
4767         PMD_INIT_FUNC_TRACE();
4768
4769         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4770         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4771         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4772
4773         /*
4774          * At least reserve one Ethernet frame for watermark
4775          * high_water/low_water in kilo bytes for ixgbe
4776          */
4777         max_high_water = (rx_buf_size -
4778                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4779         if ((fc_conf->high_water > max_high_water) ||
4780                 (fc_conf->high_water < fc_conf->low_water)) {
4781                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4782                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4783                 return -EINVAL;
4784         }
4785
4786         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4787         hw->fc.pause_time     = fc_conf->pause_time;
4788         hw->fc.high_water[0]  = fc_conf->high_water;
4789         hw->fc.low_water[0]   = fc_conf->low_water;
4790         hw->fc.send_xon       = fc_conf->send_xon;
4791         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4792         adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
4793
4794         err = ixgbe_flow_ctrl_enable(dev, hw);
4795         if (err < 0) {
4796                 PMD_INIT_LOG(ERR, "ixgbe_flow_ctrl_enable = 0x%x", err);
4797                 return -EIO;
4798         }
4799         return err;
4800 }
4801
4802 /**
4803  *  ixgbe_pfc_enable_generic - Enable flow control
4804  *  @hw: pointer to hardware structure
4805  *  @tc_num: traffic class number
4806  *  Enable flow control according to the current settings.
4807  */
4808 static int
4809 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4810 {
4811         int ret_val = 0;
4812         uint32_t mflcn_reg, fccfg_reg;
4813         uint32_t reg;
4814         uint32_t fcrtl, fcrth;
4815         uint8_t i;
4816         uint8_t nb_rx_en;
4817
4818         /* Validate the water mark configuration */
4819         if (!hw->fc.pause_time) {
4820                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4821                 goto out;
4822         }
4823
4824         /* Low water mark of zero causes XOFF floods */
4825         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4826                  /* High/Low water can not be 0 */
4827                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4828                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4829                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4830                         goto out;
4831                 }
4832
4833                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4834                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4835                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4836                         goto out;
4837                 }
4838         }
4839         /* Negotiate the fc mode to use */
4840         ixgbe_fc_autoneg(hw);
4841
4842         /* Disable any previous flow control settings */
4843         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4844         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4845
4846         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4847         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4848
4849         switch (hw->fc.current_mode) {
4850         case ixgbe_fc_none:
4851                 /*
4852                  * If the count of enabled RX Priority Flow control >1,
4853                  * and the TX pause can not be disabled
4854                  */
4855                 nb_rx_en = 0;
4856                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4857                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4858                         if (reg & IXGBE_FCRTH_FCEN)
4859                                 nb_rx_en++;
4860                 }
4861                 if (nb_rx_en > 1)
4862                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4863                 break;
4864         case ixgbe_fc_rx_pause:
4865                 /*
4866                  * Rx Flow control is enabled and Tx Flow control is
4867                  * disabled by software override. Since there really
4868                  * isn't a way to advertise that we are capable of RX
4869                  * Pause ONLY, we will advertise that we support both
4870                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4871                  * disable the adapter's ability to send PAUSE frames.
4872                  */
4873                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4874                 /*
4875                  * If the count of enabled RX Priority Flow control >1,
4876                  * and the TX pause can not be disabled
4877                  */
4878                 nb_rx_en = 0;
4879                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4880                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4881                         if (reg & IXGBE_FCRTH_FCEN)
4882                                 nb_rx_en++;
4883                 }
4884                 if (nb_rx_en > 1)
4885                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4886                 break;
4887         case ixgbe_fc_tx_pause:
4888                 /*
4889                  * Tx Flow control is enabled, and Rx Flow control is
4890                  * disabled by software override.
4891                  */
4892                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4893                 break;
4894         case ixgbe_fc_full:
4895                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4896                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4897                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4898                 break;
4899         default:
4900                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4901                 ret_val = IXGBE_ERR_CONFIG;
4902                 goto out;
4903         }
4904
4905         /* Set 802.3x based flow control settings. */
4906         mflcn_reg |= IXGBE_MFLCN_DPF;
4907         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4908         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4909
4910         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4911         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4912                 hw->fc.high_water[tc_num]) {
4913                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4914                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4915                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4916         } else {
4917                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4918                 /*
4919                  * In order to prevent Tx hangs when the internal Tx
4920                  * switch is enabled we must set the high water mark
4921                  * to the maximum FCRTH value.  This allows the Tx
4922                  * switch to function even under heavy Rx workloads.
4923                  */
4924                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4925         }
4926         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4927
4928         /* Configure pause time (2 TCs per register) */
4929         reg = hw->fc.pause_time * 0x00010001;
4930         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4931                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4932
4933         /* Configure flow control refresh threshold value */
4934         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4935
4936 out:
4937         return ret_val;
4938 }
4939
4940 static int
4941 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4942 {
4943         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4944         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4945
4946         if (hw->mac.type != ixgbe_mac_82598EB) {
4947                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4948         }
4949         return ret_val;
4950 }
4951
4952 static int
4953 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4954 {
4955         int err;
4956         uint32_t rx_buf_size;
4957         uint32_t max_high_water;
4958         uint8_t tc_num;
4959         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4960         struct ixgbe_hw *hw =
4961                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4962         struct ixgbe_dcb_config *dcb_config =
4963                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4964
4965         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4966                 ixgbe_fc_none,
4967                 ixgbe_fc_rx_pause,
4968                 ixgbe_fc_tx_pause,
4969                 ixgbe_fc_full
4970         };
4971
4972         PMD_INIT_FUNC_TRACE();
4973
4974         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4975         tc_num = map[pfc_conf->priority];
4976         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4977         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4978         /*
4979          * At least reserve one Ethernet frame for watermark
4980          * high_water/low_water in kilo bytes for ixgbe
4981          */
4982         max_high_water = (rx_buf_size -
4983                         RTE_ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4984         if ((pfc_conf->fc.high_water > max_high_water) ||
4985             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4986                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4987                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4988                 return -EINVAL;
4989         }
4990
4991         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4992         hw->fc.pause_time = pfc_conf->fc.pause_time;
4993         hw->fc.send_xon = pfc_conf->fc.send_xon;
4994         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4995         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4996
4997         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4998
4999         /* Not negotiated is not an error case */
5000         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
5001                 return 0;
5002
5003         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
5004         return -EIO;
5005 }
5006
5007 static int
5008 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
5009                           struct rte_eth_rss_reta_entry64 *reta_conf,
5010                           uint16_t reta_size)
5011 {
5012         uint16_t i, sp_reta_size;
5013         uint8_t j, mask;
5014         uint32_t reta, r;
5015         uint16_t idx, shift;
5016         struct ixgbe_adapter *adapter = dev->data->dev_private;
5017         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5018         uint32_t reta_reg;
5019
5020         PMD_INIT_FUNC_TRACE();
5021
5022         if (!ixgbe_rss_update_sp(hw->mac.type)) {
5023                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
5024                         "NIC.");
5025                 return -ENOTSUP;
5026         }
5027
5028         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5029         if (reta_size != sp_reta_size) {
5030                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5031                         "(%d) doesn't match the number hardware can supported "
5032                         "(%d)", reta_size, sp_reta_size);
5033                 return -EINVAL;
5034         }
5035
5036         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5037                 idx = i / RTE_RETA_GROUP_SIZE;
5038                 shift = i % RTE_RETA_GROUP_SIZE;
5039                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5040                                                 IXGBE_4_BIT_MASK);
5041                 if (!mask)
5042                         continue;
5043                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5044                 if (mask == IXGBE_4_BIT_MASK)
5045                         r = 0;
5046                 else
5047                         r = IXGBE_READ_REG(hw, reta_reg);
5048                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5049                         if (mask & (0x1 << j))
5050                                 reta |= reta_conf[idx].reta[shift + j] <<
5051                                                         (CHAR_BIT * j);
5052                         else
5053                                 reta |= r & (IXGBE_8_BIT_MASK <<
5054                                                 (CHAR_BIT * j));
5055                 }
5056                 IXGBE_WRITE_REG(hw, reta_reg, reta);
5057         }
5058         adapter->rss_reta_updated = 1;
5059
5060         return 0;
5061 }
5062
5063 static int
5064 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
5065                          struct rte_eth_rss_reta_entry64 *reta_conf,
5066                          uint16_t reta_size)
5067 {
5068         uint16_t i, sp_reta_size;
5069         uint8_t j, mask;
5070         uint32_t reta;
5071         uint16_t idx, shift;
5072         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5073         uint32_t reta_reg;
5074
5075         PMD_INIT_FUNC_TRACE();
5076         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
5077         if (reta_size != sp_reta_size) {
5078                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
5079                         "(%d) doesn't match the number hardware can supported "
5080                         "(%d)", reta_size, sp_reta_size);
5081                 return -EINVAL;
5082         }
5083
5084         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
5085                 idx = i / RTE_RETA_GROUP_SIZE;
5086                 shift = i % RTE_RETA_GROUP_SIZE;
5087                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
5088                                                 IXGBE_4_BIT_MASK);
5089                 if (!mask)
5090                         continue;
5091
5092                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
5093                 reta = IXGBE_READ_REG(hw, reta_reg);
5094                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
5095                         if (mask & (0x1 << j))
5096                                 reta_conf[idx].reta[shift + j] =
5097                                         ((reta >> (CHAR_BIT * j)) &
5098                                                 IXGBE_8_BIT_MASK);
5099                 }
5100         }
5101
5102         return 0;
5103 }
5104
5105 static int
5106 ixgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
5107                                 uint32_t index, uint32_t pool)
5108 {
5109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5110         uint32_t enable_addr = 1;
5111
5112         return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
5113                              pool, enable_addr);
5114 }
5115
5116 static void
5117 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
5118 {
5119         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120
5121         ixgbe_clear_rar(hw, index);
5122 }
5123
5124 static int
5125 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
5126 {
5127         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5128
5129         ixgbe_remove_rar(dev, 0);
5130         ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
5131
5132         return 0;
5133 }
5134
5135 static bool
5136 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
5137 {
5138         if (strcmp(dev->device->driver->name, drv->driver.name))
5139                 return false;
5140
5141         return true;
5142 }
5143
5144 bool
5145 is_ixgbe_supported(struct rte_eth_dev *dev)
5146 {
5147         return is_device_supported(dev, &rte_ixgbe_pmd);
5148 }
5149
5150 static int
5151 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
5152 {
5153         uint32_t hlreg0;
5154         uint32_t maxfrs;
5155         struct ixgbe_hw *hw;
5156         struct rte_eth_dev_info dev_info;
5157         uint32_t frame_size = mtu + IXGBE_ETH_OVERHEAD;
5158         struct rte_eth_dev_data *dev_data = dev->data;
5159         int ret;
5160
5161         ret = ixgbe_dev_info_get(dev, &dev_info);
5162         if (ret != 0)
5163                 return ret;
5164
5165         /* check that mtu is within the allowed range */
5166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
5167                 return -EINVAL;
5168
5169         /* If device is started, refuse mtu that requires the support of
5170          * scattered packets when this feature has not been enabled before.
5171          */
5172         if (dev_data->dev_started && !dev_data->scattered_rx &&
5173             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
5174              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
5175                 PMD_INIT_LOG(ERR, "Stop port first.");
5176                 return -EINVAL;
5177         }
5178
5179         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5180         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
5181
5182         /* switch to jumbo mode if needed */
5183         if (frame_size > RTE_ETHER_MAX_LEN) {
5184                 dev->data->dev_conf.rxmode.offloads |=
5185                         DEV_RX_OFFLOAD_JUMBO_FRAME;
5186                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
5187         } else {
5188                 dev->data->dev_conf.rxmode.offloads &=
5189                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
5190                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
5191         }
5192         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
5193
5194         /* update max frame size */
5195         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
5196
5197         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
5198         maxfrs &= 0x0000FFFF;
5199         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
5200         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
5201
5202         return 0;
5203 }
5204
5205 /*
5206  * Virtual Function operations
5207  */
5208 static void
5209 ixgbevf_intr_disable(struct rte_eth_dev *dev)
5210 {
5211         struct ixgbe_interrupt *intr =
5212                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5213         struct ixgbe_hw *hw =
5214                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215
5216         PMD_INIT_FUNC_TRACE();
5217
5218         /* Clear interrupt mask to stop from interrupts being generated */
5219         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
5220
5221         IXGBE_WRITE_FLUSH(hw);
5222
5223         /* Clear mask value. */
5224         intr->mask = 0;
5225 }
5226
5227 static void
5228 ixgbevf_intr_enable(struct rte_eth_dev *dev)
5229 {
5230         struct ixgbe_interrupt *intr =
5231                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5232         struct ixgbe_hw *hw =
5233                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5234
5235         PMD_INIT_FUNC_TRACE();
5236
5237         /* VF enable interrupt autoclean */
5238         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
5239         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
5240         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
5241
5242         IXGBE_WRITE_FLUSH(hw);
5243
5244         /* Save IXGBE_VTEIMS value to mask. */
5245         intr->mask = IXGBE_VF_IRQ_ENABLE_MASK;
5246 }
5247
5248 static int
5249 ixgbevf_dev_configure(struct rte_eth_dev *dev)
5250 {
5251         struct rte_eth_conf *conf = &dev->data->dev_conf;
5252         struct ixgbe_adapter *adapter = dev->data->dev_private;
5253
5254         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
5255                      dev->data->port_id);
5256
5257         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
5258                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
5259
5260         /*
5261          * VF has no ability to enable/disable HW CRC
5262          * Keep the persistent behavior the same as Host PF
5263          */
5264 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
5265         if (conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) {
5266                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
5267                 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_KEEP_CRC;
5268         }
5269 #else
5270         if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)) {
5271                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
5272                 conf->rxmode.offloads |= DEV_RX_OFFLOAD_KEEP_CRC;
5273         }
5274 #endif
5275
5276         /*
5277          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
5278          * allocation or vector Rx preconditions we will reset it.
5279          */
5280         adapter->rx_bulk_alloc_allowed = true;
5281         adapter->rx_vec_allowed = true;
5282
5283         return 0;
5284 }
5285
5286 static int
5287 ixgbevf_dev_start(struct rte_eth_dev *dev)
5288 {
5289         struct ixgbe_hw *hw =
5290                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291         uint32_t intr_vector = 0;
5292         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5293         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5294
5295         int err, mask = 0;
5296
5297         PMD_INIT_FUNC_TRACE();
5298
5299         /* Stop the link setup handler before resetting the HW. */
5300         ixgbe_dev_wait_setup_link_complete(dev, 0);
5301
5302         err = hw->mac.ops.reset_hw(hw);
5303
5304         /**
5305          * In this case, reuses the MAC address assigned by VF
5306          * initialization.
5307          */
5308         if (err != IXGBE_SUCCESS && err != IXGBE_ERR_INVALID_MAC_ADDR) {
5309                 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
5310                 return err;
5311         }
5312
5313         hw->mac.get_link_status = true;
5314
5315         /* negotiate mailbox API version to use with the PF. */
5316         ixgbevf_negotiate_api(hw);
5317
5318         ixgbevf_dev_tx_init(dev);
5319
5320         /* This can fail when allocating mbufs for descriptor rings */
5321         err = ixgbevf_dev_rx_init(dev);
5322         if (err) {
5323                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
5324                 ixgbe_dev_clear_queues(dev);
5325                 return err;
5326         }
5327
5328         /* Set vfta */
5329         ixgbevf_set_vfta_all(dev, 1);
5330
5331         /* Set HW strip */
5332         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
5333                 ETH_VLAN_EXTEND_MASK;
5334         err = ixgbevf_vlan_offload_config(dev, mask);
5335         if (err) {
5336                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
5337                 ixgbe_dev_clear_queues(dev);
5338                 return err;
5339         }
5340
5341         ixgbevf_dev_rxtx_start(dev);
5342
5343         /* check and configure queue intr-vector mapping */
5344         if (rte_intr_cap_multiple(intr_handle) &&
5345             dev->data->dev_conf.intr_conf.rxq) {
5346                 /* According to datasheet, only vector 0/1/2 can be used,
5347                  * now only one vector is used for Rx queue
5348                  */
5349                 intr_vector = 1;
5350                 if (rte_intr_efd_enable(intr_handle, intr_vector))
5351                         return -1;
5352         }
5353
5354         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
5355                 intr_handle->intr_vec =
5356                         rte_zmalloc("intr_vec",
5357                                     dev->data->nb_rx_queues * sizeof(int), 0);
5358                 if (intr_handle->intr_vec == NULL) {
5359                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
5360                                      " intr_vec", dev->data->nb_rx_queues);
5361                         return -ENOMEM;
5362                 }
5363         }
5364         ixgbevf_configure_msix(dev);
5365
5366         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5367          * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5368          * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5369          * is not cleared, it will fail when following rte_intr_enable( ) tries
5370          * to map Rx queue interrupt to other VFIO vectors.
5371          * So clear uio/vfio intr/evevnfd first to avoid failure.
5372          */
5373         rte_intr_disable(intr_handle);
5374
5375         rte_intr_enable(intr_handle);
5376
5377         /* Re-enable interrupt for VF */
5378         ixgbevf_intr_enable(dev);
5379
5380         /*
5381          * Update link status right before return, because it may
5382          * start link configuration process in a separate thread.
5383          */
5384         ixgbevf_dev_link_update(dev, 0);
5385
5386         hw->adapter_stopped = false;
5387
5388         return 0;
5389 }
5390
5391 static int
5392 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5393 {
5394         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5395         struct ixgbe_adapter *adapter = dev->data->dev_private;
5396         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5397         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5398
5399         if (hw->adapter_stopped)
5400                 return 0;
5401
5402         PMD_INIT_FUNC_TRACE();
5403
5404         ixgbe_dev_wait_setup_link_complete(dev, 0);
5405
5406         ixgbevf_intr_disable(dev);
5407
5408         dev->data->dev_started = 0;
5409         hw->adapter_stopped = 1;
5410         ixgbe_stop_adapter(hw);
5411
5412         /*
5413           * Clear what we set, but we still keep shadow_vfta to
5414           * restore after device starts
5415           */
5416         ixgbevf_set_vfta_all(dev, 0);
5417
5418         /* Clear stored conf */
5419         dev->data->scattered_rx = 0;
5420
5421         ixgbe_dev_clear_queues(dev);
5422
5423         /* Clean datapath event and queue/vec mapping */
5424         rte_intr_efd_disable(intr_handle);
5425         if (intr_handle->intr_vec != NULL) {
5426                 rte_free(intr_handle->intr_vec);
5427                 intr_handle->intr_vec = NULL;
5428         }
5429
5430         adapter->rss_reta_updated = 0;
5431
5432         return 0;
5433 }
5434
5435 static int
5436 ixgbevf_dev_close(struct rte_eth_dev *dev)
5437 {
5438         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5439         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5440         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5441         int ret;
5442
5443         PMD_INIT_FUNC_TRACE();
5444         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
5445                 return 0;
5446
5447         ixgbe_reset_hw(hw);
5448
5449         ret = ixgbevf_dev_stop(dev);
5450
5451         ixgbe_dev_free_queues(dev);
5452
5453         /**
5454          * Remove the VF MAC address ro ensure
5455          * that the VF traffic goes to the PF
5456          * after stop, close and detach of the VF
5457          **/
5458         ixgbevf_remove_mac_addr(dev, 0);
5459
5460         rte_intr_disable(intr_handle);
5461         rte_intr_callback_unregister(intr_handle,
5462                                      ixgbevf_dev_interrupt_handler, dev);
5463
5464         return ret;
5465 }
5466
5467 /*
5468  * Reset VF device
5469  */
5470 static int
5471 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5472 {
5473         int ret;
5474
5475         ret = eth_ixgbevf_dev_uninit(dev);
5476         if (ret)
5477                 return ret;
5478
5479         ret = eth_ixgbevf_dev_init(dev);
5480
5481         return ret;
5482 }
5483
5484 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5485 {
5486         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5487         struct ixgbe_vfta *shadow_vfta =
5488                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5489         int i = 0, j = 0, vfta = 0, mask = 1;
5490
5491         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5492                 vfta = shadow_vfta->vfta[i];
5493                 if (vfta) {
5494                         mask = 1;
5495                         for (j = 0; j < 32; j++) {
5496                                 if (vfta & mask)
5497                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
5498                                                        on, false);
5499                                 mask <<= 1;
5500                         }
5501                 }
5502         }
5503
5504 }
5505
5506 static int
5507 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5508 {
5509         struct ixgbe_hw *hw =
5510                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5511         struct ixgbe_vfta *shadow_vfta =
5512                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5513         uint32_t vid_idx = 0;
5514         uint32_t vid_bit = 0;
5515         int ret = 0;
5516
5517         PMD_INIT_FUNC_TRACE();
5518
5519         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5520         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5521         if (ret) {
5522                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5523                 return ret;
5524         }
5525         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5526         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5527
5528         /* Save what we set and retore it after device reset */
5529         if (on)
5530                 shadow_vfta->vfta[vid_idx] |= vid_bit;
5531         else
5532                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5533
5534         return 0;
5535 }
5536
5537 static void
5538 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5539 {
5540         struct ixgbe_hw *hw =
5541                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5542         uint32_t ctrl;
5543
5544         PMD_INIT_FUNC_TRACE();
5545
5546         if (queue >= hw->mac.max_rx_queues)
5547                 return;
5548
5549         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5550         if (on)
5551                 ctrl |= IXGBE_RXDCTL_VME;
5552         else
5553                 ctrl &= ~IXGBE_RXDCTL_VME;
5554         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5555
5556         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5557 }
5558
5559 static int
5560 ixgbevf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
5561 {
5562         struct ixgbe_rx_queue *rxq;
5563         uint16_t i;
5564         int on = 0;
5565
5566         /* VF function only support hw strip feature, others are not support */
5567         if (mask & ETH_VLAN_STRIP_MASK) {
5568                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
5569                         rxq = dev->data->rx_queues[i];
5570                         on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5571                         ixgbevf_vlan_strip_queue_set(dev, i, on);
5572                 }
5573         }
5574
5575         return 0;
5576 }
5577
5578 static int
5579 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5580 {
5581         ixgbe_config_vlan_strip_on_all_queues(dev, mask);
5582
5583         ixgbevf_vlan_offload_config(dev, mask);
5584
5585         return 0;
5586 }
5587
5588 int
5589 ixgbe_vt_check(struct ixgbe_hw *hw)
5590 {
5591         uint32_t reg_val;
5592
5593         /* if Virtualization Technology is enabled */
5594         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5595         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5596                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5597                 return -1;
5598         }
5599
5600         return 0;
5601 }
5602
5603 static uint32_t
5604 ixgbe_uta_vector(struct ixgbe_hw *hw, struct rte_ether_addr *uc_addr)
5605 {
5606         uint32_t vector = 0;
5607
5608         switch (hw->mac.mc_filter_type) {
5609         case 0:   /* use bits [47:36] of the address */
5610                 vector = ((uc_addr->addr_bytes[4] >> 4) |
5611                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5612                 break;
5613         case 1:   /* use bits [46:35] of the address */
5614                 vector = ((uc_addr->addr_bytes[4] >> 3) |
5615                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5616                 break;
5617         case 2:   /* use bits [45:34] of the address */
5618                 vector = ((uc_addr->addr_bytes[4] >> 2) |
5619                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5620                 break;
5621         case 3:   /* use bits [43:32] of the address */
5622                 vector = ((uc_addr->addr_bytes[4]) |
5623                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5624                 break;
5625         default:  /* Invalid mc_filter_type */
5626                 break;
5627         }
5628
5629         /* vector can only be 12-bits or boundary will be exceeded */
5630         vector &= 0xFFF;
5631         return vector;
5632 }
5633
5634 static int
5635 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,
5636                         struct rte_ether_addr *mac_addr, uint8_t on)
5637 {
5638         uint32_t vector;
5639         uint32_t uta_idx;
5640         uint32_t reg_val;
5641         uint32_t uta_shift;
5642         uint32_t rc;
5643         const uint32_t ixgbe_uta_idx_mask = 0x7F;
5644         const uint32_t ixgbe_uta_bit_shift = 5;
5645         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5646         const uint32_t bit1 = 0x1;
5647
5648         struct ixgbe_hw *hw =
5649                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650         struct ixgbe_uta_info *uta_info =
5651                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5652
5653         /* The UTA table only exists on 82599 hardware and newer */
5654         if (hw->mac.type < ixgbe_mac_82599EB)
5655                 return -ENOTSUP;
5656
5657         vector = ixgbe_uta_vector(hw, mac_addr);
5658         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5659         uta_shift = vector & ixgbe_uta_bit_mask;
5660
5661         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5662         if (rc == on)
5663                 return 0;
5664
5665         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5666         if (on) {
5667                 uta_info->uta_in_use++;
5668                 reg_val |= (bit1 << uta_shift);
5669                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5670         } else {
5671                 uta_info->uta_in_use--;
5672                 reg_val &= ~(bit1 << uta_shift);
5673                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5674         }
5675
5676         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5677
5678         if (uta_info->uta_in_use > 0)
5679                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5680                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5681         else
5682                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5683
5684         return 0;
5685 }
5686
5687 static int
5688 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5689 {
5690         int i;
5691         struct ixgbe_hw *hw =
5692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct ixgbe_uta_info *uta_info =
5694                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5695
5696         /* The UTA table only exists on 82599 hardware and newer */
5697         if (hw->mac.type < ixgbe_mac_82599EB)
5698                 return -ENOTSUP;
5699
5700         if (on) {
5701                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5702                         uta_info->uta_shadow[i] = ~0;
5703                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5704                 }
5705         } else {
5706                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5707                         uta_info->uta_shadow[i] = 0;
5708                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5709                 }
5710         }
5711         return 0;
5712
5713 }
5714
5715 uint32_t
5716 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5717 {
5718         uint32_t new_val = orig_val;
5719
5720         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5721                 new_val |= IXGBE_VMOLR_AUPE;
5722         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5723                 new_val |= IXGBE_VMOLR_ROMPE;
5724         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5725                 new_val |= IXGBE_VMOLR_ROPE;
5726         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5727                 new_val |= IXGBE_VMOLR_BAM;
5728         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5729                 new_val |= IXGBE_VMOLR_MPE;
5730
5731         return new_val;
5732 }
5733
5734 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5735 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5736 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5737 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5738 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5739         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5740         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5741
5742 static int
5743 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5744                       struct rte_eth_mirror_conf *mirror_conf,
5745                       uint8_t rule_id, uint8_t on)
5746 {
5747         uint32_t mr_ctl, vlvf;
5748         uint32_t mp_lsb = 0;
5749         uint32_t mv_msb = 0;
5750         uint32_t mv_lsb = 0;
5751         uint32_t mp_msb = 0;
5752         uint8_t i = 0;
5753         int reg_index = 0;
5754         uint64_t vlan_mask = 0;
5755
5756         const uint8_t pool_mask_offset = 32;
5757         const uint8_t vlan_mask_offset = 32;
5758         const uint8_t dst_pool_offset = 8;
5759         const uint8_t rule_mr_offset  = 4;
5760         const uint8_t mirror_rule_mask = 0x0F;
5761
5762         struct ixgbe_mirror_info *mr_info =
5763                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5764         struct ixgbe_hw *hw =
5765                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5766         uint8_t mirror_type = 0;
5767
5768         if (ixgbe_vt_check(hw) < 0)
5769                 return -ENOTSUP;
5770
5771         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5772                 return -EINVAL;
5773
5774         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5775                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5776                             mirror_conf->rule_type);
5777                 return -EINVAL;
5778         }
5779
5780         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5781                 mirror_type |= IXGBE_MRCTL_VLME;
5782                 /* Check if vlan id is valid and find conresponding VLAN ID
5783                  * index in VLVF
5784                  */
5785                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5786                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5787                                 /* search vlan id related pool vlan filter
5788                                  * index
5789                                  */
5790                                 reg_index = ixgbe_find_vlvf_slot(
5791                                                 hw,
5792                                                 mirror_conf->vlan.vlan_id[i],
5793                                                 false);
5794                                 if (reg_index < 0)
5795                                         return -EINVAL;
5796                                 vlvf = IXGBE_READ_REG(hw,
5797                                                       IXGBE_VLVF(reg_index));
5798                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5799                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5800                                       mirror_conf->vlan.vlan_id[i]))
5801                                         vlan_mask |= (1ULL << reg_index);
5802                                 else
5803                                         return -EINVAL;
5804                         }
5805                 }
5806
5807                 if (on) {
5808                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5809                         mv_msb = vlan_mask >> vlan_mask_offset;
5810
5811                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5812                                                 mirror_conf->vlan.vlan_mask;
5813                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5814                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5815                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5816                                                 mirror_conf->vlan.vlan_id[i];
5817                         }
5818                 } else {
5819                         mv_lsb = 0;
5820                         mv_msb = 0;
5821                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5822                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5823                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5824                 }
5825         }
5826
5827         /**
5828          * if enable pool mirror, write related pool mask register,if disable
5829          * pool mirror, clear PFMRVM register
5830          */
5831         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5832                 mirror_type |= IXGBE_MRCTL_VPME;
5833                 if (on) {
5834                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5835                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5836                         mr_info->mr_conf[rule_id].pool_mask =
5837                                         mirror_conf->pool_mask;
5838
5839                 } else {
5840                         mp_lsb = 0;
5841                         mp_msb = 0;
5842                         mr_info->mr_conf[rule_id].pool_mask = 0;
5843                 }
5844         }
5845         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5846                 mirror_type |= IXGBE_MRCTL_UPME;
5847         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5848                 mirror_type |= IXGBE_MRCTL_DPME;
5849
5850         /* read  mirror control register and recalculate it */
5851         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5852
5853         if (on) {
5854                 mr_ctl |= mirror_type;
5855                 mr_ctl &= mirror_rule_mask;
5856                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5857         } else {
5858                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5859         }
5860
5861         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5862         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5863
5864         /* write mirrror control  register */
5865         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5866
5867         /* write pool mirrror control  register */
5868         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5869                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5870                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5871                                 mp_msb);
5872         }
5873         /* write VLAN mirrror control  register */
5874         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5875                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5876                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5877                                 mv_msb);
5878         }
5879
5880         return 0;
5881 }
5882
5883 static int
5884 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5885 {
5886         int mr_ctl = 0;
5887         uint32_t lsb_val = 0;
5888         uint32_t msb_val = 0;
5889         const uint8_t rule_mr_offset = 4;
5890
5891         struct ixgbe_hw *hw =
5892                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5893         struct ixgbe_mirror_info *mr_info =
5894                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5895
5896         if (ixgbe_vt_check(hw) < 0)
5897                 return -ENOTSUP;
5898
5899         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5900                 return -EINVAL;
5901
5902         memset(&mr_info->mr_conf[rule_id], 0,
5903                sizeof(struct rte_eth_mirror_conf));
5904
5905         /* clear PFVMCTL register */
5906         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5907
5908         /* clear pool mask register */
5909         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5910         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5911
5912         /* clear vlan mask register */
5913         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5914         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5915
5916         return 0;
5917 }
5918
5919 static int
5920 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5921 {
5922         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5923         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5924         struct ixgbe_interrupt *intr =
5925                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5926         struct ixgbe_hw *hw =
5927                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5928         uint32_t vec = IXGBE_MISC_VEC_ID;
5929
5930         if (rte_intr_allow_others(intr_handle))
5931                 vec = IXGBE_RX_VEC_START;
5932         intr->mask |= (1 << vec);
5933         RTE_SET_USED(queue_id);
5934         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5935
5936         rte_intr_ack(intr_handle);
5937
5938         return 0;
5939 }
5940
5941 static int
5942 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5943 {
5944         struct ixgbe_interrupt *intr =
5945                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5946         struct ixgbe_hw *hw =
5947                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5948         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5949         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5950         uint32_t vec = IXGBE_MISC_VEC_ID;
5951
5952         if (rte_intr_allow_others(intr_handle))
5953                 vec = IXGBE_RX_VEC_START;
5954         intr->mask &= ~(1 << vec);
5955         RTE_SET_USED(queue_id);
5956         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, intr->mask);
5957
5958         return 0;
5959 }
5960
5961 static int
5962 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5963 {
5964         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5965         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5966         uint32_t mask;
5967         struct ixgbe_hw *hw =
5968                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5969         struct ixgbe_interrupt *intr =
5970                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5971
5972         if (queue_id < 16) {
5973                 ixgbe_disable_intr(hw);
5974                 intr->mask |= (1 << queue_id);
5975                 ixgbe_enable_intr(dev);
5976         } else if (queue_id < 32) {
5977                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5978                 mask &= (1 << queue_id);
5979                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5980         } else if (queue_id < 64) {
5981                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5982                 mask &= (1 << (queue_id - 32));
5983                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5984         }
5985         rte_intr_ack(intr_handle);
5986
5987         return 0;
5988 }
5989
5990 static int
5991 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5992 {
5993         uint32_t mask;
5994         struct ixgbe_hw *hw =
5995                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5996         struct ixgbe_interrupt *intr =
5997                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5998
5999         if (queue_id < 16) {
6000                 ixgbe_disable_intr(hw);
6001                 intr->mask &= ~(1 << queue_id);
6002                 ixgbe_enable_intr(dev);
6003         } else if (queue_id < 32) {
6004                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
6005                 mask &= ~(1 << queue_id);
6006                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
6007         } else if (queue_id < 64) {
6008                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
6009                 mask &= ~(1 << (queue_id - 32));
6010                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
6011         }
6012
6013         return 0;
6014 }
6015
6016 static void
6017 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6018                      uint8_t queue, uint8_t msix_vector)
6019 {
6020         uint32_t tmp, idx;
6021
6022         if (direction == -1) {
6023                 /* other causes */
6024                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6025                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
6026                 tmp &= ~0xFF;
6027                 tmp |= msix_vector;
6028                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
6029         } else {
6030                 /* rx or tx cause */
6031                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6032                 idx = ((16 * (queue & 1)) + (8 * direction));
6033                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
6034                 tmp &= ~(0xFF << idx);
6035                 tmp |= (msix_vector << idx);
6036                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
6037         }
6038 }
6039
6040 /**
6041  * set the IVAR registers, mapping interrupt causes to vectors
6042  * @param hw
6043  *  pointer to ixgbe_hw struct
6044  * @direction
6045  *  0 for Rx, 1 for Tx, -1 for other causes
6046  * @queue
6047  *  queue to map the corresponding interrupt to
6048  * @msix_vector
6049  *  the vector to map to the corresponding queue
6050  */
6051 static void
6052 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
6053                    uint8_t queue, uint8_t msix_vector)
6054 {
6055         uint32_t tmp, idx;
6056
6057         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
6058         if (hw->mac.type == ixgbe_mac_82598EB) {
6059                 if (direction == -1)
6060                         direction = 0;
6061                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
6062                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
6063                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
6064                 tmp |= (msix_vector << (8 * (queue & 0x3)));
6065                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
6066         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
6067                         (hw->mac.type == ixgbe_mac_X540) ||
6068                         (hw->mac.type == ixgbe_mac_X550) ||
6069                         (hw->mac.type == ixgbe_mac_X550EM_x)) {
6070                 if (direction == -1) {
6071                         /* other causes */
6072                         idx = ((queue & 1) * 8);
6073                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
6074                         tmp &= ~(0xFF << idx);
6075                         tmp |= (msix_vector << idx);
6076                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
6077                 } else {
6078                         /* rx or tx causes */
6079                         idx = ((16 * (queue & 1)) + (8 * direction));
6080                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
6081                         tmp &= ~(0xFF << idx);
6082                         tmp |= (msix_vector << idx);
6083                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
6084                 }
6085         }
6086 }
6087
6088 static void
6089 ixgbevf_configure_msix(struct rte_eth_dev *dev)
6090 {
6091         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6092         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6093         struct ixgbe_hw *hw =
6094                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6095         uint32_t q_idx;
6096         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
6097         uint32_t base = IXGBE_MISC_VEC_ID;
6098
6099         /* Configure VF other cause ivar */
6100         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
6101
6102         /* won't configure msix register if no mapping is done
6103          * between intr vector and event fd.
6104          */
6105         if (!rte_intr_dp_is_en(intr_handle))
6106                 return;
6107
6108         if (rte_intr_allow_others(intr_handle)) {
6109                 base = IXGBE_RX_VEC_START;
6110                 vector_idx = IXGBE_RX_VEC_START;
6111         }
6112
6113         /* Configure all RX queues of VF */
6114         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
6115                 /* Force all queue use vector 0,
6116                  * as IXGBE_VF_MAXMSIVECOTR = 1
6117                  */
6118                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
6119                 intr_handle->intr_vec[q_idx] = vector_idx;
6120                 if (vector_idx < base + intr_handle->nb_efd - 1)
6121                         vector_idx++;
6122         }
6123
6124         /* As RX queue setting above show, all queues use the vector 0.
6125          * Set only the ITR value of IXGBE_MISC_VEC_ID.
6126          */
6127         IXGBE_WRITE_REG(hw, IXGBE_VTEITR(IXGBE_MISC_VEC_ID),
6128                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6129                         | IXGBE_EITR_CNT_WDIS);
6130 }
6131
6132 /**
6133  * Sets up the hardware to properly generate MSI-X interrupts
6134  * @hw
6135  *  board private structure
6136  */
6137 static void
6138 ixgbe_configure_msix(struct rte_eth_dev *dev)
6139 {
6140         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
6141         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
6142         struct ixgbe_hw *hw =
6143                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6144         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
6145         uint32_t vec = IXGBE_MISC_VEC_ID;
6146         uint32_t mask;
6147         uint32_t gpie;
6148
6149         /* won't configure msix register if no mapping is done
6150          * between intr vector and event fd
6151          * but if misx has been enabled already, need to configure
6152          * auto clean, auto mask and throttling.
6153          */
6154         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6155         if (!rte_intr_dp_is_en(intr_handle) &&
6156             !(gpie & (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT)))
6157                 return;
6158
6159         if (rte_intr_allow_others(intr_handle))
6160                 vec = base = IXGBE_RX_VEC_START;
6161
6162         /* setup GPIE for MSI-x mode */
6163         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
6164         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
6165                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
6166         /* auto clearing and auto setting corresponding bits in EIMS
6167          * when MSI-X interrupt is triggered
6168          */
6169         if (hw->mac.type == ixgbe_mac_82598EB) {
6170                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
6171         } else {
6172                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
6173                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
6174         }
6175         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
6176
6177         /* Populate the IVAR table and set the ITR values to the
6178          * corresponding register.
6179          */
6180         if (rte_intr_dp_is_en(intr_handle)) {
6181                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
6182                         queue_id++) {
6183                         /* by default, 1:1 mapping */
6184                         ixgbe_set_ivar_map(hw, 0, queue_id, vec);
6185                         intr_handle->intr_vec[queue_id] = vec;
6186                         if (vec < base + intr_handle->nb_efd - 1)
6187                                 vec++;
6188                 }
6189
6190                 switch (hw->mac.type) {
6191                 case ixgbe_mac_82598EB:
6192                         ixgbe_set_ivar_map(hw, -1,
6193                                            IXGBE_IVAR_OTHER_CAUSES_INDEX,
6194                                            IXGBE_MISC_VEC_ID);
6195                         break;
6196                 case ixgbe_mac_82599EB:
6197                 case ixgbe_mac_X540:
6198                 case ixgbe_mac_X550:
6199                 case ixgbe_mac_X550EM_x:
6200                         ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
6201                         break;
6202                 default:
6203                         break;
6204                 }
6205         }
6206         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
6207                         IXGBE_EITR_INTERVAL_US(IXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
6208                         | IXGBE_EITR_CNT_WDIS);
6209
6210         /* set up to autoclear timer, and the vectors */
6211         mask = IXGBE_EIMS_ENABLE_MASK;
6212         mask &= ~(IXGBE_EIMS_OTHER |
6213                   IXGBE_EIMS_MAILBOX |
6214                   IXGBE_EIMS_LSC);
6215
6216         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
6217 }
6218
6219 int
6220 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
6221                            uint16_t queue_idx, uint16_t tx_rate)
6222 {
6223         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6224         struct rte_eth_rxmode *rxmode;
6225         uint32_t rf_dec, rf_int;
6226         uint32_t bcnrc_val;
6227         uint16_t link_speed = dev->data->dev_link.link_speed;
6228
6229         if (queue_idx >= hw->mac.max_tx_queues)
6230                 return -EINVAL;
6231
6232         if (tx_rate != 0) {
6233                 /* Calculate the rate factor values to set */
6234                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
6235                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
6236                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
6237
6238                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
6239                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
6240                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
6241                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
6242         } else {
6243                 bcnrc_val = 0;
6244         }
6245
6246         rxmode = &dev->data->dev_conf.rxmode;
6247         /*
6248          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
6249          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
6250          * set as 0x4.
6251          */
6252         if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
6253             (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
6254                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6255                         IXGBE_MMW_SIZE_JUMBO_FRAME);
6256         else
6257                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
6258                         IXGBE_MMW_SIZE_DEFAULT);
6259
6260         /* Set RTTBCNRC of queue X */
6261         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
6262         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
6263         IXGBE_WRITE_FLUSH(hw);
6264
6265         return 0;
6266 }
6267
6268 static int
6269 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
6270                      __rte_unused uint32_t index,
6271                      __rte_unused uint32_t pool)
6272 {
6273         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6274         int diag;
6275
6276         /*
6277          * On a 82599 VF, adding again the same MAC addr is not an idempotent
6278          * operation. Trap this case to avoid exhausting the [very limited]
6279          * set of PF resources used to store VF MAC addresses.
6280          */
6281         if (memcmp(hw->mac.perm_addr, mac_addr,
6282                         sizeof(struct rte_ether_addr)) == 0)
6283                 return -1;
6284         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6285         if (diag != 0)
6286                 PMD_DRV_LOG(ERR, "Unable to add MAC address "
6287                             "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
6288                             mac_addr->addr_bytes[0],
6289                             mac_addr->addr_bytes[1],
6290                             mac_addr->addr_bytes[2],
6291                             mac_addr->addr_bytes[3],
6292                             mac_addr->addr_bytes[4],
6293                             mac_addr->addr_bytes[5],
6294                             diag);
6295         return diag;
6296 }
6297
6298 static void
6299 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
6300 {
6301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6302         struct rte_ether_addr *perm_addr =
6303                 (struct rte_ether_addr *)hw->mac.perm_addr;
6304         struct rte_ether_addr *mac_addr;
6305         uint32_t i;
6306         int diag;
6307
6308         /*
6309          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
6310          * not support the deletion of a given MAC address.
6311          * Instead, it imposes to delete all MAC addresses, then to add again
6312          * all MAC addresses with the exception of the one to be deleted.
6313          */
6314         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
6315
6316         /*
6317          * Add again all MAC addresses, with the exception of the deleted one
6318          * and of the permanent MAC address.
6319          */
6320         for (i = 0, mac_addr = dev->data->mac_addrs;
6321              i < hw->mac.num_rar_entries; i++, mac_addr++) {
6322                 /* Skip the deleted MAC address */
6323                 if (i == index)
6324                         continue;
6325                 /* Skip NULL MAC addresses */
6326                 if (rte_is_zero_ether_addr(mac_addr))
6327                         continue;
6328                 /* Skip the permanent MAC address */
6329                 if (memcmp(perm_addr, mac_addr,
6330                                 sizeof(struct rte_ether_addr)) == 0)
6331                         continue;
6332                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
6333                 if (diag != 0)
6334                         PMD_DRV_LOG(ERR,
6335                                     "Adding again MAC address "
6336                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
6337                                     "diag=%d",
6338                                     mac_addr->addr_bytes[0],
6339                                     mac_addr->addr_bytes[1],
6340                                     mac_addr->addr_bytes[2],
6341                                     mac_addr->addr_bytes[3],
6342                                     mac_addr->addr_bytes[4],
6343                                     mac_addr->addr_bytes[5],
6344                                     diag);
6345         }
6346 }
6347
6348 static int
6349 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
6350                         struct rte_ether_addr *addr)
6351 {
6352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6353
6354         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
6355
6356         return 0;
6357 }
6358
6359 int
6360 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
6361                         struct rte_eth_syn_filter *filter,
6362                         bool add)
6363 {
6364         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6365         struct ixgbe_filter_info *filter_info =
6366                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6367         uint32_t syn_info;
6368         uint32_t synqf;
6369
6370         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6371                 return -EINVAL;
6372
6373         syn_info = filter_info->syn_info;
6374
6375         if (add) {
6376                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
6377                         return -EINVAL;
6378                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
6379                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
6380
6381                 if (filter->hig_pri)
6382                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
6383                 else
6384                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
6385         } else {
6386                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6387                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
6388                         return -ENOENT;
6389                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
6390         }
6391
6392         filter_info->syn_info = synqf;
6393         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6394         IXGBE_WRITE_FLUSH(hw);
6395         return 0;
6396 }
6397
6398
6399 static inline enum ixgbe_5tuple_protocol
6400 convert_protocol_type(uint8_t protocol_value)
6401 {
6402         if (protocol_value == IPPROTO_TCP)
6403                 return IXGBE_FILTER_PROTOCOL_TCP;
6404         else if (protocol_value == IPPROTO_UDP)
6405                 return IXGBE_FILTER_PROTOCOL_UDP;
6406         else if (protocol_value == IPPROTO_SCTP)
6407                 return IXGBE_FILTER_PROTOCOL_SCTP;
6408         else
6409                 return IXGBE_FILTER_PROTOCOL_NONE;
6410 }
6411
6412 /* inject a 5-tuple filter to HW */
6413 static inline void
6414 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6415                            struct ixgbe_5tuple_filter *filter)
6416 {
6417         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6418         int i;
6419         uint32_t ftqf, sdpqf;
6420         uint32_t l34timir = 0;
6421         uint8_t mask = 0xff;
6422
6423         i = filter->index;
6424
6425         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6426                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6427         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6428
6429         ftqf = (uint32_t)(filter->filter_info.proto &
6430                 IXGBE_FTQF_PROTOCOL_MASK);
6431         ftqf |= (uint32_t)((filter->filter_info.priority &
6432                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6433         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6434                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6435         if (filter->filter_info.dst_ip_mask == 0)
6436                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6437         if (filter->filter_info.src_port_mask == 0)
6438                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6439         if (filter->filter_info.dst_port_mask == 0)
6440                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6441         if (filter->filter_info.proto_mask == 0)
6442                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6443         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6444         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6445         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6446
6447         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6448         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6449         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6450         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6451
6452         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6453         l34timir |= (uint32_t)(filter->queue <<
6454                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6455         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6456 }
6457
6458 /*
6459  * add a 5tuple filter
6460  *
6461  * @param
6462  * dev: Pointer to struct rte_eth_dev.
6463  * index: the index the filter allocates.
6464  * filter: ponter to the filter that will be added.
6465  * rx_queue: the queue id the filter assigned to.
6466  *
6467  * @return
6468  *    - On success, zero.
6469  *    - On failure, a negative value.
6470  */
6471 static int
6472 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6473                         struct ixgbe_5tuple_filter *filter)
6474 {
6475         struct ixgbe_filter_info *filter_info =
6476                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6477         int i, idx, shift;
6478
6479         /*
6480          * look for an unused 5tuple filter index,
6481          * and insert the filter to list.
6482          */
6483         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6484                 idx = i / (sizeof(uint32_t) * NBBY);
6485                 shift = i % (sizeof(uint32_t) * NBBY);
6486                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6487                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6488                         filter->index = i;
6489                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6490                                           filter,
6491                                           entries);
6492                         break;
6493                 }
6494         }
6495         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6496                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6497                 return -ENOSYS;
6498         }
6499
6500         ixgbe_inject_5tuple_filter(dev, filter);
6501
6502         return 0;
6503 }
6504
6505 /*
6506  * remove a 5tuple filter
6507  *
6508  * @param
6509  * dev: Pointer to struct rte_eth_dev.
6510  * filter: the pointer of the filter will be removed.
6511  */
6512 static void
6513 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6514                         struct ixgbe_5tuple_filter *filter)
6515 {
6516         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6517         struct ixgbe_filter_info *filter_info =
6518                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6519         uint16_t index = filter->index;
6520
6521         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6522                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6523         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6524         rte_free(filter);
6525
6526         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6527         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6528         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6529         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6530         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6531 }
6532
6533 static int
6534 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6535 {
6536         struct ixgbe_hw *hw;
6537         uint32_t max_frame = mtu + IXGBE_ETH_OVERHEAD;
6538         struct rte_eth_dev_data *dev_data = dev->data;
6539
6540         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6541
6542         if (mtu < RTE_ETHER_MIN_MTU ||
6543                         max_frame > RTE_ETHER_MAX_JUMBO_FRAME_LEN)
6544                 return -EINVAL;
6545
6546         /* If device is started, refuse mtu that requires the support of
6547          * scattered packets when this feature has not been enabled before.
6548          */
6549         if (dev_data->dev_started && !dev_data->scattered_rx &&
6550             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6551              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
6552                 PMD_INIT_LOG(ERR, "Stop port first.");
6553                 return -EINVAL;
6554         }
6555
6556         /*
6557          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6558          * request of the version 2.0 of the mailbox API.
6559          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6560          * of the mailbox API.
6561          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6562          * prior to 3.11.33 which contains the following change:
6563          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6564          */
6565         ixgbevf_rlpml_set_vf(hw, max_frame);
6566
6567         /* update max frame size */
6568         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6569         return 0;
6570 }
6571
6572 static inline struct ixgbe_5tuple_filter *
6573 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6574                         struct ixgbe_5tuple_filter_info *key)
6575 {
6576         struct ixgbe_5tuple_filter *it;
6577
6578         TAILQ_FOREACH(it, filter_list, entries) {
6579                 if (memcmp(key, &it->filter_info,
6580                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6581                         return it;
6582                 }
6583         }
6584         return NULL;
6585 }
6586
6587 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6588 static inline int
6589 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6590                         struct ixgbe_5tuple_filter_info *filter_info)
6591 {
6592         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6593                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6594                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6595                 return -EINVAL;
6596
6597         switch (filter->dst_ip_mask) {
6598         case UINT32_MAX:
6599                 filter_info->dst_ip_mask = 0;
6600                 filter_info->dst_ip = filter->dst_ip;
6601                 break;
6602         case 0:
6603                 filter_info->dst_ip_mask = 1;
6604                 break;
6605         default:
6606                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6607                 return -EINVAL;
6608         }
6609
6610         switch (filter->src_ip_mask) {
6611         case UINT32_MAX:
6612                 filter_info->src_ip_mask = 0;
6613                 filter_info->src_ip = filter->src_ip;
6614                 break;
6615         case 0:
6616                 filter_info->src_ip_mask = 1;
6617                 break;
6618         default:
6619                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6620                 return -EINVAL;
6621         }
6622
6623         switch (filter->dst_port_mask) {
6624         case UINT16_MAX:
6625                 filter_info->dst_port_mask = 0;
6626                 filter_info->dst_port = filter->dst_port;
6627                 break;
6628         case 0:
6629                 filter_info->dst_port_mask = 1;
6630                 break;
6631         default:
6632                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6633                 return -EINVAL;
6634         }
6635
6636         switch (filter->src_port_mask) {
6637         case UINT16_MAX:
6638                 filter_info->src_port_mask = 0;
6639                 filter_info->src_port = filter->src_port;
6640                 break;
6641         case 0:
6642                 filter_info->src_port_mask = 1;
6643                 break;
6644         default:
6645                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6646                 return -EINVAL;
6647         }
6648
6649         switch (filter->proto_mask) {
6650         case UINT8_MAX:
6651                 filter_info->proto_mask = 0;
6652                 filter_info->proto =
6653                         convert_protocol_type(filter->proto);
6654                 break;
6655         case 0:
6656                 filter_info->proto_mask = 1;
6657                 break;
6658         default:
6659                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6660                 return -EINVAL;
6661         }
6662
6663         filter_info->priority = (uint8_t)filter->priority;
6664         return 0;
6665 }
6666
6667 /*
6668  * add or delete a ntuple filter
6669  *
6670  * @param
6671  * dev: Pointer to struct rte_eth_dev.
6672  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6673  * add: if true, add filter, if false, remove filter
6674  *
6675  * @return
6676  *    - On success, zero.
6677  *    - On failure, a negative value.
6678  */
6679 int
6680 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6681                         struct rte_eth_ntuple_filter *ntuple_filter,
6682                         bool add)
6683 {
6684         struct ixgbe_filter_info *filter_info =
6685                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6686         struct ixgbe_5tuple_filter_info filter_5tuple;
6687         struct ixgbe_5tuple_filter *filter;
6688         int ret;
6689
6690         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6691                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6692                 return -EINVAL;
6693         }
6694
6695         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6696         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6697         if (ret < 0)
6698                 return ret;
6699
6700         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6701                                          &filter_5tuple);
6702         if (filter != NULL && add) {
6703                 PMD_DRV_LOG(ERR, "filter exists.");
6704                 return -EEXIST;
6705         }
6706         if (filter == NULL && !add) {
6707                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6708                 return -ENOENT;
6709         }
6710
6711         if (add) {
6712                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6713                                 sizeof(struct ixgbe_5tuple_filter), 0);
6714                 if (filter == NULL)
6715                         return -ENOMEM;
6716                 rte_memcpy(&filter->filter_info,
6717                                  &filter_5tuple,
6718                                  sizeof(struct ixgbe_5tuple_filter_info));
6719                 filter->queue = ntuple_filter->queue;
6720                 ret = ixgbe_add_5tuple_filter(dev, filter);
6721                 if (ret < 0) {
6722                         rte_free(filter);
6723                         return ret;
6724                 }
6725         } else
6726                 ixgbe_remove_5tuple_filter(dev, filter);
6727
6728         return 0;
6729 }
6730
6731 int
6732 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6733                         struct rte_eth_ethertype_filter *filter,
6734                         bool add)
6735 {
6736         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6737         struct ixgbe_filter_info *filter_info =
6738                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6739         uint32_t etqf = 0;
6740         uint32_t etqs = 0;
6741         int ret;
6742         struct ixgbe_ethertype_filter ethertype_filter;
6743
6744         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6745                 return -EINVAL;
6746
6747         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
6748                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
6749                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6750                         " ethertype filter.", filter->ether_type);
6751                 return -EINVAL;
6752         }
6753
6754         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6755                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6756                 return -EINVAL;
6757         }
6758         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6759                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6760                 return -EINVAL;
6761         }
6762
6763         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6764         if (ret >= 0 && add) {
6765                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6766                             filter->ether_type);
6767                 return -EEXIST;
6768         }
6769         if (ret < 0 && !add) {
6770                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6771                             filter->ether_type);
6772                 return -ENOENT;
6773         }
6774
6775         if (add) {
6776                 etqf = IXGBE_ETQF_FILTER_EN;
6777                 etqf |= (uint32_t)filter->ether_type;
6778                 etqs |= (uint32_t)((filter->queue <<
6779                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6780                                     IXGBE_ETQS_RX_QUEUE);
6781                 etqs |= IXGBE_ETQS_QUEUE_EN;
6782
6783                 ethertype_filter.ethertype = filter->ether_type;
6784                 ethertype_filter.etqf = etqf;
6785                 ethertype_filter.etqs = etqs;
6786                 ethertype_filter.conf = FALSE;
6787                 ret = ixgbe_ethertype_filter_insert(filter_info,
6788                                                     &ethertype_filter);
6789                 if (ret < 0) {
6790                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6791                         return -ENOSPC;
6792                 }
6793         } else {
6794                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6795                 if (ret < 0)
6796                         return -ENOSYS;
6797         }
6798         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6799         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6800         IXGBE_WRITE_FLUSH(hw);
6801
6802         return 0;
6803 }
6804
6805 static int
6806 ixgbe_dev_filter_ctrl(__rte_unused struct rte_eth_dev *dev,
6807                      enum rte_filter_type filter_type,
6808                      enum rte_filter_op filter_op,
6809                      void *arg)
6810 {
6811         int ret = 0;
6812
6813         switch (filter_type) {
6814         case RTE_ETH_FILTER_GENERIC:
6815                 if (filter_op != RTE_ETH_FILTER_GET)
6816                         return -EINVAL;
6817                 *(const void **)arg = &ixgbe_flow_ops;
6818                 break;
6819         default:
6820                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6821                                                         filter_type);
6822                 ret = -EINVAL;
6823                 break;
6824         }
6825
6826         return ret;
6827 }
6828
6829 static u8 *
6830 ixgbe_dev_addr_list_itr(__rte_unused struct ixgbe_hw *hw,
6831                         u8 **mc_addr_ptr, u32 *vmdq)
6832 {
6833         u8 *mc_addr;
6834
6835         *vmdq = 0;
6836         mc_addr = *mc_addr_ptr;
6837         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
6838         return mc_addr;
6839 }
6840
6841 static int
6842 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6843                           struct rte_ether_addr *mc_addr_set,
6844                           uint32_t nb_mc_addr)
6845 {
6846         struct ixgbe_hw *hw;
6847         u8 *mc_addr_list;
6848
6849         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6850         mc_addr_list = (u8 *)mc_addr_set;
6851         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6852                                          ixgbe_dev_addr_list_itr, TRUE);
6853 }
6854
6855 static uint64_t
6856 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6857 {
6858         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         uint64_t systime_cycles;
6860
6861         switch (hw->mac.type) {
6862         case ixgbe_mac_X550:
6863         case ixgbe_mac_X550EM_x:
6864         case ixgbe_mac_X550EM_a:
6865                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6866                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6867                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6868                                 * NSEC_PER_SEC;
6869                 break;
6870         default:
6871                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6872                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6873                                 << 32;
6874         }
6875
6876         return systime_cycles;
6877 }
6878
6879 static uint64_t
6880 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6881 {
6882         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6883         uint64_t rx_tstamp_cycles;
6884
6885         switch (hw->mac.type) {
6886         case ixgbe_mac_X550:
6887         case ixgbe_mac_X550EM_x:
6888         case ixgbe_mac_X550EM_a:
6889                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6890                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6891                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6892                                 * NSEC_PER_SEC;
6893                 break;
6894         default:
6895                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6896                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6897                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6898                                 << 32;
6899         }
6900
6901         return rx_tstamp_cycles;
6902 }
6903
6904 static uint64_t
6905 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6906 {
6907         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6908         uint64_t tx_tstamp_cycles;
6909
6910         switch (hw->mac.type) {
6911         case ixgbe_mac_X550:
6912         case ixgbe_mac_X550EM_x:
6913         case ixgbe_mac_X550EM_a:
6914                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6915                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6916                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6917                                 * NSEC_PER_SEC;
6918                 break;
6919         default:
6920                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6921                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6922                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6923                                 << 32;
6924         }
6925
6926         return tx_tstamp_cycles;
6927 }
6928
6929 static void
6930 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6931 {
6932         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6933         struct ixgbe_adapter *adapter = dev->data->dev_private;
6934         struct rte_eth_link link;
6935         uint32_t incval = 0;
6936         uint32_t shift = 0;
6937
6938         /* Get current link speed. */
6939         ixgbe_dev_link_update(dev, 1);
6940         rte_eth_linkstatus_get(dev, &link);
6941
6942         switch (link.link_speed) {
6943         case ETH_SPEED_NUM_100M:
6944                 incval = IXGBE_INCVAL_100;
6945                 shift = IXGBE_INCVAL_SHIFT_100;
6946                 break;
6947         case ETH_SPEED_NUM_1G:
6948                 incval = IXGBE_INCVAL_1GB;
6949                 shift = IXGBE_INCVAL_SHIFT_1GB;
6950                 break;
6951         case ETH_SPEED_NUM_10G:
6952         default:
6953                 incval = IXGBE_INCVAL_10GB;
6954                 shift = IXGBE_INCVAL_SHIFT_10GB;
6955                 break;
6956         }
6957
6958         switch (hw->mac.type) {
6959         case ixgbe_mac_X550:
6960         case ixgbe_mac_X550EM_x:
6961         case ixgbe_mac_X550EM_a:
6962                 /* Independent of link speed. */
6963                 incval = 1;
6964                 /* Cycles read will be interpreted as ns. */
6965                 shift = 0;
6966                 /* Fall-through */
6967         case ixgbe_mac_X540:
6968                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6969                 break;
6970         case ixgbe_mac_82599EB:
6971                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6972                 shift -= IXGBE_INCVAL_SHIFT_82599;
6973                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6974                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6975                 break;
6976         default:
6977                 /* Not supported. */
6978                 return;
6979         }
6980
6981         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6982         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6983         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6984
6985         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6986         adapter->systime_tc.cc_shift = shift;
6987         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6988
6989         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6990         adapter->rx_tstamp_tc.cc_shift = shift;
6991         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6992
6993         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6994         adapter->tx_tstamp_tc.cc_shift = shift;
6995         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6996 }
6997
6998 static int
6999 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
7000 {
7001         struct ixgbe_adapter *adapter = dev->data->dev_private;
7002
7003         adapter->systime_tc.nsec += delta;
7004         adapter->rx_tstamp_tc.nsec += delta;
7005         adapter->tx_tstamp_tc.nsec += delta;
7006
7007         return 0;
7008 }
7009
7010 static int
7011 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
7012 {
7013         uint64_t ns;
7014         struct ixgbe_adapter *adapter = dev->data->dev_private;
7015
7016         ns = rte_timespec_to_ns(ts);
7017         /* Set the timecounters to a new value. */
7018         adapter->systime_tc.nsec = ns;
7019         adapter->rx_tstamp_tc.nsec = ns;
7020         adapter->tx_tstamp_tc.nsec = ns;
7021
7022         return 0;
7023 }
7024
7025 static int
7026 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
7027 {
7028         uint64_t ns, systime_cycles;
7029         struct ixgbe_adapter *adapter = dev->data->dev_private;
7030
7031         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
7032         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
7033         *ts = rte_ns_to_timespec(ns);
7034
7035         return 0;
7036 }
7037
7038 static int
7039 ixgbe_timesync_enable(struct rte_eth_dev *dev)
7040 {
7041         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7042         uint32_t tsync_ctl;
7043         uint32_t tsauxc;
7044
7045         /* Stop the timesync system time. */
7046         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
7047         /* Reset the timesync system time value. */
7048         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
7049         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
7050
7051         /* Enable system time for platforms where it isn't on by default. */
7052         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
7053         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
7054         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
7055
7056         ixgbe_start_timecounters(dev);
7057
7058         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7059         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
7060                         (RTE_ETHER_TYPE_1588 |
7061                          IXGBE_ETQF_FILTER_EN |
7062                          IXGBE_ETQF_1588));
7063
7064         /* Enable timestamping of received PTP packets. */
7065         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7066         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
7067         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7068
7069         /* Enable timestamping of transmitted PTP packets. */
7070         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7071         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
7072         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7073
7074         IXGBE_WRITE_FLUSH(hw);
7075
7076         return 0;
7077 }
7078
7079 static int
7080 ixgbe_timesync_disable(struct rte_eth_dev *dev)
7081 {
7082         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7083         uint32_t tsync_ctl;
7084
7085         /* Disable timestamping of transmitted PTP packets. */
7086         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7087         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
7088         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
7089
7090         /* Disable timestamping of received PTP packets. */
7091         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7092         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
7093         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
7094
7095         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
7096         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
7097
7098         /* Stop incrementating the System Time registers. */
7099         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
7100
7101         return 0;
7102 }
7103
7104 static int
7105 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7106                                  struct timespec *timestamp,
7107                                  uint32_t flags __rte_unused)
7108 {
7109         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7110         struct ixgbe_adapter *adapter = dev->data->dev_private;
7111         uint32_t tsync_rxctl;
7112         uint64_t rx_tstamp_cycles;
7113         uint64_t ns;
7114
7115         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
7116         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
7117                 return -EINVAL;
7118
7119         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
7120         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
7121         *timestamp = rte_ns_to_timespec(ns);
7122
7123         return  0;
7124 }
7125
7126 static int
7127 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7128                                  struct timespec *timestamp)
7129 {
7130         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7131         struct ixgbe_adapter *adapter = dev->data->dev_private;
7132         uint32_t tsync_txctl;
7133         uint64_t tx_tstamp_cycles;
7134         uint64_t ns;
7135
7136         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
7137         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
7138                 return -EINVAL;
7139
7140         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
7141         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
7142         *timestamp = rte_ns_to_timespec(ns);
7143
7144         return 0;
7145 }
7146
7147 static int
7148 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7149 {
7150         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7151         int count = 0;
7152         int g_ind = 0;
7153         const struct reg_info *reg_group;
7154         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7155                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7156
7157         while ((reg_group = reg_set[g_ind++]))
7158                 count += ixgbe_regs_group_count(reg_group);
7159
7160         return count;
7161 }
7162
7163 static int
7164 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7165 {
7166         int count = 0;
7167         int g_ind = 0;
7168         const struct reg_info *reg_group;
7169
7170         while ((reg_group = ixgbevf_regs[g_ind++]))
7171                 count += ixgbe_regs_group_count(reg_group);
7172
7173         return count;
7174 }
7175
7176 static int
7177 ixgbe_get_regs(struct rte_eth_dev *dev,
7178               struct rte_dev_reg_info *regs)
7179 {
7180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7181         uint32_t *data = regs->data;
7182         int g_ind = 0;
7183         int count = 0;
7184         const struct reg_info *reg_group;
7185         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7186                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7187
7188         if (data == NULL) {
7189                 regs->length = ixgbe_get_reg_length(dev);
7190                 regs->width = sizeof(uint32_t);
7191                 return 0;
7192         }
7193
7194         /* Support only full register dump */
7195         if ((regs->length == 0) ||
7196             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7197                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7198                         hw->device_id;
7199                 while ((reg_group = reg_set[g_ind++]))
7200                         count += ixgbe_read_regs_group(dev, &data[count],
7201                                 reg_group);
7202                 return 0;
7203         }
7204
7205         return -ENOTSUP;
7206 }
7207
7208 static int
7209 ixgbevf_get_regs(struct rte_eth_dev *dev,
7210                 struct rte_dev_reg_info *regs)
7211 {
7212         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7213         uint32_t *data = regs->data;
7214         int g_ind = 0;
7215         int count = 0;
7216         const struct reg_info *reg_group;
7217
7218         if (data == NULL) {
7219                 regs->length = ixgbevf_get_reg_length(dev);
7220                 regs->width = sizeof(uint32_t);
7221                 return 0;
7222         }
7223
7224         /* Support only full register dump */
7225         if ((regs->length == 0) ||
7226             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7227                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7228                         hw->device_id;
7229                 while ((reg_group = ixgbevf_regs[g_ind++]))
7230                         count += ixgbe_read_regs_group(dev, &data[count],
7231                                                       reg_group);
7232                 return 0;
7233         }
7234
7235         return -ENOTSUP;
7236 }
7237
7238 static int
7239 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7240 {
7241         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7242
7243         /* Return unit is byte count */
7244         return hw->eeprom.word_size * 2;
7245 }
7246
7247 static int
7248 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7249                 struct rte_dev_eeprom_info *in_eeprom)
7250 {
7251         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7252         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7253         uint16_t *data = in_eeprom->data;
7254         int first, length;
7255
7256         first = in_eeprom->offset >> 1;
7257         length = in_eeprom->length >> 1;
7258         if ((first > hw->eeprom.word_size) ||
7259             ((first + length) > hw->eeprom.word_size))
7260                 return -EINVAL;
7261
7262         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7263
7264         return eeprom->ops.read_buffer(hw, first, length, data);
7265 }
7266
7267 static int
7268 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7269                 struct rte_dev_eeprom_info *in_eeprom)
7270 {
7271         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7272         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7273         uint16_t *data = in_eeprom->data;
7274         int first, length;
7275
7276         first = in_eeprom->offset >> 1;
7277         length = in_eeprom->length >> 1;
7278         if ((first > hw->eeprom.word_size) ||
7279             ((first + length) > hw->eeprom.word_size))
7280                 return -EINVAL;
7281
7282         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7283
7284         return eeprom->ops.write_buffer(hw,  first, length, data);
7285 }
7286
7287 static int
7288 ixgbe_get_module_info(struct rte_eth_dev *dev,
7289                       struct rte_eth_dev_module_info *modinfo)
7290 {
7291         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7292         uint32_t status;
7293         uint8_t sff8472_rev, addr_mode;
7294         bool page_swap = false;
7295
7296         /* Check whether we support SFF-8472 or not */
7297         status = hw->phy.ops.read_i2c_eeprom(hw,
7298                                              IXGBE_SFF_SFF_8472_COMP,
7299                                              &sff8472_rev);
7300         if (status != 0)
7301                 return -EIO;
7302
7303         /* addressing mode is not supported */
7304         status = hw->phy.ops.read_i2c_eeprom(hw,
7305                                              IXGBE_SFF_SFF_8472_SWAP,
7306                                              &addr_mode);
7307         if (status != 0)
7308                 return -EIO;
7309
7310         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
7311                 PMD_DRV_LOG(ERR,
7312                             "Address change required to access page 0xA2, "
7313                             "but not supported. Please report the module "
7314                             "type to the driver maintainers.");
7315                 page_swap = true;
7316         }
7317
7318         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
7319                 /* We have a SFP, but it does not support SFF-8472 */
7320                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
7321                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
7322         } else {
7323                 /* We have a SFP which supports a revision of SFF-8472. */
7324                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
7325                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
7326         }
7327
7328         return 0;
7329 }
7330
7331 static int
7332 ixgbe_get_module_eeprom(struct rte_eth_dev *dev,
7333                         struct rte_dev_eeprom_info *info)
7334 {
7335         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7336         uint32_t status = IXGBE_ERR_PHY_ADDR_INVALID;
7337         uint8_t databyte = 0xFF;
7338         uint8_t *data = info->data;
7339         uint32_t i = 0;
7340
7341         if (info->length == 0)
7342                 return -EINVAL;
7343
7344         for (i = info->offset; i < info->offset + info->length; i++) {
7345                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
7346                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
7347                 else
7348                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
7349
7350                 if (status != 0)
7351                         return -EIO;
7352
7353                 data[i - info->offset] = databyte;
7354         }
7355
7356         return 0;
7357 }
7358
7359 uint16_t
7360 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7361         switch (mac_type) {
7362         case ixgbe_mac_X550:
7363         case ixgbe_mac_X550EM_x:
7364         case ixgbe_mac_X550EM_a:
7365                 return ETH_RSS_RETA_SIZE_512;
7366         case ixgbe_mac_X550_vf:
7367         case ixgbe_mac_X550EM_x_vf:
7368         case ixgbe_mac_X550EM_a_vf:
7369                 return ETH_RSS_RETA_SIZE_64;
7370         case ixgbe_mac_X540_vf:
7371         case ixgbe_mac_82599_vf:
7372                 return 0;
7373         default:
7374                 return ETH_RSS_RETA_SIZE_128;
7375         }
7376 }
7377
7378 uint32_t
7379 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7380         switch (mac_type) {
7381         case ixgbe_mac_X550:
7382         case ixgbe_mac_X550EM_x:
7383         case ixgbe_mac_X550EM_a:
7384                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7385                         return IXGBE_RETA(reta_idx >> 2);
7386                 else
7387                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7388         case ixgbe_mac_X550_vf:
7389         case ixgbe_mac_X550EM_x_vf:
7390         case ixgbe_mac_X550EM_a_vf:
7391                 return IXGBE_VFRETA(reta_idx >> 2);
7392         default:
7393                 return IXGBE_RETA(reta_idx >> 2);
7394         }
7395 }
7396
7397 uint32_t
7398 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7399         switch (mac_type) {
7400         case ixgbe_mac_X550_vf:
7401         case ixgbe_mac_X550EM_x_vf:
7402         case ixgbe_mac_X550EM_a_vf:
7403                 return IXGBE_VFMRQC;
7404         default:
7405                 return IXGBE_MRQC;
7406         }
7407 }
7408
7409 uint32_t
7410 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7411         switch (mac_type) {
7412         case ixgbe_mac_X550_vf:
7413         case ixgbe_mac_X550EM_x_vf:
7414         case ixgbe_mac_X550EM_a_vf:
7415                 return IXGBE_VFRSSRK(i);
7416         default:
7417                 return IXGBE_RSSRK(i);
7418         }
7419 }
7420
7421 bool
7422 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7423         switch (mac_type) {
7424         case ixgbe_mac_82599_vf:
7425         case ixgbe_mac_X540_vf:
7426                 return 0;
7427         default:
7428                 return 1;
7429         }
7430 }
7431
7432 static int
7433 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7434                         struct rte_eth_dcb_info *dcb_info)
7435 {
7436         struct ixgbe_dcb_config *dcb_config =
7437                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7438         struct ixgbe_dcb_tc_config *tc;
7439         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7440         uint8_t nb_tcs;
7441         uint8_t i, j;
7442
7443         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7444                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7445         else
7446                 dcb_info->nb_tcs = 1;
7447
7448         tc_queue = &dcb_info->tc_queue;
7449         nb_tcs = dcb_info->nb_tcs;
7450
7451         if (dcb_config->vt_mode) { /* vt is enabled*/
7452                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7453                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7454                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7455                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7456                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7457                         for (j = 0; j < nb_tcs; j++) {
7458                                 tc_queue->tc_rxq[0][j].base = j;
7459                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
7460                                 tc_queue->tc_txq[0][j].base = j;
7461                                 tc_queue->tc_txq[0][j].nb_queue = 1;
7462                         }
7463                 } else {
7464                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7465                                 for (j = 0; j < nb_tcs; j++) {
7466                                         tc_queue->tc_rxq[i][j].base =
7467                                                 i * nb_tcs + j;
7468                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
7469                                         tc_queue->tc_txq[i][j].base =
7470                                                 i * nb_tcs + j;
7471                                         tc_queue->tc_txq[i][j].nb_queue = 1;
7472                                 }
7473                         }
7474                 }
7475         } else { /* vt is disabled*/
7476                 struct rte_eth_dcb_rx_conf *rx_conf =
7477                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7478                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7479                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7480                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7481                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7482                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7483                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7484                         }
7485                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7486                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7487                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7488                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7489                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7490                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7491                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7492                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7493                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7494                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7495                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7496                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7497                         }
7498                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7499                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7500                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7501                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7502                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7503                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7504                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7505                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7506                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7507                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7508                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7509                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7510                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7511                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7512                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7513                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7514                 }
7515         }
7516         for (i = 0; i < dcb_info->nb_tcs; i++) {
7517                 tc = &dcb_config->tc_config[i];
7518                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7519         }
7520         return 0;
7521 }
7522
7523 /* Update e-tag ether type */
7524 static int
7525 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7526                             uint16_t ether_type)
7527 {
7528         uint32_t etag_etype;
7529
7530         if (hw->mac.type != ixgbe_mac_X550 &&
7531             hw->mac.type != ixgbe_mac_X550EM_x &&
7532             hw->mac.type != ixgbe_mac_X550EM_a) {
7533                 return -ENOTSUP;
7534         }
7535
7536         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7537         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7538         etag_etype |= ether_type;
7539         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7540         IXGBE_WRITE_FLUSH(hw);
7541
7542         return 0;
7543 }
7544
7545 /* Enable e-tag tunnel */
7546 static int
7547 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7548 {
7549         uint32_t etag_etype;
7550
7551         if (hw->mac.type != ixgbe_mac_X550 &&
7552             hw->mac.type != ixgbe_mac_X550EM_x &&
7553             hw->mac.type != ixgbe_mac_X550EM_a) {
7554                 return -ENOTSUP;
7555         }
7556
7557         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7558         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7559         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7560         IXGBE_WRITE_FLUSH(hw);
7561
7562         return 0;
7563 }
7564
7565 /* Enable l2 tunnel */
7566 static int
7567 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7568                            enum rte_eth_tunnel_type l2_tunnel_type)
7569 {
7570         int ret = 0;
7571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7572         struct ixgbe_l2_tn_info *l2_tn_info =
7573                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7574
7575         switch (l2_tunnel_type) {
7576         case RTE_L2_TUNNEL_TYPE_E_TAG:
7577                 l2_tn_info->e_tag_en = TRUE;
7578                 ret = ixgbe_e_tag_enable(hw);
7579                 break;
7580         default:
7581                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7582                 ret = -EINVAL;
7583                 break;
7584         }
7585
7586         return ret;
7587 }
7588
7589 /* Disable e-tag tunnel */
7590 static int
7591 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7592 {
7593         uint32_t etag_etype;
7594
7595         if (hw->mac.type != ixgbe_mac_X550 &&
7596             hw->mac.type != ixgbe_mac_X550EM_x &&
7597             hw->mac.type != ixgbe_mac_X550EM_a) {
7598                 return -ENOTSUP;
7599         }
7600
7601         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7602         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7603         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7604         IXGBE_WRITE_FLUSH(hw);
7605
7606         return 0;
7607 }
7608
7609 /* Disable l2 tunnel */
7610 static int
7611 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7612                             enum rte_eth_tunnel_type l2_tunnel_type)
7613 {
7614         int ret = 0;
7615         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7616         struct ixgbe_l2_tn_info *l2_tn_info =
7617                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7618
7619         switch (l2_tunnel_type) {
7620         case RTE_L2_TUNNEL_TYPE_E_TAG:
7621                 l2_tn_info->e_tag_en = FALSE;
7622                 ret = ixgbe_e_tag_disable(hw);
7623                 break;
7624         default:
7625                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7626                 ret = -EINVAL;
7627                 break;
7628         }
7629
7630         return ret;
7631 }
7632
7633 static int
7634 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7635                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7636 {
7637         int ret = 0;
7638         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7639         uint32_t i, rar_entries;
7640         uint32_t rar_low, rar_high;
7641
7642         if (hw->mac.type != ixgbe_mac_X550 &&
7643             hw->mac.type != ixgbe_mac_X550EM_x &&
7644             hw->mac.type != ixgbe_mac_X550EM_a) {
7645                 return -ENOTSUP;
7646         }
7647
7648         rar_entries = ixgbe_get_num_rx_addrs(hw);
7649
7650         for (i = 1; i < rar_entries; i++) {
7651                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7652                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7653                 if ((rar_high & IXGBE_RAH_AV) &&
7654                     (rar_high & IXGBE_RAH_ADTYPE) &&
7655                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7656                      l2_tunnel->tunnel_id)) {
7657                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7658                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7659
7660                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7661
7662                         return ret;
7663                 }
7664         }
7665
7666         return ret;
7667 }
7668
7669 static int
7670 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7671                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7672 {
7673         int ret = 0;
7674         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7675         uint32_t i, rar_entries;
7676         uint32_t rar_low, rar_high;
7677
7678         if (hw->mac.type != ixgbe_mac_X550 &&
7679             hw->mac.type != ixgbe_mac_X550EM_x &&
7680             hw->mac.type != ixgbe_mac_X550EM_a) {
7681                 return -ENOTSUP;
7682         }
7683
7684         /* One entry for one tunnel. Try to remove potential existing entry. */
7685         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7686
7687         rar_entries = ixgbe_get_num_rx_addrs(hw);
7688
7689         for (i = 1; i < rar_entries; i++) {
7690                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7691                 if (rar_high & IXGBE_RAH_AV) {
7692                         continue;
7693                 } else {
7694                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7695                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7696                         rar_low = l2_tunnel->tunnel_id;
7697
7698                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7699                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7700
7701                         return ret;
7702                 }
7703         }
7704
7705         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7706                      " Please remove a rule before adding a new one.");
7707         return -EINVAL;
7708 }
7709
7710 static inline struct ixgbe_l2_tn_filter *
7711 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7712                           struct ixgbe_l2_tn_key *key)
7713 {
7714         int ret;
7715
7716         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7717         if (ret < 0)
7718                 return NULL;
7719
7720         return l2_tn_info->hash_map[ret];
7721 }
7722
7723 static inline int
7724 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7725                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7726 {
7727         int ret;
7728
7729         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7730                                &l2_tn_filter->key);
7731
7732         if (ret < 0) {
7733                 PMD_DRV_LOG(ERR,
7734                             "Failed to insert L2 tunnel filter"
7735                             " to hash table %d!",
7736                             ret);
7737                 return ret;
7738         }
7739
7740         l2_tn_info->hash_map[ret] = l2_tn_filter;
7741
7742         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7743
7744         return 0;
7745 }
7746
7747 static inline int
7748 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7749                           struct ixgbe_l2_tn_key *key)
7750 {
7751         int ret;
7752         struct ixgbe_l2_tn_filter *l2_tn_filter;
7753
7754         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7755
7756         if (ret < 0) {
7757                 PMD_DRV_LOG(ERR,
7758                             "No such L2 tunnel filter to delete %d!",
7759                             ret);
7760                 return ret;
7761         }
7762
7763         l2_tn_filter = l2_tn_info->hash_map[ret];
7764         l2_tn_info->hash_map[ret] = NULL;
7765
7766         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7767         rte_free(l2_tn_filter);
7768
7769         return 0;
7770 }
7771
7772 /* Add l2 tunnel filter */
7773 int
7774 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7775                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7776                                bool restore)
7777 {
7778         int ret;
7779         struct ixgbe_l2_tn_info *l2_tn_info =
7780                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7781         struct ixgbe_l2_tn_key key;
7782         struct ixgbe_l2_tn_filter *node;
7783
7784         if (!restore) {
7785                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7786                 key.tn_id = l2_tunnel->tunnel_id;
7787
7788                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7789
7790                 if (node) {
7791                         PMD_DRV_LOG(ERR,
7792                                     "The L2 tunnel filter already exists!");
7793                         return -EINVAL;
7794                 }
7795
7796                 node = rte_zmalloc("ixgbe_l2_tn",
7797                                    sizeof(struct ixgbe_l2_tn_filter),
7798                                    0);
7799                 if (!node)
7800                         return -ENOMEM;
7801
7802                 rte_memcpy(&node->key,
7803                                  &key,
7804                                  sizeof(struct ixgbe_l2_tn_key));
7805                 node->pool = l2_tunnel->pool;
7806                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7807                 if (ret < 0) {
7808                         rte_free(node);
7809                         return ret;
7810                 }
7811         }
7812
7813         switch (l2_tunnel->l2_tunnel_type) {
7814         case RTE_L2_TUNNEL_TYPE_E_TAG:
7815                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7816                 break;
7817         default:
7818                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7819                 ret = -EINVAL;
7820                 break;
7821         }
7822
7823         if ((!restore) && (ret < 0))
7824                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7825
7826         return ret;
7827 }
7828
7829 /* Delete l2 tunnel filter */
7830 int
7831 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7832                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7833 {
7834         int ret;
7835         struct ixgbe_l2_tn_info *l2_tn_info =
7836                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7837         struct ixgbe_l2_tn_key key;
7838
7839         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7840         key.tn_id = l2_tunnel->tunnel_id;
7841         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7842         if (ret < 0)
7843                 return ret;
7844
7845         switch (l2_tunnel->l2_tunnel_type) {
7846         case RTE_L2_TUNNEL_TYPE_E_TAG:
7847                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7848                 break;
7849         default:
7850                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7851                 ret = -EINVAL;
7852                 break;
7853         }
7854
7855         return ret;
7856 }
7857
7858 static int
7859 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7860 {
7861         int ret = 0;
7862         uint32_t ctrl;
7863         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7864
7865         if (hw->mac.type != ixgbe_mac_X550 &&
7866             hw->mac.type != ixgbe_mac_X550EM_x &&
7867             hw->mac.type != ixgbe_mac_X550EM_a) {
7868                 return -ENOTSUP;
7869         }
7870
7871         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7872         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7873         if (en)
7874                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7875         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7876
7877         return ret;
7878 }
7879
7880 /* Enable l2 tunnel forwarding */
7881 static int
7882 ixgbe_dev_l2_tunnel_forwarding_enable
7883         (struct rte_eth_dev *dev,
7884          enum rte_eth_tunnel_type l2_tunnel_type)
7885 {
7886         struct ixgbe_l2_tn_info *l2_tn_info =
7887                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7888         int ret = 0;
7889
7890         switch (l2_tunnel_type) {
7891         case RTE_L2_TUNNEL_TYPE_E_TAG:
7892                 l2_tn_info->e_tag_fwd_en = TRUE;
7893                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7894                 break;
7895         default:
7896                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7897                 ret = -EINVAL;
7898                 break;
7899         }
7900
7901         return ret;
7902 }
7903
7904 /* Disable l2 tunnel forwarding */
7905 static int
7906 ixgbe_dev_l2_tunnel_forwarding_disable
7907         (struct rte_eth_dev *dev,
7908          enum rte_eth_tunnel_type l2_tunnel_type)
7909 {
7910         struct ixgbe_l2_tn_info *l2_tn_info =
7911                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7912         int ret = 0;
7913
7914         switch (l2_tunnel_type) {
7915         case RTE_L2_TUNNEL_TYPE_E_TAG:
7916                 l2_tn_info->e_tag_fwd_en = FALSE;
7917                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7918                 break;
7919         default:
7920                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7921                 ret = -EINVAL;
7922                 break;
7923         }
7924
7925         return ret;
7926 }
7927
7928 static int
7929 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7930                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7931                              bool en)
7932 {
7933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7934         int ret = 0;
7935         uint32_t vmtir, vmvir;
7936         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7937
7938         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7939                 PMD_DRV_LOG(ERR,
7940                             "VF id %u should be less than %u",
7941                             l2_tunnel->vf_id,
7942                             pci_dev->max_vfs);
7943                 return -EINVAL;
7944         }
7945
7946         if (hw->mac.type != ixgbe_mac_X550 &&
7947             hw->mac.type != ixgbe_mac_X550EM_x &&
7948             hw->mac.type != ixgbe_mac_X550EM_a) {
7949                 return -ENOTSUP;
7950         }
7951
7952         if (en)
7953                 vmtir = l2_tunnel->tunnel_id;
7954         else
7955                 vmtir = 0;
7956
7957         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7958
7959         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7960         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7961         if (en)
7962                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7963         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7964
7965         return ret;
7966 }
7967
7968 /* Enable l2 tunnel tag insertion */
7969 static int
7970 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7971                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7972 {
7973         int ret = 0;
7974
7975         switch (l2_tunnel->l2_tunnel_type) {
7976         case RTE_L2_TUNNEL_TYPE_E_TAG:
7977                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7978                 break;
7979         default:
7980                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7981                 ret = -EINVAL;
7982                 break;
7983         }
7984
7985         return ret;
7986 }
7987
7988 /* Disable l2 tunnel tag insertion */
7989 static int
7990 ixgbe_dev_l2_tunnel_insertion_disable
7991         (struct rte_eth_dev *dev,
7992          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7993 {
7994         int ret = 0;
7995
7996         switch (l2_tunnel->l2_tunnel_type) {
7997         case RTE_L2_TUNNEL_TYPE_E_TAG:
7998                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7999                 break;
8000         default:
8001                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8002                 ret = -EINVAL;
8003                 break;
8004         }
8005
8006         return ret;
8007 }
8008
8009 static int
8010 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
8011                              bool en)
8012 {
8013         int ret = 0;
8014         uint32_t qde;
8015         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8016
8017         if (hw->mac.type != ixgbe_mac_X550 &&
8018             hw->mac.type != ixgbe_mac_X550EM_x &&
8019             hw->mac.type != ixgbe_mac_X550EM_a) {
8020                 return -ENOTSUP;
8021         }
8022
8023         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
8024         if (en)
8025                 qde |= IXGBE_QDE_STRIP_TAG;
8026         else
8027                 qde &= ~IXGBE_QDE_STRIP_TAG;
8028         qde &= ~IXGBE_QDE_READ;
8029         qde |= IXGBE_QDE_WRITE;
8030         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
8031
8032         return ret;
8033 }
8034
8035 /* Enable l2 tunnel tag stripping */
8036 static int
8037 ixgbe_dev_l2_tunnel_stripping_enable
8038         (struct rte_eth_dev *dev,
8039          enum rte_eth_tunnel_type l2_tunnel_type)
8040 {
8041         int ret = 0;
8042
8043         switch (l2_tunnel_type) {
8044         case RTE_L2_TUNNEL_TYPE_E_TAG:
8045                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
8046                 break;
8047         default:
8048                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8049                 ret = -EINVAL;
8050                 break;
8051         }
8052
8053         return ret;
8054 }
8055
8056 /* Disable l2 tunnel tag stripping */
8057 static int
8058 ixgbe_dev_l2_tunnel_stripping_disable
8059         (struct rte_eth_dev *dev,
8060          enum rte_eth_tunnel_type l2_tunnel_type)
8061 {
8062         int ret = 0;
8063
8064         switch (l2_tunnel_type) {
8065         case RTE_L2_TUNNEL_TYPE_E_TAG:
8066                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
8067                 break;
8068         default:
8069                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8070                 ret = -EINVAL;
8071                 break;
8072         }
8073
8074         return ret;
8075 }
8076
8077 /* Enable/disable l2 tunnel offload functions */
8078 static int
8079 ixgbe_dev_l2_tunnel_offload_set
8080         (struct rte_eth_dev *dev,
8081          struct rte_eth_l2_tunnel_conf *l2_tunnel,
8082          uint32_t mask,
8083          uint8_t en)
8084 {
8085         int ret = 0;
8086
8087         if (l2_tunnel == NULL)
8088                 return -EINVAL;
8089
8090         ret = -EINVAL;
8091         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
8092                 if (en)
8093                         ret = ixgbe_dev_l2_tunnel_enable(
8094                                 dev,
8095                                 l2_tunnel->l2_tunnel_type);
8096                 else
8097                         ret = ixgbe_dev_l2_tunnel_disable(
8098                                 dev,
8099                                 l2_tunnel->l2_tunnel_type);
8100         }
8101
8102         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
8103                 if (en)
8104                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
8105                                 dev,
8106                                 l2_tunnel);
8107                 else
8108                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
8109                                 dev,
8110                                 l2_tunnel);
8111         }
8112
8113         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
8114                 if (en)
8115                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
8116                                 dev,
8117                                 l2_tunnel->l2_tunnel_type);
8118                 else
8119                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
8120                                 dev,
8121                                 l2_tunnel->l2_tunnel_type);
8122         }
8123
8124         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
8125                 if (en)
8126                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
8127                                 dev,
8128                                 l2_tunnel->l2_tunnel_type);
8129                 else
8130                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
8131                                 dev,
8132                                 l2_tunnel->l2_tunnel_type);
8133         }
8134
8135         return ret;
8136 }
8137
8138 static int
8139 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
8140                         uint16_t port)
8141 {
8142         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
8143         IXGBE_WRITE_FLUSH(hw);
8144
8145         return 0;
8146 }
8147
8148 /* There's only one register for VxLAN UDP port.
8149  * So, we cannot add several ports. Will update it.
8150  */
8151 static int
8152 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
8153                      uint16_t port)
8154 {
8155         if (port == 0) {
8156                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
8157                 return -EINVAL;
8158         }
8159
8160         return ixgbe_update_vxlan_port(hw, port);
8161 }
8162
8163 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8164  * UDP port, it must have a value.
8165  * So, will reset it to the original value 0.
8166  */
8167 static int
8168 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8169                      uint16_t port)
8170 {
8171         uint16_t cur_port;
8172
8173         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8174
8175         if (cur_port != port) {
8176                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8177                 return -EINVAL;
8178         }
8179
8180         return ixgbe_update_vxlan_port(hw, 0);
8181 }
8182
8183 /* Add UDP tunneling port */
8184 static int
8185 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8186                               struct rte_eth_udp_tunnel *udp_tunnel)
8187 {
8188         int ret = 0;
8189         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8190
8191         if (hw->mac.type != ixgbe_mac_X550 &&
8192             hw->mac.type != ixgbe_mac_X550EM_x &&
8193             hw->mac.type != ixgbe_mac_X550EM_a) {
8194                 return -ENOTSUP;
8195         }
8196
8197         if (udp_tunnel == NULL)
8198                 return -EINVAL;
8199
8200         switch (udp_tunnel->prot_type) {
8201         case RTE_TUNNEL_TYPE_VXLAN:
8202                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8203                 break;
8204
8205         case RTE_TUNNEL_TYPE_GENEVE:
8206         case RTE_TUNNEL_TYPE_TEREDO:
8207                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8208                 ret = -EINVAL;
8209                 break;
8210
8211         default:
8212                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8213                 ret = -EINVAL;
8214                 break;
8215         }
8216
8217         return ret;
8218 }
8219
8220 /* Remove UDP tunneling port */
8221 static int
8222 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8223                               struct rte_eth_udp_tunnel *udp_tunnel)
8224 {
8225         int ret = 0;
8226         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8227
8228         if (hw->mac.type != ixgbe_mac_X550 &&
8229             hw->mac.type != ixgbe_mac_X550EM_x &&
8230             hw->mac.type != ixgbe_mac_X550EM_a) {
8231                 return -ENOTSUP;
8232         }
8233
8234         if (udp_tunnel == NULL)
8235                 return -EINVAL;
8236
8237         switch (udp_tunnel->prot_type) {
8238         case RTE_TUNNEL_TYPE_VXLAN:
8239                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8240                 break;
8241         case RTE_TUNNEL_TYPE_GENEVE:
8242         case RTE_TUNNEL_TYPE_TEREDO:
8243                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8244                 ret = -EINVAL;
8245                 break;
8246         default:
8247                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8248                 ret = -EINVAL;
8249                 break;
8250         }
8251
8252         return ret;
8253 }
8254
8255 static int
8256 ixgbevf_dev_promiscuous_enable(struct rte_eth_dev *dev)
8257 {
8258         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8259         int ret;
8260
8261         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_PROMISC)) {
8262         case IXGBE_SUCCESS:
8263                 ret = 0;
8264                 break;
8265         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8266                 ret = -ENOTSUP;
8267                 break;
8268         default:
8269                 ret = -EAGAIN;
8270                 break;
8271         }
8272
8273         return ret;
8274 }
8275
8276 static int
8277 ixgbevf_dev_promiscuous_disable(struct rte_eth_dev *dev)
8278 {
8279         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8280         int ret;
8281
8282         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE)) {
8283         case IXGBE_SUCCESS:
8284                 ret = 0;
8285                 break;
8286         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8287                 ret = -ENOTSUP;
8288                 break;
8289         default:
8290                 ret = -EAGAIN;
8291                 break;
8292         }
8293
8294         return ret;
8295 }
8296
8297 static int
8298 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8299 {
8300         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8301         int ret;
8302         int mode = IXGBEVF_XCAST_MODE_ALLMULTI;
8303
8304         switch (hw->mac.ops.update_xcast_mode(hw, mode)) {
8305         case IXGBE_SUCCESS:
8306                 ret = 0;
8307                 break;
8308         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8309                 ret = -ENOTSUP;
8310                 break;
8311         default:
8312                 ret = -EAGAIN;
8313                 break;
8314         }
8315
8316         return ret;
8317 }
8318
8319 static int
8320 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8321 {
8322         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8323         int ret;
8324
8325         switch (hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI)) {
8326         case IXGBE_SUCCESS:
8327                 ret = 0;
8328                 break;
8329         case IXGBE_ERR_FEATURE_NOT_SUPPORTED:
8330                 ret = -ENOTSUP;
8331                 break;
8332         default:
8333                 ret = -EAGAIN;
8334                 break;
8335         }
8336
8337         return ret;
8338 }
8339
8340 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8341 {
8342         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8343         u32 in_msg = 0;
8344
8345         /* peek the message first */
8346         in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8347
8348         /* PF reset VF event */
8349         if (in_msg == IXGBE_PF_CONTROL_MSG) {
8350                 /* dummy mbx read to ack pf */
8351                 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8352                         return;
8353                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8354                                              NULL);
8355         }
8356 }
8357
8358 static int
8359 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8360 {
8361         uint32_t eicr;
8362         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8363         struct ixgbe_interrupt *intr =
8364                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8365         ixgbevf_intr_disable(dev);
8366
8367         /* read-on-clear nic registers here */
8368         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8369         intr->flags = 0;
8370
8371         /* only one misc vector supported - mailbox */
8372         eicr &= IXGBE_VTEICR_MASK;
8373         if (eicr == IXGBE_MISC_VEC_ID)
8374                 intr->flags |= IXGBE_FLAG_MAILBOX;
8375
8376         return 0;
8377 }
8378
8379 static int
8380 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8381 {
8382         struct ixgbe_interrupt *intr =
8383                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8384
8385         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8386                 ixgbevf_mbx_process(dev);
8387                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8388         }
8389
8390         ixgbevf_intr_enable(dev);
8391
8392         return 0;
8393 }
8394
8395 static void
8396 ixgbevf_dev_interrupt_handler(void *param)
8397 {
8398         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8399
8400         ixgbevf_dev_interrupt_get_status(dev);
8401         ixgbevf_dev_interrupt_action(dev);
8402 }
8403
8404 /**
8405  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8406  *  @hw: pointer to hardware structure
8407  *
8408  *  Stops the transmit data path and waits for the HW to internally empty
8409  *  the Tx security block
8410  **/
8411 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8412 {
8413 #define IXGBE_MAX_SECTX_POLL 40
8414
8415         int i;
8416         int sectxreg;
8417
8418         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8419         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8420         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8421         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8422                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8423                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8424                         break;
8425                 /* Use interrupt-safe sleep just in case */
8426                 usec_delay(1000);
8427         }
8428
8429         /* For informational purposes only */
8430         if (i >= IXGBE_MAX_SECTX_POLL)
8431                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8432                          "path fully disabled.  Continuing with init.");
8433
8434         return IXGBE_SUCCESS;
8435 }
8436
8437 /**
8438  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8439  *  @hw: pointer to hardware structure
8440  *
8441  *  Enables the transmit data path.
8442  **/
8443 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8444 {
8445         uint32_t sectxreg;
8446
8447         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8448         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8449         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8450         IXGBE_WRITE_FLUSH(hw);
8451
8452         return IXGBE_SUCCESS;
8453 }
8454
8455 /* restore n-tuple filter */
8456 static inline void
8457 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8458 {
8459         struct ixgbe_filter_info *filter_info =
8460                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8461         struct ixgbe_5tuple_filter *node;
8462
8463         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8464                 ixgbe_inject_5tuple_filter(dev, node);
8465         }
8466 }
8467
8468 /* restore ethernet type filter */
8469 static inline void
8470 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8471 {
8472         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8473         struct ixgbe_filter_info *filter_info =
8474                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8475         int i;
8476
8477         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8478                 if (filter_info->ethertype_mask & (1 << i)) {
8479                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8480                                         filter_info->ethertype_filters[i].etqf);
8481                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8482                                         filter_info->ethertype_filters[i].etqs);
8483                         IXGBE_WRITE_FLUSH(hw);
8484                 }
8485         }
8486 }
8487
8488 /* restore SYN filter */
8489 static inline void
8490 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8491 {
8492         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8493         struct ixgbe_filter_info *filter_info =
8494                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8495         uint32_t synqf;
8496
8497         synqf = filter_info->syn_info;
8498
8499         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8500                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8501                 IXGBE_WRITE_FLUSH(hw);
8502         }
8503 }
8504
8505 /* restore L2 tunnel filter */
8506 static inline void
8507 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8508 {
8509         struct ixgbe_l2_tn_info *l2_tn_info =
8510                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8511         struct ixgbe_l2_tn_filter *node;
8512         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8513
8514         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8515                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8516                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8517                 l2_tn_conf.pool           = node->pool;
8518                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8519         }
8520 }
8521
8522 /* restore rss filter */
8523 static inline void
8524 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8525 {
8526         struct ixgbe_filter_info *filter_info =
8527                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8528
8529         if (filter_info->rss_info.conf.queue_num)
8530                 ixgbe_config_rss_filter(dev,
8531                         &filter_info->rss_info, TRUE);
8532 }
8533
8534 static int
8535 ixgbe_filter_restore(struct rte_eth_dev *dev)
8536 {
8537         ixgbe_ntuple_filter_restore(dev);
8538         ixgbe_ethertype_filter_restore(dev);
8539         ixgbe_syn_filter_restore(dev);
8540         ixgbe_fdir_filter_restore(dev);
8541         ixgbe_l2_tn_filter_restore(dev);
8542         ixgbe_rss_filter_restore(dev);
8543
8544         return 0;
8545 }
8546
8547 static void
8548 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8549 {
8550         struct ixgbe_l2_tn_info *l2_tn_info =
8551                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8552         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8553
8554         if (l2_tn_info->e_tag_en)
8555                 (void)ixgbe_e_tag_enable(hw);
8556
8557         if (l2_tn_info->e_tag_fwd_en)
8558                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8559
8560         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8561 }
8562
8563 /* remove all the n-tuple filters */
8564 void
8565 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8566 {
8567         struct ixgbe_filter_info *filter_info =
8568                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8569         struct ixgbe_5tuple_filter *p_5tuple;
8570
8571         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8572                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8573 }
8574
8575 /* remove all the ether type filters */
8576 void
8577 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8578 {
8579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8580         struct ixgbe_filter_info *filter_info =
8581                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8582         int i;
8583
8584         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8585                 if (filter_info->ethertype_mask & (1 << i) &&
8586                     !filter_info->ethertype_filters[i].conf) {
8587                         (void)ixgbe_ethertype_filter_remove(filter_info,
8588                                                             (uint8_t)i);
8589                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8590                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8591                         IXGBE_WRITE_FLUSH(hw);
8592                 }
8593         }
8594 }
8595
8596 /* remove the SYN filter */
8597 void
8598 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8599 {
8600         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8601         struct ixgbe_filter_info *filter_info =
8602                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8603
8604         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8605                 filter_info->syn_info = 0;
8606
8607                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8608                 IXGBE_WRITE_FLUSH(hw);
8609         }
8610 }
8611
8612 /* remove all the L2 tunnel filters */
8613 int
8614 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8615 {
8616         struct ixgbe_l2_tn_info *l2_tn_info =
8617                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8618         struct ixgbe_l2_tn_filter *l2_tn_filter;
8619         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8620         int ret = 0;
8621
8622         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8623                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8624                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8625                 l2_tn_conf.pool           = l2_tn_filter->pool;
8626                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8627                 if (ret < 0)
8628                         return ret;
8629         }
8630
8631         return 0;
8632 }
8633
8634 void
8635 ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev,
8636                                 struct ixgbe_macsec_setting *macsec_setting)
8637 {
8638         struct ixgbe_macsec_setting *macsec =
8639                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8640
8641         macsec->offload_en = macsec_setting->offload_en;
8642         macsec->encrypt_en = macsec_setting->encrypt_en;
8643         macsec->replayprotect_en = macsec_setting->replayprotect_en;
8644 }
8645
8646 void
8647 ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev)
8648 {
8649         struct ixgbe_macsec_setting *macsec =
8650                 IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private);
8651
8652         macsec->offload_en = 0;
8653         macsec->encrypt_en = 0;
8654         macsec->replayprotect_en = 0;
8655 }
8656
8657 void
8658 ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev,
8659                                 struct ixgbe_macsec_setting *macsec_setting)
8660 {
8661         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8662         uint32_t ctrl;
8663         uint8_t en = macsec_setting->encrypt_en;
8664         uint8_t rp = macsec_setting->replayprotect_en;
8665
8666         /**
8667          * Workaround:
8668          * As no ixgbe_disable_sec_rx_path equivalent is
8669          * implemented for tx in the base code, and we are
8670          * not allowed to modify the base code in DPDK, so
8671          * just call the hand-written one directly for now.
8672          * The hardware support has been checked by
8673          * ixgbe_disable_sec_rx_path().
8674          */
8675         ixgbe_disable_sec_tx_path_generic(hw);
8676
8677         /* Enable Ethernet CRC (required by MACsec offload) */
8678         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8679         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8680         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8681
8682         /* Enable the TX and RX crypto engines */
8683         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8684         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8685         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8686
8687         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8688         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8689         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8690
8691         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8692         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8693         ctrl |= 0x3;
8694         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8695
8696         /* Enable SA lookup */
8697         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8698         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8699         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8700                      IXGBE_LSECTXCTRL_AUTH;
8701         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8702         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8703         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8704         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8705
8706         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8707         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8708         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8709         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8710         if (rp)
8711                 ctrl |= IXGBE_LSECRXCTRL_RP;
8712         else
8713                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8714         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8715
8716         /* Start the data paths */
8717         ixgbe_enable_sec_rx_path(hw);
8718         /**
8719          * Workaround:
8720          * As no ixgbe_enable_sec_rx_path equivalent is
8721          * implemented for tx in the base code, and we are
8722          * not allowed to modify the base code in DPDK, so
8723          * just call the hand-written one directly for now.
8724          */
8725         ixgbe_enable_sec_tx_path_generic(hw);
8726 }
8727
8728 void
8729 ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev)
8730 {
8731         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8732         uint32_t ctrl;
8733
8734         /**
8735          * Workaround:
8736          * As no ixgbe_disable_sec_rx_path equivalent is
8737          * implemented for tx in the base code, and we are
8738          * not allowed to modify the base code in DPDK, so
8739          * just call the hand-written one directly for now.
8740          * The hardware support has been checked by
8741          * ixgbe_disable_sec_rx_path().
8742          */
8743         ixgbe_disable_sec_tx_path_generic(hw);
8744
8745         /* Disable the TX and RX crypto engines */
8746         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8747         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8748         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8749
8750         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8751         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8752         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8753
8754         /* Disable SA lookup */
8755         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8756         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8757         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8758         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8759
8760         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8761         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8762         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8763         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8764
8765         /* Start the data paths */
8766         ixgbe_enable_sec_rx_path(hw);
8767         /**
8768          * Workaround:
8769          * As no ixgbe_enable_sec_rx_path equivalent is
8770          * implemented for tx in the base code, and we are
8771          * not allowed to modify the base code in DPDK, so
8772          * just call the hand-written one directly for now.
8773          */
8774         ixgbe_enable_sec_tx_path_generic(hw);
8775 }
8776
8777 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8778 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8779 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8780 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8781 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8782 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8783 RTE_PMD_REGISTER_PARAM_STRING(net_ixgbe_vf,
8784                               IXGBEVF_DEVARG_PFLINK_FULLCHK "=<0|1>");
8785
8786 RTE_LOG_REGISTER(ixgbe_logtype_init, pmd.net.ixgbe.init, NOTICE);
8787 RTE_LOG_REGISTER(ixgbe_logtype_driver, pmd.net.ixgbe.driver, NOTICE);
8788
8789 #ifdef RTE_LIBRTE_IXGBE_DEBUG_RX
8790 RTE_LOG_REGISTER(ixgbe_logtype_rx, pmd.net.ixgbe.rx, DEBUG);
8791 #endif
8792 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX
8793 RTE_LOG_REGISTER(ixgbe_logtype_tx, pmd.net.ixgbe.tx, DEBUG);
8794 #endif
8795 #ifdef RTE_LIBRTE_IXGBE_DEBUG_TX_FREE
8796 RTE_LOG_REGISTER(ixgbe_logtype_tx_free, pmd.net.ixgbe.tx_free, DEBUG);
8797 #endif