drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63 #include <rte_hash_crc.h>
  64
  65 #include "ixgbe_logs.h"
  66 #include "base/ixgbe_api.h"
  67 #include "base/ixgbe_vf.h"
  68 #include "base/ixgbe_common.h"
  69 #include "ixgbe_ethdev.h"
  70 #include "ixgbe_bypass.h"
  71 #include "ixgbe_rxtx.h"
  72 #include "base/ixgbe_type.h"
  73 #include "base/ixgbe_phy.h"
  74 #include "ixgbe_regs.h"
  75
  76 #include "rte_pmd_ixgbe.h"
  77
  78 /*
  79  * High threshold controlling when to start sending XOFF frames. Must be at
  80  * least 8 bytes less than receive packet buffer size. This value is in units
  81  * of 1024 bytes.
  82  */
  83 #define IXGBE_FC_HI    0x80
  84
  85 /*
  86  * Low threshold controlling when to start sending XON frames. This value is
  87  * in units of 1024 bytes.
  88  */
  89 #define IXGBE_FC_LO    0x40
  90
  91 /* Default minimum inter-interrupt interval for EITR configuration */
  92 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  93
  94 /* Timer value included in XOFF frames. */
  95 #define IXGBE_FC_PAUSE 0x680
  96
  97 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  98 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  99 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
 100
 101 #define IXGBE_MMW_SIZE_DEFAULT        0x4
 102 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 103 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 104
 105 /*
 106  *  Default values for RX/TX configuration
 107  */
 108 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 109 #define IXGBE_DEFAULT_RX_PTHRESH      8
 110 #define IXGBE_DEFAULT_RX_HTHRESH      8
 111 #define IXGBE_DEFAULT_RX_WTHRESH      0
 112
 113 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 114 #define IXGBE_DEFAULT_TX_PTHRESH      32
 115 #define IXGBE_DEFAULT_TX_HTHRESH      0
 116 #define IXGBE_DEFAULT_TX_WTHRESH      0
 117 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 118
 119 /* Bit shift and mask */
 120 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 121 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 122 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 123 #define IXGBE_8_BIT_MASK   UINT8_MAX
 124
 125 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 126
 127 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 128
 129 #define IXGBE_HKEY_MAX_INDEX 10
 130
 131 /* Additional timesync values. */
 132 #define NSEC_PER_SEC             1000000000L
 133 #define IXGBE_INCVAL_10GB        0x66666666
 134 #define IXGBE_INCVAL_1GB         0x40000000
 135 #define IXGBE_INCVAL_100         0x50000000
 136 #define IXGBE_INCVAL_SHIFT_10GB  28
 137 #define IXGBE_INCVAL_SHIFT_1GB   24
 138 #define IXGBE_INCVAL_SHIFT_100   21
 139 #define IXGBE_INCVAL_SHIFT_82599 7
 140 #define IXGBE_INCPER_SHIFT_82599 24
 141
 142 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 143
 144 #define IXGBE_VT_CTL_POOLING_MODE_MASK         0x00030000
 145 #define IXGBE_VT_CTL_POOLING_MODE_ETAG         0x00010000
 146 #define DEFAULT_ETAG_ETYPE                     0x893f
 147 #define IXGBE_ETAG_ETYPE                       0x00005084
 148 #define IXGBE_ETAG_ETYPE_MASK                  0x0000ffff
 149 #define IXGBE_ETAG_ETYPE_VALID                 0x80000000
 150 #define IXGBE_RAH_ADTYPE                       0x40000000
 151 #define IXGBE_RAL_ETAG_FILTER_MASK             0x00003fff
 152 #define IXGBE_VMVIR_TAGA_MASK                  0x18000000
 153 #define IXGBE_VMVIR_TAGA_ETAG_INSERT           0x08000000
 154 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
 155 #define IXGBE_QDE_STRIP_TAG                    0x00000004
 156 #define IXGBE_VTEICR_MASK                      0x07
 157
 158 enum ixgbevf_xcast_modes {
 159         IXGBEVF_XCAST_MODE_NONE = 0,
 160         IXGBEVF_XCAST_MODE_MULTI,
 161         IXGBEVF_XCAST_MODE_ALLMULTI,
 162 };
 163
 164 #define IXGBE_EXVET_VET_EXT_SHIFT              16
 165 #define IXGBE_DMATXCTL_VT_MASK                 0xFFFF0000
 166
 167 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 168 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 169 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
 170 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
 171 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
 172 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
 173 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
 174 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 175 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 177 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 178 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 179 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 180 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 181 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 182 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 183 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 184 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 185                                 int wait_to_complete);
 186 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 187                                 struct rte_eth_stats *stats);
 188 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 189                                 struct rte_eth_xstat *xstats, unsigned n);
 190 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 191                                   struct rte_eth_xstat *xstats, unsigned n);
 192 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 193 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 194 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 195         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 196 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 197         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit);
 198 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 199                                              uint16_t queue_id,
 200                                              uint8_t stat_idx,
 201                                              uint8_t is_rx);
 202 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 203                                  size_t fw_size);
 204 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 205                                struct rte_eth_dev_info *dev_info);
 206 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
 207 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 208                                  struct rte_eth_dev_info *dev_info);
 209 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 210
 211 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 212                 uint16_t vlan_id, int on);
 213 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
 214                                enum rte_vlan_type vlan_type,
 215                                uint16_t tpid_id);
 216 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 217                 uint16_t queue, bool on);
 218 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 219                 int on);
 220 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 221 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 222 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 223 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 224 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 225
 226 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 227 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 228 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 229                                struct rte_eth_fc_conf *fc_conf);
 230 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 231                                struct rte_eth_fc_conf *fc_conf);
 232 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 233                 struct rte_eth_pfc_conf *pfc_conf);
 234 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 235                         struct rte_eth_rss_reta_entry64 *reta_conf,
 236                         uint16_t reta_size);
 237 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 238                         struct rte_eth_rss_reta_entry64 *reta_conf,
 239                         uint16_t reta_size);
 240 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 241 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 242 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 243 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 244 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 245 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 246                                       struct rte_intr_handle *handle);
 247 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 248                 void *param);
 249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 250 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 251                 uint32_t index, uint32_t pool);
 252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 254                                            struct ether_addr *mac_addr);
 255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
 256 static int is_ixgbe_pmd(const char *driver_name);
 257
 258 /* For Virtual Function support */
 259 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 260 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 261 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 262 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 263 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 264 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 265 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 266 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 267 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 268                 struct rte_eth_stats *stats);
 269 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 270 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 271                 uint16_t vlan_id, int on);
 272 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 273                 uint16_t queue, int on);
 274 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 276 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 277                                             uint16_t queue_id);
 278 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 279                                              uint16_t queue_id);
 280 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 281                                  uint8_t queue, uint8_t msix_vector);
 282 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 283 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 284 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 285
 286 /* For Eth VMDQ APIs support */
 287 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 288                 ether_addr * mac_addr, uint8_t on);
 289 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
 290 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 291                 struct rte_eth_mirror_conf *mirror_conf,
 292                 uint8_t rule_id, uint8_t on);
 293 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 294                 uint8_t rule_id);
 295 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 296                                           uint16_t queue_id);
 297 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 298                                            uint16_t queue_id);
 299 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 300                                uint8_t queue, uint8_t msix_vector);
 301 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 302
 303 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 304                 uint16_t queue_idx, uint16_t tx_rate);
 305
 306 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 307                                  struct ether_addr *mac_addr,
 308                                  uint32_t index, uint32_t pool);
 309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 311                                              struct ether_addr *mac_addr);
 312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 313                         struct rte_eth_syn_filter *filter);
 314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 315                         enum rte_filter_op filter_op,
 316                         void *arg);
 317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 318                         struct ixgbe_5tuple_filter *filter);
 319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 320                         struct ixgbe_5tuple_filter *filter);
 321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 325                         struct rte_eth_ntuple_filter *filter);
 326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 327                                 enum rte_filter_op filter_op,
 328                                 void *arg);
 329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 330                         struct rte_eth_ethertype_filter *filter);
 331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 332                      enum rte_filter_type filter_type,
 333                      enum rte_filter_op filter_op,
 334                      void *arg);
 335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 336
 337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 338                                       struct ether_addr *mc_addr_set,
 339                                       uint32_t nb_mc_addr);
 340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 341                                    struct rte_eth_dcb_info *dcb_info);
 342
 343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 345                             struct rte_dev_reg_info *regs);
 346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 348                                 struct rte_dev_eeprom_info *eeprom);
 349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 350                                 struct rte_dev_eeprom_info *eeprom);
 351
 352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 354                                 struct rte_dev_reg_info *regs);
 355
 356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 359                                             struct timespec *timestamp,
 360                                             uint32_t flags);
 361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 362                                             struct timespec *timestamp);
 363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 365                                    struct timespec *timestamp);
 366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 367                                    const struct timespec *timestamp);
 368 static void ixgbevf_dev_interrupt_handler(struct rte_intr_handle *handle,
 369                                           void *param);
 370
 371 static int ixgbe_dev_l2_tunnel_eth_type_conf
 372         (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
 373 static int ixgbe_dev_l2_tunnel_offload_set
 374         (struct rte_eth_dev *dev,
 375          struct rte_eth_l2_tunnel_conf *l2_tunnel,
 376          uint32_t mask,
 377          uint8_t en);
 378 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
 379                                              enum rte_filter_op filter_op,
 380                                              void *arg);
 381
 382 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 383                                          struct rte_eth_udp_tunnel *udp_tunnel);
 384 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 385                                          struct rte_eth_udp_tunnel *udp_tunnel);
 386 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
 387 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 388
 389 /*
 390  * Define VF Stats MACRO for Non "cleared on read" register
 391  */
 392 #define UPDATE_VF_STAT(reg, last, cur)                          \
 393 {                                                               \
 394         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 395         cur += (latest - last) & UINT_MAX;                      \
 396         last = latest;                                          \
 397 }
 398
 399 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 400 {                                                                \
 401         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 402         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 403         u64 latest = ((new_msb << 32) | new_lsb);                \
 404         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 405         last = latest;                                           \
 406 }
 407
 408 #define IXGBE_SET_HWSTRIP(h, q) do {\
 409                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 410                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 411                 (h)->bitmap[idx] |= 1 << bit;\
 412         } while (0)
 413
 414 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
 415                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 416                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 417                 (h)->bitmap[idx] &= ~(1 << bit);\
 418         } while (0)
 419
 420 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
 421                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 422                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 423                 (r) = (h)->bitmap[idx] >> bit & 1;\
 424         } while (0)
 425
 426 /*
 427  * The set of PCI devices this driver supports
 428  */
 429 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 430         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
 431         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
 432         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
 433         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
 434         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
 435         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
 436         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
 437         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
 438         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
 439         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
 440         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
 441         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
 442         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
 443         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
 444         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
 445         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
 446         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
 447         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
 448         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
 449         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
 450         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
 451         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
 452         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
 453         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
 454         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
 455         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
 456         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
 457         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
 458         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
 459         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
 460         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
 461         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
 462         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
 463         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
 464         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
 465         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
 466         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
 467         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
 468         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
 469         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
 470         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
 471         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
 472         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
 473         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
 474         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
 475         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
 476         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
 477         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
 478         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
 479         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
 480         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
 481         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
 482         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
 483 #ifdef RTE_NIC_BYPASS
 484         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
 485 #endif
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 /*
 490  * The set of PCI devices this driver supports (for 82599 VF)
 491  */
 492 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 493         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
 494         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
 495         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
 496         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
 497         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
 498         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
 499         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
 500         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
 501         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
 502         { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
 503         { .vendor_id = 0, /* sentinel */ },
 504 };
 505
 506 static const struct rte_eth_desc_lim rx_desc_lim = {
 507         .nb_max = IXGBE_MAX_RING_DESC,
 508         .nb_min = IXGBE_MIN_RING_DESC,
 509         .nb_align = IXGBE_RXD_ALIGN,
 510 };
 511
 512 static const struct rte_eth_desc_lim tx_desc_lim = {
 513         .nb_max = IXGBE_MAX_RING_DESC,
 514         .nb_min = IXGBE_MIN_RING_DESC,
 515         .nb_align = IXGBE_TXD_ALIGN,
 516         .nb_seg_max = IXGBE_TX_MAX_SEG,
 517         .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
 518 };
 519
 520 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 521         .dev_configure        = ixgbe_dev_configure,
 522         .dev_start            = ixgbe_dev_start,
 523         .dev_stop             = ixgbe_dev_stop,
 524         .dev_set_link_up    = ixgbe_dev_set_link_up,
 525         .dev_set_link_down  = ixgbe_dev_set_link_down,
 526         .dev_close            = ixgbe_dev_close,
 527         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 528         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 529         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 530         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 531         .link_update          = ixgbe_dev_link_update,
 532         .stats_get            = ixgbe_dev_stats_get,
 533         .xstats_get           = ixgbe_dev_xstats_get,
 534         .stats_reset          = ixgbe_dev_stats_reset,
 535         .xstats_reset         = ixgbe_dev_xstats_reset,
 536         .xstats_get_names     = ixgbe_dev_xstats_get_names,
 537         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 538         .fw_version_get       = ixgbe_fw_version_get,
 539         .dev_infos_get        = ixgbe_dev_info_get,
 540         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 541         .mtu_set              = ixgbe_dev_mtu_set,
 542         .vlan_filter_set      = ixgbe_vlan_filter_set,
 543         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 544         .vlan_offload_set     = ixgbe_vlan_offload_set,
 545         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 546         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 547         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 548         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 549         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 550         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 551         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 552         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 553         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 554         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 555         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 556         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 557         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 558         .dev_led_on           = ixgbe_dev_led_on,
 559         .dev_led_off          = ixgbe_dev_led_off,
 560         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 561         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 562         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 563         .mac_addr_add         = ixgbe_add_rar,
 564         .mac_addr_remove      = ixgbe_remove_rar,
 565         .mac_addr_set         = ixgbe_set_default_mac_addr,
 566         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 567         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 568         .mirror_rule_set      = ixgbe_mirror_rule_set,
 569         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 570         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 571         .reta_update          = ixgbe_dev_rss_reta_update,
 572         .reta_query           = ixgbe_dev_rss_reta_query,
 573 #ifdef RTE_NIC_BYPASS
 574         .bypass_init          = ixgbe_bypass_init,
 575         .bypass_state_set     = ixgbe_bypass_state_store,
 576         .bypass_state_show    = ixgbe_bypass_state_show,
 577         .bypass_event_set     = ixgbe_bypass_event_store,
 578         .bypass_event_show    = ixgbe_bypass_event_show,
 579         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 580         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 581         .bypass_ver_show      = ixgbe_bypass_ver_show,
 582         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 583 #endif /* RTE_NIC_BYPASS */
 584         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 585         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 586         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 587         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 588         .rxq_info_get         = ixgbe_rxq_info_get,
 589         .txq_info_get         = ixgbe_txq_info_get,
 590         .timesync_enable      = ixgbe_timesync_enable,
 591         .timesync_disable     = ixgbe_timesync_disable,
 592         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 593         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 594         .get_reg              = ixgbe_get_regs,
 595         .get_eeprom_length    = ixgbe_get_eeprom_length,
 596         .get_eeprom           = ixgbe_get_eeprom,
 597         .set_eeprom           = ixgbe_set_eeprom,
 598         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 599         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 600         .timesync_read_time   = ixgbe_timesync_read_time,
 601         .timesync_write_time  = ixgbe_timesync_write_time,
 602         .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
 603         .l2_tunnel_offload_set   = ixgbe_dev_l2_tunnel_offload_set,
 604         .udp_tunnel_port_add  = ixgbe_dev_udp_tunnel_port_add,
 605         .udp_tunnel_port_del  = ixgbe_dev_udp_tunnel_port_del,
 606 };
 607
 608 /*
 609  * dev_ops for virtual function, bare necessities for basic vf
 610  * operation have been implemented
 611  */
 612 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 613         .dev_configure        = ixgbevf_dev_configure,
 614         .dev_start            = ixgbevf_dev_start,
 615         .dev_stop             = ixgbevf_dev_stop,
 616         .link_update          = ixgbe_dev_link_update,
 617         .stats_get            = ixgbevf_dev_stats_get,
 618         .xstats_get           = ixgbevf_dev_xstats_get,
 619         .stats_reset          = ixgbevf_dev_stats_reset,
 620         .xstats_reset         = ixgbevf_dev_stats_reset,
 621         .xstats_get_names     = ixgbevf_dev_xstats_get_names,
 622         .dev_close            = ixgbevf_dev_close,
 623         .allmulticast_enable  = ixgbevf_dev_allmulticast_enable,
 624         .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
 625         .dev_infos_get        = ixgbevf_dev_info_get,
 626         .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
 627         .mtu_set              = ixgbevf_dev_set_mtu,
 628         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 629         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 630         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 631         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 632         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 633         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 634         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 635         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 636         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 637         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 638         .mac_addr_add         = ixgbevf_add_mac_addr,
 639         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 640         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 641         .rxq_info_get         = ixgbe_rxq_info_get,
 642         .txq_info_get         = ixgbe_txq_info_get,
 643         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 644         .get_reg              = ixgbevf_get_regs,
 645         .reta_update          = ixgbe_dev_rss_reta_update,
 646         .reta_query           = ixgbe_dev_rss_reta_query,
 647         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 648         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 649 };
 650
 651 /* store statistics names and its offset in stats structure */
 652 struct rte_ixgbe_xstats_name_off {
 653         char name[RTE_ETH_XSTATS_NAME_SIZE];
 654         unsigned offset;
 655 };
 656
 657 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 658         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 659         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 660         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 661         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 662         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 663         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 664         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 665         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 666         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 667         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 668         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 669         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 670         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 671         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 672         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 673                 prc1023)},
 674         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 675                 prc1522)},
 676         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 677         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 678         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 679         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 680         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 681         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 682         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 683         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 684         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 685         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 686         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 687         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 688         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 689         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 690         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 691         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 692         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 693                 ptc1023)},
 694         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 695                 ptc1522)},
 696         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 697         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 698         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 699         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 700
 701         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 702                 fdirustat_add)},
 703         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 704                 fdirustat_remove)},
 705         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 706                 fdirfstat_fadd)},
 707         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 708                 fdirfstat_fremove)},
 709         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 710                 fdirmatch)},
 711         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 712                 fdirmiss)},
 713
 714         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 715         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 716         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 717                 fclast)},
 718         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 719         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 720         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 721         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 722         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 723                 fcoe_noddp)},
 724         {"rx_fcoe_no_direct_data_placement_ext_buff",
 725                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 726
 727         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 728                 lxontxc)},
 729         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 730                 lxonrxc)},
 731         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 732                 lxofftxc)},
 733         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 734                 lxoffrxc)},
 735         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 736 };
 737
 738 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 739                            sizeof(rte_ixgbe_stats_strings[0]))
 740
 741 /* MACsec statistics */
 742 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
 743         {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 744                 out_pkts_untagged)},
 745         {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
 746                 out_pkts_encrypted)},
 747         {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
 748                 out_pkts_protected)},
 749         {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
 750                 out_octets_encrypted)},
 751         {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
 752                 out_octets_protected)},
 753         {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
 754                 in_pkts_untagged)},
 755         {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
 756                 in_pkts_badtag)},
 757         {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
 758                 in_pkts_nosci)},
 759         {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
 760                 in_pkts_unknownsci)},
 761         {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
 762                 in_octets_decrypted)},
 763         {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
 764                 in_octets_validated)},
 765         {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
 766                 in_pkts_unchecked)},
 767         {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
 768                 in_pkts_delayed)},
 769         {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
 770                 in_pkts_late)},
 771         {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
 772                 in_pkts_ok)},
 773         {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
 774                 in_pkts_invalid)},
 775         {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
 776                 in_pkts_notvalid)},
 777         {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
 778                 in_pkts_unusedsa)},
 779         {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
 780                 in_pkts_notusingsa)},
 781 };
 782
 783 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
 784                            sizeof(rte_ixgbe_macsec_strings[0]))
 785
 786 /* Per-queue statistics */
 787 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 788         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 789         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 790         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 791         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 792 };
 793
 794 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 795                            sizeof(rte_ixgbe_rxq_strings[0]))
 796 #define IXGBE_NB_RXQ_PRIO_VALUES 8
 797
 798 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 799         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 800         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 801         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 802                 pxon2offc)},
 803 };
 804
 805 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 806                            sizeof(rte_ixgbe_txq_strings[0]))
 807 #define IXGBE_NB_TXQ_PRIO_VALUES 8
 808
 809 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 810         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 811 };
 812
 813 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 814                 sizeof(rte_ixgbevf_stats_strings[0]))
 815
 816 /**
 817  * Atomically reads the link status information from global
 818  * structure rte_eth_dev.
 819  *
 820  * @param dev
 821  *   - Pointer to the structure rte_eth_dev to read from.
 822  *   - Pointer to the buffer to be saved with the link status.
 823  *
 824  * @return
 825  *   - On success, zero.
 826  *   - On failure, negative value.
 827  */
 828 static inline int
 829 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 830                                 struct rte_eth_link *link)
 831 {
 832         struct rte_eth_link *dst = link;
 833         struct rte_eth_link *src = &(dev->data->dev_link);
 834
 835         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 836                                         *(uint64_t *)src) == 0)
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 /**
 843  * Atomically writes the link status information into global
 844  * structure rte_eth_dev.
 845  *
 846  * @param dev
 847  *   - Pointer to the structure rte_eth_dev to read from.
 848  *   - Pointer to the buffer to be saved with the link status.
 849  *
 850  * @return
 851  *   - On success, zero.
 852  *   - On failure, negative value.
 853  */
 854 static inline int
 855 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 856                                 struct rte_eth_link *link)
 857 {
 858         struct rte_eth_link *dst = &(dev->data->dev_link);
 859         struct rte_eth_link *src = link;
 860
 861         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 862                                         *(uint64_t *)src) == 0)
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 /*
 869  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 870  */
 871 static inline int
 872 ixgbe_is_sfp(struct ixgbe_hw *hw)
 873 {
 874         switch (hw->phy.type) {
 875         case ixgbe_phy_sfp_avago:
 876         case ixgbe_phy_sfp_ftl:
 877         case ixgbe_phy_sfp_intel:
 878         case ixgbe_phy_sfp_unknown:
 879         case ixgbe_phy_sfp_passive_tyco:
 880         case ixgbe_phy_sfp_passive_unknown:
 881                 return 1;
 882         default:
 883                 return 0;
 884         }
 885 }
 886
 887 static inline int32_t
 888 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 889 {
 890         uint32_t ctrl_ext;
 891         int32_t status;
 892
 893         status = ixgbe_reset_hw(hw);
 894
 895         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 896         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 897         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 898         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 899         IXGBE_WRITE_FLUSH(hw);
 900
 901         return status;
 902 }
 903
 904 static inline void
 905 ixgbe_enable_intr(struct rte_eth_dev *dev)
 906 {
 907         struct ixgbe_interrupt *intr =
 908                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 909         struct ixgbe_hw *hw =
 910                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 911
 912         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 913         IXGBE_WRITE_FLUSH(hw);
 914 }
 915
 916 /*
 917  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 918  */
 919 static void
 920 ixgbe_disable_intr(struct ixgbe_hw *hw)
 921 {
 922         PMD_INIT_FUNC_TRACE();
 923
 924         if (hw->mac.type == ixgbe_mac_82598EB) {
 925                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 926         } else {
 927                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 928                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 929                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 930         }
 931         IXGBE_WRITE_FLUSH(hw);
 932 }
 933
 934 /*
 935  * This function resets queue statistics mapping registers.
 936  * From Niantic datasheet, Initialization of Statistics section:
 937  * "...if software requires the queue counters, the RQSMR and TQSM registers
 938  * must be re-programmed following a device reset.
 939  */
 940 static void
 941 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 942 {
 943         uint32_t i;
 944
 945         for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 946                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 947                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 948         }
 949 }
 950
 951
 952 static int
 953 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 954                                   uint16_t queue_id,
 955                                   uint8_t stat_idx,
 956                                   uint8_t is_rx)
 957 {
 958 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 959 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 960 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 961
 962         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 963         struct ixgbe_stat_mapping_registers *stat_mappings =
 964                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 965         uint32_t qsmr_mask = 0;
 966         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 967         uint32_t q_map;
 968         uint8_t n, offset;
 969
 970         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 971                 (hw->mac.type != ixgbe_mac_X540) &&
 972                 (hw->mac.type != ixgbe_mac_X550) &&
 973                 (hw->mac.type != ixgbe_mac_X550EM_x) &&
 974                 (hw->mac.type != ixgbe_mac_X550EM_a))
 975                 return -ENOSYS;
 976
 977         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 978                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 979                      queue_id, stat_idx);
 980
 981         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 982         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 983                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 984                 return -EIO;
 985         }
 986         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 987
 988         /* Now clear any previous stat_idx set */
 989         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 990         if (!is_rx)
 991                 stat_mappings->tqsm[n] &= ~clearing_mask;
 992         else
 993                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 994
 995         q_map = (uint32_t)stat_idx;
 996         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 997         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 998         if (!is_rx)
 999                 stat_mappings->tqsm[n] |= qsmr_mask;
1000         else
1001                 stat_mappings->rqsmr[n] |= qsmr_mask;
1002
1003         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1004                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1005                      queue_id, stat_idx);
1006         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1007                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1008
1009         /* Now write the mapping in the appropriate register */
1010         if (is_rx) {
1011                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1012                              stat_mappings->rqsmr[n], n);
1013                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1014         } else {
1015                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1016                              stat_mappings->tqsm[n], n);
1017                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1018         }
1019         return 0;
1020 }
1021
1022 static void
1023 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1024 {
1025         struct ixgbe_stat_mapping_registers *stat_mappings =
1026                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1027         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028         int i;
1029
1030         /* write whatever was in stat mapping table to the NIC */
1031         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1032                 /* rx */
1033                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1034
1035                 /* tx */
1036                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1037         }
1038 }
1039
1040 static void
1041 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1042 {
1043         uint8_t i;
1044         struct ixgbe_dcb_tc_config *tc;
1045         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1046
1047         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1048         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1049         for (i = 0; i < dcb_max_tc; i++) {
1050                 tc = &dcb_config->tc_config[i];
1051                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1052                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1053                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1054                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1055                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1056                                  (uint8_t)(100/dcb_max_tc + (i & 1));
1057                 tc->pfc = ixgbe_dcb_pfc_disabled;
1058         }
1059
1060         /* Initialize default user to priority mapping, UPx->TC0 */
1061         tc = &dcb_config->tc_config[0];
1062         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1063         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1064         for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1065                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1066                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1067         }
1068         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1069         dcb_config->pfc_mode_enable = false;
1070         dcb_config->vt_mode = true;
1071         dcb_config->round_robin_enable = false;
1072         /* support all DCB capabilities in 82599 */
1073         dcb_config->support.capabilities = 0xFF;
1074
1075         /*we only support 4 Tcs for X540, X550 */
1076         if (hw->mac.type == ixgbe_mac_X540 ||
1077                 hw->mac.type == ixgbe_mac_X550 ||
1078                 hw->mac.type == ixgbe_mac_X550EM_x ||
1079                 hw->mac.type == ixgbe_mac_X550EM_a) {
1080                 dcb_config->num_tcs.pg_tcs = 4;
1081                 dcb_config->num_tcs.pfc_tcs = 4;
1082         }
1083 }
1084
1085 /*
1086  * Ensure that all locks are released before first NVM or PHY access
1087  */
1088 static void
1089 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1090 {
1091         uint16_t mask;
1092
1093         /*
1094          * Phy lock should not fail in this early stage. If this is the case,
1095          * it is due to an improper exit of the application.
1096          * So force the release of the faulty lock. Release of common lock
1097          * is done automatically by swfw_sync function.
1098          */
1099         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1100         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1101                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1102         }
1103         ixgbe_release_swfw_semaphore(hw, mask);
1104
1105         /*
1106          * These ones are more tricky since they are common to all ports; but
1107          * swfw_sync retries last long enough (1s) to be almost sure that if
1108          * lock can not be taken it is due to an improper lock of the
1109          * semaphore.
1110          */
1111         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1112         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1113                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1114         }
1115         ixgbe_release_swfw_semaphore(hw, mask);
1116 }
1117
1118 /*
1119  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1120  * It returns 0 on success.
1121  */
1122 static int
1123 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1124 {
1125         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1126         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1127         struct ixgbe_hw *hw =
1128                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1129         struct ixgbe_vfta *shadow_vfta =
1130                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1131         struct ixgbe_hwstrip *hwstrip =
1132                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1133         struct ixgbe_dcb_config *dcb_config =
1134                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1135         struct ixgbe_filter_info *filter_info =
1136                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1137         uint32_t ctrl_ext;
1138         uint16_t csum;
1139         int diag, i;
1140
1141         PMD_INIT_FUNC_TRACE();
1142
1143         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146         eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1147
1148         /*
1149          * For secondary processes, we don't initialise any further as primary
1150          * has already done this work. Only check we don't need a different
1151          * RX and TX function.
1152          */
1153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154                 struct ixgbe_tx_queue *txq;
1155                 /* TX queue function in primary, set by last queue initialized
1156                  * Tx queue may not initialized by primary process
1157                  */
1158                 if (eth_dev->data->tx_queues) {
1159                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160                         ixgbe_set_tx_function(eth_dev, txq);
1161                 } else {
1162                         /* Use default TX function if we get here */
1163                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164                                      "Using default TX function.");
1165                 }
1166
1167                 ixgbe_set_rx_function(eth_dev);
1168
1169                 return 0;
1170         }
1171
1172         rte_eth_copy_pci_info(eth_dev, pci_dev);
1173         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1174
1175         /* Vendor and Device ID need to be set before init of shared code */
1176         hw->device_id = pci_dev->id.device_id;
1177         hw->vendor_id = pci_dev->id.vendor_id;
1178         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179         hw->allow_unsupported_sfp = 1;
1180
1181         /* Initialize the shared code (base driver) */
1182 #ifdef RTE_NIC_BYPASS
1183         diag = ixgbe_bypass_init_shared_code(hw);
1184 #else
1185         diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_NIC_BYPASS */
1187
1188         if (diag != IXGBE_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1190                 return -EIO;
1191         }
1192
1193         /* pick up the PCI bus settings for reporting later */
1194         ixgbe_get_bus_info(hw);
1195
1196         /* Unlock any pending hardware semaphore */
1197         ixgbe_swfw_lock_reset(hw);
1198
1199         /* Initialize DCB configuration*/
1200         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201         ixgbe_dcb_init(hw, dcb_config);
1202         /* Get Hardware Flow Control setting */
1203         hw->fc.requested_mode = ixgbe_fc_full;
1204         hw->fc.current_mode = ixgbe_fc_full;
1205         hw->fc.pause_time = IXGBE_FC_PAUSE;
1206         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207                 hw->fc.low_water[i] = IXGBE_FC_LO;
1208                 hw->fc.high_water[i] = IXGBE_FC_HI;
1209         }
1210         hw->fc.send_xon = 1;
1211
1212         /* Make sure we have a good EEPROM before we read from it */
1213         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214         if (diag != IXGBE_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1216                 return -EIO;
1217         }
1218
1219 #ifdef RTE_NIC_BYPASS
1220         diag = ixgbe_bypass_init_hw(hw);
1221 #else
1222         diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_NIC_BYPASS */
1224
1225         /*
1226          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227          * is called too soon after the kernel driver unbinding/binding occurs.
1228          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230          * also called. See ixgbe_identify_phy_82599(). The reason for the
1231          * failure is not known, and only occuts when virtualisation features
1232          * are disabled in the bios. A delay of 100ms  was found to be enough by
1233          * trial-and-error, and is doubled to be safe.
1234          */
1235         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236                 rte_delay_ms(200);
1237                 diag = ixgbe_init_hw(hw);
1238         }
1239
1240         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1241                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1242                              "LOM.  Please be aware there may be issues associated "
1243                              "with your hardware.");
1244                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1245                              "please contact your Intel or hardware representative "
1246                              "who provided you with this hardware.");
1247         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1248                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1249         if (diag) {
1250                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1251                 return -EIO;
1252         }
1253
1254         /* Reset the hw statistics */
1255         ixgbe_dev_stats_reset(eth_dev);
1256
1257         /* disable interrupt */
1258         ixgbe_disable_intr(hw);
1259
1260         /* reset mappings for queue statistics hw counters*/
1261         ixgbe_reset_qstat_mappings(hw);
1262
1263         /* Allocate memory for storing MAC addresses */
1264         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1265                                                hw->mac.num_rar_entries, 0);
1266         if (eth_dev->data->mac_addrs == NULL) {
1267                 PMD_INIT_LOG(ERR,
1268                              "Failed to allocate %u bytes needed to store "
1269                              "MAC addresses",
1270                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1271                 return -ENOMEM;
1272         }
1273         /* Copy the permanent MAC address */
1274         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1275                         &eth_dev->data->mac_addrs[0]);
1276
1277         /* Allocate memory for storing hash filter MAC addresses */
1278         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1279                                                     IXGBE_VMDQ_NUM_UC_MAC, 0);
1280         if (eth_dev->data->hash_mac_addrs == NULL) {
1281                 PMD_INIT_LOG(ERR,
1282                              "Failed to allocate %d bytes needed to store MAC addresses",
1283                              ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1284                 return -ENOMEM;
1285         }
1286
1287         /* initialize the vfta */
1288         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1289
1290         /* initialize the hw strip bitmap*/
1291         memset(hwstrip, 0, sizeof(*hwstrip));
1292
1293         /* initialize PF if max_vfs not zero */
1294         ixgbe_pf_host_init(eth_dev);
1295
1296         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1297         /* let hardware know driver is loaded */
1298         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1299         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1300         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1301         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1302         IXGBE_WRITE_FLUSH(hw);
1303
1304         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1305                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1306                              (int) hw->mac.type, (int) hw->phy.type,
1307                              (int) hw->phy.sfp_type);
1308         else
1309                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1310                              (int) hw->mac.type, (int) hw->phy.type);
1311
1312         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1313                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1314                      pci_dev->id.device_id);
1315
1316         rte_intr_callback_register(intr_handle,
1317                                    ixgbe_dev_interrupt_handler, eth_dev);
1318
1319         /* enable uio/vfio intr/eventfd mapping */
1320         rte_intr_enable(intr_handle);
1321
1322         /* enable support intr */
1323         ixgbe_enable_intr(eth_dev);
1324
1325         /* initialize filter info */
1326         memset(filter_info, 0,
1327                sizeof(struct ixgbe_filter_info));
1328
1329         /* initialize 5tuple filter list */
1330         TAILQ_INIT(&filter_info->fivetuple_list);
1331
1332         /* initialize flow director filter list & hash */
1333         ixgbe_fdir_filter_init(eth_dev);
1334
1335         /* initialize l2 tunnel filter list & hash */
1336         ixgbe_l2_tn_filter_init(eth_dev);
1337
1338         TAILQ_INIT(&filter_ntuple_list);
1339         TAILQ_INIT(&filter_ethertype_list);
1340         TAILQ_INIT(&filter_syn_list);
1341         TAILQ_INIT(&filter_fdir_list);
1342         TAILQ_INIT(&filter_l2_tunnel_list);
1343         TAILQ_INIT(&ixgbe_flow_list);
1344
1345         return 0;
1346 }
1347
1348 static int
1349 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1350 {
1351         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1352         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1353         struct ixgbe_hw *hw;
1354
1355         PMD_INIT_FUNC_TRACE();
1356
1357         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1358                 return -EPERM;
1359
1360         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1361
1362         if (hw->adapter_stopped == 0)
1363                 ixgbe_dev_close(eth_dev);
1364
1365         eth_dev->dev_ops = NULL;
1366         eth_dev->rx_pkt_burst = NULL;
1367         eth_dev->tx_pkt_burst = NULL;
1368
1369         /* Unlock any pending hardware semaphore */
1370         ixgbe_swfw_lock_reset(hw);
1371
1372         /* disable uio intr before callback unregister */
1373         rte_intr_disable(intr_handle);
1374         rte_intr_callback_unregister(intr_handle,
1375                                      ixgbe_dev_interrupt_handler, eth_dev);
1376
1377         /* uninitialize PF if max_vfs not zero */
1378         ixgbe_pf_host_uninit(eth_dev);
1379
1380         rte_free(eth_dev->data->mac_addrs);
1381         eth_dev->data->mac_addrs = NULL;
1382
1383         rte_free(eth_dev->data->hash_mac_addrs);
1384         eth_dev->data->hash_mac_addrs = NULL;
1385
1386         /* remove all the fdir filters & hash */
1387         ixgbe_fdir_filter_uninit(eth_dev);
1388
1389         /* remove all the L2 tunnel filters & hash */
1390         ixgbe_l2_tn_filter_uninit(eth_dev);
1391
1392         /* Remove all ntuple filters of the device */
1393         ixgbe_ntuple_filter_uninit(eth_dev);
1394
1395         /* clear all the filters list */
1396         ixgbe_filterlist_flush();
1397
1398         return 0;
1399 }
1400
1401 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1402 {
1403         struct ixgbe_filter_info *filter_info =
1404                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1405         struct ixgbe_5tuple_filter *p_5tuple;
1406
1407         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1408                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1409                              p_5tuple,
1410                              entries);
1411                 rte_free(p_5tuple);
1412         }
1413         memset(filter_info->fivetuple_mask, 0,
1414                sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1415
1416         return 0;
1417 }
1418
1419 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1420 {
1421         struct ixgbe_hw_fdir_info *fdir_info =
1422                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1423         struct ixgbe_fdir_filter *fdir_filter;
1424
1425                 if (fdir_info->hash_map)
1426                 rte_free(fdir_info->hash_map);
1427         if (fdir_info->hash_handle)
1428                 rte_hash_free(fdir_info->hash_handle);
1429
1430         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1431                 TAILQ_REMOVE(&fdir_info->fdir_list,
1432                              fdir_filter,
1433                              entries);
1434                 rte_free(fdir_filter);
1435         }
1436
1437         return 0;
1438 }
1439
1440 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1441 {
1442         struct ixgbe_l2_tn_info *l2_tn_info =
1443                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1444         struct ixgbe_l2_tn_filter *l2_tn_filter;
1445
1446         if (l2_tn_info->hash_map)
1447                 rte_free(l2_tn_info->hash_map);
1448         if (l2_tn_info->hash_handle)
1449                 rte_hash_free(l2_tn_info->hash_handle);
1450
1451         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1452                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1453                              l2_tn_filter,
1454                              entries);
1455                 rte_free(l2_tn_filter);
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1462 {
1463         struct ixgbe_hw_fdir_info *fdir_info =
1464                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1465         char fdir_hash_name[RTE_HASH_NAMESIZE];
1466         struct rte_hash_parameters fdir_hash_params = {
1467                 .name = fdir_hash_name,
1468                 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1469                 .key_len = sizeof(union ixgbe_atr_input),
1470                 .hash_func = rte_hash_crc,
1471                 .hash_func_init_val = 0,
1472                 .socket_id = rte_socket_id(),
1473         };
1474
1475         TAILQ_INIT(&fdir_info->fdir_list);
1476         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1477                  "fdir_%s", eth_dev->data->name);
1478         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1479         if (!fdir_info->hash_handle) {
1480                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1481                 return -EINVAL;
1482         }
1483         fdir_info->hash_map = rte_zmalloc("ixgbe",
1484                                           sizeof(struct ixgbe_fdir_filter *) *
1485                                           IXGBE_MAX_FDIR_FILTER_NUM,
1486                                           0);
1487         if (!fdir_info->hash_map) {
1488                 PMD_INIT_LOG(ERR,
1489                              "Failed to allocate memory for fdir hash map!");
1490                 return -ENOMEM;
1491         }
1492         fdir_info->mask_added = FALSE;
1493
1494         return 0;
1495 }
1496
1497 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1498 {
1499         struct ixgbe_l2_tn_info *l2_tn_info =
1500                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1501         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1502         struct rte_hash_parameters l2_tn_hash_params = {
1503                 .name = l2_tn_hash_name,
1504                 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1505                 .key_len = sizeof(struct ixgbe_l2_tn_key),
1506                 .hash_func = rte_hash_crc,
1507                 .hash_func_init_val = 0,
1508                 .socket_id = rte_socket_id(),
1509         };
1510
1511         TAILQ_INIT(&l2_tn_info->l2_tn_list);
1512         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1513                  "l2_tn_%s", eth_dev->data->name);
1514         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1515         if (!l2_tn_info->hash_handle) {
1516                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1517                 return -EINVAL;
1518         }
1519         l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1520                                    sizeof(struct ixgbe_l2_tn_filter *) *
1521                                    IXGBE_MAX_L2_TN_FILTER_NUM,
1522                                    0);
1523         if (!l2_tn_info->hash_map) {
1524                 PMD_INIT_LOG(ERR,
1525                         "Failed to allocate memory for L2 TN hash map!");
1526                 return -ENOMEM;
1527         }
1528         l2_tn_info->e_tag_en = FALSE;
1529         l2_tn_info->e_tag_fwd_en = FALSE;
1530         l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1531
1532         return 0;
1533 }
1534 /*
1535  * Negotiate mailbox API version with the PF.
1536  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1537  * Then we try to negotiate starting with the most recent one.
1538  * If all negotiation attempts fail, then we will proceed with
1539  * the default one (ixgbe_mbox_api_10).
1540  */
1541 static void
1542 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1543 {
1544         int32_t i;
1545
1546         /* start with highest supported, proceed down */
1547         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1548                 ixgbe_mbox_api_12,
1549                 ixgbe_mbox_api_11,
1550                 ixgbe_mbox_api_10,
1551         };
1552
1553         for (i = 0;
1554                         i != RTE_DIM(sup_ver) &&
1555                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1556                         i++)
1557                 ;
1558 }
1559
1560 static void
1561 generate_random_mac_addr(struct ether_addr *mac_addr)
1562 {
1563         uint64_t random;
1564
1565         /* Set Organizationally Unique Identifier (OUI) prefix. */
1566         mac_addr->addr_bytes[0] = 0x00;
1567         mac_addr->addr_bytes[1] = 0x09;
1568         mac_addr->addr_bytes[2] = 0xC0;
1569         /* Force indication of locally assigned MAC address. */
1570         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1571         /* Generate the last 3 bytes of the MAC address with a random number. */
1572         random = rte_rand();
1573         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1574 }
1575
1576 /*
1577  * Virtual Function device init
1578  */
1579 static int
1580 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1581 {
1582         int diag;
1583         uint32_t tc, tcs;
1584         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1585         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1586         struct ixgbe_hw *hw =
1587                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1588         struct ixgbe_vfta *shadow_vfta =
1589                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1590         struct ixgbe_hwstrip *hwstrip =
1591                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1592         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1593
1594         PMD_INIT_FUNC_TRACE();
1595
1596         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1597         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1598         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1599
1600         /* for secondary processes, we don't initialise any further as primary
1601          * has already done this work. Only check we don't need a different
1602          * RX function
1603          */
1604         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1605                 struct ixgbe_tx_queue *txq;
1606                 /* TX queue function in primary, set by last queue initialized
1607                  * Tx queue may not initialized by primary process
1608                  */
1609                 if (eth_dev->data->tx_queues) {
1610                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1611                         ixgbe_set_tx_function(eth_dev, txq);
1612                 } else {
1613                         /* Use default TX function if we get here */
1614                         PMD_INIT_LOG(NOTICE,
1615                                      "No TX queues configured yet. Using default TX function.");
1616                 }
1617
1618                 ixgbe_set_rx_function(eth_dev);
1619
1620                 return 0;
1621         }
1622
1623         rte_eth_copy_pci_info(eth_dev, pci_dev);
1624         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1625
1626         hw->device_id = pci_dev->id.device_id;
1627         hw->vendor_id = pci_dev->id.vendor_id;
1628         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1629
1630         /* initialize the vfta */
1631         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1632
1633         /* initialize the hw strip bitmap*/
1634         memset(hwstrip, 0, sizeof(*hwstrip));
1635
1636         /* Initialize the shared code (base driver) */
1637         diag = ixgbe_init_shared_code(hw);
1638         if (diag != IXGBE_SUCCESS) {
1639                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1640                 return -EIO;
1641         }
1642
1643         /* init_mailbox_params */
1644         hw->mbx.ops.init_params(hw);
1645
1646         /* Reset the hw statistics */
1647         ixgbevf_dev_stats_reset(eth_dev);
1648
1649         /* Disable the interrupts for VF */
1650         ixgbevf_intr_disable(hw);
1651
1652         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1653         diag = hw->mac.ops.reset_hw(hw);
1654
1655         /*
1656          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1657          * the underlying PF driver has not assigned a MAC address to the VF.
1658          * In this case, assign a random MAC address.
1659          */
1660         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1661                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1662                 return diag;
1663         }
1664
1665         /* negotiate mailbox API version to use with the PF. */
1666         ixgbevf_negotiate_api(hw);
1667
1668         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1669         ixgbevf_get_queues(hw, &tcs, &tc);
1670
1671         /* Allocate memory for storing MAC addresses */
1672         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1673                                                hw->mac.num_rar_entries, 0);
1674         if (eth_dev->data->mac_addrs == NULL) {
1675                 PMD_INIT_LOG(ERR,
1676                              "Failed to allocate %u bytes needed to store "
1677                              "MAC addresses",
1678                              ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1679                 return -ENOMEM;
1680         }
1681
1682         /* Generate a random MAC address, if none was assigned by PF. */
1683         if (is_zero_ether_addr(perm_addr)) {
1684                 generate_random_mac_addr(perm_addr);
1685                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1686                 if (diag) {
1687                         rte_free(eth_dev->data->mac_addrs);
1688                         eth_dev->data->mac_addrs = NULL;
1689                         return diag;
1690                 }
1691                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1692                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1693                              "%02x:%02x:%02x:%02x:%02x:%02x",
1694                              perm_addr->addr_bytes[0],
1695                              perm_addr->addr_bytes[1],
1696                              perm_addr->addr_bytes[2],
1697                              perm_addr->addr_bytes[3],
1698                              perm_addr->addr_bytes[4],
1699                              perm_addr->addr_bytes[5]);
1700         }
1701
1702         /* Copy the permanent MAC address */
1703         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1704
1705         /* reset the hardware with the new settings */
1706         diag = hw->mac.ops.start_hw(hw);
1707         switch (diag) {
1708         case  0:
1709                 break;
1710
1711         default:
1712                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1713                 return -EIO;
1714         }
1715
1716         rte_intr_callback_register(intr_handle,
1717                                    ixgbevf_dev_interrupt_handler, eth_dev);
1718         rte_intr_enable(intr_handle);
1719         ixgbevf_intr_enable(hw);
1720
1721         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1722                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1723                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1724
1725         return 0;
1726 }
1727
1728 /* Virtual Function device uninit */
1729
1730 static int
1731 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1732 {
1733         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
1734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1735         struct ixgbe_hw *hw;
1736
1737         PMD_INIT_FUNC_TRACE();
1738
1739         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1740                 return -EPERM;
1741
1742         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1743
1744         if (hw->adapter_stopped == 0)
1745                 ixgbevf_dev_close(eth_dev);
1746
1747         eth_dev->dev_ops = NULL;
1748         eth_dev->rx_pkt_burst = NULL;
1749         eth_dev->tx_pkt_burst = NULL;
1750
1751         /* Disable the interrupts for VF */
1752         ixgbevf_intr_disable(hw);
1753
1754         rte_free(eth_dev->data->mac_addrs);
1755         eth_dev->data->mac_addrs = NULL;
1756
1757         rte_intr_disable(intr_handle);
1758         rte_intr_callback_unregister(intr_handle,
1759                                      ixgbevf_dev_interrupt_handler, eth_dev);
1760
1761         return 0;
1762 }
1763
1764 static struct eth_driver rte_ixgbe_pmd = {
1765         .pci_drv = {
1766                 .id_table = pci_id_ixgbe_map,
1767                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1768                 .probe = rte_eth_dev_pci_probe,
1769                 .remove = rte_eth_dev_pci_remove,
1770         },
1771         .eth_dev_init = eth_ixgbe_dev_init,
1772         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1773         .dev_private_size = sizeof(struct ixgbe_adapter),
1774 };
1775
1776 /*
1777  * virtual function driver struct
1778  */
1779 static struct eth_driver rte_ixgbevf_pmd = {
1780         .pci_drv = {
1781                 .id_table = pci_id_ixgbevf_map,
1782                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1783                 .probe = rte_eth_dev_pci_probe,
1784                 .remove = rte_eth_dev_pci_remove,
1785         },
1786         .eth_dev_init = eth_ixgbevf_dev_init,
1787         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1788         .dev_private_size = sizeof(struct ixgbe_adapter),
1789 };
1790
1791 static int
1792 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1793 {
1794         struct ixgbe_hw *hw =
1795                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796         struct ixgbe_vfta *shadow_vfta =
1797                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1798         uint32_t vfta;
1799         uint32_t vid_idx;
1800         uint32_t vid_bit;
1801
1802         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1803         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1804         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1805         if (on)
1806                 vfta |= vid_bit;
1807         else
1808                 vfta &= ~vid_bit;
1809         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1810
1811         /* update local VFTA copy */
1812         shadow_vfta->vfta[vid_idx] = vfta;
1813
1814         return 0;
1815 }
1816
1817 static void
1818 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1819 {
1820         if (on)
1821                 ixgbe_vlan_hw_strip_enable(dev, queue);
1822         else
1823                 ixgbe_vlan_hw_strip_disable(dev, queue);
1824 }
1825
1826 static int
1827 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1828                     enum rte_vlan_type vlan_type,
1829                     uint16_t tpid)
1830 {
1831         struct ixgbe_hw *hw =
1832                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1833         int ret = 0;
1834         uint32_t reg;
1835         uint32_t qinq;
1836
1837         qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1838         qinq &= IXGBE_DMATXCTL_GDV;
1839
1840         switch (vlan_type) {
1841         case ETH_VLAN_TYPE_INNER:
1842                 if (qinq) {
1843                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1844                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1845                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1846                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1847                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1848                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1849                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1850                 } else {
1851                         ret = -ENOTSUP;
1852                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1853                                     " by single VLAN");
1854                 }
1855                 break;
1856         case ETH_VLAN_TYPE_OUTER:
1857                 if (qinq) {
1858                         /* Only the high 16-bits is valid */
1859                         IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1860                                         IXGBE_EXVET_VET_EXT_SHIFT);
1861                 } else {
1862                         reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1863                         reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1864                         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1865                         reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1866                         reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1867                                 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1868                         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1869                 }
1870
1871                 break;
1872         default:
1873                 ret = -EINVAL;
1874                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1875                 break;
1876         }
1877
1878         return ret;
1879 }
1880
1881 void
1882 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1883 {
1884         struct ixgbe_hw *hw =
1885                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         uint32_t vlnctrl;
1887
1888         PMD_INIT_FUNC_TRACE();
1889
1890         /* Filter Table Disable */
1891         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1892         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1893
1894         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1895 }
1896
1897 void
1898 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1899 {
1900         struct ixgbe_hw *hw =
1901                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902         struct ixgbe_vfta *shadow_vfta =
1903                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1904         uint32_t vlnctrl;
1905         uint16_t i;
1906
1907         PMD_INIT_FUNC_TRACE();
1908
1909         /* Filter Table Enable */
1910         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1911         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1912         vlnctrl |= IXGBE_VLNCTRL_VFE;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1915
1916         /* write whatever is in local vfta copy */
1917         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1918                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1919 }
1920
1921 static void
1922 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1923 {
1924         struct ixgbe_hwstrip *hwstrip =
1925                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1926         struct ixgbe_rx_queue *rxq;
1927
1928         if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1929                 return;
1930
1931         if (on)
1932                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1933         else
1934                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1935
1936         if (queue >= dev->data->nb_rx_queues)
1937                 return;
1938
1939         rxq = dev->data->rx_queues[queue];
1940
1941         if (on)
1942                 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1943         else
1944                 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1945 }
1946
1947 static void
1948 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1949 {
1950         struct ixgbe_hw *hw =
1951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         uint32_t ctrl;
1953
1954         PMD_INIT_FUNC_TRACE();
1955
1956         if (hw->mac.type == ixgbe_mac_82598EB) {
1957                 /* No queue level support */
1958                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1959                 return;
1960         }
1961
1962         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1963         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1964         ctrl &= ~IXGBE_RXDCTL_VME;
1965         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1966
1967         /* record those setting for HW strip per queue */
1968         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1969 }
1970
1971 static void
1972 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1973 {
1974         struct ixgbe_hw *hw =
1975                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         uint32_t ctrl;
1977
1978         PMD_INIT_FUNC_TRACE();
1979
1980         if (hw->mac.type == ixgbe_mac_82598EB) {
1981                 /* No queue level supported */
1982                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1983                 return;
1984         }
1985
1986         /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1987         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1988         ctrl |= IXGBE_RXDCTL_VME;
1989         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1990
1991         /* record those setting for HW strip per queue */
1992         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1993 }
1994
1995 void
1996 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1997 {
1998         struct ixgbe_hw *hw =
1999                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000         uint32_t ctrl;
2001         uint16_t i;
2002         struct ixgbe_rx_queue *rxq;
2003
2004         PMD_INIT_FUNC_TRACE();
2005
2006         if (hw->mac.type == ixgbe_mac_82598EB) {
2007                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2008                 ctrl &= ~IXGBE_VLNCTRL_VME;
2009                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2010         } else {
2011                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2012                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2013                         rxq = dev->data->rx_queues[i];
2014                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2015                         ctrl &= ~IXGBE_RXDCTL_VME;
2016                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2017
2018                         /* record those setting for HW strip per queue */
2019                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2020                 }
2021         }
2022 }
2023
2024 void
2025 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2026 {
2027         struct ixgbe_hw *hw =
2028                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2029         uint32_t ctrl;
2030         uint16_t i;
2031         struct ixgbe_rx_queue *rxq;
2032
2033         PMD_INIT_FUNC_TRACE();
2034
2035         if (hw->mac.type == ixgbe_mac_82598EB) {
2036                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2037                 ctrl |= IXGBE_VLNCTRL_VME;
2038                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2039         } else {
2040                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2041                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2042                         rxq = dev->data->rx_queues[i];
2043                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2044                         ctrl |= IXGBE_RXDCTL_VME;
2045                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2046
2047                         /* record those setting for HW strip per queue */
2048                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2049                 }
2050         }
2051 }
2052
2053 static void
2054 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2055 {
2056         struct ixgbe_hw *hw =
2057                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058         uint32_t ctrl;
2059
2060         PMD_INIT_FUNC_TRACE();
2061
2062         /* DMATXCTRL: Geric Double VLAN Disable */
2063         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2064         ctrl &= ~IXGBE_DMATXCTL_GDV;
2065         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2066
2067         /* CTRL_EXT: Global Double VLAN Disable */
2068         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2069         ctrl &= ~IXGBE_EXTENDED_VLAN;
2070         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2071
2072 }
2073
2074 static void
2075 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2076 {
2077         struct ixgbe_hw *hw =
2078                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2079         uint32_t ctrl;
2080
2081         PMD_INIT_FUNC_TRACE();
2082
2083         /* DMATXCTRL: Geric Double VLAN Enable */
2084         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2085         ctrl |= IXGBE_DMATXCTL_GDV;
2086         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2087
2088         /* CTRL_EXT: Global Double VLAN Enable */
2089         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2090         ctrl |= IXGBE_EXTENDED_VLAN;
2091         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2092
2093         /* Clear pooling mode of PFVTCTL. It's required by X550. */
2094         if (hw->mac.type == ixgbe_mac_X550 ||
2095             hw->mac.type == ixgbe_mac_X550EM_x ||
2096             hw->mac.type == ixgbe_mac_X550EM_a) {
2097                 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2098                 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2099                 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2100         }
2101
2102         /*
2103          * VET EXT field in the EXVET register = 0x8100 by default
2104          * So no need to change. Same to VT field of DMATXCTL register
2105          */
2106 }
2107
2108 static void
2109 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2110 {
2111         if (mask & ETH_VLAN_STRIP_MASK) {
2112                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2113                         ixgbe_vlan_hw_strip_enable_all(dev);
2114                 else
2115                         ixgbe_vlan_hw_strip_disable_all(dev);
2116         }
2117
2118         if (mask & ETH_VLAN_FILTER_MASK) {
2119                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2120                         ixgbe_vlan_hw_filter_enable(dev);
2121                 else
2122                         ixgbe_vlan_hw_filter_disable(dev);
2123         }
2124
2125         if (mask & ETH_VLAN_EXTEND_MASK) {
2126                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2127                         ixgbe_vlan_hw_extend_enable(dev);
2128                 else
2129                         ixgbe_vlan_hw_extend_disable(dev);
2130         }
2131 }
2132
2133 static void
2134 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2135 {
2136         struct ixgbe_hw *hw =
2137                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2138         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2139         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2140
2141         vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2142         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2143 }
2144
2145 static int
2146 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2147 {
2148         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2149
2150         switch (nb_rx_q) {
2151         case 1:
2152         case 2:
2153                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2154                 break;
2155         case 4:
2156                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2157                 break;
2158         default:
2159                 return -EINVAL;
2160         }
2161
2162         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2163         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2164
2165         return 0;
2166 }
2167
2168 static int
2169 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2170 {
2171         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2172         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2173         uint16_t nb_rx_q = dev->data->nb_rx_queues;
2174         uint16_t nb_tx_q = dev->data->nb_tx_queues;
2175
2176         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2177                 /* check multi-queue mode */
2178                 switch (dev_conf->rxmode.mq_mode) {
2179                 case ETH_MQ_RX_VMDQ_DCB:
2180                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2181                         break;
2182                 case ETH_MQ_RX_VMDQ_DCB_RSS:
2183                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2184                         PMD_INIT_LOG(ERR, "SRIOV active,"
2185                                         " unsupported mq_mode rx %d.",
2186                                         dev_conf->rxmode.mq_mode);
2187                         return -EINVAL;
2188                 case ETH_MQ_RX_RSS:
2189                 case ETH_MQ_RX_VMDQ_RSS:
2190                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2191                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2192                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2193                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2194                                                 " invalid queue number"
2195                                                 " for VMDQ RSS, allowed"
2196                                                 " value are 1, 2 or 4.");
2197                                         return -EINVAL;
2198                                 }
2199                         break;
2200                 case ETH_MQ_RX_VMDQ_ONLY:
2201                 case ETH_MQ_RX_NONE:
2202                         /* if nothing mq mode configure, use default scheme */
2203                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2204                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2205                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2206                         break;
2207                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2208                         /* SRIOV only works in VMDq enable mode */
2209                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2210                                         " wrong mq_mode rx %d.",
2211                                         dev_conf->rxmode.mq_mode);
2212                         return -EINVAL;
2213                 }
2214
2215                 switch (dev_conf->txmode.mq_mode) {
2216                 case ETH_MQ_TX_VMDQ_DCB:
2217                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2218                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2219                         break;
2220                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2221                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2222                         break;
2223                 }
2224
2225                 /* check valid queue number */
2226                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2227                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2228                         PMD_INIT_LOG(ERR, "SRIOV is active,"
2229                                         " nb_rx_q=%d nb_tx_q=%d queue number"
2230                                         " must be less than or equal to %d.",
2231                                         nb_rx_q, nb_tx_q,
2232                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2233                         return -EINVAL;
2234                 }
2235         } else {
2236                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2237                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2238                                           " not supported.");
2239                         return -EINVAL;
2240                 }
2241                 /* check configuration for vmdb+dcb mode */
2242                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2243                         const struct rte_eth_vmdq_dcb_conf *conf;
2244
2245                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2246                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2247                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
2248                                 return -EINVAL;
2249                         }
2250                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2251                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2252                                conf->nb_queue_pools == ETH_32_POOLS)) {
2253                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2254                                                 " nb_queue_pools must be %d or %d.",
2255                                                 ETH_16_POOLS, ETH_32_POOLS);
2256                                 return -EINVAL;
2257                         }
2258                 }
2259                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2260                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
2261
2262                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2263                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2264                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
2265                                 return -EINVAL;
2266                         }
2267                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2268                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2269                                conf->nb_queue_pools == ETH_32_POOLS)) {
2270                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2271                                                 " nb_queue_pools != %d and"
2272                                                 " nb_queue_pools != %d.",
2273                                                 ETH_16_POOLS, ETH_32_POOLS);
2274                                 return -EINVAL;
2275                         }
2276                 }
2277
2278                 /* For DCB mode check our configuration before we go further */
2279                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2280                         const struct rte_eth_dcb_rx_conf *conf;
2281
2282                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2283                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2284                                                  IXGBE_DCB_NB_QUEUES);
2285                                 return -EINVAL;
2286                         }
2287                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2288                         if (!(conf->nb_tcs == ETH_4_TCS ||
2289                                conf->nb_tcs == ETH_8_TCS)) {
2290                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2291                                                 " and nb_tcs != %d.",
2292                                                 ETH_4_TCS, ETH_8_TCS);
2293                                 return -EINVAL;
2294                         }
2295                 }
2296
2297                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2298                         const struct rte_eth_dcb_tx_conf *conf;
2299
2300                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2301                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2302                                                  IXGBE_DCB_NB_QUEUES);
2303                                 return -EINVAL;
2304                         }
2305                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2306                         if (!(conf->nb_tcs == ETH_4_TCS ||
2307                                conf->nb_tcs == ETH_8_TCS)) {
2308                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2309                                                 " and nb_tcs != %d.",
2310                                                 ETH_4_TCS, ETH_8_TCS);
2311                                 return -EINVAL;
2312                         }
2313                 }
2314
2315                 /*
2316                  * When DCB/VT is off, maximum number of queues changes,
2317                  * except for 82598EB, which remains constant.
2318                  */
2319                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2320                                 hw->mac.type != ixgbe_mac_82598EB) {
2321                         if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2322                                 PMD_INIT_LOG(ERR,
2323                                              "Neither VT nor DCB are enabled, "
2324                                              "nb_tx_q > %d.",
2325                                              IXGBE_NONE_MODE_TX_NB_QUEUES);
2326                                 return -EINVAL;
2327                         }
2328                 }
2329         }
2330         return 0;
2331 }
2332
2333 static int
2334 ixgbe_dev_configure(struct rte_eth_dev *dev)
2335 {
2336         struct ixgbe_interrupt *intr =
2337                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2338         struct ixgbe_adapter *adapter =
2339                 (struct ixgbe_adapter *)dev->data->dev_private;
2340         int ret;
2341
2342         PMD_INIT_FUNC_TRACE();
2343         /* multipe queue mode checking */
2344         ret  = ixgbe_check_mq_mode(dev);
2345         if (ret != 0) {
2346                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2347                             ret);
2348                 return ret;
2349         }
2350
2351         /* set flag to update link status after init */
2352         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2353
2354         /*
2355          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2356          * allocation or vector Rx preconditions we will reset it.
2357          */
2358         adapter->rx_bulk_alloc_allowed = true;
2359         adapter->rx_vec_allowed = true;
2360
2361         return 0;
2362 }
2363
2364 static void
2365 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2366 {
2367         struct ixgbe_hw *hw =
2368                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369         struct ixgbe_interrupt *intr =
2370                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2371         uint32_t gpie;
2372
2373         /* only set up it on X550EM_X */
2374         if (hw->mac.type == ixgbe_mac_X550EM_x) {
2375                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2376                 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2377                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2378                 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2379                         intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2380         }
2381 }
2382
2383 /*
2384  * Configure device link speed and setup link.
2385  * It returns 0 on success.
2386  */
2387 static int
2388 ixgbe_dev_start(struct rte_eth_dev *dev)
2389 {
2390         struct ixgbe_hw *hw =
2391                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2392         struct ixgbe_vf_info *vfinfo =
2393                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2394         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2395         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2396         uint32_t intr_vector = 0;
2397         int err, link_up = 0, negotiate = 0;
2398         uint32_t speed = 0;
2399         int mask = 0;
2400         int status;
2401         uint16_t vf, idx;
2402         uint32_t *link_speeds;
2403
2404         PMD_INIT_FUNC_TRACE();
2405
2406         /* IXGBE devices don't support:
2407         *    - half duplex (checked afterwards for valid speeds)
2408         *    - fixed speed: TODO implement
2409         */
2410         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2411                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2412                              dev->data->port_id);
2413                 return -EINVAL;
2414         }
2415
2416         /* disable uio/vfio intr/eventfd mapping */
2417         rte_intr_disable(intr_handle);
2418
2419         /* stop adapter */
2420         hw->adapter_stopped = 0;
2421         ixgbe_stop_adapter(hw);
2422
2423         /* reinitialize adapter
2424          * this calls reset and start
2425          */
2426         status = ixgbe_pf_reset_hw(hw);
2427         if (status != 0)
2428                 return -1;
2429         hw->mac.ops.start_hw(hw);
2430         hw->mac.get_link_status = true;
2431
2432         /* configure PF module if SRIOV enabled */
2433         ixgbe_pf_host_configure(dev);
2434
2435         ixgbe_dev_phy_intr_setup(dev);
2436
2437         /* check and configure queue intr-vector mapping */
2438         if ((rte_intr_cap_multiple(intr_handle) ||
2439              !RTE_ETH_DEV_SRIOV(dev).active) &&
2440             dev->data->dev_conf.intr_conf.rxq != 0) {
2441                 intr_vector = dev->data->nb_rx_queues;
2442                 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2443                         PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2444                                         IXGBE_MAX_INTR_QUEUE_NUM);
2445                         return -ENOTSUP;
2446                 }
2447                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2448                         return -1;
2449         }
2450
2451         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2452                 intr_handle->intr_vec =
2453                         rte_zmalloc("intr_vec",
2454                                     dev->data->nb_rx_queues * sizeof(int), 0);
2455                 if (intr_handle->intr_vec == NULL) {
2456                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2457                                      " intr_vec\n", dev->data->nb_rx_queues);
2458                         return -ENOMEM;
2459                 }
2460         }
2461
2462         /* confiugre msix for sleep until rx interrupt */
2463         ixgbe_configure_msix(dev);
2464
2465         /* initialize transmission unit */
2466         ixgbe_dev_tx_init(dev);
2467
2468         /* This can fail when allocating mbufs for descriptor rings */
2469         err = ixgbe_dev_rx_init(dev);
2470         if (err) {
2471                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2472                 goto error;
2473         }
2474
2475     mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2476                 ETH_VLAN_EXTEND_MASK;
2477         ixgbe_vlan_offload_set(dev, mask);
2478
2479         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2480                 /* Enable vlan filtering for VMDq */
2481                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2482         }
2483
2484         /* Configure DCB hw */
2485         ixgbe_configure_dcb(dev);
2486
2487         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2488                 err = ixgbe_fdir_configure(dev);
2489                 if (err)
2490                         goto error;
2491         }
2492
2493         /* Restore vf rate limit */
2494         if (vfinfo != NULL) {
2495                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2496                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2497                                 if (vfinfo[vf].tx_rate[idx] != 0)
2498                                         rte_pmd_ixgbe_set_vf_rate_limit(
2499                                                 dev->data->port_id, vf,
2500                                                 vfinfo[vf].tx_rate[idx],
2501                                                 1 << idx);
2502         }
2503
2504         ixgbe_restore_statistics_mapping(dev);
2505
2506         err = ixgbe_dev_rxtx_start(dev);
2507         if (err < 0) {
2508                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2509                 goto error;
2510         }
2511
2512         /* Skip link setup if loopback mode is enabled for 82599. */
2513         if (hw->mac.type == ixgbe_mac_82599EB &&
2514                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2515                 goto skip_link_setup;
2516
2517         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2518                 err = hw->mac.ops.setup_sfp(hw);
2519                 if (err)
2520                         goto error;
2521         }
2522
2523         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2524                 /* Turn on the copper */
2525                 ixgbe_set_phy_power(hw, true);
2526         } else {
2527                 /* Turn on the laser */
2528                 ixgbe_enable_tx_laser(hw);
2529         }
2530
2531         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2532         if (err)
2533                 goto error;
2534         dev->data->dev_link.link_status = link_up;
2535
2536         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2537         if (err)
2538                 goto error;
2539
2540         link_speeds = &dev->data->dev_conf.link_speeds;
2541         if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2542                         ETH_LINK_SPEED_10G)) {
2543                 PMD_INIT_LOG(ERR, "Invalid link setting");
2544                 goto error;
2545         }
2546
2547         speed = 0x0;
2548         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2549                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2550                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2551                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2552         } else {
2553                 if (*link_speeds & ETH_LINK_SPEED_10G)
2554                         speed |= IXGBE_LINK_SPEED_10GB_FULL;
2555                 if (*link_speeds & ETH_LINK_SPEED_1G)
2556                         speed |= IXGBE_LINK_SPEED_1GB_FULL;
2557                 if (*link_speeds & ETH_LINK_SPEED_100M)
2558                         speed |= IXGBE_LINK_SPEED_100_FULL;
2559         }
2560
2561         err = ixgbe_setup_link(hw, speed, link_up);
2562         if (err)
2563                 goto error;
2564
2565 skip_link_setup:
2566
2567         if (rte_intr_allow_others(intr_handle)) {
2568                 /* check if lsc interrupt is enabled */
2569                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2570                         ixgbe_dev_lsc_interrupt_setup(dev);
2571                 ixgbe_dev_macsec_interrupt_setup(dev);
2572         } else {
2573                 rte_intr_callback_unregister(intr_handle,
2574                                              ixgbe_dev_interrupt_handler, dev);
2575                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2576                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2577                                      " no intr multiplex\n");
2578         }
2579
2580         /* check if rxq interrupt is enabled */
2581         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2582             rte_intr_dp_is_en(intr_handle))
2583                 ixgbe_dev_rxq_interrupt_setup(dev);
2584
2585         /* enable uio/vfio intr/eventfd mapping */
2586         rte_intr_enable(intr_handle);
2587
2588         /* resume enabled intr since hw reset */
2589         ixgbe_enable_intr(dev);
2590         ixgbe_l2_tunnel_conf(dev);
2591         ixgbe_filter_restore(dev);
2592
2593         return 0;
2594
2595 error:
2596         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2597         ixgbe_dev_clear_queues(dev);
2598         return -EIO;
2599 }
2600
2601 /*
2602  * Stop device: disable rx and tx functions to allow for reconfiguring.
2603  */
2604 static void
2605 ixgbe_dev_stop(struct rte_eth_dev *dev)
2606 {
2607         struct rte_eth_link link;
2608         struct ixgbe_hw *hw =
2609                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2610         struct ixgbe_vf_info *vfinfo =
2611                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2612         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
2613         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2614         int vf;
2615
2616         PMD_INIT_FUNC_TRACE();
2617
2618         /* disable interrupts */
2619         ixgbe_disable_intr(hw);
2620
2621         /* reset the NIC */
2622         ixgbe_pf_reset_hw(hw);
2623         hw->adapter_stopped = 0;
2624
2625         /* stop adapter */
2626         ixgbe_stop_adapter(hw);
2627
2628         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2629                 vfinfo[vf].clear_to_send = false;
2630
2631         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2632                 /* Turn off the copper */
2633                 ixgbe_set_phy_power(hw, false);
2634         } else {
2635                 /* Turn off the laser */
2636                 ixgbe_disable_tx_laser(hw);
2637         }
2638
2639         ixgbe_dev_clear_queues(dev);
2640
2641         /* Clear stored conf */
2642         dev->data->scattered_rx = 0;
2643         dev->data->lro = 0;
2644
2645         /* Clear recorded link status */
2646         memset(&link, 0, sizeof(link));
2647         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2648
2649         if (!rte_intr_allow_others(intr_handle))
2650                 /* resume to the default handler */
2651                 rte_intr_callback_register(intr_handle,
2652                                            ixgbe_dev_interrupt_handler,
2653                                            (void *)dev);
2654
2655         /* Clean datapath event and queue/vec mapping */
2656         rte_intr_efd_disable(intr_handle);
2657         if (intr_handle->intr_vec != NULL) {
2658                 rte_free(intr_handle->intr_vec);
2659                 intr_handle->intr_vec = NULL;
2660         }
2661 }
2662
2663 /*
2664  * Set device link up: enable tx.
2665  */
2666 static int
2667 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2668 {
2669         struct ixgbe_hw *hw =
2670                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         if (hw->mac.type == ixgbe_mac_82599EB) {
2672 #ifdef RTE_NIC_BYPASS
2673                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2674                         /* Not suported in bypass mode */
2675                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2676                                      "by device id 0x%x", hw->device_id);
2677                         return -ENOTSUP;
2678                 }
2679 #endif
2680         }
2681
2682         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2683                 /* Turn on the copper */
2684                 ixgbe_set_phy_power(hw, true);
2685         } else {
2686                 /* Turn on the laser */
2687                 ixgbe_enable_tx_laser(hw);
2688         }
2689
2690         return 0;
2691 }
2692
2693 /*
2694  * Set device link down: disable tx.
2695  */
2696 static int
2697 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2698 {
2699         struct ixgbe_hw *hw =
2700                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2701         if (hw->mac.type == ixgbe_mac_82599EB) {
2702 #ifdef RTE_NIC_BYPASS
2703                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2704                         /* Not suported in bypass mode */
2705                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2706                                      "by device id 0x%x", hw->device_id);
2707                         return -ENOTSUP;
2708                 }
2709 #endif
2710         }
2711
2712         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2713                 /* Turn off the copper */
2714                 ixgbe_set_phy_power(hw, false);
2715         } else {
2716                 /* Turn off the laser */
2717                 ixgbe_disable_tx_laser(hw);
2718         }
2719
2720         return 0;
2721 }
2722
2723 /*
2724  * Reest and stop device.
2725  */
2726 static void
2727 ixgbe_dev_close(struct rte_eth_dev *dev)
2728 {
2729         struct ixgbe_hw *hw =
2730                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2731
2732         PMD_INIT_FUNC_TRACE();
2733
2734         ixgbe_pf_reset_hw(hw);
2735
2736         ixgbe_dev_stop(dev);
2737         hw->adapter_stopped = 1;
2738
2739         ixgbe_dev_free_queues(dev);
2740
2741         ixgbe_disable_pcie_master(hw);
2742
2743         /* reprogram the RAR[0] in case user changed it. */
2744         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2745 }
2746
2747 static void
2748 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2749                            struct ixgbe_hw_stats *hw_stats,
2750                            struct ixgbe_macsec_stats *macsec_stats,
2751                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2752                            uint64_t *total_qprc, uint64_t *total_qprdc)
2753 {
2754         uint32_t bprc, lxon, lxoff, total;
2755         uint32_t delta_gprc = 0;
2756         unsigned i;
2757         /* Workaround for RX byte count not including CRC bytes when CRC
2758          * strip is enabled. CRC bytes are removed from counters when crc_strip
2759          * is disabled.
2760          */
2761         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2762                         IXGBE_HLREG0_RXCRCSTRP);
2763
2764         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2765         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2766         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2767         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2768
2769         for (i = 0; i < 8; i++) {
2770                 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2771
2772                 /* global total per queue */
2773                 hw_stats->mpc[i] += mp;
2774                 /* Running comprehensive total for stats display */
2775                 *total_missed_rx += hw_stats->mpc[i];
2776                 if (hw->mac.type == ixgbe_mac_82598EB) {
2777                         hw_stats->rnbc[i] +=
2778                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2779                         hw_stats->pxonrxc[i] +=
2780                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2781                         hw_stats->pxoffrxc[i] +=
2782                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2783                 } else {
2784                         hw_stats->pxonrxc[i] +=
2785                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2786                         hw_stats->pxoffrxc[i] +=
2787                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2788                         hw_stats->pxon2offc[i] +=
2789                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2790                 }
2791                 hw_stats->pxontxc[i] +=
2792                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2793                 hw_stats->pxofftxc[i] +=
2794                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2795         }
2796         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2797                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2798                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2799                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2800
2801                 delta_gprc += delta_qprc;
2802
2803                 hw_stats->qprc[i] += delta_qprc;
2804                 hw_stats->qptc[i] += delta_qptc;
2805
2806                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2807                 hw_stats->qbrc[i] +=
2808                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2809                 if (crc_strip == 0)
2810                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2811
2812                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2813                 hw_stats->qbtc[i] +=
2814                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2815
2816                 hw_stats->qprdc[i] += delta_qprdc;
2817                 *total_qprdc += hw_stats->qprdc[i];
2818
2819                 *total_qprc += hw_stats->qprc[i];
2820                 *total_qbrc += hw_stats->qbrc[i];
2821         }
2822         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2823         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2824         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2825
2826         /*
2827          * An errata states that gprc actually counts good + missed packets:
2828          * Workaround to set gprc to summated queue packet receives
2829          */
2830         hw_stats->gprc = *total_qprc;
2831
2832         if (hw->mac.type != ixgbe_mac_82598EB) {
2833                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2834                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2835                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2836                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2837                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2838                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2839                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2840                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2841         } else {
2842                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2843                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2844                 /* 82598 only has a counter in the high register */
2845                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2846                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2847                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2848         }
2849         uint64_t old_tpr = hw_stats->tpr;
2850
2851         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2852         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2853
2854         if (crc_strip == 0)
2855                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2856
2857         uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2858         hw_stats->gptc += delta_gptc;
2859         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2860         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2861
2862         /*
2863          * Workaround: mprc hardware is incorrectly counting
2864          * broadcasts, so for now we subtract those.
2865          */
2866         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2867         hw_stats->bprc += bprc;
2868         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2869         if (hw->mac.type == ixgbe_mac_82598EB)
2870                 hw_stats->mprc -= bprc;
2871
2872         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2873         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2874         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2875         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2876         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2877         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2878
2879         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2880         hw_stats->lxontxc += lxon;
2881         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2882         hw_stats->lxofftxc += lxoff;
2883         total = lxon + lxoff;
2884
2885         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2886         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2887         hw_stats->gptc -= total;
2888         hw_stats->mptc -= total;
2889         hw_stats->ptc64 -= total;
2890         hw_stats->gotc -= total * ETHER_MIN_LEN;
2891
2892         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2893         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2894         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2895         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2896         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2897         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2898         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2899         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2900         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2901         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2902         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2903         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2904         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2905         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2906         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2907         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2908         /* Only read FCOE on 82599 */
2909         if (hw->mac.type != ixgbe_mac_82598EB) {
2910                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2911                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2912                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2913                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2914                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2915         }
2916
2917         /* Flow Director Stats registers */
2918         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2919         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2920
2921         /* MACsec Stats registers */
2922         macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
2923         macsec_stats->out_pkts_encrypted +=
2924                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
2925         macsec_stats->out_pkts_protected +=
2926                 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
2927         macsec_stats->out_octets_encrypted +=
2928                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
2929         macsec_stats->out_octets_protected +=
2930                 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
2931         macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
2932         macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
2933         macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
2934         macsec_stats->in_pkts_unknownsci +=
2935                 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
2936         macsec_stats->in_octets_decrypted +=
2937                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
2938         macsec_stats->in_octets_validated +=
2939                 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
2940         macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
2941         macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
2942         macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
2943         for (i = 0; i < 2; i++) {
2944                 macsec_stats->in_pkts_ok +=
2945                         IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
2946                 macsec_stats->in_pkts_invalid +=
2947                         IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
2948                 macsec_stats->in_pkts_notvalid +=
2949                         IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
2950         }
2951         macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
2952         macsec_stats->in_pkts_notusingsa +=
2953                 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
2954 }
2955
2956 /*
2957  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2958  */
2959 static void
2960 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2961 {
2962         struct ixgbe_hw *hw =
2963                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964         struct ixgbe_hw_stats *hw_stats =
2965                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2966         struct ixgbe_macsec_stats *macsec_stats =
2967                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
2968                                 dev->data->dev_private);
2969         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2970         unsigned i;
2971
2972         total_missed_rx = 0;
2973         total_qbrc = 0;
2974         total_qprc = 0;
2975         total_qprdc = 0;
2976
2977         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
2978                         &total_qbrc, &total_qprc, &total_qprdc);
2979
2980         if (stats == NULL)
2981                 return;
2982
2983         /* Fill out the rte_eth_stats statistics structure */
2984         stats->ipackets = total_qprc;
2985         stats->ibytes = total_qbrc;
2986         stats->opackets = hw_stats->gptc;
2987         stats->obytes = hw_stats->gotc;
2988
2989         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2990                 stats->q_ipackets[i] = hw_stats->qprc[i];
2991                 stats->q_opackets[i] = hw_stats->qptc[i];
2992                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2993                 stats->q_obytes[i] = hw_stats->qbtc[i];
2994                 stats->q_errors[i] = hw_stats->qprdc[i];
2995         }
2996
2997         /* Rx Errors */
2998         stats->imissed  = total_missed_rx;
2999         stats->ierrors  = hw_stats->crcerrs +
3000                           hw_stats->mspdc +
3001                           hw_stats->rlec +
3002                           hw_stats->ruc +
3003                           hw_stats->roc +
3004                           hw_stats->illerrc +
3005                           hw_stats->errbc +
3006                           hw_stats->rfc +
3007                           hw_stats->fccrc +
3008                           hw_stats->fclast;
3009
3010         /* Tx Errors */
3011         stats->oerrors  = 0;
3012 }
3013
3014 static void
3015 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3016 {
3017         struct ixgbe_hw_stats *stats =
3018                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3019
3020         /* HW registers are cleared on read */
3021         ixgbe_dev_stats_get(dev, NULL);
3022
3023         /* Reset software totals */
3024         memset(stats, 0, sizeof(*stats));
3025 }
3026
3027 /* This function calculates the number of xstats based on the current config */
3028 static unsigned
3029 ixgbe_xstats_calc_num(void) {
3030         return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3031                 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3032                 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3033 }
3034
3035 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3036         struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned limit)
3037 {
3038         const unsigned cnt_stats = ixgbe_xstats_calc_num();
3039         unsigned stat, i, count;
3040
3041         if (xstats_names != NULL) {
3042                 count = 0;
3043
3044                 /* Note: limit >= cnt_stats checked upstream
3045                  * in rte_eth_xstats_names()
3046                  */
3047
3048                 /* Extended stats from ixgbe_hw_stats */
3049                 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3050                         snprintf(xstats_names[count].name,
3051                                 sizeof(xstats_names[count].name),
3052                                 "%s",
3053                                 rte_ixgbe_stats_strings[i].name);
3054                         count++;
3055                 }
3056
3057                 /* MACsec Stats */
3058                 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3059                         snprintf(xstats_names[count].name,
3060                                 sizeof(xstats_names[count].name),
3061                                 "%s",
3062                                 rte_ixgbe_macsec_strings[i].name);
3063                         count++;
3064                 }
3065
3066                 /* RX Priority Stats */
3067                 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3068                         for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3069                                 snprintf(xstats_names[count].name,
3070                                         sizeof(xstats_names[count].name),
3071                                         "rx_priority%u_%s", i,
3072                                         rte_ixgbe_rxq_strings[stat].name);
3073                                 count++;
3074                         }
3075                 }
3076
3077                 /* TX Priority Stats */
3078                 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3079                         for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3080                                 snprintf(xstats_names[count].name,
3081                                         sizeof(xstats_names[count].name),
3082                                         "tx_priority%u_%s", i,
3083                                         rte_ixgbe_txq_strings[stat].name);
3084                                 count++;
3085                         }
3086                 }
3087         }
3088         return cnt_stats;
3089 }
3090
3091 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3092         struct rte_eth_xstat_name *xstats_names, unsigned limit)
3093 {
3094         unsigned i;
3095
3096         if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3097                 return -ENOMEM;
3098
3099         if (xstats_names != NULL)
3100                 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3101                         snprintf(xstats_names[i].name,
3102                                 sizeof(xstats_names[i].name),
3103                                 "%s", rte_ixgbevf_stats_strings[i].name);
3104         return IXGBEVF_NB_XSTATS;
3105 }
3106
3107 static int
3108 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3109                                          unsigned n)
3110 {
3111         struct ixgbe_hw *hw =
3112                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         struct ixgbe_hw_stats *hw_stats =
3114                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3115         struct ixgbe_macsec_stats *macsec_stats =
3116                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3117                                 dev->data->dev_private);
3118         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3119         unsigned i, stat, count = 0;
3120
3121         count = ixgbe_xstats_calc_num();
3122
3123         if (n < count)
3124                 return count;
3125
3126         total_missed_rx = 0;
3127         total_qbrc = 0;
3128         total_qprc = 0;
3129         total_qprdc = 0;
3130
3131         ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3132                         &total_qbrc, &total_qprc, &total_qprdc);
3133
3134         /* If this is a reset xstats is NULL, and we have cleared the
3135          * registers by reading them.
3136          */
3137         if (!xstats)
3138                 return 0;
3139
3140         /* Extended stats from ixgbe_hw_stats */
3141         count = 0;
3142         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3143                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3144                                 rte_ixgbe_stats_strings[i].offset);
3145                 xstats[count].id = count;
3146                 count++;
3147         }
3148
3149         /* MACsec Stats */
3150         for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3151                 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3152                                 rte_ixgbe_macsec_strings[i].offset);
3153                 xstats[count].id = count;
3154                 count++;
3155         }
3156
3157         /* RX Priority Stats */
3158         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3159                 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3160                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3161                                         rte_ixgbe_rxq_strings[stat].offset +
3162                                         (sizeof(uint64_t) * i));
3163                         xstats[count].id = count;
3164                         count++;
3165                 }
3166         }
3167
3168         /* TX Priority Stats */
3169         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3170                 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3171                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3172                                         rte_ixgbe_txq_strings[stat].offset +
3173                                         (sizeof(uint64_t) * i));
3174                         xstats[count].id = count;
3175                         count++;
3176                 }
3177         }
3178         return count;
3179 }
3180
3181 static void
3182 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3183 {
3184         struct ixgbe_hw_stats *stats =
3185                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3186         struct ixgbe_macsec_stats *macsec_stats =
3187                         IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3188                                 dev->data->dev_private);
3189
3190         unsigned count = ixgbe_xstats_calc_num();
3191
3192         /* HW registers are cleared on read */
3193         ixgbe_dev_xstats_get(dev, NULL, count);
3194
3195         /* Reset software totals */
3196         memset(stats, 0, sizeof(*stats));
3197         memset(macsec_stats, 0, sizeof(*macsec_stats));
3198 }
3199
3200 static void
3201 ixgbevf_update_stats(struct rte_eth_dev *dev)
3202 {
3203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3204         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3205                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3206
3207         /* Good Rx packet, include VF loopback */
3208         UPDATE_VF_STAT(IXGBE_VFGPRC,
3209             hw_stats->last_vfgprc, hw_stats->vfgprc);
3210
3211         /* Good Rx octets, include VF loopback */
3212         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3213             hw_stats->last_vfgorc, hw_stats->vfgorc);
3214
3215         /* Good Tx packet, include VF loopback */
3216         UPDATE_VF_STAT(IXGBE_VFGPTC,
3217             hw_stats->last_vfgptc, hw_stats->vfgptc);
3218
3219         /* Good Tx octets, include VF loopback */
3220         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3221             hw_stats->last_vfgotc, hw_stats->vfgotc);
3222
3223         /* Rx Multicst Packet */
3224         UPDATE_VF_STAT(IXGBE_VFMPRC,
3225             hw_stats->last_vfmprc, hw_stats->vfmprc);
3226 }
3227
3228 static int
3229 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3230                        unsigned n)
3231 {
3232         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3233                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3234         unsigned i;
3235
3236         if (n < IXGBEVF_NB_XSTATS)
3237                 return IXGBEVF_NB_XSTATS;
3238
3239         ixgbevf_update_stats(dev);
3240
3241         if (!xstats)
3242                 return 0;
3243
3244         /* Extended stats */
3245         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3246                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3247                         rte_ixgbevf_stats_strings[i].offset);
3248         }
3249
3250         return IXGBEVF_NB_XSTATS;
3251 }
3252
3253 static void
3254 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3255 {
3256         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3257                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3258
3259         ixgbevf_update_stats(dev);
3260
3261         if (stats == NULL)
3262                 return;
3263
3264         stats->ipackets = hw_stats->vfgprc;
3265         stats->ibytes = hw_stats->vfgorc;
3266         stats->opackets = hw_stats->vfgptc;
3267         stats->obytes = hw_stats->vfgotc;
3268 }
3269
3270 static void
3271 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3272 {
3273         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3274                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3275
3276         /* Sync HW register to the last stats */
3277         ixgbevf_dev_stats_get(dev, NULL);
3278
3279         /* reset HW current stats*/
3280         hw_stats->vfgprc = 0;
3281         hw_stats->vfgorc = 0;
3282         hw_stats->vfgptc = 0;
3283         hw_stats->vfgotc = 0;
3284 }
3285
3286 static int
3287 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3288 {
3289         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3290         u16 eeprom_verh, eeprom_verl;
3291         u32 etrack_id;
3292         int ret;
3293
3294         ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3295         ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3296
3297         etrack_id = (eeprom_verh << 16) | eeprom_verl;
3298         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3299
3300         ret += 1; /* add the size of '\0' */
3301         if (fw_size < (u32)ret)
3302                 return ret;
3303         else
3304                 return 0;
3305 }
3306
3307 static void
3308 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3309 {
3310         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3311         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3312         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3313
3314         dev_info->pci_dev = pci_dev;
3315         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3316         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3317         if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3318                 /*
3319                  * When DCB/VT is off, maximum number of queues changes,
3320                  * except for 82598EB, which remains constant.
3321                  */
3322                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3323                                 hw->mac.type != ixgbe_mac_82598EB)
3324                         dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3325         }
3326         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3327         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3328         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3329         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3330         dev_info->max_vfs = pci_dev->max_vfs;
3331         if (hw->mac.type == ixgbe_mac_82598EB)
3332                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3333         else
3334                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3335         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3336         dev_info->rx_offload_capa =
3337                 DEV_RX_OFFLOAD_VLAN_STRIP |
3338                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3339                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3340                 DEV_RX_OFFLOAD_TCP_CKSUM;
3341
3342         /*
3343          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3344          * mode.
3345          */
3346         if ((hw->mac.type == ixgbe_mac_82599EB ||
3347              hw->mac.type == ixgbe_mac_X540) &&
3348             !RTE_ETH_DEV_SRIOV(dev).active)
3349                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3350
3351         if (hw->mac.type == ixgbe_mac_82599EB ||
3352             hw->mac.type == ixgbe_mac_X540)
3353                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3354
3355         if (hw->mac.type == ixgbe_mac_X550 ||
3356             hw->mac.type == ixgbe_mac_X550EM_x ||
3357             hw->mac.type == ixgbe_mac_X550EM_a)
3358                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3359
3360         dev_info->tx_offload_capa =
3361                 DEV_TX_OFFLOAD_VLAN_INSERT |
3362                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3363                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3364                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3365                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3366                 DEV_TX_OFFLOAD_TCP_TSO;
3367
3368         if (hw->mac.type == ixgbe_mac_82599EB ||
3369             hw->mac.type == ixgbe_mac_X540)
3370                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3371
3372         if (hw->mac.type == ixgbe_mac_X550 ||
3373             hw->mac.type == ixgbe_mac_X550EM_x ||
3374             hw->mac.type == ixgbe_mac_X550EM_a)
3375                 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3376
3377         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3378                 .rx_thresh = {
3379                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3380                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3381                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3382                 },
3383                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3384                 .rx_drop_en = 0,
3385         };
3386
3387         dev_info->default_txconf = (struct rte_eth_txconf) {
3388                 .tx_thresh = {
3389                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3390                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3391                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3392                 },
3393                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3394                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3395                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3396                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3397         };
3398
3399         dev_info->rx_desc_lim = rx_desc_lim;
3400         dev_info->tx_desc_lim = tx_desc_lim;
3401
3402         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3403         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3404         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3405
3406         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3407         if (hw->mac.type == ixgbe_mac_X540 ||
3408             hw->mac.type == ixgbe_mac_X540_vf ||
3409             hw->mac.type == ixgbe_mac_X550 ||
3410             hw->mac.type == ixgbe_mac_X550_vf) {
3411                 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3412         }
3413 }
3414
3415 static const uint32_t *
3416 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3417 {
3418         static const uint32_t ptypes[] = {
3419                 /* For non-vec functions,
3420                  * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3421                  * for vec functions,
3422                  * refers to _recv_raw_pkts_vec().
3423                  */
3424                 RTE_PTYPE_L2_ETHER,
3425                 RTE_PTYPE_L3_IPV4,
3426                 RTE_PTYPE_L3_IPV4_EXT,
3427                 RTE_PTYPE_L3_IPV6,
3428                 RTE_PTYPE_L3_IPV6_EXT,
3429                 RTE_PTYPE_L4_SCTP,
3430                 RTE_PTYPE_L4_TCP,
3431                 RTE_PTYPE_L4_UDP,
3432                 RTE_PTYPE_TUNNEL_IP,
3433                 RTE_PTYPE_INNER_L3_IPV6,
3434                 RTE_PTYPE_INNER_L3_IPV6_EXT,
3435                 RTE_PTYPE_INNER_L4_TCP,
3436                 RTE_PTYPE_INNER_L4_UDP,
3437                 RTE_PTYPE_UNKNOWN
3438         };
3439
3440         if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3441             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3442             dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3443             dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3444                 return ptypes;
3445         return NULL;
3446 }
3447
3448 static void
3449 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3450                      struct rte_eth_dev_info *dev_info)
3451 {
3452         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3453         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3454
3455         dev_info->pci_dev = pci_dev;
3456         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3457         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3458         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3459         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
3460         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3461         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3462         dev_info->max_vfs = pci_dev->max_vfs;
3463         if (hw->mac.type == ixgbe_mac_82598EB)
3464                 dev_info->max_vmdq_pools = ETH_16_POOLS;
3465         else
3466                 dev_info->max_vmdq_pools = ETH_64_POOLS;
3467         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3468                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3469                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
3470                                 DEV_RX_OFFLOAD_TCP_CKSUM;
3471         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3472                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
3473                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
3474                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
3475                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
3476                                 DEV_TX_OFFLOAD_TCP_TSO;
3477
3478         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3479                 .rx_thresh = {
3480                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3481                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3482                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3483                 },
3484                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3485                 .rx_drop_en = 0,
3486         };
3487
3488         dev_info->default_txconf = (struct rte_eth_txconf) {
3489                 .tx_thresh = {
3490                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3491                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3492                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3493                 },
3494                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3495                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3496                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3497                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3498         };
3499
3500         dev_info->rx_desc_lim = rx_desc_lim;
3501         dev_info->tx_desc_lim = tx_desc_lim;
3502 }
3503
3504 /* return 0 means link status changed, -1 means not changed */
3505 static int
3506 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3507 {
3508         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3509         struct rte_eth_link link, old;
3510         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3511         int link_up;
3512         int diag;
3513
3514         link.link_status = ETH_LINK_DOWN;
3515         link.link_speed = 0;
3516         link.link_duplex = ETH_LINK_HALF_DUPLEX;
3517         memset(&old, 0, sizeof(old));
3518         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3519
3520         hw->mac.get_link_status = true;
3521
3522         /* check if it needs to wait to complete, if lsc interrupt is enabled */
3523         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3524                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3525         else
3526                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3527
3528         if (diag != 0) {
3529                 link.link_speed = ETH_SPEED_NUM_100M;
3530                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3531                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3532                 if (link.link_status == old.link_status)
3533                         return -1;
3534                 return 0;
3535         }
3536
3537         if (link_up == 0) {
3538                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3539                 if (link.link_status == old.link_status)
3540                         return -1;
3541                 return 0;
3542         }
3543         link.link_status = ETH_LINK_UP;
3544         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3545
3546         switch (link_speed) {
3547         default:
3548         case IXGBE_LINK_SPEED_UNKNOWN:
3549                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3550                 link.link_speed = ETH_SPEED_NUM_100M;
3551                 break;
3552
3553         case IXGBE_LINK_SPEED_100_FULL:
3554                 link.link_speed = ETH_SPEED_NUM_100M;
3555                 break;
3556
3557         case IXGBE_LINK_SPEED_1GB_FULL:
3558                 link.link_speed = ETH_SPEED_NUM_1G;
3559                 break;
3560
3561         case IXGBE_LINK_SPEED_10GB_FULL:
3562                 link.link_speed = ETH_SPEED_NUM_10G;
3563                 break;
3564         }
3565         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3566
3567         if (link.link_status == old.link_status)
3568                 return -1;
3569
3570         return 0;
3571 }
3572
3573 static void
3574 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3575 {
3576         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3577         uint32_t fctrl;
3578
3579         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3580         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3581         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3582 }
3583
3584 static void
3585 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3586 {
3587         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3588         uint32_t fctrl;
3589
3590         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3591         fctrl &= (~IXGBE_FCTRL_UPE);
3592         if (dev->data->all_multicast == 1)
3593                 fctrl |= IXGBE_FCTRL_MPE;
3594         else
3595                 fctrl &= (~IXGBE_FCTRL_MPE);
3596         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3597 }
3598
3599 static void
3600 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3601 {
3602         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603         uint32_t fctrl;
3604
3605         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3606         fctrl |= IXGBE_FCTRL_MPE;
3607         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3608 }
3609
3610 static void
3611 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3612 {
3613         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3614         uint32_t fctrl;
3615
3616         if (dev->data->promiscuous == 1)
3617                 return; /* must remain in all_multicast mode */
3618
3619         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3620         fctrl &= (~IXGBE_FCTRL_MPE);
3621         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3622 }
3623
3624 /**
3625  * It clears the interrupt causes and enables the interrupt.
3626  * It will be called once only during nic initialized.
3627  *
3628  * @param dev
3629  *  Pointer to struct rte_eth_dev.
3630  *
3631  * @return
3632  *  - On success, zero.
3633  *  - On failure, a negative value.
3634  */
3635 static int
3636 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3637 {
3638         struct ixgbe_interrupt *intr =
3639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3640
3641         ixgbe_dev_link_status_print(dev);
3642         intr->mask |= IXGBE_EICR_LSC;
3643
3644         return 0;
3645 }
3646
3647 /**
3648  * It clears the interrupt causes and enables the interrupt.
3649  * It will be called once only during nic initialized.
3650  *
3651  * @param dev
3652  *  Pointer to struct rte_eth_dev.
3653  *
3654  * @return
3655  *  - On success, zero.
3656  *  - On failure, a negative value.
3657  */
3658 static int
3659 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3660 {
3661         struct ixgbe_interrupt *intr =
3662                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3663
3664         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3665
3666         return 0;
3667 }
3668
3669 /**
3670  * It clears the interrupt causes and enables the interrupt.
3671  * It will be called once only during nic initialized.
3672  *
3673  * @param dev
3674  *  Pointer to struct rte_eth_dev.
3675  *
3676  * @return
3677  *  - On success, zero.
3678  *  - On failure, a negative value.
3679  */
3680 static int
3681 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3682 {
3683         struct ixgbe_interrupt *intr =
3684                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3685
3686         intr->mask |= IXGBE_EICR_LINKSEC;
3687
3688         return 0;
3689 }
3690
3691 /*
3692  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3693  *
3694  * @param dev
3695  *  Pointer to struct rte_eth_dev.
3696  *
3697  * @return
3698  *  - On success, zero.
3699  *  - On failure, a negative value.
3700  */
3701 static int
3702 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3703 {
3704         uint32_t eicr;
3705         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3706         struct ixgbe_interrupt *intr =
3707                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3708
3709         /* clear all cause mask */
3710         ixgbe_disable_intr(hw);
3711
3712         /* read-on-clear nic registers here */
3713         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3714         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3715
3716         intr->flags = 0;
3717
3718         /* set flag for async link update */
3719         if (eicr & IXGBE_EICR_LSC)
3720                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3721
3722         if (eicr & IXGBE_EICR_MAILBOX)
3723                 intr->flags |= IXGBE_FLAG_MAILBOX;
3724
3725         if (eicr & IXGBE_EICR_LINKSEC)
3726                 intr->flags |= IXGBE_FLAG_MACSEC;
3727
3728         if (hw->mac.type ==  ixgbe_mac_X550EM_x &&
3729             hw->phy.type == ixgbe_phy_x550em_ext_t &&
3730             (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
3731                 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
3732
3733         return 0;
3734 }
3735
3736 /**
3737  * It gets and then prints the link status.
3738  *
3739  * @param dev
3740  *  Pointer to struct rte_eth_dev.
3741  *
3742  * @return
3743  *  - On success, zero.
3744  *  - On failure, a negative value.
3745  */
3746 static void
3747 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3748 {
3749         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3750         struct rte_eth_link link;
3751
3752         memset(&link, 0, sizeof(link));
3753         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3754         if (link.link_status) {
3755                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3756                                         (int)(dev->data->port_id),
3757                                         (unsigned)link.link_speed,
3758                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3759                                         "full-duplex" : "half-duplex");
3760         } else {
3761                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3762                                 (int)(dev->data->port_id));
3763         }
3764         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3765                                 pci_dev->addr.domain,
3766                                 pci_dev->addr.bus,
3767                                 pci_dev->addr.devid,
3768                                 pci_dev->addr.function);
3769 }
3770
3771 /*
3772  * It executes link_update after knowing an interrupt occurred.
3773  *
3774  * @param dev
3775  *  Pointer to struct rte_eth_dev.
3776  *
3777  * @return
3778  *  - On success, zero.
3779  *  - On failure, a negative value.
3780  */
3781 static int
3782 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3783                            struct rte_intr_handle *intr_handle)
3784 {
3785         struct ixgbe_interrupt *intr =
3786                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3787         int64_t timeout;
3788         struct rte_eth_link link;
3789         struct ixgbe_hw *hw =
3790                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791
3792         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3793
3794         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3795                 ixgbe_pf_mbx_process(dev);
3796                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3797         }
3798
3799         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3800                 ixgbe_handle_lasi(hw);
3801                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3802         }
3803
3804         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3805                 /* get the link status before link update, for predicting later */
3806                 memset(&link, 0, sizeof(link));
3807                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3808
3809                 ixgbe_dev_link_update(dev, 0);
3810
3811                 /* likely to up */
3812                 if (!link.link_status)
3813                         /* handle it 1 sec later, wait it being stable */
3814                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3815                 /* likely to down */
3816                 else
3817                         /* handle it 4 sec later, wait it being stable */
3818                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3819
3820                 ixgbe_dev_link_status_print(dev);
3821                 intr->mask_original = intr->mask;
3822                 /* only disable lsc interrupt */
3823                 intr->mask &= ~IXGBE_EIMS_LSC;
3824                 if (rte_eal_alarm_set(timeout * 1000,
3825                                       ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
3826                         PMD_DRV_LOG(ERR, "Error setting alarm");
3827                 else
3828                         intr->mask = intr->mask_original;
3829         }
3830
3831         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3832         ixgbe_enable_intr(dev);
3833         rte_intr_enable(intr_handle);
3834
3835         return 0;
3836 }
3837
3838 /**
3839  * Interrupt handler which shall be registered for alarm callback for delayed
3840  * handling specific interrupt to wait for the stable nic state. As the
3841  * NIC interrupt state is not stable for ixgbe after link is just down,
3842  * it needs to wait 4 seconds to get the stable status.
3843  *
3844  * @param handle
3845  *  Pointer to interrupt handle.
3846  * @param param
3847  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3848  *
3849  * @return
3850  *  void
3851  */
3852 static void
3853 ixgbe_dev_interrupt_delayed_handler(void *param)
3854 {
3855         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3856         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
3857         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3858         struct ixgbe_interrupt *intr =
3859                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3860         struct ixgbe_hw *hw =
3861                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3862         uint32_t eicr;
3863
3864         ixgbe_disable_intr(hw);
3865
3866         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3867         if (eicr & IXGBE_EICR_MAILBOX)
3868                 ixgbe_pf_mbx_process(dev);
3869
3870         if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
3871                 ixgbe_handle_lasi(hw);
3872                 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
3873         }
3874
3875         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3876                 ixgbe_dev_link_update(dev, 0);
3877                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3878                 ixgbe_dev_link_status_print(dev);
3879                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
3880         }
3881
3882         if (intr->flags & IXGBE_FLAG_MACSEC) {
3883                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3884                                               NULL);
3885                 intr->flags &= ~IXGBE_FLAG_MACSEC;
3886         }
3887
3888         /* restore original mask */
3889         intr->mask = intr->mask_original;
3890         intr->mask_original = 0;
3891
3892         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3893         ixgbe_enable_intr(dev);
3894         rte_intr_enable(intr_handle);
3895 }
3896
3897 /**
3898  * Interrupt handler triggered by NIC  for handling
3899  * specific interrupt.
3900  *
3901  * @param handle
3902  *  Pointer to interrupt handle.
3903  * @param param
3904  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3905  *
3906  * @return
3907  *  void
3908  */
3909 static void
3910 ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
3911                             void *param)
3912 {
3913         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3914
3915         ixgbe_dev_interrupt_get_status(dev);
3916         ixgbe_dev_interrupt_action(dev, handle);
3917 }
3918
3919 static int
3920 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3921 {
3922         struct ixgbe_hw *hw;
3923
3924         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925         return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3926 }
3927
3928 static int
3929 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3930 {
3931         struct ixgbe_hw *hw;
3932
3933         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3934         return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
3935 }
3936
3937 static int
3938 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3939 {
3940         struct ixgbe_hw *hw;
3941         uint32_t mflcn_reg;
3942         uint32_t fccfg_reg;
3943         int rx_pause;
3944         int tx_pause;
3945
3946         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3947
3948         fc_conf->pause_time = hw->fc.pause_time;
3949         fc_conf->high_water = hw->fc.high_water[0];
3950         fc_conf->low_water = hw->fc.low_water[0];
3951         fc_conf->send_xon = hw->fc.send_xon;
3952         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3953
3954         /*
3955          * Return rx_pause status according to actual setting of
3956          * MFLCN register.
3957          */
3958         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3959         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3960                 rx_pause = 1;
3961         else
3962                 rx_pause = 0;
3963
3964         /*
3965          * Return tx_pause status according to actual setting of
3966          * FCCFG register.
3967          */
3968         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3969         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3970                 tx_pause = 1;
3971         else
3972                 tx_pause = 0;
3973
3974         if (rx_pause && tx_pause)
3975                 fc_conf->mode = RTE_FC_FULL;
3976         else if (rx_pause)
3977                 fc_conf->mode = RTE_FC_RX_PAUSE;
3978         else if (tx_pause)
3979                 fc_conf->mode = RTE_FC_TX_PAUSE;
3980         else
3981                 fc_conf->mode = RTE_FC_NONE;
3982
3983         return 0;
3984 }
3985
3986 static int
3987 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3988 {
3989         struct ixgbe_hw *hw;
3990         int err;
3991         uint32_t rx_buf_size;
3992         uint32_t max_high_water;
3993         uint32_t mflcn;
3994         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3995                 ixgbe_fc_none,
3996                 ixgbe_fc_rx_pause,
3997                 ixgbe_fc_tx_pause,
3998                 ixgbe_fc_full
3999         };
4000
4001         PMD_INIT_FUNC_TRACE();
4002
4003         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4004         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4005         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4006
4007         /*
4008          * At least reserve one Ethernet frame for watermark
4009          * high_water/low_water in kilo bytes for ixgbe
4010          */
4011         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4012         if ((fc_conf->high_water > max_high_water) ||
4013                 (fc_conf->high_water < fc_conf->low_water)) {
4014                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4015                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4016                 return -EINVAL;
4017         }
4018
4019         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4020         hw->fc.pause_time     = fc_conf->pause_time;
4021         hw->fc.high_water[0]  = fc_conf->high_water;
4022         hw->fc.low_water[0]   = fc_conf->low_water;
4023         hw->fc.send_xon       = fc_conf->send_xon;
4024         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4025
4026         err = ixgbe_fc_enable(hw);
4027
4028         /* Not negotiated is not an error case */
4029         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4030
4031                 /* check if we want to forward MAC frames - driver doesn't have native
4032                  * capability to do that, so we'll write the registers ourselves */
4033
4034                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4035
4036                 /* set or clear MFLCN.PMCF bit depending on configuration */
4037                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4038                         mflcn |= IXGBE_MFLCN_PMCF;
4039                 else
4040                         mflcn &= ~IXGBE_MFLCN_PMCF;
4041
4042                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4043                 IXGBE_WRITE_FLUSH(hw);
4044
4045                 return 0;
4046         }
4047
4048         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4049         return -EIO;
4050 }
4051
4052 /**
4053  *  ixgbe_pfc_enable_generic - Enable flow control
4054  *  @hw: pointer to hardware structure
4055  *  @tc_num: traffic class number
4056  *  Enable flow control according to the current settings.
4057  */
4058 static int
4059 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4060 {
4061         int ret_val = 0;
4062         uint32_t mflcn_reg, fccfg_reg;
4063         uint32_t reg;
4064         uint32_t fcrtl, fcrth;
4065         uint8_t i;
4066         uint8_t nb_rx_en;
4067
4068         /* Validate the water mark configuration */
4069         if (!hw->fc.pause_time) {
4070                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4071                 goto out;
4072         }
4073
4074         /* Low water mark of zero causes XOFF floods */
4075         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4076                  /* High/Low water can not be 0 */
4077                 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4078                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4079                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4080                         goto out;
4081                 }
4082
4083                 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4084                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4085                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4086                         goto out;
4087                 }
4088         }
4089         /* Negotiate the fc mode to use */
4090         ixgbe_fc_autoneg(hw);
4091
4092         /* Disable any previous flow control settings */
4093         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4094         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4095
4096         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4097         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4098
4099         switch (hw->fc.current_mode) {
4100         case ixgbe_fc_none:
4101                 /*
4102                  * If the count of enabled RX Priority Flow control >1,
4103                  * and the TX pause can not be disabled
4104                  */
4105                 nb_rx_en = 0;
4106                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4107                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4108                         if (reg & IXGBE_FCRTH_FCEN)
4109                                 nb_rx_en++;
4110                 }
4111                 if (nb_rx_en > 1)
4112                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4113                 break;
4114         case ixgbe_fc_rx_pause:
4115                 /*
4116                  * Rx Flow control is enabled and Tx Flow control is
4117                  * disabled by software override. Since there really
4118                  * isn't a way to advertise that we are capable of RX
4119                  * Pause ONLY, we will advertise that we support both
4120                  * symmetric and asymmetric Rx PAUSE.  Later, we will
4121                  * disable the adapter's ability to send PAUSE frames.
4122                  */
4123                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4124                 /*
4125                  * If the count of enabled RX Priority Flow control >1,
4126                  * and the TX pause can not be disabled
4127                  */
4128                 nb_rx_en = 0;
4129                 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4130                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4131                         if (reg & IXGBE_FCRTH_FCEN)
4132                                 nb_rx_en++;
4133                 }
4134                 if (nb_rx_en > 1)
4135                         fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4136                 break;
4137         case ixgbe_fc_tx_pause:
4138                 /*
4139                  * Tx Flow control is enabled, and Rx Flow control is
4140                  * disabled by software override.
4141                  */
4142                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4143                 break;
4144         case ixgbe_fc_full:
4145                 /* Flow control (both Rx and Tx) is enabled by SW override. */
4146                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4147                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4148                 break;
4149         default:
4150                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4151                 ret_val = IXGBE_ERR_CONFIG;
4152                 goto out;
4153         }
4154
4155         /* Set 802.3x based flow control settings. */
4156         mflcn_reg |= IXGBE_MFLCN_DPF;
4157         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4158         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4159
4160         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4161         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4162                 hw->fc.high_water[tc_num]) {
4163                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4164                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4165                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4166         } else {
4167                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4168                 /*
4169                  * In order to prevent Tx hangs when the internal Tx
4170                  * switch is enabled we must set the high water mark
4171                  * to the maximum FCRTH value.  This allows the Tx
4172                  * switch to function even under heavy Rx workloads.
4173                  */
4174                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4175         }
4176         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4177
4178         /* Configure pause time (2 TCs per register) */
4179         reg = hw->fc.pause_time * 0x00010001;
4180         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4181                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4182
4183         /* Configure flow control refresh threshold value */
4184         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4185
4186 out:
4187         return ret_val;
4188 }
4189
4190 static int
4191 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4192 {
4193         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4194         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4195
4196         if (hw->mac.type != ixgbe_mac_82598EB) {
4197                 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4198         }
4199         return ret_val;
4200 }
4201
4202 static int
4203 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4204 {
4205         int err;
4206         uint32_t rx_buf_size;
4207         uint32_t max_high_water;
4208         uint8_t tc_num;
4209         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4210         struct ixgbe_hw *hw =
4211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4212         struct ixgbe_dcb_config *dcb_config =
4213                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4214
4215         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4216                 ixgbe_fc_none,
4217                 ixgbe_fc_rx_pause,
4218                 ixgbe_fc_tx_pause,
4219                 ixgbe_fc_full
4220         };
4221
4222         PMD_INIT_FUNC_TRACE();
4223
4224         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4225         tc_num = map[pfc_conf->priority];
4226         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4227         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4228         /*
4229          * At least reserve one Ethernet frame for watermark
4230          * high_water/low_water in kilo bytes for ixgbe
4231          */
4232         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4233         if ((pfc_conf->fc.high_water > max_high_water) ||
4234             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4235                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4236                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4237                 return -EINVAL;
4238         }
4239
4240         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4241         hw->fc.pause_time = pfc_conf->fc.pause_time;
4242         hw->fc.send_xon = pfc_conf->fc.send_xon;
4243         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
4244         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4245
4246         err = ixgbe_dcb_pfc_enable(dev, tc_num);
4247
4248         /* Not negotiated is not an error case */
4249         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4250                 return 0;
4251
4252         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4253         return -EIO;
4254 }
4255
4256 static int
4257 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4258                           struct rte_eth_rss_reta_entry64 *reta_conf,
4259                           uint16_t reta_size)
4260 {
4261         uint16_t i, sp_reta_size;
4262         uint8_t j, mask;
4263         uint32_t reta, r;
4264         uint16_t idx, shift;
4265         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4266         uint32_t reta_reg;
4267
4268         PMD_INIT_FUNC_TRACE();
4269
4270         if (!ixgbe_rss_update_sp(hw->mac.type)) {
4271                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4272                         "NIC.");
4273                 return -ENOTSUP;
4274         }
4275
4276         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4277         if (reta_size != sp_reta_size) {
4278                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4279                         "(%d) doesn't match the number hardware can supported "
4280                         "(%d)\n", reta_size, sp_reta_size);
4281                 return -EINVAL;
4282         }
4283
4284         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4285                 idx = i / RTE_RETA_GROUP_SIZE;
4286                 shift = i % RTE_RETA_GROUP_SIZE;
4287                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4288                                                 IXGBE_4_BIT_MASK);
4289                 if (!mask)
4290                         continue;
4291                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4292                 if (mask == IXGBE_4_BIT_MASK)
4293                         r = 0;
4294                 else
4295                         r = IXGBE_READ_REG(hw, reta_reg);
4296                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4297                         if (mask & (0x1 << j))
4298                                 reta |= reta_conf[idx].reta[shift + j] <<
4299                                                         (CHAR_BIT * j);
4300                         else
4301                                 reta |= r & (IXGBE_8_BIT_MASK <<
4302                                                 (CHAR_BIT * j));
4303                 }
4304                 IXGBE_WRITE_REG(hw, reta_reg, reta);
4305         }
4306
4307         return 0;
4308 }
4309
4310 static int
4311 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4312                          struct rte_eth_rss_reta_entry64 *reta_conf,
4313                          uint16_t reta_size)
4314 {
4315         uint16_t i, sp_reta_size;
4316         uint8_t j, mask;
4317         uint32_t reta;
4318         uint16_t idx, shift;
4319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4320         uint32_t reta_reg;
4321
4322         PMD_INIT_FUNC_TRACE();
4323         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4324         if (reta_size != sp_reta_size) {
4325                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4326                         "(%d) doesn't match the number hardware can supported "
4327                         "(%d)\n", reta_size, sp_reta_size);
4328                 return -EINVAL;
4329         }
4330
4331         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4332                 idx = i / RTE_RETA_GROUP_SIZE;
4333                 shift = i % RTE_RETA_GROUP_SIZE;
4334                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4335                                                 IXGBE_4_BIT_MASK);
4336                 if (!mask)
4337                         continue;
4338
4339                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4340                 reta = IXGBE_READ_REG(hw, reta_reg);
4341                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4342                         if (mask & (0x1 << j))
4343                                 reta_conf[idx].reta[shift + j] =
4344                                         ((reta >> (CHAR_BIT * j)) &
4345                                                 IXGBE_8_BIT_MASK);
4346                 }
4347         }
4348
4349         return 0;
4350 }
4351
4352 static void
4353 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4354                                 uint32_t index, uint32_t pool)
4355 {
4356         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357         uint32_t enable_addr = 1;
4358
4359         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
4360 }
4361
4362 static void
4363 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4364 {
4365         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366
4367         ixgbe_clear_rar(hw, index);
4368 }
4369
4370 static void
4371 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4372 {
4373         ixgbe_remove_rar(dev, 0);
4374
4375         ixgbe_add_rar(dev, addr, 0, 0);
4376 }
4377
4378 static int
4379 is_ixgbe_pmd(const char *driver_name)
4380 {
4381         if (!strstr(driver_name, "ixgbe"))
4382                 return -ENOTSUP;
4383
4384         if (strstr(driver_name, "ixgbe_vf"))
4385                 return -ENOTSUP;
4386
4387         return 0;
4388 }
4389
4390 int
4391 rte_pmd_ixgbe_set_vf_mac_addr(uint8_t port, uint16_t vf,
4392                 struct ether_addr *mac_addr)
4393 {
4394         struct ixgbe_hw *hw;
4395         struct ixgbe_vf_info *vfinfo;
4396         int rar_entry;
4397         uint8_t *new_mac = (uint8_t *)(mac_addr);
4398         struct rte_eth_dev *dev;
4399         struct rte_eth_dev_info dev_info;
4400
4401         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4402
4403         dev = &rte_eth_devices[port];
4404         rte_eth_dev_info_get(port, &dev_info);
4405
4406         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4407                 return -ENOTSUP;
4408
4409         if (vf >= dev_info.max_vfs)
4410                 return -EINVAL;
4411
4412         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4413         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4414         rar_entry = hw->mac.num_rar_entries - (vf + 1);
4415
4416         if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
4417                 rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac,
4418                                 ETHER_ADDR_LEN);
4419                 return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf,
4420                                 IXGBE_RAH_AV);
4421         }
4422         return -EINVAL;
4423 }
4424
4425 static int
4426 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4427 {
4428         uint32_t hlreg0;
4429         uint32_t maxfrs;
4430         struct ixgbe_hw *hw;
4431         struct rte_eth_dev_info dev_info;
4432         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4433
4434         ixgbe_dev_info_get(dev, &dev_info);
4435
4436         /* check that mtu is within the allowed range */
4437         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4438                 return -EINVAL;
4439
4440         /* refuse mtu that requires the support of scattered packets when this
4441          * feature has not been enabled before.
4442          */
4443         if (!dev->data->scattered_rx &&
4444             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4445              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4446                 return -EINVAL;
4447
4448         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4449         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4450
4451         /* switch to jumbo mode if needed */
4452         if (frame_size > ETHER_MAX_LEN) {
4453                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4454                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4455         } else {
4456                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4457                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4458         }
4459         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4460
4461         /* update max frame size */
4462         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4463
4464         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4465         maxfrs &= 0x0000FFFF;
4466         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4467         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4468
4469         return 0;
4470 }
4471
4472 /*
4473  * Virtual Function operations
4474  */
4475 static void
4476 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4477 {
4478         PMD_INIT_FUNC_TRACE();
4479
4480         /* Clear interrupt mask to stop from interrupts being generated */
4481         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4482
4483         IXGBE_WRITE_FLUSH(hw);
4484 }
4485
4486 static void
4487 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4488 {
4489         PMD_INIT_FUNC_TRACE();
4490
4491         /* VF enable interrupt autoclean */
4492         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4493         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4494         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4495
4496         IXGBE_WRITE_FLUSH(hw);
4497 }
4498
4499 static int
4500 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4501 {
4502         struct rte_eth_conf *conf = &dev->data->dev_conf;
4503         struct ixgbe_adapter *adapter =
4504                         (struct ixgbe_adapter *)dev->data->dev_private;
4505
4506         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4507                      dev->data->port_id);
4508
4509         /*
4510          * VF has no ability to enable/disable HW CRC
4511          * Keep the persistent behavior the same as Host PF
4512          */
4513 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4514         if (!conf->rxmode.hw_strip_crc) {
4515                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4516                 conf->rxmode.hw_strip_crc = 1;
4517         }
4518 #else
4519         if (conf->rxmode.hw_strip_crc) {
4520                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4521                 conf->rxmode.hw_strip_crc = 0;
4522         }
4523 #endif
4524
4525         /*
4526          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4527          * allocation or vector Rx preconditions we will reset it.
4528          */
4529         adapter->rx_bulk_alloc_allowed = true;
4530         adapter->rx_vec_allowed = true;
4531
4532         return 0;
4533 }
4534
4535 static int
4536 ixgbevf_dev_start(struct rte_eth_dev *dev)
4537 {
4538         struct ixgbe_hw *hw =
4539                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4540         uint32_t intr_vector = 0;
4541         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4542         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4543
4544         int err, mask = 0;
4545
4546         PMD_INIT_FUNC_TRACE();
4547
4548         hw->mac.ops.reset_hw(hw);
4549         hw->mac.get_link_status = true;
4550
4551         /* negotiate mailbox API version to use with the PF. */
4552         ixgbevf_negotiate_api(hw);
4553
4554         ixgbevf_dev_tx_init(dev);
4555
4556         /* This can fail when allocating mbufs for descriptor rings */
4557         err = ixgbevf_dev_rx_init(dev);
4558         if (err) {
4559                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4560                 ixgbe_dev_clear_queues(dev);
4561                 return err;
4562         }
4563
4564         /* Set vfta */
4565         ixgbevf_set_vfta_all(dev, 1);
4566
4567         /* Set HW strip */
4568         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4569                 ETH_VLAN_EXTEND_MASK;
4570         ixgbevf_vlan_offload_set(dev, mask);
4571
4572         ixgbevf_dev_rxtx_start(dev);
4573
4574         /* check and configure queue intr-vector mapping */
4575         if (dev->data->dev_conf.intr_conf.rxq != 0) {
4576                 intr_vector = dev->data->nb_rx_queues;
4577                 if (rte_intr_efd_enable(intr_handle, intr_vector))
4578                         return -1;
4579         }
4580
4581         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4582                 intr_handle->intr_vec =
4583                         rte_zmalloc("intr_vec",
4584                                     dev->data->nb_rx_queues * sizeof(int), 0);
4585                 if (intr_handle->intr_vec == NULL) {
4586                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4587                                      " intr_vec\n", dev->data->nb_rx_queues);
4588                         return -ENOMEM;
4589                 }
4590         }
4591         ixgbevf_configure_msix(dev);
4592
4593         rte_intr_enable(intr_handle);
4594
4595         /* Re-enable interrupt for VF */
4596         ixgbevf_intr_enable(hw);
4597
4598         return 0;
4599 }
4600
4601 static void
4602 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4603 {
4604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4605         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
4606         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4607
4608         PMD_INIT_FUNC_TRACE();
4609
4610         ixgbevf_intr_disable(hw);
4611
4612         hw->adapter_stopped = 1;
4613         ixgbe_stop_adapter(hw);
4614
4615         /*
4616           * Clear what we set, but we still keep shadow_vfta to
4617           * restore after device starts
4618           */
4619         ixgbevf_set_vfta_all(dev, 0);
4620
4621         /* Clear stored conf */
4622         dev->data->scattered_rx = 0;
4623
4624         ixgbe_dev_clear_queues(dev);
4625
4626         /* Clean datapath event and queue/vec mapping */
4627         rte_intr_efd_disable(intr_handle);
4628         if (intr_handle->intr_vec != NULL) {
4629                 rte_free(intr_handle->intr_vec);
4630                 intr_handle->intr_vec = NULL;
4631         }
4632 }
4633
4634 static void
4635 ixgbevf_dev_close(struct rte_eth_dev *dev)
4636 {
4637         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4638
4639         PMD_INIT_FUNC_TRACE();
4640
4641         ixgbe_reset_hw(hw);
4642
4643         ixgbevf_dev_stop(dev);
4644
4645         ixgbe_dev_free_queues(dev);
4646
4647         /**
4648          * Remove the VF MAC address ro ensure
4649          * that the VF traffic goes to the PF
4650          * after stop, close and detach of the VF
4651          **/
4652         ixgbevf_remove_mac_addr(dev, 0);
4653 }
4654
4655 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4656 {
4657         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4658         struct ixgbe_vfta *shadow_vfta =
4659                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4660         int i = 0, j = 0, vfta = 0, mask = 1;
4661
4662         for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4663                 vfta = shadow_vfta->vfta[i];
4664                 if (vfta) {
4665                         mask = 1;
4666                         for (j = 0; j < 32; j++) {
4667                                 if (vfta & mask)
4668                                         ixgbe_set_vfta(hw, (i<<5)+j, 0,
4669                                                        on, false);
4670                                 mask <<= 1;
4671                         }
4672                 }
4673         }
4674
4675 }
4676
4677 static int
4678 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4679 {
4680         struct ixgbe_hw *hw =
4681                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4682         struct ixgbe_vfta *shadow_vfta =
4683                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4684         uint32_t vid_idx = 0;
4685         uint32_t vid_bit = 0;
4686         int ret = 0;
4687
4688         PMD_INIT_FUNC_TRACE();
4689
4690         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4691         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4692         if (ret) {
4693                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4694                 return ret;
4695         }
4696         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4697         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4698
4699         /* Save what we set and retore it after device reset */
4700         if (on)
4701                 shadow_vfta->vfta[vid_idx] |= vid_bit;
4702         else
4703                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4704
4705         return 0;
4706 }
4707
4708 static void
4709 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4710 {
4711         struct ixgbe_hw *hw =
4712                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4713         uint32_t ctrl;
4714
4715         PMD_INIT_FUNC_TRACE();
4716
4717         if (queue >= hw->mac.max_rx_queues)
4718                 return;
4719
4720         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4721         if (on)
4722                 ctrl |= IXGBE_RXDCTL_VME;
4723         else
4724                 ctrl &= ~IXGBE_RXDCTL_VME;
4725         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4726
4727         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4728 }
4729
4730 static void
4731 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4732 {
4733         struct ixgbe_hw *hw =
4734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4735         uint16_t i;
4736         int on = 0;
4737
4738         /* VF function only support hw strip feature, others are not support */
4739         if (mask & ETH_VLAN_STRIP_MASK) {
4740                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4741
4742                 for (i = 0; i < hw->mac.max_rx_queues; i++)
4743                         ixgbevf_vlan_strip_queue_set(dev, i, on);
4744         }
4745 }
4746
4747 static int
4748 ixgbe_vt_check(struct ixgbe_hw *hw)
4749 {
4750         uint32_t reg_val;
4751
4752         /* if Virtualization Technology is enabled */
4753         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4754         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4755                 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
4756                 return -1;
4757         }
4758
4759         return 0;
4760 }
4761
4762 static uint32_t
4763 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
4764 {
4765         uint32_t vector = 0;
4766
4767         switch (hw->mac.mc_filter_type) {
4768         case 0:   /* use bits [47:36] of the address */
4769                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4770                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4771                 break;
4772         case 1:   /* use bits [46:35] of the address */
4773                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4774                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4775                 break;
4776         case 2:   /* use bits [45:34] of the address */
4777                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4778                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4779                 break;
4780         case 3:   /* use bits [43:32] of the address */
4781                 vector = ((uc_addr->addr_bytes[4]) |
4782                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4783                 break;
4784         default:  /* Invalid mc_filter_type */
4785                 break;
4786         }
4787
4788         /* vector can only be 12-bits or boundary will be exceeded */
4789         vector &= 0xFFF;
4790         return vector;
4791 }
4792
4793 static int
4794 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4795                         uint8_t on)
4796 {
4797         uint32_t vector;
4798         uint32_t uta_idx;
4799         uint32_t reg_val;
4800         uint32_t uta_shift;
4801         uint32_t rc;
4802         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4803         const uint32_t ixgbe_uta_bit_shift = 5;
4804         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4805         const uint32_t bit1 = 0x1;
4806
4807         struct ixgbe_hw *hw =
4808                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4809         struct ixgbe_uta_info *uta_info =
4810                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4811
4812         /* The UTA table only exists on 82599 hardware and newer */
4813         if (hw->mac.type < ixgbe_mac_82599EB)
4814                 return -ENOTSUP;
4815
4816         vector = ixgbe_uta_vector(hw, mac_addr);
4817         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4818         uta_shift = vector & ixgbe_uta_bit_mask;
4819
4820         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4821         if (rc == on)
4822                 return 0;
4823
4824         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4825         if (on) {
4826                 uta_info->uta_in_use++;
4827                 reg_val |= (bit1 << uta_shift);
4828                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4829         } else {
4830                 uta_info->uta_in_use--;
4831                 reg_val &= ~(bit1 << uta_shift);
4832                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4833         }
4834
4835         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4836
4837         if (uta_info->uta_in_use > 0)
4838                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4839                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4840         else
4841                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
4842
4843         return 0;
4844 }
4845
4846 static int
4847 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4848 {
4849         int i;
4850         struct ixgbe_hw *hw =
4851                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4852         struct ixgbe_uta_info *uta_info =
4853                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4854
4855         /* The UTA table only exists on 82599 hardware and newer */
4856         if (hw->mac.type < ixgbe_mac_82599EB)
4857                 return -ENOTSUP;
4858
4859         if (on) {
4860                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4861                         uta_info->uta_shadow[i] = ~0;
4862                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4863                 }
4864         } else {
4865                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4866                         uta_info->uta_shadow[i] = 0;
4867                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4868                 }
4869         }
4870         return 0;
4871
4872 }
4873
4874 uint32_t
4875 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4876 {
4877         uint32_t new_val = orig_val;
4878
4879         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4880                 new_val |= IXGBE_VMOLR_AUPE;
4881         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4882                 new_val |= IXGBE_VMOLR_ROMPE;
4883         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4884                 new_val |= IXGBE_VMOLR_ROPE;
4885         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4886                 new_val |= IXGBE_VMOLR_BAM;
4887         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4888                 new_val |= IXGBE_VMOLR_MPE;
4889
4890         return new_val;
4891 }
4892
4893
4894 int
4895 rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4896 {
4897         struct ixgbe_hw *hw;
4898         struct ixgbe_mac_info *mac;
4899         struct rte_eth_dev *dev;
4900         struct rte_eth_dev_info dev_info;
4901
4902         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4903
4904         dev = &rte_eth_devices[port];
4905         rte_eth_dev_info_get(port, &dev_info);
4906
4907         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4908                 return -ENOTSUP;
4909
4910         if (vf >= dev_info.max_vfs)
4911                 return -EINVAL;
4912
4913         if (on > 1)
4914                 return -EINVAL;
4915
4916         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4917         mac = &hw->mac;
4918
4919         mac->ops.set_vlan_anti_spoofing(hw, on, vf);
4920
4921         return 0;
4922 }
4923
4924 int
4925 rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf, uint8_t on)
4926 {
4927         struct ixgbe_hw *hw;
4928         struct ixgbe_mac_info *mac;
4929         struct rte_eth_dev *dev;
4930         struct rte_eth_dev_info dev_info;
4931
4932         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4933
4934         dev = &rte_eth_devices[port];
4935         rte_eth_dev_info_get(port, &dev_info);
4936
4937         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4938                 return -ENOTSUP;
4939
4940         if (vf >= dev_info.max_vfs)
4941                 return -EINVAL;
4942
4943         if (on > 1)
4944                 return -EINVAL;
4945
4946         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4947         mac = &hw->mac;
4948         mac->ops.set_mac_anti_spoofing(hw, on, vf);
4949
4950         return 0;
4951 }
4952
4953 int
4954 rte_pmd_ixgbe_set_vf_vlan_insert(uint8_t port, uint16_t vf, uint16_t vlan_id)
4955 {
4956         struct ixgbe_hw *hw;
4957         uint32_t ctrl;
4958         struct rte_eth_dev *dev;
4959         struct rte_eth_dev_info dev_info;
4960
4961         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4962
4963         dev = &rte_eth_devices[port];
4964         rte_eth_dev_info_get(port, &dev_info);
4965
4966         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
4967                 return -ENOTSUP;
4968
4969         if (vf >= dev_info.max_vfs)
4970                 return -EINVAL;
4971
4972         if (vlan_id > ETHER_MAX_VLAN_ID)
4973                 return -EINVAL;
4974
4975         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4976         ctrl = IXGBE_READ_REG(hw, IXGBE_VMVIR(vf));
4977         if (vlan_id) {
4978                 ctrl = vlan_id;
4979                 ctrl |= IXGBE_VMVIR_VLANA_DEFAULT;
4980         } else {
4981                 ctrl = 0;
4982         }
4983
4984         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), ctrl);
4985
4986         return 0;
4987 }
4988
4989 int
4990 rte_pmd_ixgbe_set_tx_loopback(uint8_t port, uint8_t on)
4991 {
4992         struct ixgbe_hw *hw;
4993         uint32_t ctrl;
4994         struct rte_eth_dev *dev;
4995         struct rte_eth_dev_info dev_info;
4996
4997         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
4998
4999         dev = &rte_eth_devices[port];
5000         rte_eth_dev_info_get(port, &dev_info);
5001
5002         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5003                 return -ENOTSUP;
5004
5005         if (on > 1)
5006                 return -EINVAL;
5007
5008         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5009         ctrl = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
5010         /* enable or disable VMDQ loopback */
5011         if (on)
5012                 ctrl |= IXGBE_PFDTXGSWC_VT_LBEN;
5013         else
5014                 ctrl &= ~IXGBE_PFDTXGSWC_VT_LBEN;
5015
5016         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, ctrl);
5017
5018         return 0;
5019 }
5020
5021 int
5022 rte_pmd_ixgbe_set_all_queues_drop_en(uint8_t port, uint8_t on)
5023 {
5024         struct ixgbe_hw *hw;
5025         uint32_t reg_value;
5026         int i;
5027         int num_queues = (int)(IXGBE_QDE_IDX_MASK >> IXGBE_QDE_IDX_SHIFT);
5028         struct rte_eth_dev *dev;
5029         struct rte_eth_dev_info dev_info;
5030
5031         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5032
5033         dev = &rte_eth_devices[port];
5034         rte_eth_dev_info_get(port, &dev_info);
5035
5036         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5037                 return -ENOTSUP;
5038
5039         if (on > 1)
5040                 return -EINVAL;
5041
5042         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5043         for (i = 0; i <= num_queues; i++) {
5044                 reg_value = IXGBE_QDE_WRITE |
5045                                 (i << IXGBE_QDE_IDX_SHIFT) |
5046                                 (on & IXGBE_QDE_ENABLE);
5047                 IXGBE_WRITE_REG(hw, IXGBE_QDE, reg_value);
5048         }
5049
5050         return 0;
5051 }
5052
5053 int
5054 rte_pmd_ixgbe_set_vf_split_drop_en(uint8_t port, uint16_t vf, uint8_t on)
5055 {
5056         struct ixgbe_hw *hw;
5057         uint32_t reg_value;
5058         struct rte_eth_dev *dev;
5059         struct rte_eth_dev_info dev_info;
5060
5061         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5062
5063         dev = &rte_eth_devices[port];
5064         rte_eth_dev_info_get(port, &dev_info);
5065
5066         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5067                 return -ENOTSUP;
5068
5069         /* only support VF's 0 to 63 */
5070         if ((vf >= dev_info.max_vfs) || (vf > 63))
5071                 return -EINVAL;
5072
5073         if (on > 1)
5074                 return -EINVAL;
5075
5076         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5077         reg_value = IXGBE_READ_REG(hw, IXGBE_SRRCTL(vf));
5078         if (on)
5079                 reg_value |= IXGBE_SRRCTL_DROP_EN;
5080         else
5081                 reg_value &= ~IXGBE_SRRCTL_DROP_EN;
5082
5083         IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(vf), reg_value);
5084
5085         return 0;
5086 }
5087
5088 int
5089 rte_pmd_ixgbe_set_vf_vlan_stripq(uint8_t port, uint16_t vf, uint8_t on)
5090 {
5091         struct rte_eth_dev *dev;
5092         struct rte_eth_dev_info dev_info;
5093         uint16_t queues_per_pool;
5094         uint32_t q;
5095
5096         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5097
5098         dev = &rte_eth_devices[port];
5099         rte_eth_dev_info_get(port, &dev_info);
5100
5101         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5102                 return -ENOTSUP;
5103
5104         if (vf >= dev_info.max_vfs)
5105                 return -EINVAL;
5106
5107         if (on > 1)
5108                 return -EINVAL;
5109
5110         RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->vlan_strip_queue_set, -ENOTSUP);
5111
5112         /* The PF has 128 queue pairs and in SRIOV configuration
5113          * those queues will be assigned to VF's, so RXDCTL
5114          * registers will be dealing with queues which will be
5115          * assigned to VF's.
5116          * Let's say we have SRIOV configured with 31 VF's then the
5117          * first 124 queues 0-123 will be allocated to VF's and only
5118          * the last 4 queues 123-127 will be assigned to the PF.
5119          */
5120
5121         queues_per_pool = dev_info.vmdq_queue_num / dev_info.max_vmdq_pools;
5122
5123         for (q = 0; q < queues_per_pool; q++)
5124                 (*dev->dev_ops->vlan_strip_queue_set)(dev,
5125                                 q + vf * queues_per_pool, on);
5126         return 0;
5127 }
5128
5129 int
5130 rte_pmd_ixgbe_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mask, uint8_t on)
5131 {
5132         int val = 0;
5133         struct rte_eth_dev *dev;
5134         struct rte_eth_dev_info dev_info;
5135         struct ixgbe_hw *hw;
5136         uint32_t vmolr;
5137
5138         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5139
5140         dev = &rte_eth_devices[port];
5141         rte_eth_dev_info_get(port, &dev_info);
5142
5143         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5144                 return -ENOTSUP;
5145
5146         if (vf >= dev_info.max_vfs)
5147                 return -EINVAL;
5148
5149         if (on > 1)
5150                 return -EINVAL;
5151
5152         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153         vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
5154
5155         if (hw->mac.type == ixgbe_mac_82598EB) {
5156                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
5157                              " on 82599 hardware and newer");
5158                 return -ENOTSUP;
5159         }
5160         if (ixgbe_vt_check(hw) < 0)
5161                 return -ENOTSUP;
5162
5163         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
5164
5165         if (on)
5166                 vmolr |= val;
5167         else
5168                 vmolr &= ~val;
5169
5170         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
5171
5172         return 0;
5173 }
5174
5175 int
5176 rte_pmd_ixgbe_set_vf_rx(uint8_t port, uint16_t vf, uint8_t on)
5177 {
5178         struct rte_eth_dev *dev;
5179         struct rte_eth_dev_info dev_info;
5180         uint32_t reg, addr;
5181         uint32_t val;
5182         const uint8_t bit1 = 0x1;
5183         struct ixgbe_hw *hw;
5184
5185         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5186
5187         dev = &rte_eth_devices[port];
5188         rte_eth_dev_info_get(port, &dev_info);
5189
5190         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5191                 return -ENOTSUP;
5192
5193         if (vf >= dev_info.max_vfs)
5194                 return -EINVAL;
5195
5196         if (on > 1)
5197                 return -EINVAL;
5198
5199         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5200
5201         if (ixgbe_vt_check(hw) < 0)
5202                 return -ENOTSUP;
5203
5204         /* for vf >= 32, set bit in PFVFRE[1], otherwise PFVFRE[0] */
5205         if (vf >= 32) {
5206                 addr = IXGBE_VFRE(1);
5207                 val = bit1 << (vf - 32);
5208         } else {
5209                 addr = IXGBE_VFRE(0);
5210                 val = bit1 << vf;
5211         }
5212
5213         reg = IXGBE_READ_REG(hw, addr);
5214
5215         if (on)
5216                 reg |= val;
5217         else
5218                 reg &= ~val;
5219
5220         IXGBE_WRITE_REG(hw, addr, reg);
5221
5222         return 0;
5223 }
5224
5225 int
5226 rte_pmd_ixgbe_set_vf_tx(uint8_t port, uint16_t vf, uint8_t on)
5227 {
5228         struct rte_eth_dev *dev;
5229         struct rte_eth_dev_info dev_info;
5230         uint32_t reg, addr;
5231         uint32_t val;
5232         const uint8_t bit1 = 0x1;
5233
5234         struct ixgbe_hw *hw;
5235
5236         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5237
5238         dev = &rte_eth_devices[port];
5239         rte_eth_dev_info_get(port, &dev_info);
5240
5241         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5242                 return -ENOTSUP;
5243
5244         if (vf >= dev_info.max_vfs)
5245                 return -EINVAL;
5246
5247         if (on > 1)
5248                 return -EINVAL;
5249
5250         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251         if (ixgbe_vt_check(hw) < 0)
5252                 return -ENOTSUP;
5253
5254         /* for vf >= 32, set bit in PFVFTE[1], otherwise PFVFTE[0] */
5255         if (vf >= 32) {
5256                 addr = IXGBE_VFTE(1);
5257                 val = bit1 << (vf - 32);
5258         } else {
5259                 addr = IXGBE_VFTE(0);
5260                 val = bit1 << vf;
5261         }
5262
5263         reg = IXGBE_READ_REG(hw, addr);
5264
5265         if (on)
5266                 reg |= val;
5267         else
5268                 reg &= ~val;
5269
5270         IXGBE_WRITE_REG(hw, addr, reg);
5271
5272         return 0;
5273 }
5274
5275 int
5276 rte_pmd_ixgbe_set_vf_vlan_filter(uint8_t port, uint16_t vlan,
5277                         uint64_t vf_mask, uint8_t vlan_on)
5278 {
5279         struct rte_eth_dev *dev;
5280         struct rte_eth_dev_info dev_info;
5281         int ret = 0;
5282         uint16_t vf_idx;
5283         struct ixgbe_hw *hw;
5284
5285         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5286
5287         dev = &rte_eth_devices[port];
5288         rte_eth_dev_info_get(port, &dev_info);
5289
5290         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5291                 return -ENOTSUP;
5292
5293         if ((vlan > ETHER_MAX_VLAN_ID) || (vf_mask == 0))
5294                 return -EINVAL;
5295
5296         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5297         if (ixgbe_vt_check(hw) < 0)
5298                 return -ENOTSUP;
5299
5300         for (vf_idx = 0; vf_idx < 64; vf_idx++) {
5301                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
5302                         ret = hw->mac.ops.set_vfta(hw, vlan, vf_idx,
5303                                                    vlan_on, false);
5304                         if (ret < 0)
5305                                 return ret;
5306                 }
5307         }
5308
5309         return ret;
5310 }
5311
5312 int rte_pmd_ixgbe_set_vf_rate_limit(uint8_t port, uint16_t vf,
5313         uint16_t tx_rate, uint64_t q_msk)
5314 {
5315         struct rte_eth_dev *dev;
5316         struct rte_eth_dev_info dev_info;
5317         struct ixgbe_hw *hw;
5318         struct ixgbe_vf_info *vfinfo;
5319         struct rte_eth_link link;
5320         uint8_t  nb_q_per_pool;
5321         uint32_t queue_stride;
5322         uint32_t queue_idx, idx = 0, vf_idx;
5323         uint32_t queue_end;
5324         uint16_t total_rate = 0;
5325         struct rte_pci_device *pci_dev;
5326
5327         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
5328
5329         dev = &rte_eth_devices[port];
5330         rte_eth_dev_info_get(port, &dev_info);
5331         rte_eth_link_get_nowait(port, &link);
5332
5333         if (is_ixgbe_pmd(dev_info.driver_name) != 0)
5334                 return -ENOTSUP;
5335
5336         if (vf >= dev_info.max_vfs)
5337                 return -EINVAL;
5338
5339         if (tx_rate > link.link_speed)
5340                 return -EINVAL;
5341
5342         if (q_msk == 0)
5343                 return 0;
5344
5345         pci_dev = IXGBE_DEV_TO_PCI(dev);
5346         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5347         vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
5348         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
5349         queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
5350         queue_idx = vf * queue_stride;
5351         queue_end = queue_idx + nb_q_per_pool - 1;
5352         if (queue_end >= hw->mac.max_tx_queues)
5353                 return -EINVAL;
5354
5355         if (vfinfo) {
5356                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
5357                         if (vf_idx == vf)
5358                                 continue;
5359                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
5360                                 idx++)
5361                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
5362                 }
5363         } else {
5364                 return -EINVAL;
5365         }
5366
5367         /* Store tx_rate for this vf. */
5368         for (idx = 0; idx < nb_q_per_pool; idx++) {
5369                 if (((uint64_t)0x1 << idx) & q_msk) {
5370                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
5371                                 vfinfo[vf].tx_rate[idx] = tx_rate;
5372                         total_rate += tx_rate;
5373                 }
5374         }
5375
5376         if (total_rate > dev->data->dev_link.link_speed) {
5377                 /* Reset stored TX rate of the VF if it causes exceed
5378                  * link speed.
5379                  */
5380                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
5381                 return -EINVAL;
5382         }
5383
5384         /* Set RTTBCNRC of each queue/pool for vf X  */
5385         for (; queue_idx <= queue_end; queue_idx++) {
5386                 if (0x1 & q_msk)
5387                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
5388                 q_msk = q_msk >> 1;
5389         }
5390
5391         return 0;
5392 }
5393
5394 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
5395 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
5396 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
5397 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
5398 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5399         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5400         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5401
5402 static int
5403 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5404                         struct rte_eth_mirror_conf *mirror_conf,
5405                         uint8_t rule_id, uint8_t on)
5406 {
5407         uint32_t mr_ctl, vlvf;
5408         uint32_t mp_lsb = 0;
5409         uint32_t mv_msb = 0;
5410         uint32_t mv_lsb = 0;
5411         uint32_t mp_msb = 0;
5412         uint8_t i = 0;
5413         int reg_index = 0;
5414         uint64_t vlan_mask = 0;
5415
5416         const uint8_t pool_mask_offset = 32;
5417         const uint8_t vlan_mask_offset = 32;
5418         const uint8_t dst_pool_offset = 8;
5419         const uint8_t rule_mr_offset  = 4;
5420         const uint8_t mirror_rule_mask = 0x0F;
5421
5422         struct ixgbe_mirror_info *mr_info =
5423                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5424         struct ixgbe_hw *hw =
5425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5426         uint8_t mirror_type = 0;
5427
5428         if (ixgbe_vt_check(hw) < 0)
5429                 return -ENOTSUP;
5430
5431         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5432                 return -EINVAL;
5433
5434         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5435                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5436                         mirror_conf->rule_type);
5437                 return -EINVAL;
5438         }
5439
5440         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5441                 mirror_type |= IXGBE_MRCTL_VLME;
5442                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
5443                 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5444                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5445                                 /* search vlan id related pool vlan filter index */
5446                                 reg_index = ixgbe_find_vlvf_slot(hw,
5447                                                  mirror_conf->vlan.vlan_id[i],
5448                                                  false);
5449                                 if (reg_index < 0)
5450                                         return -EINVAL;
5451                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
5452                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
5453                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5454                                       mirror_conf->vlan.vlan_id[i]))
5455                                         vlan_mask |= (1ULL << reg_index);
5456                                 else
5457                                         return -EINVAL;
5458                         }
5459                 }
5460
5461                 if (on) {
5462                         mv_lsb = vlan_mask & 0xFFFFFFFF;
5463                         mv_msb = vlan_mask >> vlan_mask_offset;
5464
5465                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
5466                                                 mirror_conf->vlan.vlan_mask;
5467                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5468                                 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5469                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5470                                                 mirror_conf->vlan.vlan_id[i];
5471                         }
5472                 } else {
5473                         mv_lsb = 0;
5474                         mv_msb = 0;
5475                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5476                         for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5477                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5478                 }
5479         }
5480
5481         /*
5482          * if enable pool mirror, write related pool mask register,if disable
5483          * pool mirror, clear PFMRVM register
5484          */
5485         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5486                 mirror_type |= IXGBE_MRCTL_VPME;
5487                 if (on) {
5488                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5489                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5490                         mr_info->mr_conf[rule_id].pool_mask =
5491                                         mirror_conf->pool_mask;
5492
5493                 } else {
5494                         mp_lsb = 0;
5495                         mp_msb = 0;
5496                         mr_info->mr_conf[rule_id].pool_mask = 0;
5497                 }
5498         }
5499         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5500                 mirror_type |= IXGBE_MRCTL_UPME;
5501         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5502                 mirror_type |= IXGBE_MRCTL_DPME;
5503
5504         /* read  mirror control register and recalculate it */
5505         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5506
5507         if (on) {
5508                 mr_ctl |= mirror_type;
5509                 mr_ctl &= mirror_rule_mask;
5510                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5511         } else
5512                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5513
5514         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5515         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5516
5517         /* write mirrror control  register */
5518         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5519
5520         /* write pool mirrror control  register */
5521         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5522                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5523                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5524                                 mp_msb);
5525         }
5526         /* write VLAN mirrror control  register */
5527         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5528                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5529                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5530                                 mv_msb);
5531         }
5532
5533         return 0;
5534 }
5535
5536 static int
5537 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5538 {
5539         int mr_ctl = 0;
5540         uint32_t lsb_val = 0;
5541         uint32_t msb_val = 0;
5542         const uint8_t rule_mr_offset = 4;
5543
5544         struct ixgbe_hw *hw =
5545                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5546         struct ixgbe_mirror_info *mr_info =
5547                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5548
5549         if (ixgbe_vt_check(hw) < 0)
5550                 return -ENOTSUP;
5551
5552         memset(&mr_info->mr_conf[rule_id], 0,
5553                 sizeof(struct rte_eth_mirror_conf));
5554
5555         /* clear PFVMCTL register */
5556         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5557
5558         /* clear pool mask register */
5559         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5560         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5561
5562         /* clear vlan mask register */
5563         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5564         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5565
5566         return 0;
5567 }
5568
5569 static int
5570 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5571 {
5572         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5573         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5574         uint32_t mask;
5575         struct ixgbe_hw *hw =
5576                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5577
5578         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5579         mask |= (1 << IXGBE_MISC_VEC_ID);
5580         RTE_SET_USED(queue_id);
5581         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5582
5583         rte_intr_enable(intr_handle);
5584
5585         return 0;
5586 }
5587
5588 static int
5589 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5590 {
5591         uint32_t mask;
5592         struct ixgbe_hw *hw =
5593                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5594
5595         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5596         mask &= ~(1 << IXGBE_MISC_VEC_ID);
5597         RTE_SET_USED(queue_id);
5598         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5599
5600         return 0;
5601 }
5602
5603 static int
5604 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5605 {
5606         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5607         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5608         uint32_t mask;
5609         struct ixgbe_hw *hw =
5610                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5611         struct ixgbe_interrupt *intr =
5612                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5613
5614         if (queue_id < 16) {
5615                 ixgbe_disable_intr(hw);
5616                 intr->mask |= (1 << queue_id);
5617                 ixgbe_enable_intr(dev);
5618         } else if (queue_id < 32) {
5619                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5620                 mask &= (1 << queue_id);
5621                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5622         } else if (queue_id < 64) {
5623                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5624                 mask &= (1 << (queue_id - 32));
5625                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5626         }
5627         rte_intr_enable(intr_handle);
5628
5629         return 0;
5630 }
5631
5632 static int
5633 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5634 {
5635         uint32_t mask;
5636         struct ixgbe_hw *hw =
5637                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5638         struct ixgbe_interrupt *intr =
5639                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5640
5641         if (queue_id < 16) {
5642                 ixgbe_disable_intr(hw);
5643                 intr->mask &= ~(1 << queue_id);
5644                 ixgbe_enable_intr(dev);
5645         } else if (queue_id < 32) {
5646                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5647                 mask &= ~(1 << queue_id);
5648                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5649         } else if (queue_id < 64) {
5650                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5651                 mask &= ~(1 << (queue_id - 32));
5652                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5653         }
5654
5655         return 0;
5656 }
5657
5658 static void
5659 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5660                      uint8_t queue, uint8_t msix_vector)
5661 {
5662         uint32_t tmp, idx;
5663
5664         if (direction == -1) {
5665                 /* other causes */
5666                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5667                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5668                 tmp &= ~0xFF;
5669                 tmp |= msix_vector;
5670                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5671         } else {
5672                 /* rx or tx cause */
5673                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5674                 idx = ((16 * (queue & 1)) + (8 * direction));
5675                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5676                 tmp &= ~(0xFF << idx);
5677                 tmp |= (msix_vector << idx);
5678                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5679         }
5680 }
5681
5682 /**
5683  * set the IVAR registers, mapping interrupt causes to vectors
5684  * @param hw
5685  *  pointer to ixgbe_hw struct
5686  * @direction
5687  *  0 for Rx, 1 for Tx, -1 for other causes
5688  * @queue
5689  *  queue to map the corresponding interrupt to
5690  * @msix_vector
5691  *  the vector to map to the corresponding queue
5692  */
5693 static void
5694 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5695                    uint8_t queue, uint8_t msix_vector)
5696 {
5697         uint32_t tmp, idx;
5698
5699         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5700         if (hw->mac.type == ixgbe_mac_82598EB) {
5701                 if (direction == -1)
5702                         direction = 0;
5703                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5704                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5705                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5706                 tmp |= (msix_vector << (8 * (queue & 0x3)));
5707                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5708         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5709                         (hw->mac.type == ixgbe_mac_X540)) {
5710                 if (direction == -1) {
5711                         /* other causes */
5712                         idx = ((queue & 1) * 8);
5713                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5714                         tmp &= ~(0xFF << idx);
5715                         tmp |= (msix_vector << idx);
5716                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5717                 } else {
5718                         /* rx or tx causes */
5719                         idx = ((16 * (queue & 1)) + (8 * direction));
5720                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5721                         tmp &= ~(0xFF << idx);
5722                         tmp |= (msix_vector << idx);
5723                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5724                 }
5725         }
5726 }
5727
5728 static void
5729 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5730 {
5731         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5732         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5733         struct ixgbe_hw *hw =
5734                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735         uint32_t q_idx;
5736         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5737
5738         /* Configure VF other cause ivar */
5739         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5740
5741         /* won't configure msix register if no mapping is done
5742          * between intr vector and event fd.
5743          */
5744         if (!rte_intr_dp_is_en(intr_handle))
5745                 return;
5746
5747         /* Configure all RX queues of VF */
5748         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5749                 /* Force all queue use vector 0,
5750                  * as IXGBE_VF_MAXMSIVECOTR = 1
5751                  */
5752                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5753                 intr_handle->intr_vec[q_idx] = vector_idx;
5754         }
5755 }
5756
5757 /**
5758  * Sets up the hardware to properly generate MSI-X interrupts
5759  * @hw
5760  *  board private structure
5761  */
5762 static void
5763 ixgbe_configure_msix(struct rte_eth_dev *dev)
5764 {
5765         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
5766         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5767         struct ixgbe_hw *hw =
5768                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5769         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5770         uint32_t vec = IXGBE_MISC_VEC_ID;
5771         uint32_t mask;
5772         uint32_t gpie;
5773
5774         /* won't configure msix register if no mapping is done
5775          * between intr vector and event fd
5776          */
5777         if (!rte_intr_dp_is_en(intr_handle))
5778                 return;
5779
5780         if (rte_intr_allow_others(intr_handle))
5781                 vec = base = IXGBE_RX_VEC_START;
5782
5783         /* setup GPIE for MSI-x mode */
5784         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5785         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5786                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5787         /* auto clearing and auto setting corresponding bits in EIMS
5788          * when MSI-X interrupt is triggered
5789          */
5790         if (hw->mac.type == ixgbe_mac_82598EB) {
5791                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5792         } else {
5793                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5794                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5795         }
5796         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5797
5798         /* Populate the IVAR table and set the ITR values to the
5799          * corresponding register.
5800          */
5801         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5802              queue_id++) {
5803                 /* by default, 1:1 mapping */
5804                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5805                 intr_handle->intr_vec[queue_id] = vec;
5806                 if (vec < base + intr_handle->nb_efd - 1)
5807                         vec++;
5808         }
5809
5810         switch (hw->mac.type) {
5811         case ixgbe_mac_82598EB:
5812                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5813                                    IXGBE_MISC_VEC_ID);
5814                 break;
5815         case ixgbe_mac_82599EB:
5816         case ixgbe_mac_X540:
5817                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5818                 break;
5819         default:
5820                 break;
5821         }
5822         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5823                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5824
5825         /* set up to autoclear timer, and the vectors */
5826         mask = IXGBE_EIMS_ENABLE_MASK;
5827         mask &= ~(IXGBE_EIMS_OTHER |
5828                   IXGBE_EIMS_MAILBOX |
5829                   IXGBE_EIMS_LSC);
5830
5831         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5832 }
5833
5834 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5835         uint16_t queue_idx, uint16_t tx_rate)
5836 {
5837         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5838         uint32_t rf_dec, rf_int;
5839         uint32_t bcnrc_val;
5840         uint16_t link_speed = dev->data->dev_link.link_speed;
5841
5842         if (queue_idx >= hw->mac.max_tx_queues)
5843                 return -EINVAL;
5844
5845         if (tx_rate != 0) {
5846                 /* Calculate the rate factor values to set */
5847                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5848                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5849                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5850
5851                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5852                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5853                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5854                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5855         } else {
5856                 bcnrc_val = 0;
5857         }
5858
5859         /*
5860          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5861          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5862          * set as 0x4.
5863          */
5864         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5865                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5866                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
5867                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5868                         IXGBE_MMW_SIZE_JUMBO_FRAME);
5869         else
5870                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5871                         IXGBE_MMW_SIZE_DEFAULT);
5872
5873         /* Set RTTBCNRC of queue X */
5874         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5875         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5876         IXGBE_WRITE_FLUSH(hw);
5877
5878         return 0;
5879 }
5880
5881 static void
5882 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5883                      __attribute__((unused)) uint32_t index,
5884                      __attribute__((unused)) uint32_t pool)
5885 {
5886         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5887         int diag;
5888
5889         /*
5890          * On a 82599 VF, adding again the same MAC addr is not an idempotent
5891          * operation. Trap this case to avoid exhausting the [very limited]
5892          * set of PF resources used to store VF MAC addresses.
5893          */
5894         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5895                 return;
5896         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5897         if (diag == 0)
5898                 return;
5899         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
5900 }
5901
5902 static void
5903 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5904 {
5905         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5906         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5907         struct ether_addr *mac_addr;
5908         uint32_t i;
5909         int diag;
5910
5911         /*
5912          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5913          * not support the deletion of a given MAC address.
5914          * Instead, it imposes to delete all MAC addresses, then to add again
5915          * all MAC addresses with the exception of the one to be deleted.
5916          */
5917         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5918
5919         /*
5920          * Add again all MAC addresses, with the exception of the deleted one
5921          * and of the permanent MAC address.
5922          */
5923         for (i = 0, mac_addr = dev->data->mac_addrs;
5924              i < hw->mac.num_rar_entries; i++, mac_addr++) {
5925                 /* Skip the deleted MAC address */
5926                 if (i == index)
5927                         continue;
5928                 /* Skip NULL MAC addresses */
5929                 if (is_zero_ether_addr(mac_addr))
5930                         continue;
5931                 /* Skip the permanent MAC address */
5932                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5933                         continue;
5934                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5935                 if (diag != 0)
5936                         PMD_DRV_LOG(ERR,
5937                                     "Adding again MAC address "
5938                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
5939                                     "diag=%d",
5940                                     mac_addr->addr_bytes[0],
5941                                     mac_addr->addr_bytes[1],
5942                                     mac_addr->addr_bytes[2],
5943                                     mac_addr->addr_bytes[3],
5944                                     mac_addr->addr_bytes[4],
5945                                     mac_addr->addr_bytes[5],
5946                                     diag);
5947         }
5948 }
5949
5950 static void
5951 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5952 {
5953         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5954
5955         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5956 }
5957
5958 #define MAC_TYPE_FILTER_SUP(type)    do {\
5959         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
5960                 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
5961                 (type) != ixgbe_mac_X550EM_a)\
5962                 return -ENOTSUP;\
5963 } while (0)
5964
5965 int
5966 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5967                         struct rte_eth_syn_filter *filter,
5968                         bool add)
5969 {
5970         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5971         struct ixgbe_filter_info *filter_info =
5972                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5973         uint32_t syn_info;
5974         uint32_t synqf;
5975
5976         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5977                 return -EINVAL;
5978
5979         syn_info = filter_info->syn_info;
5980
5981         if (add) {
5982                 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5983                         return -EINVAL;
5984                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5985                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5986
5987                 if (filter->hig_pri)
5988                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
5989                 else
5990                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5991         } else {
5992                 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5993                 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5994                         return -ENOENT;
5995                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5996         }
5997
5998         filter_info->syn_info = synqf;
5999         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
6000         IXGBE_WRITE_FLUSH(hw);
6001         return 0;
6002 }
6003
6004 static int
6005 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
6006                         struct rte_eth_syn_filter *filter)
6007 {
6008         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6009         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
6010
6011         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
6012                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
6013                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
6014                 return 0;
6015         }
6016         return -ENOENT;
6017 }
6018
6019 static int
6020 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
6021                         enum rte_filter_op filter_op,
6022                         void *arg)
6023 {
6024         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6025         int ret;
6026
6027         MAC_TYPE_FILTER_SUP(hw->mac.type);
6028
6029         if (filter_op == RTE_ETH_FILTER_NOP)
6030                 return 0;
6031
6032         if (arg == NULL) {
6033                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6034                             filter_op);
6035                 return -EINVAL;
6036         }
6037
6038         switch (filter_op) {
6039         case RTE_ETH_FILTER_ADD:
6040                 ret = ixgbe_syn_filter_set(dev,
6041                                 (struct rte_eth_syn_filter *)arg,
6042                                 TRUE);
6043                 break;
6044         case RTE_ETH_FILTER_DELETE:
6045                 ret = ixgbe_syn_filter_set(dev,
6046                                 (struct rte_eth_syn_filter *)arg,
6047                                 FALSE);
6048                 break;
6049         case RTE_ETH_FILTER_GET:
6050                 ret = ixgbe_syn_filter_get(dev,
6051                                 (struct rte_eth_syn_filter *)arg);
6052                 break;
6053         default:
6054                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
6055                 ret = -EINVAL;
6056                 break;
6057         }
6058
6059         return ret;
6060 }
6061
6062
6063 static inline enum ixgbe_5tuple_protocol
6064 convert_protocol_type(uint8_t protocol_value)
6065 {
6066         if (protocol_value == IPPROTO_TCP)
6067                 return IXGBE_FILTER_PROTOCOL_TCP;
6068         else if (protocol_value == IPPROTO_UDP)
6069                 return IXGBE_FILTER_PROTOCOL_UDP;
6070         else if (protocol_value == IPPROTO_SCTP)
6071                 return IXGBE_FILTER_PROTOCOL_SCTP;
6072         else
6073                 return IXGBE_FILTER_PROTOCOL_NONE;
6074 }
6075
6076 /* inject a 5-tuple filter to HW */
6077 static inline void
6078 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6079                            struct ixgbe_5tuple_filter *filter)
6080 {
6081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6082         int i;
6083         uint32_t ftqf, sdpqf;
6084         uint32_t l34timir = 0;
6085         uint8_t mask = 0xff;
6086
6087         i = filter->index;
6088
6089         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6090                                 IXGBE_SDPQF_DSTPORT_SHIFT);
6091         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6092
6093         ftqf = (uint32_t)(filter->filter_info.proto &
6094                 IXGBE_FTQF_PROTOCOL_MASK);
6095         ftqf |= (uint32_t)((filter->filter_info.priority &
6096                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6097         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6098                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6099         if (filter->filter_info.dst_ip_mask == 0)
6100                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6101         if (filter->filter_info.src_port_mask == 0)
6102                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6103         if (filter->filter_info.dst_port_mask == 0)
6104                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6105         if (filter->filter_info.proto_mask == 0)
6106                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6107         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6108         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6109         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6110
6111         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6112         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6113         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6114         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6115
6116         l34timir |= IXGBE_L34T_IMIR_RESERVE;
6117         l34timir |= (uint32_t)(filter->queue <<
6118                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6119         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6120 }
6121
6122 /*
6123  * add a 5tuple filter
6124  *
6125  * @param
6126  * dev: Pointer to struct rte_eth_dev.
6127  * index: the index the filter allocates.
6128  * filter: ponter to the filter that will be added.
6129  * rx_queue: the queue id the filter assigned to.
6130  *
6131  * @return
6132  *    - On success, zero.
6133  *    - On failure, a negative value.
6134  */
6135 static int
6136 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6137                         struct ixgbe_5tuple_filter *filter)
6138 {
6139         struct ixgbe_filter_info *filter_info =
6140                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6141         int i, idx, shift;
6142
6143         /*
6144          * look for an unused 5tuple filter index,
6145          * and insert the filter to list.
6146          */
6147         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6148                 idx = i / (sizeof(uint32_t) * NBBY);
6149                 shift = i % (sizeof(uint32_t) * NBBY);
6150                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6151                         filter_info->fivetuple_mask[idx] |= 1 << shift;
6152                         filter->index = i;
6153                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6154                                           filter,
6155                                           entries);
6156                         break;
6157                 }
6158         }
6159         if (i >= IXGBE_MAX_FTQF_FILTERS) {
6160                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6161                 return -ENOSYS;
6162         }
6163
6164         ixgbe_inject_5tuple_filter(dev, filter);
6165
6166         return 0;
6167 }
6168
6169 /*
6170  * remove a 5tuple filter
6171  *
6172  * @param
6173  * dev: Pointer to struct rte_eth_dev.
6174  * filter: the pointer of the filter will be removed.
6175  */
6176 static void
6177 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6178                         struct ixgbe_5tuple_filter *filter)
6179 {
6180         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6181         struct ixgbe_filter_info *filter_info =
6182                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6183         uint16_t index = filter->index;
6184
6185         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6186                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6187         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6188         rte_free(filter);
6189
6190         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6191         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6192         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6193         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6194         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6195 }
6196
6197 static int
6198 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6199 {
6200         struct ixgbe_hw *hw;
6201         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6202
6203         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6204
6205         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6206                 return -EINVAL;
6207
6208         /* refuse mtu that requires the support of scattered packets when this
6209          * feature has not been enabled before.
6210          */
6211         if (!dev->data->scattered_rx &&
6212             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6213              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6214                 return -EINVAL;
6215
6216         /*
6217          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6218          * request of the version 2.0 of the mailbox API.
6219          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6220          * of the mailbox API.
6221          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6222          * prior to 3.11.33 which contains the following change:
6223          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6224          */
6225         ixgbevf_rlpml_set_vf(hw, max_frame);
6226
6227         /* update max frame size */
6228         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6229         return 0;
6230 }
6231
6232 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
6233         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
6234                 return -ENOTSUP;\
6235 } while (0)
6236
6237 static inline struct ixgbe_5tuple_filter *
6238 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6239                         struct ixgbe_5tuple_filter_info *key)
6240 {
6241         struct ixgbe_5tuple_filter *it;
6242
6243         TAILQ_FOREACH(it, filter_list, entries) {
6244                 if (memcmp(key, &it->filter_info,
6245                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6246                         return it;
6247                 }
6248         }
6249         return NULL;
6250 }
6251
6252 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6253 static inline int
6254 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6255                         struct ixgbe_5tuple_filter_info *filter_info)
6256 {
6257         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6258                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6259                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6260                 return -EINVAL;
6261
6262         switch (filter->dst_ip_mask) {
6263         case UINT32_MAX:
6264                 filter_info->dst_ip_mask = 0;
6265                 filter_info->dst_ip = filter->dst_ip;
6266                 break;
6267         case 0:
6268                 filter_info->dst_ip_mask = 1;
6269                 break;
6270         default:
6271                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6272                 return -EINVAL;
6273         }
6274
6275         switch (filter->src_ip_mask) {
6276         case UINT32_MAX:
6277                 filter_info->src_ip_mask = 0;
6278                 filter_info->src_ip = filter->src_ip;
6279                 break;
6280         case 0:
6281                 filter_info->src_ip_mask = 1;
6282                 break;
6283         default:
6284                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6285                 return -EINVAL;
6286         }
6287
6288         switch (filter->dst_port_mask) {
6289         case UINT16_MAX:
6290                 filter_info->dst_port_mask = 0;
6291                 filter_info->dst_port = filter->dst_port;
6292                 break;
6293         case 0:
6294                 filter_info->dst_port_mask = 1;
6295                 break;
6296         default:
6297                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6298                 return -EINVAL;
6299         }
6300
6301         switch (filter->src_port_mask) {
6302         case UINT16_MAX:
6303                 filter_info->src_port_mask = 0;
6304                 filter_info->src_port = filter->src_port;
6305                 break;
6306         case 0:
6307                 filter_info->src_port_mask = 1;
6308                 break;
6309         default:
6310                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6311                 return -EINVAL;
6312         }
6313
6314         switch (filter->proto_mask) {
6315         case UINT8_MAX:
6316                 filter_info->proto_mask = 0;
6317                 filter_info->proto =
6318                         convert_protocol_type(filter->proto);
6319                 break;
6320         case 0:
6321                 filter_info->proto_mask = 1;
6322                 break;
6323         default:
6324                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6325                 return -EINVAL;
6326         }
6327
6328         filter_info->priority = (uint8_t)filter->priority;
6329         return 0;
6330 }
6331
6332 /*
6333  * add or delete a ntuple filter
6334  *
6335  * @param
6336  * dev: Pointer to struct rte_eth_dev.
6337  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6338  * add: if true, add filter, if false, remove filter
6339  *
6340  * @return
6341  *    - On success, zero.
6342  *    - On failure, a negative value.
6343  */
6344 int
6345 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6346                         struct rte_eth_ntuple_filter *ntuple_filter,
6347                         bool add)
6348 {
6349         struct ixgbe_filter_info *filter_info =
6350                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6351         struct ixgbe_5tuple_filter_info filter_5tuple;
6352         struct ixgbe_5tuple_filter *filter;
6353         int ret;
6354
6355         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6356                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6357                 return -EINVAL;
6358         }
6359
6360         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6361         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6362         if (ret < 0)
6363                 return ret;
6364
6365         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6366                                          &filter_5tuple);
6367         if (filter != NULL && add) {
6368                 PMD_DRV_LOG(ERR, "filter exists.");
6369                 return -EEXIST;
6370         }
6371         if (filter == NULL && !add) {
6372                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6373                 return -ENOENT;
6374         }
6375
6376         if (add) {
6377                 filter = rte_zmalloc("ixgbe_5tuple_filter",
6378                                 sizeof(struct ixgbe_5tuple_filter), 0);
6379                 if (filter == NULL)
6380                         return -ENOMEM;
6381                 (void)rte_memcpy(&filter->filter_info,
6382                                  &filter_5tuple,
6383                                  sizeof(struct ixgbe_5tuple_filter_info));
6384                 filter->queue = ntuple_filter->queue;
6385                 ret = ixgbe_add_5tuple_filter(dev, filter);
6386                 if (ret < 0) {
6387                         rte_free(filter);
6388                         return ret;
6389                 }
6390         } else
6391                 ixgbe_remove_5tuple_filter(dev, filter);
6392
6393         return 0;
6394 }
6395
6396 /*
6397  * get a ntuple filter
6398  *
6399  * @param
6400  * dev: Pointer to struct rte_eth_dev.
6401  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6402  *
6403  * @return
6404  *    - On success, zero.
6405  *    - On failure, a negative value.
6406  */
6407 static int
6408 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6409                         struct rte_eth_ntuple_filter *ntuple_filter)
6410 {
6411         struct ixgbe_filter_info *filter_info =
6412                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6413         struct ixgbe_5tuple_filter_info filter_5tuple;
6414         struct ixgbe_5tuple_filter *filter;
6415         int ret;
6416
6417         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6418                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6419                 return -EINVAL;
6420         }
6421
6422         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6423         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6424         if (ret < 0)
6425                 return ret;
6426
6427         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6428                                          &filter_5tuple);
6429         if (filter == NULL) {
6430                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6431                 return -ENOENT;
6432         }
6433         ntuple_filter->queue = filter->queue;
6434         return 0;
6435 }
6436
6437 /*
6438  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6439  * @dev: pointer to rte_eth_dev structure
6440  * @filter_op:operation will be taken.
6441  * @arg: a pointer to specific structure corresponding to the filter_op
6442  *
6443  * @return
6444  *    - On success, zero.
6445  *    - On failure, a negative value.
6446  */
6447 static int
6448 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6449                                 enum rte_filter_op filter_op,
6450                                 void *arg)
6451 {
6452         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6453         int ret;
6454
6455         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6456
6457         if (filter_op == RTE_ETH_FILTER_NOP)
6458                 return 0;
6459
6460         if (arg == NULL) {
6461                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6462                             filter_op);
6463                 return -EINVAL;
6464         }
6465
6466         switch (filter_op) {
6467         case RTE_ETH_FILTER_ADD:
6468                 ret = ixgbe_add_del_ntuple_filter(dev,
6469                         (struct rte_eth_ntuple_filter *)arg,
6470                         TRUE);
6471                 break;
6472         case RTE_ETH_FILTER_DELETE:
6473                 ret = ixgbe_add_del_ntuple_filter(dev,
6474                         (struct rte_eth_ntuple_filter *)arg,
6475                         FALSE);
6476                 break;
6477         case RTE_ETH_FILTER_GET:
6478                 ret = ixgbe_get_ntuple_filter(dev,
6479                         (struct rte_eth_ntuple_filter *)arg);
6480                 break;
6481         default:
6482                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6483                 ret = -EINVAL;
6484                 break;
6485         }
6486         return ret;
6487 }
6488
6489 int
6490 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6491                         struct rte_eth_ethertype_filter *filter,
6492                         bool add)
6493 {
6494         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6495         struct ixgbe_filter_info *filter_info =
6496                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6497         uint32_t etqf = 0;
6498         uint32_t etqs = 0;
6499         int ret;
6500         struct ixgbe_ethertype_filter ethertype_filter;
6501
6502         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6503                 return -EINVAL;
6504
6505         if (filter->ether_type == ETHER_TYPE_IPv4 ||
6506                 filter->ether_type == ETHER_TYPE_IPv6) {
6507                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6508                         " ethertype filter.", filter->ether_type);
6509                 return -EINVAL;
6510         }
6511
6512         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6513                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6514                 return -EINVAL;
6515         }
6516         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6517                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6518                 return -EINVAL;
6519         }
6520
6521         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6522         if (ret >= 0 && add) {
6523                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6524                             filter->ether_type);
6525                 return -EEXIST;
6526         }
6527         if (ret < 0 && !add) {
6528                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6529                             filter->ether_type);
6530                 return -ENOENT;
6531         }
6532
6533         if (add) {
6534                 etqf = IXGBE_ETQF_FILTER_EN;
6535                 etqf |= (uint32_t)filter->ether_type;
6536                 etqs |= (uint32_t)((filter->queue <<
6537                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
6538                                     IXGBE_ETQS_RX_QUEUE);
6539                 etqs |= IXGBE_ETQS_QUEUE_EN;
6540
6541                 ethertype_filter.ethertype = filter->ether_type;
6542                 ethertype_filter.etqf = etqf;
6543                 ethertype_filter.etqs = etqs;
6544                 ethertype_filter.conf = FALSE;
6545                 ret = ixgbe_ethertype_filter_insert(filter_info,
6546                                                     &ethertype_filter);
6547                 if (ret < 0) {
6548                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
6549                         return -ENOSPC;
6550                 }
6551         } else {
6552                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6553                 if (ret < 0)
6554                         return -ENOSYS;
6555         }
6556         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6557         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6558         IXGBE_WRITE_FLUSH(hw);
6559
6560         return 0;
6561 }
6562
6563 static int
6564 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6565                         struct rte_eth_ethertype_filter *filter)
6566 {
6567         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6568         struct ixgbe_filter_info *filter_info =
6569                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6570         uint32_t etqf, etqs;
6571         int ret;
6572
6573         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6574         if (ret < 0) {
6575                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6576                             filter->ether_type);
6577                 return -ENOENT;
6578         }
6579
6580         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6581         if (etqf & IXGBE_ETQF_FILTER_EN) {
6582                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6583                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6584                 filter->flags = 0;
6585                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6586                                IXGBE_ETQS_RX_QUEUE_SHIFT;
6587                 return 0;
6588         }
6589         return -ENOENT;
6590 }
6591
6592 /*
6593  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6594  * @dev: pointer to rte_eth_dev structure
6595  * @filter_op:operation will be taken.
6596  * @arg: a pointer to specific structure corresponding to the filter_op
6597  */
6598 static int
6599 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6600                                 enum rte_filter_op filter_op,
6601                                 void *arg)
6602 {
6603         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6604         int ret;
6605
6606         MAC_TYPE_FILTER_SUP(hw->mac.type);
6607
6608         if (filter_op == RTE_ETH_FILTER_NOP)
6609                 return 0;
6610
6611         if (arg == NULL) {
6612                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6613                             filter_op);
6614                 return -EINVAL;
6615         }
6616
6617         switch (filter_op) {
6618         case RTE_ETH_FILTER_ADD:
6619                 ret = ixgbe_add_del_ethertype_filter(dev,
6620                         (struct rte_eth_ethertype_filter *)arg,
6621                         TRUE);
6622                 break;
6623         case RTE_ETH_FILTER_DELETE:
6624                 ret = ixgbe_add_del_ethertype_filter(dev,
6625                         (struct rte_eth_ethertype_filter *)arg,
6626                         FALSE);
6627                 break;
6628         case RTE_ETH_FILTER_GET:
6629                 ret = ixgbe_get_ethertype_filter(dev,
6630                         (struct rte_eth_ethertype_filter *)arg);
6631                 break;
6632         default:
6633                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6634                 ret = -EINVAL;
6635                 break;
6636         }
6637         return ret;
6638 }
6639
6640 static int
6641 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6642                      enum rte_filter_type filter_type,
6643                      enum rte_filter_op filter_op,
6644                      void *arg)
6645 {
6646         int ret = 0;
6647
6648         switch (filter_type) {
6649         case RTE_ETH_FILTER_NTUPLE:
6650                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6651                 break;
6652         case RTE_ETH_FILTER_ETHERTYPE:
6653                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6654                 break;
6655         case RTE_ETH_FILTER_SYN:
6656                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6657                 break;
6658         case RTE_ETH_FILTER_FDIR:
6659                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6660                 break;
6661         case RTE_ETH_FILTER_L2_TUNNEL:
6662                 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6663                 break;
6664         case RTE_ETH_FILTER_GENERIC:
6665                 if (filter_op != RTE_ETH_FILTER_GET)
6666                         return -EINVAL;
6667                 *(const void **)arg = &ixgbe_flow_ops;
6668                 break;
6669         default:
6670                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6671                                                         filter_type);
6672                 ret = -EINVAL;
6673                 break;
6674         }
6675
6676         return ret;
6677 }
6678
6679 static u8 *
6680 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6681                         u8 **mc_addr_ptr, u32 *vmdq)
6682 {
6683         u8 *mc_addr;
6684
6685         *vmdq = 0;
6686         mc_addr = *mc_addr_ptr;
6687         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6688         return mc_addr;
6689 }
6690
6691 static int
6692 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6693                           struct ether_addr *mc_addr_set,
6694                           uint32_t nb_mc_addr)
6695 {
6696         struct ixgbe_hw *hw;
6697         u8 *mc_addr_list;
6698
6699         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700         mc_addr_list = (u8 *)mc_addr_set;
6701         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6702                                          ixgbe_dev_addr_list_itr, TRUE);
6703 }
6704
6705 static uint64_t
6706 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6707 {
6708         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6709         uint64_t systime_cycles;
6710
6711         switch (hw->mac.type) {
6712         case ixgbe_mac_X550:
6713         case ixgbe_mac_X550EM_x:
6714         case ixgbe_mac_X550EM_a:
6715                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6716                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6717                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6718                                 * NSEC_PER_SEC;
6719                 break;
6720         default:
6721                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6722                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6723                                 << 32;
6724         }
6725
6726         return systime_cycles;
6727 }
6728
6729 static uint64_t
6730 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6731 {
6732         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6733         uint64_t rx_tstamp_cycles;
6734
6735         switch (hw->mac.type) {
6736         case ixgbe_mac_X550:
6737         case ixgbe_mac_X550EM_x:
6738         case ixgbe_mac_X550EM_a:
6739                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6740                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6741                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6742                                 * NSEC_PER_SEC;
6743                 break;
6744         default:
6745                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6746                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6747                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6748                                 << 32;
6749         }
6750
6751         return rx_tstamp_cycles;
6752 }
6753
6754 static uint64_t
6755 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6756 {
6757         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6758         uint64_t tx_tstamp_cycles;
6759
6760         switch (hw->mac.type) {
6761         case ixgbe_mac_X550:
6762         case ixgbe_mac_X550EM_x:
6763         case ixgbe_mac_X550EM_a:
6764                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6765                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6766                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6767                                 * NSEC_PER_SEC;
6768                 break;
6769         default:
6770                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6771                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6772                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6773                                 << 32;
6774         }
6775
6776         return tx_tstamp_cycles;
6777 }
6778
6779 static void
6780 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6781 {
6782         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6783         struct ixgbe_adapter *adapter =
6784                 (struct ixgbe_adapter *)dev->data->dev_private;
6785         struct rte_eth_link link;
6786         uint32_t incval = 0;
6787         uint32_t shift = 0;
6788
6789         /* Get current link speed. */
6790         memset(&link, 0, sizeof(link));
6791         ixgbe_dev_link_update(dev, 1);
6792         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6793
6794         switch (link.link_speed) {
6795         case ETH_SPEED_NUM_100M:
6796                 incval = IXGBE_INCVAL_100;
6797                 shift = IXGBE_INCVAL_SHIFT_100;
6798                 break;
6799         case ETH_SPEED_NUM_1G:
6800                 incval = IXGBE_INCVAL_1GB;
6801                 shift = IXGBE_INCVAL_SHIFT_1GB;
6802                 break;
6803         case ETH_SPEED_NUM_10G:
6804         default:
6805                 incval = IXGBE_INCVAL_10GB;
6806                 shift = IXGBE_INCVAL_SHIFT_10GB;
6807                 break;
6808         }
6809
6810         switch (hw->mac.type) {
6811         case ixgbe_mac_X550:
6812         case ixgbe_mac_X550EM_x:
6813         case ixgbe_mac_X550EM_a:
6814                 /* Independent of link speed. */
6815                 incval = 1;
6816                 /* Cycles read will be interpreted as ns. */
6817                 shift = 0;
6818                 /* Fall-through */
6819         case ixgbe_mac_X540:
6820                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6821                 break;
6822         case ixgbe_mac_82599EB:
6823                 incval >>= IXGBE_INCVAL_SHIFT_82599;
6824                 shift -= IXGBE_INCVAL_SHIFT_82599;
6825                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6826                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6827                 break;
6828         default:
6829                 /* Not supported. */
6830                 return;
6831         }
6832
6833         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6834         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6835         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6836
6837         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6838         adapter->systime_tc.cc_shift = shift;
6839         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6840
6841         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6842         adapter->rx_tstamp_tc.cc_shift = shift;
6843         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6844
6845         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6846         adapter->tx_tstamp_tc.cc_shift = shift;
6847         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6848 }
6849
6850 static int
6851 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6852 {
6853         struct ixgbe_adapter *adapter =
6854                         (struct ixgbe_adapter *)dev->data->dev_private;
6855
6856         adapter->systime_tc.nsec += delta;
6857         adapter->rx_tstamp_tc.nsec += delta;
6858         adapter->tx_tstamp_tc.nsec += delta;
6859
6860         return 0;
6861 }
6862
6863 static int
6864 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6865 {
6866         uint64_t ns;
6867         struct ixgbe_adapter *adapter =
6868                         (struct ixgbe_adapter *)dev->data->dev_private;
6869
6870         ns = rte_timespec_to_ns(ts);
6871         /* Set the timecounters to a new value. */
6872         adapter->systime_tc.nsec = ns;
6873         adapter->rx_tstamp_tc.nsec = ns;
6874         adapter->tx_tstamp_tc.nsec = ns;
6875
6876         return 0;
6877 }
6878
6879 static int
6880 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6881 {
6882         uint64_t ns, systime_cycles;
6883         struct ixgbe_adapter *adapter =
6884                         (struct ixgbe_adapter *)dev->data->dev_private;
6885
6886         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6887         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6888         *ts = rte_ns_to_timespec(ns);
6889
6890         return 0;
6891 }
6892
6893 static int
6894 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6895 {
6896         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6897         uint32_t tsync_ctl;
6898         uint32_t tsauxc;
6899
6900         /* Stop the timesync system time. */
6901         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6902         /* Reset the timesync system time value. */
6903         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6904         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6905
6906         /* Enable system time for platforms where it isn't on by default. */
6907         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6908         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6909         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6910
6911         ixgbe_start_timecounters(dev);
6912
6913         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6914         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6915                         (ETHER_TYPE_1588 |
6916                          IXGBE_ETQF_FILTER_EN |
6917                          IXGBE_ETQF_1588));
6918
6919         /* Enable timestamping of received PTP packets. */
6920         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6921         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6922         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6923
6924         /* Enable timestamping of transmitted PTP packets. */
6925         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6926         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6927         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6928
6929         IXGBE_WRITE_FLUSH(hw);
6930
6931         return 0;
6932 }
6933
6934 static int
6935 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6936 {
6937         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6938         uint32_t tsync_ctl;
6939
6940         /* Disable timestamping of transmitted PTP packets. */
6941         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6942         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6943         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6944
6945         /* Disable timestamping of received PTP packets. */
6946         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6947         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6948         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6949
6950         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6951         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6952
6953         /* Stop incrementating the System Time registers. */
6954         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6955
6956         return 0;
6957 }
6958
6959 static int
6960 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6961                                  struct timespec *timestamp,
6962                                  uint32_t flags __rte_unused)
6963 {
6964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6965         struct ixgbe_adapter *adapter =
6966                 (struct ixgbe_adapter *)dev->data->dev_private;
6967         uint32_t tsync_rxctl;
6968         uint64_t rx_tstamp_cycles;
6969         uint64_t ns;
6970
6971         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6972         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6973                 return -EINVAL;
6974
6975         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6976         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6977         *timestamp = rte_ns_to_timespec(ns);
6978
6979         return  0;
6980 }
6981
6982 static int
6983 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6984                                  struct timespec *timestamp)
6985 {
6986         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6987         struct ixgbe_adapter *adapter =
6988                 (struct ixgbe_adapter *)dev->data->dev_private;
6989         uint32_t tsync_txctl;
6990         uint64_t tx_tstamp_cycles;
6991         uint64_t ns;
6992
6993         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6994         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6995                 return -EINVAL;
6996
6997         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6998         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6999         *timestamp = rte_ns_to_timespec(ns);
7000
7001         return 0;
7002 }
7003
7004 static int
7005 ixgbe_get_reg_length(struct rte_eth_dev *dev)
7006 {
7007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7008         int count = 0;
7009         int g_ind = 0;
7010         const struct reg_info *reg_group;
7011         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7012                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7013
7014         while ((reg_group = reg_set[g_ind++]))
7015                 count += ixgbe_regs_group_count(reg_group);
7016
7017         return count;
7018 }
7019
7020 static int
7021 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
7022 {
7023         int count = 0;
7024         int g_ind = 0;
7025         const struct reg_info *reg_group;
7026
7027         while ((reg_group = ixgbevf_regs[g_ind++]))
7028                 count += ixgbe_regs_group_count(reg_group);
7029
7030         return count;
7031 }
7032
7033 static int
7034 ixgbe_get_regs(struct rte_eth_dev *dev,
7035               struct rte_dev_reg_info *regs)
7036 {
7037         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7038         uint32_t *data = regs->data;
7039         int g_ind = 0;
7040         int count = 0;
7041         const struct reg_info *reg_group;
7042         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7043                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7044
7045         if (data == NULL) {
7046                 regs->length = ixgbe_get_reg_length(dev);
7047                 regs->width = sizeof(uint32_t);
7048                 return 0;
7049         }
7050
7051         /* Support only full register dump */
7052         if ((regs->length == 0) ||
7053             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7054                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7055                         hw->device_id;
7056                 while ((reg_group = reg_set[g_ind++]))
7057                         count += ixgbe_read_regs_group(dev, &data[count],
7058                                 reg_group);
7059                 return 0;
7060         }
7061
7062         return -ENOTSUP;
7063 }
7064
7065 static int
7066 ixgbevf_get_regs(struct rte_eth_dev *dev,
7067                 struct rte_dev_reg_info *regs)
7068 {
7069         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7070         uint32_t *data = regs->data;
7071         int g_ind = 0;
7072         int count = 0;
7073         const struct reg_info *reg_group;
7074
7075         if (data == NULL) {
7076                 regs->length = ixgbevf_get_reg_length(dev);
7077                 regs->width = sizeof(uint32_t);
7078                 return 0;
7079         }
7080
7081         /* Support only full register dump */
7082         if ((regs->length == 0) ||
7083             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7084                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7085                         hw->device_id;
7086                 while ((reg_group = ixgbevf_regs[g_ind++]))
7087                         count += ixgbe_read_regs_group(dev, &data[count],
7088                                                       reg_group);
7089                 return 0;
7090         }
7091
7092         return -ENOTSUP;
7093 }
7094
7095 static int
7096 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7097 {
7098         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7099
7100         /* Return unit is byte count */
7101         return hw->eeprom.word_size * 2;
7102 }
7103
7104 static int
7105 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7106                 struct rte_dev_eeprom_info *in_eeprom)
7107 {
7108         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7109         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7110         uint16_t *data = in_eeprom->data;
7111         int first, length;
7112
7113         first = in_eeprom->offset >> 1;
7114         length = in_eeprom->length >> 1;
7115         if ((first > hw->eeprom.word_size) ||
7116             ((first + length) > hw->eeprom.word_size))
7117                 return -EINVAL;
7118
7119         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7120
7121         return eeprom->ops.read_buffer(hw, first, length, data);
7122 }
7123
7124 static int
7125 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7126                 struct rte_dev_eeprom_info *in_eeprom)
7127 {
7128         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7129         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7130         uint16_t *data = in_eeprom->data;
7131         int first, length;
7132
7133         first = in_eeprom->offset >> 1;
7134         length = in_eeprom->length >> 1;
7135         if ((first > hw->eeprom.word_size) ||
7136             ((first + length) > hw->eeprom.word_size))
7137                 return -EINVAL;
7138
7139         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7140
7141         return eeprom->ops.write_buffer(hw,  first, length, data);
7142 }
7143
7144 uint16_t
7145 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7146         switch (mac_type) {
7147         case ixgbe_mac_X550:
7148         case ixgbe_mac_X550EM_x:
7149         case ixgbe_mac_X550EM_a:
7150                 return ETH_RSS_RETA_SIZE_512;
7151         case ixgbe_mac_X550_vf:
7152         case ixgbe_mac_X550EM_x_vf:
7153         case ixgbe_mac_X550EM_a_vf:
7154                 return ETH_RSS_RETA_SIZE_64;
7155         default:
7156                 return ETH_RSS_RETA_SIZE_128;
7157         }
7158 }
7159
7160 uint32_t
7161 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7162         switch (mac_type) {
7163         case ixgbe_mac_X550:
7164         case ixgbe_mac_X550EM_x:
7165         case ixgbe_mac_X550EM_a:
7166                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7167                         return IXGBE_RETA(reta_idx >> 2);
7168                 else
7169                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7170         case ixgbe_mac_X550_vf:
7171         case ixgbe_mac_X550EM_x_vf:
7172         case ixgbe_mac_X550EM_a_vf:
7173                 return IXGBE_VFRETA(reta_idx >> 2);
7174         default:
7175                 return IXGBE_RETA(reta_idx >> 2);
7176         }
7177 }
7178
7179 uint32_t
7180 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7181         switch (mac_type) {
7182         case ixgbe_mac_X550_vf:
7183         case ixgbe_mac_X550EM_x_vf:
7184         case ixgbe_mac_X550EM_a_vf:
7185                 return IXGBE_VFMRQC;
7186         default:
7187                 return IXGBE_MRQC;
7188         }
7189 }
7190
7191 uint32_t
7192 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7193         switch (mac_type) {
7194         case ixgbe_mac_X550_vf:
7195         case ixgbe_mac_X550EM_x_vf:
7196         case ixgbe_mac_X550EM_a_vf:
7197                 return IXGBE_VFRSSRK(i);
7198         default:
7199                 return IXGBE_RSSRK(i);
7200         }
7201 }
7202
7203 bool
7204 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7205         switch (mac_type) {
7206         case ixgbe_mac_82599_vf:
7207         case ixgbe_mac_X540_vf:
7208                 return 0;
7209         default:
7210                 return 1;
7211         }
7212 }
7213
7214 static int
7215 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7216                         struct rte_eth_dcb_info *dcb_info)
7217 {
7218         struct ixgbe_dcb_config *dcb_config =
7219                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7220         struct ixgbe_dcb_tc_config *tc;
7221         uint8_t i, j;
7222
7223         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7224                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7225         else
7226                 dcb_info->nb_tcs = 1;
7227
7228         if (dcb_config->vt_mode) { /* vt is enabled*/
7229                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7230                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7231                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7232                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7233                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7234                         for (j = 0; j < dcb_info->nb_tcs; j++) {
7235                                 dcb_info->tc_queue.tc_rxq[i][j].base =
7236                                                 i * dcb_info->nb_tcs + j;
7237                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7238                                 dcb_info->tc_queue.tc_txq[i][j].base =
7239                                                 i * dcb_info->nb_tcs + j;
7240                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7241                         }
7242                 }
7243         } else { /* vt is disabled*/
7244                 struct rte_eth_dcb_rx_conf *rx_conf =
7245                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7246                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7247                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7248                 if (dcb_info->nb_tcs == ETH_4_TCS) {
7249                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7250                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7251                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7252                         }
7253                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7254                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
7255                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
7256                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
7257                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7258                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7259                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7260                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7261                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7262                         for (i = 0; i < dcb_info->nb_tcs; i++) {
7263                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7264                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7265                         }
7266                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
7267                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
7268                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
7269                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
7270                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
7271                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
7272                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
7273                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
7274                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7275                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7276                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7277                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7278                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7279                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7280                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7281                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7282                 }
7283         }
7284         for (i = 0; i < dcb_info->nb_tcs; i++) {
7285                 tc = &dcb_config->tc_config[i];
7286                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7287         }
7288         return 0;
7289 }
7290
7291 /* Update e-tag ether type */
7292 static int
7293 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7294                             uint16_t ether_type)
7295 {
7296         uint32_t etag_etype;
7297
7298         if (hw->mac.type != ixgbe_mac_X550 &&
7299             hw->mac.type != ixgbe_mac_X550EM_x &&
7300             hw->mac.type != ixgbe_mac_X550EM_a) {
7301                 return -ENOTSUP;
7302         }
7303
7304         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7305         etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7306         etag_etype |= ether_type;
7307         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7308         IXGBE_WRITE_FLUSH(hw);
7309
7310         return 0;
7311 }
7312
7313 /* Config l2 tunnel ether type */
7314 static int
7315 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7316                                   struct rte_eth_l2_tunnel_conf *l2_tunnel)
7317 {
7318         int ret = 0;
7319         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7320         struct ixgbe_l2_tn_info *l2_tn_info =
7321                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7322
7323         if (l2_tunnel == NULL)
7324                 return -EINVAL;
7325
7326         switch (l2_tunnel->l2_tunnel_type) {
7327         case RTE_L2_TUNNEL_TYPE_E_TAG:
7328                 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7329                 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7330                 break;
7331         default:
7332                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7333                 ret = -EINVAL;
7334                 break;
7335         }
7336
7337         return ret;
7338 }
7339
7340 /* Enable e-tag tunnel */
7341 static int
7342 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7343 {
7344         uint32_t etag_etype;
7345
7346         if (hw->mac.type != ixgbe_mac_X550 &&
7347             hw->mac.type != ixgbe_mac_X550EM_x &&
7348             hw->mac.type != ixgbe_mac_X550EM_a) {
7349                 return -ENOTSUP;
7350         }
7351
7352         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7353         etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7354         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7355         IXGBE_WRITE_FLUSH(hw);
7356
7357         return 0;
7358 }
7359
7360 /* Enable l2 tunnel */
7361 static int
7362 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7363                            enum rte_eth_tunnel_type l2_tunnel_type)
7364 {
7365         int ret = 0;
7366         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7367         struct ixgbe_l2_tn_info *l2_tn_info =
7368                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7369
7370         switch (l2_tunnel_type) {
7371         case RTE_L2_TUNNEL_TYPE_E_TAG:
7372                 l2_tn_info->e_tag_en = TRUE;
7373                 ret = ixgbe_e_tag_enable(hw);
7374                 break;
7375         default:
7376                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7377                 ret = -EINVAL;
7378                 break;
7379         }
7380
7381         return ret;
7382 }
7383
7384 /* Disable e-tag tunnel */
7385 static int
7386 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7387 {
7388         uint32_t etag_etype;
7389
7390         if (hw->mac.type != ixgbe_mac_X550 &&
7391             hw->mac.type != ixgbe_mac_X550EM_x &&
7392             hw->mac.type != ixgbe_mac_X550EM_a) {
7393                 return -ENOTSUP;
7394         }
7395
7396         etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7397         etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7398         IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7399         IXGBE_WRITE_FLUSH(hw);
7400
7401         return 0;
7402 }
7403
7404 /* Disable l2 tunnel */
7405 static int
7406 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7407                             enum rte_eth_tunnel_type l2_tunnel_type)
7408 {
7409         int ret = 0;
7410         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7411         struct ixgbe_l2_tn_info *l2_tn_info =
7412                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7413
7414         switch (l2_tunnel_type) {
7415         case RTE_L2_TUNNEL_TYPE_E_TAG:
7416                 l2_tn_info->e_tag_en = FALSE;
7417                 ret = ixgbe_e_tag_disable(hw);
7418                 break;
7419         default:
7420                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7421                 ret = -EINVAL;
7422                 break;
7423         }
7424
7425         return ret;
7426 }
7427
7428 static int
7429 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7430                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7431 {
7432         int ret = 0;
7433         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7434         uint32_t i, rar_entries;
7435         uint32_t rar_low, rar_high;
7436
7437         if (hw->mac.type != ixgbe_mac_X550 &&
7438             hw->mac.type != ixgbe_mac_X550EM_x &&
7439             hw->mac.type != ixgbe_mac_X550EM_a) {
7440                 return -ENOTSUP;
7441         }
7442
7443         rar_entries = ixgbe_get_num_rx_addrs(hw);
7444
7445         for (i = 1; i < rar_entries; i++) {
7446                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7447                 rar_low  = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7448                 if ((rar_high & IXGBE_RAH_AV) &&
7449                     (rar_high & IXGBE_RAH_ADTYPE) &&
7450                     ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7451                      l2_tunnel->tunnel_id)) {
7452                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7453                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7454
7455                         ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7456
7457                         return ret;
7458                 }
7459         }
7460
7461         return ret;
7462 }
7463
7464 static int
7465 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7466                        struct rte_eth_l2_tunnel_conf *l2_tunnel)
7467 {
7468         int ret = 0;
7469         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7470         uint32_t i, rar_entries;
7471         uint32_t rar_low, rar_high;
7472
7473         if (hw->mac.type != ixgbe_mac_X550 &&
7474             hw->mac.type != ixgbe_mac_X550EM_x &&
7475             hw->mac.type != ixgbe_mac_X550EM_a) {
7476                 return -ENOTSUP;
7477         }
7478
7479         /* One entry for one tunnel. Try to remove potential existing entry. */
7480         ixgbe_e_tag_filter_del(dev, l2_tunnel);
7481
7482         rar_entries = ixgbe_get_num_rx_addrs(hw);
7483
7484         for (i = 1; i < rar_entries; i++) {
7485                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7486                 if (rar_high & IXGBE_RAH_AV) {
7487                         continue;
7488                 } else {
7489                         ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7490                         rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7491                         rar_low = l2_tunnel->tunnel_id;
7492
7493                         IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7494                         IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7495
7496                         return ret;
7497                 }
7498         }
7499
7500         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7501                      " Please remove a rule before adding a new one.");
7502         return -EINVAL;
7503 }
7504
7505 static inline struct ixgbe_l2_tn_filter *
7506 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7507                           struct ixgbe_l2_tn_key *key)
7508 {
7509         int ret;
7510
7511         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7512         if (ret < 0)
7513                 return NULL;
7514
7515         return l2_tn_info->hash_map[ret];
7516 }
7517
7518 static inline int
7519 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7520                           struct ixgbe_l2_tn_filter *l2_tn_filter)
7521 {
7522         int ret;
7523
7524         ret = rte_hash_add_key(l2_tn_info->hash_handle,
7525                                &l2_tn_filter->key);
7526
7527         if (ret < 0) {
7528                 PMD_DRV_LOG(ERR,
7529                             "Failed to insert L2 tunnel filter"
7530                             " to hash table %d!",
7531                             ret);
7532                 return ret;
7533         }
7534
7535         l2_tn_info->hash_map[ret] = l2_tn_filter;
7536
7537         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7538
7539         return 0;
7540 }
7541
7542 static inline int
7543 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7544                           struct ixgbe_l2_tn_key *key)
7545 {
7546         int ret;
7547         struct ixgbe_l2_tn_filter *l2_tn_filter;
7548
7549         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7550
7551         if (ret < 0) {
7552                 PMD_DRV_LOG(ERR,
7553                             "No such L2 tunnel filter to delete %d!",
7554                             ret);
7555                 return ret;
7556         }
7557
7558         l2_tn_filter = l2_tn_info->hash_map[ret];
7559         l2_tn_info->hash_map[ret] = NULL;
7560
7561         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7562         rte_free(l2_tn_filter);
7563
7564         return 0;
7565 }
7566
7567 /* Add l2 tunnel filter */
7568 int
7569 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7570                                struct rte_eth_l2_tunnel_conf *l2_tunnel,
7571                                bool restore)
7572 {
7573         int ret;
7574         struct ixgbe_l2_tn_info *l2_tn_info =
7575                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7576         struct ixgbe_l2_tn_key key;
7577         struct ixgbe_l2_tn_filter *node;
7578
7579         if (!restore) {
7580                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7581                 key.tn_id = l2_tunnel->tunnel_id;
7582
7583                 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7584
7585                 if (node) {
7586                         PMD_DRV_LOG(ERR,
7587                                     "The L2 tunnel filter already exists!");
7588                         return -EINVAL;
7589                 }
7590
7591                 node = rte_zmalloc("ixgbe_l2_tn",
7592                                    sizeof(struct ixgbe_l2_tn_filter),
7593                                    0);
7594                 if (!node)
7595                         return -ENOMEM;
7596
7597                 (void)rte_memcpy(&node->key,
7598                                  &key,
7599                                  sizeof(struct ixgbe_l2_tn_key));
7600                 node->pool = l2_tunnel->pool;
7601                 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7602                 if (ret < 0) {
7603                         rte_free(node);
7604                         return ret;
7605                 }
7606         }
7607
7608         switch (l2_tunnel->l2_tunnel_type) {
7609         case RTE_L2_TUNNEL_TYPE_E_TAG:
7610                 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7611                 break;
7612         default:
7613                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7614                 ret = -EINVAL;
7615                 break;
7616         }
7617
7618         if ((!restore) && (ret < 0))
7619                 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7620
7621         return ret;
7622 }
7623
7624 /* Delete l2 tunnel filter */
7625 int
7626 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7627                                struct rte_eth_l2_tunnel_conf *l2_tunnel)
7628 {
7629         int ret;
7630         struct ixgbe_l2_tn_info *l2_tn_info =
7631                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7632         struct ixgbe_l2_tn_key key;
7633
7634         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7635         key.tn_id = l2_tunnel->tunnel_id;
7636         ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7637         if (ret < 0)
7638                 return ret;
7639
7640         switch (l2_tunnel->l2_tunnel_type) {
7641         case RTE_L2_TUNNEL_TYPE_E_TAG:
7642                 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7643                 break;
7644         default:
7645                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7646                 ret = -EINVAL;
7647                 break;
7648         }
7649
7650         return ret;
7651 }
7652
7653 /**
7654  * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7655  * @dev: pointer to rte_eth_dev structure
7656  * @filter_op:operation will be taken.
7657  * @arg: a pointer to specific structure corresponding to the filter_op
7658  */
7659 static int
7660 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7661                                   enum rte_filter_op filter_op,
7662                                   void *arg)
7663 {
7664         int ret;
7665
7666         if (filter_op == RTE_ETH_FILTER_NOP)
7667                 return 0;
7668
7669         if (arg == NULL) {
7670                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7671                             filter_op);
7672                 return -EINVAL;
7673         }
7674
7675         switch (filter_op) {
7676         case RTE_ETH_FILTER_ADD:
7677                 ret = ixgbe_dev_l2_tunnel_filter_add
7678                         (dev,
7679                          (struct rte_eth_l2_tunnel_conf *)arg,
7680                          FALSE);
7681                 break;
7682         case RTE_ETH_FILTER_DELETE:
7683                 ret = ixgbe_dev_l2_tunnel_filter_del
7684                         (dev,
7685                          (struct rte_eth_l2_tunnel_conf *)arg);
7686                 break;
7687         default:
7688                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7689                 ret = -EINVAL;
7690                 break;
7691         }
7692         return ret;
7693 }
7694
7695 static int
7696 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7697 {
7698         int ret = 0;
7699         uint32_t ctrl;
7700         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7701
7702         if (hw->mac.type != ixgbe_mac_X550 &&
7703             hw->mac.type != ixgbe_mac_X550EM_x &&
7704             hw->mac.type != ixgbe_mac_X550EM_a) {
7705                 return -ENOTSUP;
7706         }
7707
7708         ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7709         ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7710         if (en)
7711                 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7712         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7713
7714         return ret;
7715 }
7716
7717 /* Enable l2 tunnel forwarding */
7718 static int
7719 ixgbe_dev_l2_tunnel_forwarding_enable
7720         (struct rte_eth_dev *dev,
7721          enum rte_eth_tunnel_type l2_tunnel_type)
7722 {
7723         struct ixgbe_l2_tn_info *l2_tn_info =
7724                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7725         int ret = 0;
7726
7727         switch (l2_tunnel_type) {
7728         case RTE_L2_TUNNEL_TYPE_E_TAG:
7729                 l2_tn_info->e_tag_fwd_en = TRUE;
7730                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7731                 break;
7732         default:
7733                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7734                 ret = -EINVAL;
7735                 break;
7736         }
7737
7738         return ret;
7739 }
7740
7741 /* Disable l2 tunnel forwarding */
7742 static int
7743 ixgbe_dev_l2_tunnel_forwarding_disable
7744         (struct rte_eth_dev *dev,
7745          enum rte_eth_tunnel_type l2_tunnel_type)
7746 {
7747         struct ixgbe_l2_tn_info *l2_tn_info =
7748                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7749         int ret = 0;
7750
7751         switch (l2_tunnel_type) {
7752         case RTE_L2_TUNNEL_TYPE_E_TAG:
7753                 l2_tn_info->e_tag_fwd_en = FALSE;
7754                 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7755                 break;
7756         default:
7757                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7758                 ret = -EINVAL;
7759                 break;
7760         }
7761
7762         return ret;
7763 }
7764
7765 static int
7766 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7767                              struct rte_eth_l2_tunnel_conf *l2_tunnel,
7768                              bool en)
7769 {
7770         struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(dev);
7771         int ret = 0;
7772         uint32_t vmtir, vmvir;
7773         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7774
7775         if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7776                 PMD_DRV_LOG(ERR,
7777                             "VF id %u should be less than %u",
7778                             l2_tunnel->vf_id,
7779                             pci_dev->max_vfs);
7780                 return -EINVAL;
7781         }
7782
7783         if (hw->mac.type != ixgbe_mac_X550 &&
7784             hw->mac.type != ixgbe_mac_X550EM_x &&
7785             hw->mac.type != ixgbe_mac_X550EM_a) {
7786                 return -ENOTSUP;
7787         }
7788
7789         if (en)
7790                 vmtir = l2_tunnel->tunnel_id;
7791         else
7792                 vmtir = 0;
7793
7794         IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7795
7796         vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7797         vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7798         if (en)
7799                 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7800         IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7801
7802         return ret;
7803 }
7804
7805 /* Enable l2 tunnel tag insertion */
7806 static int
7807 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7808                                      struct rte_eth_l2_tunnel_conf *l2_tunnel)
7809 {
7810         int ret = 0;
7811
7812         switch (l2_tunnel->l2_tunnel_type) {
7813         case RTE_L2_TUNNEL_TYPE_E_TAG:
7814                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7815                 break;
7816         default:
7817                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7818                 ret = -EINVAL;
7819                 break;
7820         }
7821
7822         return ret;
7823 }
7824
7825 /* Disable l2 tunnel tag insertion */
7826 static int
7827 ixgbe_dev_l2_tunnel_insertion_disable
7828         (struct rte_eth_dev *dev,
7829          struct rte_eth_l2_tunnel_conf *l2_tunnel)
7830 {
7831         int ret = 0;
7832
7833         switch (l2_tunnel->l2_tunnel_type) {
7834         case RTE_L2_TUNNEL_TYPE_E_TAG:
7835                 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7836                 break;
7837         default:
7838                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7839                 ret = -EINVAL;
7840                 break;
7841         }
7842
7843         return ret;
7844 }
7845
7846 static int
7847 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7848                              bool en)
7849 {
7850         int ret = 0;
7851         uint32_t qde;
7852         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7853
7854         if (hw->mac.type != ixgbe_mac_X550 &&
7855             hw->mac.type != ixgbe_mac_X550EM_x &&
7856             hw->mac.type != ixgbe_mac_X550EM_a) {
7857                 return -ENOTSUP;
7858         }
7859
7860         qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7861         if (en)
7862                 qde |= IXGBE_QDE_STRIP_TAG;
7863         else
7864                 qde &= ~IXGBE_QDE_STRIP_TAG;
7865         qde &= ~IXGBE_QDE_READ;
7866         qde |= IXGBE_QDE_WRITE;
7867         IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7868
7869         return ret;
7870 }
7871
7872 /* Enable l2 tunnel tag stripping */
7873 static int
7874 ixgbe_dev_l2_tunnel_stripping_enable
7875         (struct rte_eth_dev *dev,
7876          enum rte_eth_tunnel_type l2_tunnel_type)
7877 {
7878         int ret = 0;
7879
7880         switch (l2_tunnel_type) {
7881         case RTE_L2_TUNNEL_TYPE_E_TAG:
7882                 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7883                 break;
7884         default:
7885                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7886                 ret = -EINVAL;
7887                 break;
7888         }
7889
7890         return ret;
7891 }
7892
7893 /* Disable l2 tunnel tag stripping */
7894 static int
7895 ixgbe_dev_l2_tunnel_stripping_disable
7896         (struct rte_eth_dev *dev,
7897          enum rte_eth_tunnel_type l2_tunnel_type)
7898 {
7899         int ret = 0;
7900
7901         switch (l2_tunnel_type) {
7902         case RTE_L2_TUNNEL_TYPE_E_TAG:
7903                 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7904                 break;
7905         default:
7906                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7907                 ret = -EINVAL;
7908                 break;
7909         }
7910
7911         return ret;
7912 }
7913
7914 /* Enable/disable l2 tunnel offload functions */
7915 static int
7916 ixgbe_dev_l2_tunnel_offload_set
7917         (struct rte_eth_dev *dev,
7918          struct rte_eth_l2_tunnel_conf *l2_tunnel,
7919          uint32_t mask,
7920          uint8_t en)
7921 {
7922         int ret = 0;
7923
7924         if (l2_tunnel == NULL)
7925                 return -EINVAL;
7926
7927         ret = -EINVAL;
7928         if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7929                 if (en)
7930                         ret = ixgbe_dev_l2_tunnel_enable(
7931                                 dev,
7932                                 l2_tunnel->l2_tunnel_type);
7933                 else
7934                         ret = ixgbe_dev_l2_tunnel_disable(
7935                                 dev,
7936                                 l2_tunnel->l2_tunnel_type);
7937         }
7938
7939         if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7940                 if (en)
7941                         ret = ixgbe_dev_l2_tunnel_insertion_enable(
7942                                 dev,
7943                                 l2_tunnel);
7944                 else
7945                         ret = ixgbe_dev_l2_tunnel_insertion_disable(
7946                                 dev,
7947                                 l2_tunnel);
7948         }
7949
7950         if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7951                 if (en)
7952                         ret = ixgbe_dev_l2_tunnel_stripping_enable(
7953                                 dev,
7954                                 l2_tunnel->l2_tunnel_type);
7955                 else
7956                         ret = ixgbe_dev_l2_tunnel_stripping_disable(
7957                                 dev,
7958                                 l2_tunnel->l2_tunnel_type);
7959         }
7960
7961         if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7962                 if (en)
7963                         ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7964                                 dev,
7965                                 l2_tunnel->l2_tunnel_type);
7966                 else
7967                         ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7968                                 dev,
7969                                 l2_tunnel->l2_tunnel_type);
7970         }
7971
7972         return ret;
7973 }
7974
7975 static int
7976 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7977                         uint16_t port)
7978 {
7979         IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7980         IXGBE_WRITE_FLUSH(hw);
7981
7982         return 0;
7983 }
7984
7985 /* There's only one register for VxLAN UDP port.
7986  * So, we cannot add several ports. Will update it.
7987  */
7988 static int
7989 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7990                      uint16_t port)
7991 {
7992         if (port == 0) {
7993                 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7994                 return -EINVAL;
7995         }
7996
7997         return ixgbe_update_vxlan_port(hw, port);
7998 }
7999
8000 /* We cannot delete the VxLAN port. For there's a register for VxLAN
8001  * UDP port, it must have a value.
8002  * So, will reset it to the original value 0.
8003  */
8004 static int
8005 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
8006                      uint16_t port)
8007 {
8008         uint16_t cur_port;
8009
8010         cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
8011
8012         if (cur_port != port) {
8013                 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
8014                 return -EINVAL;
8015         }
8016
8017         return ixgbe_update_vxlan_port(hw, 0);
8018 }
8019
8020 /* Add UDP tunneling port */
8021 static int
8022 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8023                               struct rte_eth_udp_tunnel *udp_tunnel)
8024 {
8025         int ret = 0;
8026         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8027
8028         if (hw->mac.type != ixgbe_mac_X550 &&
8029             hw->mac.type != ixgbe_mac_X550EM_x &&
8030             hw->mac.type != ixgbe_mac_X550EM_a) {
8031                 return -ENOTSUP;
8032         }
8033
8034         if (udp_tunnel == NULL)
8035                 return -EINVAL;
8036
8037         switch (udp_tunnel->prot_type) {
8038         case RTE_TUNNEL_TYPE_VXLAN:
8039                 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8040                 break;
8041
8042         case RTE_TUNNEL_TYPE_GENEVE:
8043         case RTE_TUNNEL_TYPE_TEREDO:
8044                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8045                 ret = -EINVAL;
8046                 break;
8047
8048         default:
8049                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8050                 ret = -EINVAL;
8051                 break;
8052         }
8053
8054         return ret;
8055 }
8056
8057 /* Remove UDP tunneling port */
8058 static int
8059 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8060                               struct rte_eth_udp_tunnel *udp_tunnel)
8061 {
8062         int ret = 0;
8063         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8064
8065         if (hw->mac.type != ixgbe_mac_X550 &&
8066             hw->mac.type != ixgbe_mac_X550EM_x &&
8067             hw->mac.type != ixgbe_mac_X550EM_a) {
8068                 return -ENOTSUP;
8069         }
8070
8071         if (udp_tunnel == NULL)
8072                 return -EINVAL;
8073
8074         switch (udp_tunnel->prot_type) {
8075         case RTE_TUNNEL_TYPE_VXLAN:
8076                 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8077                 break;
8078         case RTE_TUNNEL_TYPE_GENEVE:
8079         case RTE_TUNNEL_TYPE_TEREDO:
8080                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8081                 ret = -EINVAL;
8082                 break;
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -EINVAL;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 static void
8093 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8094 {
8095         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8096
8097         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8098 }
8099
8100 static void
8101 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8102 {
8103         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8104
8105         hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_NONE);
8106 }
8107
8108 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8109 {
8110         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8111         u32 in_msg = 0;
8112
8113         if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8114                 return;
8115
8116         /* PF reset VF event */
8117         if (in_msg == IXGBE_PF_CONTROL_MSG)
8118                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
8119 }
8120
8121 static int
8122 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8123 {
8124         uint32_t eicr;
8125         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8126         struct ixgbe_interrupt *intr =
8127                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8128         ixgbevf_intr_disable(hw);
8129
8130         /* read-on-clear nic registers here */
8131         eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8132         intr->flags = 0;
8133
8134         /* only one misc vector supported - mailbox */
8135         eicr &= IXGBE_VTEICR_MASK;
8136         if (eicr == IXGBE_MISC_VEC_ID)
8137                 intr->flags |= IXGBE_FLAG_MAILBOX;
8138
8139         return 0;
8140 }
8141
8142 static int
8143 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8144 {
8145         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8146         struct ixgbe_interrupt *intr =
8147                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8148
8149         if (intr->flags & IXGBE_FLAG_MAILBOX) {
8150                 ixgbevf_mbx_process(dev);
8151                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8152         }
8153
8154         ixgbevf_intr_enable(hw);
8155
8156         return 0;
8157 }
8158
8159 static void
8160 ixgbevf_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
8161                               void *param)
8162 {
8163         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8164
8165         ixgbevf_dev_interrupt_get_status(dev);
8166         ixgbevf_dev_interrupt_action(dev);
8167 }
8168
8169 /**
8170  *  ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8171  *  @hw: pointer to hardware structure
8172  *
8173  *  Stops the transmit data path and waits for the HW to internally empty
8174  *  the Tx security block
8175  **/
8176 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8177 {
8178 #define IXGBE_MAX_SECTX_POLL 40
8179
8180         int i;
8181         int sectxreg;
8182
8183         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8184         sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8185         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8186         for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8187                 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8188                 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8189                         break;
8190                 /* Use interrupt-safe sleep just in case */
8191                 usec_delay(1000);
8192         }
8193
8194         /* For informational purposes only */
8195         if (i >= IXGBE_MAX_SECTX_POLL)
8196                 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8197                          "path fully disabled.  Continuing with init.\n");
8198
8199         return IXGBE_SUCCESS;
8200 }
8201
8202 /**
8203  *  ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8204  *  @hw: pointer to hardware structure
8205  *
8206  *  Enables the transmit data path.
8207  **/
8208 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8209 {
8210         uint32_t sectxreg;
8211
8212         sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8213         sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8214         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8215         IXGBE_WRITE_FLUSH(hw);
8216
8217         return IXGBE_SUCCESS;
8218 }
8219
8220 int
8221 rte_pmd_ixgbe_macsec_enable(uint8_t port, uint8_t en, uint8_t rp)
8222 {
8223         struct ixgbe_hw *hw;
8224         struct rte_eth_dev *dev;
8225         uint32_t ctrl;
8226
8227         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8228
8229         dev = &rte_eth_devices[port];
8230         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8231
8232         /* Stop the data paths */
8233         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8234                 return -ENOTSUP;
8235         /*
8236          * Workaround:
8237          * As no ixgbe_disable_sec_rx_path equivalent is
8238          * implemented for tx in the base code, and we are
8239          * not allowed to modify the base code in DPDK, so
8240          * just call the hand-written one directly for now.
8241          * The hardware support has been checked by
8242          * ixgbe_disable_sec_rx_path().
8243          */
8244         ixgbe_disable_sec_tx_path_generic(hw);
8245
8246         /* Enable Ethernet CRC (required by MACsec offload) */
8247         ctrl = IXGBE_READ_REG(hw, IXGBE_HLREG0);
8248         ctrl |= IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP;
8249         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl);
8250
8251         /* Enable the TX and RX crypto engines */
8252         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8253         ctrl &= ~IXGBE_SECTXCTRL_SECTX_DIS;
8254         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8255
8256         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8257         ctrl &= ~IXGBE_SECRXCTRL_SECRX_DIS;
8258         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8259
8260         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
8261         ctrl &= ~IXGBE_SECTX_MINSECIFG_MASK;
8262         ctrl |= 0x3;
8263         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl);
8264
8265         /* Enable SA lookup */
8266         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8267         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8268         ctrl |= en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT :
8269                      IXGBE_LSECTXCTRL_AUTH;
8270         ctrl |= IXGBE_LSECTXCTRL_AISCI;
8271         ctrl &= ~IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8272         ctrl |= IXGBE_MACSEC_PNTHRSH & IXGBE_LSECTXCTRL_PNTHRSH_MASK;
8273         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8274
8275         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8276         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8277         ctrl |= IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT;
8278         ctrl &= ~IXGBE_LSECRXCTRL_PLSH;
8279         if (rp)
8280                 ctrl |= IXGBE_LSECRXCTRL_RP;
8281         else
8282                 ctrl &= ~IXGBE_LSECRXCTRL_RP;
8283         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8284
8285         /* Start the data paths */
8286         ixgbe_enable_sec_rx_path(hw);
8287         /*
8288          * Workaround:
8289          * As no ixgbe_enable_sec_rx_path equivalent is
8290          * implemented for tx in the base code, and we are
8291          * not allowed to modify the base code in DPDK, so
8292          * just call the hand-written one directly for now.
8293          */
8294         ixgbe_enable_sec_tx_path_generic(hw);
8295
8296         return 0;
8297 }
8298
8299 int
8300 rte_pmd_ixgbe_macsec_disable(uint8_t port)
8301 {
8302         struct ixgbe_hw *hw;
8303         struct rte_eth_dev *dev;
8304         uint32_t ctrl;
8305
8306         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8307
8308         dev = &rte_eth_devices[port];
8309         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8310
8311         /* Stop the data paths */
8312         if (ixgbe_disable_sec_rx_path(hw) != IXGBE_SUCCESS)
8313                 return -ENOTSUP;
8314         /*
8315          * Workaround:
8316          * As no ixgbe_disable_sec_rx_path equivalent is
8317          * implemented for tx in the base code, and we are
8318          * not allowed to modify the base code in DPDK, so
8319          * just call the hand-written one directly for now.
8320          * The hardware support has been checked by
8321          * ixgbe_disable_sec_rx_path().
8322          */
8323         ixgbe_disable_sec_tx_path_generic(hw);
8324
8325         /* Disable the TX and RX crypto engines */
8326         ctrl = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8327         ctrl |= IXGBE_SECTXCTRL_SECTX_DIS;
8328         IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl);
8329
8330         ctrl = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
8331         ctrl |= IXGBE_SECRXCTRL_SECRX_DIS;
8332         IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl);
8333
8334         /* Disable SA lookup */
8335         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL);
8336         ctrl &= ~IXGBE_LSECTXCTRL_EN_MASK;
8337         ctrl |= IXGBE_LSECTXCTRL_DISABLE;
8338         IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl);
8339
8340         ctrl = IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL);
8341         ctrl &= ~IXGBE_LSECRXCTRL_EN_MASK;
8342         ctrl |= IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT;
8343         IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl);
8344
8345         /* Start the data paths */
8346         ixgbe_enable_sec_rx_path(hw);
8347         /*
8348          * Workaround:
8349          * As no ixgbe_enable_sec_rx_path equivalent is
8350          * implemented for tx in the base code, and we are
8351          * not allowed to modify the base code in DPDK, so
8352          * just call the hand-written one directly for now.
8353          */
8354         ixgbe_enable_sec_tx_path_generic(hw);
8355
8356         return 0;
8357 }
8358
8359 int
8360 rte_pmd_ixgbe_macsec_config_txsc(uint8_t port, uint8_t *mac)
8361 {
8362         struct ixgbe_hw *hw;
8363         struct rte_eth_dev *dev;
8364         uint32_t ctrl;
8365
8366         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8367
8368         dev = &rte_eth_devices[port];
8369         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8370
8371         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8372         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCL, ctrl);
8373
8374         ctrl = mac[4] | (mac[5] << 8);
8375         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSCH, ctrl);
8376
8377         return 0;
8378 }
8379
8380 int
8381 rte_pmd_ixgbe_macsec_config_rxsc(uint8_t port, uint8_t *mac, uint16_t pi)
8382 {
8383         struct ixgbe_hw *hw;
8384         struct rte_eth_dev *dev;
8385         uint32_t ctrl;
8386
8387         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8388
8389         dev = &rte_eth_devices[port];
8390         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8391
8392         ctrl = mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24);
8393         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCL, ctrl);
8394
8395         pi = rte_cpu_to_be_16(pi);
8396         ctrl = mac[4] | (mac[5] << 8) | (pi << 16);
8397         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSCH, ctrl);
8398
8399         return 0;
8400 }
8401
8402 int
8403 rte_pmd_ixgbe_macsec_select_txsa(uint8_t port, uint8_t idx, uint8_t an,
8404                                  uint32_t pn, uint8_t *key)
8405 {
8406         struct ixgbe_hw *hw;
8407         struct rte_eth_dev *dev;
8408         uint32_t ctrl, i;
8409
8410         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8411
8412         dev = &rte_eth_devices[port];
8413         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8414
8415         if (idx != 0 && idx != 1)
8416                 return -EINVAL;
8417
8418         if (an >= 4)
8419                 return -EINVAL;
8420
8421         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8422
8423         /* Set the PN and key */
8424         pn = rte_cpu_to_be_32(pn);
8425         if (idx == 0) {
8426                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN0, pn);
8427
8428                 for (i = 0; i < 4; i++) {
8429                         ctrl = (key[i * 4 + 0] <<  0) |
8430                                (key[i * 4 + 1] <<  8) |
8431                                (key[i * 4 + 2] << 16) |
8432                                (key[i * 4 + 3] << 24);
8433                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY0(i), ctrl);
8434                 }
8435         } else {
8436                 IXGBE_WRITE_REG(hw, IXGBE_LSECTXPN1, pn);
8437
8438                 for (i = 0; i < 4; i++) {
8439                         ctrl = (key[i * 4 + 0] <<  0) |
8440                                (key[i * 4 + 1] <<  8) |
8441                                (key[i * 4 + 2] << 16) |
8442                                (key[i * 4 + 3] << 24);
8443                         IXGBE_WRITE_REG(hw, IXGBE_LSECTXKEY1(i), ctrl);
8444                 }
8445         }
8446
8447         /* Set AN and select the SA */
8448         ctrl = (an << idx * 2) | (idx << 4);
8449         IXGBE_WRITE_REG(hw, IXGBE_LSECTXSA, ctrl);
8450
8451         return 0;
8452 }
8453
8454 int
8455 rte_pmd_ixgbe_macsec_select_rxsa(uint8_t port, uint8_t idx, uint8_t an,
8456                                  uint32_t pn, uint8_t *key)
8457 {
8458         struct ixgbe_hw *hw;
8459         struct rte_eth_dev *dev;
8460         uint32_t ctrl, i;
8461
8462         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
8463
8464         dev = &rte_eth_devices[port];
8465         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8466
8467         if (idx != 0 && idx != 1)
8468                 return -EINVAL;
8469
8470         if (an >= 4)
8471                 return -EINVAL;
8472
8473         /* Set the PN */
8474         pn = rte_cpu_to_be_32(pn);
8475         IXGBE_WRITE_REG(hw, IXGBE_LSECRXPN(idx), pn);
8476
8477         /* Set the key */
8478         for (i = 0; i < 4; i++) {
8479                 ctrl = (key[i * 4 + 0] <<  0) |
8480                        (key[i * 4 + 1] <<  8) |
8481                        (key[i * 4 + 2] << 16) |
8482                        (key[i * 4 + 3] << 24);
8483                 IXGBE_WRITE_REG(hw, IXGBE_LSECRXKEY(idx, i), ctrl);
8484         }
8485
8486         /* Set the AN and validate the SA */
8487         ctrl = an | (1 << 2);
8488         IXGBE_WRITE_REG(hw, IXGBE_LSECRXSA(idx), ctrl);
8489
8490         return 0;
8491 }
8492
8493 /* restore n-tuple filter */
8494 static inline void
8495 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8496 {
8497         struct ixgbe_filter_info *filter_info =
8498                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8499         struct ixgbe_5tuple_filter *node;
8500
8501         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8502                 ixgbe_inject_5tuple_filter(dev, node);
8503         }
8504 }
8505
8506 /* restore ethernet type filter */
8507 static inline void
8508 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8509 {
8510         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8511         struct ixgbe_filter_info *filter_info =
8512                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8513         int i;
8514
8515         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8516                 if (filter_info->ethertype_mask & (1 << i)) {
8517                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8518                                         filter_info->ethertype_filters[i].etqf);
8519                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8520                                         filter_info->ethertype_filters[i].etqs);
8521                         IXGBE_WRITE_FLUSH(hw);
8522                 }
8523         }
8524 }
8525
8526 /* restore SYN filter */
8527 static inline void
8528 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8529 {
8530         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8531         struct ixgbe_filter_info *filter_info =
8532                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8533         uint32_t synqf;
8534
8535         synqf = filter_info->syn_info;
8536
8537         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8538                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8539                 IXGBE_WRITE_FLUSH(hw);
8540         }
8541 }
8542
8543 /* restore L2 tunnel filter */
8544 static inline void
8545 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8546 {
8547         struct ixgbe_l2_tn_info *l2_tn_info =
8548                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8549         struct ixgbe_l2_tn_filter *node;
8550         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8551
8552         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8553                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8554                 l2_tn_conf.tunnel_id      = node->key.tn_id;
8555                 l2_tn_conf.pool           = node->pool;
8556                 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8557         }
8558 }
8559
8560 static int
8561 ixgbe_filter_restore(struct rte_eth_dev *dev)
8562 {
8563         ixgbe_ntuple_filter_restore(dev);
8564         ixgbe_ethertype_filter_restore(dev);
8565         ixgbe_syn_filter_restore(dev);
8566         ixgbe_fdir_filter_restore(dev);
8567         ixgbe_l2_tn_filter_restore(dev);
8568
8569         return 0;
8570 }
8571
8572 static void
8573 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8574 {
8575         struct ixgbe_l2_tn_info *l2_tn_info =
8576                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8577         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8578
8579         if (l2_tn_info->e_tag_en)
8580                 (void)ixgbe_e_tag_enable(hw);
8581
8582         if (l2_tn_info->e_tag_fwd_en)
8583                 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8584
8585         (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8586 }
8587
8588 /* remove all the n-tuple filters */
8589 void
8590 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8591 {
8592         struct ixgbe_filter_info *filter_info =
8593                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8594         struct ixgbe_5tuple_filter *p_5tuple;
8595
8596         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8597                 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8598 }
8599
8600 /* remove all the ether type filters */
8601 void
8602 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8603 {
8604         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8605         struct ixgbe_filter_info *filter_info =
8606                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8607         int i;
8608
8609         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8610                 if (filter_info->ethertype_mask & (1 << i) &&
8611                     !filter_info->ethertype_filters[i].conf) {
8612                         (void)ixgbe_ethertype_filter_remove(filter_info,
8613                                                             (uint8_t)i);
8614                         IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8615                         IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8616                         IXGBE_WRITE_FLUSH(hw);
8617                 }
8618         }
8619 }
8620
8621 /* remove the SYN filter */
8622 void
8623 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8624 {
8625         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626         struct ixgbe_filter_info *filter_info =
8627                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8628
8629         if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8630                 filter_info->syn_info = 0;
8631
8632                 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8633                 IXGBE_WRITE_FLUSH(hw);
8634         }
8635 }
8636
8637 /* remove all the L2 tunnel filters */
8638 int
8639 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8640 {
8641         struct ixgbe_l2_tn_info *l2_tn_info =
8642                 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8643         struct ixgbe_l2_tn_filter *l2_tn_filter;
8644         struct rte_eth_l2_tunnel_conf l2_tn_conf;
8645         int ret = 0;
8646
8647         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8648                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8649                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
8650                 l2_tn_conf.pool           = l2_tn_filter->pool;
8651                 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8652                 if (ret < 0)
8653                         return ret;
8654         }
8655
8656         return 0;
8657 }
8658
8659 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd.pci_drv);
8660 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8661 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio");
8662 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd.pci_drv);
8663 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8664 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio");