4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
63 #include <rte_hash_crc.h>
65 #include "ixgbe_logs.h"
66 #include "base/ixgbe_api.h"
67 #include "base/ixgbe_vf.h"
68 #include "base/ixgbe_common.h"
69 #include "ixgbe_ethdev.h"
70 #include "ixgbe_bypass.h"
71 #include "ixgbe_rxtx.h"
72 #include "base/ixgbe_type.h"
73 #include "base/ixgbe_phy.h"
74 #include "ixgbe_regs.h"
77 * High threshold controlling when to start sending XOFF frames. Must be at
78 * least 8 bytes less than receive packet buffer size. This value is in units
81 #define IXGBE_FC_HI 0x80
84 * Low threshold controlling when to start sending XON frames. This value is
85 * in units of 1024 bytes.
87 #define IXGBE_FC_LO 0x40
89 /* Default minimum inter-interrupt interval for EITR configuration */
90 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
92 /* Timer value included in XOFF frames. */
93 #define IXGBE_FC_PAUSE 0x680
95 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
96 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
97 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
99 #define IXGBE_MMW_SIZE_DEFAULT 0x4
100 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
101 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
104 * Default values for RX/TX configuration
106 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
107 #define IXGBE_DEFAULT_RX_PTHRESH 8
108 #define IXGBE_DEFAULT_RX_HTHRESH 8
109 #define IXGBE_DEFAULT_RX_WTHRESH 0
111 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
112 #define IXGBE_DEFAULT_TX_PTHRESH 32
113 #define IXGBE_DEFAULT_TX_HTHRESH 0
114 #define IXGBE_DEFAULT_TX_WTHRESH 0
115 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
117 /* Bit shift and mask */
118 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
119 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
120 #define IXGBE_8_BIT_WIDTH CHAR_BIT
121 #define IXGBE_8_BIT_MASK UINT8_MAX
123 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
125 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
127 #define IXGBE_HKEY_MAX_INDEX 10
129 /* Additional timesync values. */
130 #define NSEC_PER_SEC 1000000000L
131 #define IXGBE_INCVAL_10GB 0x66666666
132 #define IXGBE_INCVAL_1GB 0x40000000
133 #define IXGBE_INCVAL_100 0x50000000
134 #define IXGBE_INCVAL_SHIFT_10GB 28
135 #define IXGBE_INCVAL_SHIFT_1GB 24
136 #define IXGBE_INCVAL_SHIFT_100 21
137 #define IXGBE_INCVAL_SHIFT_82599 7
138 #define IXGBE_INCPER_SHIFT_82599 24
140 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
143 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
144 #define DEFAULT_ETAG_ETYPE 0x893f
145 #define IXGBE_ETAG_ETYPE 0x00005084
146 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
147 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
148 #define IXGBE_RAH_ADTYPE 0x40000000
149 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
150 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
151 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
152 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
153 #define IXGBE_QDE_STRIP_TAG 0x00000004
154 #define IXGBE_VTEICR_MASK 0x07
156 #define IXGBE_EXVET_VET_EXT_SHIFT 16
157 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
159 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
160 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
161 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
163 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
165 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
167 static int ixgbe_dev_start(struct rte_eth_dev *dev);
168 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
169 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
171 static void ixgbe_dev_close(struct rte_eth_dev *dev);
172 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
176 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
177 int wait_to_complete);
178 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
179 struct rte_eth_stats *stats);
180 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
181 struct rte_eth_xstat *xstats, unsigned n);
182 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
183 struct rte_eth_xstat *xstats, unsigned n);
185 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
186 uint64_t *values, unsigned int n);
187 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
188 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
189 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
190 struct rte_eth_xstat_name *xstats_names,
192 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
193 struct rte_eth_xstat_name *xstats_names, unsigned limit);
194 static int ixgbe_dev_xstats_get_names_by_id(
195 struct rte_eth_dev *dev,
196 struct rte_eth_xstat_name *xstats_names,
199 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
203 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
205 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
206 struct rte_eth_dev_info *dev_info);
207 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
208 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
209 struct rte_eth_dev_info *dev_info);
210 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
212 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
213 uint16_t vlan_id, int on);
214 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
215 enum rte_vlan_type vlan_type,
217 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
218 uint16_t queue, bool on);
219 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
221 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
222 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
223 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
225 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
227 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
229 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
230 struct rte_eth_fc_conf *fc_conf);
231 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
232 struct rte_eth_fc_conf *fc_conf);
233 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
234 struct rte_eth_pfc_conf *pfc_conf);
235 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
236 struct rte_eth_rss_reta_entry64 *reta_conf,
238 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
239 struct rte_eth_rss_reta_entry64 *reta_conf,
241 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
242 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
243 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
247 struct rte_intr_handle *handle);
248 static void ixgbe_dev_interrupt_handler(void *param);
249 static void ixgbe_dev_interrupt_delayed_handler(void *param);
250 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
251 uint32_t index, uint32_t pool);
252 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
253 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
254 struct ether_addr *mac_addr);
255 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
256 static bool is_device_supported(struct rte_eth_dev *dev,
257 struct rte_pci_driver *drv);
259 /* For Virtual Function support */
260 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
261 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
262 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
263 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
265 int wait_to_complete);
266 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
267 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
268 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
269 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
270 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
271 struct rte_eth_stats *stats);
272 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
273 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
274 uint16_t vlan_id, int on);
275 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
276 uint16_t queue, int on);
277 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
278 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
279 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
281 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
283 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
284 uint8_t queue, uint8_t msix_vector);
285 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
286 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
287 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
289 /* For Eth VMDQ APIs support */
290 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
291 ether_addr * mac_addr, uint8_t on);
292 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
293 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
294 struct rte_eth_mirror_conf *mirror_conf,
295 uint8_t rule_id, uint8_t on);
296 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
298 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
300 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
302 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
303 uint8_t queue, uint8_t msix_vector);
304 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
306 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
307 struct ether_addr *mac_addr,
308 uint32_t index, uint32_t pool);
309 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
310 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
311 struct ether_addr *mac_addr);
312 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
313 struct rte_eth_syn_filter *filter);
314 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
315 enum rte_filter_op filter_op,
317 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
318 struct ixgbe_5tuple_filter *filter);
319 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
322 enum rte_filter_op filter_op,
324 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
325 struct rte_eth_ntuple_filter *filter);
326 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
327 enum rte_filter_op filter_op,
329 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
330 struct rte_eth_ethertype_filter *filter);
331 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
332 enum rte_filter_type filter_type,
333 enum rte_filter_op filter_op,
335 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
337 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
338 struct ether_addr *mc_addr_set,
339 uint32_t nb_mc_addr);
340 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
341 struct rte_eth_dcb_info *dcb_info);
343 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
344 static int ixgbe_get_regs(struct rte_eth_dev *dev,
345 struct rte_dev_reg_info *regs);
346 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
347 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
348 struct rte_dev_eeprom_info *eeprom);
349 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
352 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
353 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
354 struct rte_dev_reg_info *regs);
356 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
357 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
358 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
359 struct timespec *timestamp,
361 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
362 struct timespec *timestamp);
363 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
364 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
365 struct timespec *timestamp);
366 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
367 const struct timespec *timestamp);
368 static void ixgbevf_dev_interrupt_handler(void *param);
370 static int ixgbe_dev_l2_tunnel_eth_type_conf
371 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
372 static int ixgbe_dev_l2_tunnel_offload_set
373 (struct rte_eth_dev *dev,
374 struct rte_eth_l2_tunnel_conf *l2_tunnel,
377 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
378 enum rte_filter_op filter_op,
381 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
382 struct rte_eth_udp_tunnel *udp_tunnel);
383 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
386 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
389 * Define VF Stats MACRO for Non "cleared on read" register
391 #define UPDATE_VF_STAT(reg, last, cur) \
393 uint32_t latest = IXGBE_READ_REG(hw, reg); \
394 cur += (latest - last) & UINT_MAX; \
398 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
400 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
401 u64 new_msb = IXGBE_READ_REG(hw, msb); \
402 u64 latest = ((new_msb << 32) | new_lsb); \
403 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
407 #define IXGBE_SET_HWSTRIP(h, q) do {\
408 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
409 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
410 (h)->bitmap[idx] |= 1 << bit;\
413 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
414 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
415 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
416 (h)->bitmap[idx] &= ~(1 << bit);\
419 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
420 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
421 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
422 (r) = (h)->bitmap[idx] >> bit & 1;\
426 * The set of PCI devices this driver supports
428 static const struct rte_pci_id pci_id_ixgbe_map[] = {
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
482 #ifdef RTE_LIBRTE_IXGBE_BYPASS
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
485 { .vendor_id = 0, /* sentinel */ },
489 * The set of PCI devices this driver supports (for 82599 VF)
491 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
492 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
493 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
502 { .vendor_id = 0, /* sentinel */ },
505 static const struct rte_eth_desc_lim rx_desc_lim = {
506 .nb_max = IXGBE_MAX_RING_DESC,
507 .nb_min = IXGBE_MIN_RING_DESC,
508 .nb_align = IXGBE_RXD_ALIGN,
511 static const struct rte_eth_desc_lim tx_desc_lim = {
512 .nb_max = IXGBE_MAX_RING_DESC,
513 .nb_min = IXGBE_MIN_RING_DESC,
514 .nb_align = IXGBE_TXD_ALIGN,
515 .nb_seg_max = IXGBE_TX_MAX_SEG,
516 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
519 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
520 .dev_configure = ixgbe_dev_configure,
521 .dev_start = ixgbe_dev_start,
522 .dev_stop = ixgbe_dev_stop,
523 .dev_set_link_up = ixgbe_dev_set_link_up,
524 .dev_set_link_down = ixgbe_dev_set_link_down,
525 .dev_close = ixgbe_dev_close,
526 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
527 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
528 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
529 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
530 .link_update = ixgbe_dev_link_update,
531 .stats_get = ixgbe_dev_stats_get,
532 .xstats_get = ixgbe_dev_xstats_get,
533 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
534 .stats_reset = ixgbe_dev_stats_reset,
535 .xstats_reset = ixgbe_dev_xstats_reset,
536 .xstats_get_names = ixgbe_dev_xstats_get_names,
537 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
538 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
539 .fw_version_get = ixgbe_fw_version_get,
540 .dev_infos_get = ixgbe_dev_info_get,
541 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
542 .mtu_set = ixgbe_dev_mtu_set,
543 .vlan_filter_set = ixgbe_vlan_filter_set,
544 .vlan_tpid_set = ixgbe_vlan_tpid_set,
545 .vlan_offload_set = ixgbe_vlan_offload_set,
546 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
547 .rx_queue_start = ixgbe_dev_rx_queue_start,
548 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
549 .tx_queue_start = ixgbe_dev_tx_queue_start,
550 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
551 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
552 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
553 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
554 .rx_queue_release = ixgbe_dev_rx_queue_release,
555 .rx_queue_count = ixgbe_dev_rx_queue_count,
556 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
557 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
558 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
559 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
560 .tx_queue_release = ixgbe_dev_tx_queue_release,
561 .dev_led_on = ixgbe_dev_led_on,
562 .dev_led_off = ixgbe_dev_led_off,
563 .flow_ctrl_get = ixgbe_flow_ctrl_get,
564 .flow_ctrl_set = ixgbe_flow_ctrl_set,
565 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
566 .mac_addr_add = ixgbe_add_rar,
567 .mac_addr_remove = ixgbe_remove_rar,
568 .mac_addr_set = ixgbe_set_default_mac_addr,
569 .uc_hash_table_set = ixgbe_uc_hash_table_set,
570 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
571 .mirror_rule_set = ixgbe_mirror_rule_set,
572 .mirror_rule_reset = ixgbe_mirror_rule_reset,
573 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
574 .reta_update = ixgbe_dev_rss_reta_update,
575 .reta_query = ixgbe_dev_rss_reta_query,
576 .rss_hash_update = ixgbe_dev_rss_hash_update,
577 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
578 .filter_ctrl = ixgbe_dev_filter_ctrl,
579 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
580 .rxq_info_get = ixgbe_rxq_info_get,
581 .txq_info_get = ixgbe_txq_info_get,
582 .timesync_enable = ixgbe_timesync_enable,
583 .timesync_disable = ixgbe_timesync_disable,
584 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
585 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
586 .get_reg = ixgbe_get_regs,
587 .get_eeprom_length = ixgbe_get_eeprom_length,
588 .get_eeprom = ixgbe_get_eeprom,
589 .set_eeprom = ixgbe_set_eeprom,
590 .get_dcb_info = ixgbe_dev_get_dcb_info,
591 .timesync_adjust_time = ixgbe_timesync_adjust_time,
592 .timesync_read_time = ixgbe_timesync_read_time,
593 .timesync_write_time = ixgbe_timesync_write_time,
594 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
595 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
596 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
597 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
598 .tm_ops_get = ixgbe_tm_ops_get,
602 * dev_ops for virtual function, bare necessities for basic vf
603 * operation have been implemented
605 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
606 .dev_configure = ixgbevf_dev_configure,
607 .dev_start = ixgbevf_dev_start,
608 .dev_stop = ixgbevf_dev_stop,
609 .link_update = ixgbevf_dev_link_update,
610 .stats_get = ixgbevf_dev_stats_get,
611 .xstats_get = ixgbevf_dev_xstats_get,
612 .stats_reset = ixgbevf_dev_stats_reset,
613 .xstats_reset = ixgbevf_dev_stats_reset,
614 .xstats_get_names = ixgbevf_dev_xstats_get_names,
615 .dev_close = ixgbevf_dev_close,
616 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
617 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
618 .dev_infos_get = ixgbevf_dev_info_get,
619 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
620 .mtu_set = ixgbevf_dev_set_mtu,
621 .vlan_filter_set = ixgbevf_vlan_filter_set,
622 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
623 .vlan_offload_set = ixgbevf_vlan_offload_set,
624 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
625 .rx_queue_release = ixgbe_dev_rx_queue_release,
626 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
627 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
628 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
629 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
630 .tx_queue_release = ixgbe_dev_tx_queue_release,
631 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
632 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
633 .mac_addr_add = ixgbevf_add_mac_addr,
634 .mac_addr_remove = ixgbevf_remove_mac_addr,
635 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
636 .rxq_info_get = ixgbe_rxq_info_get,
637 .txq_info_get = ixgbe_txq_info_get,
638 .mac_addr_set = ixgbevf_set_default_mac_addr,
639 .get_reg = ixgbevf_get_regs,
640 .reta_update = ixgbe_dev_rss_reta_update,
641 .reta_query = ixgbe_dev_rss_reta_query,
642 .rss_hash_update = ixgbe_dev_rss_hash_update,
643 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
646 /* store statistics names and its offset in stats structure */
647 struct rte_ixgbe_xstats_name_off {
648 char name[RTE_ETH_XSTATS_NAME_SIZE];
652 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
653 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
654 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
655 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
656 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
657 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
658 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
659 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
660 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
661 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
662 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
663 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
664 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
665 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
666 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
667 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
669 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
671 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
672 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
673 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
674 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
675 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
676 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
677 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
678 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
679 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
680 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
681 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
682 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
683 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
684 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
685 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
686 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
687 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
689 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
691 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
692 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
693 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
694 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
696 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
698 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
700 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
702 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
704 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
706 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
709 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
710 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
711 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
713 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
714 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
715 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
716 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
717 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
719 {"rx_fcoe_no_direct_data_placement_ext_buff",
720 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
722 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
724 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
726 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
728 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
730 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
733 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
734 sizeof(rte_ixgbe_stats_strings[0]))
736 /* MACsec statistics */
737 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
738 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
740 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
741 out_pkts_encrypted)},
742 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
743 out_pkts_protected)},
744 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
745 out_octets_encrypted)},
746 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
747 out_octets_protected)},
748 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
754 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
755 in_pkts_unknownsci)},
756 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
757 in_octets_decrypted)},
758 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
759 in_octets_validated)},
760 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
762 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
764 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
766 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
768 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
770 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
772 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
774 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
775 in_pkts_notusingsa)},
778 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
779 sizeof(rte_ixgbe_macsec_strings[0]))
781 /* Per-queue statistics */
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
783 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
784 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
785 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
786 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
789 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
790 sizeof(rte_ixgbe_rxq_strings[0]))
791 #define IXGBE_NB_RXQ_PRIO_VALUES 8
793 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
794 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
795 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
796 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
800 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
801 sizeof(rte_ixgbe_txq_strings[0]))
802 #define IXGBE_NB_TXQ_PRIO_VALUES 8
804 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
805 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
808 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
809 sizeof(rte_ixgbevf_stats_strings[0]))
812 * Atomically reads the link status information from global
813 * structure rte_eth_dev.
816 * - Pointer to the structure rte_eth_dev to read from.
817 * - Pointer to the buffer to be saved with the link status.
820 * - On success, zero.
821 * - On failure, negative value.
824 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
825 struct rte_eth_link *link)
827 struct rte_eth_link *dst = link;
828 struct rte_eth_link *src = &(dev->data->dev_link);
830 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
831 *(uint64_t *)src) == 0)
838 * Atomically writes the link status information into global
839 * structure rte_eth_dev.
842 * - Pointer to the structure rte_eth_dev to read from.
843 * - Pointer to the buffer to be saved with the link status.
846 * - On success, zero.
847 * - On failure, negative value.
850 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
851 struct rte_eth_link *link)
853 struct rte_eth_link *dst = &(dev->data->dev_link);
854 struct rte_eth_link *src = link;
856 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
857 *(uint64_t *)src) == 0)
864 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
867 ixgbe_is_sfp(struct ixgbe_hw *hw)
869 switch (hw->phy.type) {
870 case ixgbe_phy_sfp_avago:
871 case ixgbe_phy_sfp_ftl:
872 case ixgbe_phy_sfp_intel:
873 case ixgbe_phy_sfp_unknown:
874 case ixgbe_phy_sfp_passive_tyco:
875 case ixgbe_phy_sfp_passive_unknown:
882 static inline int32_t
883 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
888 status = ixgbe_reset_hw(hw);
890 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
891 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
892 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
893 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
894 IXGBE_WRITE_FLUSH(hw);
896 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
897 status = IXGBE_SUCCESS;
902 ixgbe_enable_intr(struct rte_eth_dev *dev)
904 struct ixgbe_interrupt *intr =
905 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
906 struct ixgbe_hw *hw =
907 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
909 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
910 IXGBE_WRITE_FLUSH(hw);
914 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
917 ixgbe_disable_intr(struct ixgbe_hw *hw)
919 PMD_INIT_FUNC_TRACE();
921 if (hw->mac.type == ixgbe_mac_82598EB) {
922 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
924 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
928 IXGBE_WRITE_FLUSH(hw);
932 * This function resets queue statistics mapping registers.
933 * From Niantic datasheet, Initialization of Statistics section:
934 * "...if software requires the queue counters, the RQSMR and TQSM registers
935 * must be re-programmed following a device reset.
938 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
942 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
943 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
944 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
950 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
955 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
956 #define NB_QMAP_FIELDS_PER_QSM_REG 4
957 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
959 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
960 struct ixgbe_stat_mapping_registers *stat_mappings =
961 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
962 uint32_t qsmr_mask = 0;
963 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
967 if ((hw->mac.type != ixgbe_mac_82599EB) &&
968 (hw->mac.type != ixgbe_mac_X540) &&
969 (hw->mac.type != ixgbe_mac_X550) &&
970 (hw->mac.type != ixgbe_mac_X550EM_x) &&
971 (hw->mac.type != ixgbe_mac_X550EM_a))
974 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
975 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
978 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
979 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
980 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
983 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
985 /* Now clear any previous stat_idx set */
986 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
988 stat_mappings->tqsm[n] &= ~clearing_mask;
990 stat_mappings->rqsmr[n] &= ~clearing_mask;
992 q_map = (uint32_t)stat_idx;
993 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
994 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
996 stat_mappings->tqsm[n] |= qsmr_mask;
998 stat_mappings->rqsmr[n] |= qsmr_mask;
1000 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1001 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1002 queue_id, stat_idx);
1003 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1004 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1006 /* Now write the mapping in the appropriate register */
1008 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1009 stat_mappings->rqsmr[n], n);
1010 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1012 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1013 stat_mappings->tqsm[n], n);
1014 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1020 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1022 struct ixgbe_stat_mapping_registers *stat_mappings =
1023 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1024 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 /* write whatever was in stat mapping table to the NIC */
1028 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1030 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1033 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1038 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1041 struct ixgbe_dcb_tc_config *tc;
1042 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1044 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1045 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1046 for (i = 0; i < dcb_max_tc; i++) {
1047 tc = &dcb_config->tc_config[i];
1048 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1049 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1050 (uint8_t)(100/dcb_max_tc + (i & 1));
1051 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1052 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1053 (uint8_t)(100/dcb_max_tc + (i & 1));
1054 tc->pfc = ixgbe_dcb_pfc_disabled;
1057 /* Initialize default user to priority mapping, UPx->TC0 */
1058 tc = &dcb_config->tc_config[0];
1059 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1060 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1061 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1062 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1063 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1065 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1066 dcb_config->pfc_mode_enable = false;
1067 dcb_config->vt_mode = true;
1068 dcb_config->round_robin_enable = false;
1069 /* support all DCB capabilities in 82599 */
1070 dcb_config->support.capabilities = 0xFF;
1072 /*we only support 4 Tcs for X540, X550 */
1073 if (hw->mac.type == ixgbe_mac_X540 ||
1074 hw->mac.type == ixgbe_mac_X550 ||
1075 hw->mac.type == ixgbe_mac_X550EM_x ||
1076 hw->mac.type == ixgbe_mac_X550EM_a) {
1077 dcb_config->num_tcs.pg_tcs = 4;
1078 dcb_config->num_tcs.pfc_tcs = 4;
1083 * Ensure that all locks are released before first NVM or PHY access
1086 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1091 * Phy lock should not fail in this early stage. If this is the case,
1092 * it is due to an improper exit of the application.
1093 * So force the release of the faulty lock. Release of common lock
1094 * is done automatically by swfw_sync function.
1096 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1097 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1098 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1100 ixgbe_release_swfw_semaphore(hw, mask);
1103 * These ones are more tricky since they are common to all ports; but
1104 * swfw_sync retries last long enough (1s) to be almost sure that if
1105 * lock can not be taken it is due to an improper lock of the
1108 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1109 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1110 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1112 ixgbe_release_swfw_semaphore(hw, mask);
1116 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1117 * It returns 0 on success.
1120 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1122 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1124 struct ixgbe_hw *hw =
1125 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1126 struct ixgbe_vfta *shadow_vfta =
1127 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1128 struct ixgbe_hwstrip *hwstrip =
1129 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1130 struct ixgbe_dcb_config *dcb_config =
1131 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1132 struct ixgbe_filter_info *filter_info =
1133 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1134 struct ixgbe_bw_conf *bw_conf =
1135 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1140 PMD_INIT_FUNC_TRACE();
1142 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1143 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1144 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1145 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1148 * For secondary processes, we don't initialise any further as primary
1149 * has already done this work. Only check we don't need a different
1150 * RX and TX function.
1152 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1153 struct ixgbe_tx_queue *txq;
1154 /* TX queue function in primary, set by last queue initialized
1155 * Tx queue may not initialized by primary process
1157 if (eth_dev->data->tx_queues) {
1158 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1159 ixgbe_set_tx_function(eth_dev, txq);
1161 /* Use default TX function if we get here */
1162 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1163 "Using default TX function.");
1166 ixgbe_set_rx_function(eth_dev);
1171 rte_eth_copy_pci_info(eth_dev, pci_dev);
1172 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1174 /* Vendor and Device ID need to be set before init of shared code */
1175 hw->device_id = pci_dev->id.device_id;
1176 hw->vendor_id = pci_dev->id.vendor_id;
1177 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1178 hw->allow_unsupported_sfp = 1;
1180 /* Initialize the shared code (base driver) */
1181 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1182 diag = ixgbe_bypass_init_shared_code(hw);
1184 diag = ixgbe_init_shared_code(hw);
1185 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1187 if (diag != IXGBE_SUCCESS) {
1188 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1192 /* pick up the PCI bus settings for reporting later */
1193 ixgbe_get_bus_info(hw);
1195 /* Unlock any pending hardware semaphore */
1196 ixgbe_swfw_lock_reset(hw);
1198 /* Initialize DCB configuration*/
1199 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1200 ixgbe_dcb_init(hw, dcb_config);
1201 /* Get Hardware Flow Control setting */
1202 hw->fc.requested_mode = ixgbe_fc_full;
1203 hw->fc.current_mode = ixgbe_fc_full;
1204 hw->fc.pause_time = IXGBE_FC_PAUSE;
1205 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1206 hw->fc.low_water[i] = IXGBE_FC_LO;
1207 hw->fc.high_water[i] = IXGBE_FC_HI;
1209 hw->fc.send_xon = 1;
1211 /* Make sure we have a good EEPROM before we read from it */
1212 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1213 if (diag != IXGBE_SUCCESS) {
1214 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1218 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1219 diag = ixgbe_bypass_init_hw(hw);
1221 diag = ixgbe_init_hw(hw);
1222 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1225 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1226 * is called too soon after the kernel driver unbinding/binding occurs.
1227 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1228 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1229 * also called. See ixgbe_identify_phy_82599(). The reason for the
1230 * failure is not known, and only occuts when virtualisation features
1231 * are disabled in the bios. A delay of 100ms was found to be enough by
1232 * trial-and-error, and is doubled to be safe.
1234 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1236 diag = ixgbe_init_hw(hw);
1239 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1240 diag = IXGBE_SUCCESS;
1242 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1243 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1244 "LOM. Please be aware there may be issues associated "
1245 "with your hardware.");
1246 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1247 "please contact your Intel or hardware representative "
1248 "who provided you with this hardware.");
1249 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1250 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1252 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1256 /* Reset the hw statistics */
1257 ixgbe_dev_stats_reset(eth_dev);
1259 /* disable interrupt */
1260 ixgbe_disable_intr(hw);
1262 /* reset mappings for queue statistics hw counters*/
1263 ixgbe_reset_qstat_mappings(hw);
1265 /* Allocate memory for storing MAC addresses */
1266 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1267 hw->mac.num_rar_entries, 0);
1268 if (eth_dev->data->mac_addrs == NULL) {
1270 "Failed to allocate %u bytes needed to store "
1272 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1275 /* Copy the permanent MAC address */
1276 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1277 ð_dev->data->mac_addrs[0]);
1279 /* Allocate memory for storing hash filter MAC addresses */
1280 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1281 IXGBE_VMDQ_NUM_UC_MAC, 0);
1282 if (eth_dev->data->hash_mac_addrs == NULL) {
1284 "Failed to allocate %d bytes needed to store MAC addresses",
1285 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1289 /* initialize the vfta */
1290 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1292 /* initialize the hw strip bitmap*/
1293 memset(hwstrip, 0, sizeof(*hwstrip));
1295 /* initialize PF if max_vfs not zero */
1296 ixgbe_pf_host_init(eth_dev);
1298 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1299 /* let hardware know driver is loaded */
1300 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1301 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1302 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1303 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1304 IXGBE_WRITE_FLUSH(hw);
1306 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1307 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1308 (int) hw->mac.type, (int) hw->phy.type,
1309 (int) hw->phy.sfp_type);
1311 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1312 (int) hw->mac.type, (int) hw->phy.type);
1314 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1315 eth_dev->data->port_id, pci_dev->id.vendor_id,
1316 pci_dev->id.device_id);
1318 rte_intr_callback_register(intr_handle,
1319 ixgbe_dev_interrupt_handler, eth_dev);
1321 /* enable uio/vfio intr/eventfd mapping */
1322 rte_intr_enable(intr_handle);
1324 /* enable support intr */
1325 ixgbe_enable_intr(eth_dev);
1327 /* initialize filter info */
1328 memset(filter_info, 0,
1329 sizeof(struct ixgbe_filter_info));
1331 /* initialize 5tuple filter list */
1332 TAILQ_INIT(&filter_info->fivetuple_list);
1334 /* initialize flow director filter list & hash */
1335 ixgbe_fdir_filter_init(eth_dev);
1337 /* initialize l2 tunnel filter list & hash */
1338 ixgbe_l2_tn_filter_init(eth_dev);
1340 TAILQ_INIT(&filter_ntuple_list);
1341 TAILQ_INIT(&filter_ethertype_list);
1342 TAILQ_INIT(&filter_syn_list);
1343 TAILQ_INIT(&filter_fdir_list);
1344 TAILQ_INIT(&filter_l2_tunnel_list);
1345 TAILQ_INIT(&ixgbe_flow_list);
1347 /* initialize bandwidth configuration info */
1348 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1350 /* initialize Traffic Manager configuration */
1351 ixgbe_tm_conf_init(eth_dev);
1357 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1361 struct ixgbe_hw *hw;
1363 PMD_INIT_FUNC_TRACE();
1365 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1368 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1370 if (hw->adapter_stopped == 0)
1371 ixgbe_dev_close(eth_dev);
1373 eth_dev->dev_ops = NULL;
1374 eth_dev->rx_pkt_burst = NULL;
1375 eth_dev->tx_pkt_burst = NULL;
1377 /* Unlock any pending hardware semaphore */
1378 ixgbe_swfw_lock_reset(hw);
1380 /* disable uio intr before callback unregister */
1381 rte_intr_disable(intr_handle);
1382 rte_intr_callback_unregister(intr_handle,
1383 ixgbe_dev_interrupt_handler, eth_dev);
1385 /* uninitialize PF if max_vfs not zero */
1386 ixgbe_pf_host_uninit(eth_dev);
1388 rte_free(eth_dev->data->mac_addrs);
1389 eth_dev->data->mac_addrs = NULL;
1391 rte_free(eth_dev->data->hash_mac_addrs);
1392 eth_dev->data->hash_mac_addrs = NULL;
1394 /* remove all the fdir filters & hash */
1395 ixgbe_fdir_filter_uninit(eth_dev);
1397 /* remove all the L2 tunnel filters & hash */
1398 ixgbe_l2_tn_filter_uninit(eth_dev);
1400 /* Remove all ntuple filters of the device */
1401 ixgbe_ntuple_filter_uninit(eth_dev);
1403 /* clear all the filters list */
1404 ixgbe_filterlist_flush();
1406 /* Remove all Traffic Manager configuration */
1407 ixgbe_tm_conf_uninit(eth_dev);
1412 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1414 struct ixgbe_filter_info *filter_info =
1415 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1416 struct ixgbe_5tuple_filter *p_5tuple;
1418 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1419 TAILQ_REMOVE(&filter_info->fivetuple_list,
1424 memset(filter_info->fivetuple_mask, 0,
1425 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1430 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1432 struct ixgbe_hw_fdir_info *fdir_info =
1433 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1434 struct ixgbe_fdir_filter *fdir_filter;
1436 if (fdir_info->hash_map)
1437 rte_free(fdir_info->hash_map);
1438 if (fdir_info->hash_handle)
1439 rte_hash_free(fdir_info->hash_handle);
1441 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1442 TAILQ_REMOVE(&fdir_info->fdir_list,
1445 rte_free(fdir_filter);
1451 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1453 struct ixgbe_l2_tn_info *l2_tn_info =
1454 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1455 struct ixgbe_l2_tn_filter *l2_tn_filter;
1457 if (l2_tn_info->hash_map)
1458 rte_free(l2_tn_info->hash_map);
1459 if (l2_tn_info->hash_handle)
1460 rte_hash_free(l2_tn_info->hash_handle);
1462 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1463 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1466 rte_free(l2_tn_filter);
1472 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1474 struct ixgbe_hw_fdir_info *fdir_info =
1475 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1476 char fdir_hash_name[RTE_HASH_NAMESIZE];
1477 struct rte_hash_parameters fdir_hash_params = {
1478 .name = fdir_hash_name,
1479 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1480 .key_len = sizeof(union ixgbe_atr_input),
1481 .hash_func = rte_hash_crc,
1482 .hash_func_init_val = 0,
1483 .socket_id = rte_socket_id(),
1486 TAILQ_INIT(&fdir_info->fdir_list);
1487 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1488 "fdir_%s", eth_dev->device->name);
1489 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1490 if (!fdir_info->hash_handle) {
1491 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1494 fdir_info->hash_map = rte_zmalloc("ixgbe",
1495 sizeof(struct ixgbe_fdir_filter *) *
1496 IXGBE_MAX_FDIR_FILTER_NUM,
1498 if (!fdir_info->hash_map) {
1500 "Failed to allocate memory for fdir hash map!");
1503 fdir_info->mask_added = FALSE;
1508 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1510 struct ixgbe_l2_tn_info *l2_tn_info =
1511 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1512 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1513 struct rte_hash_parameters l2_tn_hash_params = {
1514 .name = l2_tn_hash_name,
1515 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1516 .key_len = sizeof(struct ixgbe_l2_tn_key),
1517 .hash_func = rte_hash_crc,
1518 .hash_func_init_val = 0,
1519 .socket_id = rte_socket_id(),
1522 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1523 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1524 "l2_tn_%s", eth_dev->device->name);
1525 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1526 if (!l2_tn_info->hash_handle) {
1527 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1530 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1531 sizeof(struct ixgbe_l2_tn_filter *) *
1532 IXGBE_MAX_L2_TN_FILTER_NUM,
1534 if (!l2_tn_info->hash_map) {
1536 "Failed to allocate memory for L2 TN hash map!");
1539 l2_tn_info->e_tag_en = FALSE;
1540 l2_tn_info->e_tag_fwd_en = FALSE;
1541 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1546 * Negotiate mailbox API version with the PF.
1547 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1548 * Then we try to negotiate starting with the most recent one.
1549 * If all negotiation attempts fail, then we will proceed with
1550 * the default one (ixgbe_mbox_api_10).
1553 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1557 /* start with highest supported, proceed down */
1558 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1565 i != RTE_DIM(sup_ver) &&
1566 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1572 generate_random_mac_addr(struct ether_addr *mac_addr)
1576 /* Set Organizationally Unique Identifier (OUI) prefix. */
1577 mac_addr->addr_bytes[0] = 0x00;
1578 mac_addr->addr_bytes[1] = 0x09;
1579 mac_addr->addr_bytes[2] = 0xC0;
1580 /* Force indication of locally assigned MAC address. */
1581 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1582 /* Generate the last 3 bytes of the MAC address with a random number. */
1583 random = rte_rand();
1584 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1588 * Virtual Function device init
1591 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1595 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1596 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1597 struct ixgbe_hw *hw =
1598 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1599 struct ixgbe_vfta *shadow_vfta =
1600 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1601 struct ixgbe_hwstrip *hwstrip =
1602 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1603 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1605 PMD_INIT_FUNC_TRACE();
1607 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1608 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1609 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1611 /* for secondary processes, we don't initialise any further as primary
1612 * has already done this work. Only check we don't need a different
1615 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1616 struct ixgbe_tx_queue *txq;
1617 /* TX queue function in primary, set by last queue initialized
1618 * Tx queue may not initialized by primary process
1620 if (eth_dev->data->tx_queues) {
1621 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1622 ixgbe_set_tx_function(eth_dev, txq);
1624 /* Use default TX function if we get here */
1625 PMD_INIT_LOG(NOTICE,
1626 "No TX queues configured yet. Using default TX function.");
1629 ixgbe_set_rx_function(eth_dev);
1634 rte_eth_copy_pci_info(eth_dev, pci_dev);
1635 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1637 hw->device_id = pci_dev->id.device_id;
1638 hw->vendor_id = pci_dev->id.vendor_id;
1639 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1641 /* initialize the vfta */
1642 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1644 /* initialize the hw strip bitmap*/
1645 memset(hwstrip, 0, sizeof(*hwstrip));
1647 /* Initialize the shared code (base driver) */
1648 diag = ixgbe_init_shared_code(hw);
1649 if (diag != IXGBE_SUCCESS) {
1650 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1654 /* init_mailbox_params */
1655 hw->mbx.ops.init_params(hw);
1657 /* Reset the hw statistics */
1658 ixgbevf_dev_stats_reset(eth_dev);
1660 /* Disable the interrupts for VF */
1661 ixgbevf_intr_disable(hw);
1663 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1664 diag = hw->mac.ops.reset_hw(hw);
1667 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1668 * the underlying PF driver has not assigned a MAC address to the VF.
1669 * In this case, assign a random MAC address.
1671 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1672 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1676 /* negotiate mailbox API version to use with the PF. */
1677 ixgbevf_negotiate_api(hw);
1679 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1680 ixgbevf_get_queues(hw, &tcs, &tc);
1682 /* Allocate memory for storing MAC addresses */
1683 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1684 hw->mac.num_rar_entries, 0);
1685 if (eth_dev->data->mac_addrs == NULL) {
1687 "Failed to allocate %u bytes needed to store "
1689 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1693 /* Generate a random MAC address, if none was assigned by PF. */
1694 if (is_zero_ether_addr(perm_addr)) {
1695 generate_random_mac_addr(perm_addr);
1696 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1698 rte_free(eth_dev->data->mac_addrs);
1699 eth_dev->data->mac_addrs = NULL;
1702 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1703 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1704 "%02x:%02x:%02x:%02x:%02x:%02x",
1705 perm_addr->addr_bytes[0],
1706 perm_addr->addr_bytes[1],
1707 perm_addr->addr_bytes[2],
1708 perm_addr->addr_bytes[3],
1709 perm_addr->addr_bytes[4],
1710 perm_addr->addr_bytes[5]);
1713 /* Copy the permanent MAC address */
1714 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1716 /* reset the hardware with the new settings */
1717 diag = hw->mac.ops.start_hw(hw);
1723 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1727 rte_intr_callback_register(intr_handle,
1728 ixgbevf_dev_interrupt_handler, eth_dev);
1729 rte_intr_enable(intr_handle);
1730 ixgbevf_intr_enable(hw);
1732 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1733 eth_dev->data->port_id, pci_dev->id.vendor_id,
1734 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1739 /* Virtual Function device uninit */
1742 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1744 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1745 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1746 struct ixgbe_hw *hw;
1748 PMD_INIT_FUNC_TRACE();
1750 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1753 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1755 if (hw->adapter_stopped == 0)
1756 ixgbevf_dev_close(eth_dev);
1758 eth_dev->dev_ops = NULL;
1759 eth_dev->rx_pkt_burst = NULL;
1760 eth_dev->tx_pkt_burst = NULL;
1762 /* Disable the interrupts for VF */
1763 ixgbevf_intr_disable(hw);
1765 rte_free(eth_dev->data->mac_addrs);
1766 eth_dev->data->mac_addrs = NULL;
1768 rte_intr_disable(intr_handle);
1769 rte_intr_callback_unregister(intr_handle,
1770 ixgbevf_dev_interrupt_handler, eth_dev);
1775 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1776 struct rte_pci_device *pci_dev)
1778 return rte_eth_dev_pci_generic_probe(pci_dev,
1779 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1782 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1784 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1787 static struct rte_pci_driver rte_ixgbe_pmd = {
1788 .id_table = pci_id_ixgbe_map,
1789 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1790 .probe = eth_ixgbe_pci_probe,
1791 .remove = eth_ixgbe_pci_remove,
1794 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1795 struct rte_pci_device *pci_dev)
1797 return rte_eth_dev_pci_generic_probe(pci_dev,
1798 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1801 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1803 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1807 * virtual function driver struct
1809 static struct rte_pci_driver rte_ixgbevf_pmd = {
1810 .id_table = pci_id_ixgbevf_map,
1811 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1812 .probe = eth_ixgbevf_pci_probe,
1813 .remove = eth_ixgbevf_pci_remove,
1817 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1819 struct ixgbe_hw *hw =
1820 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1821 struct ixgbe_vfta *shadow_vfta =
1822 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1827 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1828 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1829 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1834 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1836 /* update local VFTA copy */
1837 shadow_vfta->vfta[vid_idx] = vfta;
1843 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1846 ixgbe_vlan_hw_strip_enable(dev, queue);
1848 ixgbe_vlan_hw_strip_disable(dev, queue);
1852 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1853 enum rte_vlan_type vlan_type,
1856 struct ixgbe_hw *hw =
1857 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1862 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1863 qinq &= IXGBE_DMATXCTL_GDV;
1865 switch (vlan_type) {
1866 case ETH_VLAN_TYPE_INNER:
1868 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1869 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1870 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1871 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1872 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1873 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1874 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1877 PMD_DRV_LOG(ERR, "Inner type is not supported"
1881 case ETH_VLAN_TYPE_OUTER:
1883 /* Only the high 16-bits is valid */
1884 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1885 IXGBE_EXVET_VET_EXT_SHIFT);
1887 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1888 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1889 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1890 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1891 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1892 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1893 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1899 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1907 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1909 struct ixgbe_hw *hw =
1910 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 PMD_INIT_FUNC_TRACE();
1915 /* Filter Table Disable */
1916 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1917 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1919 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1923 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1925 struct ixgbe_hw *hw =
1926 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1927 struct ixgbe_vfta *shadow_vfta =
1928 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1932 PMD_INIT_FUNC_TRACE();
1934 /* Filter Table Enable */
1935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1936 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1937 vlnctrl |= IXGBE_VLNCTRL_VFE;
1939 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1941 /* write whatever is in local vfta copy */
1942 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1943 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1947 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1949 struct ixgbe_hwstrip *hwstrip =
1950 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1951 struct ixgbe_rx_queue *rxq;
1953 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1957 IXGBE_SET_HWSTRIP(hwstrip, queue);
1959 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1961 if (queue >= dev->data->nb_rx_queues)
1964 rxq = dev->data->rx_queues[queue];
1967 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1969 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1973 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1975 struct ixgbe_hw *hw =
1976 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1979 PMD_INIT_FUNC_TRACE();
1981 if (hw->mac.type == ixgbe_mac_82598EB) {
1982 /* No queue level support */
1983 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1987 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1988 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1989 ctrl &= ~IXGBE_RXDCTL_VME;
1990 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1992 /* record those setting for HW strip per queue */
1993 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1997 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1999 struct ixgbe_hw *hw =
2000 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2003 PMD_INIT_FUNC_TRACE();
2005 if (hw->mac.type == ixgbe_mac_82598EB) {
2006 /* No queue level supported */
2007 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2011 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2012 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2013 ctrl |= IXGBE_RXDCTL_VME;
2014 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2016 /* record those setting for HW strip per queue */
2017 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2021 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2023 struct ixgbe_hw *hw =
2024 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2027 struct ixgbe_rx_queue *rxq;
2029 PMD_INIT_FUNC_TRACE();
2031 if (hw->mac.type == ixgbe_mac_82598EB) {
2032 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2033 ctrl &= ~IXGBE_VLNCTRL_VME;
2034 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2036 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2037 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2038 rxq = dev->data->rx_queues[i];
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2040 ctrl &= ~IXGBE_RXDCTL_VME;
2041 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2043 /* record those setting for HW strip per queue */
2044 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2050 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2052 struct ixgbe_hw *hw =
2053 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2056 struct ixgbe_rx_queue *rxq;
2058 PMD_INIT_FUNC_TRACE();
2060 if (hw->mac.type == ixgbe_mac_82598EB) {
2061 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2062 ctrl |= IXGBE_VLNCTRL_VME;
2063 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2065 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2066 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2067 rxq = dev->data->rx_queues[i];
2068 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2069 ctrl |= IXGBE_RXDCTL_VME;
2070 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2072 /* record those setting for HW strip per queue */
2073 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2079 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2081 struct ixgbe_hw *hw =
2082 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2085 PMD_INIT_FUNC_TRACE();
2087 /* DMATXCTRL: Geric Double VLAN Disable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2089 ctrl &= ~IXGBE_DMATXCTL_GDV;
2090 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2092 /* CTRL_EXT: Global Double VLAN Disable */
2093 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2094 ctrl &= ~IXGBE_EXTENDED_VLAN;
2095 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2100 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2102 struct ixgbe_hw *hw =
2103 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 PMD_INIT_FUNC_TRACE();
2108 /* DMATXCTRL: Geric Double VLAN Enable */
2109 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2110 ctrl |= IXGBE_DMATXCTL_GDV;
2111 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2113 /* CTRL_EXT: Global Double VLAN Enable */
2114 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2115 ctrl |= IXGBE_EXTENDED_VLAN;
2116 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2118 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2119 if (hw->mac.type == ixgbe_mac_X550 ||
2120 hw->mac.type == ixgbe_mac_X550EM_x ||
2121 hw->mac.type == ixgbe_mac_X550EM_a) {
2122 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2123 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2124 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2128 * VET EXT field in the EXVET register = 0x8100 by default
2129 * So no need to change. Same to VT field of DMATXCTL register
2134 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2136 if (mask & ETH_VLAN_STRIP_MASK) {
2137 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2138 ixgbe_vlan_hw_strip_enable_all(dev);
2140 ixgbe_vlan_hw_strip_disable_all(dev);
2143 if (mask & ETH_VLAN_FILTER_MASK) {
2144 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2145 ixgbe_vlan_hw_filter_enable(dev);
2147 ixgbe_vlan_hw_filter_disable(dev);
2150 if (mask & ETH_VLAN_EXTEND_MASK) {
2151 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2152 ixgbe_vlan_hw_extend_enable(dev);
2154 ixgbe_vlan_hw_extend_disable(dev);
2159 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2161 struct ixgbe_hw *hw =
2162 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2164 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2166 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2167 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2171 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2173 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2181 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2187 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2188 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2194 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2196 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2197 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2199 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2201 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2202 /* check multi-queue mode */
2203 switch (dev_conf->rxmode.mq_mode) {
2204 case ETH_MQ_RX_VMDQ_DCB:
2205 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2207 case ETH_MQ_RX_VMDQ_DCB_RSS:
2208 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2209 PMD_INIT_LOG(ERR, "SRIOV active,"
2210 " unsupported mq_mode rx %d.",
2211 dev_conf->rxmode.mq_mode);
2214 case ETH_MQ_RX_VMDQ_RSS:
2215 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2216 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2217 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2218 PMD_INIT_LOG(ERR, "SRIOV is active,"
2219 " invalid queue number"
2220 " for VMDQ RSS, allowed"
2221 " value are 1, 2 or 4.");
2225 case ETH_MQ_RX_VMDQ_ONLY:
2226 case ETH_MQ_RX_NONE:
2227 /* if nothing mq mode configure, use default scheme */
2228 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2229 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2230 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2232 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2233 /* SRIOV only works in VMDq enable mode */
2234 PMD_INIT_LOG(ERR, "SRIOV is active,"
2235 " wrong mq_mode rx %d.",
2236 dev_conf->rxmode.mq_mode);
2240 switch (dev_conf->txmode.mq_mode) {
2241 case ETH_MQ_TX_VMDQ_DCB:
2242 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2243 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2245 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2246 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2250 /* check valid queue number */
2251 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2252 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2253 PMD_INIT_LOG(ERR, "SRIOV is active,"
2254 " nb_rx_q=%d nb_tx_q=%d queue number"
2255 " must be less than or equal to %d.",
2257 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2261 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2262 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2266 /* check configuration for vmdb+dcb mode */
2267 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2268 const struct rte_eth_vmdq_dcb_conf *conf;
2270 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2271 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2272 IXGBE_VMDQ_DCB_NB_QUEUES);
2275 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2276 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2277 conf->nb_queue_pools == ETH_32_POOLS)) {
2278 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2279 " nb_queue_pools must be %d or %d.",
2280 ETH_16_POOLS, ETH_32_POOLS);
2284 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2285 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2287 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2288 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2289 IXGBE_VMDQ_DCB_NB_QUEUES);
2292 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2293 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2294 conf->nb_queue_pools == ETH_32_POOLS)) {
2295 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2296 " nb_queue_pools != %d and"
2297 " nb_queue_pools != %d.",
2298 ETH_16_POOLS, ETH_32_POOLS);
2303 /* For DCB mode check our configuration before we go further */
2304 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2305 const struct rte_eth_dcb_rx_conf *conf;
2307 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2308 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2309 IXGBE_DCB_NB_QUEUES);
2312 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2313 if (!(conf->nb_tcs == ETH_4_TCS ||
2314 conf->nb_tcs == ETH_8_TCS)) {
2315 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2316 " and nb_tcs != %d.",
2317 ETH_4_TCS, ETH_8_TCS);
2322 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2323 const struct rte_eth_dcb_tx_conf *conf;
2325 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2326 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2327 IXGBE_DCB_NB_QUEUES);
2330 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2331 if (!(conf->nb_tcs == ETH_4_TCS ||
2332 conf->nb_tcs == ETH_8_TCS)) {
2333 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2334 " and nb_tcs != %d.",
2335 ETH_4_TCS, ETH_8_TCS);
2341 * When DCB/VT is off, maximum number of queues changes,
2342 * except for 82598EB, which remains constant.
2344 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2345 hw->mac.type != ixgbe_mac_82598EB) {
2346 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2348 "Neither VT nor DCB are enabled, "
2350 IXGBE_NONE_MODE_TX_NB_QUEUES);
2359 ixgbe_dev_configure(struct rte_eth_dev *dev)
2361 struct ixgbe_interrupt *intr =
2362 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2363 struct ixgbe_adapter *adapter =
2364 (struct ixgbe_adapter *)dev->data->dev_private;
2367 PMD_INIT_FUNC_TRACE();
2368 /* multipe queue mode checking */
2369 ret = ixgbe_check_mq_mode(dev);
2371 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2376 /* set flag to update link status after init */
2377 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2380 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2381 * allocation or vector Rx preconditions we will reset it.
2383 adapter->rx_bulk_alloc_allowed = true;
2384 adapter->rx_vec_allowed = true;
2390 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2392 struct ixgbe_hw *hw =
2393 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 struct ixgbe_interrupt *intr =
2395 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2398 /* only set up it on X550EM_X */
2399 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2400 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2401 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2402 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2403 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2404 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2409 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2410 uint16_t tx_rate, uint64_t q_msk)
2412 struct ixgbe_hw *hw;
2413 struct ixgbe_vf_info *vfinfo;
2414 struct rte_eth_link link;
2415 uint8_t nb_q_per_pool;
2416 uint32_t queue_stride;
2417 uint32_t queue_idx, idx = 0, vf_idx;
2419 uint16_t total_rate = 0;
2420 struct rte_pci_device *pci_dev;
2422 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2423 rte_eth_link_get_nowait(dev->data->port_id, &link);
2425 if (vf >= pci_dev->max_vfs)
2428 if (tx_rate > link.link_speed)
2434 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2436 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2437 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2438 queue_idx = vf * queue_stride;
2439 queue_end = queue_idx + nb_q_per_pool - 1;
2440 if (queue_end >= hw->mac.max_tx_queues)
2444 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2447 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2449 total_rate += vfinfo[vf_idx].tx_rate[idx];
2455 /* Store tx_rate for this vf. */
2456 for (idx = 0; idx < nb_q_per_pool; idx++) {
2457 if (((uint64_t)0x1 << idx) & q_msk) {
2458 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2459 vfinfo[vf].tx_rate[idx] = tx_rate;
2460 total_rate += tx_rate;
2464 if (total_rate > dev->data->dev_link.link_speed) {
2465 /* Reset stored TX rate of the VF if it causes exceed
2468 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2472 /* Set RTTBCNRC of each queue/pool for vf X */
2473 for (; queue_idx <= queue_end; queue_idx++) {
2475 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2483 * Configure device link speed and setup link.
2484 * It returns 0 on success.
2487 ixgbe_dev_start(struct rte_eth_dev *dev)
2489 struct ixgbe_hw *hw =
2490 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2491 struct ixgbe_vf_info *vfinfo =
2492 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2493 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2494 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2495 uint32_t intr_vector = 0;
2496 int err, link_up = 0, negotiate = 0;
2501 uint32_t *link_speeds;
2502 struct ixgbe_tm_conf *tm_conf =
2503 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2505 PMD_INIT_FUNC_TRACE();
2507 /* IXGBE devices don't support:
2508 * - half duplex (checked afterwards for valid speeds)
2509 * - fixed speed: TODO implement
2511 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2512 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2513 dev->data->port_id);
2517 /* disable uio/vfio intr/eventfd mapping */
2518 rte_intr_disable(intr_handle);
2521 hw->adapter_stopped = 0;
2522 ixgbe_stop_adapter(hw);
2524 /* reinitialize adapter
2525 * this calls reset and start
2527 status = ixgbe_pf_reset_hw(hw);
2530 hw->mac.ops.start_hw(hw);
2531 hw->mac.get_link_status = true;
2533 /* configure PF module if SRIOV enabled */
2534 ixgbe_pf_host_configure(dev);
2536 ixgbe_dev_phy_intr_setup(dev);
2538 /* check and configure queue intr-vector mapping */
2539 if ((rte_intr_cap_multiple(intr_handle) ||
2540 !RTE_ETH_DEV_SRIOV(dev).active) &&
2541 dev->data->dev_conf.intr_conf.rxq != 0) {
2542 intr_vector = dev->data->nb_rx_queues;
2543 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2544 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2545 IXGBE_MAX_INTR_QUEUE_NUM);
2548 if (rte_intr_efd_enable(intr_handle, intr_vector))
2552 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2553 intr_handle->intr_vec =
2554 rte_zmalloc("intr_vec",
2555 dev->data->nb_rx_queues * sizeof(int), 0);
2556 if (intr_handle->intr_vec == NULL) {
2557 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2558 " intr_vec", dev->data->nb_rx_queues);
2563 /* confiugre msix for sleep until rx interrupt */
2564 ixgbe_configure_msix(dev);
2566 /* initialize transmission unit */
2567 ixgbe_dev_tx_init(dev);
2569 /* This can fail when allocating mbufs for descriptor rings */
2570 err = ixgbe_dev_rx_init(dev);
2572 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2576 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2577 ETH_VLAN_EXTEND_MASK;
2578 ixgbe_vlan_offload_set(dev, mask);
2580 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2581 /* Enable vlan filtering for VMDq */
2582 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2585 /* Configure DCB hw */
2586 ixgbe_configure_dcb(dev);
2588 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2589 err = ixgbe_fdir_configure(dev);
2594 /* Restore vf rate limit */
2595 if (vfinfo != NULL) {
2596 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2597 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2598 if (vfinfo[vf].tx_rate[idx] != 0)
2599 ixgbe_set_vf_rate_limit(
2601 vfinfo[vf].tx_rate[idx],
2605 ixgbe_restore_statistics_mapping(dev);
2607 err = ixgbe_dev_rxtx_start(dev);
2609 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2613 /* Skip link setup if loopback mode is enabled for 82599. */
2614 if (hw->mac.type == ixgbe_mac_82599EB &&
2615 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2616 goto skip_link_setup;
2618 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2619 err = hw->mac.ops.setup_sfp(hw);
2624 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2625 /* Turn on the copper */
2626 ixgbe_set_phy_power(hw, true);
2628 /* Turn on the laser */
2629 ixgbe_enable_tx_laser(hw);
2632 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2635 dev->data->dev_link.link_status = link_up;
2637 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2641 link_speeds = &dev->data->dev_conf.link_speeds;
2642 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2643 ETH_LINK_SPEED_10G)) {
2644 PMD_INIT_LOG(ERR, "Invalid link setting");
2649 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2650 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2651 IXGBE_LINK_SPEED_82599_AUTONEG :
2652 IXGBE_LINK_SPEED_82598_AUTONEG;
2654 if (*link_speeds & ETH_LINK_SPEED_10G)
2655 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2656 if (*link_speeds & ETH_LINK_SPEED_1G)
2657 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2658 if (*link_speeds & ETH_LINK_SPEED_100M)
2659 speed |= IXGBE_LINK_SPEED_100_FULL;
2662 err = ixgbe_setup_link(hw, speed, link_up);
2668 if (rte_intr_allow_others(intr_handle)) {
2669 /* check if lsc interrupt is enabled */
2670 if (dev->data->dev_conf.intr_conf.lsc != 0)
2671 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2673 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2674 ixgbe_dev_macsec_interrupt_setup(dev);
2676 rte_intr_callback_unregister(intr_handle,
2677 ixgbe_dev_interrupt_handler, dev);
2678 if (dev->data->dev_conf.intr_conf.lsc != 0)
2679 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2680 " no intr multiplex");
2683 /* check if rxq interrupt is enabled */
2684 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2685 rte_intr_dp_is_en(intr_handle))
2686 ixgbe_dev_rxq_interrupt_setup(dev);
2688 /* enable uio/vfio intr/eventfd mapping */
2689 rte_intr_enable(intr_handle);
2691 /* resume enabled intr since hw reset */
2692 ixgbe_enable_intr(dev);
2693 ixgbe_l2_tunnel_conf(dev);
2694 ixgbe_filter_restore(dev);
2696 if (tm_conf->root && !tm_conf->committed)
2697 PMD_DRV_LOG(WARNING,
2698 "please call hierarchy_commit() "
2699 "before starting the port");
2704 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2705 ixgbe_dev_clear_queues(dev);
2710 * Stop device: disable rx and tx functions to allow for reconfiguring.
2713 ixgbe_dev_stop(struct rte_eth_dev *dev)
2715 struct rte_eth_link link;
2716 struct ixgbe_hw *hw =
2717 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2718 struct ixgbe_vf_info *vfinfo =
2719 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2720 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2721 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2723 struct ixgbe_tm_conf *tm_conf =
2724 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2726 PMD_INIT_FUNC_TRACE();
2728 /* disable interrupts */
2729 ixgbe_disable_intr(hw);
2732 ixgbe_pf_reset_hw(hw);
2733 hw->adapter_stopped = 0;
2736 ixgbe_stop_adapter(hw);
2738 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2739 vfinfo[vf].clear_to_send = false;
2741 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2742 /* Turn off the copper */
2743 ixgbe_set_phy_power(hw, false);
2745 /* Turn off the laser */
2746 ixgbe_disable_tx_laser(hw);
2749 ixgbe_dev_clear_queues(dev);
2751 /* Clear stored conf */
2752 dev->data->scattered_rx = 0;
2755 /* Clear recorded link status */
2756 memset(&link, 0, sizeof(link));
2757 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2759 if (!rte_intr_allow_others(intr_handle))
2760 /* resume to the default handler */
2761 rte_intr_callback_register(intr_handle,
2762 ixgbe_dev_interrupt_handler,
2765 /* Clean datapath event and queue/vec mapping */
2766 rte_intr_efd_disable(intr_handle);
2767 if (intr_handle->intr_vec != NULL) {
2768 rte_free(intr_handle->intr_vec);
2769 intr_handle->intr_vec = NULL;
2772 /* reset hierarchy commit */
2773 tm_conf->committed = false;
2777 * Set device link up: enable tx.
2780 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2782 struct ixgbe_hw *hw =
2783 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784 if (hw->mac.type == ixgbe_mac_82599EB) {
2785 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2786 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2787 /* Not suported in bypass mode */
2788 PMD_INIT_LOG(ERR, "Set link up is not supported "
2789 "by device id 0x%x", hw->device_id);
2795 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2796 /* Turn on the copper */
2797 ixgbe_set_phy_power(hw, true);
2799 /* Turn on the laser */
2800 ixgbe_enable_tx_laser(hw);
2807 * Set device link down: disable tx.
2810 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2812 struct ixgbe_hw *hw =
2813 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814 if (hw->mac.type == ixgbe_mac_82599EB) {
2815 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2816 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2817 /* Not suported in bypass mode */
2818 PMD_INIT_LOG(ERR, "Set link down is not supported "
2819 "by device id 0x%x", hw->device_id);
2825 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2826 /* Turn off the copper */
2827 ixgbe_set_phy_power(hw, false);
2829 /* Turn off the laser */
2830 ixgbe_disable_tx_laser(hw);
2837 * Reest and stop device.
2840 ixgbe_dev_close(struct rte_eth_dev *dev)
2842 struct ixgbe_hw *hw =
2843 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2845 PMD_INIT_FUNC_TRACE();
2847 ixgbe_pf_reset_hw(hw);
2849 ixgbe_dev_stop(dev);
2850 hw->adapter_stopped = 1;
2852 ixgbe_dev_free_queues(dev);
2854 ixgbe_disable_pcie_master(hw);
2856 /* reprogram the RAR[0] in case user changed it. */
2857 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2861 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2862 struct ixgbe_hw_stats *hw_stats,
2863 struct ixgbe_macsec_stats *macsec_stats,
2864 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2865 uint64_t *total_qprc, uint64_t *total_qprdc)
2867 uint32_t bprc, lxon, lxoff, total;
2868 uint32_t delta_gprc = 0;
2870 /* Workaround for RX byte count not including CRC bytes when CRC
2871 * strip is enabled. CRC bytes are removed from counters when crc_strip
2874 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2875 IXGBE_HLREG0_RXCRCSTRP);
2877 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2878 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2879 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2880 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2882 for (i = 0; i < 8; i++) {
2883 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2885 /* global total per queue */
2886 hw_stats->mpc[i] += mp;
2887 /* Running comprehensive total for stats display */
2888 *total_missed_rx += hw_stats->mpc[i];
2889 if (hw->mac.type == ixgbe_mac_82598EB) {
2890 hw_stats->rnbc[i] +=
2891 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2892 hw_stats->pxonrxc[i] +=
2893 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2894 hw_stats->pxoffrxc[i] +=
2895 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2897 hw_stats->pxonrxc[i] +=
2898 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2899 hw_stats->pxoffrxc[i] +=
2900 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2901 hw_stats->pxon2offc[i] +=
2902 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2904 hw_stats->pxontxc[i] +=
2905 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2906 hw_stats->pxofftxc[i] +=
2907 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2909 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2910 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2911 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2912 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2914 delta_gprc += delta_qprc;
2916 hw_stats->qprc[i] += delta_qprc;
2917 hw_stats->qptc[i] += delta_qptc;
2919 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2920 hw_stats->qbrc[i] +=
2921 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2923 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2925 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2926 hw_stats->qbtc[i] +=
2927 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2929 hw_stats->qprdc[i] += delta_qprdc;
2930 *total_qprdc += hw_stats->qprdc[i];
2932 *total_qprc += hw_stats->qprc[i];
2933 *total_qbrc += hw_stats->qbrc[i];
2935 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2936 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2937 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2940 * An errata states that gprc actually counts good + missed packets:
2941 * Workaround to set gprc to summated queue packet receives
2943 hw_stats->gprc = *total_qprc;
2945 if (hw->mac.type != ixgbe_mac_82598EB) {
2946 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2947 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2948 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2949 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2950 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2951 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2952 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2953 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2955 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2956 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2957 /* 82598 only has a counter in the high register */
2958 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2959 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2960 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2962 uint64_t old_tpr = hw_stats->tpr;
2964 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2965 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2968 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2970 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2971 hw_stats->gptc += delta_gptc;
2972 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2973 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2976 * Workaround: mprc hardware is incorrectly counting
2977 * broadcasts, so for now we subtract those.
2979 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2980 hw_stats->bprc += bprc;
2981 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2982 if (hw->mac.type == ixgbe_mac_82598EB)
2983 hw_stats->mprc -= bprc;
2985 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2986 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2987 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2988 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2989 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2990 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2992 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2993 hw_stats->lxontxc += lxon;
2994 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2995 hw_stats->lxofftxc += lxoff;
2996 total = lxon + lxoff;
2998 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2999 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3000 hw_stats->gptc -= total;
3001 hw_stats->mptc -= total;
3002 hw_stats->ptc64 -= total;
3003 hw_stats->gotc -= total * ETHER_MIN_LEN;
3005 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3006 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3007 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3008 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3009 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
3010 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3011 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3012 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3013 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3014 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3015 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3016 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3017 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3018 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3019 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3020 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3021 /* Only read FCOE on 82599 */
3022 if (hw->mac.type != ixgbe_mac_82598EB) {
3023 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3024 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3025 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3026 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3027 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3030 /* Flow Director Stats registers */
3031 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3032 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3034 /* MACsec Stats registers */
3035 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3036 macsec_stats->out_pkts_encrypted +=
3037 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3038 macsec_stats->out_pkts_protected +=
3039 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3040 macsec_stats->out_octets_encrypted +=
3041 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3042 macsec_stats->out_octets_protected +=
3043 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3044 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3045 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3046 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3047 macsec_stats->in_pkts_unknownsci +=
3048 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3049 macsec_stats->in_octets_decrypted +=
3050 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3051 macsec_stats->in_octets_validated +=
3052 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3053 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3054 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3055 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3056 for (i = 0; i < 2; i++) {
3057 macsec_stats->in_pkts_ok +=
3058 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3059 macsec_stats->in_pkts_invalid +=
3060 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3061 macsec_stats->in_pkts_notvalid +=
3062 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3064 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3065 macsec_stats->in_pkts_notusingsa +=
3066 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3070 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3073 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3075 struct ixgbe_hw *hw =
3076 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3077 struct ixgbe_hw_stats *hw_stats =
3078 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3079 struct ixgbe_macsec_stats *macsec_stats =
3080 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3081 dev->data->dev_private);
3082 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3085 total_missed_rx = 0;
3090 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3091 &total_qbrc, &total_qprc, &total_qprdc);
3096 /* Fill out the rte_eth_stats statistics structure */
3097 stats->ipackets = total_qprc;
3098 stats->ibytes = total_qbrc;
3099 stats->opackets = hw_stats->gptc;
3100 stats->obytes = hw_stats->gotc;
3102 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3103 stats->q_ipackets[i] = hw_stats->qprc[i];
3104 stats->q_opackets[i] = hw_stats->qptc[i];
3105 stats->q_ibytes[i] = hw_stats->qbrc[i];
3106 stats->q_obytes[i] = hw_stats->qbtc[i];
3107 stats->q_errors[i] = hw_stats->qprdc[i];
3111 stats->imissed = total_missed_rx;
3112 stats->ierrors = hw_stats->crcerrs +
3128 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3130 struct ixgbe_hw_stats *stats =
3131 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3133 /* HW registers are cleared on read */
3134 ixgbe_dev_stats_get(dev, NULL);
3136 /* Reset software totals */
3137 memset(stats, 0, sizeof(*stats));
3140 /* This function calculates the number of xstats based on the current config */
3142 ixgbe_xstats_calc_num(void) {
3143 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3144 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3145 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3148 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3149 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3151 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3152 unsigned stat, i, count;
3154 if (xstats_names != NULL) {
3157 /* Note: limit >= cnt_stats checked upstream
3158 * in rte_eth_xstats_names()
3161 /* Extended stats from ixgbe_hw_stats */
3162 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3163 snprintf(xstats_names[count].name,
3164 sizeof(xstats_names[count].name),
3166 rte_ixgbe_stats_strings[i].name);
3171 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3172 snprintf(xstats_names[count].name,
3173 sizeof(xstats_names[count].name),
3175 rte_ixgbe_macsec_strings[i].name);
3179 /* RX Priority Stats */
3180 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3181 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3182 snprintf(xstats_names[count].name,
3183 sizeof(xstats_names[count].name),
3184 "rx_priority%u_%s", i,
3185 rte_ixgbe_rxq_strings[stat].name);
3190 /* TX Priority Stats */
3191 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3192 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3193 snprintf(xstats_names[count].name,
3194 sizeof(xstats_names[count].name),
3195 "tx_priority%u_%s", i,
3196 rte_ixgbe_txq_strings[stat].name);
3204 static int ixgbe_dev_xstats_get_names_by_id(
3205 struct rte_eth_dev *dev,
3206 struct rte_eth_xstat_name *xstats_names,
3207 const uint64_t *ids,
3211 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3212 unsigned int stat, i, count;
3214 if (xstats_names != NULL) {
3217 /* Note: limit >= cnt_stats checked upstream
3218 * in rte_eth_xstats_names()
3221 /* Extended stats from ixgbe_hw_stats */
3222 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3223 snprintf(xstats_names[count].name,
3224 sizeof(xstats_names[count].name),
3226 rte_ixgbe_stats_strings[i].name);
3231 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3232 snprintf(xstats_names[count].name,
3233 sizeof(xstats_names[count].name),
3235 rte_ixgbe_macsec_strings[i].name);
3239 /* RX Priority Stats */
3240 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3241 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3242 snprintf(xstats_names[count].name,
3243 sizeof(xstats_names[count].name),
3244 "rx_priority%u_%s", i,
3245 rte_ixgbe_rxq_strings[stat].name);
3250 /* TX Priority Stats */
3251 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3252 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3253 snprintf(xstats_names[count].name,
3254 sizeof(xstats_names[count].name),
3255 "tx_priority%u_%s", i,
3256 rte_ixgbe_txq_strings[stat].name);
3265 uint16_t size = ixgbe_xstats_calc_num();
3266 struct rte_eth_xstat_name xstats_names_copy[size];
3268 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3271 for (i = 0; i < limit; i++) {
3272 if (ids[i] >= size) {
3273 PMD_INIT_LOG(ERR, "id value isn't valid");
3276 strcpy(xstats_names[i].name,
3277 xstats_names_copy[ids[i]].name);
3282 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3283 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3287 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3290 if (xstats_names != NULL)
3291 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3292 snprintf(xstats_names[i].name,
3293 sizeof(xstats_names[i].name),
3294 "%s", rte_ixgbevf_stats_strings[i].name);
3295 return IXGBEVF_NB_XSTATS;
3299 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3302 struct ixgbe_hw *hw =
3303 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3304 struct ixgbe_hw_stats *hw_stats =
3305 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3306 struct ixgbe_macsec_stats *macsec_stats =
3307 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3308 dev->data->dev_private);
3309 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3310 unsigned i, stat, count = 0;
3312 count = ixgbe_xstats_calc_num();
3317 total_missed_rx = 0;
3322 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3323 &total_qbrc, &total_qprc, &total_qprdc);
3325 /* If this is a reset xstats is NULL, and we have cleared the
3326 * registers by reading them.
3331 /* Extended stats from ixgbe_hw_stats */
3333 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3334 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3335 rte_ixgbe_stats_strings[i].offset);
3336 xstats[count].id = count;
3341 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3342 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3343 rte_ixgbe_macsec_strings[i].offset);
3344 xstats[count].id = count;
3348 /* RX Priority Stats */
3349 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3350 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3351 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3352 rte_ixgbe_rxq_strings[stat].offset +
3353 (sizeof(uint64_t) * i));
3354 xstats[count].id = count;
3359 /* TX Priority Stats */
3360 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3361 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3362 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3363 rte_ixgbe_txq_strings[stat].offset +
3364 (sizeof(uint64_t) * i));
3365 xstats[count].id = count;
3373 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3374 uint64_t *values, unsigned int n)
3377 struct ixgbe_hw *hw =
3378 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379 struct ixgbe_hw_stats *hw_stats =
3380 IXGBE_DEV_PRIVATE_TO_STATS(
3381 dev->data->dev_private);
3382 struct ixgbe_macsec_stats *macsec_stats =
3383 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3384 dev->data->dev_private);
3385 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3386 unsigned int i, stat, count = 0;
3388 count = ixgbe_xstats_calc_num();
3390 if (!ids && n < count)
3393 total_missed_rx = 0;
3398 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3399 &total_missed_rx, &total_qbrc, &total_qprc,
3402 /* If this is a reset xstats is NULL, and we have cleared the
3403 * registers by reading them.
3405 if (!ids && !values)
3408 /* Extended stats from ixgbe_hw_stats */
3410 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3411 values[count] = *(uint64_t *)(((char *)hw_stats) +
3412 rte_ixgbe_stats_strings[i].offset);
3417 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3418 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3419 rte_ixgbe_macsec_strings[i].offset);
3423 /* RX Priority Stats */
3424 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3425 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3427 *(uint64_t *)(((char *)hw_stats) +
3428 rte_ixgbe_rxq_strings[stat].offset +
3429 (sizeof(uint64_t) * i));
3434 /* TX Priority Stats */
3435 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3436 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3438 *(uint64_t *)(((char *)hw_stats) +
3439 rte_ixgbe_txq_strings[stat].offset +
3440 (sizeof(uint64_t) * i));
3448 uint16_t size = ixgbe_xstats_calc_num();
3449 uint64_t values_copy[size];
3451 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3453 for (i = 0; i < n; i++) {
3454 if (ids[i] >= size) {
3455 PMD_INIT_LOG(ERR, "id value isn't valid");
3458 values[i] = values_copy[ids[i]];
3464 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3466 struct ixgbe_hw_stats *stats =
3467 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3468 struct ixgbe_macsec_stats *macsec_stats =
3469 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3470 dev->data->dev_private);
3472 unsigned count = ixgbe_xstats_calc_num();
3474 /* HW registers are cleared on read */
3475 ixgbe_dev_xstats_get(dev, NULL, count);
3477 /* Reset software totals */
3478 memset(stats, 0, sizeof(*stats));
3479 memset(macsec_stats, 0, sizeof(*macsec_stats));
3483 ixgbevf_update_stats(struct rte_eth_dev *dev)
3485 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3486 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3487 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3489 /* Good Rx packet, include VF loopback */
3490 UPDATE_VF_STAT(IXGBE_VFGPRC,
3491 hw_stats->last_vfgprc, hw_stats->vfgprc);
3493 /* Good Rx octets, include VF loopback */
3494 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3495 hw_stats->last_vfgorc, hw_stats->vfgorc);
3497 /* Good Tx packet, include VF loopback */
3498 UPDATE_VF_STAT(IXGBE_VFGPTC,
3499 hw_stats->last_vfgptc, hw_stats->vfgptc);
3501 /* Good Tx octets, include VF loopback */
3502 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3503 hw_stats->last_vfgotc, hw_stats->vfgotc);
3505 /* Rx Multicst Packet */
3506 UPDATE_VF_STAT(IXGBE_VFMPRC,
3507 hw_stats->last_vfmprc, hw_stats->vfmprc);
3511 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3514 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3515 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3518 if (n < IXGBEVF_NB_XSTATS)
3519 return IXGBEVF_NB_XSTATS;
3521 ixgbevf_update_stats(dev);
3526 /* Extended stats */
3527 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3529 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3530 rte_ixgbevf_stats_strings[i].offset);
3533 return IXGBEVF_NB_XSTATS;
3537 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3539 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3540 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3542 ixgbevf_update_stats(dev);
3547 stats->ipackets = hw_stats->vfgprc;
3548 stats->ibytes = hw_stats->vfgorc;
3549 stats->opackets = hw_stats->vfgptc;
3550 stats->obytes = hw_stats->vfgotc;
3554 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3556 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3557 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3559 /* Sync HW register to the last stats */
3560 ixgbevf_dev_stats_get(dev, NULL);
3562 /* reset HW current stats*/
3563 hw_stats->vfgprc = 0;
3564 hw_stats->vfgorc = 0;
3565 hw_stats->vfgptc = 0;
3566 hw_stats->vfgotc = 0;
3570 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3572 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3573 u16 eeprom_verh, eeprom_verl;
3577 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3578 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3580 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3581 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3583 ret += 1; /* add the size of '\0' */
3584 if (fw_size < (u32)ret)
3591 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3593 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3594 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3597 dev_info->pci_dev = pci_dev;
3598 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3599 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3600 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3602 * When DCB/VT is off, maximum number of queues changes,
3603 * except for 82598EB, which remains constant.
3605 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3606 hw->mac.type != ixgbe_mac_82598EB)
3607 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3609 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3610 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3611 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3612 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3613 dev_info->max_vfs = pci_dev->max_vfs;
3614 if (hw->mac.type == ixgbe_mac_82598EB)
3615 dev_info->max_vmdq_pools = ETH_16_POOLS;
3617 dev_info->max_vmdq_pools = ETH_64_POOLS;
3618 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3619 dev_info->rx_offload_capa =
3620 DEV_RX_OFFLOAD_VLAN_STRIP |
3621 DEV_RX_OFFLOAD_IPV4_CKSUM |
3622 DEV_RX_OFFLOAD_UDP_CKSUM |
3623 DEV_RX_OFFLOAD_TCP_CKSUM;
3626 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3629 if ((hw->mac.type == ixgbe_mac_82599EB ||
3630 hw->mac.type == ixgbe_mac_X540) &&
3631 !RTE_ETH_DEV_SRIOV(dev).active)
3632 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3634 if (hw->mac.type == ixgbe_mac_82599EB ||
3635 hw->mac.type == ixgbe_mac_X540)
3636 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3638 if (hw->mac.type == ixgbe_mac_X550 ||
3639 hw->mac.type == ixgbe_mac_X550EM_x ||
3640 hw->mac.type == ixgbe_mac_X550EM_a)
3641 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3643 dev_info->tx_offload_capa =
3644 DEV_TX_OFFLOAD_VLAN_INSERT |
3645 DEV_TX_OFFLOAD_IPV4_CKSUM |
3646 DEV_TX_OFFLOAD_UDP_CKSUM |
3647 DEV_TX_OFFLOAD_TCP_CKSUM |
3648 DEV_TX_OFFLOAD_SCTP_CKSUM |
3649 DEV_TX_OFFLOAD_TCP_TSO;
3651 if (hw->mac.type == ixgbe_mac_82599EB ||
3652 hw->mac.type == ixgbe_mac_X540)
3653 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3655 if (hw->mac.type == ixgbe_mac_X550 ||
3656 hw->mac.type == ixgbe_mac_X550EM_x ||
3657 hw->mac.type == ixgbe_mac_X550EM_a)
3658 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3660 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3662 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3663 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3664 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3666 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3670 dev_info->default_txconf = (struct rte_eth_txconf) {
3672 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3673 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3674 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3676 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3677 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3678 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3679 ETH_TXQ_FLAGS_NOOFFLOADS,
3682 dev_info->rx_desc_lim = rx_desc_lim;
3683 dev_info->tx_desc_lim = tx_desc_lim;
3685 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3686 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3687 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3689 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3690 if (hw->mac.type == ixgbe_mac_X540 ||
3691 hw->mac.type == ixgbe_mac_X540_vf ||
3692 hw->mac.type == ixgbe_mac_X550 ||
3693 hw->mac.type == ixgbe_mac_X550_vf) {
3694 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3698 static const uint32_t *
3699 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3701 static const uint32_t ptypes[] = {
3702 /* For non-vec functions,
3703 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3704 * for vec functions,
3705 * refers to _recv_raw_pkts_vec().
3709 RTE_PTYPE_L3_IPV4_EXT,
3711 RTE_PTYPE_L3_IPV6_EXT,
3715 RTE_PTYPE_TUNNEL_IP,
3716 RTE_PTYPE_INNER_L3_IPV6,
3717 RTE_PTYPE_INNER_L3_IPV6_EXT,
3718 RTE_PTYPE_INNER_L4_TCP,
3719 RTE_PTYPE_INNER_L4_UDP,
3723 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3724 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3725 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3726 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3729 #if defined(RTE_ARCH_X86)
3730 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3731 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3738 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3739 struct rte_eth_dev_info *dev_info)
3741 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3742 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3744 dev_info->pci_dev = pci_dev;
3745 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3746 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3747 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3748 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3749 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3750 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3751 dev_info->max_vfs = pci_dev->max_vfs;
3752 if (hw->mac.type == ixgbe_mac_82598EB)
3753 dev_info->max_vmdq_pools = ETH_16_POOLS;
3755 dev_info->max_vmdq_pools = ETH_64_POOLS;
3756 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3757 DEV_RX_OFFLOAD_IPV4_CKSUM |
3758 DEV_RX_OFFLOAD_UDP_CKSUM |
3759 DEV_RX_OFFLOAD_TCP_CKSUM;
3760 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3761 DEV_TX_OFFLOAD_IPV4_CKSUM |
3762 DEV_TX_OFFLOAD_UDP_CKSUM |
3763 DEV_TX_OFFLOAD_TCP_CKSUM |
3764 DEV_TX_OFFLOAD_SCTP_CKSUM |
3765 DEV_TX_OFFLOAD_TCP_TSO;
3767 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3769 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3770 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3771 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3773 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3777 dev_info->default_txconf = (struct rte_eth_txconf) {
3779 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3780 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3781 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3783 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3784 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3785 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3786 ETH_TXQ_FLAGS_NOOFFLOADS,
3789 dev_info->rx_desc_lim = rx_desc_lim;
3790 dev_info->tx_desc_lim = tx_desc_lim;
3794 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3795 int *link_up, int wait_to_complete)
3798 * for a quick link status checking, wait_to_compelet == 0,
3799 * skip PF link status checking
3801 bool no_pflink_check = wait_to_complete == 0;
3802 struct ixgbe_mbx_info *mbx = &hw->mbx;
3803 struct ixgbe_mac_info *mac = &hw->mac;
3804 uint32_t links_reg, in_msg;
3807 /* If we were hit with a reset drop the link */
3808 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3809 mac->get_link_status = true;
3811 if (!mac->get_link_status)
3814 /* if link status is down no point in checking to see if pf is up */
3815 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3816 if (!(links_reg & IXGBE_LINKS_UP))
3819 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3820 * before the link status is correct
3822 if (mac->type == ixgbe_mac_82599_vf) {
3825 for (i = 0; i < 5; i++) {
3827 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3829 if (!(links_reg & IXGBE_LINKS_UP))
3834 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3835 case IXGBE_LINKS_SPEED_10G_82599:
3836 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3837 if (hw->mac.type >= ixgbe_mac_X550) {
3838 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3839 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3842 case IXGBE_LINKS_SPEED_1G_82599:
3843 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3845 case IXGBE_LINKS_SPEED_100_82599:
3846 *speed = IXGBE_LINK_SPEED_100_FULL;
3847 if (hw->mac.type == ixgbe_mac_X550) {
3848 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3849 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3852 case IXGBE_LINKS_SPEED_10_X550EM_A:
3853 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3854 /* Since Reserved in older MAC's */
3855 if (hw->mac.type >= ixgbe_mac_X550)
3856 *speed = IXGBE_LINK_SPEED_10_FULL;
3859 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3862 if (no_pflink_check) {
3863 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3864 mac->get_link_status = true;
3866 mac->get_link_status = false;
3870 /* if the read failed it could just be a mailbox collision, best wait
3871 * until we are called again and don't report an error
3873 if (mbx->ops.read(hw, &in_msg, 1, 0))
3876 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3877 /* msg is not CTS and is NACK we must have lost CTS status */
3878 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3883 /* the pf is talking, if we timed out in the past we reinit */
3884 if (!mbx->timeout) {
3889 /* if we passed all the tests above then the link is up and we no
3890 * longer need to check for link
3892 mac->get_link_status = false;
3895 *link_up = !mac->get_link_status;
3899 /* return 0 means link status changed, -1 means not changed */
3901 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3902 int wait_to_complete, int vf)
3904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3905 struct rte_eth_link link, old;
3906 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3907 struct ixgbe_interrupt *intr =
3908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3913 bool autoneg = false;
3915 link.link_status = ETH_LINK_DOWN;
3916 link.link_speed = 0;
3917 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3918 memset(&old, 0, sizeof(old));
3919 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3921 hw->mac.get_link_status = true;
3923 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3924 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3925 speed = hw->phy.autoneg_advertised;
3927 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3928 ixgbe_setup_link(hw, speed, true);
3931 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3932 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3936 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3938 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3941 link.link_speed = ETH_SPEED_NUM_100M;
3942 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3943 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3944 if (link.link_status == old.link_status)
3950 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3951 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3952 if (link.link_status == old.link_status)
3956 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3957 link.link_status = ETH_LINK_UP;
3958 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3960 switch (link_speed) {
3962 case IXGBE_LINK_SPEED_UNKNOWN:
3963 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3964 link.link_speed = ETH_SPEED_NUM_100M;
3967 case IXGBE_LINK_SPEED_100_FULL:
3968 link.link_speed = ETH_SPEED_NUM_100M;
3971 case IXGBE_LINK_SPEED_1GB_FULL:
3972 link.link_speed = ETH_SPEED_NUM_1G;
3975 case IXGBE_LINK_SPEED_10GB_FULL:
3976 link.link_speed = ETH_SPEED_NUM_10G;
3979 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3981 if (link.link_status == old.link_status)
3988 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3990 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3994 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3996 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
4000 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
4002 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4006 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4007 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4011 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
4013 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4016 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4017 fctrl &= (~IXGBE_FCTRL_UPE);
4018 if (dev->data->all_multicast == 1)
4019 fctrl |= IXGBE_FCTRL_MPE;
4021 fctrl &= (~IXGBE_FCTRL_MPE);
4022 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4026 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4028 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4031 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4032 fctrl |= IXGBE_FCTRL_MPE;
4033 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4037 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4039 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4042 if (dev->data->promiscuous == 1)
4043 return; /* must remain in all_multicast mode */
4045 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4046 fctrl &= (~IXGBE_FCTRL_MPE);
4047 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4051 * It clears the interrupt causes and enables the interrupt.
4052 * It will be called once only during nic initialized.
4055 * Pointer to struct rte_eth_dev.
4057 * Enable or Disable.
4060 * - On success, zero.
4061 * - On failure, a negative value.
4064 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4066 struct ixgbe_interrupt *intr =
4067 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4069 ixgbe_dev_link_status_print(dev);
4071 intr->mask |= IXGBE_EICR_LSC;
4073 intr->mask &= ~IXGBE_EICR_LSC;
4079 * It clears the interrupt causes and enables the interrupt.
4080 * It will be called once only during nic initialized.
4083 * Pointer to struct rte_eth_dev.
4086 * - On success, zero.
4087 * - On failure, a negative value.
4090 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4092 struct ixgbe_interrupt *intr =
4093 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4095 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4101 * It clears the interrupt causes and enables the interrupt.
4102 * It will be called once only during nic initialized.
4105 * Pointer to struct rte_eth_dev.
4108 * - On success, zero.
4109 * - On failure, a negative value.
4112 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4114 struct ixgbe_interrupt *intr =
4115 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4117 intr->mask |= IXGBE_EICR_LINKSEC;
4123 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4126 * Pointer to struct rte_eth_dev.
4129 * - On success, zero.
4130 * - On failure, a negative value.
4133 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4136 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4137 struct ixgbe_interrupt *intr =
4138 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4140 /* clear all cause mask */
4141 ixgbe_disable_intr(hw);
4143 /* read-on-clear nic registers here */
4144 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4145 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4149 /* set flag for async link update */
4150 if (eicr & IXGBE_EICR_LSC)
4151 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4153 if (eicr & IXGBE_EICR_MAILBOX)
4154 intr->flags |= IXGBE_FLAG_MAILBOX;
4156 if (eicr & IXGBE_EICR_LINKSEC)
4157 intr->flags |= IXGBE_FLAG_MACSEC;
4159 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4160 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4161 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4162 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4168 * It gets and then prints the link status.
4171 * Pointer to struct rte_eth_dev.
4174 * - On success, zero.
4175 * - On failure, a negative value.
4178 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4180 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4181 struct rte_eth_link link;
4183 memset(&link, 0, sizeof(link));
4184 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4185 if (link.link_status) {
4186 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4187 (int)(dev->data->port_id),
4188 (unsigned)link.link_speed,
4189 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4190 "full-duplex" : "half-duplex");
4192 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4193 (int)(dev->data->port_id));
4195 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4196 pci_dev->addr.domain,
4198 pci_dev->addr.devid,
4199 pci_dev->addr.function);
4203 * It executes link_update after knowing an interrupt occurred.
4206 * Pointer to struct rte_eth_dev.
4209 * - On success, zero.
4210 * - On failure, a negative value.
4213 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4214 struct rte_intr_handle *intr_handle)
4216 struct ixgbe_interrupt *intr =
4217 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4219 struct rte_eth_link link;
4220 struct ixgbe_hw *hw =
4221 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4223 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4225 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4226 ixgbe_pf_mbx_process(dev);
4227 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4230 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4231 ixgbe_handle_lasi(hw);
4232 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4235 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4236 /* get the link status before link update, for predicting later */
4237 memset(&link, 0, sizeof(link));
4238 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4240 ixgbe_dev_link_update(dev, 0);
4243 if (!link.link_status)
4244 /* handle it 1 sec later, wait it being stable */
4245 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4246 /* likely to down */
4248 /* handle it 4 sec later, wait it being stable */
4249 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4251 ixgbe_dev_link_status_print(dev);
4252 if (rte_eal_alarm_set(timeout * 1000,
4253 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4254 PMD_DRV_LOG(ERR, "Error setting alarm");
4256 /* remember original mask */
4257 intr->mask_original = intr->mask;
4258 /* only disable lsc interrupt */
4259 intr->mask &= ~IXGBE_EIMS_LSC;
4263 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4264 ixgbe_enable_intr(dev);
4265 rte_intr_enable(intr_handle);
4271 * Interrupt handler which shall be registered for alarm callback for delayed
4272 * handling specific interrupt to wait for the stable nic state. As the
4273 * NIC interrupt state is not stable for ixgbe after link is just down,
4274 * it needs to wait 4 seconds to get the stable status.
4277 * Pointer to interrupt handle.
4279 * The address of parameter (struct rte_eth_dev *) regsitered before.
4285 ixgbe_dev_interrupt_delayed_handler(void *param)
4287 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4288 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4289 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4290 struct ixgbe_interrupt *intr =
4291 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4292 struct ixgbe_hw *hw =
4293 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4296 ixgbe_disable_intr(hw);
4298 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4299 if (eicr & IXGBE_EICR_MAILBOX)
4300 ixgbe_pf_mbx_process(dev);
4302 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4303 ixgbe_handle_lasi(hw);
4304 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4307 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4308 ixgbe_dev_link_update(dev, 0);
4309 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4310 ixgbe_dev_link_status_print(dev);
4311 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4315 if (intr->flags & IXGBE_FLAG_MACSEC) {
4316 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4318 intr->flags &= ~IXGBE_FLAG_MACSEC;
4321 /* restore original mask */
4322 intr->mask = intr->mask_original;
4323 intr->mask_original = 0;
4325 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4326 ixgbe_enable_intr(dev);
4327 rte_intr_enable(intr_handle);
4331 * Interrupt handler triggered by NIC for handling
4332 * specific interrupt.
4335 * Pointer to interrupt handle.
4337 * The address of parameter (struct rte_eth_dev *) regsitered before.
4343 ixgbe_dev_interrupt_handler(void *param)
4345 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4347 ixgbe_dev_interrupt_get_status(dev);
4348 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4352 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4354 struct ixgbe_hw *hw;
4356 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4357 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4361 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4363 struct ixgbe_hw *hw;
4365 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4366 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4370 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4372 struct ixgbe_hw *hw;
4378 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380 fc_conf->pause_time = hw->fc.pause_time;
4381 fc_conf->high_water = hw->fc.high_water[0];
4382 fc_conf->low_water = hw->fc.low_water[0];
4383 fc_conf->send_xon = hw->fc.send_xon;
4384 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4387 * Return rx_pause status according to actual setting of
4390 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4391 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4397 * Return tx_pause status according to actual setting of
4400 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4401 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4406 if (rx_pause && tx_pause)
4407 fc_conf->mode = RTE_FC_FULL;
4409 fc_conf->mode = RTE_FC_RX_PAUSE;
4411 fc_conf->mode = RTE_FC_TX_PAUSE;
4413 fc_conf->mode = RTE_FC_NONE;
4419 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4421 struct ixgbe_hw *hw;
4423 uint32_t rx_buf_size;
4424 uint32_t max_high_water;
4426 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4433 PMD_INIT_FUNC_TRACE();
4435 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4436 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4437 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4440 * At least reserve one Ethernet frame for watermark
4441 * high_water/low_water in kilo bytes for ixgbe
4443 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4444 if ((fc_conf->high_water > max_high_water) ||
4445 (fc_conf->high_water < fc_conf->low_water)) {
4446 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4447 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4451 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4452 hw->fc.pause_time = fc_conf->pause_time;
4453 hw->fc.high_water[0] = fc_conf->high_water;
4454 hw->fc.low_water[0] = fc_conf->low_water;
4455 hw->fc.send_xon = fc_conf->send_xon;
4456 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4458 err = ixgbe_fc_enable(hw);
4460 /* Not negotiated is not an error case */
4461 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4463 /* check if we want to forward MAC frames - driver doesn't have native
4464 * capability to do that, so we'll write the registers ourselves */
4466 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4468 /* set or clear MFLCN.PMCF bit depending on configuration */
4469 if (fc_conf->mac_ctrl_frame_fwd != 0)
4470 mflcn |= IXGBE_MFLCN_PMCF;
4472 mflcn &= ~IXGBE_MFLCN_PMCF;
4474 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4475 IXGBE_WRITE_FLUSH(hw);
4480 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4485 * ixgbe_pfc_enable_generic - Enable flow control
4486 * @hw: pointer to hardware structure
4487 * @tc_num: traffic class number
4488 * Enable flow control according to the current settings.
4491 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4494 uint32_t mflcn_reg, fccfg_reg;
4496 uint32_t fcrtl, fcrth;
4500 /* Validate the water mark configuration */
4501 if (!hw->fc.pause_time) {
4502 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4506 /* Low water mark of zero causes XOFF floods */
4507 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4508 /* High/Low water can not be 0 */
4509 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4510 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4511 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4515 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4516 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4517 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4521 /* Negotiate the fc mode to use */
4522 ixgbe_fc_autoneg(hw);
4524 /* Disable any previous flow control settings */
4525 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4526 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4528 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4529 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4531 switch (hw->fc.current_mode) {
4534 * If the count of enabled RX Priority Flow control >1,
4535 * and the TX pause can not be disabled
4538 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4539 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4540 if (reg & IXGBE_FCRTH_FCEN)
4544 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4546 case ixgbe_fc_rx_pause:
4548 * Rx Flow control is enabled and Tx Flow control is
4549 * disabled by software override. Since there really
4550 * isn't a way to advertise that we are capable of RX
4551 * Pause ONLY, we will advertise that we support both
4552 * symmetric and asymmetric Rx PAUSE. Later, we will
4553 * disable the adapter's ability to send PAUSE frames.
4555 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4557 * If the count of enabled RX Priority Flow control >1,
4558 * and the TX pause can not be disabled
4561 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4562 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4563 if (reg & IXGBE_FCRTH_FCEN)
4567 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4569 case ixgbe_fc_tx_pause:
4571 * Tx Flow control is enabled, and Rx Flow control is
4572 * disabled by software override.
4574 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4577 /* Flow control (both Rx and Tx) is enabled by SW override. */
4578 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4579 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4582 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4583 ret_val = IXGBE_ERR_CONFIG;
4587 /* Set 802.3x based flow control settings. */
4588 mflcn_reg |= IXGBE_MFLCN_DPF;
4589 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4590 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4592 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4593 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4594 hw->fc.high_water[tc_num]) {
4595 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4596 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4597 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4599 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4601 * In order to prevent Tx hangs when the internal Tx
4602 * switch is enabled we must set the high water mark
4603 * to the maximum FCRTH value. This allows the Tx
4604 * switch to function even under heavy Rx workloads.
4606 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4608 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4610 /* Configure pause time (2 TCs per register) */
4611 reg = hw->fc.pause_time * 0x00010001;
4612 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4613 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4615 /* Configure flow control refresh threshold value */
4616 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4623 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4625 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4626 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4628 if (hw->mac.type != ixgbe_mac_82598EB) {
4629 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4635 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4638 uint32_t rx_buf_size;
4639 uint32_t max_high_water;
4641 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4642 struct ixgbe_hw *hw =
4643 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4644 struct ixgbe_dcb_config *dcb_config =
4645 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4647 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4654 PMD_INIT_FUNC_TRACE();
4656 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4657 tc_num = map[pfc_conf->priority];
4658 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4659 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4661 * At least reserve one Ethernet frame for watermark
4662 * high_water/low_water in kilo bytes for ixgbe
4664 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4665 if ((pfc_conf->fc.high_water > max_high_water) ||
4666 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4667 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4668 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4672 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4673 hw->fc.pause_time = pfc_conf->fc.pause_time;
4674 hw->fc.send_xon = pfc_conf->fc.send_xon;
4675 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4676 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4678 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4680 /* Not negotiated is not an error case */
4681 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4684 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4689 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4690 struct rte_eth_rss_reta_entry64 *reta_conf,
4693 uint16_t i, sp_reta_size;
4696 uint16_t idx, shift;
4697 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4700 PMD_INIT_FUNC_TRACE();
4702 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4703 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4708 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4709 if (reta_size != sp_reta_size) {
4710 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4711 "(%d) doesn't match the number hardware can supported "
4712 "(%d)", reta_size, sp_reta_size);
4716 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4717 idx = i / RTE_RETA_GROUP_SIZE;
4718 shift = i % RTE_RETA_GROUP_SIZE;
4719 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4723 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4724 if (mask == IXGBE_4_BIT_MASK)
4727 r = IXGBE_READ_REG(hw, reta_reg);
4728 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4729 if (mask & (0x1 << j))
4730 reta |= reta_conf[idx].reta[shift + j] <<
4733 reta |= r & (IXGBE_8_BIT_MASK <<
4736 IXGBE_WRITE_REG(hw, reta_reg, reta);
4743 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4744 struct rte_eth_rss_reta_entry64 *reta_conf,
4747 uint16_t i, sp_reta_size;
4750 uint16_t idx, shift;
4751 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4754 PMD_INIT_FUNC_TRACE();
4755 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4756 if (reta_size != sp_reta_size) {
4757 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4758 "(%d) doesn't match the number hardware can supported "
4759 "(%d)", reta_size, sp_reta_size);
4763 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4764 idx = i / RTE_RETA_GROUP_SIZE;
4765 shift = i % RTE_RETA_GROUP_SIZE;
4766 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4771 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4772 reta = IXGBE_READ_REG(hw, reta_reg);
4773 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4774 if (mask & (0x1 << j))
4775 reta_conf[idx].reta[shift + j] =
4776 ((reta >> (CHAR_BIT * j)) &
4785 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4786 uint32_t index, uint32_t pool)
4788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4789 uint32_t enable_addr = 1;
4791 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4796 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4798 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4800 ixgbe_clear_rar(hw, index);
4804 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4806 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4808 ixgbe_remove_rar(dev, 0);
4810 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4814 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4816 if (strcmp(dev->device->driver->name, drv->driver.name))
4823 is_ixgbe_supported(struct rte_eth_dev *dev)
4825 return is_device_supported(dev, &rte_ixgbe_pmd);
4829 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4833 struct ixgbe_hw *hw;
4834 struct rte_eth_dev_info dev_info;
4835 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4836 struct rte_eth_dev_data *dev_data = dev->data;
4838 ixgbe_dev_info_get(dev, &dev_info);
4840 /* check that mtu is within the allowed range */
4841 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4844 /* If device is started, refuse mtu that requires the support of
4845 * scattered packets when this feature has not been enabled before.
4847 if (dev_data->dev_started && !dev_data->scattered_rx &&
4848 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4849 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4850 PMD_INIT_LOG(ERR, "Stop port first.");
4854 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4855 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4857 /* switch to jumbo mode if needed */
4858 if (frame_size > ETHER_MAX_LEN) {
4859 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4860 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4862 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4863 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4865 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4867 /* update max frame size */
4868 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4870 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4871 maxfrs &= 0x0000FFFF;
4872 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4873 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4879 * Virtual Function operations
4882 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4884 PMD_INIT_FUNC_TRACE();
4886 /* Clear interrupt mask to stop from interrupts being generated */
4887 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4889 IXGBE_WRITE_FLUSH(hw);
4893 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4895 PMD_INIT_FUNC_TRACE();
4897 /* VF enable interrupt autoclean */
4898 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4899 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4900 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4902 IXGBE_WRITE_FLUSH(hw);
4906 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4908 struct rte_eth_conf *conf = &dev->data->dev_conf;
4909 struct ixgbe_adapter *adapter =
4910 (struct ixgbe_adapter *)dev->data->dev_private;
4912 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4913 dev->data->port_id);
4916 * VF has no ability to enable/disable HW CRC
4917 * Keep the persistent behavior the same as Host PF
4919 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4920 if (!conf->rxmode.hw_strip_crc) {
4921 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4922 conf->rxmode.hw_strip_crc = 1;
4925 if (conf->rxmode.hw_strip_crc) {
4926 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4927 conf->rxmode.hw_strip_crc = 0;
4932 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4933 * allocation or vector Rx preconditions we will reset it.
4935 adapter->rx_bulk_alloc_allowed = true;
4936 adapter->rx_vec_allowed = true;
4942 ixgbevf_dev_start(struct rte_eth_dev *dev)
4944 struct ixgbe_hw *hw =
4945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4946 uint32_t intr_vector = 0;
4947 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4948 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4952 PMD_INIT_FUNC_TRACE();
4954 hw->mac.ops.reset_hw(hw);
4955 hw->mac.get_link_status = true;
4957 /* negotiate mailbox API version to use with the PF. */
4958 ixgbevf_negotiate_api(hw);
4960 ixgbevf_dev_tx_init(dev);
4962 /* This can fail when allocating mbufs for descriptor rings */
4963 err = ixgbevf_dev_rx_init(dev);
4965 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4966 ixgbe_dev_clear_queues(dev);
4971 ixgbevf_set_vfta_all(dev, 1);
4974 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4975 ETH_VLAN_EXTEND_MASK;
4976 ixgbevf_vlan_offload_set(dev, mask);
4978 ixgbevf_dev_rxtx_start(dev);
4980 /* check and configure queue intr-vector mapping */
4981 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4982 intr_vector = dev->data->nb_rx_queues;
4983 if (rte_intr_efd_enable(intr_handle, intr_vector))
4987 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4988 intr_handle->intr_vec =
4989 rte_zmalloc("intr_vec",
4990 dev->data->nb_rx_queues * sizeof(int), 0);
4991 if (intr_handle->intr_vec == NULL) {
4992 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4993 " intr_vec", dev->data->nb_rx_queues);
4997 ixgbevf_configure_msix(dev);
4999 rte_intr_enable(intr_handle);
5001 /* Re-enable interrupt for VF */
5002 ixgbevf_intr_enable(hw);
5008 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5011 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5012 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5014 PMD_INIT_FUNC_TRACE();
5016 ixgbevf_intr_disable(hw);
5018 hw->adapter_stopped = 1;
5019 ixgbe_stop_adapter(hw);
5022 * Clear what we set, but we still keep shadow_vfta to
5023 * restore after device starts
5025 ixgbevf_set_vfta_all(dev, 0);
5027 /* Clear stored conf */
5028 dev->data->scattered_rx = 0;
5030 ixgbe_dev_clear_queues(dev);
5032 /* Clean datapath event and queue/vec mapping */
5033 rte_intr_efd_disable(intr_handle);
5034 if (intr_handle->intr_vec != NULL) {
5035 rte_free(intr_handle->intr_vec);
5036 intr_handle->intr_vec = NULL;
5041 ixgbevf_dev_close(struct rte_eth_dev *dev)
5043 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045 PMD_INIT_FUNC_TRACE();
5049 ixgbevf_dev_stop(dev);
5051 ixgbe_dev_free_queues(dev);
5054 * Remove the VF MAC address ro ensure
5055 * that the VF traffic goes to the PF
5056 * after stop, close and detach of the VF
5058 ixgbevf_remove_mac_addr(dev, 0);
5061 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5063 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5064 struct ixgbe_vfta *shadow_vfta =
5065 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5066 int i = 0, j = 0, vfta = 0, mask = 1;
5068 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5069 vfta = shadow_vfta->vfta[i];
5072 for (j = 0; j < 32; j++) {
5074 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5084 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5086 struct ixgbe_hw *hw =
5087 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5088 struct ixgbe_vfta *shadow_vfta =
5089 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5090 uint32_t vid_idx = 0;
5091 uint32_t vid_bit = 0;
5094 PMD_INIT_FUNC_TRACE();
5096 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5097 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5099 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5102 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5103 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5105 /* Save what we set and retore it after device reset */
5107 shadow_vfta->vfta[vid_idx] |= vid_bit;
5109 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5115 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5117 struct ixgbe_hw *hw =
5118 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121 PMD_INIT_FUNC_TRACE();
5123 if (queue >= hw->mac.max_rx_queues)
5126 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5128 ctrl |= IXGBE_RXDCTL_VME;
5130 ctrl &= ~IXGBE_RXDCTL_VME;
5131 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5133 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5137 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5139 struct ixgbe_hw *hw =
5140 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5144 /* VF function only support hw strip feature, others are not support */
5145 if (mask & ETH_VLAN_STRIP_MASK) {
5146 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
5148 for (i = 0; i < hw->mac.max_rx_queues; i++)
5149 ixgbevf_vlan_strip_queue_set(dev, i, on);
5154 ixgbe_vt_check(struct ixgbe_hw *hw)
5158 /* if Virtualization Technology is enabled */
5159 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5160 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5161 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5169 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5171 uint32_t vector = 0;
5173 switch (hw->mac.mc_filter_type) {
5174 case 0: /* use bits [47:36] of the address */
5175 vector = ((uc_addr->addr_bytes[4] >> 4) |
5176 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5178 case 1: /* use bits [46:35] of the address */
5179 vector = ((uc_addr->addr_bytes[4] >> 3) |
5180 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5182 case 2: /* use bits [45:34] of the address */
5183 vector = ((uc_addr->addr_bytes[4] >> 2) |
5184 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5186 case 3: /* use bits [43:32] of the address */
5187 vector = ((uc_addr->addr_bytes[4]) |
5188 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5190 default: /* Invalid mc_filter_type */
5194 /* vector can only be 12-bits or boundary will be exceeded */
5200 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5208 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5209 const uint32_t ixgbe_uta_bit_shift = 5;
5210 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5211 const uint32_t bit1 = 0x1;
5213 struct ixgbe_hw *hw =
5214 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5215 struct ixgbe_uta_info *uta_info =
5216 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5218 /* The UTA table only exists on 82599 hardware and newer */
5219 if (hw->mac.type < ixgbe_mac_82599EB)
5222 vector = ixgbe_uta_vector(hw, mac_addr);
5223 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5224 uta_shift = vector & ixgbe_uta_bit_mask;
5226 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5230 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5232 uta_info->uta_in_use++;
5233 reg_val |= (bit1 << uta_shift);
5234 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5236 uta_info->uta_in_use--;
5237 reg_val &= ~(bit1 << uta_shift);
5238 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5241 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5243 if (uta_info->uta_in_use > 0)
5244 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5245 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5247 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5253 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5256 struct ixgbe_hw *hw =
5257 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5258 struct ixgbe_uta_info *uta_info =
5259 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5261 /* The UTA table only exists on 82599 hardware and newer */
5262 if (hw->mac.type < ixgbe_mac_82599EB)
5266 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5267 uta_info->uta_shadow[i] = ~0;
5268 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5271 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5272 uta_info->uta_shadow[i] = 0;
5273 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5281 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5283 uint32_t new_val = orig_val;
5285 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5286 new_val |= IXGBE_VMOLR_AUPE;
5287 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5288 new_val |= IXGBE_VMOLR_ROMPE;
5289 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5290 new_val |= IXGBE_VMOLR_ROPE;
5291 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5292 new_val |= IXGBE_VMOLR_BAM;
5293 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5294 new_val |= IXGBE_VMOLR_MPE;
5299 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5300 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5301 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5302 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5303 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5304 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5305 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5308 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5309 struct rte_eth_mirror_conf *mirror_conf,
5310 uint8_t rule_id, uint8_t on)
5312 uint32_t mr_ctl, vlvf;
5313 uint32_t mp_lsb = 0;
5314 uint32_t mv_msb = 0;
5315 uint32_t mv_lsb = 0;
5316 uint32_t mp_msb = 0;
5319 uint64_t vlan_mask = 0;
5321 const uint8_t pool_mask_offset = 32;
5322 const uint8_t vlan_mask_offset = 32;
5323 const uint8_t dst_pool_offset = 8;
5324 const uint8_t rule_mr_offset = 4;
5325 const uint8_t mirror_rule_mask = 0x0F;
5327 struct ixgbe_mirror_info *mr_info =
5328 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5329 struct ixgbe_hw *hw =
5330 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5331 uint8_t mirror_type = 0;
5333 if (ixgbe_vt_check(hw) < 0)
5336 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5339 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5340 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5341 mirror_conf->rule_type);
5345 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5346 mirror_type |= IXGBE_MRCTL_VLME;
5347 /* Check if vlan id is valid and find conresponding VLAN ID
5350 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5351 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5352 /* search vlan id related pool vlan filter
5355 reg_index = ixgbe_find_vlvf_slot(
5357 mirror_conf->vlan.vlan_id[i],
5361 vlvf = IXGBE_READ_REG(hw,
5362 IXGBE_VLVF(reg_index));
5363 if ((vlvf & IXGBE_VLVF_VIEN) &&
5364 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5365 mirror_conf->vlan.vlan_id[i]))
5366 vlan_mask |= (1ULL << reg_index);
5373 mv_lsb = vlan_mask & 0xFFFFFFFF;
5374 mv_msb = vlan_mask >> vlan_mask_offset;
5376 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5377 mirror_conf->vlan.vlan_mask;
5378 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5379 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5380 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5381 mirror_conf->vlan.vlan_id[i];
5386 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5387 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5388 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5393 * if enable pool mirror, write related pool mask register,if disable
5394 * pool mirror, clear PFMRVM register
5396 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5397 mirror_type |= IXGBE_MRCTL_VPME;
5399 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5400 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5401 mr_info->mr_conf[rule_id].pool_mask =
5402 mirror_conf->pool_mask;
5407 mr_info->mr_conf[rule_id].pool_mask = 0;
5410 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5411 mirror_type |= IXGBE_MRCTL_UPME;
5412 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5413 mirror_type |= IXGBE_MRCTL_DPME;
5415 /* read mirror control register and recalculate it */
5416 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5419 mr_ctl |= mirror_type;
5420 mr_ctl &= mirror_rule_mask;
5421 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5423 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5426 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5427 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5429 /* write mirrror control register */
5430 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5432 /* write pool mirrror control register */
5433 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5434 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5435 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5438 /* write VLAN mirrror control register */
5439 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5440 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5441 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5449 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5452 uint32_t lsb_val = 0;
5453 uint32_t msb_val = 0;
5454 const uint8_t rule_mr_offset = 4;
5456 struct ixgbe_hw *hw =
5457 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5458 struct ixgbe_mirror_info *mr_info =
5459 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5461 if (ixgbe_vt_check(hw) < 0)
5464 memset(&mr_info->mr_conf[rule_id], 0,
5465 sizeof(struct rte_eth_mirror_conf));
5467 /* clear PFVMCTL register */
5468 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5470 /* clear pool mask register */
5471 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5472 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5474 /* clear vlan mask register */
5475 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5476 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5482 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5484 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5485 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5487 struct ixgbe_hw *hw =
5488 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5491 mask |= (1 << IXGBE_MISC_VEC_ID);
5492 RTE_SET_USED(queue_id);
5493 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5495 rte_intr_enable(intr_handle);
5501 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5504 struct ixgbe_hw *hw =
5505 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5507 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5508 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5509 RTE_SET_USED(queue_id);
5510 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5516 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5518 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5519 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5521 struct ixgbe_hw *hw =
5522 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5523 struct ixgbe_interrupt *intr =
5524 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5526 if (queue_id < 16) {
5527 ixgbe_disable_intr(hw);
5528 intr->mask |= (1 << queue_id);
5529 ixgbe_enable_intr(dev);
5530 } else if (queue_id < 32) {
5531 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5532 mask &= (1 << queue_id);
5533 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5534 } else if (queue_id < 64) {
5535 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5536 mask &= (1 << (queue_id - 32));
5537 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5539 rte_intr_enable(intr_handle);
5545 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5548 struct ixgbe_hw *hw =
5549 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5550 struct ixgbe_interrupt *intr =
5551 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5553 if (queue_id < 16) {
5554 ixgbe_disable_intr(hw);
5555 intr->mask &= ~(1 << queue_id);
5556 ixgbe_enable_intr(dev);
5557 } else if (queue_id < 32) {
5558 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5559 mask &= ~(1 << queue_id);
5560 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5561 } else if (queue_id < 64) {
5562 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5563 mask &= ~(1 << (queue_id - 32));
5564 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5571 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5572 uint8_t queue, uint8_t msix_vector)
5576 if (direction == -1) {
5578 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5579 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5582 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5584 /* rx or tx cause */
5585 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5586 idx = ((16 * (queue & 1)) + (8 * direction));
5587 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5588 tmp &= ~(0xFF << idx);
5589 tmp |= (msix_vector << idx);
5590 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5595 * set the IVAR registers, mapping interrupt causes to vectors
5597 * pointer to ixgbe_hw struct
5599 * 0 for Rx, 1 for Tx, -1 for other causes
5601 * queue to map the corresponding interrupt to
5603 * the vector to map to the corresponding queue
5606 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5607 uint8_t queue, uint8_t msix_vector)
5611 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5612 if (hw->mac.type == ixgbe_mac_82598EB) {
5613 if (direction == -1)
5615 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5616 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5617 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5618 tmp |= (msix_vector << (8 * (queue & 0x3)));
5619 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5620 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5621 (hw->mac.type == ixgbe_mac_X540) ||
5622 (hw->mac.type == ixgbe_mac_X550)) {
5623 if (direction == -1) {
5625 idx = ((queue & 1) * 8);
5626 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5627 tmp &= ~(0xFF << idx);
5628 tmp |= (msix_vector << idx);
5629 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5631 /* rx or tx causes */
5632 idx = ((16 * (queue & 1)) + (8 * direction));
5633 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5634 tmp &= ~(0xFF << idx);
5635 tmp |= (msix_vector << idx);
5636 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5642 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5644 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5645 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5646 struct ixgbe_hw *hw =
5647 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5649 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5651 /* Configure VF other cause ivar */
5652 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5654 /* won't configure msix register if no mapping is done
5655 * between intr vector and event fd.
5657 if (!rte_intr_dp_is_en(intr_handle))
5660 /* Configure all RX queues of VF */
5661 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5662 /* Force all queue use vector 0,
5663 * as IXGBE_VF_MAXMSIVECOTR = 1
5665 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5666 intr_handle->intr_vec[q_idx] = vector_idx;
5671 * Sets up the hardware to properly generate MSI-X interrupts
5673 * board private structure
5676 ixgbe_configure_msix(struct rte_eth_dev *dev)
5678 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5679 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5680 struct ixgbe_hw *hw =
5681 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5682 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5683 uint32_t vec = IXGBE_MISC_VEC_ID;
5687 /* won't configure msix register if no mapping is done
5688 * between intr vector and event fd
5690 if (!rte_intr_dp_is_en(intr_handle))
5693 if (rte_intr_allow_others(intr_handle))
5694 vec = base = IXGBE_RX_VEC_START;
5696 /* setup GPIE for MSI-x mode */
5697 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5698 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5699 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5700 /* auto clearing and auto setting corresponding bits in EIMS
5701 * when MSI-X interrupt is triggered
5703 if (hw->mac.type == ixgbe_mac_82598EB) {
5704 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5706 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5707 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5709 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5711 /* Populate the IVAR table and set the ITR values to the
5712 * corresponding register.
5714 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5716 /* by default, 1:1 mapping */
5717 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5718 intr_handle->intr_vec[queue_id] = vec;
5719 if (vec < base + intr_handle->nb_efd - 1)
5723 switch (hw->mac.type) {
5724 case ixgbe_mac_82598EB:
5725 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5728 case ixgbe_mac_82599EB:
5729 case ixgbe_mac_X540:
5730 case ixgbe_mac_X550:
5731 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5736 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5737 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5739 /* set up to autoclear timer, and the vectors */
5740 mask = IXGBE_EIMS_ENABLE_MASK;
5741 mask &= ~(IXGBE_EIMS_OTHER |
5742 IXGBE_EIMS_MAILBOX |
5745 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5749 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5750 uint16_t queue_idx, uint16_t tx_rate)
5752 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5753 uint32_t rf_dec, rf_int;
5755 uint16_t link_speed = dev->data->dev_link.link_speed;
5757 if (queue_idx >= hw->mac.max_tx_queues)
5761 /* Calculate the rate factor values to set */
5762 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5763 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5764 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5766 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5767 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5768 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5769 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5775 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5776 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5779 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5780 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5781 IXGBE_MAX_JUMBO_FRAME_SIZE))
5782 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5783 IXGBE_MMW_SIZE_JUMBO_FRAME);
5785 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5786 IXGBE_MMW_SIZE_DEFAULT);
5788 /* Set RTTBCNRC of queue X */
5789 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5790 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5791 IXGBE_WRITE_FLUSH(hw);
5797 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5798 __attribute__((unused)) uint32_t index,
5799 __attribute__((unused)) uint32_t pool)
5801 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5805 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5806 * operation. Trap this case to avoid exhausting the [very limited]
5807 * set of PF resources used to store VF MAC addresses.
5809 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5811 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5813 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5814 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5815 mac_addr->addr_bytes[0],
5816 mac_addr->addr_bytes[1],
5817 mac_addr->addr_bytes[2],
5818 mac_addr->addr_bytes[3],
5819 mac_addr->addr_bytes[4],
5820 mac_addr->addr_bytes[5],
5826 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5828 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5829 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5830 struct ether_addr *mac_addr;
5835 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5836 * not support the deletion of a given MAC address.
5837 * Instead, it imposes to delete all MAC addresses, then to add again
5838 * all MAC addresses with the exception of the one to be deleted.
5840 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5843 * Add again all MAC addresses, with the exception of the deleted one
5844 * and of the permanent MAC address.
5846 for (i = 0, mac_addr = dev->data->mac_addrs;
5847 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5848 /* Skip the deleted MAC address */
5851 /* Skip NULL MAC addresses */
5852 if (is_zero_ether_addr(mac_addr))
5854 /* Skip the permanent MAC address */
5855 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5857 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5860 "Adding again MAC address "
5861 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5863 mac_addr->addr_bytes[0],
5864 mac_addr->addr_bytes[1],
5865 mac_addr->addr_bytes[2],
5866 mac_addr->addr_bytes[3],
5867 mac_addr->addr_bytes[4],
5868 mac_addr->addr_bytes[5],
5874 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5878 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5882 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5883 struct rte_eth_syn_filter *filter,
5886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5887 struct ixgbe_filter_info *filter_info =
5888 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5892 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5895 syn_info = filter_info->syn_info;
5898 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5900 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5901 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5903 if (filter->hig_pri)
5904 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5906 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5908 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5909 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5911 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5914 filter_info->syn_info = synqf;
5915 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5916 IXGBE_WRITE_FLUSH(hw);
5921 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5922 struct rte_eth_syn_filter *filter)
5924 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5925 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5927 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5928 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5929 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5936 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5937 enum rte_filter_op filter_op,
5940 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943 MAC_TYPE_FILTER_SUP(hw->mac.type);
5945 if (filter_op == RTE_ETH_FILTER_NOP)
5949 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5954 switch (filter_op) {
5955 case RTE_ETH_FILTER_ADD:
5956 ret = ixgbe_syn_filter_set(dev,
5957 (struct rte_eth_syn_filter *)arg,
5960 case RTE_ETH_FILTER_DELETE:
5961 ret = ixgbe_syn_filter_set(dev,
5962 (struct rte_eth_syn_filter *)arg,
5965 case RTE_ETH_FILTER_GET:
5966 ret = ixgbe_syn_filter_get(dev,
5967 (struct rte_eth_syn_filter *)arg);
5970 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5979 static inline enum ixgbe_5tuple_protocol
5980 convert_protocol_type(uint8_t protocol_value)
5982 if (protocol_value == IPPROTO_TCP)
5983 return IXGBE_FILTER_PROTOCOL_TCP;
5984 else if (protocol_value == IPPROTO_UDP)
5985 return IXGBE_FILTER_PROTOCOL_UDP;
5986 else if (protocol_value == IPPROTO_SCTP)
5987 return IXGBE_FILTER_PROTOCOL_SCTP;
5989 return IXGBE_FILTER_PROTOCOL_NONE;
5992 /* inject a 5-tuple filter to HW */
5994 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5995 struct ixgbe_5tuple_filter *filter)
5997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5999 uint32_t ftqf, sdpqf;
6000 uint32_t l34timir = 0;
6001 uint8_t mask = 0xff;
6005 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6006 IXGBE_SDPQF_DSTPORT_SHIFT);
6007 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6009 ftqf = (uint32_t)(filter->filter_info.proto &
6010 IXGBE_FTQF_PROTOCOL_MASK);
6011 ftqf |= (uint32_t)((filter->filter_info.priority &
6012 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6013 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6014 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6015 if (filter->filter_info.dst_ip_mask == 0)
6016 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6017 if (filter->filter_info.src_port_mask == 0)
6018 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6019 if (filter->filter_info.dst_port_mask == 0)
6020 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6021 if (filter->filter_info.proto_mask == 0)
6022 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6023 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6024 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6025 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6027 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6028 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6029 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6030 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6032 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6033 l34timir |= (uint32_t)(filter->queue <<
6034 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6035 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6039 * add a 5tuple filter
6042 * dev: Pointer to struct rte_eth_dev.
6043 * index: the index the filter allocates.
6044 * filter: ponter to the filter that will be added.
6045 * rx_queue: the queue id the filter assigned to.
6048 * - On success, zero.
6049 * - On failure, a negative value.
6052 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6053 struct ixgbe_5tuple_filter *filter)
6055 struct ixgbe_filter_info *filter_info =
6056 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6060 * look for an unused 5tuple filter index,
6061 * and insert the filter to list.
6063 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6064 idx = i / (sizeof(uint32_t) * NBBY);
6065 shift = i % (sizeof(uint32_t) * NBBY);
6066 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6067 filter_info->fivetuple_mask[idx] |= 1 << shift;
6069 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6075 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6076 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6080 ixgbe_inject_5tuple_filter(dev, filter);
6086 * remove a 5tuple filter
6089 * dev: Pointer to struct rte_eth_dev.
6090 * filter: the pointer of the filter will be removed.
6093 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6094 struct ixgbe_5tuple_filter *filter)
6096 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097 struct ixgbe_filter_info *filter_info =
6098 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6099 uint16_t index = filter->index;
6101 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6102 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6103 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6106 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6107 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6108 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6109 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6110 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6114 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6116 struct ixgbe_hw *hw;
6117 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6118 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6120 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6122 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6125 /* refuse mtu that requires the support of scattered packets when this
6126 * feature has not been enabled before.
6128 if (!rx_conf->enable_scatter &&
6129 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6130 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6134 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6135 * request of the version 2.0 of the mailbox API.
6136 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6137 * of the mailbox API.
6138 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6139 * prior to 3.11.33 which contains the following change:
6140 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6142 ixgbevf_rlpml_set_vf(hw, max_frame);
6144 /* update max frame size */
6145 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6149 static inline struct ixgbe_5tuple_filter *
6150 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6151 struct ixgbe_5tuple_filter_info *key)
6153 struct ixgbe_5tuple_filter *it;
6155 TAILQ_FOREACH(it, filter_list, entries) {
6156 if (memcmp(key, &it->filter_info,
6157 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6164 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6166 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6167 struct ixgbe_5tuple_filter_info *filter_info)
6169 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6170 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6171 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6174 switch (filter->dst_ip_mask) {
6176 filter_info->dst_ip_mask = 0;
6177 filter_info->dst_ip = filter->dst_ip;
6180 filter_info->dst_ip_mask = 1;
6183 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6187 switch (filter->src_ip_mask) {
6189 filter_info->src_ip_mask = 0;
6190 filter_info->src_ip = filter->src_ip;
6193 filter_info->src_ip_mask = 1;
6196 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6200 switch (filter->dst_port_mask) {
6202 filter_info->dst_port_mask = 0;
6203 filter_info->dst_port = filter->dst_port;
6206 filter_info->dst_port_mask = 1;
6209 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6213 switch (filter->src_port_mask) {
6215 filter_info->src_port_mask = 0;
6216 filter_info->src_port = filter->src_port;
6219 filter_info->src_port_mask = 1;
6222 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6226 switch (filter->proto_mask) {
6228 filter_info->proto_mask = 0;
6229 filter_info->proto =
6230 convert_protocol_type(filter->proto);
6233 filter_info->proto_mask = 1;
6236 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6240 filter_info->priority = (uint8_t)filter->priority;
6245 * add or delete a ntuple filter
6248 * dev: Pointer to struct rte_eth_dev.
6249 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6250 * add: if true, add filter, if false, remove filter
6253 * - On success, zero.
6254 * - On failure, a negative value.
6257 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6258 struct rte_eth_ntuple_filter *ntuple_filter,
6261 struct ixgbe_filter_info *filter_info =
6262 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6263 struct ixgbe_5tuple_filter_info filter_5tuple;
6264 struct ixgbe_5tuple_filter *filter;
6267 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6268 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6272 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6273 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6277 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6279 if (filter != NULL && add) {
6280 PMD_DRV_LOG(ERR, "filter exists.");
6283 if (filter == NULL && !add) {
6284 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6289 filter = rte_zmalloc("ixgbe_5tuple_filter",
6290 sizeof(struct ixgbe_5tuple_filter), 0);
6293 (void)rte_memcpy(&filter->filter_info,
6295 sizeof(struct ixgbe_5tuple_filter_info));
6296 filter->queue = ntuple_filter->queue;
6297 ret = ixgbe_add_5tuple_filter(dev, filter);
6303 ixgbe_remove_5tuple_filter(dev, filter);
6309 * get a ntuple filter
6312 * dev: Pointer to struct rte_eth_dev.
6313 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6316 * - On success, zero.
6317 * - On failure, a negative value.
6320 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6321 struct rte_eth_ntuple_filter *ntuple_filter)
6323 struct ixgbe_filter_info *filter_info =
6324 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6325 struct ixgbe_5tuple_filter_info filter_5tuple;
6326 struct ixgbe_5tuple_filter *filter;
6329 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6330 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6334 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6335 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6339 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6341 if (filter == NULL) {
6342 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6345 ntuple_filter->queue = filter->queue;
6350 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6351 * @dev: pointer to rte_eth_dev structure
6352 * @filter_op:operation will be taken.
6353 * @arg: a pointer to specific structure corresponding to the filter_op
6356 * - On success, zero.
6357 * - On failure, a negative value.
6360 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6361 enum rte_filter_op filter_op,
6364 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6367 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6369 if (filter_op == RTE_ETH_FILTER_NOP)
6373 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6378 switch (filter_op) {
6379 case RTE_ETH_FILTER_ADD:
6380 ret = ixgbe_add_del_ntuple_filter(dev,
6381 (struct rte_eth_ntuple_filter *)arg,
6384 case RTE_ETH_FILTER_DELETE:
6385 ret = ixgbe_add_del_ntuple_filter(dev,
6386 (struct rte_eth_ntuple_filter *)arg,
6389 case RTE_ETH_FILTER_GET:
6390 ret = ixgbe_get_ntuple_filter(dev,
6391 (struct rte_eth_ntuple_filter *)arg);
6394 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6402 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6403 struct rte_eth_ethertype_filter *filter,
6406 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6407 struct ixgbe_filter_info *filter_info =
6408 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6412 struct ixgbe_ethertype_filter ethertype_filter;
6414 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6417 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6418 filter->ether_type == ETHER_TYPE_IPv6) {
6419 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6420 " ethertype filter.", filter->ether_type);
6424 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6425 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6428 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6429 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6433 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6434 if (ret >= 0 && add) {
6435 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6436 filter->ether_type);
6439 if (ret < 0 && !add) {
6440 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6441 filter->ether_type);
6446 etqf = IXGBE_ETQF_FILTER_EN;
6447 etqf |= (uint32_t)filter->ether_type;
6448 etqs |= (uint32_t)((filter->queue <<
6449 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6450 IXGBE_ETQS_RX_QUEUE);
6451 etqs |= IXGBE_ETQS_QUEUE_EN;
6453 ethertype_filter.ethertype = filter->ether_type;
6454 ethertype_filter.etqf = etqf;
6455 ethertype_filter.etqs = etqs;
6456 ethertype_filter.conf = FALSE;
6457 ret = ixgbe_ethertype_filter_insert(filter_info,
6460 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6464 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6468 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6469 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6470 IXGBE_WRITE_FLUSH(hw);
6476 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6477 struct rte_eth_ethertype_filter *filter)
6479 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6480 struct ixgbe_filter_info *filter_info =
6481 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6482 uint32_t etqf, etqs;
6485 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6487 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6488 filter->ether_type);
6492 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6493 if (etqf & IXGBE_ETQF_FILTER_EN) {
6494 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6495 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6497 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6498 IXGBE_ETQS_RX_QUEUE_SHIFT;
6505 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6506 * @dev: pointer to rte_eth_dev structure
6507 * @filter_op:operation will be taken.
6508 * @arg: a pointer to specific structure corresponding to the filter_op
6511 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6512 enum rte_filter_op filter_op,
6515 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518 MAC_TYPE_FILTER_SUP(hw->mac.type);
6520 if (filter_op == RTE_ETH_FILTER_NOP)
6524 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6529 switch (filter_op) {
6530 case RTE_ETH_FILTER_ADD:
6531 ret = ixgbe_add_del_ethertype_filter(dev,
6532 (struct rte_eth_ethertype_filter *)arg,
6535 case RTE_ETH_FILTER_DELETE:
6536 ret = ixgbe_add_del_ethertype_filter(dev,
6537 (struct rte_eth_ethertype_filter *)arg,
6540 case RTE_ETH_FILTER_GET:
6541 ret = ixgbe_get_ethertype_filter(dev,
6542 (struct rte_eth_ethertype_filter *)arg);
6545 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6553 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6554 enum rte_filter_type filter_type,
6555 enum rte_filter_op filter_op,
6560 switch (filter_type) {
6561 case RTE_ETH_FILTER_NTUPLE:
6562 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6564 case RTE_ETH_FILTER_ETHERTYPE:
6565 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6567 case RTE_ETH_FILTER_SYN:
6568 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6570 case RTE_ETH_FILTER_FDIR:
6571 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6573 case RTE_ETH_FILTER_L2_TUNNEL:
6574 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6576 case RTE_ETH_FILTER_GENERIC:
6577 if (filter_op != RTE_ETH_FILTER_GET)
6579 *(const void **)arg = &ixgbe_flow_ops;
6582 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6592 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6593 u8 **mc_addr_ptr, u32 *vmdq)
6598 mc_addr = *mc_addr_ptr;
6599 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6604 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6605 struct ether_addr *mc_addr_set,
6606 uint32_t nb_mc_addr)
6608 struct ixgbe_hw *hw;
6611 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6612 mc_addr_list = (u8 *)mc_addr_set;
6613 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6614 ixgbe_dev_addr_list_itr, TRUE);
6618 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6620 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6621 uint64_t systime_cycles;
6623 switch (hw->mac.type) {
6624 case ixgbe_mac_X550:
6625 case ixgbe_mac_X550EM_x:
6626 case ixgbe_mac_X550EM_a:
6627 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6628 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6629 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6633 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6634 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6638 return systime_cycles;
6642 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6644 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6645 uint64_t rx_tstamp_cycles;
6647 switch (hw->mac.type) {
6648 case ixgbe_mac_X550:
6649 case ixgbe_mac_X550EM_x:
6650 case ixgbe_mac_X550EM_a:
6651 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6652 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6653 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6657 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6658 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6659 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6663 return rx_tstamp_cycles;
6667 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6669 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6670 uint64_t tx_tstamp_cycles;
6672 switch (hw->mac.type) {
6673 case ixgbe_mac_X550:
6674 case ixgbe_mac_X550EM_x:
6675 case ixgbe_mac_X550EM_a:
6676 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6677 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6678 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6682 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6683 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6684 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6688 return tx_tstamp_cycles;
6692 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6694 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6695 struct ixgbe_adapter *adapter =
6696 (struct ixgbe_adapter *)dev->data->dev_private;
6697 struct rte_eth_link link;
6698 uint32_t incval = 0;
6701 /* Get current link speed. */
6702 memset(&link, 0, sizeof(link));
6703 ixgbe_dev_link_update(dev, 1);
6704 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6706 switch (link.link_speed) {
6707 case ETH_SPEED_NUM_100M:
6708 incval = IXGBE_INCVAL_100;
6709 shift = IXGBE_INCVAL_SHIFT_100;
6711 case ETH_SPEED_NUM_1G:
6712 incval = IXGBE_INCVAL_1GB;
6713 shift = IXGBE_INCVAL_SHIFT_1GB;
6715 case ETH_SPEED_NUM_10G:
6717 incval = IXGBE_INCVAL_10GB;
6718 shift = IXGBE_INCVAL_SHIFT_10GB;
6722 switch (hw->mac.type) {
6723 case ixgbe_mac_X550:
6724 case ixgbe_mac_X550EM_x:
6725 case ixgbe_mac_X550EM_a:
6726 /* Independent of link speed. */
6728 /* Cycles read will be interpreted as ns. */
6731 case ixgbe_mac_X540:
6732 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6734 case ixgbe_mac_82599EB:
6735 incval >>= IXGBE_INCVAL_SHIFT_82599;
6736 shift -= IXGBE_INCVAL_SHIFT_82599;
6737 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6738 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6741 /* Not supported. */
6745 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6746 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6747 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6749 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6750 adapter->systime_tc.cc_shift = shift;
6751 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6753 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6754 adapter->rx_tstamp_tc.cc_shift = shift;
6755 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6757 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6758 adapter->tx_tstamp_tc.cc_shift = shift;
6759 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6763 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6765 struct ixgbe_adapter *adapter =
6766 (struct ixgbe_adapter *)dev->data->dev_private;
6768 adapter->systime_tc.nsec += delta;
6769 adapter->rx_tstamp_tc.nsec += delta;
6770 adapter->tx_tstamp_tc.nsec += delta;
6776 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6779 struct ixgbe_adapter *adapter =
6780 (struct ixgbe_adapter *)dev->data->dev_private;
6782 ns = rte_timespec_to_ns(ts);
6783 /* Set the timecounters to a new value. */
6784 adapter->systime_tc.nsec = ns;
6785 adapter->rx_tstamp_tc.nsec = ns;
6786 adapter->tx_tstamp_tc.nsec = ns;
6792 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6794 uint64_t ns, systime_cycles;
6795 struct ixgbe_adapter *adapter =
6796 (struct ixgbe_adapter *)dev->data->dev_private;
6798 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6799 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6800 *ts = rte_ns_to_timespec(ns);
6806 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6808 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6812 /* Stop the timesync system time. */
6813 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6814 /* Reset the timesync system time value. */
6815 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6816 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6818 /* Enable system time for platforms where it isn't on by default. */
6819 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6820 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6821 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6823 ixgbe_start_timecounters(dev);
6825 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6826 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6828 IXGBE_ETQF_FILTER_EN |
6831 /* Enable timestamping of received PTP packets. */
6832 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6833 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6834 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6836 /* Enable timestamping of transmitted PTP packets. */
6837 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6838 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6839 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6841 IXGBE_WRITE_FLUSH(hw);
6847 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6849 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6852 /* Disable timestamping of transmitted PTP packets. */
6853 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6854 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6855 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6857 /* Disable timestamping of received PTP packets. */
6858 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6859 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6860 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6862 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6863 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6865 /* Stop incrementating the System Time registers. */
6866 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6872 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6873 struct timespec *timestamp,
6874 uint32_t flags __rte_unused)
6876 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6877 struct ixgbe_adapter *adapter =
6878 (struct ixgbe_adapter *)dev->data->dev_private;
6879 uint32_t tsync_rxctl;
6880 uint64_t rx_tstamp_cycles;
6883 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6884 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6887 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6888 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6889 *timestamp = rte_ns_to_timespec(ns);
6895 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6896 struct timespec *timestamp)
6898 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6899 struct ixgbe_adapter *adapter =
6900 (struct ixgbe_adapter *)dev->data->dev_private;
6901 uint32_t tsync_txctl;
6902 uint64_t tx_tstamp_cycles;
6905 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6906 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6909 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6910 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6911 *timestamp = rte_ns_to_timespec(ns);
6917 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6919 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6922 const struct reg_info *reg_group;
6923 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6924 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6926 while ((reg_group = reg_set[g_ind++]))
6927 count += ixgbe_regs_group_count(reg_group);
6933 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6937 const struct reg_info *reg_group;
6939 while ((reg_group = ixgbevf_regs[g_ind++]))
6940 count += ixgbe_regs_group_count(reg_group);
6946 ixgbe_get_regs(struct rte_eth_dev *dev,
6947 struct rte_dev_reg_info *regs)
6949 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6950 uint32_t *data = regs->data;
6953 const struct reg_info *reg_group;
6954 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6955 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6958 regs->length = ixgbe_get_reg_length(dev);
6959 regs->width = sizeof(uint32_t);
6963 /* Support only full register dump */
6964 if ((regs->length == 0) ||
6965 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6966 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6968 while ((reg_group = reg_set[g_ind++]))
6969 count += ixgbe_read_regs_group(dev, &data[count],
6978 ixgbevf_get_regs(struct rte_eth_dev *dev,
6979 struct rte_dev_reg_info *regs)
6981 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6982 uint32_t *data = regs->data;
6985 const struct reg_info *reg_group;
6988 regs->length = ixgbevf_get_reg_length(dev);
6989 regs->width = sizeof(uint32_t);
6993 /* Support only full register dump */
6994 if ((regs->length == 0) ||
6995 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6996 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6998 while ((reg_group = ixgbevf_regs[g_ind++]))
6999 count += ixgbe_read_regs_group(dev, &data[count],
7008 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7010 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7012 /* Return unit is byte count */
7013 return hw->eeprom.word_size * 2;
7017 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7018 struct rte_dev_eeprom_info *in_eeprom)
7020 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7021 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7022 uint16_t *data = in_eeprom->data;
7025 first = in_eeprom->offset >> 1;
7026 length = in_eeprom->length >> 1;
7027 if ((first > hw->eeprom.word_size) ||
7028 ((first + length) > hw->eeprom.word_size))
7031 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7033 return eeprom->ops.read_buffer(hw, first, length, data);
7037 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7038 struct rte_dev_eeprom_info *in_eeprom)
7040 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7041 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7042 uint16_t *data = in_eeprom->data;
7045 first = in_eeprom->offset >> 1;
7046 length = in_eeprom->length >> 1;
7047 if ((first > hw->eeprom.word_size) ||
7048 ((first + length) > hw->eeprom.word_size))
7051 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7053 return eeprom->ops.write_buffer(hw, first, length, data);
7057 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7059 case ixgbe_mac_X550:
7060 case ixgbe_mac_X550EM_x:
7061 case ixgbe_mac_X550EM_a:
7062 return ETH_RSS_RETA_SIZE_512;
7063 case ixgbe_mac_X550_vf:
7064 case ixgbe_mac_X550EM_x_vf:
7065 case ixgbe_mac_X550EM_a_vf:
7066 return ETH_RSS_RETA_SIZE_64;
7068 return ETH_RSS_RETA_SIZE_128;
7073 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7075 case ixgbe_mac_X550:
7076 case ixgbe_mac_X550EM_x:
7077 case ixgbe_mac_X550EM_a:
7078 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7079 return IXGBE_RETA(reta_idx >> 2);
7081 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7082 case ixgbe_mac_X550_vf:
7083 case ixgbe_mac_X550EM_x_vf:
7084 case ixgbe_mac_X550EM_a_vf:
7085 return IXGBE_VFRETA(reta_idx >> 2);
7087 return IXGBE_RETA(reta_idx >> 2);
7092 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7094 case ixgbe_mac_X550_vf:
7095 case ixgbe_mac_X550EM_x_vf:
7096 case ixgbe_mac_X550EM_a_vf:
7097 return IXGBE_VFMRQC;
7104 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7106 case ixgbe_mac_X550_vf:
7107 case ixgbe_mac_X550EM_x_vf:
7108 case ixgbe_mac_X550EM_a_vf:
7109 return IXGBE_VFRSSRK(i);
7111 return IXGBE_RSSRK(i);
7116 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7118 case ixgbe_mac_82599_vf:
7119 case ixgbe_mac_X540_vf:
7127 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7128 struct rte_eth_dcb_info *dcb_info)
7130 struct ixgbe_dcb_config *dcb_config =
7131 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7132 struct ixgbe_dcb_tc_config *tc;
7135 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7136 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7138 dcb_info->nb_tcs = 1;
7140 if (dcb_config->vt_mode) { /* vt is enabled*/
7141 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7142 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7143 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7144 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7145 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7146 for (j = 0; j < dcb_info->nb_tcs; j++) {
7147 dcb_info->tc_queue.tc_rxq[i][j].base =
7148 i * dcb_info->nb_tcs + j;
7149 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
7150 dcb_info->tc_queue.tc_txq[i][j].base =
7151 i * dcb_info->nb_tcs + j;
7152 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7155 } else { /* vt is disabled*/
7156 struct rte_eth_dcb_rx_conf *rx_conf =
7157 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7158 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7159 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7160 if (dcb_info->nb_tcs == ETH_4_TCS) {
7161 for (i = 0; i < dcb_info->nb_tcs; i++) {
7162 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7163 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7165 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7166 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7167 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7168 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7169 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7170 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7171 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7172 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7173 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7174 for (i = 0; i < dcb_info->nb_tcs; i++) {
7175 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7176 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7178 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7179 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7180 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7181 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7182 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7183 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7184 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7185 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7186 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7187 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7188 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7189 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7190 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7191 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7192 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7193 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7196 for (i = 0; i < dcb_info->nb_tcs; i++) {
7197 tc = &dcb_config->tc_config[i];
7198 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7203 /* Update e-tag ether type */
7205 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7206 uint16_t ether_type)
7208 uint32_t etag_etype;
7210 if (hw->mac.type != ixgbe_mac_X550 &&
7211 hw->mac.type != ixgbe_mac_X550EM_x &&
7212 hw->mac.type != ixgbe_mac_X550EM_a) {
7216 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7217 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7218 etag_etype |= ether_type;
7219 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7220 IXGBE_WRITE_FLUSH(hw);
7225 /* Config l2 tunnel ether type */
7227 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7228 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7231 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7232 struct ixgbe_l2_tn_info *l2_tn_info =
7233 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7235 if (l2_tunnel == NULL)
7238 switch (l2_tunnel->l2_tunnel_type) {
7239 case RTE_L2_TUNNEL_TYPE_E_TAG:
7240 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7241 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7244 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7252 /* Enable e-tag tunnel */
7254 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7256 uint32_t etag_etype;
7258 if (hw->mac.type != ixgbe_mac_X550 &&
7259 hw->mac.type != ixgbe_mac_X550EM_x &&
7260 hw->mac.type != ixgbe_mac_X550EM_a) {
7264 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7265 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7266 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7267 IXGBE_WRITE_FLUSH(hw);
7272 /* Enable l2 tunnel */
7274 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7275 enum rte_eth_tunnel_type l2_tunnel_type)
7278 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7279 struct ixgbe_l2_tn_info *l2_tn_info =
7280 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7282 switch (l2_tunnel_type) {
7283 case RTE_L2_TUNNEL_TYPE_E_TAG:
7284 l2_tn_info->e_tag_en = TRUE;
7285 ret = ixgbe_e_tag_enable(hw);
7288 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7296 /* Disable e-tag tunnel */
7298 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7300 uint32_t etag_etype;
7302 if (hw->mac.type != ixgbe_mac_X550 &&
7303 hw->mac.type != ixgbe_mac_X550EM_x &&
7304 hw->mac.type != ixgbe_mac_X550EM_a) {
7308 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7309 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7310 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7311 IXGBE_WRITE_FLUSH(hw);
7316 /* Disable l2 tunnel */
7318 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7319 enum rte_eth_tunnel_type l2_tunnel_type)
7322 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7323 struct ixgbe_l2_tn_info *l2_tn_info =
7324 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7326 switch (l2_tunnel_type) {
7327 case RTE_L2_TUNNEL_TYPE_E_TAG:
7328 l2_tn_info->e_tag_en = FALSE;
7329 ret = ixgbe_e_tag_disable(hw);
7332 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7341 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7342 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7345 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7346 uint32_t i, rar_entries;
7347 uint32_t rar_low, rar_high;
7349 if (hw->mac.type != ixgbe_mac_X550 &&
7350 hw->mac.type != ixgbe_mac_X550EM_x &&
7351 hw->mac.type != ixgbe_mac_X550EM_a) {
7355 rar_entries = ixgbe_get_num_rx_addrs(hw);
7357 for (i = 1; i < rar_entries; i++) {
7358 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7359 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7360 if ((rar_high & IXGBE_RAH_AV) &&
7361 (rar_high & IXGBE_RAH_ADTYPE) &&
7362 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7363 l2_tunnel->tunnel_id)) {
7364 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7365 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7367 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7377 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7378 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7381 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7382 uint32_t i, rar_entries;
7383 uint32_t rar_low, rar_high;
7385 if (hw->mac.type != ixgbe_mac_X550 &&
7386 hw->mac.type != ixgbe_mac_X550EM_x &&
7387 hw->mac.type != ixgbe_mac_X550EM_a) {
7391 /* One entry for one tunnel. Try to remove potential existing entry. */
7392 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7394 rar_entries = ixgbe_get_num_rx_addrs(hw);
7396 for (i = 1; i < rar_entries; i++) {
7397 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7398 if (rar_high & IXGBE_RAH_AV) {
7401 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7402 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7403 rar_low = l2_tunnel->tunnel_id;
7405 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7406 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7412 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7413 " Please remove a rule before adding a new one.");
7417 static inline struct ixgbe_l2_tn_filter *
7418 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7419 struct ixgbe_l2_tn_key *key)
7423 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7427 return l2_tn_info->hash_map[ret];
7431 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7432 struct ixgbe_l2_tn_filter *l2_tn_filter)
7436 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7437 &l2_tn_filter->key);
7441 "Failed to insert L2 tunnel filter"
7442 " to hash table %d!",
7447 l2_tn_info->hash_map[ret] = l2_tn_filter;
7449 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7455 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7456 struct ixgbe_l2_tn_key *key)
7459 struct ixgbe_l2_tn_filter *l2_tn_filter;
7461 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7465 "No such L2 tunnel filter to delete %d!",
7470 l2_tn_filter = l2_tn_info->hash_map[ret];
7471 l2_tn_info->hash_map[ret] = NULL;
7473 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7474 rte_free(l2_tn_filter);
7479 /* Add l2 tunnel filter */
7481 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7482 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7486 struct ixgbe_l2_tn_info *l2_tn_info =
7487 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7488 struct ixgbe_l2_tn_key key;
7489 struct ixgbe_l2_tn_filter *node;
7492 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7493 key.tn_id = l2_tunnel->tunnel_id;
7495 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7499 "The L2 tunnel filter already exists!");
7503 node = rte_zmalloc("ixgbe_l2_tn",
7504 sizeof(struct ixgbe_l2_tn_filter),
7509 (void)rte_memcpy(&node->key,
7511 sizeof(struct ixgbe_l2_tn_key));
7512 node->pool = l2_tunnel->pool;
7513 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7520 switch (l2_tunnel->l2_tunnel_type) {
7521 case RTE_L2_TUNNEL_TYPE_E_TAG:
7522 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7525 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7530 if ((!restore) && (ret < 0))
7531 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7536 /* Delete l2 tunnel filter */
7538 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7539 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7542 struct ixgbe_l2_tn_info *l2_tn_info =
7543 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7544 struct ixgbe_l2_tn_key key;
7546 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7547 key.tn_id = l2_tunnel->tunnel_id;
7548 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7552 switch (l2_tunnel->l2_tunnel_type) {
7553 case RTE_L2_TUNNEL_TYPE_E_TAG:
7554 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7557 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7566 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7567 * @dev: pointer to rte_eth_dev structure
7568 * @filter_op:operation will be taken.
7569 * @arg: a pointer to specific structure corresponding to the filter_op
7572 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7573 enum rte_filter_op filter_op,
7578 if (filter_op == RTE_ETH_FILTER_NOP)
7582 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7587 switch (filter_op) {
7588 case RTE_ETH_FILTER_ADD:
7589 ret = ixgbe_dev_l2_tunnel_filter_add
7591 (struct rte_eth_l2_tunnel_conf *)arg,
7594 case RTE_ETH_FILTER_DELETE:
7595 ret = ixgbe_dev_l2_tunnel_filter_del
7597 (struct rte_eth_l2_tunnel_conf *)arg);
7600 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7608 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7614 if (hw->mac.type != ixgbe_mac_X550 &&
7615 hw->mac.type != ixgbe_mac_X550EM_x &&
7616 hw->mac.type != ixgbe_mac_X550EM_a) {
7620 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7621 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7623 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7624 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7629 /* Enable l2 tunnel forwarding */
7631 ixgbe_dev_l2_tunnel_forwarding_enable
7632 (struct rte_eth_dev *dev,
7633 enum rte_eth_tunnel_type l2_tunnel_type)
7635 struct ixgbe_l2_tn_info *l2_tn_info =
7636 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7639 switch (l2_tunnel_type) {
7640 case RTE_L2_TUNNEL_TYPE_E_TAG:
7641 l2_tn_info->e_tag_fwd_en = TRUE;
7642 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7645 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7653 /* Disable l2 tunnel forwarding */
7655 ixgbe_dev_l2_tunnel_forwarding_disable
7656 (struct rte_eth_dev *dev,
7657 enum rte_eth_tunnel_type l2_tunnel_type)
7659 struct ixgbe_l2_tn_info *l2_tn_info =
7660 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7663 switch (l2_tunnel_type) {
7664 case RTE_L2_TUNNEL_TYPE_E_TAG:
7665 l2_tn_info->e_tag_fwd_en = FALSE;
7666 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7669 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7678 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7679 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7682 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7684 uint32_t vmtir, vmvir;
7685 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7687 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7689 "VF id %u should be less than %u",
7695 if (hw->mac.type != ixgbe_mac_X550 &&
7696 hw->mac.type != ixgbe_mac_X550EM_x &&
7697 hw->mac.type != ixgbe_mac_X550EM_a) {
7702 vmtir = l2_tunnel->tunnel_id;
7706 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7708 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7709 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7711 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7712 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7717 /* Enable l2 tunnel tag insertion */
7719 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7720 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7724 switch (l2_tunnel->l2_tunnel_type) {
7725 case RTE_L2_TUNNEL_TYPE_E_TAG:
7726 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7729 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7737 /* Disable l2 tunnel tag insertion */
7739 ixgbe_dev_l2_tunnel_insertion_disable
7740 (struct rte_eth_dev *dev,
7741 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7745 switch (l2_tunnel->l2_tunnel_type) {
7746 case RTE_L2_TUNNEL_TYPE_E_TAG:
7747 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7750 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7759 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7764 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7766 if (hw->mac.type != ixgbe_mac_X550 &&
7767 hw->mac.type != ixgbe_mac_X550EM_x &&
7768 hw->mac.type != ixgbe_mac_X550EM_a) {
7772 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7774 qde |= IXGBE_QDE_STRIP_TAG;
7776 qde &= ~IXGBE_QDE_STRIP_TAG;
7777 qde &= ~IXGBE_QDE_READ;
7778 qde |= IXGBE_QDE_WRITE;
7779 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7784 /* Enable l2 tunnel tag stripping */
7786 ixgbe_dev_l2_tunnel_stripping_enable
7787 (struct rte_eth_dev *dev,
7788 enum rte_eth_tunnel_type l2_tunnel_type)
7792 switch (l2_tunnel_type) {
7793 case RTE_L2_TUNNEL_TYPE_E_TAG:
7794 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7797 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7805 /* Disable l2 tunnel tag stripping */
7807 ixgbe_dev_l2_tunnel_stripping_disable
7808 (struct rte_eth_dev *dev,
7809 enum rte_eth_tunnel_type l2_tunnel_type)
7813 switch (l2_tunnel_type) {
7814 case RTE_L2_TUNNEL_TYPE_E_TAG:
7815 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7818 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7826 /* Enable/disable l2 tunnel offload functions */
7828 ixgbe_dev_l2_tunnel_offload_set
7829 (struct rte_eth_dev *dev,
7830 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7836 if (l2_tunnel == NULL)
7840 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7842 ret = ixgbe_dev_l2_tunnel_enable(
7844 l2_tunnel->l2_tunnel_type);
7846 ret = ixgbe_dev_l2_tunnel_disable(
7848 l2_tunnel->l2_tunnel_type);
7851 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7853 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7857 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7862 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7864 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7866 l2_tunnel->l2_tunnel_type);
7868 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7870 l2_tunnel->l2_tunnel_type);
7873 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7875 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7877 l2_tunnel->l2_tunnel_type);
7879 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7881 l2_tunnel->l2_tunnel_type);
7888 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7891 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7892 IXGBE_WRITE_FLUSH(hw);
7897 /* There's only one register for VxLAN UDP port.
7898 * So, we cannot add several ports. Will update it.
7901 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7905 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7909 return ixgbe_update_vxlan_port(hw, port);
7912 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7913 * UDP port, it must have a value.
7914 * So, will reset it to the original value 0.
7917 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7922 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7924 if (cur_port != port) {
7925 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7929 return ixgbe_update_vxlan_port(hw, 0);
7932 /* Add UDP tunneling port */
7934 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7935 struct rte_eth_udp_tunnel *udp_tunnel)
7938 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7940 if (hw->mac.type != ixgbe_mac_X550 &&
7941 hw->mac.type != ixgbe_mac_X550EM_x &&
7942 hw->mac.type != ixgbe_mac_X550EM_a) {
7946 if (udp_tunnel == NULL)
7949 switch (udp_tunnel->prot_type) {
7950 case RTE_TUNNEL_TYPE_VXLAN:
7951 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7954 case RTE_TUNNEL_TYPE_GENEVE:
7955 case RTE_TUNNEL_TYPE_TEREDO:
7956 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7961 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7969 /* Remove UDP tunneling port */
7971 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7972 struct rte_eth_udp_tunnel *udp_tunnel)
7975 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7977 if (hw->mac.type != ixgbe_mac_X550 &&
7978 hw->mac.type != ixgbe_mac_X550EM_x &&
7979 hw->mac.type != ixgbe_mac_X550EM_a) {
7983 if (udp_tunnel == NULL)
7986 switch (udp_tunnel->prot_type) {
7987 case RTE_TUNNEL_TYPE_VXLAN:
7988 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7990 case RTE_TUNNEL_TYPE_GENEVE:
7991 case RTE_TUNNEL_TYPE_TEREDO:
7992 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7996 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8005 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8007 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8013 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8015 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8017 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8020 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8022 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8025 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8028 /* PF reset VF event */
8029 if (in_msg == IXGBE_PF_CONTROL_MSG)
8030 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8035 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8038 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8039 struct ixgbe_interrupt *intr =
8040 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8041 ixgbevf_intr_disable(hw);
8043 /* read-on-clear nic registers here */
8044 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8047 /* only one misc vector supported - mailbox */
8048 eicr &= IXGBE_VTEICR_MASK;
8049 if (eicr == IXGBE_MISC_VEC_ID)
8050 intr->flags |= IXGBE_FLAG_MAILBOX;
8056 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8059 struct ixgbe_interrupt *intr =
8060 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8062 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8063 ixgbevf_mbx_process(dev);
8064 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8067 ixgbevf_intr_enable(hw);
8073 ixgbevf_dev_interrupt_handler(void *param)
8075 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8077 ixgbevf_dev_interrupt_get_status(dev);
8078 ixgbevf_dev_interrupt_action(dev);
8082 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8083 * @hw: pointer to hardware structure
8085 * Stops the transmit data path and waits for the HW to internally empty
8086 * the Tx security block
8088 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8090 #define IXGBE_MAX_SECTX_POLL 40
8095 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8096 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8097 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8098 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8099 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8100 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8102 /* Use interrupt-safe sleep just in case */
8106 /* For informational purposes only */
8107 if (i >= IXGBE_MAX_SECTX_POLL)
8108 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8109 "path fully disabled. Continuing with init.");
8111 return IXGBE_SUCCESS;
8115 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8116 * @hw: pointer to hardware structure
8118 * Enables the transmit data path.
8120 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8124 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8125 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8126 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8127 IXGBE_WRITE_FLUSH(hw);
8129 return IXGBE_SUCCESS;
8132 /* restore n-tuple filter */
8134 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8136 struct ixgbe_filter_info *filter_info =
8137 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8138 struct ixgbe_5tuple_filter *node;
8140 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8141 ixgbe_inject_5tuple_filter(dev, node);
8145 /* restore ethernet type filter */
8147 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8149 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8150 struct ixgbe_filter_info *filter_info =
8151 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8154 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8155 if (filter_info->ethertype_mask & (1 << i)) {
8156 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8157 filter_info->ethertype_filters[i].etqf);
8158 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8159 filter_info->ethertype_filters[i].etqs);
8160 IXGBE_WRITE_FLUSH(hw);
8165 /* restore SYN filter */
8167 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8169 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8170 struct ixgbe_filter_info *filter_info =
8171 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8174 synqf = filter_info->syn_info;
8176 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8177 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8178 IXGBE_WRITE_FLUSH(hw);
8182 /* restore L2 tunnel filter */
8184 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8186 struct ixgbe_l2_tn_info *l2_tn_info =
8187 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8188 struct ixgbe_l2_tn_filter *node;
8189 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8191 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8192 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8193 l2_tn_conf.tunnel_id = node->key.tn_id;
8194 l2_tn_conf.pool = node->pool;
8195 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8200 ixgbe_filter_restore(struct rte_eth_dev *dev)
8202 ixgbe_ntuple_filter_restore(dev);
8203 ixgbe_ethertype_filter_restore(dev);
8204 ixgbe_syn_filter_restore(dev);
8205 ixgbe_fdir_filter_restore(dev);
8206 ixgbe_l2_tn_filter_restore(dev);
8212 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8214 struct ixgbe_l2_tn_info *l2_tn_info =
8215 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8216 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8218 if (l2_tn_info->e_tag_en)
8219 (void)ixgbe_e_tag_enable(hw);
8221 if (l2_tn_info->e_tag_fwd_en)
8222 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8224 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8227 /* remove all the n-tuple filters */
8229 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8231 struct ixgbe_filter_info *filter_info =
8232 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8233 struct ixgbe_5tuple_filter *p_5tuple;
8235 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8236 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8239 /* remove all the ether type filters */
8241 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8243 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8244 struct ixgbe_filter_info *filter_info =
8245 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8248 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8249 if (filter_info->ethertype_mask & (1 << i) &&
8250 !filter_info->ethertype_filters[i].conf) {
8251 (void)ixgbe_ethertype_filter_remove(filter_info,
8253 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8254 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8255 IXGBE_WRITE_FLUSH(hw);
8260 /* remove the SYN filter */
8262 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8264 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8265 struct ixgbe_filter_info *filter_info =
8266 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8268 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8269 filter_info->syn_info = 0;
8271 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8272 IXGBE_WRITE_FLUSH(hw);
8276 /* remove all the L2 tunnel filters */
8278 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8280 struct ixgbe_l2_tn_info *l2_tn_info =
8281 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8282 struct ixgbe_l2_tn_filter *l2_tn_filter;
8283 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8286 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8287 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8288 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8289 l2_tn_conf.pool = l2_tn_filter->pool;
8290 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8298 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8299 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8300 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8301 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8302 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8303 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");