drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71
  72 /*
  73  * High threshold controlling when to start sending XOFF frames. Must be at
  74  * least 8 bytes less than receive packet buffer size. This value is in units
  75  * of 1024 bytes.
  76  */
  77 #define IXGBE_FC_HI    0x80
  78
  79 /*
  80  * Low threshold controlling when to start sending XON frames. This value is
  81  * in units of 1024 bytes.
  82  */
  83 #define IXGBE_FC_LO    0x40
  84
  85 /* Timer value included in XOFF frames. */
  86 #define IXGBE_FC_PAUSE 0x680
  87
  88 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  89 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  90 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  91
  92 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  93 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
  94
  95 /*
  96  *  Default values for RX/TX configuration
  97  */
  98 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
  99 #define IXGBE_DEFAULT_RX_PTHRESH      8
 100 #define IXGBE_DEFAULT_RX_HTHRESH      8
 101 #define IXGBE_DEFAULT_RX_WTHRESH      0
 102
 103 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 104 #define IXGBE_DEFAULT_TX_PTHRESH      32
 105 #define IXGBE_DEFAULT_TX_HTHRESH      0
 106 #define IXGBE_DEFAULT_TX_WTHRESH      0
 107 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 108
 109 /* Bit shift and mask */
 110 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 111 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 112 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 113 #define IXGBE_8_BIT_MASK   UINT8_MAX
 114
 115 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 116
 117 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 118
 119 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 120 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 121 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 122 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 123 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 124 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 125 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 126 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 127 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 128 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 129 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 130 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 131                                 int wait_to_complete);
 132 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 133                                 struct rte_eth_stats *stats);
 134 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 135 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 136                                              uint16_t queue_id,
 137                                              uint8_t stat_idx,
 138                                              uint8_t is_rx);
 139 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 140                                struct rte_eth_dev_info *dev_info);
 141 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 142                                  struct rte_eth_dev_info *dev_info);
 143 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 144
 145 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 146                 uint16_t vlan_id, int on);
 147 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 148 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 149                 uint16_t queue, bool on);
 150 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 151                 int on);
 152 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 153 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 154 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 155 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 156 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 157
 158 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 159 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 160 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 161                                struct rte_eth_fc_conf *fc_conf);
 162 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 163                                struct rte_eth_fc_conf *fc_conf);
 164 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 165                 struct rte_eth_pfc_conf *pfc_conf);
 166 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 167                         struct rte_eth_rss_reta_entry64 *reta_conf,
 168                         uint16_t reta_size);
 169 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 170                         struct rte_eth_rss_reta_entry64 *reta_conf,
 171                         uint16_t reta_size);
 172 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 173 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 174 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 175 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 176 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 177                 void *param);
 178 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 179 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 180                 uint32_t index, uint32_t pool);
 181 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 182 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 183
 184 /* For Virtual Function support */
 185 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 186 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 187 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 188 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 189 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 190 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 191 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 192                 struct rte_eth_stats *stats);
 193 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 194 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 195                 uint16_t vlan_id, int on);
 196 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 197                 uint16_t queue, int on);
 198 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 199 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 200
 201 /* For Eth VMDQ APIs support */
 202 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 203                 ether_addr* mac_addr,uint8_t on);
 204 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 205 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 206                 uint16_t rx_mask, uint8_t on);
 207 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 208 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 209 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 210                 uint64_t pool_mask,uint8_t vlan_on);
 211 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 212                 struct rte_eth_mirror_conf *mirror_conf,
 213                 uint8_t rule_id, uint8_t on);
 214 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 215                 uint8_t rule_id);
 216
 217 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 218                 uint16_t queue_idx, uint16_t tx_rate);
 219 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 220                 uint16_t tx_rate, uint64_t q_msk);
 221
 222 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 223                                  struct ether_addr *mac_addr,
 224                                  uint32_t index, uint32_t pool);
 225 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 226 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 227                         struct rte_eth_syn_filter *filter,
 228                         bool add);
 229 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 230                         struct rte_eth_syn_filter *filter);
 231 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 232                         enum rte_filter_op filter_op,
 233                         void *arg);
 234 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 235                         struct ixgbe_5tuple_filter *filter);
 236 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 237                         struct ixgbe_5tuple_filter *filter);
 238 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 239                         struct rte_eth_ntuple_filter *filter,
 240                         bool add);
 241 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 242                                 enum rte_filter_op filter_op,
 243                                 void *arg);
 244 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 245                         struct rte_eth_ntuple_filter *filter);
 246 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 247                         struct rte_eth_ethertype_filter *filter,
 248                         bool add);
 249 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 250                                 enum rte_filter_op filter_op,
 251                                 void *arg);
 252 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 253                         struct rte_eth_ethertype_filter *filter);
 254 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 255                      enum rte_filter_type filter_type,
 256                      enum rte_filter_op filter_op,
 257                      void *arg);
 258 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 259
 260 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 261                                       struct ether_addr *mc_addr_set,
 262                                       uint32_t nb_mc_addr);
 263
 264 /*
 265  * Define VF Stats MACRO for Non "cleared on read" register
 266  */
 267 #define UPDATE_VF_STAT(reg, last, cur)                          \
 268 {                                                               \
 269         u32 latest = IXGBE_READ_REG(hw, reg);                   \
 270         cur += latest - last;                                   \
 271         last = latest;                                          \
 272 }
 273
 274 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 275 {                                                                \
 276         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 277         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 278         u64 latest = ((new_msb << 32) | new_lsb);                \
 279         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 280         last = latest;                                           \
 281 }
 282
 283 #define IXGBE_SET_HWSTRIP(h, q) do{\
 284                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 285                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 286                 (h)->bitmap[idx] |= 1 << bit;\
 287         }while(0)
 288
 289 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 290                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 291                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 292                 (h)->bitmap[idx] &= ~(1 << bit);\
 293         }while(0)
 294
 295 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 296                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 297                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 298                 (r) = (h)->bitmap[idx] >> bit & 1;\
 299         }while(0)
 300
 301 /*
 302  * The set of PCI devices this driver supports
 303  */
 304 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 305
 306 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 307 #include "rte_pci_dev_ids.h"
 308
 309 { .vendor_id = 0, /* sentinel */ },
 310 };
 311
 312
 313 /*
 314  * The set of PCI devices this driver supports (for 82599 VF)
 315  */
 316 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 317
 318 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 319 #include "rte_pci_dev_ids.h"
 320 { .vendor_id = 0, /* sentinel */ },
 321
 322 };
 323
 324 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 325         .dev_configure        = ixgbe_dev_configure,
 326         .dev_start            = ixgbe_dev_start,
 327         .dev_stop             = ixgbe_dev_stop,
 328         .dev_set_link_up    = ixgbe_dev_set_link_up,
 329         .dev_set_link_down  = ixgbe_dev_set_link_down,
 330         .dev_close            = ixgbe_dev_close,
 331         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 332         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 333         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 334         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 335         .link_update          = ixgbe_dev_link_update,
 336         .stats_get            = ixgbe_dev_stats_get,
 337         .stats_reset          = ixgbe_dev_stats_reset,
 338         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 339         .dev_infos_get        = ixgbe_dev_info_get,
 340         .mtu_set              = ixgbe_dev_mtu_set,
 341         .vlan_filter_set      = ixgbe_vlan_filter_set,
 342         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 343         .vlan_offload_set     = ixgbe_vlan_offload_set,
 344         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 345         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 346         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 347         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 348         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 349         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 350         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 351         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 352         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 353         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 354         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 355         .dev_led_on           = ixgbe_dev_led_on,
 356         .dev_led_off          = ixgbe_dev_led_off,
 357         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 358         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 359         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 360         .mac_addr_add         = ixgbe_add_rar,
 361         .mac_addr_remove      = ixgbe_remove_rar,
 362         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 363         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 364         .mirror_rule_set      = ixgbe_mirror_rule_set,
 365         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 366         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 367         .set_vf_rx            = ixgbe_set_pool_rx,
 368         .set_vf_tx            = ixgbe_set_pool_tx,
 369         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 370         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 371         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 372         .reta_update          = ixgbe_dev_rss_reta_update,
 373         .reta_query           = ixgbe_dev_rss_reta_query,
 374 #ifdef RTE_NIC_BYPASS
 375         .bypass_init          = ixgbe_bypass_init,
 376         .bypass_state_set     = ixgbe_bypass_state_store,
 377         .bypass_state_show    = ixgbe_bypass_state_show,
 378         .bypass_event_set     = ixgbe_bypass_event_store,
 379         .bypass_event_show    = ixgbe_bypass_event_show,
 380         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 381         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 382         .bypass_ver_show      = ixgbe_bypass_ver_show,
 383         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 384 #endif /* RTE_NIC_BYPASS */
 385         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 386         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 387         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 388         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 389 };
 390
 391 /*
 392  * dev_ops for virtual function, bare necessities for basic vf
 393  * operation have been implemented
 394  */
 395 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 396         .dev_configure        = ixgbevf_dev_configure,
 397         .dev_start            = ixgbevf_dev_start,
 398         .dev_stop             = ixgbevf_dev_stop,
 399         .link_update          = ixgbe_dev_link_update,
 400         .stats_get            = ixgbevf_dev_stats_get,
 401         .stats_reset          = ixgbevf_dev_stats_reset,
 402         .dev_close            = ixgbevf_dev_close,
 403         .dev_infos_get        = ixgbevf_dev_info_get,
 404         .mtu_set              = ixgbevf_dev_set_mtu,
 405         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 406         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 407         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 408         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 409         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 410         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 411         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 412         .mac_addr_add         = ixgbevf_add_mac_addr,
 413         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 414         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 415 };
 416
 417 /**
 418  * Atomically reads the link status information from global
 419  * structure rte_eth_dev.
 420  *
 421  * @param dev
 422  *   - Pointer to the structure rte_eth_dev to read from.
 423  *   - Pointer to the buffer to be saved with the link status.
 424  *
 425  * @return
 426  *   - On success, zero.
 427  *   - On failure, negative value.
 428  */
 429 static inline int
 430 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 431                                 struct rte_eth_link *link)
 432 {
 433         struct rte_eth_link *dst = link;
 434         struct rte_eth_link *src = &(dev->data->dev_link);
 435
 436         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 437                                         *(uint64_t *)src) == 0)
 438                 return -1;
 439
 440         return 0;
 441 }
 442
 443 /**
 444  * Atomically writes the link status information into global
 445  * structure rte_eth_dev.
 446  *
 447  * @param dev
 448  *   - Pointer to the structure rte_eth_dev to read from.
 449  *   - Pointer to the buffer to be saved with the link status.
 450  *
 451  * @return
 452  *   - On success, zero.
 453  *   - On failure, negative value.
 454  */
 455 static inline int
 456 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 457                                 struct rte_eth_link *link)
 458 {
 459         struct rte_eth_link *dst = &(dev->data->dev_link);
 460         struct rte_eth_link *src = link;
 461
 462         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 463                                         *(uint64_t *)src) == 0)
 464                 return -1;
 465
 466         return 0;
 467 }
 468
 469 /*
 470  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 471  */
 472 static inline int
 473 ixgbe_is_sfp(struct ixgbe_hw *hw)
 474 {
 475         switch (hw->phy.type) {
 476         case ixgbe_phy_sfp_avago:
 477         case ixgbe_phy_sfp_ftl:
 478         case ixgbe_phy_sfp_intel:
 479         case ixgbe_phy_sfp_unknown:
 480         case ixgbe_phy_sfp_passive_tyco:
 481         case ixgbe_phy_sfp_passive_unknown:
 482                 return 1;
 483         default:
 484                 return 0;
 485         }
 486 }
 487
 488 static inline int32_t
 489 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 490 {
 491         uint32_t ctrl_ext;
 492         int32_t status;
 493
 494         status = ixgbe_reset_hw(hw);
 495
 496         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 497         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 498         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 499         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 500         IXGBE_WRITE_FLUSH(hw);
 501
 502         return status;
 503 }
 504
 505 static inline void
 506 ixgbe_enable_intr(struct rte_eth_dev *dev)
 507 {
 508         struct ixgbe_interrupt *intr =
 509                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 510         struct ixgbe_hw *hw =
 511                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 512
 513         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 514         IXGBE_WRITE_FLUSH(hw);
 515 }
 516
 517 /*
 518  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 519  */
 520 static void
 521 ixgbe_disable_intr(struct ixgbe_hw *hw)
 522 {
 523         PMD_INIT_FUNC_TRACE();
 524
 525         if (hw->mac.type == ixgbe_mac_82598EB) {
 526                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 527         } else {
 528                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 529                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 530                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 531         }
 532         IXGBE_WRITE_FLUSH(hw);
 533 }
 534
 535 /*
 536  * This function resets queue statistics mapping registers.
 537  * From Niantic datasheet, Initialization of Statistics section:
 538  * "...if software requires the queue counters, the RQSMR and TQSM registers
 539  * must be re-programmed following a device reset.
 540  */
 541 static void
 542 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 543 {
 544         uint32_t i;
 545
 546         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 547                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 548                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 549         }
 550 }
 551
 552
 553 static int
 554 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 555                                   uint16_t queue_id,
 556                                   uint8_t stat_idx,
 557                                   uint8_t is_rx)
 558 {
 559 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 560 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 561 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 562
 563         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 564         struct ixgbe_stat_mapping_registers *stat_mappings =
 565                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 566         uint32_t qsmr_mask = 0;
 567         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 568         uint32_t q_map;
 569         uint8_t n, offset;
 570
 571         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 572                 (hw->mac.type != ixgbe_mac_X540) &&
 573                 (hw->mac.type != ixgbe_mac_X550) &&
 574                 (hw->mac.type != ixgbe_mac_X550EM_x))
 575                 return -ENOSYS;
 576
 577         PMD_INIT_LOG(INFO, "Setting port %d, %s queue_id %d to stat index %d",
 578                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 579                      queue_id, stat_idx);
 580
 581         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 582         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 583                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 584                 return -EIO;
 585         }
 586         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 587
 588         /* Now clear any previous stat_idx set */
 589         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 590         if (!is_rx)
 591                 stat_mappings->tqsm[n] &= ~clearing_mask;
 592         else
 593                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 594
 595         q_map = (uint32_t)stat_idx;
 596         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 597         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 598         if (!is_rx)
 599                 stat_mappings->tqsm[n] |= qsmr_mask;
 600         else
 601                 stat_mappings->rqsmr[n] |= qsmr_mask;
 602
 603         PMD_INIT_LOG(INFO, "Set port %d, %s queue_id %d to stat index %d",
 604                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 605                      queue_id, stat_idx);
 606         PMD_INIT_LOG(INFO, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 607                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 608
 609         /* Now write the mapping in the appropriate register */
 610         if (is_rx) {
 611                 PMD_INIT_LOG(INFO, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 612                              stat_mappings->rqsmr[n], n);
 613                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 614         }
 615         else {
 616                 PMD_INIT_LOG(INFO, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 617                              stat_mappings->tqsm[n], n);
 618                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 619         }
 620         return 0;
 621 }
 622
 623 static void
 624 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 625 {
 626         struct ixgbe_stat_mapping_registers *stat_mappings =
 627                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 628         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629         int i;
 630
 631         /* write whatever was in stat mapping table to the NIC */
 632         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 633                 /* rx */
 634                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 635
 636                 /* tx */
 637                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 638         }
 639 }
 640
 641 static void
 642 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 643 {
 644         uint8_t i;
 645         struct ixgbe_dcb_tc_config *tc;
 646         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 647
 648         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 649         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 650         for (i = 0; i < dcb_max_tc; i++) {
 651                 tc = &dcb_config->tc_config[i];
 652                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 653                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 654                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 655                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 656                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 657                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 658                 tc->pfc = ixgbe_dcb_pfc_disabled;
 659         }
 660
 661         /* Initialize default user to priority mapping, UPx->TC0 */
 662         tc = &dcb_config->tc_config[0];
 663         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 664         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 665         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 666                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 667                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 668         }
 669         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 670         dcb_config->pfc_mode_enable = false;
 671         dcb_config->vt_mode = true;
 672         dcb_config->round_robin_enable = false;
 673         /* support all DCB capabilities in 82599 */
 674         dcb_config->support.capabilities = 0xFF;
 675
 676         /*we only support 4 Tcs for X540, X550 */
 677         if (hw->mac.type == ixgbe_mac_X540 ||
 678                 hw->mac.type == ixgbe_mac_X550 ||
 679                 hw->mac.type == ixgbe_mac_X550EM_x) {
 680                 dcb_config->num_tcs.pg_tcs = 4;
 681                 dcb_config->num_tcs.pfc_tcs = 4;
 682         }
 683 }
 684
 685 /*
 686  * Ensure that all locks are released before first NVM or PHY access
 687  */
 688 static void
 689 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 690 {
 691         uint16_t mask;
 692
 693         /*
 694          * Phy lock should not fail in this early stage. If this is the case,
 695          * it is due to an improper exit of the application.
 696          * So force the release of the faulty lock. Release of common lock
 697          * is done automatically by swfw_sync function.
 698          */
 699         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 700         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 701                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 702         }
 703         ixgbe_release_swfw_semaphore(hw, mask);
 704
 705         /*
 706          * These ones are more tricky since they are common to all ports; but
 707          * swfw_sync retries last long enough (1s) to be almost sure that if
 708          * lock can not be taken it is due to an improper lock of the
 709          * semaphore.
 710          */
 711         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 712         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 713                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 714         }
 715         ixgbe_release_swfw_semaphore(hw, mask);
 716 }
 717
 718 /*
 719  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 720  * It returns 0 on success.
 721  */
 722 static int
 723 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 724 {
 725         struct rte_pci_device *pci_dev;
 726         struct ixgbe_hw *hw =
 727                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 728         struct ixgbe_vfta * shadow_vfta =
 729                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 730         struct ixgbe_hwstrip *hwstrip =
 731                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 732         struct ixgbe_dcb_config *dcb_config =
 733                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 734         struct ixgbe_filter_info *filter_info =
 735                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 736         uint32_t ctrl_ext;
 737         uint16_t csum;
 738         int diag, i;
 739
 740         PMD_INIT_FUNC_TRACE();
 741
 742         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 743         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 744         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 745
 746         /*
 747          * For secondary processes, we don't initialise any further as primary
 748          * has already done this work. Only check we don't need a different
 749          * RX and TX function.
 750          */
 751         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 752                 struct ixgbe_tx_queue *txq;
 753                 /* TX queue function in primary, set by last queue initialized
 754                  * Tx queue may not initialized by primary process */
 755                 if (eth_dev->data->tx_queues) {
 756                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 757                         ixgbe_set_tx_function(eth_dev, txq);
 758                 } else {
 759                         /* Use default TX function if we get here */
 760                         PMD_INIT_LOG(INFO, "No TX queues configured yet. "
 761                                            "Using default TX function.");
 762                 }
 763
 764                 ixgbe_set_rx_function(eth_dev);
 765
 766                 return 0;
 767         }
 768         pci_dev = eth_dev->pci_dev;
 769
 770         /* Vendor and Device ID need to be set before init of shared code */
 771         hw->device_id = pci_dev->id.device_id;
 772         hw->vendor_id = pci_dev->id.vendor_id;
 773         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 774         hw->allow_unsupported_sfp = 1;
 775
 776         /* Initialize the shared code (base driver) */
 777 #ifdef RTE_NIC_BYPASS
 778         diag = ixgbe_bypass_init_shared_code(hw);
 779 #else
 780         diag = ixgbe_init_shared_code(hw);
 781 #endif /* RTE_NIC_BYPASS */
 782
 783         if (diag != IXGBE_SUCCESS) {
 784                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
 785                 return -EIO;
 786         }
 787
 788         /* pick up the PCI bus settings for reporting later */
 789         ixgbe_get_bus_info(hw);
 790
 791         /* Unlock any pending hardware semaphore */
 792         ixgbe_swfw_lock_reset(hw);
 793
 794         /* Initialize DCB configuration*/
 795         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
 796         ixgbe_dcb_init(hw,dcb_config);
 797         /* Get Hardware Flow Control setting */
 798         hw->fc.requested_mode = ixgbe_fc_full;
 799         hw->fc.current_mode = ixgbe_fc_full;
 800         hw->fc.pause_time = IXGBE_FC_PAUSE;
 801         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
 802                 hw->fc.low_water[i] = IXGBE_FC_LO;
 803                 hw->fc.high_water[i] = IXGBE_FC_HI;
 804         }
 805         hw->fc.send_xon = 1;
 806
 807         /* Make sure we have a good EEPROM before we read from it */
 808         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
 809         if (diag != IXGBE_SUCCESS) {
 810                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
 811                 return -EIO;
 812         }
 813
 814 #ifdef RTE_NIC_BYPASS
 815         diag = ixgbe_bypass_init_hw(hw);
 816 #else
 817         diag = ixgbe_init_hw(hw);
 818 #endif /* RTE_NIC_BYPASS */
 819
 820         /*
 821          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
 822          * is called too soon after the kernel driver unbinding/binding occurs.
 823          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
 824          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
 825          * also called. See ixgbe_identify_phy_82599(). The reason for the
 826          * failure is not known, and only occuts when virtualisation features
 827          * are disabled in the bios. A delay of 100ms  was found to be enough by
 828          * trial-and-error, and is doubled to be safe.
 829          */
 830         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
 831                 rte_delay_ms(200);
 832                 diag = ixgbe_init_hw(hw);
 833         }
 834
 835         if (diag == IXGBE_ERR_EEPROM_VERSION) {
 836                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 837                     "LOM.  Please be aware there may be issues associated "
 838                     "with your hardware.");
 839                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 840                     "please contact your Intel or hardware representative "
 841                     "who provided you with this hardware.");
 842         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
 843                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 844         if (diag) {
 845                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
 846                 return -EIO;
 847         }
 848
 849         /* disable interrupt */
 850         ixgbe_disable_intr(hw);
 851
 852         /* reset mappings for queue statistics hw counters*/
 853         ixgbe_reset_qstat_mappings(hw);
 854
 855         /* Allocate memory for storing MAC addresses */
 856         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 857                         hw->mac.num_rar_entries, 0);
 858         if (eth_dev->data->mac_addrs == NULL) {
 859                 PMD_INIT_LOG(ERR,
 860                         "Failed to allocate %u bytes needed to store "
 861                         "MAC addresses",
 862                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 863                 return -ENOMEM;
 864         }
 865         /* Copy the permanent MAC address */
 866         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
 867                         &eth_dev->data->mac_addrs[0]);
 868
 869         /* Allocate memory for storing hash filter MAC addresses */
 870         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
 871                         IXGBE_VMDQ_NUM_UC_MAC, 0);
 872         if (eth_dev->data->hash_mac_addrs == NULL) {
 873                 PMD_INIT_LOG(ERR,
 874                         "Failed to allocate %d bytes needed to store MAC addresses",
 875                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
 876                 return -ENOMEM;
 877         }
 878
 879         /* initialize the vfta */
 880         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 881
 882         /* initialize the hw strip bitmap*/
 883         memset(hwstrip, 0, sizeof(*hwstrip));
 884
 885         /* initialize PF if max_vfs not zero */
 886         ixgbe_pf_host_init(eth_dev);
 887
 888         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 889         /* let hardware know driver is loaded */
 890         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
 891         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 892         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 893         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 894         IXGBE_WRITE_FLUSH(hw);
 895
 896         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
 897                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 898                              (int) hw->mac.type, (int) hw->phy.type,
 899                              (int) hw->phy.sfp_type);
 900         else
 901                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 902                              (int) hw->mac.type, (int) hw->phy.type);
 903
 904         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 905                         eth_dev->data->port_id, pci_dev->id.vendor_id,
 906                         pci_dev->id.device_id);
 907
 908         rte_intr_callback_register(&(pci_dev->intr_handle),
 909                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
 910
 911         /* enable uio intr after callback register */
 912         rte_intr_enable(&(pci_dev->intr_handle));
 913
 914         /* enable support intr */
 915         ixgbe_enable_intr(eth_dev);
 916
 917         /* initialize 5tuple filter list */
 918         TAILQ_INIT(&filter_info->fivetuple_list);
 919         memset(filter_info->fivetuple_mask, 0,
 920                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
 921
 922         return 0;
 923 }
 924
 925
 926 /*
 927  * Negotiate mailbox API version with the PF.
 928  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
 929  * Then we try to negotiate starting with the most recent one.
 930  * If all negotiation attempts fail, then we will proceed with
 931  * the default one (ixgbe_mbox_api_10).
 932  */
 933 static void
 934 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
 935 {
 936         int32_t i;
 937
 938         /* start with highest supported, proceed down */
 939         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
 940                 ixgbe_mbox_api_11,
 941                 ixgbe_mbox_api_10,
 942         };
 943
 944         for (i = 0;
 945                         i != RTE_DIM(sup_ver) &&
 946                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
 947                         i++)
 948                 ;
 949 }
 950
 951 static void
 952 generate_random_mac_addr(struct ether_addr *mac_addr)
 953 {
 954         uint64_t random;
 955
 956         /* Set Organizationally Unique Identifier (OUI) prefix. */
 957         mac_addr->addr_bytes[0] = 0x00;
 958         mac_addr->addr_bytes[1] = 0x09;
 959         mac_addr->addr_bytes[2] = 0xC0;
 960         /* Force indication of locally assigned MAC address. */
 961         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
 962         /* Generate the last 3 bytes of the MAC address with a random number. */
 963         random = rte_rand();
 964         memcpy(&mac_addr->addr_bytes[3], &random, 3);
 965 }
 966
 967 /*
 968  * Virtual Function device init
 969  */
 970 static int
 971 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
 972 {
 973         int diag;
 974         uint32_t tc, tcs;
 975         struct rte_pci_device *pci_dev;
 976         struct ixgbe_hw *hw =
 977                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 978         struct ixgbe_vfta * shadow_vfta =
 979                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 980         struct ixgbe_hwstrip *hwstrip =
 981                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 982         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
 983
 984         PMD_INIT_FUNC_TRACE();
 985
 986         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
 987         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 988         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 989
 990         /* for secondary processes, we don't initialise any further as primary
 991          * has already done this work. Only check we don't need a different
 992          * RX function */
 993         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 994                 if (eth_dev->data->scattered_rx)
 995                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
 996                 return 0;
 997         }
 998
 999         pci_dev = eth_dev->pci_dev;
1000
1001         hw->device_id = pci_dev->id.device_id;
1002         hw->vendor_id = pci_dev->id.vendor_id;
1003         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1004
1005         /* initialize the vfta */
1006         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1007
1008         /* initialize the hw strip bitmap*/
1009         memset(hwstrip, 0, sizeof(*hwstrip));
1010
1011         /* Initialize the shared code (base driver) */
1012         diag = ixgbe_init_shared_code(hw);
1013         if (diag != IXGBE_SUCCESS) {
1014                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1015                 return -EIO;
1016         }
1017
1018         /* init_mailbox_params */
1019         hw->mbx.ops.init_params(hw);
1020
1021         /* Disable the interrupts for VF */
1022         ixgbevf_intr_disable(hw);
1023
1024         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1025         diag = hw->mac.ops.reset_hw(hw);
1026
1027         /*
1028          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1029          * the underlying PF driver has not assigned a MAC address to the VF.
1030          * In this case, assign a random MAC address.
1031          */
1032         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1033                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1034                 return (diag);
1035         }
1036
1037         /* negotiate mailbox API version to use with the PF. */
1038         ixgbevf_negotiate_api(hw);
1039
1040         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1041         ixgbevf_get_queues(hw, &tcs, &tc);
1042
1043         /* Allocate memory for storing MAC addresses */
1044         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1045                         hw->mac.num_rar_entries, 0);
1046         if (eth_dev->data->mac_addrs == NULL) {
1047                 PMD_INIT_LOG(ERR,
1048                         "Failed to allocate %u bytes needed to store "
1049                         "MAC addresses",
1050                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1051                 return -ENOMEM;
1052         }
1053
1054         /* Generate a random MAC address, if none was assigned by PF. */
1055         if (is_zero_ether_addr(perm_addr)) {
1056                 generate_random_mac_addr(perm_addr);
1057                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1058                 if (diag) {
1059                         rte_free(eth_dev->data->mac_addrs);
1060                         eth_dev->data->mac_addrs = NULL;
1061                         return diag;
1062                 }
1063                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1064                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1065                              "%02x:%02x:%02x:%02x:%02x:%02x",
1066                              perm_addr->addr_bytes[0],
1067                              perm_addr->addr_bytes[1],
1068                              perm_addr->addr_bytes[2],
1069                              perm_addr->addr_bytes[3],
1070                              perm_addr->addr_bytes[4],
1071                              perm_addr->addr_bytes[5]);
1072         }
1073
1074         /* Copy the permanent MAC address */
1075         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1076
1077         /* reset the hardware with the new settings */
1078         diag = hw->mac.ops.start_hw(hw);
1079         switch (diag) {
1080                 case  0:
1081                         break;
1082
1083                 default:
1084                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1085                         return (-EIO);
1086         }
1087
1088         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1089                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1090                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1091
1092         return 0;
1093 }
1094
1095 static struct eth_driver rte_ixgbe_pmd = {
1096         .pci_drv = {
1097                 .name = "rte_ixgbe_pmd",
1098                 .id_table = pci_id_ixgbe_map,
1099                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1100         },
1101         .eth_dev_init = eth_ixgbe_dev_init,
1102         .dev_private_size = sizeof(struct ixgbe_adapter),
1103 };
1104
1105 /*
1106  * virtual function driver struct
1107  */
1108 static struct eth_driver rte_ixgbevf_pmd = {
1109         .pci_drv = {
1110                 .name = "rte_ixgbevf_pmd",
1111                 .id_table = pci_id_ixgbevf_map,
1112                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1113         },
1114         .eth_dev_init = eth_ixgbevf_dev_init,
1115         .dev_private_size = sizeof(struct ixgbe_adapter),
1116 };
1117
1118 /*
1119  * Driver initialization routine.
1120  * Invoked once at EAL init time.
1121  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1122  */
1123 static int
1124 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1125 {
1126         PMD_INIT_FUNC_TRACE();
1127
1128         rte_eth_driver_register(&rte_ixgbe_pmd);
1129         return 0;
1130 }
1131
1132 /*
1133  * VF Driver initialization routine.
1134  * Invoked one at EAL init time.
1135  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1136  */
1137 static int
1138 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1139 {
1140         PMD_INIT_FUNC_TRACE();
1141
1142         rte_eth_driver_register(&rte_ixgbevf_pmd);
1143         return (0);
1144 }
1145
1146 static int
1147 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1148 {
1149         struct ixgbe_hw *hw =
1150                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1151         struct ixgbe_vfta * shadow_vfta =
1152                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1153         uint32_t vfta;
1154         uint32_t vid_idx;
1155         uint32_t vid_bit;
1156
1157         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1158         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1159         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1160         if (on)
1161                 vfta |= vid_bit;
1162         else
1163                 vfta &= ~vid_bit;
1164         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1165
1166         /* update local VFTA copy */
1167         shadow_vfta->vfta[vid_idx] = vfta;
1168
1169         return 0;
1170 }
1171
1172 static void
1173 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1174 {
1175         if (on)
1176                 ixgbe_vlan_hw_strip_enable(dev, queue);
1177         else
1178                 ixgbe_vlan_hw_strip_disable(dev, queue);
1179 }
1180
1181 static void
1182 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1183 {
1184         struct ixgbe_hw *hw =
1185                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1186
1187         /* Only the high 16-bits is valid */
1188         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1189 }
1190
1191 void
1192 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1193 {
1194         struct ixgbe_hw *hw =
1195                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1196         uint32_t vlnctrl;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         /* Filter Table Disable */
1201         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1202         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1203
1204         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1205 }
1206
1207 void
1208 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1209 {
1210         struct ixgbe_hw *hw =
1211                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1212         struct ixgbe_vfta * shadow_vfta =
1213                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1214         uint32_t vlnctrl;
1215         uint16_t i;
1216
1217         PMD_INIT_FUNC_TRACE();
1218
1219         /* Filter Table Enable */
1220         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1221         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1222         vlnctrl |= IXGBE_VLNCTRL_VFE;
1223
1224         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1225
1226         /* write whatever is in local vfta copy */
1227         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1228                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1229 }
1230
1231 static void
1232 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1233 {
1234         struct ixgbe_hwstrip *hwstrip =
1235                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1236
1237         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1238                 return;
1239
1240         if (on)
1241                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1242         else
1243                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1244 }
1245
1246 static void
1247 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1248 {
1249         struct ixgbe_hw *hw =
1250                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1251         uint32_t ctrl;
1252
1253         PMD_INIT_FUNC_TRACE();
1254
1255         if (hw->mac.type == ixgbe_mac_82598EB) {
1256                 /* No queue level support */
1257                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1258                 return;
1259         }
1260         else {
1261                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1262                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1263                 ctrl &= ~IXGBE_RXDCTL_VME;
1264                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1265         }
1266         /* record those setting for HW strip per queue */
1267         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1268 }
1269
1270 static void
1271 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1272 {
1273         struct ixgbe_hw *hw =
1274                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1275         uint32_t ctrl;
1276
1277         PMD_INIT_FUNC_TRACE();
1278
1279         if (hw->mac.type == ixgbe_mac_82598EB) {
1280                 /* No queue level supported */
1281                 PMD_INIT_LOG(INFO, "82598EB not support queue level hw strip");
1282                 return;
1283         }
1284         else {
1285                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1286                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1287                 ctrl |= IXGBE_RXDCTL_VME;
1288                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1289         }
1290         /* record those setting for HW strip per queue */
1291         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1292 }
1293
1294 void
1295 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1296 {
1297         struct ixgbe_hw *hw =
1298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1299         uint32_t ctrl;
1300         uint16_t i;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         if (hw->mac.type == ixgbe_mac_82598EB) {
1305                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1306                 ctrl &= ~IXGBE_VLNCTRL_VME;
1307                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1308         }
1309         else {
1310                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1311                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1312                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1313                         ctrl &= ~IXGBE_RXDCTL_VME;
1314                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1315
1316                         /* record those setting for HW strip per queue */
1317                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1318                 }
1319         }
1320 }
1321
1322 void
1323 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1324 {
1325         struct ixgbe_hw *hw =
1326                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1327         uint32_t ctrl;
1328         uint16_t i;
1329
1330         PMD_INIT_FUNC_TRACE();
1331
1332         if (hw->mac.type == ixgbe_mac_82598EB) {
1333                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1334                 ctrl |= IXGBE_VLNCTRL_VME;
1335                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1336         }
1337         else {
1338                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1339                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1340                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1341                         ctrl |= IXGBE_RXDCTL_VME;
1342                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1343
1344                         /* record those setting for HW strip per queue */
1345                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1346                 }
1347         }
1348 }
1349
1350 static void
1351 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1352 {
1353         struct ixgbe_hw *hw =
1354                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355         uint32_t ctrl;
1356
1357         PMD_INIT_FUNC_TRACE();
1358
1359         /* DMATXCTRL: Geric Double VLAN Disable */
1360         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1361         ctrl &= ~IXGBE_DMATXCTL_GDV;
1362         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1363
1364         /* CTRL_EXT: Global Double VLAN Disable */
1365         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1366         ctrl &= ~IXGBE_EXTENDED_VLAN;
1367         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1368
1369 }
1370
1371 static void
1372 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1373 {
1374         struct ixgbe_hw *hw =
1375                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         uint32_t ctrl;
1377
1378         PMD_INIT_FUNC_TRACE();
1379
1380         /* DMATXCTRL: Geric Double VLAN Enable */
1381         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1382         ctrl |= IXGBE_DMATXCTL_GDV;
1383         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1384
1385         /* CTRL_EXT: Global Double VLAN Enable */
1386         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1387         ctrl |= IXGBE_EXTENDED_VLAN;
1388         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1389
1390         /*
1391          * VET EXT field in the EXVET register = 0x8100 by default
1392          * So no need to change. Same to VT field of DMATXCTL register
1393          */
1394 }
1395
1396 static void
1397 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1398 {
1399         if(mask & ETH_VLAN_STRIP_MASK){
1400                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1401                         ixgbe_vlan_hw_strip_enable_all(dev);
1402                 else
1403                         ixgbe_vlan_hw_strip_disable_all(dev);
1404         }
1405
1406         if(mask & ETH_VLAN_FILTER_MASK){
1407                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1408                         ixgbe_vlan_hw_filter_enable(dev);
1409                 else
1410                         ixgbe_vlan_hw_filter_disable(dev);
1411         }
1412
1413         if(mask & ETH_VLAN_EXTEND_MASK){
1414                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1415                         ixgbe_vlan_hw_extend_enable(dev);
1416                 else
1417                         ixgbe_vlan_hw_extend_disable(dev);
1418         }
1419 }
1420
1421 static void
1422 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1423 {
1424         struct ixgbe_hw *hw =
1425                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1427         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1428         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1429         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1430 }
1431
1432 static int
1433 ixgbe_dev_configure(struct rte_eth_dev *dev)
1434 {
1435         struct ixgbe_interrupt *intr =
1436                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1437         struct ixgbe_adapter *adapter =
1438                 (struct ixgbe_adapter *)dev->data->dev_private;
1439
1440         PMD_INIT_FUNC_TRACE();
1441
1442         /* set flag to update link status after init */
1443         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1444
1445         /*
1446          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1447          * allocation or vector Rx preconditions we will reset it.
1448          */
1449         adapter->rx_bulk_alloc_allowed = true;
1450         adapter->rx_vec_allowed = true;
1451
1452         return 0;
1453 }
1454
1455 /*
1456  * Configure device link speed and setup link.
1457  * It returns 0 on success.
1458  */
1459 static int
1460 ixgbe_dev_start(struct rte_eth_dev *dev)
1461 {
1462         struct ixgbe_hw *hw =
1463                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1464         struct ixgbe_vf_info *vfinfo =
1465                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1466         int err, link_up = 0, negotiate = 0;
1467         uint32_t speed = 0;
1468         int mask = 0;
1469         int status;
1470         uint16_t vf, idx;
1471
1472         PMD_INIT_FUNC_TRACE();
1473
1474         /* IXGBE devices don't support half duplex */
1475         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1476                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1477                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1478                              dev->data->dev_conf.link_duplex,
1479                              dev->data->port_id);
1480                 return -EINVAL;
1481         }
1482
1483         /* stop adapter */
1484         hw->adapter_stopped = FALSE;
1485         ixgbe_stop_adapter(hw);
1486
1487         /* reinitialize adapter
1488          * this calls reset and start */
1489         status = ixgbe_pf_reset_hw(hw);
1490         if (status != 0)
1491                 return -1;
1492         hw->mac.ops.start_hw(hw);
1493         hw->mac.get_link_status = true;
1494
1495         /* configure PF module if SRIOV enabled */
1496         ixgbe_pf_host_configure(dev);
1497
1498         /* initialize transmission unit */
1499         ixgbe_dev_tx_init(dev);
1500
1501         /* This can fail when allocating mbufs for descriptor rings */
1502         err = ixgbe_dev_rx_init(dev);
1503         if (err) {
1504                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1505                 goto error;
1506         }
1507
1508         err = ixgbe_dev_rxtx_start(dev);
1509         if (err < 0) {
1510                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1511                 goto error;
1512         }
1513
1514         /* Skip link setup if loopback mode is enabled for 82599. */
1515         if (hw->mac.type == ixgbe_mac_82599EB &&
1516                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
1517                 goto skip_link_setup;
1518
1519         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1520                 err = hw->mac.ops.setup_sfp(hw);
1521                 if (err)
1522                         goto error;
1523         }
1524
1525         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1526                 /* Turn on the copper */
1527                 ixgbe_set_phy_power(hw, true);
1528         } else {
1529                 /* Turn on the laser */
1530                 ixgbe_enable_tx_laser(hw);
1531         }
1532
1533         err = ixgbe_check_link(hw, &speed, &link_up, 0);
1534         if (err)
1535                 goto error;
1536         dev->data->dev_link.link_status = link_up;
1537
1538         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
1539         if (err)
1540                 goto error;
1541
1542         switch(dev->data->dev_conf.link_speed) {
1543         case ETH_LINK_SPEED_AUTONEG:
1544                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
1545                                 IXGBE_LINK_SPEED_82599_AUTONEG :
1546                                 IXGBE_LINK_SPEED_82598_AUTONEG;
1547                 break;
1548         case ETH_LINK_SPEED_100:
1549                 /*
1550                  * Invalid for 82598 but error will be detected by
1551                  * ixgbe_setup_link()
1552                  */
1553                 speed = IXGBE_LINK_SPEED_100_FULL;
1554                 break;
1555         case ETH_LINK_SPEED_1000:
1556                 speed = IXGBE_LINK_SPEED_1GB_FULL;
1557                 break;
1558         case ETH_LINK_SPEED_10000:
1559                 speed = IXGBE_LINK_SPEED_10GB_FULL;
1560                 break;
1561         default:
1562                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
1563                              dev->data->dev_conf.link_speed,
1564                              dev->data->port_id);
1565                 goto error;
1566         }
1567
1568         err = ixgbe_setup_link(hw, speed, link_up);
1569         if (err)
1570                 goto error;
1571
1572 skip_link_setup:
1573
1574         /* check if lsc interrupt is enabled */
1575         if (dev->data->dev_conf.intr_conf.lsc != 0)
1576                 ixgbe_dev_lsc_interrupt_setup(dev);
1577
1578         /* resume enabled intr since hw reset */
1579         ixgbe_enable_intr(dev);
1580
1581         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
1582                 ETH_VLAN_EXTEND_MASK;
1583         ixgbe_vlan_offload_set(dev, mask);
1584
1585         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1586                 /* Enable vlan filtering for VMDq */
1587                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
1588         }
1589
1590         /* Configure DCB hw */
1591         ixgbe_configure_dcb(dev);
1592
1593         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1594                 err = ixgbe_fdir_configure(dev);
1595                 if (err)
1596                         goto error;
1597         }
1598
1599         /* Restore vf rate limit */
1600         if (vfinfo != NULL) {
1601                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
1602                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1603                                 if (vfinfo[vf].tx_rate[idx] != 0)
1604                                         ixgbe_set_vf_rate_limit(dev, vf,
1605                                                 vfinfo[vf].tx_rate[idx],
1606                                                 1 << idx);
1607         }
1608
1609         ixgbe_restore_statistics_mapping(dev);
1610
1611         return (0);
1612
1613 error:
1614         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
1615         ixgbe_dev_clear_queues(dev);
1616         return -EIO;
1617 }
1618
1619 /*
1620  * Stop device: disable rx and tx functions to allow for reconfiguring.
1621  */
1622 static void
1623 ixgbe_dev_stop(struct rte_eth_dev *dev)
1624 {
1625         struct rte_eth_link link;
1626         struct ixgbe_hw *hw =
1627                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1628         struct ixgbe_vf_info *vfinfo =
1629                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1630         struct ixgbe_filter_info *filter_info =
1631                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
1632         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
1633         int vf;
1634
1635         PMD_INIT_FUNC_TRACE();
1636
1637         /* disable interrupts */
1638         ixgbe_disable_intr(hw);
1639
1640         /* reset the NIC */
1641         ixgbe_pf_reset_hw(hw);
1642         hw->adapter_stopped = FALSE;
1643
1644         /* stop adapter */
1645         ixgbe_stop_adapter(hw);
1646
1647         for (vf = 0; vfinfo != NULL &&
1648                      vf < dev->pci_dev->max_vfs; vf++)
1649                 vfinfo[vf].clear_to_send = false;
1650
1651         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1652                 /* Turn off the copper */
1653                 ixgbe_set_phy_power(hw, false);
1654         } else {
1655                 /* Turn off the laser */
1656                 ixgbe_disable_tx_laser(hw);
1657         }
1658
1659         ixgbe_dev_clear_queues(dev);
1660
1661         /* Clear stored conf */
1662         dev->data->scattered_rx = 0;
1663         dev->data->lro = 0;
1664
1665         /* Clear recorded link status */
1666         memset(&link, 0, sizeof(link));
1667         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
1668
1669         /* Remove all ntuple filters of the device */
1670         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
1671              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
1672                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
1673                 TAILQ_REMOVE(&filter_info->fivetuple_list,
1674                              p_5tuple, entries);
1675                 rte_free(p_5tuple);
1676         }
1677         memset(filter_info->fivetuple_mask, 0,
1678                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1679
1680 }
1681
1682 /*
1683  * Set device link up: enable tx.
1684  */
1685 static int
1686 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
1687 {
1688         struct ixgbe_hw *hw =
1689                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1690         if (hw->mac.type == ixgbe_mac_82599EB) {
1691 #ifdef RTE_NIC_BYPASS
1692                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1693                         /* Not suported in bypass mode */
1694                         PMD_INIT_LOG(ERR, "Set link up is not supported "
1695                                      "by device id 0x%x", hw->device_id);
1696                         return -ENOTSUP;
1697                 }
1698 #endif
1699         }
1700
1701         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1702                 /* Turn on the copper */
1703                 ixgbe_set_phy_power(hw, true);
1704         } else {
1705                 /* Turn on the laser */
1706                 ixgbe_enable_tx_laser(hw);
1707         }
1708
1709         return 0;
1710 }
1711
1712 /*
1713  * Set device link down: disable tx.
1714  */
1715 static int
1716 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
1717 {
1718         struct ixgbe_hw *hw =
1719                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720         if (hw->mac.type == ixgbe_mac_82599EB) {
1721 #ifdef RTE_NIC_BYPASS
1722                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
1723                         /* Not suported in bypass mode */
1724                         PMD_INIT_LOG(ERR, "Set link down is not supported "
1725                                      "by device id 0x%x", hw->device_id);
1726                         return -ENOTSUP;
1727                 }
1728 #endif
1729         }
1730
1731         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
1732                 /* Turn off the copper */
1733                 ixgbe_set_phy_power(hw, false);
1734         } else {
1735                 /* Turn off the laser */
1736                 ixgbe_disable_tx_laser(hw);
1737         }
1738
1739         return 0;
1740 }
1741
1742 /*
1743  * Reest and stop device.
1744  */
1745 static void
1746 ixgbe_dev_close(struct rte_eth_dev *dev)
1747 {
1748         struct ixgbe_hw *hw =
1749                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1750
1751         PMD_INIT_FUNC_TRACE();
1752
1753         ixgbe_pf_reset_hw(hw);
1754
1755         ixgbe_dev_stop(dev);
1756         hw->adapter_stopped = 1;
1757
1758         ixgbe_disable_pcie_master(hw);
1759
1760         /* reprogram the RAR[0] in case user changed it. */
1761         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1762 }
1763
1764 /*
1765  * This function is based on ixgbe_update_stats_counters() in base/ixgbe.c
1766  */
1767 static void
1768 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1769 {
1770         struct ixgbe_hw *hw =
1771                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772         struct ixgbe_hw_stats *hw_stats =
1773                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1774         uint32_t bprc, lxon, lxoff, total;
1775         uint64_t total_missed_rx, total_qbrc, total_qprc;
1776         unsigned i;
1777
1778         total_missed_rx = 0;
1779         total_qbrc = 0;
1780         total_qprc = 0;
1781
1782         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1783         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
1784         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
1785         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
1786
1787         for (i = 0; i < 8; i++) {
1788                 uint32_t mp;
1789                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
1790                 /* global total per queue */
1791                 hw_stats->mpc[i] += mp;
1792                 /* Running comprehensive total for stats display */
1793                 total_missed_rx += hw_stats->mpc[i];
1794                 if (hw->mac.type == ixgbe_mac_82598EB)
1795                         hw_stats->rnbc[i] +=
1796                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
1797                 hw_stats->pxontxc[i] +=
1798                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
1799                 hw_stats->pxonrxc[i] +=
1800                     IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
1801                 hw_stats->pxofftxc[i] +=
1802                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
1803                 hw_stats->pxoffrxc[i] +=
1804                     IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
1805                 hw_stats->pxon2offc[i] +=
1806                     IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
1807         }
1808         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1809                 hw_stats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
1810                 hw_stats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
1811                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
1812                 hw_stats->qbrc[i] +=
1813                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
1814                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
1815                 hw_stats->qbtc[i] +=
1816                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
1817                 hw_stats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
1818
1819                 total_qprc += hw_stats->qprc[i];
1820                 total_qbrc += hw_stats->qbrc[i];
1821         }
1822         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
1823         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
1824         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
1825
1826         /* Note that gprc counts missed packets */
1827         hw_stats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
1828
1829         if (hw->mac.type != ixgbe_mac_82598EB) {
1830                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
1831                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
1832                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
1833                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
1834                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
1835                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
1836                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
1837                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
1838         } else {
1839                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
1840                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
1841                 /* 82598 only has a counter in the high register */
1842                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
1843                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
1844                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
1845         }
1846
1847         /*
1848          * Workaround: mprc hardware is incorrectly counting
1849          * broadcasts, so for now we subtract those.
1850          */
1851         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
1852         hw_stats->bprc += bprc;
1853         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
1854         if (hw->mac.type == ixgbe_mac_82598EB)
1855                 hw_stats->mprc -= bprc;
1856
1857         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
1858         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
1859         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
1860         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
1861         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
1862         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
1863
1864         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
1865         hw_stats->lxontxc += lxon;
1866         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
1867         hw_stats->lxofftxc += lxoff;
1868         total = lxon + lxoff;
1869
1870         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
1871         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
1872         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
1873         hw_stats->gptc -= total;
1874         hw_stats->mptc -= total;
1875         hw_stats->ptc64 -= total;
1876         hw_stats->gotc -= total * ETHER_MIN_LEN;
1877
1878         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
1879         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
1880         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
1881         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
1882         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
1883         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
1884         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
1885         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
1886         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
1887         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
1888         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
1889         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
1890         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
1891         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
1892         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
1893         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
1894         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
1895         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
1896         /* Only read FCOE on 82599 */
1897         if (hw->mac.type != ixgbe_mac_82598EB) {
1898                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
1899                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
1900                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
1901                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
1902                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
1903         }
1904
1905         if (stats == NULL)
1906                 return;
1907
1908         /* Fill out the rte_eth_stats statistics structure */
1909         stats->ipackets = total_qprc;
1910         stats->ibytes = total_qbrc;
1911         stats->opackets = hw_stats->gptc;
1912         stats->obytes = hw_stats->gotc;
1913         stats->imcasts = hw_stats->mprc;
1914
1915         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
1916                 stats->q_ipackets[i] = hw_stats->qprc[i];
1917                 stats->q_opackets[i] = hw_stats->qptc[i];
1918                 stats->q_ibytes[i] = hw_stats->qbrc[i];
1919                 stats->q_obytes[i] = hw_stats->qbtc[i];
1920                 stats->q_errors[i] = hw_stats->qprdc[i];
1921         }
1922
1923         /* Rx Errors */
1924         stats->ibadcrc  = hw_stats->crcerrs;
1925         stats->ibadlen  = hw_stats->rlec + hw_stats->ruc + hw_stats->roc;
1926         stats->imissed  = total_missed_rx;
1927         stats->ierrors  = stats->ibadcrc +
1928                           stats->ibadlen +
1929                           stats->imissed +
1930                           hw_stats->illerrc + hw_stats->errbc;
1931
1932         /* Tx Errors */
1933         stats->oerrors  = 0;
1934
1935         /* XON/XOFF pause frames */
1936         stats->tx_pause_xon  = hw_stats->lxontxc;
1937         stats->rx_pause_xon  = hw_stats->lxonrxc;
1938         stats->tx_pause_xoff = hw_stats->lxofftxc;
1939         stats->rx_pause_xoff = hw_stats->lxoffrxc;
1940
1941         /* Flow Director Stats registers */
1942         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1943         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1944         stats->fdirmatch = hw_stats->fdirmatch;
1945         stats->fdirmiss = hw_stats->fdirmiss;
1946 }
1947
1948 static void
1949 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
1950 {
1951         struct ixgbe_hw_stats *stats =
1952                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1953
1954         /* HW registers are cleared on read */
1955         ixgbe_dev_stats_get(dev, NULL);
1956
1957         /* Reset software totals */
1958         memset(stats, 0, sizeof(*stats));
1959 }
1960
1961 static void
1962 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1963 {
1964         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1965         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
1966                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
1967
1968         /* Good Rx packet, include VF loopback */
1969         UPDATE_VF_STAT(IXGBE_VFGPRC,
1970             hw_stats->last_vfgprc, hw_stats->vfgprc);
1971
1972         /* Good Rx octets, include VF loopback */
1973         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
1974             hw_stats->last_vfgorc, hw_stats->vfgorc);
1975
1976         /* Good Tx packet, include VF loopback */
1977         UPDATE_VF_STAT(IXGBE_VFGPTC,
1978             hw_stats->last_vfgptc, hw_stats->vfgptc);
1979
1980         /* Good Tx octets, include VF loopback */
1981         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
1982             hw_stats->last_vfgotc, hw_stats->vfgotc);
1983
1984         /* Rx Multicst Packet */
1985         UPDATE_VF_STAT(IXGBE_VFMPRC,
1986             hw_stats->last_vfmprc, hw_stats->vfmprc);
1987
1988         if (stats == NULL)
1989                 return;
1990
1991         stats->ipackets = hw_stats->vfgprc;
1992         stats->ibytes = hw_stats->vfgorc;
1993         stats->opackets = hw_stats->vfgptc;
1994         stats->obytes = hw_stats->vfgotc;
1995         stats->imcasts = hw_stats->vfmprc;
1996 }
1997
1998 static void
1999 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2000 {
2001         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2002                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2003
2004         /* Sync HW register to the last stats */
2005         ixgbevf_dev_stats_get(dev, NULL);
2006
2007         /* reset HW current stats*/
2008         hw_stats->vfgprc = 0;
2009         hw_stats->vfgorc = 0;
2010         hw_stats->vfgptc = 0;
2011         hw_stats->vfgotc = 0;
2012         hw_stats->vfmprc = 0;
2013
2014 }
2015
2016 static void
2017 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2018 {
2019         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2020
2021         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2022         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2023         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2024         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2025         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2026         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2027         dev_info->max_vfs = dev->pci_dev->max_vfs;
2028         if (hw->mac.type == ixgbe_mac_82598EB)
2029                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2030         else
2031                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2032         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2033         dev_info->rx_offload_capa =
2034                 DEV_RX_OFFLOAD_VLAN_STRIP |
2035                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2036                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2037                 DEV_RX_OFFLOAD_TCP_CKSUM;
2038
2039         /*
2040          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2041          * mode.
2042          */
2043         if ((hw->mac.type == ixgbe_mac_82599EB ||
2044              hw->mac.type == ixgbe_mac_X540) &&
2045             !RTE_ETH_DEV_SRIOV(dev).active)
2046                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2047
2048         dev_info->tx_offload_capa =
2049                 DEV_TX_OFFLOAD_VLAN_INSERT |
2050                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2051                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2052                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2053                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2054                 DEV_TX_OFFLOAD_TCP_TSO;
2055
2056         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2057                 .rx_thresh = {
2058                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2059                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2060                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2061                 },
2062                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2063                 .rx_drop_en = 0,
2064         };
2065
2066         dev_info->default_txconf = (struct rte_eth_txconf) {
2067                 .tx_thresh = {
2068                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2069                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2070                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2071                 },
2072                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2073                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2074                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2075                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2076         };
2077         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2078         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2079 }
2080
2081 static void
2082 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2083                      struct rte_eth_dev_info *dev_info)
2084 {
2085         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2086
2087         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2088         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2089         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2090         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2091         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2092         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2093         dev_info->max_vfs = dev->pci_dev->max_vfs;
2094         if (hw->mac.type == ixgbe_mac_82598EB)
2095                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2096         else
2097                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2098         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2099                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2100                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2101                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2102         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2103                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2104                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2105                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2106                                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2107
2108         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2109                 .rx_thresh = {
2110                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2111                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2112                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2113                 },
2114                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2115                 .rx_drop_en = 0,
2116         };
2117
2118         dev_info->default_txconf = (struct rte_eth_txconf) {
2119                 .tx_thresh = {
2120                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2121                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2122                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2123                 },
2124                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2125                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2126                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2127                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2128         };
2129 }
2130
2131 /* return 0 means link status changed, -1 means not changed */
2132 static int
2133 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2134 {
2135         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2136         struct rte_eth_link link, old;
2137         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2138         int link_up;
2139         int diag;
2140
2141         link.link_status = 0;
2142         link.link_speed = 0;
2143         link.link_duplex = 0;
2144         memset(&old, 0, sizeof(old));
2145         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2146
2147         hw->mac.get_link_status = true;
2148
2149         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2150         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2151                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2152         else
2153                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2154
2155         if (diag != 0) {
2156                 link.link_speed = ETH_LINK_SPEED_100;
2157                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2158                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2159                 if (link.link_status == old.link_status)
2160                         return -1;
2161                 return 0;
2162         }
2163
2164         if (link_up == 0) {
2165                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2166                 if (link.link_status == old.link_status)
2167                         return -1;
2168                 return 0;
2169         }
2170         link.link_status = 1;
2171         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2172
2173         switch (link_speed) {
2174         default:
2175         case IXGBE_LINK_SPEED_UNKNOWN:
2176                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2177                 link.link_speed = ETH_LINK_SPEED_100;
2178                 break;
2179
2180         case IXGBE_LINK_SPEED_100_FULL:
2181                 link.link_speed = ETH_LINK_SPEED_100;
2182                 break;
2183
2184         case IXGBE_LINK_SPEED_1GB_FULL:
2185                 link.link_speed = ETH_LINK_SPEED_1000;
2186                 break;
2187
2188         case IXGBE_LINK_SPEED_10GB_FULL:
2189                 link.link_speed = ETH_LINK_SPEED_10000;
2190                 break;
2191         }
2192         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2193
2194         if (link.link_status == old.link_status)
2195                 return -1;
2196
2197         return 0;
2198 }
2199
2200 static void
2201 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2202 {
2203         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2204         uint32_t fctrl;
2205
2206         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2207         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2208         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2209 }
2210
2211 static void
2212 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2213 {
2214         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2215         uint32_t fctrl;
2216
2217         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2218         fctrl &= (~IXGBE_FCTRL_UPE);
2219         if (dev->data->all_multicast == 1)
2220                 fctrl |= IXGBE_FCTRL_MPE;
2221         else
2222                 fctrl &= (~IXGBE_FCTRL_MPE);
2223         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2224 }
2225
2226 static void
2227 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2228 {
2229         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2230         uint32_t fctrl;
2231
2232         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2233         fctrl |= IXGBE_FCTRL_MPE;
2234         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2235 }
2236
2237 static void
2238 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2239 {
2240         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2241         uint32_t fctrl;
2242
2243         if (dev->data->promiscuous == 1)
2244                 return; /* must remain in all_multicast mode */
2245
2246         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2247         fctrl &= (~IXGBE_FCTRL_MPE);
2248         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2249 }
2250
2251 /**
2252  * It clears the interrupt causes and enables the interrupt.
2253  * It will be called once only during nic initialized.
2254  *
2255  * @param dev
2256  *  Pointer to struct rte_eth_dev.
2257  *
2258  * @return
2259  *  - On success, zero.
2260  *  - On failure, a negative value.
2261  */
2262 static int
2263 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
2264 {
2265         struct ixgbe_interrupt *intr =
2266                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2267
2268         ixgbe_dev_link_status_print(dev);
2269         intr->mask |= IXGBE_EICR_LSC;
2270
2271         return 0;
2272 }
2273
2274 /*
2275  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
2276  *
2277  * @param dev
2278  *  Pointer to struct rte_eth_dev.
2279  *
2280  * @return
2281  *  - On success, zero.
2282  *  - On failure, a negative value.
2283  */
2284 static int
2285 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2286 {
2287         uint32_t eicr;
2288         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2289         struct ixgbe_interrupt *intr =
2290                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2291
2292         /* clear all cause mask */
2293         ixgbe_disable_intr(hw);
2294
2295         /* read-on-clear nic registers here */
2296         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2297         PMD_DRV_LOG(INFO, "eicr %x", eicr);
2298
2299         intr->flags = 0;
2300         if (eicr & IXGBE_EICR_LSC) {
2301                 /* set flag for async link update */
2302                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2303         }
2304
2305         if (eicr & IXGBE_EICR_MAILBOX)
2306                 intr->flags |= IXGBE_FLAG_MAILBOX;
2307
2308         return 0;
2309 }
2310
2311 /**
2312  * It gets and then prints the link status.
2313  *
2314  * @param dev
2315  *  Pointer to struct rte_eth_dev.
2316  *
2317  * @return
2318  *  - On success, zero.
2319  *  - On failure, a negative value.
2320  */
2321 static void
2322 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
2323 {
2324         struct rte_eth_link link;
2325
2326         memset(&link, 0, sizeof(link));
2327         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2328         if (link.link_status) {
2329                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2330                                         (int)(dev->data->port_id),
2331                                         (unsigned)link.link_speed,
2332                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2333                                         "full-duplex" : "half-duplex");
2334         } else {
2335                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2336                                 (int)(dev->data->port_id));
2337         }
2338         PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
2339                                 dev->pci_dev->addr.domain,
2340                                 dev->pci_dev->addr.bus,
2341                                 dev->pci_dev->addr.devid,
2342                                 dev->pci_dev->addr.function);
2343 }
2344
2345 /*
2346  * It executes link_update after knowing an interrupt occurred.
2347  *
2348  * @param dev
2349  *  Pointer to struct rte_eth_dev.
2350  *
2351  * @return
2352  *  - On success, zero.
2353  *  - On failure, a negative value.
2354  */
2355 static int
2356 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
2357 {
2358         struct ixgbe_interrupt *intr =
2359                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2360         int64_t timeout;
2361         struct rte_eth_link link;
2362         int intr_enable_delay = false;
2363
2364         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
2365
2366         if (intr->flags & IXGBE_FLAG_MAILBOX) {
2367                 ixgbe_pf_mbx_process(dev);
2368                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
2369         }
2370
2371         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2372                 /* get the link status before link update, for predicting later */
2373                 memset(&link, 0, sizeof(link));
2374                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
2375
2376                 ixgbe_dev_link_update(dev, 0);
2377
2378                 /* likely to up */
2379                 if (!link.link_status)
2380                         /* handle it 1 sec later, wait it being stable */
2381                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
2382                 /* likely to down */
2383                 else
2384                         /* handle it 4 sec later, wait it being stable */
2385                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
2386
2387                 ixgbe_dev_link_status_print(dev);
2388
2389                 intr_enable_delay = true;
2390         }
2391
2392         if (intr_enable_delay) {
2393                 if (rte_eal_alarm_set(timeout * 1000,
2394                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
2395                         PMD_DRV_LOG(ERR, "Error setting alarm");
2396         } else {
2397                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
2398                 ixgbe_enable_intr(dev);
2399                 rte_intr_enable(&(dev->pci_dev->intr_handle));
2400         }
2401
2402
2403         return 0;
2404 }
2405
2406 /**
2407  * Interrupt handler which shall be registered for alarm callback for delayed
2408  * handling specific interrupt to wait for the stable nic state. As the
2409  * NIC interrupt state is not stable for ixgbe after link is just down,
2410  * it needs to wait 4 seconds to get the stable status.
2411  *
2412  * @param handle
2413  *  Pointer to interrupt handle.
2414  * @param param
2415  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2416  *
2417  * @return
2418  *  void
2419  */
2420 static void
2421 ixgbe_dev_interrupt_delayed_handler(void *param)
2422 {
2423         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2424         struct ixgbe_interrupt *intr =
2425                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2426         struct ixgbe_hw *hw =
2427                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428         uint32_t eicr;
2429
2430         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2431         if (eicr & IXGBE_EICR_MAILBOX)
2432                 ixgbe_pf_mbx_process(dev);
2433
2434         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
2435                 ixgbe_dev_link_update(dev, 0);
2436                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
2437                 ixgbe_dev_link_status_print(dev);
2438                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
2439         }
2440
2441         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
2442         ixgbe_enable_intr(dev);
2443         rte_intr_enable(&(dev->pci_dev->intr_handle));
2444 }
2445
2446 /**
2447  * Interrupt handler triggered by NIC  for handling
2448  * specific interrupt.
2449  *
2450  * @param handle
2451  *  Pointer to interrupt handle.
2452  * @param param
2453  *  The address of parameter (struct rte_eth_dev *) regsitered before.
2454  *
2455  * @return
2456  *  void
2457  */
2458 static void
2459 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
2460                                                         void *param)
2461 {
2462         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2463         ixgbe_dev_interrupt_get_status(dev);
2464         ixgbe_dev_interrupt_action(dev);
2465 }
2466
2467 static int
2468 ixgbe_dev_led_on(struct rte_eth_dev *dev)
2469 {
2470         struct ixgbe_hw *hw;
2471
2472         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2473         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2474 }
2475
2476 static int
2477 ixgbe_dev_led_off(struct rte_eth_dev *dev)
2478 {
2479         struct ixgbe_hw *hw;
2480
2481         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2482         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
2483 }
2484
2485 static int
2486 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2487 {
2488         struct ixgbe_hw *hw;
2489         uint32_t mflcn_reg;
2490         uint32_t fccfg_reg;
2491         int rx_pause;
2492         int tx_pause;
2493
2494         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2495
2496         fc_conf->pause_time = hw->fc.pause_time;
2497         fc_conf->high_water = hw->fc.high_water[0];
2498         fc_conf->low_water = hw->fc.low_water[0];
2499         fc_conf->send_xon = hw->fc.send_xon;
2500         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
2501
2502         /*
2503          * Return rx_pause status according to actual setting of
2504          * MFLCN register.
2505          */
2506         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2507         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
2508                 rx_pause = 1;
2509         else
2510                 rx_pause = 0;
2511
2512         /*
2513          * Return tx_pause status according to actual setting of
2514          * FCCFG register.
2515          */
2516         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2517         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
2518                 tx_pause = 1;
2519         else
2520                 tx_pause = 0;
2521
2522         if (rx_pause && tx_pause)
2523                 fc_conf->mode = RTE_FC_FULL;
2524         else if (rx_pause)
2525                 fc_conf->mode = RTE_FC_RX_PAUSE;
2526         else if (tx_pause)
2527                 fc_conf->mode = RTE_FC_TX_PAUSE;
2528         else
2529                 fc_conf->mode = RTE_FC_NONE;
2530
2531         return 0;
2532 }
2533
2534 static int
2535 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2536 {
2537         struct ixgbe_hw *hw;
2538         int err;
2539         uint32_t rx_buf_size;
2540         uint32_t max_high_water;
2541         uint32_t mflcn;
2542         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2543                 ixgbe_fc_none,
2544                 ixgbe_fc_rx_pause,
2545                 ixgbe_fc_tx_pause,
2546                 ixgbe_fc_full
2547         };
2548
2549         PMD_INIT_FUNC_TRACE();
2550
2551         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2552         if (fc_conf->autoneg != !hw->fc.disable_fc_autoneg)
2553                 return -ENOTSUP;
2554         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
2555         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2556
2557         /*
2558          * At least reserve one Ethernet frame for watermark
2559          * high_water/low_water in kilo bytes for ixgbe
2560          */
2561         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2562         if ((fc_conf->high_water > max_high_water) ||
2563                 (fc_conf->high_water < fc_conf->low_water)) {
2564                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2565                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2566                 return (-EINVAL);
2567         }
2568
2569         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
2570         hw->fc.pause_time     = fc_conf->pause_time;
2571         hw->fc.high_water[0]  = fc_conf->high_water;
2572         hw->fc.low_water[0]   = fc_conf->low_water;
2573         hw->fc.send_xon       = fc_conf->send_xon;
2574
2575         err = ixgbe_fc_enable(hw);
2576
2577         /* Not negotiated is not an error case */
2578         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
2579
2580                 /* check if we want to forward MAC frames - driver doesn't have native
2581                  * capability to do that, so we'll write the registers ourselves */
2582
2583                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2584
2585                 /* set or clear MFLCN.PMCF bit depending on configuration */
2586                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2587                         mflcn |= IXGBE_MFLCN_PMCF;
2588                 else
2589                         mflcn &= ~IXGBE_MFLCN_PMCF;
2590
2591                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
2592                 IXGBE_WRITE_FLUSH(hw);
2593
2594                 return 0;
2595         }
2596
2597         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
2598         return -EIO;
2599 }
2600
2601 /**
2602  *  ixgbe_pfc_enable_generic - Enable flow control
2603  *  @hw: pointer to hardware structure
2604  *  @tc_num: traffic class number
2605  *  Enable flow control according to the current settings.
2606  */
2607 static int
2608 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
2609 {
2610         int ret_val = 0;
2611         uint32_t mflcn_reg, fccfg_reg;
2612         uint32_t reg;
2613         uint32_t fcrtl, fcrth;
2614         uint8_t i;
2615         uint8_t nb_rx_en;
2616
2617         /* Validate the water mark configuration */
2618         if (!hw->fc.pause_time) {
2619                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2620                 goto out;
2621         }
2622
2623         /* Low water mark of zero causes XOFF floods */
2624         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
2625                  /* High/Low water can not be 0 */
2626                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
2627                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2628                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2629                         goto out;
2630                 }
2631
2632                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
2633                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
2634                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2635                         goto out;
2636                 }
2637         }
2638         /* Negotiate the fc mode to use */
2639         ixgbe_fc_autoneg(hw);
2640
2641         /* Disable any previous flow control settings */
2642         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2643         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
2644
2645         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2646         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2647
2648         switch (hw->fc.current_mode) {
2649         case ixgbe_fc_none:
2650                 /*
2651                  * If the count of enabled RX Priority Flow control >1,
2652                  * and the TX pause can not be disabled
2653                  */
2654                 nb_rx_en = 0;
2655                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2656                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2657                         if (reg & IXGBE_FCRTH_FCEN)
2658                                 nb_rx_en++;
2659                 }
2660                 if (nb_rx_en > 1)
2661                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2662                 break;
2663         case ixgbe_fc_rx_pause:
2664                 /*
2665                  * Rx Flow control is enabled and Tx Flow control is
2666                  * disabled by software override. Since there really
2667                  * isn't a way to advertise that we are capable of RX
2668                  * Pause ONLY, we will advertise that we support both
2669                  * symmetric and asymmetric Rx PAUSE.  Later, we will
2670                  * disable the adapter's ability to send PAUSE frames.
2671                  */
2672                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2673                 /*
2674                  * If the count of enabled RX Priority Flow control >1,
2675                  * and the TX pause can not be disabled
2676                  */
2677                 nb_rx_en = 0;
2678                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2679                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
2680                         if (reg & IXGBE_FCRTH_FCEN)
2681                                 nb_rx_en++;
2682                 }
2683                 if (nb_rx_en > 1)
2684                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2685                 break;
2686         case ixgbe_fc_tx_pause:
2687                 /*
2688                  * Tx Flow control is enabled, and Rx Flow control is
2689                  * disabled by software override.
2690                  */
2691                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
2692                 break;
2693         case ixgbe_fc_full:
2694                 /* Flow control (both Rx and Tx) is enabled by SW override. */
2695                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
2696                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
2697                 break;
2698         default:
2699                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
2700                 ret_val = IXGBE_ERR_CONFIG;
2701                 goto out;
2702                 break;
2703         }
2704
2705         /* Set 802.3x based flow control settings. */
2706         mflcn_reg |= IXGBE_MFLCN_DPF;
2707         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2708         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2709
2710         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2711         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2712                 hw->fc.high_water[tc_num]) {
2713                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
2714                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
2715                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
2716         } else {
2717                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
2718                 /*
2719                  * In order to prevent Tx hangs when the internal Tx
2720                  * switch is enabled we must set the high water mark
2721                  * to the maximum FCRTH value.  This allows the Tx
2722                  * switch to function even under heavy Rx workloads.
2723                  */
2724                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
2725         }
2726         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
2727
2728         /* Configure pause time (2 TCs per register) */
2729         reg = hw->fc.pause_time * 0x00010001;
2730         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2731                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2732
2733         /* Configure flow control refresh threshold value */
2734         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2735
2736 out:
2737         return ret_val;
2738 }
2739
2740 static int
2741 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
2742 {
2743         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2744         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
2745
2746         if(hw->mac.type != ixgbe_mac_82598EB) {
2747                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
2748         }
2749         return ret_val;
2750 }
2751
2752 static int
2753 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
2754 {
2755         int err;
2756         uint32_t rx_buf_size;
2757         uint32_t max_high_water;
2758         uint8_t tc_num;
2759         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
2760         struct ixgbe_hw *hw =
2761                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         struct ixgbe_dcb_config *dcb_config =
2763                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
2764
2765         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
2766                 ixgbe_fc_none,
2767                 ixgbe_fc_rx_pause,
2768                 ixgbe_fc_tx_pause,
2769                 ixgbe_fc_full
2770         };
2771
2772         PMD_INIT_FUNC_TRACE();
2773
2774         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
2775         tc_num = map[pfc_conf->priority];
2776         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
2777         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2778         /*
2779          * At least reserve one Ethernet frame for watermark
2780          * high_water/low_water in kilo bytes for ixgbe
2781          */
2782         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
2783         if ((pfc_conf->fc.high_water > max_high_water) ||
2784             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
2785                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
2786                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
2787                 return (-EINVAL);
2788         }
2789
2790         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
2791         hw->fc.pause_time = pfc_conf->fc.pause_time;
2792         hw->fc.send_xon = pfc_conf->fc.send_xon;
2793         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
2794         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
2795
2796         err = ixgbe_dcb_pfc_enable(dev,tc_num);
2797
2798         /* Not negotiated is not an error case */
2799         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
2800                 return 0;
2801
2802         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
2803         return -EIO;
2804 }
2805
2806 static int
2807 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
2808                           struct rte_eth_rss_reta_entry64 *reta_conf,
2809                           uint16_t reta_size)
2810 {
2811         uint8_t i, j, mask;
2812         uint32_t reta, r;
2813         uint16_t idx, shift;
2814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815
2816         PMD_INIT_FUNC_TRACE();
2817         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2818                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2819                         "(%d) doesn't match the number hardware can supported "
2820                         "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2821                 return -EINVAL;
2822         }
2823
2824         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
2825                 idx = i / RTE_RETA_GROUP_SIZE;
2826                 shift = i % RTE_RETA_GROUP_SIZE;
2827                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2828                                                 IXGBE_4_BIT_MASK);
2829                 if (!mask)
2830                         continue;
2831                 if (mask == IXGBE_4_BIT_MASK)
2832                         r = 0;
2833                 else
2834                         r = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2835                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2836                         if (mask & (0x1 << j))
2837                                 reta |= reta_conf[idx].reta[shift + j] <<
2838                                                         (CHAR_BIT * j);
2839                         else
2840                                 reta |= r & (IXGBE_8_BIT_MASK <<
2841                                                 (CHAR_BIT * j));
2842                 }
2843                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2844         }
2845
2846         return 0;
2847 }
2848
2849 static int
2850 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
2851                          struct rte_eth_rss_reta_entry64 *reta_conf,
2852                          uint16_t reta_size)
2853 {
2854         uint8_t i, j, mask;
2855         uint32_t reta;
2856         uint16_t idx, shift;
2857         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2858
2859         PMD_INIT_FUNC_TRACE();
2860         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2861                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2862                         "(%d) doesn't match the number hardware can supported "
2863                                 "(%d)\n", reta_size, ETH_RSS_RETA_SIZE_128);
2864                 return -EINVAL;
2865         }
2866
2867         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IXGBE_4_BIT_WIDTH) {
2868                 idx = i / RTE_RETA_GROUP_SIZE;
2869                 shift = i % RTE_RETA_GROUP_SIZE;
2870                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2871                                                 IXGBE_4_BIT_MASK);
2872                 if (!mask)
2873                         continue;
2874
2875                 reta = IXGBE_READ_REG(hw, IXGBE_RETA(i >> 2));
2876                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
2877                         if (mask & (0x1 << j))
2878                                 reta_conf[idx].reta[shift + j] =
2879                                         ((reta >> (CHAR_BIT * j)) &
2880                                                 IXGBE_8_BIT_MASK);
2881                 }
2882         }
2883
2884         return 0;
2885 }
2886
2887 static void
2888 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
2889                                 uint32_t index, uint32_t pool)
2890 {
2891         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2892         uint32_t enable_addr = 1;
2893
2894         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
2895 }
2896
2897 static void
2898 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
2899 {
2900         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901
2902         ixgbe_clear_rar(hw, index);
2903 }
2904
2905 static int
2906 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2907 {
2908         uint32_t hlreg0;
2909         uint32_t maxfrs;
2910         struct ixgbe_hw *hw;
2911         struct rte_eth_dev_info dev_info;
2912         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2913
2914         ixgbe_dev_info_get(dev, &dev_info);
2915
2916         /* check that mtu is within the allowed range */
2917         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
2918                 return -EINVAL;
2919
2920         /* refuse mtu that requires the support of scattered packets when this
2921          * feature has not been enabled before. */
2922         if (!dev->data->scattered_rx &&
2923             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
2924              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
2925                 return -EINVAL;
2926
2927         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2928         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2929
2930         /* switch to jumbo mode if needed */
2931         if (frame_size > ETHER_MAX_LEN) {
2932                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2933                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2934         } else {
2935                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2936                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2937         }
2938         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2939
2940         /* update max frame size */
2941         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2942
2943         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
2944         maxfrs &= 0x0000FFFF;
2945         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
2946         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
2947
2948         return 0;
2949 }
2950
2951 /*
2952  * Virtual Function operations
2953  */
2954 static void
2955 ixgbevf_intr_disable(struct ixgbe_hw *hw)
2956 {
2957         PMD_INIT_FUNC_TRACE();
2958
2959         /* Clear interrupt mask to stop from interrupts being generated */
2960         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
2961
2962         IXGBE_WRITE_FLUSH(hw);
2963 }
2964
2965 static int
2966 ixgbevf_dev_configure(struct rte_eth_dev *dev)
2967 {
2968         struct rte_eth_conf* conf = &dev->data->dev_conf;
2969         struct ixgbe_adapter *adapter =
2970                         (struct ixgbe_adapter *)dev->data->dev_private;
2971
2972         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
2973                      dev->data->port_id);
2974
2975         /*
2976          * VF has no ability to enable/disable HW CRC
2977          * Keep the persistent behavior the same as Host PF
2978          */
2979 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
2980         if (!conf->rxmode.hw_strip_crc) {
2981                 PMD_INIT_LOG(INFO, "VF can't disable HW CRC Strip");
2982                 conf->rxmode.hw_strip_crc = 1;
2983         }
2984 #else
2985         if (conf->rxmode.hw_strip_crc) {
2986                 PMD_INIT_LOG(INFO, "VF can't enable HW CRC Strip");
2987                 conf->rxmode.hw_strip_crc = 0;
2988         }
2989 #endif
2990
2991         /*
2992          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2993          * allocation or vector Rx preconditions we will reset it.
2994          */
2995         adapter->rx_bulk_alloc_allowed = true;
2996         adapter->rx_vec_allowed = true;
2997
2998         return 0;
2999 }
3000
3001 static int
3002 ixgbevf_dev_start(struct rte_eth_dev *dev)
3003 {
3004         struct ixgbe_hw *hw =
3005                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3006         int err, mask = 0;
3007
3008         PMD_INIT_FUNC_TRACE();
3009
3010         hw->mac.ops.reset_hw(hw);
3011         hw->mac.get_link_status = true;
3012
3013         /* negotiate mailbox API version to use with the PF. */
3014         ixgbevf_negotiate_api(hw);
3015
3016         ixgbevf_dev_tx_init(dev);
3017
3018         /* This can fail when allocating mbufs for descriptor rings */
3019         err = ixgbevf_dev_rx_init(dev);
3020         if (err) {
3021                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3022                 ixgbe_dev_clear_queues(dev);
3023                 return err;
3024         }
3025
3026         /* Set vfta */
3027         ixgbevf_set_vfta_all(dev,1);
3028
3029         /* Set HW strip */
3030         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3031                 ETH_VLAN_EXTEND_MASK;
3032         ixgbevf_vlan_offload_set(dev, mask);
3033
3034         ixgbevf_dev_rxtx_start(dev);
3035
3036         return 0;
3037 }
3038
3039 static void
3040 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3041 {
3042         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3043
3044         PMD_INIT_FUNC_TRACE();
3045
3046         hw->adapter_stopped = TRUE;
3047         ixgbe_stop_adapter(hw);
3048
3049         /*
3050           * Clear what we set, but we still keep shadow_vfta to
3051           * restore after device starts
3052           */
3053         ixgbevf_set_vfta_all(dev,0);
3054
3055         /* Clear stored conf */
3056         dev->data->scattered_rx = 0;
3057
3058         ixgbe_dev_clear_queues(dev);
3059 }
3060
3061 static void
3062 ixgbevf_dev_close(struct rte_eth_dev *dev)
3063 {
3064         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3065
3066         PMD_INIT_FUNC_TRACE();
3067
3068         ixgbe_reset_hw(hw);
3069
3070         ixgbevf_dev_stop(dev);
3071
3072         /* reprogram the RAR[0] in case user changed it. */
3073         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3074 }
3075
3076 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3077 {
3078         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079         struct ixgbe_vfta * shadow_vfta =
3080                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3081         int i = 0, j = 0, vfta = 0, mask = 1;
3082
3083         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3084                 vfta = shadow_vfta->vfta[i];
3085                 if(vfta){
3086                         mask = 1;
3087                         for (j = 0; j < 32; j++){
3088                                 if(vfta & mask)
3089                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3090                                 mask<<=1;
3091                         }
3092                 }
3093         }
3094
3095 }
3096
3097 static int
3098 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3099 {
3100         struct ixgbe_hw *hw =
3101                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3102         struct ixgbe_vfta * shadow_vfta =
3103                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3104         uint32_t vid_idx = 0;
3105         uint32_t vid_bit = 0;
3106         int ret = 0;
3107
3108         PMD_INIT_FUNC_TRACE();
3109
3110         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3111         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3112         if(ret){
3113                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3114                 return ret;
3115         }
3116         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3117         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3118
3119         /* Save what we set and retore it after device reset */
3120         if (on)
3121                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3122         else
3123                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3124
3125         return 0;
3126 }
3127
3128 static void
3129 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3130 {
3131         struct ixgbe_hw *hw =
3132                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3133         uint32_t ctrl;
3134
3135         PMD_INIT_FUNC_TRACE();
3136
3137         if(queue >= hw->mac.max_rx_queues)
3138                 return;
3139
3140         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3141         if(on)
3142                 ctrl |= IXGBE_RXDCTL_VME;
3143         else
3144                 ctrl &= ~IXGBE_RXDCTL_VME;
3145         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3146
3147         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3148 }
3149
3150 static void
3151 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3152 {
3153         struct ixgbe_hw *hw =
3154                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3155         uint16_t i;
3156         int on = 0;
3157
3158         /* VF function only support hw strip feature, others are not support */
3159         if(mask & ETH_VLAN_STRIP_MASK){
3160                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
3161
3162                 for(i=0; i < hw->mac.max_rx_queues; i++)
3163                         ixgbevf_vlan_strip_queue_set(dev,i,on);
3164         }
3165 }
3166
3167 static int
3168 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
3169 {
3170         uint32_t reg_val;
3171
3172         /* we only need to do this if VMDq is enabled */
3173         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3174         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
3175                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
3176                 return (-1);
3177         }
3178
3179         return 0;
3180 }
3181
3182 static uint32_t
3183 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
3184 {
3185         uint32_t vector = 0;
3186         switch (hw->mac.mc_filter_type) {
3187         case 0:   /* use bits [47:36] of the address */
3188                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3189                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3190                 break;
3191         case 1:   /* use bits [46:35] of the address */
3192                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3193                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3194                 break;
3195         case 2:   /* use bits [45:34] of the address */
3196                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3197                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3198                 break;
3199         case 3:   /* use bits [43:32] of the address */
3200                 vector = ((uc_addr->addr_bytes[4]) |
3201                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3202                 break;
3203         default:  /* Invalid mc_filter_type */
3204                 break;
3205         }
3206
3207         /* vector can only be 12-bits or boundary will be exceeded */
3208         vector &= 0xFFF;
3209         return vector;
3210 }
3211
3212 static int
3213 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
3214                                uint8_t on)
3215 {
3216         uint32_t vector;
3217         uint32_t uta_idx;
3218         uint32_t reg_val;
3219         uint32_t uta_shift;
3220         uint32_t rc;
3221         const uint32_t ixgbe_uta_idx_mask = 0x7F;
3222         const uint32_t ixgbe_uta_bit_shift = 5;
3223         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
3224         const uint32_t bit1 = 0x1;
3225
3226         struct ixgbe_hw *hw =
3227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3228         struct ixgbe_uta_info *uta_info =
3229                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3230
3231         /* The UTA table only exists on 82599 hardware and newer */
3232         if (hw->mac.type < ixgbe_mac_82599EB)
3233                 return (-ENOTSUP);
3234
3235         vector = ixgbe_uta_vector(hw,mac_addr);
3236         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
3237         uta_shift = vector & ixgbe_uta_bit_mask;
3238
3239         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
3240         if(rc == on)
3241                 return 0;
3242
3243         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
3244         if (on) {
3245                 uta_info->uta_in_use++;
3246                 reg_val |= (bit1 << uta_shift);
3247                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
3248         } else {
3249                 uta_info->uta_in_use--;
3250                 reg_val &= ~(bit1 << uta_shift);
3251                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
3252         }
3253
3254         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
3255
3256         if (uta_info->uta_in_use > 0)
3257                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
3258                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
3259         else
3260                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
3261
3262         return 0;
3263 }
3264
3265 static int
3266 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3267 {
3268         int i;
3269         struct ixgbe_hw *hw =
3270                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3271         struct ixgbe_uta_info *uta_info =
3272                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
3273
3274         /* The UTA table only exists on 82599 hardware and newer */
3275         if (hw->mac.type < ixgbe_mac_82599EB)
3276                 return (-ENOTSUP);
3277
3278         if(on) {
3279                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3280                         uta_info->uta_shadow[i] = ~0;
3281                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3282                 }
3283         } else {
3284                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3285                         uta_info->uta_shadow[i] = 0;
3286                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3287                 }
3288         }
3289         return 0;
3290
3291 }
3292
3293 uint32_t
3294 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3295 {
3296         uint32_t new_val = orig_val;
3297
3298         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3299                 new_val |= IXGBE_VMOLR_AUPE;
3300         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3301                 new_val |= IXGBE_VMOLR_ROMPE;
3302         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3303                 new_val |= IXGBE_VMOLR_ROPE;
3304         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3305                 new_val |= IXGBE_VMOLR_BAM;
3306         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3307                 new_val |= IXGBE_VMOLR_MPE;
3308
3309         return new_val;
3310 }
3311
3312 static int
3313 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
3314                                uint16_t rx_mask, uint8_t on)
3315 {
3316         int val = 0;
3317
3318         struct ixgbe_hw *hw =
3319                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3320         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
3321
3322         if (hw->mac.type == ixgbe_mac_82598EB) {
3323                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
3324                              " on 82599 hardware and newer");
3325                 return (-ENOTSUP);
3326         }
3327         if (ixgbe_vmdq_mode_check(hw) < 0)
3328                 return (-ENOTSUP);
3329
3330         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
3331
3332         if (on)
3333                 vmolr |= val;
3334         else
3335                 vmolr &= ~val;
3336
3337         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
3338
3339         return 0;
3340 }
3341
3342 static int
3343 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3344 {
3345         uint32_t reg,addr;
3346         uint32_t val;
3347         const uint8_t bit1 = 0x1;
3348
3349         struct ixgbe_hw *hw =
3350                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351
3352         if (ixgbe_vmdq_mode_check(hw) < 0)
3353                 return (-ENOTSUP);
3354
3355         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
3356         reg = IXGBE_READ_REG(hw, addr);
3357         val = bit1 << pool;
3358
3359         if (on)
3360                 reg |= val;
3361         else
3362                 reg &= ~val;
3363
3364         IXGBE_WRITE_REG(hw, addr,reg);
3365
3366         return 0;
3367 }
3368
3369 static int
3370 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
3371 {
3372         uint32_t reg,addr;
3373         uint32_t val;
3374         const uint8_t bit1 = 0x1;
3375
3376         struct ixgbe_hw *hw =
3377                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3378
3379         if (ixgbe_vmdq_mode_check(hw) < 0)
3380                 return (-ENOTSUP);
3381
3382         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
3383         reg = IXGBE_READ_REG(hw, addr);
3384         val = bit1 << pool;
3385
3386         if (on)
3387                 reg |= val;
3388         else
3389                 reg &= ~val;
3390
3391         IXGBE_WRITE_REG(hw, addr,reg);
3392
3393         return 0;
3394 }
3395
3396 static int
3397 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
3398                         uint64_t pool_mask, uint8_t vlan_on)
3399 {
3400         int ret = 0;
3401         uint16_t pool_idx;
3402         struct ixgbe_hw *hw =
3403                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3404
3405         if (ixgbe_vmdq_mode_check(hw) < 0)
3406                 return (-ENOTSUP);
3407         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
3408                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
3409                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
3410                         if (ret < 0)
3411                                 return ret;
3412         }
3413
3414         return ret;
3415 }
3416
3417 static int
3418 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
3419                         struct rte_eth_mirror_conf *mirror_conf,
3420                         uint8_t rule_id, uint8_t on)
3421 {
3422         uint32_t mr_ctl,vlvf;
3423         uint32_t mp_lsb = 0;
3424         uint32_t mv_msb = 0;
3425         uint32_t mv_lsb = 0;
3426         uint32_t mp_msb = 0;
3427         uint8_t i = 0;
3428         int reg_index = 0;
3429         uint64_t vlan_mask = 0;
3430
3431         const uint8_t pool_mask_offset = 32;
3432         const uint8_t vlan_mask_offset = 32;
3433         const uint8_t dst_pool_offset = 8;
3434         const uint8_t rule_mr_offset  = 4;
3435         const uint8_t mirror_rule_mask= 0x0F;
3436
3437         struct ixgbe_mirror_info *mr_info =
3438                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3439         struct ixgbe_hw *hw =
3440                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3441
3442         if (ixgbe_vmdq_mode_check(hw) < 0)
3443                 return -ENOTSUP;
3444
3445         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
3446                 return -EINVAL;
3447
3448         /* Check if vlan mask is valid */
3449         if ((mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) && (on)) {
3450                 if (mirror_conf->vlan.vlan_mask == 0)
3451                         return (-EINVAL);
3452         }
3453
3454         /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
3455         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3456                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
3457                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
3458                                 /* search vlan id related pool vlan filter index */
3459                                 reg_index = ixgbe_find_vlvf_slot(hw,
3460                                                 mirror_conf->vlan.vlan_id[i]);
3461                                 if(reg_index < 0)
3462                                         return (-EINVAL);
3463                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
3464                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
3465                                         ((vlvf & IXGBE_VLVF_VLANID_MASK)
3466                                                 == mirror_conf->vlan.vlan_id[i]))
3467                                         vlan_mask |= (1ULL << reg_index);
3468                                 else
3469                                         return (-EINVAL);
3470                         }
3471                 }
3472
3473                 if (on) {
3474                         mv_lsb = vlan_mask & 0xFFFFFFFF;
3475                         mv_msb = vlan_mask >> vlan_mask_offset;
3476
3477                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
3478                                                 mirror_conf->vlan.vlan_mask;
3479                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
3480                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
3481                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
3482                                                 mirror_conf->vlan.vlan_id[i];
3483                         }
3484                 } else {
3485                         mv_lsb = 0;
3486                         mv_msb = 0;
3487                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
3488                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
3489                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
3490                 }
3491         }
3492
3493         /*
3494          * if enable pool mirror, write related pool mask register,if disable
3495          * pool mirror, clear PFMRVM register
3496          */
3497         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3498                 if (on) {
3499                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
3500                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
3501                         mr_info->mr_conf[rule_id].pool_mask =
3502                                         mirror_conf->pool_mask;
3503
3504                 } else {
3505                         mp_lsb = 0;
3506                         mp_msb = 0;
3507                         mr_info->mr_conf[rule_id].pool_mask = 0;
3508                 }
3509         }
3510
3511         /* read  mirror control register and recalculate it */
3512         mr_ctl = IXGBE_READ_REG(hw,IXGBE_MRCTL(rule_id));
3513
3514         if (on) {
3515                 mr_ctl |= mirror_conf->rule_type_mask;
3516                 mr_ctl &= mirror_rule_mask;
3517                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
3518         } else
3519                 mr_ctl &= ~(mirror_conf->rule_type_mask & mirror_rule_mask);
3520
3521         mr_info->mr_conf[rule_id].rule_type_mask = (uint8_t)(mr_ctl & mirror_rule_mask);
3522         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
3523
3524         /* write mirrror control  register */
3525         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3526
3527         /* write pool mirrror control  register */
3528         if (mirror_conf->rule_type_mask & ETH_VMDQ_POOL_MIRROR) {
3529                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
3530                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
3531                                 mp_msb);
3532         }
3533         /* write VLAN mirrror control  register */
3534         if (mirror_conf->rule_type_mask & ETH_VMDQ_VLAN_MIRROR) {
3535                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
3536                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
3537                                 mv_msb);
3538         }
3539
3540         return 0;
3541 }
3542
3543 static int
3544 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
3545 {
3546         int mr_ctl = 0;
3547         uint32_t lsb_val = 0;
3548         uint32_t msb_val = 0;
3549         const uint8_t rule_mr_offset = 4;
3550
3551         struct ixgbe_hw *hw =
3552                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553         struct ixgbe_mirror_info *mr_info =
3554                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
3555
3556         if (ixgbe_vmdq_mode_check(hw) < 0)
3557                 return (-ENOTSUP);
3558
3559         memset(&mr_info->mr_conf[rule_id], 0,
3560                 sizeof(struct rte_eth_mirror_conf));
3561
3562         /* clear PFVMCTL register */
3563         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
3564
3565         /* clear pool mask register */
3566         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
3567         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
3568
3569         /* clear vlan mask register */
3570         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
3571         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
3572
3573         return 0;
3574 }
3575
3576 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3577         uint16_t queue_idx, uint16_t tx_rate)
3578 {
3579         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3580         uint32_t rf_dec, rf_int;
3581         uint32_t bcnrc_val;
3582         uint16_t link_speed = dev->data->dev_link.link_speed;
3583
3584         if (queue_idx >= hw->mac.max_tx_queues)
3585                 return -EINVAL;
3586
3587         if (tx_rate != 0) {
3588                 /* Calculate the rate factor values to set */
3589                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
3590                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
3591                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
3592
3593                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
3594                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
3595                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
3596                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
3597         } else {
3598                 bcnrc_val = 0;
3599         }
3600
3601         /*
3602          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
3603          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
3604          * set as 0x4.
3605          */
3606         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
3607                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
3608                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
3609                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3610                         IXGBE_MMW_SIZE_JUMBO_FRAME);
3611         else
3612                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
3613                         IXGBE_MMW_SIZE_DEFAULT);
3614
3615         /* Set RTTBCNRC of queue X */
3616         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
3617         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
3618         IXGBE_WRITE_FLUSH(hw);
3619
3620         return 0;
3621 }
3622
3623 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
3624         uint16_t tx_rate, uint64_t q_msk)
3625 {
3626         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3627         struct ixgbe_vf_info *vfinfo =
3628                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
3629         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
3630         uint32_t queue_stride =
3631                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
3632         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
3633         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
3634         uint16_t total_rate = 0;
3635
3636         if (queue_end >= hw->mac.max_tx_queues)
3637                 return -EINVAL;
3638
3639         if (vfinfo != NULL) {
3640                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
3641                         if (vf_idx == vf)
3642                                 continue;
3643                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
3644                                 idx++)
3645                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
3646                 }
3647         } else
3648                 return -EINVAL;
3649
3650         /* Store tx_rate for this vf. */
3651         for (idx = 0; idx < nb_q_per_pool; idx++) {
3652                 if (((uint64_t)0x1 << idx) & q_msk) {
3653                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
3654                                 vfinfo[vf].tx_rate[idx] = tx_rate;
3655                         total_rate += tx_rate;
3656                 }
3657         }
3658
3659         if (total_rate > dev->data->dev_link.link_speed) {
3660                 /*
3661                  * Reset stored TX rate of the VF if it causes exceed
3662                  * link speed.
3663                  */
3664                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
3665                 return -EINVAL;
3666         }
3667
3668         /* Set RTTBCNRC of each queue/pool for vf X  */
3669         for (; queue_idx <= queue_end; queue_idx++) {
3670                 if (0x1 & q_msk)
3671                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
3672                 q_msk = q_msk >> 1;
3673         }
3674
3675         return 0;
3676 }
3677
3678 static void
3679 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3680                      __attribute__((unused)) uint32_t index,
3681                      __attribute__((unused)) uint32_t pool)
3682 {
3683         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3684         int diag;
3685
3686         /*
3687          * On a 82599 VF, adding again the same MAC addr is not an idempotent
3688          * operation. Trap this case to avoid exhausting the [very limited]
3689          * set of PF resources used to store VF MAC addresses.
3690          */
3691         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3692                 return;
3693         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3694         if (diag == 0)
3695                 return;
3696         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
3697 }
3698
3699 static void
3700 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
3701 {
3702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3703         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
3704         struct ether_addr *mac_addr;
3705         uint32_t i;
3706         int diag;
3707
3708         /*
3709          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
3710          * not support the deletion of a given MAC address.
3711          * Instead, it imposes to delete all MAC addresses, then to add again
3712          * all MAC addresses with the exception of the one to be deleted.
3713          */
3714         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
3715
3716         /*
3717          * Add again all MAC addresses, with the exception of the deleted one
3718          * and of the permanent MAC address.
3719          */
3720         for (i = 0, mac_addr = dev->data->mac_addrs;
3721              i < hw->mac.num_rar_entries; i++, mac_addr++) {
3722                 /* Skip the deleted MAC address */
3723                 if (i == index)
3724                         continue;
3725                 /* Skip NULL MAC addresses */
3726                 if (is_zero_ether_addr(mac_addr))
3727                         continue;
3728                 /* Skip the permanent MAC address */
3729                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
3730                         continue;
3731                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
3732                 if (diag != 0)
3733                         PMD_DRV_LOG(ERR,
3734                                     "Adding again MAC address "
3735                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
3736                                     "diag=%d",
3737                                     mac_addr->addr_bytes[0],
3738                                     mac_addr->addr_bytes[1],
3739                                     mac_addr->addr_bytes[2],
3740                                     mac_addr->addr_bytes[3],
3741                                     mac_addr->addr_bytes[4],
3742                                     mac_addr->addr_bytes[5],
3743                                     diag);
3744         }
3745 }
3746
3747 #define MAC_TYPE_FILTER_SUP(type)    do {\
3748         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
3749                 (type) != ixgbe_mac_X550)\
3750                 return -ENOTSUP;\
3751 } while (0)
3752
3753 static int
3754 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
3755                         struct rte_eth_syn_filter *filter,
3756                         bool add)
3757 {
3758         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3759         uint32_t synqf;
3760
3761         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
3762                 return -EINVAL;
3763
3764         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3765
3766         if (add) {
3767                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
3768                         return -EINVAL;
3769                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
3770                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
3771
3772                 if (filter->hig_pri)
3773                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
3774                 else
3775                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
3776         } else {
3777                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
3778                         return -ENOENT;
3779                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
3780         }
3781         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
3782         IXGBE_WRITE_FLUSH(hw);
3783         return 0;
3784 }
3785
3786 static int
3787 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
3788                         struct rte_eth_syn_filter *filter)
3789 {
3790         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3791         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
3792
3793         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
3794                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
3795                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
3796                 return 0;
3797         }
3798         return -ENOENT;
3799 }
3800
3801 static int
3802 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
3803                         enum rte_filter_op filter_op,
3804                         void *arg)
3805 {
3806         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         int ret;
3808
3809         MAC_TYPE_FILTER_SUP(hw->mac.type);
3810
3811         if (filter_op == RTE_ETH_FILTER_NOP)
3812                 return 0;
3813
3814         if (arg == NULL) {
3815                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
3816                             filter_op);
3817                 return -EINVAL;
3818         }
3819
3820         switch (filter_op) {
3821         case RTE_ETH_FILTER_ADD:
3822                 ret = ixgbe_syn_filter_set(dev,
3823                                 (struct rte_eth_syn_filter *)arg,
3824                                 TRUE);
3825                 break;
3826         case RTE_ETH_FILTER_DELETE:
3827                 ret = ixgbe_syn_filter_set(dev,
3828                                 (struct rte_eth_syn_filter *)arg,
3829                                 FALSE);
3830                 break;
3831         case RTE_ETH_FILTER_GET:
3832                 ret = ixgbe_syn_filter_get(dev,
3833                                 (struct rte_eth_syn_filter *)arg);
3834                 break;
3835         default:
3836                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
3837                 ret = -EINVAL;
3838                 break;
3839         }
3840
3841         return ret;
3842 }
3843
3844
3845 static inline enum ixgbe_5tuple_protocol
3846 convert_protocol_type(uint8_t protocol_value)
3847 {
3848         if (protocol_value == IPPROTO_TCP)
3849                 return IXGBE_FILTER_PROTOCOL_TCP;
3850         else if (protocol_value == IPPROTO_UDP)
3851                 return IXGBE_FILTER_PROTOCOL_UDP;
3852         else if (protocol_value == IPPROTO_SCTP)
3853                 return IXGBE_FILTER_PROTOCOL_SCTP;
3854         else
3855                 return IXGBE_FILTER_PROTOCOL_NONE;
3856 }
3857
3858 /*
3859  * add a 5tuple filter
3860  *
3861  * @param
3862  * dev: Pointer to struct rte_eth_dev.
3863  * index: the index the filter allocates.
3864  * filter: ponter to the filter that will be added.
3865  * rx_queue: the queue id the filter assigned to.
3866  *
3867  * @return
3868  *    - On success, zero.
3869  *    - On failure, a negative value.
3870  */
3871 static int
3872 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3873                         struct ixgbe_5tuple_filter *filter)
3874 {
3875         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876         struct ixgbe_filter_info *filter_info =
3877                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3878         int i, idx, shift;
3879         uint32_t ftqf, sdpqf;
3880         uint32_t l34timir = 0;
3881         uint8_t mask = 0xff;
3882
3883         /*
3884          * look for an unused 5tuple filter index,
3885          * and insert the filter to list.
3886          */
3887         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
3888                 idx = i / (sizeof(uint32_t) * NBBY);
3889                 shift = i % (sizeof(uint32_t) * NBBY);
3890                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3891                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3892                         filter->index = i;
3893                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3894                                           filter,
3895                                           entries);
3896                         break;
3897                 }
3898         }
3899         if (i >= IXGBE_MAX_FTQF_FILTERS) {
3900                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3901                 return -ENOSYS;
3902         }
3903
3904         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
3905                                 IXGBE_SDPQF_DSTPORT_SHIFT);
3906         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
3907
3908         ftqf = (uint32_t)(filter->filter_info.proto &
3909                 IXGBE_FTQF_PROTOCOL_MASK);
3910         ftqf |= (uint32_t)((filter->filter_info.priority &
3911                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
3912         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3913                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
3914         if (filter->filter_info.dst_ip_mask == 0)
3915                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
3916         if (filter->filter_info.src_port_mask == 0)
3917                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
3918         if (filter->filter_info.dst_port_mask == 0)
3919                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
3920         if (filter->filter_info.proto_mask == 0)
3921                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
3922         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
3923         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
3924         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
3925
3926         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
3927         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
3928         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
3929         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
3930
3931         l34timir |= IXGBE_L34T_IMIR_RESERVE;
3932         l34timir |= (uint32_t)(filter->queue <<
3933                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
3934         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
3935         return 0;
3936 }
3937
3938 /*
3939  * remove a 5tuple filter
3940  *
3941  * @param
3942  * dev: Pointer to struct rte_eth_dev.
3943  * filter: the pointer of the filter will be removed.
3944  */
3945 static void
3946 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3947                         struct ixgbe_5tuple_filter *filter)
3948 {
3949         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3950         struct ixgbe_filter_info *filter_info =
3951                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
3952         uint16_t index = filter->index;
3953
3954         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3955                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3956         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3957         rte_free(filter);
3958
3959         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
3960         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
3961         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
3962         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
3963         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
3964 }
3965
3966 static int
3967 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
3968 {
3969         struct ixgbe_hw *hw;
3970         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3971
3972         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3973
3974         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
3975                 return -EINVAL;
3976
3977         /* refuse mtu that requires the support of scattered packets when this
3978          * feature has not been enabled before. */
3979         if (!dev->data->scattered_rx &&
3980             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
3981              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3982                 return -EINVAL;
3983
3984         /*
3985          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
3986          * request of the version 2.0 of the mailbox API.
3987          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
3988          * of the mailbox API.
3989          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
3990          * prior to 3.11.33 which contains the following change:
3991          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
3992          */
3993         ixgbevf_rlpml_set_vf(hw, max_frame);
3994
3995         /* update max frame size */
3996         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
3997         return 0;
3998 }
3999
4000 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
4001         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
4002                 return -ENOTSUP;\
4003 } while (0)
4004
4005 static inline struct ixgbe_5tuple_filter *
4006 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
4007                         struct ixgbe_5tuple_filter_info *key)
4008 {
4009         struct ixgbe_5tuple_filter *it;
4010
4011         TAILQ_FOREACH(it, filter_list, entries) {
4012                 if (memcmp(key, &it->filter_info,
4013                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
4014                         return it;
4015                 }
4016         }
4017         return NULL;
4018 }
4019
4020 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
4021 static inline int
4022 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
4023                         struct ixgbe_5tuple_filter_info *filter_info)
4024 {
4025         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
4026                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
4027                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
4028                 return -EINVAL;
4029
4030         switch (filter->dst_ip_mask) {
4031         case UINT32_MAX:
4032                 filter_info->dst_ip_mask = 0;
4033                 filter_info->dst_ip = filter->dst_ip;
4034                 break;
4035         case 0:
4036                 filter_info->dst_ip_mask = 1;
4037                 break;
4038         default:
4039                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
4040                 return -EINVAL;
4041         }
4042
4043         switch (filter->src_ip_mask) {
4044         case UINT32_MAX:
4045                 filter_info->src_ip_mask = 0;
4046                 filter_info->src_ip = filter->src_ip;
4047                 break;
4048         case 0:
4049                 filter_info->src_ip_mask = 1;
4050                 break;
4051         default:
4052                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4053                 return -EINVAL;
4054         }
4055
4056         switch (filter->dst_port_mask) {
4057         case UINT16_MAX:
4058                 filter_info->dst_port_mask = 0;
4059                 filter_info->dst_port = filter->dst_port;
4060                 break;
4061         case 0:
4062                 filter_info->dst_port_mask = 1;
4063                 break;
4064         default:
4065                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4066                 return -EINVAL;
4067         }
4068
4069         switch (filter->src_port_mask) {
4070         case UINT16_MAX:
4071                 filter_info->src_port_mask = 0;
4072                 filter_info->src_port = filter->src_port;
4073                 break;
4074         case 0:
4075                 filter_info->src_port_mask = 1;
4076                 break;
4077         default:
4078                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4079                 return -EINVAL;
4080         }
4081
4082         switch (filter->proto_mask) {
4083         case UINT8_MAX:
4084                 filter_info->proto_mask = 0;
4085                 filter_info->proto =
4086                         convert_protocol_type(filter->proto);
4087                 break;
4088         case 0:
4089                 filter_info->proto_mask = 1;
4090                 break;
4091         default:
4092                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4093                 return -EINVAL;
4094         }
4095
4096         filter_info->priority = (uint8_t)filter->priority;
4097         return 0;
4098 }
4099
4100 /*
4101  * add or delete a ntuple filter
4102  *
4103  * @param
4104  * dev: Pointer to struct rte_eth_dev.
4105  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4106  * add: if true, add filter, if false, remove filter
4107  *
4108  * @return
4109  *    - On success, zero.
4110  *    - On failure, a negative value.
4111  */
4112 static int
4113 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4114                         struct rte_eth_ntuple_filter *ntuple_filter,
4115                         bool add)
4116 {
4117         struct ixgbe_filter_info *filter_info =
4118                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4119         struct ixgbe_5tuple_filter_info filter_5tuple;
4120         struct ixgbe_5tuple_filter *filter;
4121         int ret;
4122
4123         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4124                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4125                 return -EINVAL;
4126         }
4127
4128         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4129         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4130         if (ret < 0)
4131                 return ret;
4132
4133         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4134                                          &filter_5tuple);
4135         if (filter != NULL && add) {
4136                 PMD_DRV_LOG(ERR, "filter exists.");
4137                 return -EEXIST;
4138         }
4139         if (filter == NULL && !add) {
4140                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4141                 return -ENOENT;
4142         }
4143
4144         if (add) {
4145                 filter = rte_zmalloc("ixgbe_5tuple_filter",
4146                                 sizeof(struct ixgbe_5tuple_filter), 0);
4147                 if (filter == NULL)
4148                         return -ENOMEM;
4149                 (void)rte_memcpy(&filter->filter_info,
4150                                  &filter_5tuple,
4151                                  sizeof(struct ixgbe_5tuple_filter_info));
4152                 filter->queue = ntuple_filter->queue;
4153                 ret = ixgbe_add_5tuple_filter(dev, filter);
4154                 if (ret < 0) {
4155                         rte_free(filter);
4156                         return ret;
4157                 }
4158         } else
4159                 ixgbe_remove_5tuple_filter(dev, filter);
4160
4161         return 0;
4162 }
4163
4164 /*
4165  * get a ntuple filter
4166  *
4167  * @param
4168  * dev: Pointer to struct rte_eth_dev.
4169  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4170  *
4171  * @return
4172  *    - On success, zero.
4173  *    - On failure, a negative value.
4174  */
4175 static int
4176 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
4177                         struct rte_eth_ntuple_filter *ntuple_filter)
4178 {
4179         struct ixgbe_filter_info *filter_info =
4180                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4181         struct ixgbe_5tuple_filter_info filter_5tuple;
4182         struct ixgbe_5tuple_filter *filter;
4183         int ret;
4184
4185         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4186                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4187                 return -EINVAL;
4188         }
4189
4190         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
4191         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4192         if (ret < 0)
4193                 return ret;
4194
4195         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4196                                          &filter_5tuple);
4197         if (filter == NULL) {
4198                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4199                 return -ENOENT;
4200         }
4201         ntuple_filter->queue = filter->queue;
4202         return 0;
4203 }
4204
4205 /*
4206  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
4207  * @dev: pointer to rte_eth_dev structure
4208  * @filter_op:operation will be taken.
4209  * @arg: a pointer to specific structure corresponding to the filter_op
4210  *
4211  * @return
4212  *    - On success, zero.
4213  *    - On failure, a negative value.
4214  */
4215 static int
4216 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
4217                                 enum rte_filter_op filter_op,
4218                                 void *arg)
4219 {
4220         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4221         int ret;
4222
4223         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
4224
4225         if (filter_op == RTE_ETH_FILTER_NOP)
4226                 return 0;
4227
4228         if (arg == NULL) {
4229                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4230                             filter_op);
4231                 return -EINVAL;
4232         }
4233
4234         switch (filter_op) {
4235         case RTE_ETH_FILTER_ADD:
4236                 ret = ixgbe_add_del_ntuple_filter(dev,
4237                         (struct rte_eth_ntuple_filter *)arg,
4238                         TRUE);
4239                 break;
4240         case RTE_ETH_FILTER_DELETE:
4241                 ret = ixgbe_add_del_ntuple_filter(dev,
4242                         (struct rte_eth_ntuple_filter *)arg,
4243                         FALSE);
4244                 break;
4245         case RTE_ETH_FILTER_GET:
4246                 ret = ixgbe_get_ntuple_filter(dev,
4247                         (struct rte_eth_ntuple_filter *)arg);
4248                 break;
4249         default:
4250                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4251                 ret = -EINVAL;
4252                 break;
4253         }
4254         return ret;
4255 }
4256
4257 static inline int
4258 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
4259                         uint16_t ethertype)
4260 {
4261         int i;
4262
4263         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4264                 if (filter_info->ethertype_filters[i] == ethertype &&
4265                     (filter_info->ethertype_mask & (1 << i)))
4266                         return i;
4267         }
4268         return -1;
4269 }
4270
4271 static inline int
4272 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
4273                         uint16_t ethertype)
4274 {
4275         int i;
4276
4277         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
4278                 if (!(filter_info->ethertype_mask & (1 << i))) {
4279                         filter_info->ethertype_mask |= 1 << i;
4280                         filter_info->ethertype_filters[i] = ethertype;
4281                         return i;
4282                 }
4283         }
4284         return -1;
4285 }
4286
4287 static inline int
4288 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
4289                         uint8_t idx)
4290 {
4291         if (idx >= IXGBE_MAX_ETQF_FILTERS)
4292                 return -1;
4293         filter_info->ethertype_mask &= ~(1 << idx);
4294         filter_info->ethertype_filters[idx] = 0;
4295         return idx;
4296 }
4297
4298 static int
4299 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4300                         struct rte_eth_ethertype_filter *filter,
4301                         bool add)
4302 {
4303         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4304         struct ixgbe_filter_info *filter_info =
4305                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4306         uint32_t etqf = 0;
4307         uint32_t etqs = 0;
4308         int ret;
4309
4310         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4311                 return -EINVAL;
4312
4313         if (filter->ether_type == ETHER_TYPE_IPv4 ||
4314                 filter->ether_type == ETHER_TYPE_IPv6) {
4315                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4316                         " ethertype filter.", filter->ether_type);
4317                 return -EINVAL;
4318         }
4319
4320         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4321                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4322                 return -EINVAL;
4323         }
4324         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4325                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4326                 return -EINVAL;
4327         }
4328
4329         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4330         if (ret >= 0 && add) {
4331                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4332                             filter->ether_type);
4333                 return -EEXIST;
4334         }
4335         if (ret < 0 && !add) {
4336                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4337                             filter->ether_type);
4338                 return -ENOENT;
4339         }
4340
4341         if (add) {
4342                 ret = ixgbe_ethertype_filter_insert(filter_info,
4343                         filter->ether_type);
4344                 if (ret < 0) {
4345                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4346                         return -ENOSYS;
4347                 }
4348                 etqf = IXGBE_ETQF_FILTER_EN;
4349                 etqf |= (uint32_t)filter->ether_type;
4350                 etqs |= (uint32_t)((filter->queue <<
4351                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
4352                                     IXGBE_ETQS_RX_QUEUE);
4353                 etqs |= IXGBE_ETQS_QUEUE_EN;
4354         } else {
4355                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4356                 if (ret < 0)
4357                         return -ENOSYS;
4358         }
4359         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
4360         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
4361         IXGBE_WRITE_FLUSH(hw);
4362
4363         return 0;
4364 }
4365
4366 static int
4367 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
4368                         struct rte_eth_ethertype_filter *filter)
4369 {
4370         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4371         struct ixgbe_filter_info *filter_info =
4372                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
4373         uint32_t etqf, etqs;
4374         int ret;
4375
4376         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4377         if (ret < 0) {
4378                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4379                             filter->ether_type);
4380                 return -ENOENT;
4381         }
4382
4383         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
4384         if (etqf & IXGBE_ETQF_FILTER_EN) {
4385                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
4386                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
4387                 filter->flags = 0;
4388                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
4389                                IXGBE_ETQS_RX_QUEUE_SHIFT;
4390                 return 0;
4391         }
4392         return -ENOENT;
4393 }
4394
4395 /*
4396  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
4397  * @dev: pointer to rte_eth_dev structure
4398  * @filter_op:operation will be taken.
4399  * @arg: a pointer to specific structure corresponding to the filter_op
4400  */
4401 static int
4402 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
4403                                 enum rte_filter_op filter_op,
4404                                 void *arg)
4405 {
4406         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4407         int ret;
4408
4409         MAC_TYPE_FILTER_SUP(hw->mac.type);
4410
4411         if (filter_op == RTE_ETH_FILTER_NOP)
4412                 return 0;
4413
4414         if (arg == NULL) {
4415                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
4416                             filter_op);
4417                 return -EINVAL;
4418         }
4419
4420         switch (filter_op) {
4421         case RTE_ETH_FILTER_ADD:
4422                 ret = ixgbe_add_del_ethertype_filter(dev,
4423                         (struct rte_eth_ethertype_filter *)arg,
4424                         TRUE);
4425                 break;
4426         case RTE_ETH_FILTER_DELETE:
4427                 ret = ixgbe_add_del_ethertype_filter(dev,
4428                         (struct rte_eth_ethertype_filter *)arg,
4429                         FALSE);
4430                 break;
4431         case RTE_ETH_FILTER_GET:
4432                 ret = ixgbe_get_ethertype_filter(dev,
4433                         (struct rte_eth_ethertype_filter *)arg);
4434                 break;
4435         default:
4436                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
4437                 ret = -EINVAL;
4438                 break;
4439         }
4440         return ret;
4441 }
4442
4443 static int
4444 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
4445                      enum rte_filter_type filter_type,
4446                      enum rte_filter_op filter_op,
4447                      void *arg)
4448 {
4449         int ret = -EINVAL;
4450
4451         switch (filter_type) {
4452         case RTE_ETH_FILTER_NTUPLE:
4453                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
4454                 break;
4455         case RTE_ETH_FILTER_ETHERTYPE:
4456                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
4457                 break;
4458         case RTE_ETH_FILTER_SYN:
4459                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
4460                 break;
4461         case RTE_ETH_FILTER_FDIR:
4462                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
4463                 break;
4464         default:
4465                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4466                                                         filter_type);
4467                 break;
4468         }
4469
4470         return ret;
4471 }
4472
4473 static u8 *
4474 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
4475                         u8 **mc_addr_ptr, u32 *vmdq)
4476 {
4477         u8 *mc_addr;
4478
4479         *vmdq = 0;
4480         mc_addr = *mc_addr_ptr;
4481         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
4482         return mc_addr;
4483 }
4484
4485 static int
4486 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4487                            struct ether_addr *mc_addr_set,
4488                            uint32_t nb_mc_addr)
4489 {
4490         struct ixgbe_hw *hw;
4491         u8 *mc_addr_list;
4492
4493         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4494         mc_addr_list = (u8 *)mc_addr_set;
4495         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4496                                          ixgbe_dev_addr_list_itr, TRUE);
4497 }
4498
4499 static struct rte_driver rte_ixgbe_driver = {
4500         .type = PMD_PDEV,
4501         .init = rte_ixgbe_pmd_init,
4502 };
4503
4504 static struct rte_driver rte_ixgbevf_driver = {
4505         .type = PMD_PDEV,
4506         .init = rte_ixgbevf_pmd_init,
4507 };
4508
4509 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
4510 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);