drivers/net/ixgbe/ixgbe_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <rte_byteorder.h>
  44 #include <rte_common.h>
  45 #include <rte_cycles.h>
  46
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_eal.h>
  56 #include <rte_alarm.h>
  57 #include <rte_ether.h>
  58 #include <rte_ethdev.h>
  59 #include <rte_atomic.h>
  60 #include <rte_malloc.h>
  61 #include <rte_random.h>
  62 #include <rte_dev.h>
  63
  64 #include "ixgbe_logs.h"
  65 #include "base/ixgbe_api.h"
  66 #include "base/ixgbe_vf.h"
  67 #include "base/ixgbe_common.h"
  68 #include "ixgbe_ethdev.h"
  69 #include "ixgbe_bypass.h"
  70 #include "ixgbe_rxtx.h"
  71 #include "base/ixgbe_type.h"
  72 #include "base/ixgbe_phy.h"
  73 #include "ixgbe_regs.h"
  74
  75 /*
  76  * High threshold controlling when to start sending XOFF frames. Must be at
  77  * least 8 bytes less than receive packet buffer size. This value is in units
  78  * of 1024 bytes.
  79  */
  80 #define IXGBE_FC_HI    0x80
  81
  82 /*
  83  * Low threshold controlling when to start sending XON frames. This value is
  84  * in units of 1024 bytes.
  85  */
  86 #define IXGBE_FC_LO    0x40
  87
  88 /* Default minimum inter-interrupt interval for EITR configuration */
  89 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT    0x79E
  90
  91 /* Timer value included in XOFF frames. */
  92 #define IXGBE_FC_PAUSE 0x680
  93
  94 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
  95 #define IXGBE_LINK_UP_CHECK_TIMEOUT   1000 /* ms */
  96 #define IXGBE_VMDQ_NUM_UC_MAC         4096 /* Maximum nb. of UC MAC addr. */
  97
  98 #define IXGBE_MMW_SIZE_DEFAULT        0x4
  99 #define IXGBE_MMW_SIZE_JUMBO_FRAME    0x14
 100 #define IXGBE_MAX_RING_DESC           4096 /* replicate define from rxtx */
 101
 102 /*
 103  *  Default values for RX/TX configuration
 104  */
 105 #define IXGBE_DEFAULT_RX_FREE_THRESH  32
 106 #define IXGBE_DEFAULT_RX_PTHRESH      8
 107 #define IXGBE_DEFAULT_RX_HTHRESH      8
 108 #define IXGBE_DEFAULT_RX_WTHRESH      0
 109
 110 #define IXGBE_DEFAULT_TX_FREE_THRESH  32
 111 #define IXGBE_DEFAULT_TX_PTHRESH      32
 112 #define IXGBE_DEFAULT_TX_HTHRESH      0
 113 #define IXGBE_DEFAULT_TX_WTHRESH      0
 114 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
 115
 116 /* Bit shift and mask */
 117 #define IXGBE_4_BIT_WIDTH  (CHAR_BIT / 2)
 118 #define IXGBE_4_BIT_MASK   RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
 119 #define IXGBE_8_BIT_WIDTH  CHAR_BIT
 120 #define IXGBE_8_BIT_MASK   UINT8_MAX
 121
 122 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
 123
 124 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
 125
 126 #define IXGBE_HKEY_MAX_INDEX 10
 127
 128 /* Additional timesync values. */
 129 #define NSEC_PER_SEC             1000000000L
 130 #define IXGBE_INCVAL_10GB        0x66666666
 131 #define IXGBE_INCVAL_1GB         0x40000000
 132 #define IXGBE_INCVAL_100         0x50000000
 133 #define IXGBE_INCVAL_SHIFT_10GB  28
 134 #define IXGBE_INCVAL_SHIFT_1GB   24
 135 #define IXGBE_INCVAL_SHIFT_100   21
 136 #define IXGBE_INCVAL_SHIFT_82599 7
 137 #define IXGBE_INCPER_SHIFT_82599 24
 138
 139 #define IXGBE_CYCLECOUNTER_MASK   0xffffffffffffffff
 140
 141 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
 142 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
 143 static int  ixgbe_dev_configure(struct rte_eth_dev *dev);
 144 static int  ixgbe_dev_start(struct rte_eth_dev *dev);
 145 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
 146 static int  ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
 147 static int  ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
 148 static void ixgbe_dev_close(struct rte_eth_dev *dev);
 149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
 150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
 151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
 152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
 153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
 154                                 int wait_to_complete);
 155 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
 156                                 struct rte_eth_stats *stats);
 157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
 158                                 struct rte_eth_xstats *xstats, unsigned n);
 159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
 160                                   struct rte_eth_xstats *xstats, unsigned n);
 161 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
 162 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
 163 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 164                                              uint16_t queue_id,
 165                                              uint8_t stat_idx,
 166                                              uint8_t is_rx);
 167 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
 168                                struct rte_eth_dev_info *dev_info);
 169 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
 170                                  struct rte_eth_dev_info *dev_info);
 171 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 172
 173 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
 174                 uint16_t vlan_id, int on);
 175 static void ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid_id);
 176 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
 177                 uint16_t queue, bool on);
 178 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
 179                 int on);
 180 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 181 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 182 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
 183 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
 184 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
 185
 186 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
 187 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
 188 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
 189                                struct rte_eth_fc_conf *fc_conf);
 190 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
 191                                struct rte_eth_fc_conf *fc_conf);
 192 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 193                 struct rte_eth_pfc_conf *pfc_conf);
 194 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
 195                         struct rte_eth_rss_reta_entry64 *reta_conf,
 196                         uint16_t reta_size);
 197 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
 198                         struct rte_eth_rss_reta_entry64 *reta_conf,
 199                         uint16_t reta_size);
 200 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
 201 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
 202 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 203 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 204 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev);
 205 static void ixgbe_dev_interrupt_handler(struct rte_intr_handle *handle,
 206                 void *param);
 207 static void ixgbe_dev_interrupt_delayed_handler(void *param);
 208 static void ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
 209                 uint32_t index, uint32_t pool);
 210 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
 211 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
 212                                            struct ether_addr *mac_addr);
 213 static void ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config);
 214
 215 /* For Virtual Function support */
 216 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int  ixgbevf_dev_configure(struct rte_eth_dev *dev);
 219 static int  ixgbevf_dev_start(struct rte_eth_dev *dev);
 220 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
 221 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
 222 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
 223 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
 224 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
 225                 struct rte_eth_stats *stats);
 226 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
 227 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
 228                 uint16_t vlan_id, int on);
 229 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
 230                 uint16_t queue, int on);
 231 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 232 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
 233 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 234                                             uint16_t queue_id);
 235 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 236                                              uint16_t queue_id);
 237 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 238                                  uint8_t queue, uint8_t msix_vector);
 239 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
 240
 241 /* For Eth VMDQ APIs support */
 242 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
 243                 ether_addr* mac_addr,uint8_t on);
 244 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev,uint8_t on);
 245 static int  ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev,  uint16_t pool,
 246                 uint16_t rx_mask, uint8_t on);
 247 static int ixgbe_set_pool_rx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 248 static int ixgbe_set_pool_tx(struct rte_eth_dev *dev,uint16_t pool,uint8_t on);
 249 static int ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
 250                 uint64_t pool_mask,uint8_t vlan_on);
 251 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
 252                 struct rte_eth_mirror_conf *mirror_conf,
 253                 uint8_t rule_id, uint8_t on);
 254 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
 255                 uint8_t rule_id);
 256 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 257                                           uint16_t queue_id);
 258 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 259                                            uint16_t queue_id);
 260 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
 261                                uint8_t queue, uint8_t msix_vector);
 262 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
 263
 264 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
 265                 uint16_t queue_idx, uint16_t tx_rate);
 266 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
 267                 uint16_t tx_rate, uint64_t q_msk);
 268
 269 static void ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
 270                                  struct ether_addr *mac_addr,
 271                                  uint32_t index, uint32_t pool);
 272 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 273 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
 274                                              struct ether_addr *mac_addr);
 275 static int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
 276                         struct rte_eth_syn_filter *filter,
 277                         bool add);
 278 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
 279                         struct rte_eth_syn_filter *filter);
 280 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
 281                         enum rte_filter_op filter_op,
 282                         void *arg);
 283 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
 284                         struct ixgbe_5tuple_filter *filter);
 285 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
 286                         struct ixgbe_5tuple_filter *filter);
 287 static int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
 288                         struct rte_eth_ntuple_filter *filter,
 289                         bool add);
 290 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
 291                                 enum rte_filter_op filter_op,
 292                                 void *arg);
 293 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
 294                         struct rte_eth_ntuple_filter *filter);
 295 static int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
 296                         struct rte_eth_ethertype_filter *filter,
 297                         bool add);
 298 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
 299                                 enum rte_filter_op filter_op,
 300                                 void *arg);
 301 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
 302                         struct rte_eth_ethertype_filter *filter);
 303 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
 304                      enum rte_filter_type filter_type,
 305                      enum rte_filter_op filter_op,
 306                      void *arg);
 307 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
 308
 309 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
 310                                       struct ether_addr *mc_addr_set,
 311                                       uint32_t nb_mc_addr);
 312 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
 313                                    struct rte_eth_dcb_info *dcb_info);
 314
 315 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
 316 static int ixgbe_get_regs(struct rte_eth_dev *dev,
 317                             struct rte_dev_reg_info *regs);
 318 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
 319 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
 320                                 struct rte_dev_eeprom_info *eeprom);
 321 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
 322                                 struct rte_dev_eeprom_info *eeprom);
 323
 324 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
 325 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
 326                                 struct rte_dev_reg_info *regs);
 327
 328 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
 329 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
 330 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 331                                             struct timespec *timestamp,
 332                                             uint32_t flags);
 333 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 334                                             struct timespec *timestamp);
 335 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 336 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
 337                                    struct timespec *timestamp);
 338 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
 339                                    const struct timespec *timestamp);
 340
 341 /*
 342  * Define VF Stats MACRO for Non "cleared on read" register
 343  */
 344 #define UPDATE_VF_STAT(reg, last, cur)                          \
 345 {                                                               \
 346         uint32_t latest = IXGBE_READ_REG(hw, reg);              \
 347         cur += (latest - last) & UINT_MAX;                      \
 348         last = latest;                                          \
 349 }
 350
 351 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur)                \
 352 {                                                                \
 353         u64 new_lsb = IXGBE_READ_REG(hw, lsb);                   \
 354         u64 new_msb = IXGBE_READ_REG(hw, msb);                   \
 355         u64 latest = ((new_msb << 32) | new_lsb);                \
 356         cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
 357         last = latest;                                           \
 358 }
 359
 360 #define IXGBE_SET_HWSTRIP(h, q) do{\
 361                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 362                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 363                 (h)->bitmap[idx] |= 1 << bit;\
 364         }while(0)
 365
 366 #define IXGBE_CLEAR_HWSTRIP(h, q) do{\
 367                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 368                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 369                 (h)->bitmap[idx] &= ~(1 << bit);\
 370         }while(0)
 371
 372 #define IXGBE_GET_HWSTRIP(h, q, r) do{\
 373                 uint32_t idx = (q) / (sizeof ((h)->bitmap[0]) * NBBY); \
 374                 uint32_t bit = (q) % (sizeof ((h)->bitmap[0]) * NBBY); \
 375                 (r) = (h)->bitmap[idx] >> bit & 1;\
 376         }while(0)
 377
 378 /*
 379  * The set of PCI devices this driver supports
 380  */
 381 static const struct rte_pci_id pci_id_ixgbe_map[] = {
 382
 383 #define RTE_PCI_DEV_ID_DECL_IXGBE(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 384 #include "rte_pci_dev_ids.h"
 385
 386 { .vendor_id = 0, /* sentinel */ },
 387 };
 388
 389
 390 /*
 391  * The set of PCI devices this driver supports (for 82599 VF)
 392  */
 393 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
 394
 395 #define RTE_PCI_DEV_ID_DECL_IXGBEVF(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 396 #include "rte_pci_dev_ids.h"
 397 { .vendor_id = 0, /* sentinel */ },
 398
 399 };
 400
 401 static const struct rte_eth_desc_lim rx_desc_lim = {
 402         .nb_max = IXGBE_MAX_RING_DESC,
 403         .nb_min = IXGBE_MIN_RING_DESC,
 404         .nb_align = IXGBE_RXD_ALIGN,
 405 };
 406
 407 static const struct rte_eth_desc_lim tx_desc_lim = {
 408         .nb_max = IXGBE_MAX_RING_DESC,
 409         .nb_min = IXGBE_MIN_RING_DESC,
 410         .nb_align = IXGBE_TXD_ALIGN,
 411 };
 412
 413 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
 414         .dev_configure        = ixgbe_dev_configure,
 415         .dev_start            = ixgbe_dev_start,
 416         .dev_stop             = ixgbe_dev_stop,
 417         .dev_set_link_up    = ixgbe_dev_set_link_up,
 418         .dev_set_link_down  = ixgbe_dev_set_link_down,
 419         .dev_close            = ixgbe_dev_close,
 420         .promiscuous_enable   = ixgbe_dev_promiscuous_enable,
 421         .promiscuous_disable  = ixgbe_dev_promiscuous_disable,
 422         .allmulticast_enable  = ixgbe_dev_allmulticast_enable,
 423         .allmulticast_disable = ixgbe_dev_allmulticast_disable,
 424         .link_update          = ixgbe_dev_link_update,
 425         .stats_get            = ixgbe_dev_stats_get,
 426         .xstats_get           = ixgbe_dev_xstats_get,
 427         .stats_reset          = ixgbe_dev_stats_reset,
 428         .xstats_reset         = ixgbe_dev_xstats_reset,
 429         .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
 430         .dev_infos_get        = ixgbe_dev_info_get,
 431         .mtu_set              = ixgbe_dev_mtu_set,
 432         .vlan_filter_set      = ixgbe_vlan_filter_set,
 433         .vlan_tpid_set        = ixgbe_vlan_tpid_set,
 434         .vlan_offload_set     = ixgbe_vlan_offload_set,
 435         .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
 436         .rx_queue_start       = ixgbe_dev_rx_queue_start,
 437         .rx_queue_stop        = ixgbe_dev_rx_queue_stop,
 438         .tx_queue_start       = ixgbe_dev_tx_queue_start,
 439         .tx_queue_stop        = ixgbe_dev_tx_queue_stop,
 440         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 441         .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
 442         .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
 443         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 444         .rx_queue_count       = ixgbe_dev_rx_queue_count,
 445         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 446         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 447         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 448         .dev_led_on           = ixgbe_dev_led_on,
 449         .dev_led_off          = ixgbe_dev_led_off,
 450         .flow_ctrl_get        = ixgbe_flow_ctrl_get,
 451         .flow_ctrl_set        = ixgbe_flow_ctrl_set,
 452         .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
 453         .mac_addr_add         = ixgbe_add_rar,
 454         .mac_addr_remove      = ixgbe_remove_rar,
 455         .mac_addr_set         = ixgbe_set_default_mac_addr,
 456         .uc_hash_table_set    = ixgbe_uc_hash_table_set,
 457         .uc_all_hash_table_set  = ixgbe_uc_all_hash_table_set,
 458         .mirror_rule_set      = ixgbe_mirror_rule_set,
 459         .mirror_rule_reset    = ixgbe_mirror_rule_reset,
 460         .set_vf_rx_mode       = ixgbe_set_pool_rx_mode,
 461         .set_vf_rx            = ixgbe_set_pool_rx,
 462         .set_vf_tx            = ixgbe_set_pool_tx,
 463         .set_vf_vlan_filter   = ixgbe_set_pool_vlan_filter,
 464         .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
 465         .set_vf_rate_limit    = ixgbe_set_vf_rate_limit,
 466         .reta_update          = ixgbe_dev_rss_reta_update,
 467         .reta_query           = ixgbe_dev_rss_reta_query,
 468 #ifdef RTE_NIC_BYPASS
 469         .bypass_init          = ixgbe_bypass_init,
 470         .bypass_state_set     = ixgbe_bypass_state_store,
 471         .bypass_state_show    = ixgbe_bypass_state_show,
 472         .bypass_event_set     = ixgbe_bypass_event_store,
 473         .bypass_event_show    = ixgbe_bypass_event_show,
 474         .bypass_wd_timeout_set  = ixgbe_bypass_wd_timeout_store,
 475         .bypass_wd_timeout_show = ixgbe_bypass_wd_timeout_show,
 476         .bypass_ver_show      = ixgbe_bypass_ver_show,
 477         .bypass_wd_reset      = ixgbe_bypass_wd_reset,
 478 #endif /* RTE_NIC_BYPASS */
 479         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 480         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 481         .filter_ctrl          = ixgbe_dev_filter_ctrl,
 482         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 483         .rxq_info_get         = ixgbe_rxq_info_get,
 484         .txq_info_get         = ixgbe_txq_info_get,
 485         .timesync_enable      = ixgbe_timesync_enable,
 486         .timesync_disable     = ixgbe_timesync_disable,
 487         .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
 488         .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
 489         .get_reg_length       = ixgbe_get_reg_length,
 490         .get_reg              = ixgbe_get_regs,
 491         .get_eeprom_length    = ixgbe_get_eeprom_length,
 492         .get_eeprom           = ixgbe_get_eeprom,
 493         .set_eeprom           = ixgbe_set_eeprom,
 494         .get_dcb_info         = ixgbe_dev_get_dcb_info,
 495         .timesync_adjust_time = ixgbe_timesync_adjust_time,
 496         .timesync_read_time   = ixgbe_timesync_read_time,
 497         .timesync_write_time  = ixgbe_timesync_write_time,
 498 };
 499
 500 /*
 501  * dev_ops for virtual function, bare necessities for basic vf
 502  * operation have been implemented
 503  */
 504 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
 505         .dev_configure        = ixgbevf_dev_configure,
 506         .dev_start            = ixgbevf_dev_start,
 507         .dev_stop             = ixgbevf_dev_stop,
 508         .link_update          = ixgbe_dev_link_update,
 509         .stats_get            = ixgbevf_dev_stats_get,
 510         .xstats_get           = ixgbevf_dev_xstats_get,
 511         .stats_reset          = ixgbevf_dev_stats_reset,
 512         .xstats_reset         = ixgbevf_dev_stats_reset,
 513         .dev_close            = ixgbevf_dev_close,
 514         .dev_infos_get        = ixgbevf_dev_info_get,
 515         .mtu_set              = ixgbevf_dev_set_mtu,
 516         .vlan_filter_set      = ixgbevf_vlan_filter_set,
 517         .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
 518         .vlan_offload_set     = ixgbevf_vlan_offload_set,
 519         .rx_queue_setup       = ixgbe_dev_rx_queue_setup,
 520         .rx_queue_release     = ixgbe_dev_rx_queue_release,
 521         .rx_descriptor_done   = ixgbe_dev_rx_descriptor_done,
 522         .tx_queue_setup       = ixgbe_dev_tx_queue_setup,
 523         .tx_queue_release     = ixgbe_dev_tx_queue_release,
 524         .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
 525         .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
 526         .mac_addr_add         = ixgbevf_add_mac_addr,
 527         .mac_addr_remove      = ixgbevf_remove_mac_addr,
 528         .set_mc_addr_list     = ixgbe_dev_set_mc_addr_list,
 529         .rxq_info_get         = ixgbe_rxq_info_get,
 530         .txq_info_get         = ixgbe_txq_info_get,
 531         .mac_addr_set         = ixgbevf_set_default_mac_addr,
 532         .get_reg_length       = ixgbevf_get_reg_length,
 533         .get_reg              = ixgbevf_get_regs,
 534         .reta_update          = ixgbe_dev_rss_reta_update,
 535         .reta_query           = ixgbe_dev_rss_reta_query,
 536         .rss_hash_update      = ixgbe_dev_rss_hash_update,
 537         .rss_hash_conf_get    = ixgbe_dev_rss_hash_conf_get,
 538 };
 539
 540 /* store statistics names and its offset in stats structure */
 541 struct rte_ixgbe_xstats_name_off {
 542         char name[RTE_ETH_XSTATS_NAME_SIZE];
 543         unsigned offset;
 544 };
 545
 546 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
 547         {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
 548         {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
 549         {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
 550         {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
 551         {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
 552         {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
 553         {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
 554         {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
 555         {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
 556         {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
 557         {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
 558         {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
 559         {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
 560         {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
 561         {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 562                 prc1023)},
 563         {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 564                 prc1522)},
 565         {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
 566         {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
 567         {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
 568         {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
 569         {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
 570         {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
 571         {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
 572         {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
 573         {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
 574         {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
 575         {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
 576         {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
 577         {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
 578         {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
 579         {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
 580         {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
 581         {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
 582                 ptc1023)},
 583         {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
 584                 ptc1522)},
 585         {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
 586         {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
 587         {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
 588         {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
 589
 590         {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
 591                 fdirustat_add)},
 592         {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
 593                 fdirustat_remove)},
 594         {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
 595                 fdirfstat_fadd)},
 596         {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
 597                 fdirfstat_fremove)},
 598         {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
 599                 fdirmatch)},
 600         {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
 601                 fdirmiss)},
 602
 603         {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
 604         {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
 605         {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
 606                 fclast)},
 607         {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
 608         {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
 609         {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
 610         {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
 611         {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
 612                 fcoe_noddp)},
 613         {"rx_fcoe_no_direct_data_placement_ext_buff",
 614                 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
 615
 616         {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 617                 lxontxc)},
 618         {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
 619                 lxonrxc)},
 620         {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 621                 lxofftxc)},
 622         {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
 623                 lxoffrxc)},
 624         {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
 625 };
 626
 627 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
 628                            sizeof(rte_ixgbe_stats_strings[0]))
 629
 630 /* Per-queue statistics */
 631 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
 632         {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
 633         {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
 634         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
 635         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
 636 };
 637
 638 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
 639                            sizeof(rte_ixgbe_rxq_strings[0]))
 640
 641 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
 642         {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
 643         {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
 644         {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
 645                 pxon2offc)},
 646 };
 647
 648 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
 649                            sizeof(rte_ixgbe_txq_strings[0]))
 650
 651 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
 652         {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
 653 };
 654
 655 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) /  \
 656                 sizeof(rte_ixgbevf_stats_strings[0]))
 657
 658 /**
 659  * Atomically reads the link status information from global
 660  * structure rte_eth_dev.
 661  *
 662  * @param dev
 663  *   - Pointer to the structure rte_eth_dev to read from.
 664  *   - Pointer to the buffer to be saved with the link status.
 665  *
 666  * @return
 667  *   - On success, zero.
 668  *   - On failure, negative value.
 669  */
 670 static inline int
 671 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 672                                 struct rte_eth_link *link)
 673 {
 674         struct rte_eth_link *dst = link;
 675         struct rte_eth_link *src = &(dev->data->dev_link);
 676
 677         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 678                                         *(uint64_t *)src) == 0)
 679                 return -1;
 680
 681         return 0;
 682 }
 683
 684 /**
 685  * Atomically writes the link status information into global
 686  * structure rte_eth_dev.
 687  *
 688  * @param dev
 689  *   - Pointer to the structure rte_eth_dev to read from.
 690  *   - Pointer to the buffer to be saved with the link status.
 691  *
 692  * @return
 693  *   - On success, zero.
 694  *   - On failure, negative value.
 695  */
 696 static inline int
 697 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 698                                 struct rte_eth_link *link)
 699 {
 700         struct rte_eth_link *dst = &(dev->data->dev_link);
 701         struct rte_eth_link *src = link;
 702
 703         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 704                                         *(uint64_t *)src) == 0)
 705                 return -1;
 706
 707         return 0;
 708 }
 709
 710 /*
 711  * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
 712  */
 713 static inline int
 714 ixgbe_is_sfp(struct ixgbe_hw *hw)
 715 {
 716         switch (hw->phy.type) {
 717         case ixgbe_phy_sfp_avago:
 718         case ixgbe_phy_sfp_ftl:
 719         case ixgbe_phy_sfp_intel:
 720         case ixgbe_phy_sfp_unknown:
 721         case ixgbe_phy_sfp_passive_tyco:
 722         case ixgbe_phy_sfp_passive_unknown:
 723                 return 1;
 724         default:
 725                 return 0;
 726         }
 727 }
 728
 729 static inline int32_t
 730 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
 731 {
 732         uint32_t ctrl_ext;
 733         int32_t status;
 734
 735         status = ixgbe_reset_hw(hw);
 736
 737         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 738         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 739         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
 740         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 741         IXGBE_WRITE_FLUSH(hw);
 742
 743         return status;
 744 }
 745
 746 static inline void
 747 ixgbe_enable_intr(struct rte_eth_dev *dev)
 748 {
 749         struct ixgbe_interrupt *intr =
 750                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
 751         struct ixgbe_hw *hw =
 752                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 753
 754         IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
 755         IXGBE_WRITE_FLUSH(hw);
 756 }
 757
 758 /*
 759  * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
 760  */
 761 static void
 762 ixgbe_disable_intr(struct ixgbe_hw *hw)
 763 {
 764         PMD_INIT_FUNC_TRACE();
 765
 766         if (hw->mac.type == ixgbe_mac_82598EB) {
 767                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
 768         } else {
 769                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
 770                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
 771                 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
 772         }
 773         IXGBE_WRITE_FLUSH(hw);
 774 }
 775
 776 /*
 777  * This function resets queue statistics mapping registers.
 778  * From Niantic datasheet, Initialization of Statistics section:
 779  * "...if software requires the queue counters, the RQSMR and TQSM registers
 780  * must be re-programmed following a device reset.
 781  */
 782 static void
 783 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
 784 {
 785         uint32_t i;
 786
 787         for(i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
 788                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
 789                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
 790         }
 791 }
 792
 793
 794 static int
 795 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 796                                   uint16_t queue_id,
 797                                   uint8_t stat_idx,
 798                                   uint8_t is_rx)
 799 {
 800 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
 801 #define NB_QMAP_FIELDS_PER_QSM_REG 4
 802 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
 803
 804         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 805         struct ixgbe_stat_mapping_registers *stat_mappings =
 806                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
 807         uint32_t qsmr_mask = 0;
 808         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 809         uint32_t q_map;
 810         uint8_t n, offset;
 811
 812         if ((hw->mac.type != ixgbe_mac_82599EB) &&
 813                 (hw->mac.type != ixgbe_mac_X540) &&
 814                 (hw->mac.type != ixgbe_mac_X550) &&
 815                 (hw->mac.type != ixgbe_mac_X550EM_x))
 816                 return -ENOSYS;
 817
 818         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 819                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 820                      queue_id, stat_idx);
 821
 822         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 823         if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
 824                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 825                 return -EIO;
 826         }
 827         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 828
 829         /* Now clear any previous stat_idx set */
 830         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 831         if (!is_rx)
 832                 stat_mappings->tqsm[n] &= ~clearing_mask;
 833         else
 834                 stat_mappings->rqsmr[n] &= ~clearing_mask;
 835
 836         q_map = (uint32_t)stat_idx;
 837         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 838         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 839         if (!is_rx)
 840                 stat_mappings->tqsm[n] |= qsmr_mask;
 841         else
 842                 stat_mappings->rqsmr[n] |= qsmr_mask;
 843
 844         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 845                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 846                      queue_id, stat_idx);
 847         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 848                      is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
 849
 850         /* Now write the mapping in the appropriate register */
 851         if (is_rx) {
 852                 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
 853                              stat_mappings->rqsmr[n], n);
 854                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
 855         }
 856         else {
 857                 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
 858                              stat_mappings->tqsm[n], n);
 859                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
 860         }
 861         return 0;
 862 }
 863
 864 static void
 865 ixgbe_restore_statistics_mapping(struct rte_eth_dev * dev)
 866 {
 867         struct ixgbe_stat_mapping_registers *stat_mappings =
 868                 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
 869         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 870         int i;
 871
 872         /* write whatever was in stat mapping table to the NIC */
 873         for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
 874                 /* rx */
 875                 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
 876
 877                 /* tx */
 878                 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
 879         }
 880 }
 881
 882 static void
 883 ixgbe_dcb_init(struct ixgbe_hw *hw,struct ixgbe_dcb_config *dcb_config)
 884 {
 885         uint8_t i;
 886         struct ixgbe_dcb_tc_config *tc;
 887         uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
 888
 889         dcb_config->num_tcs.pg_tcs = dcb_max_tc;
 890         dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
 891         for (i = 0; i < dcb_max_tc; i++) {
 892                 tc = &dcb_config->tc_config[i];
 893                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
 894                 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
 895                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 896                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
 897                 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
 898                                  (uint8_t)(100/dcb_max_tc + (i & 1));
 899                 tc->pfc = ixgbe_dcb_pfc_disabled;
 900         }
 901
 902         /* Initialize default user to priority mapping, UPx->TC0 */
 903         tc = &dcb_config->tc_config[0];
 904         tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 905         tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 906         for (i = 0; i< IXGBE_DCB_MAX_BW_GROUP; i++) {
 907                 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
 908                 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
 909         }
 910         dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
 911         dcb_config->pfc_mode_enable = false;
 912         dcb_config->vt_mode = true;
 913         dcb_config->round_robin_enable = false;
 914         /* support all DCB capabilities in 82599 */
 915         dcb_config->support.capabilities = 0xFF;
 916
 917         /*we only support 4 Tcs for X540, X550 */
 918         if (hw->mac.type == ixgbe_mac_X540 ||
 919                 hw->mac.type == ixgbe_mac_X550 ||
 920                 hw->mac.type == ixgbe_mac_X550EM_x) {
 921                 dcb_config->num_tcs.pg_tcs = 4;
 922                 dcb_config->num_tcs.pfc_tcs = 4;
 923         }
 924 }
 925
 926 /*
 927  * Ensure that all locks are released before first NVM or PHY access
 928  */
 929 static void
 930 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
 931 {
 932         uint16_t mask;
 933
 934         /*
 935          * Phy lock should not fail in this early stage. If this is the case,
 936          * it is due to an improper exit of the application.
 937          * So force the release of the faulty lock. Release of common lock
 938          * is done automatically by swfw_sync function.
 939          */
 940         mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
 941         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 942                 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
 943         }
 944         ixgbe_release_swfw_semaphore(hw, mask);
 945
 946         /*
 947          * These ones are more tricky since they are common to all ports; but
 948          * swfw_sync retries last long enough (1s) to be almost sure that if
 949          * lock can not be taken it is due to an improper lock of the
 950          * semaphore.
 951          */
 952         mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
 953         if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
 954                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 955         }
 956         ixgbe_release_swfw_semaphore(hw, mask);
 957 }
 958
 959 /*
 960  * This function is based on code in ixgbe_attach() in base/ixgbe.c.
 961  * It returns 0 on success.
 962  */
 963 static int
 964 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
 965 {
 966         struct rte_pci_device *pci_dev;
 967         struct ixgbe_hw *hw =
 968                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
 969         struct ixgbe_vfta * shadow_vfta =
 970                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
 971         struct ixgbe_hwstrip *hwstrip =
 972                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
 973         struct ixgbe_dcb_config *dcb_config =
 974                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
 975         struct ixgbe_filter_info *filter_info =
 976                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
 977         uint32_t ctrl_ext;
 978         uint16_t csum;
 979         int diag, i;
 980
 981         PMD_INIT_FUNC_TRACE();
 982
 983         eth_dev->dev_ops = &ixgbe_eth_dev_ops;
 984         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
 985         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
 986
 987         /*
 988          * For secondary processes, we don't initialise any further as primary
 989          * has already done this work. Only check we don't need a different
 990          * RX and TX function.
 991          */
 992         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 993                 struct ixgbe_tx_queue *txq;
 994                 /* TX queue function in primary, set by last queue initialized
 995                  * Tx queue may not initialized by primary process */
 996                 if (eth_dev->data->tx_queues) {
 997                         txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
 998                         ixgbe_set_tx_function(eth_dev, txq);
 999                 } else {
1000                         /* Use default TX function if we get here */
1001                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1002                                              "Using default TX function.");
1003                 }
1004
1005                 ixgbe_set_rx_function(eth_dev);
1006
1007                 return 0;
1008         }
1009         pci_dev = eth_dev->pci_dev;
1010
1011         rte_eth_copy_pci_info(eth_dev, pci_dev);
1012
1013         /* Vendor and Device ID need to be set before init of shared code */
1014         hw->device_id = pci_dev->id.device_id;
1015         hw->vendor_id = pci_dev->id.vendor_id;
1016         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1017         hw->allow_unsupported_sfp = 1;
1018
1019         /* Initialize the shared code (base driver) */
1020 #ifdef RTE_NIC_BYPASS
1021         diag = ixgbe_bypass_init_shared_code(hw);
1022 #else
1023         diag = ixgbe_init_shared_code(hw);
1024 #endif /* RTE_NIC_BYPASS */
1025
1026         if (diag != IXGBE_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1028                 return -EIO;
1029         }
1030
1031         /* pick up the PCI bus settings for reporting later */
1032         ixgbe_get_bus_info(hw);
1033
1034         /* Unlock any pending hardware semaphore */
1035         ixgbe_swfw_lock_reset(hw);
1036
1037         /* Initialize DCB configuration*/
1038         memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1039         ixgbe_dcb_init(hw,dcb_config);
1040         /* Get Hardware Flow Control setting */
1041         hw->fc.requested_mode = ixgbe_fc_full;
1042         hw->fc.current_mode = ixgbe_fc_full;
1043         hw->fc.pause_time = IXGBE_FC_PAUSE;
1044         for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1045                 hw->fc.low_water[i] = IXGBE_FC_LO;
1046                 hw->fc.high_water[i] = IXGBE_FC_HI;
1047         }
1048         hw->fc.send_xon = 1;
1049
1050         /* Make sure we have a good EEPROM before we read from it */
1051         diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1052         if (diag != IXGBE_SUCCESS) {
1053                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1054                 return -EIO;
1055         }
1056
1057 #ifdef RTE_NIC_BYPASS
1058         diag = ixgbe_bypass_init_hw(hw);
1059 #else
1060         diag = ixgbe_init_hw(hw);
1061 #endif /* RTE_NIC_BYPASS */
1062
1063         /*
1064          * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1065          * is called too soon after the kernel driver unbinding/binding occurs.
1066          * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1067          * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1068          * also called. See ixgbe_identify_phy_82599(). The reason for the
1069          * failure is not known, and only occuts when virtualisation features
1070          * are disabled in the bios. A delay of 100ms  was found to be enough by
1071          * trial-and-error, and is doubled to be safe.
1072          */
1073         if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1074                 rte_delay_ms(200);
1075                 diag = ixgbe_init_hw(hw);
1076         }
1077
1078         if (diag == IXGBE_ERR_EEPROM_VERSION) {
1079                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1080                     "LOM.  Please be aware there may be issues associated "
1081                     "with your hardware.");
1082                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1083                     "please contact your Intel or hardware representative "
1084                     "who provided you with this hardware.");
1085         } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1086                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1087         if (diag) {
1088                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1089                 return -EIO;
1090         }
1091
1092         /* Reset the hw statistics */
1093         ixgbe_dev_stats_reset(eth_dev);
1094
1095         /* disable interrupt */
1096         ixgbe_disable_intr(hw);
1097
1098         /* reset mappings for queue statistics hw counters*/
1099         ixgbe_reset_qstat_mappings(hw);
1100
1101         /* Allocate memory for storing MAC addresses */
1102         eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1103                         hw->mac.num_rar_entries, 0);
1104         if (eth_dev->data->mac_addrs == NULL) {
1105                 PMD_INIT_LOG(ERR,
1106                         "Failed to allocate %u bytes needed to store "
1107                         "MAC addresses",
1108                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1109                 return -ENOMEM;
1110         }
1111         /* Copy the permanent MAC address */
1112         ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1113                         &eth_dev->data->mac_addrs[0]);
1114
1115         /* Allocate memory for storing hash filter MAC addresses */
1116         eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1117                         IXGBE_VMDQ_NUM_UC_MAC, 0);
1118         if (eth_dev->data->hash_mac_addrs == NULL) {
1119                 PMD_INIT_LOG(ERR,
1120                         "Failed to allocate %d bytes needed to store MAC addresses",
1121                         ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1122                 return -ENOMEM;
1123         }
1124
1125         /* initialize the vfta */
1126         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1127
1128         /* initialize the hw strip bitmap*/
1129         memset(hwstrip, 0, sizeof(*hwstrip));
1130
1131         /* initialize PF if max_vfs not zero */
1132         ixgbe_pf_host_init(eth_dev);
1133
1134         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1135         /* let hardware know driver is loaded */
1136         ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1137         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1138         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1139         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1140         IXGBE_WRITE_FLUSH(hw);
1141
1142         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1143                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1144                              (int) hw->mac.type, (int) hw->phy.type,
1145                              (int) hw->phy.sfp_type);
1146         else
1147                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1148                              (int) hw->mac.type, (int) hw->phy.type);
1149
1150         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1151                         eth_dev->data->port_id, pci_dev->id.vendor_id,
1152                         pci_dev->id.device_id);
1153
1154         rte_intr_callback_register(&pci_dev->intr_handle,
1155                                    ixgbe_dev_interrupt_handler,
1156                                    (void *)eth_dev);
1157
1158         /* enable uio/vfio intr/eventfd mapping */
1159         rte_intr_enable(&pci_dev->intr_handle);
1160
1161         /* enable support intr */
1162         ixgbe_enable_intr(eth_dev);
1163
1164         /* initialize 5tuple filter list */
1165         TAILQ_INIT(&filter_info->fivetuple_list);
1166         memset(filter_info->fivetuple_mask, 0,
1167                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1168
1169         return 0;
1170 }
1171
1172 static int
1173 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1174 {
1175         struct rte_pci_device *pci_dev;
1176         struct ixgbe_hw *hw;
1177
1178         PMD_INIT_FUNC_TRACE();
1179
1180         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1181                 return -EPERM;
1182
1183         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1184         pci_dev = eth_dev->pci_dev;
1185
1186         if (hw->adapter_stopped == 0)
1187                 ixgbe_dev_close(eth_dev);
1188
1189         eth_dev->dev_ops = NULL;
1190         eth_dev->rx_pkt_burst = NULL;
1191         eth_dev->tx_pkt_burst = NULL;
1192
1193         /* Unlock any pending hardware semaphore */
1194         ixgbe_swfw_lock_reset(hw);
1195
1196         /* disable uio intr before callback unregister */
1197         rte_intr_disable(&(pci_dev->intr_handle));
1198         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1199                 ixgbe_dev_interrupt_handler, (void *)eth_dev);
1200
1201         /* uninitialize PF if max_vfs not zero */
1202         ixgbe_pf_host_uninit(eth_dev);
1203
1204         rte_free(eth_dev->data->mac_addrs);
1205         eth_dev->data->mac_addrs = NULL;
1206
1207         rte_free(eth_dev->data->hash_mac_addrs);
1208         eth_dev->data->hash_mac_addrs = NULL;
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * Negotiate mailbox API version with the PF.
1215  * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1216  * Then we try to negotiate starting with the most recent one.
1217  * If all negotiation attempts fail, then we will proceed with
1218  * the default one (ixgbe_mbox_api_10).
1219  */
1220 static void
1221 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1222 {
1223         int32_t i;
1224
1225         /* start with highest supported, proceed down */
1226         static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1227                 ixgbe_mbox_api_11,
1228                 ixgbe_mbox_api_10,
1229         };
1230
1231         for (i = 0;
1232                         i != RTE_DIM(sup_ver) &&
1233                         ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1234                         i++)
1235                 ;
1236 }
1237
1238 static void
1239 generate_random_mac_addr(struct ether_addr *mac_addr)
1240 {
1241         uint64_t random;
1242
1243         /* Set Organizationally Unique Identifier (OUI) prefix. */
1244         mac_addr->addr_bytes[0] = 0x00;
1245         mac_addr->addr_bytes[1] = 0x09;
1246         mac_addr->addr_bytes[2] = 0xC0;
1247         /* Force indication of locally assigned MAC address. */
1248         mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1249         /* Generate the last 3 bytes of the MAC address with a random number. */
1250         random = rte_rand();
1251         memcpy(&mac_addr->addr_bytes[3], &random, 3);
1252 }
1253
1254 /*
1255  * Virtual Function device init
1256  */
1257 static int
1258 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1259 {
1260         int diag;
1261         uint32_t tc, tcs;
1262         struct rte_pci_device *pci_dev;
1263         struct ixgbe_hw *hw =
1264                 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1265         struct ixgbe_vfta * shadow_vfta =
1266                 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1267         struct ixgbe_hwstrip *hwstrip =
1268                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1269         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1270
1271         PMD_INIT_FUNC_TRACE();
1272
1273         eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1274         eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1275         eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1276
1277         /* for secondary processes, we don't initialise any further as primary
1278          * has already done this work. Only check we don't need a different
1279          * RX function */
1280         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1281                 if (eth_dev->data->scattered_rx)
1282                         eth_dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
1283                 return 0;
1284         }
1285
1286         pci_dev = eth_dev->pci_dev;
1287
1288         rte_eth_copy_pci_info(eth_dev, pci_dev);
1289
1290         hw->device_id = pci_dev->id.device_id;
1291         hw->vendor_id = pci_dev->id.vendor_id;
1292         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1293
1294         /* initialize the vfta */
1295         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1296
1297         /* initialize the hw strip bitmap*/
1298         memset(hwstrip, 0, sizeof(*hwstrip));
1299
1300         /* Initialize the shared code (base driver) */
1301         diag = ixgbe_init_shared_code(hw);
1302         if (diag != IXGBE_SUCCESS) {
1303                 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1304                 return -EIO;
1305         }
1306
1307         /* init_mailbox_params */
1308         hw->mbx.ops.init_params(hw);
1309
1310         /* Reset the hw statistics */
1311         ixgbevf_dev_stats_reset(eth_dev);
1312
1313         /* Disable the interrupts for VF */
1314         ixgbevf_intr_disable(hw);
1315
1316         hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1317         diag = hw->mac.ops.reset_hw(hw);
1318
1319         /*
1320          * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1321          * the underlying PF driver has not assigned a MAC address to the VF.
1322          * In this case, assign a random MAC address.
1323          */
1324         if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1325                 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1326                 return (diag);
1327         }
1328
1329         /* negotiate mailbox API version to use with the PF. */
1330         ixgbevf_negotiate_api(hw);
1331
1332         /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1333         ixgbevf_get_queues(hw, &tcs, &tc);
1334
1335         /* Allocate memory for storing MAC addresses */
1336         eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1337                         hw->mac.num_rar_entries, 0);
1338         if (eth_dev->data->mac_addrs == NULL) {
1339                 PMD_INIT_LOG(ERR,
1340                         "Failed to allocate %u bytes needed to store "
1341                         "MAC addresses",
1342                         ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1343                 return -ENOMEM;
1344         }
1345
1346         /* Generate a random MAC address, if none was assigned by PF. */
1347         if (is_zero_ether_addr(perm_addr)) {
1348                 generate_random_mac_addr(perm_addr);
1349                 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1350                 if (diag) {
1351                         rte_free(eth_dev->data->mac_addrs);
1352                         eth_dev->data->mac_addrs = NULL;
1353                         return diag;
1354                 }
1355                 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1356                 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1357                              "%02x:%02x:%02x:%02x:%02x:%02x",
1358                              perm_addr->addr_bytes[0],
1359                              perm_addr->addr_bytes[1],
1360                              perm_addr->addr_bytes[2],
1361                              perm_addr->addr_bytes[3],
1362                              perm_addr->addr_bytes[4],
1363                              perm_addr->addr_bytes[5]);
1364         }
1365
1366         /* Copy the permanent MAC address */
1367         ether_addr_copy(perm_addr, &eth_dev->data->mac_addrs[0]);
1368
1369         /* reset the hardware with the new settings */
1370         diag = hw->mac.ops.start_hw(hw);
1371         switch (diag) {
1372                 case  0:
1373                         break;
1374
1375                 default:
1376                         PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1377                         return (-EIO);
1378         }
1379
1380         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1381                      eth_dev->data->port_id, pci_dev->id.vendor_id,
1382                      pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1383
1384         return 0;
1385 }
1386
1387 /* Virtual Function device uninit */
1388
1389 static int
1390 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1391 {
1392         struct ixgbe_hw *hw;
1393         unsigned i;
1394
1395         PMD_INIT_FUNC_TRACE();
1396
1397         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1398                 return -EPERM;
1399
1400         hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1401
1402         if (hw->adapter_stopped == 0)
1403                 ixgbevf_dev_close(eth_dev);
1404
1405         eth_dev->dev_ops = NULL;
1406         eth_dev->rx_pkt_burst = NULL;
1407         eth_dev->tx_pkt_burst = NULL;
1408
1409         /* Disable the interrupts for VF */
1410         ixgbevf_intr_disable(hw);
1411
1412         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
1413                 ixgbe_dev_rx_queue_release(eth_dev->data->rx_queues[i]);
1414                 eth_dev->data->rx_queues[i] = NULL;
1415         }
1416         eth_dev->data->nb_rx_queues = 0;
1417
1418         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
1419                 ixgbe_dev_tx_queue_release(eth_dev->data->tx_queues[i]);
1420                 eth_dev->data->tx_queues[i] = NULL;
1421         }
1422         eth_dev->data->nb_tx_queues = 0;
1423
1424         rte_free(eth_dev->data->mac_addrs);
1425         eth_dev->data->mac_addrs = NULL;
1426
1427         return 0;
1428 }
1429
1430 static struct eth_driver rte_ixgbe_pmd = {
1431         .pci_drv = {
1432                 .name = "rte_ixgbe_pmd",
1433                 .id_table = pci_id_ixgbe_map,
1434                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1435                         RTE_PCI_DRV_DETACHABLE,
1436         },
1437         .eth_dev_init = eth_ixgbe_dev_init,
1438         .eth_dev_uninit = eth_ixgbe_dev_uninit,
1439         .dev_private_size = sizeof(struct ixgbe_adapter),
1440 };
1441
1442 /*
1443  * virtual function driver struct
1444  */
1445 static struct eth_driver rte_ixgbevf_pmd = {
1446         .pci_drv = {
1447                 .name = "rte_ixgbevf_pmd",
1448                 .id_table = pci_id_ixgbevf_map,
1449                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_DETACHABLE,
1450         },
1451         .eth_dev_init = eth_ixgbevf_dev_init,
1452         .eth_dev_uninit = eth_ixgbevf_dev_uninit,
1453         .dev_private_size = sizeof(struct ixgbe_adapter),
1454 };
1455
1456 /*
1457  * Driver initialization routine.
1458  * Invoked once at EAL init time.
1459  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
1460  */
1461 static int
1462 rte_ixgbe_pmd_init(const char *name __rte_unused, const char *params __rte_unused)
1463 {
1464         PMD_INIT_FUNC_TRACE();
1465
1466         rte_eth_driver_register(&rte_ixgbe_pmd);
1467         return 0;
1468 }
1469
1470 /*
1471  * VF Driver initialization routine.
1472  * Invoked one at EAL init time.
1473  * Register itself as the [Virtual Poll Mode] Driver of PCI niantic devices.
1474  */
1475 static int
1476 rte_ixgbevf_pmd_init(const char *name __rte_unused, const char *param __rte_unused)
1477 {
1478         PMD_INIT_FUNC_TRACE();
1479
1480         rte_eth_driver_register(&rte_ixgbevf_pmd);
1481         return (0);
1482 }
1483
1484 static int
1485 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1486 {
1487         struct ixgbe_hw *hw =
1488                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1489         struct ixgbe_vfta * shadow_vfta =
1490                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1491         uint32_t vfta;
1492         uint32_t vid_idx;
1493         uint32_t vid_bit;
1494
1495         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1496         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1497         vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1498         if (on)
1499                 vfta |= vid_bit;
1500         else
1501                 vfta &= ~vid_bit;
1502         IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1503
1504         /* update local VFTA copy */
1505         shadow_vfta->vfta[vid_idx] = vfta;
1506
1507         return 0;
1508 }
1509
1510 static void
1511 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1512 {
1513         if (on)
1514                 ixgbe_vlan_hw_strip_enable(dev, queue);
1515         else
1516                 ixgbe_vlan_hw_strip_disable(dev, queue);
1517 }
1518
1519 static void
1520 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid)
1521 {
1522         struct ixgbe_hw *hw =
1523                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524
1525         /* Only the high 16-bits is valid */
1526         IXGBE_WRITE_REG(hw, IXGBE_EXVET, tpid << 16);
1527 }
1528
1529 void
1530 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1531 {
1532         struct ixgbe_hw *hw =
1533                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1534         uint32_t vlnctrl;
1535
1536         PMD_INIT_FUNC_TRACE();
1537
1538         /* Filter Table Disable */
1539         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1540         vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1541
1542         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1543 }
1544
1545 void
1546 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1547 {
1548         struct ixgbe_hw *hw =
1549                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1550         struct ixgbe_vfta * shadow_vfta =
1551                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1552         uint32_t vlnctrl;
1553         uint16_t i;
1554
1555         PMD_INIT_FUNC_TRACE();
1556
1557         /* Filter Table Enable */
1558         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1559         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1560         vlnctrl |= IXGBE_VLNCTRL_VFE;
1561
1562         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1563
1564         /* write whatever is in local vfta copy */
1565         for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1566                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1567 }
1568
1569 static void
1570 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1571 {
1572         struct ixgbe_hwstrip *hwstrip =
1573                 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1574
1575         if(queue >= IXGBE_MAX_RX_QUEUE_NUM)
1576                 return;
1577
1578         if (on)
1579                 IXGBE_SET_HWSTRIP(hwstrip, queue);
1580         else
1581                 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1582 }
1583
1584 static void
1585 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1586 {
1587         struct ixgbe_hw *hw =
1588                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589         uint32_t ctrl;
1590
1591         PMD_INIT_FUNC_TRACE();
1592
1593         if (hw->mac.type == ixgbe_mac_82598EB) {
1594                 /* No queue level support */
1595                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1596                 return;
1597         }
1598         else {
1599                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1600                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1601                 ctrl &= ~IXGBE_RXDCTL_VME;
1602                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1603         }
1604         /* record those setting for HW strip per queue */
1605         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1606 }
1607
1608 static void
1609 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1610 {
1611         struct ixgbe_hw *hw =
1612                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1613         uint32_t ctrl;
1614
1615         PMD_INIT_FUNC_TRACE();
1616
1617         if (hw->mac.type == ixgbe_mac_82598EB) {
1618                 /* No queue level supported */
1619                 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1620                 return;
1621         }
1622         else {
1623                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1624                 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1625                 ctrl |= IXGBE_RXDCTL_VME;
1626                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1627         }
1628         /* record those setting for HW strip per queue */
1629         ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1630 }
1631
1632 void
1633 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
1634 {
1635         struct ixgbe_hw *hw =
1636                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1637         uint32_t ctrl;
1638         uint16_t i;
1639
1640         PMD_INIT_FUNC_TRACE();
1641
1642         if (hw->mac.type == ixgbe_mac_82598EB) {
1643                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1644                 ctrl &= ~IXGBE_VLNCTRL_VME;
1645                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1646         }
1647         else {
1648                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1649                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1650                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1651                         ctrl &= ~IXGBE_RXDCTL_VME;
1652                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1653
1654                         /* record those setting for HW strip per queue */
1655                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
1656                 }
1657         }
1658 }
1659
1660 void
1661 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
1662 {
1663         struct ixgbe_hw *hw =
1664                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1665         uint32_t ctrl;
1666         uint16_t i;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         if (hw->mac.type == ixgbe_mac_82598EB) {
1671                 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1672                 ctrl |= IXGBE_VLNCTRL_VME;
1673                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
1674         }
1675         else {
1676                 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1677                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1678                         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1679                         ctrl |= IXGBE_RXDCTL_VME;
1680                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), ctrl);
1681
1682                         /* record those setting for HW strip per queue */
1683                         ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
1684                 }
1685         }
1686 }
1687
1688 static void
1689 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1690 {
1691         struct ixgbe_hw *hw =
1692                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1693         uint32_t ctrl;
1694
1695         PMD_INIT_FUNC_TRACE();
1696
1697         /* DMATXCTRL: Geric Double VLAN Disable */
1698         ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1699         ctrl &= ~IXGBE_DMATXCTL_GDV;
1700         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1701
1702         /* CTRL_EXT: Global Double VLAN Disable */
1703         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1704         ctrl &= ~IXGBE_EXTENDED_VLAN;
1705         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1706
1707 }
1708
1709 static void
1710 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1711 {
1712         struct ixgbe_hw *hw =
1713                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1714         uint32_t ctrl;
1715
1716         PMD_INIT_FUNC_TRACE();
1717
1718         /* DMATXCTRL: Geric Double VLAN Enable */
1719         ctrl  = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1720         ctrl |= IXGBE_DMATXCTL_GDV;
1721         IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1722
1723         /* CTRL_EXT: Global Double VLAN Enable */
1724         ctrl  = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1725         ctrl |= IXGBE_EXTENDED_VLAN;
1726         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1727
1728         /*
1729          * VET EXT field in the EXVET register = 0x8100 by default
1730          * So no need to change. Same to VT field of DMATXCTL register
1731          */
1732 }
1733
1734 static void
1735 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1736 {
1737         if(mask & ETH_VLAN_STRIP_MASK){
1738                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1739                         ixgbe_vlan_hw_strip_enable_all(dev);
1740                 else
1741                         ixgbe_vlan_hw_strip_disable_all(dev);
1742         }
1743
1744         if(mask & ETH_VLAN_FILTER_MASK){
1745                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
1746                         ixgbe_vlan_hw_filter_enable(dev);
1747                 else
1748                         ixgbe_vlan_hw_filter_disable(dev);
1749         }
1750
1751         if(mask & ETH_VLAN_EXTEND_MASK){
1752                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1753                         ixgbe_vlan_hw_extend_enable(dev);
1754                 else
1755                         ixgbe_vlan_hw_extend_disable(dev);
1756         }
1757 }
1758
1759 static void
1760 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1761 {
1762         struct ixgbe_hw *hw =
1763                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764         /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
1765         uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1766         vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
1767         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
1768 }
1769
1770 static int
1771 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1772 {
1773         switch (nb_rx_q) {
1774         case 1:
1775         case 2:
1776                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1777                 break;
1778         case 4:
1779                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1780                 break;
1781         default:
1782                 return -EINVAL;
1783         }
1784
1785         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
1786         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = dev->pci_dev->max_vfs * nb_rx_q;
1787
1788         return 0;
1789 }
1790
1791 static int
1792 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
1793 {
1794         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1795         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1796         uint16_t nb_tx_q = dev->data->nb_rx_queues;
1797
1798         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1799                 /* check multi-queue mode */
1800                 switch (dev_conf->rxmode.mq_mode) {
1801                 case ETH_MQ_RX_VMDQ_DCB:
1802                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1803                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1804                         PMD_INIT_LOG(ERR, "SRIOV active,"
1805                                         " unsupported mq_mode rx %d.",
1806                                         dev_conf->rxmode.mq_mode);
1807                         return -EINVAL;
1808                 case ETH_MQ_RX_RSS:
1809                 case ETH_MQ_RX_VMDQ_RSS:
1810                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1811                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1812                                 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1813                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1814                                                 " invalid queue number"
1815                                                 " for VMDQ RSS, allowed"
1816                                                 " value are 1, 2 or 4.");
1817                                         return -EINVAL;
1818                                 }
1819                         break;
1820                 case ETH_MQ_RX_VMDQ_ONLY:
1821                 case ETH_MQ_RX_NONE:
1822                         /* if nothing mq mode configure, use default scheme */
1823                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
1824                         if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
1825                                 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
1826                         break;
1827                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1828                         /* SRIOV only works in VMDq enable mode */
1829                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1830                                         " wrong mq_mode rx %d.",
1831                                         dev_conf->rxmode.mq_mode);
1832                         return -EINVAL;
1833                 }
1834
1835                 switch (dev_conf->txmode.mq_mode) {
1836                 case ETH_MQ_TX_VMDQ_DCB:
1837                         /* DCB VMDQ in SRIOV mode, not implement yet */
1838                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1839                                         " unsupported VMDQ mq_mode tx %d.",
1840                                         dev_conf->txmode.mq_mode);
1841                         return -EINVAL;
1842                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1843                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
1844                         break;
1845                 }
1846
1847                 /* check valid queue number */
1848                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1849                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1850                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1851                                         " queue number must less equal to %d.",
1852                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1853                         return -EINVAL;
1854                 }
1855         } else {
1856                 /* check configuration for vmdb+dcb mode */
1857                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1858                         const struct rte_eth_vmdq_dcb_conf *conf;
1859
1860                         if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1861                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1862                                                 IXGBE_VMDQ_DCB_NB_QUEUES);
1863                                 return -EINVAL;
1864                         }
1865                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1866                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1867                                conf->nb_queue_pools == ETH_32_POOLS)) {
1868                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1869                                                 " nb_queue_pools must be %d or %d.",
1870                                                 ETH_16_POOLS, ETH_32_POOLS);
1871                                 return -EINVAL;
1872                         }
1873                 }
1874                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1875                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1876
1877                         if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
1878                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1879                                                  IXGBE_VMDQ_DCB_NB_QUEUES);
1880                                 return -EINVAL;
1881                         }
1882                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1883                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1884                                conf->nb_queue_pools == ETH_32_POOLS)) {
1885                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1886                                                 " nb_queue_pools != %d and"
1887                                                 " nb_queue_pools != %d.",
1888                                                 ETH_16_POOLS, ETH_32_POOLS);
1889                                 return -EINVAL;
1890                         }
1891                 }
1892
1893                 /* For DCB mode check our configuration before we go further */
1894                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1895                         const struct rte_eth_dcb_rx_conf *conf;
1896
1897                         if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
1898                                 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
1899                                                  IXGBE_DCB_NB_QUEUES);
1900                                 return -EINVAL;
1901                         }
1902                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1903                         if (!(conf->nb_tcs == ETH_4_TCS ||
1904                                conf->nb_tcs == ETH_8_TCS)) {
1905                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1906                                                 " and nb_tcs != %d.",
1907                                                 ETH_4_TCS, ETH_8_TCS);
1908                                 return -EINVAL;
1909                         }
1910                 }
1911
1912                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1913                         const struct rte_eth_dcb_tx_conf *conf;
1914
1915                         if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
1916                                 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
1917                                                  IXGBE_DCB_NB_QUEUES);
1918                                 return -EINVAL;
1919                         }
1920                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1921                         if (!(conf->nb_tcs == ETH_4_TCS ||
1922                                conf->nb_tcs == ETH_8_TCS)) {
1923                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1924                                                 " and nb_tcs != %d.",
1925                                                 ETH_4_TCS, ETH_8_TCS);
1926                                 return -EINVAL;
1927                         }
1928                 }
1929         }
1930         return 0;
1931 }
1932
1933 static int
1934 ixgbe_dev_configure(struct rte_eth_dev *dev)
1935 {
1936         struct ixgbe_interrupt *intr =
1937                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1938         struct ixgbe_adapter *adapter =
1939                 (struct ixgbe_adapter *)dev->data->dev_private;
1940         int ret;
1941
1942         PMD_INIT_FUNC_TRACE();
1943         /* multipe queue mode checking */
1944         ret  = ixgbe_check_mq_mode(dev);
1945         if (ret != 0) {
1946                 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
1947                             ret);
1948                 return ret;
1949         }
1950
1951         /* set flag to update link status after init */
1952         intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1953
1954         /*
1955          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1956          * allocation or vector Rx preconditions we will reset it.
1957          */
1958         adapter->rx_bulk_alloc_allowed = true;
1959         adapter->rx_vec_allowed = true;
1960
1961         return 0;
1962 }
1963
1964 /*
1965  * Configure device link speed and setup link.
1966  * It returns 0 on success.
1967  */
1968 static int
1969 ixgbe_dev_start(struct rte_eth_dev *dev)
1970 {
1971         struct ixgbe_hw *hw =
1972                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1973         struct ixgbe_vf_info *vfinfo =
1974                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
1975         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1976         uint32_t intr_vector = 0;
1977         int err, link_up = 0, negotiate = 0;
1978         uint32_t speed = 0;
1979         int mask = 0;
1980         int status;
1981         uint16_t vf, idx;
1982
1983         PMD_INIT_FUNC_TRACE();
1984
1985         /* IXGBE devices don't support half duplex */
1986         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1987                         (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1988                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1989                              dev->data->dev_conf.link_duplex,
1990                              dev->data->port_id);
1991                 return -EINVAL;
1992         }
1993
1994         /* stop adapter */
1995         hw->adapter_stopped = 0;
1996         ixgbe_stop_adapter(hw);
1997
1998         /* reinitialize adapter
1999          * this calls reset and start */
2000         status = ixgbe_pf_reset_hw(hw);
2001         if (status != 0)
2002                 return -1;
2003         hw->mac.ops.start_hw(hw);
2004         hw->mac.get_link_status = true;
2005
2006         /* configure PF module if SRIOV enabled */
2007         ixgbe_pf_host_configure(dev);
2008
2009         /* check and configure queue intr-vector mapping */
2010         if ((rte_intr_cap_multiple(intr_handle) ||
2011              !RTE_ETH_DEV_SRIOV(dev).active) &&
2012             dev->data->dev_conf.intr_conf.rxq != 0) {
2013                 intr_vector = dev->data->nb_rx_queues;
2014                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2015                         return -1;
2016         }
2017
2018         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2019                 intr_handle->intr_vec =
2020                         rte_zmalloc("intr_vec",
2021                                     dev->data->nb_rx_queues * sizeof(int), 0);
2022                 if (intr_handle->intr_vec == NULL) {
2023                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2024                                      " intr_vec\n", dev->data->nb_rx_queues);
2025                         return -ENOMEM;
2026                 }
2027         }
2028
2029         /* confiugre msix for sleep until rx interrupt */
2030         ixgbe_configure_msix(dev);
2031
2032         /* initialize transmission unit */
2033         ixgbe_dev_tx_init(dev);
2034
2035         /* This can fail when allocating mbufs for descriptor rings */
2036         err = ixgbe_dev_rx_init(dev);
2037         if (err) {
2038                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2039                 goto error;
2040         }
2041
2042         err = ixgbe_dev_rxtx_start(dev);
2043         if (err < 0) {
2044                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2045                 goto error;
2046         }
2047
2048         /* Skip link setup if loopback mode is enabled for 82599. */
2049         if (hw->mac.type == ixgbe_mac_82599EB &&
2050                         dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2051                 goto skip_link_setup;
2052
2053         if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2054                 err = hw->mac.ops.setup_sfp(hw);
2055                 if (err)
2056                         goto error;
2057         }
2058
2059         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2060                 /* Turn on the copper */
2061                 ixgbe_set_phy_power(hw, true);
2062         } else {
2063                 /* Turn on the laser */
2064                 ixgbe_enable_tx_laser(hw);
2065         }
2066
2067         err = ixgbe_check_link(hw, &speed, &link_up, 0);
2068         if (err)
2069                 goto error;
2070         dev->data->dev_link.link_status = link_up;
2071
2072         err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2073         if (err)
2074                 goto error;
2075
2076         switch(dev->data->dev_conf.link_speed) {
2077         case ETH_LINK_SPEED_AUTONEG:
2078                 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2079                                 IXGBE_LINK_SPEED_82599_AUTONEG :
2080                                 IXGBE_LINK_SPEED_82598_AUTONEG;
2081                 break;
2082         case ETH_LINK_SPEED_100:
2083                 /*
2084                  * Invalid for 82598 but error will be detected by
2085                  * ixgbe_setup_link()
2086                  */
2087                 speed = IXGBE_LINK_SPEED_100_FULL;
2088                 break;
2089         case ETH_LINK_SPEED_1000:
2090                 speed = IXGBE_LINK_SPEED_1GB_FULL;
2091                 break;
2092         case ETH_LINK_SPEED_10000:
2093                 speed = IXGBE_LINK_SPEED_10GB_FULL;
2094                 break;
2095         default:
2096                 PMD_INIT_LOG(ERR, "Invalid link_speed (%hu) for port %hhu",
2097                              dev->data->dev_conf.link_speed,
2098                              dev->data->port_id);
2099                 goto error;
2100         }
2101
2102         err = ixgbe_setup_link(hw, speed, link_up);
2103         if (err)
2104                 goto error;
2105
2106 skip_link_setup:
2107
2108         if (rte_intr_allow_others(intr_handle)) {
2109                 /* check if lsc interrupt is enabled */
2110                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2111                         ixgbe_dev_lsc_interrupt_setup(dev);
2112         } else {
2113                 rte_intr_callback_unregister(intr_handle,
2114                                              ixgbe_dev_interrupt_handler,
2115                                              (void *)dev);
2116                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2117                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2118                                      " no intr multiplex\n");
2119         }
2120
2121         /* check if rxq interrupt is enabled */
2122         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2123             rte_intr_dp_is_en(intr_handle))
2124                 ixgbe_dev_rxq_interrupt_setup(dev);
2125
2126         /* enable uio/vfio intr/eventfd mapping */
2127         rte_intr_enable(intr_handle);
2128
2129         /* resume enabled intr since hw reset */
2130         ixgbe_enable_intr(dev);
2131
2132         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
2133                 ETH_VLAN_EXTEND_MASK;
2134         ixgbe_vlan_offload_set(dev, mask);
2135
2136         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2137                 /* Enable vlan filtering for VMDq */
2138                 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2139         }
2140
2141         /* Configure DCB hw */
2142         ixgbe_configure_dcb(dev);
2143
2144         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2145                 err = ixgbe_fdir_configure(dev);
2146                 if (err)
2147                         goto error;
2148         }
2149
2150         /* Restore vf rate limit */
2151         if (vfinfo != NULL) {
2152                 for (vf = 0; vf < dev->pci_dev->max_vfs; vf++)
2153                         for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2154                                 if (vfinfo[vf].tx_rate[idx] != 0)
2155                                         ixgbe_set_vf_rate_limit(dev, vf,
2156                                                 vfinfo[vf].tx_rate[idx],
2157                                                 1 << idx);
2158         }
2159
2160         ixgbe_restore_statistics_mapping(dev);
2161
2162         return (0);
2163
2164 error:
2165         PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2166         ixgbe_dev_clear_queues(dev);
2167         return -EIO;
2168 }
2169
2170 /*
2171  * Stop device: disable rx and tx functions to allow for reconfiguring.
2172  */
2173 static void
2174 ixgbe_dev_stop(struct rte_eth_dev *dev)
2175 {
2176         struct rte_eth_link link;
2177         struct ixgbe_hw *hw =
2178                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2179         struct ixgbe_vf_info *vfinfo =
2180                 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2181         struct ixgbe_filter_info *filter_info =
2182                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
2183         struct ixgbe_5tuple_filter *p_5tuple, *p_5tuple_next;
2184         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
2185         int vf;
2186
2187         PMD_INIT_FUNC_TRACE();
2188
2189         /* disable interrupts */
2190         ixgbe_disable_intr(hw);
2191
2192         /* disable intr eventfd mapping */
2193         rte_intr_disable(intr_handle);
2194
2195         /* reset the NIC */
2196         ixgbe_pf_reset_hw(hw);
2197         hw->adapter_stopped = 0;
2198
2199         /* stop adapter */
2200         ixgbe_stop_adapter(hw);
2201
2202         for (vf = 0; vfinfo != NULL &&
2203                      vf < dev->pci_dev->max_vfs; vf++)
2204                 vfinfo[vf].clear_to_send = false;
2205
2206         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2207                 /* Turn off the copper */
2208                 ixgbe_set_phy_power(hw, false);
2209         } else {
2210                 /* Turn off the laser */
2211                 ixgbe_disable_tx_laser(hw);
2212         }
2213
2214         ixgbe_dev_clear_queues(dev);
2215
2216         /* Clear stored conf */
2217         dev->data->scattered_rx = 0;
2218         dev->data->lro = 0;
2219
2220         /* Clear recorded link status */
2221         memset(&link, 0, sizeof(link));
2222         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2223
2224         /* Remove all ntuple filters of the device */
2225         for (p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list);
2226              p_5tuple != NULL; p_5tuple = p_5tuple_next) {
2227                 p_5tuple_next = TAILQ_NEXT(p_5tuple, entries);
2228                 TAILQ_REMOVE(&filter_info->fivetuple_list,
2229                              p_5tuple, entries);
2230                 rte_free(p_5tuple);
2231         }
2232         memset(filter_info->fivetuple_mask, 0,
2233                 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
2234
2235         if (!rte_intr_allow_others(intr_handle))
2236                 /* resume to the default handler */
2237                 rte_intr_callback_register(intr_handle,
2238                                            ixgbe_dev_interrupt_handler,
2239                                            (void *)dev);
2240
2241         /* Clean datapath event and queue/vec mapping */
2242         rte_intr_efd_disable(intr_handle);
2243         if (intr_handle->intr_vec != NULL) {
2244                 rte_free(intr_handle->intr_vec);
2245                 intr_handle->intr_vec = NULL;
2246         }
2247 }
2248
2249 /*
2250  * Set device link up: enable tx.
2251  */
2252 static int
2253 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2254 {
2255         struct ixgbe_hw *hw =
2256                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257         if (hw->mac.type == ixgbe_mac_82599EB) {
2258 #ifdef RTE_NIC_BYPASS
2259                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2260                         /* Not suported in bypass mode */
2261                         PMD_INIT_LOG(ERR, "Set link up is not supported "
2262                                      "by device id 0x%x", hw->device_id);
2263                         return -ENOTSUP;
2264                 }
2265 #endif
2266         }
2267
2268         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2269                 /* Turn on the copper */
2270                 ixgbe_set_phy_power(hw, true);
2271         } else {
2272                 /* Turn on the laser */
2273                 ixgbe_enable_tx_laser(hw);
2274         }
2275
2276         return 0;
2277 }
2278
2279 /*
2280  * Set device link down: disable tx.
2281  */
2282 static int
2283 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2284 {
2285         struct ixgbe_hw *hw =
2286                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2287         if (hw->mac.type == ixgbe_mac_82599EB) {
2288 #ifdef RTE_NIC_BYPASS
2289                 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2290                         /* Not suported in bypass mode */
2291                         PMD_INIT_LOG(ERR, "Set link down is not supported "
2292                                      "by device id 0x%x", hw->device_id);
2293                         return -ENOTSUP;
2294                 }
2295 #endif
2296         }
2297
2298         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2299                 /* Turn off the copper */
2300                 ixgbe_set_phy_power(hw, false);
2301         } else {
2302                 /* Turn off the laser */
2303                 ixgbe_disable_tx_laser(hw);
2304         }
2305
2306         return 0;
2307 }
2308
2309 /*
2310  * Reest and stop device.
2311  */
2312 static void
2313 ixgbe_dev_close(struct rte_eth_dev *dev)
2314 {
2315         struct ixgbe_hw *hw =
2316                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317
2318         PMD_INIT_FUNC_TRACE();
2319
2320         ixgbe_pf_reset_hw(hw);
2321
2322         ixgbe_dev_stop(dev);
2323         hw->adapter_stopped = 1;
2324
2325         ixgbe_dev_free_queues(dev);
2326
2327         ixgbe_disable_pcie_master(hw);
2328
2329         /* reprogram the RAR[0] in case user changed it. */
2330         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2331 }
2332
2333 static void
2334 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2335                            struct ixgbe_hw_stats *hw_stats,
2336                            uint64_t *total_missed_rx, uint64_t *total_qbrc,
2337                            uint64_t *total_qprc, uint64_t *total_qprdc)
2338 {
2339         uint32_t bprc, lxon, lxoff, total;
2340         uint32_t delta_gprc = 0;
2341         uint32_t delta_gptc = 0;
2342         unsigned i;
2343         /* Workaround for RX byte count not including CRC bytes when CRC
2344 +        * strip is enabled. CRC bytes are removed from counters when crc_strip
2345          * is disabled.
2346 +        */
2347         int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2348                         IXGBE_HLREG0_RXCRCSTRP);
2349
2350         hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2351         hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2352         hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2353         hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2354
2355         for (i = 0; i < 8; i++) {
2356                 uint32_t mp;
2357                 mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2358                 /* global total per queue */
2359                 hw_stats->mpc[i] += mp;
2360                 /* Running comprehensive total for stats display */
2361                 *total_missed_rx += hw_stats->mpc[i];
2362                 if (hw->mac.type == ixgbe_mac_82598EB) {
2363                         hw_stats->rnbc[i] +=
2364                             IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2365                         hw_stats->pxonrxc[i] +=
2366                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2367                         hw_stats->pxoffrxc[i] +=
2368                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2369                 } else {
2370                         hw_stats->pxonrxc[i] +=
2371                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2372                         hw_stats->pxoffrxc[i] +=
2373                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2374                         hw_stats->pxon2offc[i] +=
2375                                 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2376                 }
2377                 hw_stats->pxontxc[i] +=
2378                     IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2379                 hw_stats->pxofftxc[i] +=
2380                     IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2381         }
2382         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2383                 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2384                 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2385                 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2386
2387                 delta_gprc += delta_qprc;
2388                 delta_gptc += delta_qptc;
2389
2390                 hw_stats->qprc[i] += delta_qprc;
2391                 hw_stats->qptc[i] += delta_qptc;
2392
2393                 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2394                 hw_stats->qbrc[i] +=
2395                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2396                 if (crc_strip == 0)
2397                         hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2398
2399                 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2400                 hw_stats->qbtc[i] +=
2401                     ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2402
2403                 hw_stats->qprdc[i] += delta_qprdc;
2404                 *total_qprdc += hw_stats->qprdc[i];
2405
2406                 *total_qprc += hw_stats->qprc[i];
2407                 *total_qbrc += hw_stats->qbrc[i];
2408         }
2409         hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2410         hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2411         hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2412
2413         /*
2414          * An errata states that gprc actually counts good + missed packets:
2415          * Workaround to set gprc to summated queue packet receives
2416          */
2417         hw_stats->gprc = *total_qprc;
2418
2419         if (hw->mac.type != ixgbe_mac_82598EB) {
2420                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2421                 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2422                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2423                 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2424                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2425                 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2426                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2427                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2428         } else {
2429                 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2430                 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2431                 /* 82598 only has a counter in the high register */
2432                 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2433                 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2434                 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2435         }
2436         uint64_t old_tpr = hw_stats->tpr;
2437
2438         hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2439         hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2440
2441         if (crc_strip == 0)
2442                 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2443
2444         hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2445         hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2446
2447         /*
2448          * Workaround: mprc hardware is incorrectly counting
2449          * broadcasts, so for now we subtract those.
2450          */
2451         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2452         hw_stats->bprc += bprc;
2453         hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2454         if (hw->mac.type == ixgbe_mac_82598EB)
2455                 hw_stats->mprc -= bprc;
2456
2457         hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2458         hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2459         hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2460         hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2461         hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2462         hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2463
2464         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2465         hw_stats->lxontxc += lxon;
2466         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2467         hw_stats->lxofftxc += lxoff;
2468         total = lxon + lxoff;
2469
2470         hw_stats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
2471         hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2472         hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2473         hw_stats->gptc -= total;
2474         hw_stats->mptc -= total;
2475         hw_stats->ptc64 -= total;
2476         hw_stats->gotc -= total * ETHER_MIN_LEN;
2477
2478         hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2479         hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2480         hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2481         hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2482         hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2483         hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2484         hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2485         hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2486         hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2487         hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2488         hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2489         hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2490         hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2491         hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
2492         hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
2493         hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
2494         /* Only read FCOE on 82599 */
2495         if (hw->mac.type != ixgbe_mac_82598EB) {
2496                 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
2497                 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
2498                 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
2499                 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
2500                 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
2501         }
2502
2503         /* Flow Director Stats registers */
2504         hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
2505         hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
2506 }
2507
2508 /*
2509  * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
2510  */
2511 static void
2512 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2513 {
2514         struct ixgbe_hw *hw =
2515                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2516         struct ixgbe_hw_stats *hw_stats =
2517                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2518         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2519         unsigned i;
2520
2521         total_missed_rx = 0;
2522         total_qbrc = 0;
2523         total_qprc = 0;
2524         total_qprdc = 0;
2525
2526         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2527                         &total_qprc, &total_qprdc);
2528
2529         if (stats == NULL)
2530                 return;
2531
2532         /* Fill out the rte_eth_stats statistics structure */
2533         stats->ipackets = total_qprc;
2534         stats->ibytes = total_qbrc;
2535         stats->opackets = hw_stats->gptc;
2536         stats->obytes = hw_stats->gotc;
2537
2538         for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2539                 stats->q_ipackets[i] = hw_stats->qprc[i];
2540                 stats->q_opackets[i] = hw_stats->qptc[i];
2541                 stats->q_ibytes[i] = hw_stats->qbrc[i];
2542                 stats->q_obytes[i] = hw_stats->qbtc[i];
2543                 stats->q_errors[i] = hw_stats->qprdc[i];
2544         }
2545
2546         /* Rx Errors */
2547         stats->ierrors  = hw_stats->crcerrs +
2548                           hw_stats->mspdc +
2549                           hw_stats->rlec +
2550                           hw_stats->ruc +
2551                           hw_stats->roc +
2552                           total_missed_rx +
2553                           hw_stats->illerrc +
2554                           hw_stats->errbc +
2555                           hw_stats->rfc +
2556                           hw_stats->fccrc +
2557                           hw_stats->fclast;
2558
2559         /* Tx Errors */
2560         stats->oerrors  = 0;
2561 }
2562
2563 static void
2564 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
2565 {
2566         struct ixgbe_hw_stats *stats =
2567                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2568
2569         /* HW registers are cleared on read */
2570         ixgbe_dev_stats_get(dev, NULL);
2571
2572         /* Reset software totals */
2573         memset(stats, 0, sizeof(*stats));
2574 }
2575
2576 /* This function calculates the number of xstats based on the current config */
2577 static unsigned
2578 ixgbe_xstats_calc_num(void) {
2579         return IXGBE_NB_HW_STATS + (IXGBE_NB_RXQ_PRIO_STATS * 8) +
2580                 (IXGBE_NB_TXQ_PRIO_STATS * 8);
2581 }
2582
2583 static int
2584 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2585                                          unsigned n)
2586 {
2587         struct ixgbe_hw *hw =
2588                         IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2589         struct ixgbe_hw_stats *hw_stats =
2590                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2591         uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
2592         unsigned i, stat, count = 0;
2593
2594         count = ixgbe_xstats_calc_num();
2595
2596         if (n < count)
2597                 return count;
2598
2599         total_missed_rx = 0;
2600         total_qbrc = 0;
2601         total_qprc = 0;
2602         total_qprdc = 0;
2603
2604         ixgbe_read_stats_registers(hw, hw_stats, &total_missed_rx, &total_qbrc,
2605                                    &total_qprc, &total_qprdc);
2606
2607         /* If this is a reset xstats is NULL, and we have cleared the
2608          * registers by reading them.
2609          */
2610         if (!xstats)
2611                 return 0;
2612
2613         /* Extended stats from ixgbe_hw_stats */
2614         count = 0;
2615         for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
2616                 snprintf(xstats[count].name, sizeof(xstats[count].name), "%s",
2617                          rte_ixgbe_stats_strings[i].name);
2618                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2619                                 rte_ixgbe_stats_strings[i].offset);
2620                 count++;
2621         }
2622
2623         /* RX Priority Stats */
2624         for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
2625                 for (i = 0; i < 8; i++) {
2626                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2627                                  "rx_priority%u_%s", i,
2628                                  rte_ixgbe_rxq_strings[stat].name);
2629                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2630                                         rte_ixgbe_rxq_strings[stat].offset +
2631                                         (sizeof(uint64_t) * i));
2632                         count++;
2633                 }
2634         }
2635
2636         /* TX Priority Stats */
2637         for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
2638                 for (i = 0; i < 8; i++) {
2639                         snprintf(xstats[count].name, sizeof(xstats[count].name),
2640                                  "tx_priority%u_%s", i,
2641                                  rte_ixgbe_txq_strings[stat].name);
2642                         xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2643                                         rte_ixgbe_txq_strings[stat].offset +
2644                                         (sizeof(uint64_t) * i));
2645                         count++;
2646                 }
2647         }
2648
2649         return count;
2650 }
2651
2652 static void
2653 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2654 {
2655         struct ixgbe_hw_stats *stats =
2656                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2657
2658         unsigned count = ixgbe_xstats_calc_num();
2659
2660         /* HW registers are cleared on read */
2661         ixgbe_dev_xstats_get(dev, NULL, count);
2662
2663         /* Reset software totals */
2664         memset(stats, 0, sizeof(*stats));
2665 }
2666
2667 static void
2668 ixgbevf_update_stats(struct rte_eth_dev *dev)
2669 {
2670         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2671         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2672                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2673
2674         /* Good Rx packet, include VF loopback */
2675         UPDATE_VF_STAT(IXGBE_VFGPRC,
2676             hw_stats->last_vfgprc, hw_stats->vfgprc);
2677
2678         /* Good Rx octets, include VF loopback */
2679         UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
2680             hw_stats->last_vfgorc, hw_stats->vfgorc);
2681
2682         /* Good Tx packet, include VF loopback */
2683         UPDATE_VF_STAT(IXGBE_VFGPTC,
2684             hw_stats->last_vfgptc, hw_stats->vfgptc);
2685
2686         /* Good Tx octets, include VF loopback */
2687         UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
2688             hw_stats->last_vfgotc, hw_stats->vfgotc);
2689
2690         /* Rx Multicst Packet */
2691         UPDATE_VF_STAT(IXGBE_VFMPRC,
2692             hw_stats->last_vfmprc, hw_stats->vfmprc);
2693 }
2694
2695 static int
2696 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2697                        unsigned n)
2698 {
2699         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2700                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2701         unsigned i;
2702
2703         if (n < IXGBEVF_NB_XSTATS)
2704                 return IXGBEVF_NB_XSTATS;
2705
2706         ixgbevf_update_stats(dev);
2707
2708         if (!xstats)
2709                 return 0;
2710
2711         /* Extended stats */
2712         for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
2713                 snprintf(xstats[i].name, sizeof(xstats[i].name),
2714                          "%s", rte_ixgbevf_stats_strings[i].name);
2715                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
2716                         rte_ixgbevf_stats_strings[i].offset);
2717         }
2718
2719         return IXGBEVF_NB_XSTATS;
2720 }
2721
2722 static void
2723 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2724 {
2725         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
2726                           IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2727
2728         ixgbevf_update_stats(dev);
2729
2730         if (stats == NULL)
2731                 return;
2732
2733         stats->ipackets = hw_stats->vfgprc;
2734         stats->ibytes = hw_stats->vfgorc;
2735         stats->opackets = hw_stats->vfgptc;
2736         stats->obytes = hw_stats->vfgotc;
2737         stats->imcasts = hw_stats->vfmprc;
2738         /* stats->imcasts should be removed as imcasts is deprecated */
2739 }
2740
2741 static void
2742 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
2743 {
2744         struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats*)
2745                         IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
2746
2747         /* Sync HW register to the last stats */
2748         ixgbevf_dev_stats_get(dev, NULL);
2749
2750         /* reset HW current stats*/
2751         hw_stats->vfgprc = 0;
2752         hw_stats->vfgorc = 0;
2753         hw_stats->vfgptc = 0;
2754         hw_stats->vfgotc = 0;
2755         hw_stats->vfmprc = 0;
2756
2757 }
2758
2759 static void
2760 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2761 {
2762         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763
2764         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2765         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2766         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
2767         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
2768         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2769         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2770         dev_info->max_vfs = dev->pci_dev->max_vfs;
2771         if (hw->mac.type == ixgbe_mac_82598EB)
2772                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2773         else
2774                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2775         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2776         dev_info->rx_offload_capa =
2777                 DEV_RX_OFFLOAD_VLAN_STRIP |
2778                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2779                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2780                 DEV_RX_OFFLOAD_TCP_CKSUM;
2781
2782         /*
2783          * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
2784          * mode.
2785          */
2786         if ((hw->mac.type == ixgbe_mac_82599EB ||
2787              hw->mac.type == ixgbe_mac_X540) &&
2788             !RTE_ETH_DEV_SRIOV(dev).active)
2789                 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
2790
2791         dev_info->tx_offload_capa =
2792                 DEV_TX_OFFLOAD_VLAN_INSERT |
2793                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2794                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2795                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2796                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2797                 DEV_TX_OFFLOAD_TCP_TSO;
2798
2799         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2800                 .rx_thresh = {
2801                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2802                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2803                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2804                 },
2805                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2806                 .rx_drop_en = 0,
2807         };
2808
2809         dev_info->default_txconf = (struct rte_eth_txconf) {
2810                 .tx_thresh = {
2811                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2812                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2813                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2814                 },
2815                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2816                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2817                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2818                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2819         };
2820
2821         dev_info->rx_desc_lim = rx_desc_lim;
2822         dev_info->tx_desc_lim = tx_desc_lim;
2823
2824         dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2825         dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
2826         dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
2827 }
2828
2829 static void
2830 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
2831                      struct rte_eth_dev_info *dev_info)
2832 {
2833         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2834
2835         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2836         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2837         dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
2838         dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS reg */
2839         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2840         dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
2841         dev_info->max_vfs = dev->pci_dev->max_vfs;
2842         if (hw->mac.type == ixgbe_mac_82598EB)
2843                 dev_info->max_vmdq_pools = ETH_16_POOLS;
2844         else
2845                 dev_info->max_vmdq_pools = ETH_64_POOLS;
2846         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
2847                                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2848                                 DEV_RX_OFFLOAD_UDP_CKSUM  |
2849                                 DEV_RX_OFFLOAD_TCP_CKSUM;
2850         dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
2851                                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
2852                                 DEV_TX_OFFLOAD_UDP_CKSUM   |
2853                                 DEV_TX_OFFLOAD_TCP_CKSUM   |
2854                                 DEV_TX_OFFLOAD_SCTP_CKSUM  |
2855                                 DEV_TX_OFFLOAD_TCP_TSO;
2856
2857         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2858                 .rx_thresh = {
2859                         .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
2860                         .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
2861                         .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
2862                 },
2863                 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
2864                 .rx_drop_en = 0,
2865         };
2866
2867         dev_info->default_txconf = (struct rte_eth_txconf) {
2868                 .tx_thresh = {
2869                         .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
2870                         .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
2871                         .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
2872                 },
2873                 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
2874                 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
2875                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2876                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2877         };
2878
2879         dev_info->rx_desc_lim = rx_desc_lim;
2880         dev_info->tx_desc_lim = tx_desc_lim;
2881 }
2882
2883 /* return 0 means link status changed, -1 means not changed */
2884 static int
2885 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2886 {
2887         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2888         struct rte_eth_link link, old;
2889         ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
2890         int link_up;
2891         int diag;
2892
2893         link.link_status = 0;
2894         link.link_speed = 0;
2895         link.link_duplex = 0;
2896         memset(&old, 0, sizeof(old));
2897         rte_ixgbe_dev_atomic_read_link_status(dev, &old);
2898
2899         hw->mac.get_link_status = true;
2900
2901         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2902         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2903                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
2904         else
2905                 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
2906
2907         if (diag != 0) {
2908                 link.link_speed = ETH_LINK_SPEED_100;
2909                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2910                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2911                 if (link.link_status == old.link_status)
2912                         return -1;
2913                 return 0;
2914         }
2915
2916         if (link_up == 0) {
2917                 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2918                 if (link.link_status == old.link_status)
2919                         return -1;
2920                 return 0;
2921         }
2922         link.link_status = 1;
2923         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2924
2925         switch (link_speed) {
2926         default:
2927         case IXGBE_LINK_SPEED_UNKNOWN:
2928                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
2929                 link.link_speed = ETH_LINK_SPEED_100;
2930                 break;
2931
2932         case IXGBE_LINK_SPEED_100_FULL:
2933                 link.link_speed = ETH_LINK_SPEED_100;
2934                 break;
2935
2936         case IXGBE_LINK_SPEED_1GB_FULL:
2937                 link.link_speed = ETH_LINK_SPEED_1000;
2938                 break;
2939
2940         case IXGBE_LINK_SPEED_10GB_FULL:
2941                 link.link_speed = ETH_LINK_SPEED_10000;
2942                 break;
2943         }
2944         rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2945
2946         if (link.link_status == old.link_status)
2947                 return -1;
2948
2949         return 0;
2950 }
2951
2952 static void
2953 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2954 {
2955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2956         uint32_t fctrl;
2957
2958         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2959         fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2960         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2961 }
2962
2963 static void
2964 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2965 {
2966         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2967         uint32_t fctrl;
2968
2969         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2970         fctrl &= (~IXGBE_FCTRL_UPE);
2971         if (dev->data->all_multicast == 1)
2972                 fctrl |= IXGBE_FCTRL_MPE;
2973         else
2974                 fctrl &= (~IXGBE_FCTRL_MPE);
2975         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2976 }
2977
2978 static void
2979 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2980 {
2981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2982         uint32_t fctrl;
2983
2984         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2985         fctrl |= IXGBE_FCTRL_MPE;
2986         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2987 }
2988
2989 static void
2990 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2991 {
2992         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2993         uint32_t fctrl;
2994
2995         if (dev->data->promiscuous == 1)
2996                 return; /* must remain in all_multicast mode */
2997
2998         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2999         fctrl &= (~IXGBE_FCTRL_MPE);
3000         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3001 }
3002
3003 /**
3004  * It clears the interrupt causes and enables the interrupt.
3005  * It will be called once only during nic initialized.
3006  *
3007  * @param dev
3008  *  Pointer to struct rte_eth_dev.
3009  *
3010  * @return
3011  *  - On success, zero.
3012  *  - On failure, a negative value.
3013  */
3014 static int
3015 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3016 {
3017         struct ixgbe_interrupt *intr =
3018                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3019
3020         ixgbe_dev_link_status_print(dev);
3021         intr->mask |= IXGBE_EICR_LSC;
3022
3023         return 0;
3024 }
3025
3026 /**
3027  * It clears the interrupt causes and enables the interrupt.
3028  * It will be called once only during nic initialized.
3029  *
3030  * @param dev
3031  *  Pointer to struct rte_eth_dev.
3032  *
3033  * @return
3034  *  - On success, zero.
3035  *  - On failure, a negative value.
3036  */
3037 static int
3038 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3039 {
3040         struct ixgbe_interrupt *intr =
3041                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3042
3043         intr->mask |= IXGBE_EICR_RTX_QUEUE;
3044
3045         return 0;
3046 }
3047
3048 /*
3049  * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3050  *
3051  * @param dev
3052  *  Pointer to struct rte_eth_dev.
3053  *
3054  * @return
3055  *  - On success, zero.
3056  *  - On failure, a negative value.
3057  */
3058 static int
3059 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3060 {
3061         uint32_t eicr;
3062         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3063         struct ixgbe_interrupt *intr =
3064                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3065
3066         /* clear all cause mask */
3067         ixgbe_disable_intr(hw);
3068
3069         /* read-on-clear nic registers here */
3070         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3071         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
3072
3073         intr->flags = 0;
3074
3075         /* set flag for async link update */
3076         if (eicr & IXGBE_EICR_LSC)
3077                 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3078
3079         if (eicr & IXGBE_EICR_MAILBOX)
3080                 intr->flags |= IXGBE_FLAG_MAILBOX;
3081
3082         return 0;
3083 }
3084
3085 /**
3086  * It gets and then prints the link status.
3087  *
3088  * @param dev
3089  *  Pointer to struct rte_eth_dev.
3090  *
3091  * @return
3092  *  - On success, zero.
3093  *  - On failure, a negative value.
3094  */
3095 static void
3096 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
3097 {
3098         struct rte_eth_link link;
3099
3100         memset(&link, 0, sizeof(link));
3101         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3102         if (link.link_status) {
3103                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
3104                                         (int)(dev->data->port_id),
3105                                         (unsigned)link.link_speed,
3106                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
3107                                         "full-duplex" : "half-duplex");
3108         } else {
3109                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
3110                                 (int)(dev->data->port_id));
3111         }
3112         PMD_INIT_LOG(DEBUG, "PCI Address: %04d:%02d:%02d:%d",
3113                                 dev->pci_dev->addr.domain,
3114                                 dev->pci_dev->addr.bus,
3115                                 dev->pci_dev->addr.devid,
3116                                 dev->pci_dev->addr.function);
3117 }
3118
3119 /*
3120  * It executes link_update after knowing an interrupt occurred.
3121  *
3122  * @param dev
3123  *  Pointer to struct rte_eth_dev.
3124  *
3125  * @return
3126  *  - On success, zero.
3127  *  - On failure, a negative value.
3128  */
3129 static int
3130 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev)
3131 {
3132         struct ixgbe_interrupt *intr =
3133                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3134         int64_t timeout;
3135         struct rte_eth_link link;
3136         int intr_enable_delay = false;
3137
3138         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3139
3140         if (intr->flags & IXGBE_FLAG_MAILBOX) {
3141                 ixgbe_pf_mbx_process(dev);
3142                 intr->flags &= ~IXGBE_FLAG_MAILBOX;
3143         }
3144
3145         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3146                 /* get the link status before link update, for predicting later */
3147                 memset(&link, 0, sizeof(link));
3148                 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
3149
3150                 ixgbe_dev_link_update(dev, 0);
3151
3152                 /* likely to up */
3153                 if (!link.link_status)
3154                         /* handle it 1 sec later, wait it being stable */
3155                         timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
3156                 /* likely to down */
3157                 else
3158                         /* handle it 4 sec later, wait it being stable */
3159                         timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
3160
3161                 ixgbe_dev_link_status_print(dev);
3162
3163                 intr_enable_delay = true;
3164         }
3165
3166         if (intr_enable_delay) {
3167                 if (rte_eal_alarm_set(timeout * 1000,
3168                                       ixgbe_dev_interrupt_delayed_handler, (void*)dev) < 0)
3169                         PMD_DRV_LOG(ERR, "Error setting alarm");
3170         } else {
3171                 PMD_DRV_LOG(DEBUG, "enable intr immediately");
3172                 ixgbe_enable_intr(dev);
3173                 rte_intr_enable(&(dev->pci_dev->intr_handle));
3174         }
3175
3176
3177         return 0;
3178 }
3179
3180 /**
3181  * Interrupt handler which shall be registered for alarm callback for delayed
3182  * handling specific interrupt to wait for the stable nic state. As the
3183  * NIC interrupt state is not stable for ixgbe after link is just down,
3184  * it needs to wait 4 seconds to get the stable status.
3185  *
3186  * @param handle
3187  *  Pointer to interrupt handle.
3188  * @param param
3189  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3190  *
3191  * @return
3192  *  void
3193  */
3194 static void
3195 ixgbe_dev_interrupt_delayed_handler(void *param)
3196 {
3197         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3198         struct ixgbe_interrupt *intr =
3199                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3200         struct ixgbe_hw *hw =
3201                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202         uint32_t eicr;
3203
3204         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3205         if (eicr & IXGBE_EICR_MAILBOX)
3206                 ixgbe_pf_mbx_process(dev);
3207
3208         if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3209                 ixgbe_dev_link_update(dev, 0);
3210                 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3211                 ixgbe_dev_link_status_print(dev);
3212                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
3213         }
3214
3215         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3216         ixgbe_enable_intr(dev);
3217         rte_intr_enable(&(dev->pci_dev->intr_handle));
3218 }
3219
3220 /**
3221  * Interrupt handler triggered by NIC  for handling
3222  * specific interrupt.
3223  *
3224  * @param handle
3225  *  Pointer to interrupt handle.
3226  * @param param
3227  *  The address of parameter (struct rte_eth_dev *) regsitered before.
3228  *
3229  * @return
3230  *  void
3231  */
3232 static void
3233 ixgbe_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
3234                             void *param)
3235 {
3236         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3237
3238         ixgbe_dev_interrupt_get_status(dev);
3239         ixgbe_dev_interrupt_action(dev);
3240 }
3241
3242 static int
3243 ixgbe_dev_led_on(struct rte_eth_dev *dev)
3244 {
3245         struct ixgbe_hw *hw;
3246
3247         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3248         return (ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3249 }
3250
3251 static int
3252 ixgbe_dev_led_off(struct rte_eth_dev *dev)
3253 {
3254         struct ixgbe_hw *hw;
3255
3256         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3257         return (ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP);
3258 }
3259
3260 static int
3261 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3262 {
3263         struct ixgbe_hw *hw;
3264         uint32_t mflcn_reg;
3265         uint32_t fccfg_reg;
3266         int rx_pause;
3267         int tx_pause;
3268
3269         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3270
3271         fc_conf->pause_time = hw->fc.pause_time;
3272         fc_conf->high_water = hw->fc.high_water[0];
3273         fc_conf->low_water = hw->fc.low_water[0];
3274         fc_conf->send_xon = hw->fc.send_xon;
3275         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3276
3277         /*
3278          * Return rx_pause status according to actual setting of
3279          * MFLCN register.
3280          */
3281         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3282         if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
3283                 rx_pause = 1;
3284         else
3285                 rx_pause = 0;
3286
3287         /*
3288          * Return tx_pause status according to actual setting of
3289          * FCCFG register.
3290          */
3291         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3292         if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
3293                 tx_pause = 1;
3294         else
3295                 tx_pause = 0;
3296
3297         if (rx_pause && tx_pause)
3298                 fc_conf->mode = RTE_FC_FULL;
3299         else if (rx_pause)
3300                 fc_conf->mode = RTE_FC_RX_PAUSE;
3301         else if (tx_pause)
3302                 fc_conf->mode = RTE_FC_TX_PAUSE;
3303         else
3304                 fc_conf->mode = RTE_FC_NONE;
3305
3306         return 0;
3307 }
3308
3309 static int
3310 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3311 {
3312         struct ixgbe_hw *hw;
3313         int err;
3314         uint32_t rx_buf_size;
3315         uint32_t max_high_water;
3316         uint32_t mflcn;
3317         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3318                 ixgbe_fc_none,
3319                 ixgbe_fc_rx_pause,
3320                 ixgbe_fc_tx_pause,
3321                 ixgbe_fc_full
3322         };
3323
3324         PMD_INIT_FUNC_TRACE();
3325
3326         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3327         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
3328         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3329
3330         /*
3331          * At least reserve one Ethernet frame for watermark
3332          * high_water/low_water in kilo bytes for ixgbe
3333          */
3334         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3335         if ((fc_conf->high_water > max_high_water) ||
3336                 (fc_conf->high_water < fc_conf->low_water)) {
3337                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3338                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3339                 return (-EINVAL);
3340         }
3341
3342         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
3343         hw->fc.pause_time     = fc_conf->pause_time;
3344         hw->fc.high_water[0]  = fc_conf->high_water;
3345         hw->fc.low_water[0]   = fc_conf->low_water;
3346         hw->fc.send_xon       = fc_conf->send_xon;
3347         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3348
3349         err = ixgbe_fc_enable(hw);
3350
3351         /* Not negotiated is not an error case */
3352         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
3353
3354                 /* check if we want to forward MAC frames - driver doesn't have native
3355                  * capability to do that, so we'll write the registers ourselves */
3356
3357                 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3358
3359                 /* set or clear MFLCN.PMCF bit depending on configuration */
3360                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3361                         mflcn |= IXGBE_MFLCN_PMCF;
3362                 else
3363                         mflcn &= ~IXGBE_MFLCN_PMCF;
3364
3365                 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
3366                 IXGBE_WRITE_FLUSH(hw);
3367
3368                 return 0;
3369         }
3370
3371         PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
3372         return -EIO;
3373 }
3374
3375 /**
3376  *  ixgbe_pfc_enable_generic - Enable flow control
3377  *  @hw: pointer to hardware structure
3378  *  @tc_num: traffic class number
3379  *  Enable flow control according to the current settings.
3380  */
3381 static int
3382 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw,uint8_t tc_num)
3383 {
3384         int ret_val = 0;
3385         uint32_t mflcn_reg, fccfg_reg;
3386         uint32_t reg;
3387         uint32_t fcrtl, fcrth;
3388         uint8_t i;
3389         uint8_t nb_rx_en;
3390
3391         /* Validate the water mark configuration */
3392         if (!hw->fc.pause_time) {
3393                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3394                 goto out;
3395         }
3396
3397         /* Low water mark of zero causes XOFF floods */
3398         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
3399                  /* High/Low water can not be 0 */
3400                 if( (!hw->fc.high_water[tc_num])|| (!hw->fc.low_water[tc_num])) {
3401                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3402                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3403                         goto out;
3404                 }
3405
3406                 if(hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
3407                         PMD_INIT_LOG(ERR, "Invalid water mark configuration");
3408                         ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
3409                         goto out;
3410                 }
3411         }
3412         /* Negotiate the fc mode to use */
3413         ixgbe_fc_autoneg(hw);
3414
3415         /* Disable any previous flow control settings */
3416         mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
3417         mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
3418
3419         fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
3420         fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
3421
3422         switch (hw->fc.current_mode) {
3423         case ixgbe_fc_none:
3424                 /*
3425                  * If the count of enabled RX Priority Flow control >1,
3426                  * and the TX pause can not be disabled
3427                  */
3428                 nb_rx_en = 0;
3429                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3430                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3431                         if (reg & IXGBE_FCRTH_FCEN)
3432                                 nb_rx_en++;
3433                 }
3434                 if (nb_rx_en > 1)
3435                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3436                 break;
3437         case ixgbe_fc_rx_pause:
3438                 /*
3439                  * Rx Flow control is enabled and Tx Flow control is
3440                  * disabled by software override. Since there really
3441                  * isn't a way to advertise that we are capable of RX
3442                  * Pause ONLY, we will advertise that we support both
3443                  * symmetric and asymmetric Rx PAUSE.  Later, we will
3444                  * disable the adapter's ability to send PAUSE frames.
3445                  */
3446                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3447                 /*
3448                  * If the count of enabled RX Priority Flow control >1,
3449                  * and the TX pause can not be disabled
3450                  */
3451                 nb_rx_en = 0;
3452                 for (i =0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3453                         reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
3454                         if (reg & IXGBE_FCRTH_FCEN)
3455                                 nb_rx_en++;
3456                 }
3457                 if (nb_rx_en > 1)
3458                         fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3459                 break;
3460         case ixgbe_fc_tx_pause:
3461                 /*
3462                  * Tx Flow control is enabled, and Rx Flow control is
3463                  * disabled by software override.
3464                  */
3465                 fccfg_reg |=IXGBE_FCCFG_TFCE_PRIORITY;
3466                 break;
3467         case ixgbe_fc_full:
3468                 /* Flow control (both Rx and Tx) is enabled by SW override. */
3469                 mflcn_reg |= IXGBE_MFLCN_RPFCE;
3470                 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
3471                 break;
3472         default:
3473                 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
3474                 ret_val = IXGBE_ERR_CONFIG;
3475                 goto out;
3476                 break;
3477         }
3478
3479         /* Set 802.3x based flow control settings. */
3480         mflcn_reg |= IXGBE_MFLCN_DPF;
3481         IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
3482         IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
3483
3484         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
3485         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
3486                 hw->fc.high_water[tc_num]) {
3487                 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
3488                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
3489                 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
3490         } else {
3491                 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
3492                 /*
3493                  * In order to prevent Tx hangs when the internal Tx
3494                  * switch is enabled we must set the high water mark
3495                  * to the maximum FCRTH value.  This allows the Tx
3496                  * switch to function even under heavy Rx workloads.
3497                  */
3498                 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
3499         }
3500         IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
3501
3502         /* Configure pause time (2 TCs per register) */
3503         reg = hw->fc.pause_time * 0x00010001;
3504         for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
3505                 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
3506
3507         /* Configure flow control refresh threshold value */
3508         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
3509
3510 out:
3511         return ret_val;
3512 }
3513
3514 static int
3515 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev,uint8_t tc_num)
3516 {
3517         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3518         int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
3519
3520         if(hw->mac.type != ixgbe_mac_82598EB) {
3521                 ret_val = ixgbe_dcb_pfc_enable_generic(hw,tc_num);
3522         }
3523         return ret_val;
3524 }
3525
3526 static int
3527 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
3528 {
3529         int err;
3530         uint32_t rx_buf_size;
3531         uint32_t max_high_water;
3532         uint8_t tc_num;
3533         uint8_t  map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
3534         struct ixgbe_hw *hw =
3535                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536         struct ixgbe_dcb_config *dcb_config =
3537                 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3538
3539         enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
3540                 ixgbe_fc_none,
3541                 ixgbe_fc_rx_pause,
3542                 ixgbe_fc_tx_pause,
3543                 ixgbe_fc_full
3544         };
3545
3546         PMD_INIT_FUNC_TRACE();
3547
3548         ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3549         tc_num = map[pfc_conf->priority];
3550         rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
3551         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3552         /*
3553          * At least reserve one Ethernet frame for watermark
3554          * high_water/low_water in kilo bytes for ixgbe
3555          */
3556         max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
3557         if ((pfc_conf->fc.high_water > max_high_water) ||
3558             (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
3559                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3560                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3561                 return (-EINVAL);
3562         }
3563
3564         hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
3565         hw->fc.pause_time = pfc_conf->fc.pause_time;
3566         hw->fc.send_xon = pfc_conf->fc.send_xon;
3567         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3568         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3569
3570         err = ixgbe_dcb_pfc_enable(dev,tc_num);
3571
3572         /* Not negotiated is not an error case */
3573         if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
3574                 return 0;
3575
3576         PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
3577         return -EIO;
3578 }
3579
3580 static int
3581 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3582                           struct rte_eth_rss_reta_entry64 *reta_conf,
3583                           uint16_t reta_size)
3584 {
3585         uint8_t i, j, mask;
3586         uint32_t reta, r;
3587         uint16_t idx, shift;
3588         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3589         uint16_t sp_reta_size;
3590         uint32_t reta_reg;
3591
3592         PMD_INIT_FUNC_TRACE();
3593
3594         if (!ixgbe_rss_update_sp(hw->mac.type)) {
3595                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3596                         "NIC.");
3597                 return -ENOTSUP;
3598         }
3599
3600         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3601         if (reta_size != sp_reta_size) {
3602                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3603                         "(%d) doesn't match the number hardware can supported "
3604                         "(%d)\n", reta_size, sp_reta_size);
3605                 return -EINVAL;
3606         }
3607
3608         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3609                 idx = i / RTE_RETA_GROUP_SIZE;
3610                 shift = i % RTE_RETA_GROUP_SIZE;
3611                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3612                                                 IXGBE_4_BIT_MASK);
3613                 if (!mask)
3614                         continue;
3615                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3616                 if (mask == IXGBE_4_BIT_MASK)
3617                         r = 0;
3618                 else
3619                         r = IXGBE_READ_REG(hw, reta_reg);
3620                 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3621                         if (mask & (0x1 << j))
3622                                 reta |= reta_conf[idx].reta[shift + j] <<
3623                                                         (CHAR_BIT * j);
3624                         else
3625                                 reta |= r & (IXGBE_8_BIT_MASK <<
3626                                                 (CHAR_BIT * j));
3627                 }
3628                 IXGBE_WRITE_REG(hw, reta_reg, reta);
3629         }
3630
3631         return 0;
3632 }
3633
3634 static int
3635 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3636                          struct rte_eth_rss_reta_entry64 *reta_conf,
3637                          uint16_t reta_size)
3638 {
3639         uint8_t i, j, mask;
3640         uint32_t reta;
3641         uint16_t idx, shift;
3642         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3643         uint16_t sp_reta_size;
3644         uint32_t reta_reg;
3645
3646         PMD_INIT_FUNC_TRACE();
3647         sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
3648         if (reta_size != sp_reta_size) {
3649                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3650                         "(%d) doesn't match the number hardware can supported "
3651                         "(%d)\n", reta_size, sp_reta_size);
3652                 return -EINVAL;
3653         }
3654
3655         for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
3656                 idx = i / RTE_RETA_GROUP_SIZE;
3657                 shift = i % RTE_RETA_GROUP_SIZE;
3658                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
3659                                                 IXGBE_4_BIT_MASK);
3660                 if (!mask)
3661                         continue;
3662
3663                 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
3664                 reta = IXGBE_READ_REG(hw, reta_reg);
3665                 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
3666                         if (mask & (0x1 << j))
3667                                 reta_conf[idx].reta[shift + j] =
3668                                         ((reta >> (CHAR_BIT * j)) &
3669                                                 IXGBE_8_BIT_MASK);
3670                 }
3671         }
3672
3673         return 0;
3674 }
3675
3676 static void
3677 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
3678                                 uint32_t index, uint32_t pool)
3679 {
3680         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681         uint32_t enable_addr = 1;
3682
3683         ixgbe_set_rar(hw, index, mac_addr->addr_bytes, pool, enable_addr);
3684 }
3685
3686 static void
3687 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3688 {
3689         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3690
3691         ixgbe_clear_rar(hw, index);
3692 }
3693
3694 static void
3695 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
3696 {
3697         ixgbe_remove_rar(dev, 0);
3698
3699         ixgbe_add_rar(dev, addr, 0, 0);
3700 }
3701
3702 static int
3703 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3704 {
3705         uint32_t hlreg0;
3706         uint32_t maxfrs;
3707         struct ixgbe_hw *hw;
3708         struct rte_eth_dev_info dev_info;
3709         uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3710
3711         ixgbe_dev_info_get(dev, &dev_info);
3712
3713         /* check that mtu is within the allowed range */
3714         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
3715                 return -EINVAL;
3716
3717         /* refuse mtu that requires the support of scattered packets when this
3718          * feature has not been enabled before. */
3719         if (!dev->data->scattered_rx &&
3720             (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
3721              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
3722                 return -EINVAL;
3723
3724         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3726
3727         /* switch to jumbo mode if needed */
3728         if (frame_size > ETHER_MAX_LEN) {
3729                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
3730                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3731         } else {
3732                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
3733                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
3734         }
3735         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3736
3737         /* update max frame size */
3738         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3739
3740         maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
3741         maxfrs &= 0x0000FFFF;
3742         maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
3743         IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
3744
3745         return 0;
3746 }
3747
3748 /*
3749  * Virtual Function operations
3750  */
3751 static void
3752 ixgbevf_intr_disable(struct ixgbe_hw *hw)
3753 {
3754         PMD_INIT_FUNC_TRACE();
3755
3756         /* Clear interrupt mask to stop from interrupts being generated */
3757         IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
3758
3759         IXGBE_WRITE_FLUSH(hw);
3760 }
3761
3762 static void
3763 ixgbevf_intr_enable(struct ixgbe_hw *hw)
3764 {
3765         PMD_INIT_FUNC_TRACE();
3766
3767         /* VF enable interrupt autoclean */
3768         IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
3769         IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
3770         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
3771
3772         IXGBE_WRITE_FLUSH(hw);
3773 }
3774
3775 static int
3776 ixgbevf_dev_configure(struct rte_eth_dev *dev)
3777 {
3778         struct rte_eth_conf* conf = &dev->data->dev_conf;
3779         struct ixgbe_adapter *adapter =
3780                         (struct ixgbe_adapter *)dev->data->dev_private;
3781
3782         PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
3783                      dev->data->port_id);
3784
3785         /*
3786          * VF has no ability to enable/disable HW CRC
3787          * Keep the persistent behavior the same as Host PF
3788          */
3789 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
3790         if (!conf->rxmode.hw_strip_crc) {
3791                 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
3792                 conf->rxmode.hw_strip_crc = 1;
3793         }
3794 #else
3795         if (conf->rxmode.hw_strip_crc) {
3796                 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
3797                 conf->rxmode.hw_strip_crc = 0;
3798         }
3799 #endif
3800
3801         /*
3802          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
3803          * allocation or vector Rx preconditions we will reset it.
3804          */
3805         adapter->rx_bulk_alloc_allowed = true;
3806         adapter->rx_vec_allowed = true;
3807
3808         return 0;
3809 }
3810
3811 static int
3812 ixgbevf_dev_start(struct rte_eth_dev *dev)
3813 {
3814         struct ixgbe_hw *hw =
3815                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3816         uint32_t intr_vector = 0;
3817         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3818
3819         int err, mask = 0;
3820
3821         PMD_INIT_FUNC_TRACE();
3822
3823         hw->mac.ops.reset_hw(hw);
3824         hw->mac.get_link_status = true;
3825
3826         /* negotiate mailbox API version to use with the PF. */
3827         ixgbevf_negotiate_api(hw);
3828
3829         ixgbevf_dev_tx_init(dev);
3830
3831         /* This can fail when allocating mbufs for descriptor rings */
3832         err = ixgbevf_dev_rx_init(dev);
3833         if (err) {
3834                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
3835                 ixgbe_dev_clear_queues(dev);
3836                 return err;
3837         }
3838
3839         /* Set vfta */
3840         ixgbevf_set_vfta_all(dev,1);
3841
3842         /* Set HW strip */
3843         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
3844                 ETH_VLAN_EXTEND_MASK;
3845         ixgbevf_vlan_offload_set(dev, mask);
3846
3847         ixgbevf_dev_rxtx_start(dev);
3848
3849         /* check and configure queue intr-vector mapping */
3850         if (dev->data->dev_conf.intr_conf.rxq != 0) {
3851                 intr_vector = dev->data->nb_rx_queues;
3852                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3853                         return -1;
3854         }
3855
3856         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3857                 intr_handle->intr_vec =
3858                         rte_zmalloc("intr_vec",
3859                                     dev->data->nb_rx_queues * sizeof(int), 0);
3860                 if (intr_handle->intr_vec == NULL) {
3861                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
3862                                      " intr_vec\n", dev->data->nb_rx_queues);
3863                         return -ENOMEM;
3864                 }
3865         }
3866         ixgbevf_configure_msix(dev);
3867
3868         rte_intr_enable(intr_handle);
3869
3870         /* Re-enable interrupt for VF */
3871         ixgbevf_intr_enable(hw);
3872
3873         return 0;
3874 }
3875
3876 static void
3877 ixgbevf_dev_stop(struct rte_eth_dev *dev)
3878 {
3879         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3880         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
3881
3882         PMD_INIT_FUNC_TRACE();
3883
3884         hw->adapter_stopped = 1;
3885         ixgbe_stop_adapter(hw);
3886
3887         /*
3888           * Clear what we set, but we still keep shadow_vfta to
3889           * restore after device starts
3890           */
3891         ixgbevf_set_vfta_all(dev,0);
3892
3893         /* Clear stored conf */
3894         dev->data->scattered_rx = 0;
3895
3896         ixgbe_dev_clear_queues(dev);
3897
3898         /* disable intr eventfd mapping */
3899         rte_intr_disable(intr_handle);
3900
3901         /* Clean datapath event and queue/vec mapping */
3902         rte_intr_efd_disable(intr_handle);
3903         if (intr_handle->intr_vec != NULL) {
3904                 rte_free(intr_handle->intr_vec);
3905                 intr_handle->intr_vec = NULL;
3906         }
3907 }
3908
3909 static void
3910 ixgbevf_dev_close(struct rte_eth_dev *dev)
3911 {
3912         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3913
3914         PMD_INIT_FUNC_TRACE();
3915
3916         ixgbe_reset_hw(hw);
3917
3918         ixgbevf_dev_stop(dev);
3919
3920         ixgbe_dev_free_queues(dev);
3921
3922         /* reprogram the RAR[0] in case user changed it. */
3923         ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3924 }
3925
3926 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
3927 {
3928         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3929         struct ixgbe_vfta * shadow_vfta =
3930                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3931         int i = 0, j = 0, vfta = 0, mask = 1;
3932
3933         for (i = 0; i < IXGBE_VFTA_SIZE; i++){
3934                 vfta = shadow_vfta->vfta[i];
3935                 if(vfta){
3936                         mask = 1;
3937                         for (j = 0; j < 32; j++){
3938                                 if(vfta & mask)
3939                                         ixgbe_set_vfta(hw, (i<<5)+j, 0, on);
3940                                 mask<<=1;
3941                         }
3942                 }
3943         }
3944
3945 }
3946
3947 static int
3948 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3949 {
3950         struct ixgbe_hw *hw =
3951                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3952         struct ixgbe_vfta * shadow_vfta =
3953                 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
3954         uint32_t vid_idx = 0;
3955         uint32_t vid_bit = 0;
3956         int ret = 0;
3957
3958         PMD_INIT_FUNC_TRACE();
3959
3960         /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
3961         ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on);
3962         if(ret){
3963                 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
3964                 return ret;
3965         }
3966         vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
3967         vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
3968
3969         /* Save what we set and retore it after device reset */
3970         if (on)
3971                 shadow_vfta->vfta[vid_idx] |= vid_bit;
3972         else
3973                 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
3974
3975         return 0;
3976 }
3977
3978 static void
3979 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
3980 {
3981         struct ixgbe_hw *hw =
3982                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3983         uint32_t ctrl;
3984
3985         PMD_INIT_FUNC_TRACE();
3986
3987         if(queue >= hw->mac.max_rx_queues)
3988                 return;
3989
3990         ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
3991         if(on)
3992                 ctrl |= IXGBE_RXDCTL_VME;
3993         else
3994                 ctrl &= ~IXGBE_RXDCTL_VME;
3995         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
3996
3997         ixgbe_vlan_hw_strip_bitmap_set( dev, queue, on);
3998 }
3999
4000 static void
4001 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4002 {
4003         struct ixgbe_hw *hw =
4004                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4005         uint16_t i;
4006         int on = 0;
4007
4008         /* VF function only support hw strip feature, others are not support */
4009         if(mask & ETH_VLAN_STRIP_MASK){
4010                 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4011
4012                 for(i=0; i < hw->mac.max_rx_queues; i++)
4013                         ixgbevf_vlan_strip_queue_set(dev,i,on);
4014         }
4015 }
4016
4017 static int
4018 ixgbe_vmdq_mode_check(struct ixgbe_hw *hw)
4019 {
4020         uint32_t reg_val;
4021
4022         /* we only need to do this if VMDq is enabled */
4023         reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4024         if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
4025                 PMD_INIT_LOG(ERR, "VMDq must be enabled for this setting");
4026                 return (-1);
4027         }
4028
4029         return 0;
4030 }
4031
4032 static uint32_t
4033 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr* uc_addr)
4034 {
4035         uint32_t vector = 0;
4036         switch (hw->mac.mc_filter_type) {
4037         case 0:   /* use bits [47:36] of the address */
4038                 vector = ((uc_addr->addr_bytes[4] >> 4) |
4039                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
4040                 break;
4041         case 1:   /* use bits [46:35] of the address */
4042                 vector = ((uc_addr->addr_bytes[4] >> 3) |
4043                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
4044                 break;
4045         case 2:   /* use bits [45:34] of the address */
4046                 vector = ((uc_addr->addr_bytes[4] >> 2) |
4047                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
4048                 break;
4049         case 3:   /* use bits [43:32] of the address */
4050                 vector = ((uc_addr->addr_bytes[4]) |
4051                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
4052                 break;
4053         default:  /* Invalid mc_filter_type */
4054                 break;
4055         }
4056
4057         /* vector can only be 12-bits or boundary will be exceeded */
4058         vector &= 0xFFF;
4059         return vector;
4060 }
4061
4062 static int
4063 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev,struct ether_addr* mac_addr,
4064                                uint8_t on)
4065 {
4066         uint32_t vector;
4067         uint32_t uta_idx;
4068         uint32_t reg_val;
4069         uint32_t uta_shift;
4070         uint32_t rc;
4071         const uint32_t ixgbe_uta_idx_mask = 0x7F;
4072         const uint32_t ixgbe_uta_bit_shift = 5;
4073         const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
4074         const uint32_t bit1 = 0x1;
4075
4076         struct ixgbe_hw *hw =
4077                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4078         struct ixgbe_uta_info *uta_info =
4079                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4080
4081         /* The UTA table only exists on 82599 hardware and newer */
4082         if (hw->mac.type < ixgbe_mac_82599EB)
4083                 return (-ENOTSUP);
4084
4085         vector = ixgbe_uta_vector(hw,mac_addr);
4086         uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
4087         uta_shift = vector & ixgbe_uta_bit_mask;
4088
4089         rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
4090         if(rc == on)
4091                 return 0;
4092
4093         reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
4094         if (on) {
4095                 uta_info->uta_in_use++;
4096                 reg_val |= (bit1 << uta_shift);
4097                 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
4098         } else {
4099                 uta_info->uta_in_use--;
4100                 reg_val &= ~(bit1 << uta_shift);
4101                 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
4102         }
4103
4104         IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
4105
4106         if (uta_info->uta_in_use > 0)
4107                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
4108                                 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
4109         else
4110                 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,hw->mac.mc_filter_type);
4111
4112         return 0;
4113 }
4114
4115 static int
4116 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
4117 {
4118         int i;
4119         struct ixgbe_hw *hw =
4120                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121         struct ixgbe_uta_info *uta_info =
4122                 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
4123
4124         /* The UTA table only exists on 82599 hardware and newer */
4125         if (hw->mac.type < ixgbe_mac_82599EB)
4126                 return (-ENOTSUP);
4127
4128         if(on) {
4129                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4130                         uta_info->uta_shadow[i] = ~0;
4131                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
4132                 }
4133         } else {
4134                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
4135                         uta_info->uta_shadow[i] = 0;
4136                         IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
4137                 }
4138         }
4139         return 0;
4140
4141 }
4142
4143 uint32_t
4144 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
4145 {
4146         uint32_t new_val = orig_val;
4147
4148         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
4149                 new_val |= IXGBE_VMOLR_AUPE;
4150         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
4151                 new_val |= IXGBE_VMOLR_ROMPE;
4152         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
4153                 new_val |= IXGBE_VMOLR_ROPE;
4154         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
4155                 new_val |= IXGBE_VMOLR_BAM;
4156         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
4157                 new_val |= IXGBE_VMOLR_MPE;
4158
4159         return new_val;
4160 }
4161
4162 static int
4163 ixgbe_set_pool_rx_mode(struct rte_eth_dev *dev, uint16_t pool,
4164                                uint16_t rx_mask, uint8_t on)
4165 {
4166         int val = 0;
4167
4168         struct ixgbe_hw *hw =
4169                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4170         uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4171
4172         if (hw->mac.type == ixgbe_mac_82598EB) {
4173                 PMD_INIT_LOG(ERR, "setting VF receive mode set should be done"
4174                              " on 82599 hardware and newer");
4175                 return (-ENOTSUP);
4176         }
4177         if (ixgbe_vmdq_mode_check(hw) < 0)
4178                 return (-ENOTSUP);
4179
4180         val = ixgbe_convert_vm_rx_mask_to_val(rx_mask, val);
4181
4182         if (on)
4183                 vmolr |= val;
4184         else
4185                 vmolr &= ~val;
4186
4187         IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4188
4189         return 0;
4190 }
4191
4192 static int
4193 ixgbe_set_pool_rx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4194 {
4195         uint32_t reg,addr;
4196         uint32_t val;
4197         const uint8_t bit1 = 0x1;
4198
4199         struct ixgbe_hw *hw =
4200                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4201
4202         if (ixgbe_vmdq_mode_check(hw) < 0)
4203                 return (-ENOTSUP);
4204
4205         addr = IXGBE_VFRE(pool >= ETH_64_POOLS/2);
4206         reg = IXGBE_READ_REG(hw, addr);
4207         val = bit1 << pool;
4208
4209         if (on)
4210                 reg |= val;
4211         else
4212                 reg &= ~val;
4213
4214         IXGBE_WRITE_REG(hw, addr,reg);
4215
4216         return 0;
4217 }
4218
4219 static int
4220 ixgbe_set_pool_tx(struct rte_eth_dev *dev, uint16_t pool, uint8_t on)
4221 {
4222         uint32_t reg,addr;
4223         uint32_t val;
4224         const uint8_t bit1 = 0x1;
4225
4226         struct ixgbe_hw *hw =
4227                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4228
4229         if (ixgbe_vmdq_mode_check(hw) < 0)
4230                 return (-ENOTSUP);
4231
4232         addr = IXGBE_VFTE(pool >= ETH_64_POOLS/2);
4233         reg = IXGBE_READ_REG(hw, addr);
4234         val = bit1 << pool;
4235
4236         if (on)
4237                 reg |= val;
4238         else
4239                 reg &= ~val;
4240
4241         IXGBE_WRITE_REG(hw, addr,reg);
4242
4243         return 0;
4244 }
4245
4246 static int
4247 ixgbe_set_pool_vlan_filter(struct rte_eth_dev *dev, uint16_t vlan,
4248                         uint64_t pool_mask, uint8_t vlan_on)
4249 {
4250         int ret = 0;
4251         uint16_t pool_idx;
4252         struct ixgbe_hw *hw =
4253                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4254
4255         if (ixgbe_vmdq_mode_check(hw) < 0)
4256                 return (-ENOTSUP);
4257         for (pool_idx = 0; pool_idx < ETH_64_POOLS; pool_idx++) {
4258                 if (pool_mask & ((uint64_t)(1ULL << pool_idx)))
4259                         ret = hw->mac.ops.set_vfta(hw,vlan,pool_idx,vlan_on);
4260                         if (ret < 0)
4261                                 return ret;
4262         }
4263
4264         return ret;
4265 }
4266
4267 #define IXGBE_MRCTL_VPME  0x01 /* Virtual Pool Mirroring. */
4268 #define IXGBE_MRCTL_UPME  0x02 /* Uplink Port Mirroring. */
4269 #define IXGBE_MRCTL_DPME  0x04 /* Downlink Port Mirroring. */
4270 #define IXGBE_MRCTL_VLME  0x08 /* VLAN Mirroring. */
4271 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
4272         ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
4273         ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
4274
4275 static int
4276 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
4277                         struct rte_eth_mirror_conf *mirror_conf,
4278                         uint8_t rule_id, uint8_t on)
4279 {
4280         uint32_t mr_ctl,vlvf;
4281         uint32_t mp_lsb = 0;
4282         uint32_t mv_msb = 0;
4283         uint32_t mv_lsb = 0;
4284         uint32_t mp_msb = 0;
4285         uint8_t i = 0;
4286         int reg_index = 0;
4287         uint64_t vlan_mask = 0;
4288
4289         const uint8_t pool_mask_offset = 32;
4290         const uint8_t vlan_mask_offset = 32;
4291         const uint8_t dst_pool_offset = 8;
4292         const uint8_t rule_mr_offset  = 4;
4293         const uint8_t mirror_rule_mask= 0x0F;
4294
4295         struct ixgbe_mirror_info *mr_info =
4296                         (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4297         struct ixgbe_hw *hw =
4298                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4299         uint8_t mirror_type = 0;
4300
4301         if (ixgbe_vmdq_mode_check(hw) < 0)
4302                 return -ENOTSUP;
4303
4304         if (rule_id >= IXGBE_MAX_MIRROR_RULES)
4305                 return -EINVAL;
4306
4307         if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
4308                 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
4309                         mirror_conf->rule_type);
4310                 return -EINVAL;
4311         }
4312
4313         if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
4314                 mirror_type |= IXGBE_MRCTL_VLME;
4315                 /* Check if vlan id is valid and find conresponding VLAN ID index in VLVF */
4316                 for (i = 0;i < IXGBE_VLVF_ENTRIES; i++) {
4317                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
4318                                 /* search vlan id related pool vlan filter index */
4319                                 reg_index = ixgbe_find_vlvf_slot(hw,
4320                                                 mirror_conf->vlan.vlan_id[i]);
4321                                 if(reg_index < 0)
4322                                         return -EINVAL;
4323                                 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(reg_index));
4324                                 if ((vlvf & IXGBE_VLVF_VIEN) &&
4325                                     ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
4326                                       mirror_conf->vlan.vlan_id[i]))
4327                                         vlan_mask |= (1ULL << reg_index);
4328                                 else
4329                                         return -EINVAL;
4330                         }
4331                 }
4332
4333                 if (on) {
4334                         mv_lsb = vlan_mask & 0xFFFFFFFF;
4335                         mv_msb = vlan_mask >> vlan_mask_offset;
4336
4337                         mr_info->mr_conf[rule_id].vlan.vlan_mask =
4338                                                 mirror_conf->vlan.vlan_mask;
4339                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
4340                                 if(mirror_conf->vlan.vlan_mask & (1ULL << i))
4341                                         mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
4342                                                 mirror_conf->vlan.vlan_id[i];
4343                         }
4344                 } else {
4345                         mv_lsb = 0;
4346                         mv_msb = 0;
4347                         mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
4348                         for(i = 0 ;i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
4349                                 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
4350                 }
4351         }
4352
4353         /*
4354          * if enable pool mirror, write related pool mask register,if disable
4355          * pool mirror, clear PFMRVM register
4356          */
4357         if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
4358                 mirror_type |= IXGBE_MRCTL_VPME;
4359                 if (on) {
4360                         mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
4361                         mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
4362                         mr_info->mr_conf[rule_id].pool_mask =
4363                                         mirror_conf->pool_mask;
4364
4365                 } else {
4366                         mp_lsb = 0;
4367                         mp_msb = 0;
4368                         mr_info->mr_conf[rule_id].pool_mask = 0;
4369                 }
4370         }
4371         if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
4372                 mirror_type |= IXGBE_MRCTL_UPME;
4373         if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
4374                 mirror_type |= IXGBE_MRCTL_DPME;
4375
4376         /* read  mirror control register and recalculate it */
4377         mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
4378
4379         if (on) {
4380                 mr_ctl |= mirror_type;
4381                 mr_ctl &= mirror_rule_mask;
4382                 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
4383         } else
4384                 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
4385
4386         mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
4387         mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
4388
4389         /* write mirrror control  register */
4390         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4391
4392         /* write pool mirrror control  register */
4393         if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
4394                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
4395                 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
4396                                 mp_msb);
4397         }
4398         /* write VLAN mirrror control  register */
4399         if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
4400                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
4401                 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
4402                                 mv_msb);
4403         }
4404
4405         return 0;
4406 }
4407
4408 static int
4409 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
4410 {
4411         int mr_ctl = 0;
4412         uint32_t lsb_val = 0;
4413         uint32_t msb_val = 0;
4414         const uint8_t rule_mr_offset = 4;
4415
4416         struct ixgbe_hw *hw =
4417                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4418         struct ixgbe_mirror_info *mr_info =
4419                 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
4420
4421         if (ixgbe_vmdq_mode_check(hw) < 0)
4422                 return (-ENOTSUP);
4423
4424         memset(&mr_info->mr_conf[rule_id], 0,
4425                 sizeof(struct rte_eth_mirror_conf));
4426
4427         /* clear PFVMCTL register */
4428         IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
4429
4430         /* clear pool mask register */
4431         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
4432         IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
4433
4434         /* clear vlan mask register */
4435         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
4436         IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
4437
4438         return 0;
4439 }
4440
4441 static int
4442 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4443 {
4444         uint32_t mask;
4445         struct ixgbe_hw *hw =
4446                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4447
4448         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4449         mask |= (1 << IXGBE_MISC_VEC_ID);
4450         RTE_SET_USED(queue_id);
4451         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4452
4453         rte_intr_enable(&dev->pci_dev->intr_handle);
4454
4455         return 0;
4456 }
4457
4458 static int
4459 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4460 {
4461         uint32_t mask;
4462         struct ixgbe_hw *hw =
4463                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4464
4465         mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
4466         mask &= ~(1 << IXGBE_MISC_VEC_ID);
4467         RTE_SET_USED(queue_id);
4468         IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
4469
4470         return 0;
4471 }
4472
4473 static int
4474 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
4475 {
4476         uint32_t mask;
4477         struct ixgbe_hw *hw =
4478                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479         struct ixgbe_interrupt *intr =
4480                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4481
4482         if (queue_id < 16) {
4483                 ixgbe_disable_intr(hw);
4484                 intr->mask |= (1 << queue_id);
4485                 ixgbe_enable_intr(dev);
4486         } else if (queue_id < 32) {
4487                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4488                 mask &= (1 << queue_id);
4489                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4490         } else if (queue_id < 64) {
4491                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4492                 mask &= (1 << (queue_id - 32));
4493                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4494         }
4495         rte_intr_enable(&dev->pci_dev->intr_handle);
4496
4497         return 0;
4498 }
4499
4500 static int
4501 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
4502 {
4503         uint32_t mask;
4504         struct ixgbe_hw *hw =
4505                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4506         struct ixgbe_interrupt *intr =
4507                 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4508
4509         if (queue_id < 16) {
4510                 ixgbe_disable_intr(hw);
4511                 intr->mask &= ~(1 << queue_id);
4512                 ixgbe_enable_intr(dev);
4513         } else if (queue_id < 32) {
4514                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
4515                 mask &= ~(1 << queue_id);
4516                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
4517         } else if (queue_id < 64) {
4518                 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
4519                 mask &= ~(1 << (queue_id - 32));
4520                 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
4521         }
4522
4523         return 0;
4524 }
4525
4526 static void
4527 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4528                      uint8_t queue, uint8_t msix_vector)
4529 {
4530         uint32_t tmp, idx;
4531
4532         if (direction == -1) {
4533                 /* other causes */
4534                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4535                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
4536                 tmp &= ~0xFF;
4537                 tmp |= msix_vector;
4538                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
4539         } else {
4540                 /* rx or tx cause */
4541                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4542                 idx = ((16 * (queue & 1)) + (8 * direction));
4543                 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
4544                 tmp &= ~(0xFF << idx);
4545                 tmp |= (msix_vector << idx);
4546                 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
4547         }
4548 }
4549
4550 /**
4551  * set the IVAR registers, mapping interrupt causes to vectors
4552  * @param hw
4553  *  pointer to ixgbe_hw struct
4554  * @direction
4555  *  0 for Rx, 1 for Tx, -1 for other causes
4556  * @queue
4557  *  queue to map the corresponding interrupt to
4558  * @msix_vector
4559  *  the vector to map to the corresponding queue
4560  */
4561 static void
4562 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
4563                    uint8_t queue, uint8_t msix_vector)
4564 {
4565         uint32_t tmp, idx;
4566
4567         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
4568         if (hw->mac.type == ixgbe_mac_82598EB) {
4569                 if (direction == -1)
4570                         direction = 0;
4571                 idx = (((direction * 64) + queue) >> 2) & 0x1F;
4572                 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
4573                 tmp &= ~(0xFF << (8 * (queue & 0x3)));
4574                 tmp |= (msix_vector << (8 * (queue & 0x3)));
4575                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
4576         } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
4577                         (hw->mac.type == ixgbe_mac_X540)) {
4578                 if (direction == -1) {
4579                         /* other causes */
4580                         idx = ((queue & 1) * 8);
4581                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
4582                         tmp &= ~(0xFF << idx);
4583                         tmp |= (msix_vector << idx);
4584                         IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
4585                 } else {
4586                         /* rx or tx causes */
4587                         idx = ((16 * (queue & 1)) + (8 * direction));
4588                         tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
4589                         tmp &= ~(0xFF << idx);
4590                         tmp |= (msix_vector << idx);
4591                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
4592                 }
4593         }
4594 }
4595
4596 static void
4597 ixgbevf_configure_msix(struct rte_eth_dev *dev)
4598 {
4599         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4600         struct ixgbe_hw *hw =
4601                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4602         uint32_t q_idx;
4603         uint32_t vector_idx = IXGBE_MISC_VEC_ID;
4604
4605         /* won't configure msix register if no mapping is done
4606          * between intr vector and event fd.
4607          */
4608         if (!rte_intr_dp_is_en(intr_handle))
4609                 return;
4610
4611         /* Configure all RX queues of VF */
4612         for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
4613                 /* Force all queue use vector 0,
4614                  * as IXGBE_VF_MAXMSIVECOTR = 1
4615                  */
4616                 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
4617                 intr_handle->intr_vec[q_idx] = vector_idx;
4618         }
4619
4620         /* Configure VF other cause ivar */
4621         ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
4622 }
4623
4624 /**
4625  * Sets up the hardware to properly generate MSI-X interrupts
4626  * @hw
4627  *  board private structure
4628  */
4629 static void
4630 ixgbe_configure_msix(struct rte_eth_dev *dev)
4631 {
4632         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
4633         struct ixgbe_hw *hw =
4634                 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4635         uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
4636         uint32_t vec = IXGBE_MISC_VEC_ID;
4637         uint32_t mask;
4638         uint32_t gpie;
4639
4640         /* won't configure msix register if no mapping is done
4641          * between intr vector and event fd
4642          */
4643         if (!rte_intr_dp_is_en(intr_handle))
4644                 return;
4645
4646         if (rte_intr_allow_others(intr_handle))
4647                 vec = base = IXGBE_RX_VEC_START;
4648
4649         /* setup GPIE for MSI-x mode */
4650         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
4651         gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4652                 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
4653         /* auto clearing and auto setting corresponding bits in EIMS
4654          * when MSI-X interrupt is triggered
4655          */
4656         if (hw->mac.type == ixgbe_mac_82598EB) {
4657                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4658         } else {
4659                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4660                 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4661         }
4662         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4663
4664         /* Populate the IVAR table and set the ITR values to the
4665          * corresponding register.
4666          */
4667         for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
4668              queue_id++) {
4669                 /* by default, 1:1 mapping */
4670                 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
4671                 intr_handle->intr_vec[queue_id] = vec;
4672                 if (vec < base + intr_handle->nb_efd - 1)
4673                         vec++;
4674         }
4675
4676         switch (hw->mac.type) {
4677         case ixgbe_mac_82598EB:
4678                 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
4679                                    IXGBE_MISC_VEC_ID);
4680                 break;
4681         case ixgbe_mac_82599EB:
4682         case ixgbe_mac_X540:
4683                 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
4684                 break;
4685         default:
4686                 break;
4687         }
4688         IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
4689                         IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
4690
4691         /* set up to autoclear timer, and the vectors */
4692         mask = IXGBE_EIMS_ENABLE_MASK;
4693         mask &= ~(IXGBE_EIMS_OTHER |
4694                   IXGBE_EIMS_MAILBOX |
4695                   IXGBE_EIMS_LSC);
4696
4697         IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
4698 }
4699
4700 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
4701         uint16_t queue_idx, uint16_t tx_rate)
4702 {
4703         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         uint32_t rf_dec, rf_int;
4705         uint32_t bcnrc_val;
4706         uint16_t link_speed = dev->data->dev_link.link_speed;
4707
4708         if (queue_idx >= hw->mac.max_tx_queues)
4709                 return -EINVAL;
4710
4711         if (tx_rate != 0) {
4712                 /* Calculate the rate factor values to set */
4713                 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
4714                 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
4715                 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
4716
4717                 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
4718                 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
4719                                 IXGBE_RTTBCNRC_RF_INT_MASK_M);
4720                 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
4721         } else {
4722                 bcnrc_val = 0;
4723         }
4724
4725         /*
4726          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
4727          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
4728          * set as 0x4.
4729          */
4730         if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
4731                 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
4732                                 IXGBE_MAX_JUMBO_FRAME_SIZE))
4733                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4734                         IXGBE_MMW_SIZE_JUMBO_FRAME);
4735         else
4736                 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
4737                         IXGBE_MMW_SIZE_DEFAULT);
4738
4739         /* Set RTTBCNRC of queue X */
4740         IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
4741         IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
4742         IXGBE_WRITE_FLUSH(hw);
4743
4744         return 0;
4745 }
4746
4747 static int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
4748         uint16_t tx_rate, uint64_t q_msk)
4749 {
4750         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4751         struct ixgbe_vf_info *vfinfo =
4752                 *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
4753         uint8_t  nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
4754         uint32_t queue_stride =
4755                 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
4756         uint32_t queue_idx = vf * queue_stride, idx = 0, vf_idx;
4757         uint32_t queue_end = queue_idx + nb_q_per_pool - 1;
4758         uint16_t total_rate = 0;
4759
4760         if (queue_end >= hw->mac.max_tx_queues)
4761                 return -EINVAL;
4762
4763         if (vfinfo != NULL) {
4764                 for (vf_idx = 0; vf_idx < dev->pci_dev->max_vfs; vf_idx++) {
4765                         if (vf_idx == vf)
4766                                 continue;
4767                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
4768                                 idx++)
4769                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
4770                 }
4771         } else
4772                 return -EINVAL;
4773
4774         /* Store tx_rate for this vf. */
4775         for (idx = 0; idx < nb_q_per_pool; idx++) {
4776                 if (((uint64_t)0x1 << idx) & q_msk) {
4777                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
4778                                 vfinfo[vf].tx_rate[idx] = tx_rate;
4779                         total_rate += tx_rate;
4780                 }
4781         }
4782
4783         if (total_rate > dev->data->dev_link.link_speed) {
4784                 /*
4785                  * Reset stored TX rate of the VF if it causes exceed
4786                  * link speed.
4787                  */
4788                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
4789                 return -EINVAL;
4790         }
4791
4792         /* Set RTTBCNRC of each queue/pool for vf X  */
4793         for (; queue_idx <= queue_end; queue_idx++) {
4794                 if (0x1 & q_msk)
4795                         ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
4796                 q_msk = q_msk >> 1;
4797         }
4798
4799         return 0;
4800 }
4801
4802 static void
4803 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4804                      __attribute__((unused)) uint32_t index,
4805                      __attribute__((unused)) uint32_t pool)
4806 {
4807         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4808         int diag;
4809
4810         /*
4811          * On a 82599 VF, adding again the same MAC addr is not an idempotent
4812          * operation. Trap this case to avoid exhausting the [very limited]
4813          * set of PF resources used to store VF MAC addresses.
4814          */
4815         if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4816                 return;
4817         diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4818         if (diag == 0)
4819                 return;
4820         PMD_DRV_LOG(ERR, "Unable to add MAC address - diag=%d", diag);
4821 }
4822
4823 static void
4824 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
4825 {
4826         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4827         struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
4828         struct ether_addr *mac_addr;
4829         uint32_t i;
4830         int diag;
4831
4832         /*
4833          * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
4834          * not support the deletion of a given MAC address.
4835          * Instead, it imposes to delete all MAC addresses, then to add again
4836          * all MAC addresses with the exception of the one to be deleted.
4837          */
4838         (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
4839
4840         /*
4841          * Add again all MAC addresses, with the exception of the deleted one
4842          * and of the permanent MAC address.
4843          */
4844         for (i = 0, mac_addr = dev->data->mac_addrs;
4845              i < hw->mac.num_rar_entries; i++, mac_addr++) {
4846                 /* Skip the deleted MAC address */
4847                 if (i == index)
4848                         continue;
4849                 /* Skip NULL MAC addresses */
4850                 if (is_zero_ether_addr(mac_addr))
4851                         continue;
4852                 /* Skip the permanent MAC address */
4853                 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
4854                         continue;
4855                 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
4856                 if (diag != 0)
4857                         PMD_DRV_LOG(ERR,
4858                                     "Adding again MAC address "
4859                                     "%02x:%02x:%02x:%02x:%02x:%02x failed "
4860                                     "diag=%d",
4861                                     mac_addr->addr_bytes[0],
4862                                     mac_addr->addr_bytes[1],
4863                                     mac_addr->addr_bytes[2],
4864                                     mac_addr->addr_bytes[3],
4865                                     mac_addr->addr_bytes[4],
4866                                     mac_addr->addr_bytes[5],
4867                                     diag);
4868         }
4869 }
4870
4871 static void
4872 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4873 {
4874         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4875
4876         hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
4877 }
4878
4879 #define MAC_TYPE_FILTER_SUP(type)    do {\
4880         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
4881                 (type) != ixgbe_mac_X550)\
4882                 return -ENOTSUP;\
4883 } while (0)
4884
4885 static int
4886 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
4887                         struct rte_eth_syn_filter *filter,
4888                         bool add)
4889 {
4890         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4891         uint32_t synqf;
4892
4893         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
4894                 return -EINVAL;
4895
4896         synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4897
4898         if (add) {
4899                 if (synqf & IXGBE_SYN_FILTER_ENABLE)
4900                         return -EINVAL;
4901                 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
4902                         IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
4903
4904                 if (filter->hig_pri)
4905                         synqf |= IXGBE_SYN_FILTER_SYNQFP;
4906                 else
4907                         synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
4908         } else {
4909                 if (!(synqf & IXGBE_SYN_FILTER_ENABLE))
4910                         return -ENOENT;
4911                 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
4912         }
4913         IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
4914         IXGBE_WRITE_FLUSH(hw);
4915         return 0;
4916 }
4917
4918 static int
4919 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
4920                         struct rte_eth_syn_filter *filter)
4921 {
4922         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4923         uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
4924
4925         if (synqf & IXGBE_SYN_FILTER_ENABLE) {
4926                 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
4927                 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
4928                 return 0;
4929         }
4930         return -ENOENT;
4931 }
4932
4933 static int
4934 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
4935                         enum rte_filter_op filter_op,
4936                         void *arg)
4937 {
4938         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939         int ret;
4940
4941         MAC_TYPE_FILTER_SUP(hw->mac.type);
4942
4943         if (filter_op == RTE_ETH_FILTER_NOP)
4944                 return 0;
4945
4946         if (arg == NULL) {
4947                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
4948                             filter_op);
4949                 return -EINVAL;
4950         }
4951
4952         switch (filter_op) {
4953         case RTE_ETH_FILTER_ADD:
4954                 ret = ixgbe_syn_filter_set(dev,
4955                                 (struct rte_eth_syn_filter *)arg,
4956                                 TRUE);
4957                 break;
4958         case RTE_ETH_FILTER_DELETE:
4959                 ret = ixgbe_syn_filter_set(dev,
4960                                 (struct rte_eth_syn_filter *)arg,
4961                                 FALSE);
4962                 break;
4963         case RTE_ETH_FILTER_GET:
4964                 ret = ixgbe_syn_filter_get(dev,
4965                                 (struct rte_eth_syn_filter *)arg);
4966                 break;
4967         default:
4968                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
4969                 ret = -EINVAL;
4970                 break;
4971         }
4972
4973         return ret;
4974 }
4975
4976
4977 static inline enum ixgbe_5tuple_protocol
4978 convert_protocol_type(uint8_t protocol_value)
4979 {
4980         if (protocol_value == IPPROTO_TCP)
4981                 return IXGBE_FILTER_PROTOCOL_TCP;
4982         else if (protocol_value == IPPROTO_UDP)
4983                 return IXGBE_FILTER_PROTOCOL_UDP;
4984         else if (protocol_value == IPPROTO_SCTP)
4985                 return IXGBE_FILTER_PROTOCOL_SCTP;
4986         else
4987                 return IXGBE_FILTER_PROTOCOL_NONE;
4988 }
4989
4990 /*
4991  * add a 5tuple filter
4992  *
4993  * @param
4994  * dev: Pointer to struct rte_eth_dev.
4995  * index: the index the filter allocates.
4996  * filter: ponter to the filter that will be added.
4997  * rx_queue: the queue id the filter assigned to.
4998  *
4999  * @return
5000  *    - On success, zero.
5001  *    - On failure, a negative value.
5002  */
5003 static int
5004 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5005                         struct ixgbe_5tuple_filter *filter)
5006 {
5007         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5008         struct ixgbe_filter_info *filter_info =
5009                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5010         int i, idx, shift;
5011         uint32_t ftqf, sdpqf;
5012         uint32_t l34timir = 0;
5013         uint8_t mask = 0xff;
5014
5015         /*
5016          * look for an unused 5tuple filter index,
5017          * and insert the filter to list.
5018          */
5019         for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5020                 idx = i / (sizeof(uint32_t) * NBBY);
5021                 shift = i % (sizeof(uint32_t) * NBBY);
5022                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5023                         filter_info->fivetuple_mask[idx] |= 1 << shift;
5024                         filter->index = i;
5025                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5026                                           filter,
5027                                           entries);
5028                         break;
5029                 }
5030         }
5031         if (i >= IXGBE_MAX_FTQF_FILTERS) {
5032                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5033                 return -ENOSYS;
5034         }
5035
5036         sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5037                                 IXGBE_SDPQF_DSTPORT_SHIFT);
5038         sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5039
5040         ftqf = (uint32_t)(filter->filter_info.proto &
5041                 IXGBE_FTQF_PROTOCOL_MASK);
5042         ftqf |= (uint32_t)((filter->filter_info.priority &
5043                 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5044         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5045                 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5046         if (filter->filter_info.dst_ip_mask == 0)
5047                 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5048         if (filter->filter_info.src_port_mask == 0)
5049                 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5050         if (filter->filter_info.dst_port_mask == 0)
5051                 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5052         if (filter->filter_info.proto_mask == 0)
5053                 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5054         ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5055         ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5056         ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5057
5058         IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5059         IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5060         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5061         IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5062
5063         l34timir |= IXGBE_L34T_IMIR_RESERVE;
5064         l34timir |= (uint32_t)(filter->queue <<
5065                                 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5066         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5067         return 0;
5068 }
5069
5070 /*
5071  * remove a 5tuple filter
5072  *
5073  * @param
5074  * dev: Pointer to struct rte_eth_dev.
5075  * filter: the pointer of the filter will be removed.
5076  */
5077 static void
5078 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5079                         struct ixgbe_5tuple_filter *filter)
5080 {
5081         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5082         struct ixgbe_filter_info *filter_info =
5083                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5084         uint16_t index = filter->index;
5085
5086         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5087                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5088         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5089         rte_free(filter);
5090
5091         IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5092         IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5093         IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5094         IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5095         IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5096 }
5097
5098 static int
5099 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5100 {
5101         struct ixgbe_hw *hw;
5102         uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5103
5104         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5105
5106         if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5107                 return -EINVAL;
5108
5109         /* refuse mtu that requires the support of scattered packets when this
5110          * feature has not been enabled before. */
5111         if (!dev->data->scattered_rx &&
5112             (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5113              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5114                 return -EINVAL;
5115
5116         /*
5117          * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5118          * request of the version 2.0 of the mailbox API.
5119          * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5120          * of the mailbox API.
5121          * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5122          * prior to 3.11.33 which contains the following change:
5123          * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5124          */
5125         ixgbevf_rlpml_set_vf(hw, max_frame);
5126
5127         /* update max frame size */
5128         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5129         return 0;
5130 }
5131
5132 #define MAC_TYPE_FILTER_SUP_EXT(type)    do {\
5133         if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
5134                 return -ENOTSUP;\
5135 } while (0)
5136
5137 static inline struct ixgbe_5tuple_filter *
5138 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5139                         struct ixgbe_5tuple_filter_info *key)
5140 {
5141         struct ixgbe_5tuple_filter *it;
5142
5143         TAILQ_FOREACH(it, filter_list, entries) {
5144                 if (memcmp(key, &it->filter_info,
5145                         sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
5146                         return it;
5147                 }
5148         }
5149         return NULL;
5150 }
5151
5152 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
5153 static inline int
5154 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
5155                         struct ixgbe_5tuple_filter_info *filter_info)
5156 {
5157         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
5158                 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
5159                 filter->priority < IXGBE_5TUPLE_MIN_PRI)
5160                 return -EINVAL;
5161
5162         switch (filter->dst_ip_mask) {
5163         case UINT32_MAX:
5164                 filter_info->dst_ip_mask = 0;
5165                 filter_info->dst_ip = filter->dst_ip;
5166                 break;
5167         case 0:
5168                 filter_info->dst_ip_mask = 1;
5169                 break;
5170         default:
5171                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
5172                 return -EINVAL;
5173         }
5174
5175         switch (filter->src_ip_mask) {
5176         case UINT32_MAX:
5177                 filter_info->src_ip_mask = 0;
5178                 filter_info->src_ip = filter->src_ip;
5179                 break;
5180         case 0:
5181                 filter_info->src_ip_mask = 1;
5182                 break;
5183         default:
5184                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
5185                 return -EINVAL;
5186         }
5187
5188         switch (filter->dst_port_mask) {
5189         case UINT16_MAX:
5190                 filter_info->dst_port_mask = 0;
5191                 filter_info->dst_port = filter->dst_port;
5192                 break;
5193         case 0:
5194                 filter_info->dst_port_mask = 1;
5195                 break;
5196         default:
5197                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
5198                 return -EINVAL;
5199         }
5200
5201         switch (filter->src_port_mask) {
5202         case UINT16_MAX:
5203                 filter_info->src_port_mask = 0;
5204                 filter_info->src_port = filter->src_port;
5205                 break;
5206         case 0:
5207                 filter_info->src_port_mask = 1;
5208                 break;
5209         default:
5210                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
5211                 return -EINVAL;
5212         }
5213
5214         switch (filter->proto_mask) {
5215         case UINT8_MAX:
5216                 filter_info->proto_mask = 0;
5217                 filter_info->proto =
5218                         convert_protocol_type(filter->proto);
5219                 break;
5220         case 0:
5221                 filter_info->proto_mask = 1;
5222                 break;
5223         default:
5224                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
5225                 return -EINVAL;
5226         }
5227
5228         filter_info->priority = (uint8_t)filter->priority;
5229         return 0;
5230 }
5231
5232 /*
5233  * add or delete a ntuple filter
5234  *
5235  * @param
5236  * dev: Pointer to struct rte_eth_dev.
5237  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5238  * add: if true, add filter, if false, remove filter
5239  *
5240  * @return
5241  *    - On success, zero.
5242  *    - On failure, a negative value.
5243  */
5244 static int
5245 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
5246                         struct rte_eth_ntuple_filter *ntuple_filter,
5247                         bool add)
5248 {
5249         struct ixgbe_filter_info *filter_info =
5250                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5251         struct ixgbe_5tuple_filter_info filter_5tuple;
5252         struct ixgbe_5tuple_filter *filter;
5253         int ret;
5254
5255         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5256                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5257                 return -EINVAL;
5258         }
5259
5260         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5261         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5262         if (ret < 0)
5263                 return ret;
5264
5265         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5266                                          &filter_5tuple);
5267         if (filter != NULL && add) {
5268                 PMD_DRV_LOG(ERR, "filter exists.");
5269                 return -EEXIST;
5270         }
5271         if (filter == NULL && !add) {
5272                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5273                 return -ENOENT;
5274         }
5275
5276         if (add) {
5277                 filter = rte_zmalloc("ixgbe_5tuple_filter",
5278                                 sizeof(struct ixgbe_5tuple_filter), 0);
5279                 if (filter == NULL)
5280                         return -ENOMEM;
5281                 (void)rte_memcpy(&filter->filter_info,
5282                                  &filter_5tuple,
5283                                  sizeof(struct ixgbe_5tuple_filter_info));
5284                 filter->queue = ntuple_filter->queue;
5285                 ret = ixgbe_add_5tuple_filter(dev, filter);
5286                 if (ret < 0) {
5287                         rte_free(filter);
5288                         return ret;
5289                 }
5290         } else
5291                 ixgbe_remove_5tuple_filter(dev, filter);
5292
5293         return 0;
5294 }
5295
5296 /*
5297  * get a ntuple filter
5298  *
5299  * @param
5300  * dev: Pointer to struct rte_eth_dev.
5301  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
5302  *
5303  * @return
5304  *    - On success, zero.
5305  *    - On failure, a negative value.
5306  */
5307 static int
5308 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
5309                         struct rte_eth_ntuple_filter *ntuple_filter)
5310 {
5311         struct ixgbe_filter_info *filter_info =
5312                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5313         struct ixgbe_5tuple_filter_info filter_5tuple;
5314         struct ixgbe_5tuple_filter *filter;
5315         int ret;
5316
5317         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
5318                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
5319                 return -EINVAL;
5320         }
5321
5322         memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
5323         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
5324         if (ret < 0)
5325                 return ret;
5326
5327         filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
5328                                          &filter_5tuple);
5329         if (filter == NULL) {
5330                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
5331                 return -ENOENT;
5332         }
5333         ntuple_filter->queue = filter->queue;
5334         return 0;
5335 }
5336
5337 /*
5338  * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
5339  * @dev: pointer to rte_eth_dev structure
5340  * @filter_op:operation will be taken.
5341  * @arg: a pointer to specific structure corresponding to the filter_op
5342  *
5343  * @return
5344  *    - On success, zero.
5345  *    - On failure, a negative value.
5346  */
5347 static int
5348 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
5349                                 enum rte_filter_op filter_op,
5350                                 void *arg)
5351 {
5352         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5353         int ret;
5354
5355         MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
5356
5357         if (filter_op == RTE_ETH_FILTER_NOP)
5358                 return 0;
5359
5360         if (arg == NULL) {
5361                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5362                             filter_op);
5363                 return -EINVAL;
5364         }
5365
5366         switch (filter_op) {
5367         case RTE_ETH_FILTER_ADD:
5368                 ret = ixgbe_add_del_ntuple_filter(dev,
5369                         (struct rte_eth_ntuple_filter *)arg,
5370                         TRUE);
5371                 break;
5372         case RTE_ETH_FILTER_DELETE:
5373                 ret = ixgbe_add_del_ntuple_filter(dev,
5374                         (struct rte_eth_ntuple_filter *)arg,
5375                         FALSE);
5376                 break;
5377         case RTE_ETH_FILTER_GET:
5378                 ret = ixgbe_get_ntuple_filter(dev,
5379                         (struct rte_eth_ntuple_filter *)arg);
5380                 break;
5381         default:
5382                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5383                 ret = -EINVAL;
5384                 break;
5385         }
5386         return ret;
5387 }
5388
5389 static inline int
5390 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
5391                         uint16_t ethertype)
5392 {
5393         int i;
5394
5395         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5396                 if (filter_info->ethertype_filters[i] == ethertype &&
5397                     (filter_info->ethertype_mask & (1 << i)))
5398                         return i;
5399         }
5400         return -1;
5401 }
5402
5403 static inline int
5404 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
5405                         uint16_t ethertype)
5406 {
5407         int i;
5408
5409         for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
5410                 if (!(filter_info->ethertype_mask & (1 << i))) {
5411                         filter_info->ethertype_mask |= 1 << i;
5412                         filter_info->ethertype_filters[i] = ethertype;
5413                         return i;
5414                 }
5415         }
5416         return -1;
5417 }
5418
5419 static inline int
5420 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
5421                         uint8_t idx)
5422 {
5423         if (idx >= IXGBE_MAX_ETQF_FILTERS)
5424                 return -1;
5425         filter_info->ethertype_mask &= ~(1 << idx);
5426         filter_info->ethertype_filters[idx] = 0;
5427         return idx;
5428 }
5429
5430 static int
5431 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
5432                         struct rte_eth_ethertype_filter *filter,
5433                         bool add)
5434 {
5435         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5436         struct ixgbe_filter_info *filter_info =
5437                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5438         uint32_t etqf = 0;
5439         uint32_t etqs = 0;
5440         int ret;
5441
5442         if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5443                 return -EINVAL;
5444
5445         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5446                 filter->ether_type == ETHER_TYPE_IPv6) {
5447                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5448                         " ethertype filter.", filter->ether_type);
5449                 return -EINVAL;
5450         }
5451
5452         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
5453                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
5454                 return -EINVAL;
5455         }
5456         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
5457                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
5458                 return -EINVAL;
5459         }
5460
5461         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5462         if (ret >= 0 && add) {
5463                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
5464                             filter->ether_type);
5465                 return -EEXIST;
5466         }
5467         if (ret < 0 && !add) {
5468                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5469                             filter->ether_type);
5470                 return -ENOENT;
5471         }
5472
5473         if (add) {
5474                 ret = ixgbe_ethertype_filter_insert(filter_info,
5475                         filter->ether_type);
5476                 if (ret < 0) {
5477                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
5478                         return -ENOSYS;
5479                 }
5480                 etqf = IXGBE_ETQF_FILTER_EN;
5481                 etqf |= (uint32_t)filter->ether_type;
5482                 etqs |= (uint32_t)((filter->queue <<
5483                                     IXGBE_ETQS_RX_QUEUE_SHIFT) &
5484                                     IXGBE_ETQS_RX_QUEUE);
5485                 etqs |= IXGBE_ETQS_QUEUE_EN;
5486         } else {
5487                 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
5488                 if (ret < 0)
5489                         return -ENOSYS;
5490         }
5491         IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
5492         IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
5493         IXGBE_WRITE_FLUSH(hw);
5494
5495         return 0;
5496 }
5497
5498 static int
5499 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
5500                         struct rte_eth_ethertype_filter *filter)
5501 {
5502         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5503         struct ixgbe_filter_info *filter_info =
5504                 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5505         uint32_t etqf, etqs;
5506         int ret;
5507
5508         ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
5509         if (ret < 0) {
5510                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
5511                             filter->ether_type);
5512                 return -ENOENT;
5513         }
5514
5515         etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
5516         if (etqf & IXGBE_ETQF_FILTER_EN) {
5517                 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
5518                 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
5519                 filter->flags = 0;
5520                 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
5521                                IXGBE_ETQS_RX_QUEUE_SHIFT;
5522                 return 0;
5523         }
5524         return -ENOENT;
5525 }
5526
5527 /*
5528  * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
5529  * @dev: pointer to rte_eth_dev structure
5530  * @filter_op:operation will be taken.
5531  * @arg: a pointer to specific structure corresponding to the filter_op
5532  */
5533 static int
5534 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
5535                                 enum rte_filter_op filter_op,
5536                                 void *arg)
5537 {
5538         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5539         int ret;
5540
5541         MAC_TYPE_FILTER_SUP(hw->mac.type);
5542
5543         if (filter_op == RTE_ETH_FILTER_NOP)
5544                 return 0;
5545
5546         if (arg == NULL) {
5547                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
5548                             filter_op);
5549                 return -EINVAL;
5550         }
5551
5552         switch (filter_op) {
5553         case RTE_ETH_FILTER_ADD:
5554                 ret = ixgbe_add_del_ethertype_filter(dev,
5555                         (struct rte_eth_ethertype_filter *)arg,
5556                         TRUE);
5557                 break;
5558         case RTE_ETH_FILTER_DELETE:
5559                 ret = ixgbe_add_del_ethertype_filter(dev,
5560                         (struct rte_eth_ethertype_filter *)arg,
5561                         FALSE);
5562                 break;
5563         case RTE_ETH_FILTER_GET:
5564                 ret = ixgbe_get_ethertype_filter(dev,
5565                         (struct rte_eth_ethertype_filter *)arg);
5566                 break;
5567         default:
5568                 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
5569                 ret = -EINVAL;
5570                 break;
5571         }
5572         return ret;
5573 }
5574
5575 static int
5576 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
5577                      enum rte_filter_type filter_type,
5578                      enum rte_filter_op filter_op,
5579                      void *arg)
5580 {
5581         int ret = -EINVAL;
5582
5583         switch (filter_type) {
5584         case RTE_ETH_FILTER_NTUPLE:
5585                 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
5586                 break;
5587         case RTE_ETH_FILTER_ETHERTYPE:
5588                 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
5589                 break;
5590         case RTE_ETH_FILTER_SYN:
5591                 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
5592                 break;
5593         case RTE_ETH_FILTER_FDIR:
5594                 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
5595                 break;
5596         default:
5597                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5598                                                         filter_type);
5599                 break;
5600         }
5601
5602         return ret;
5603 }
5604
5605 static u8 *
5606 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
5607                         u8 **mc_addr_ptr, u32 *vmdq)
5608 {
5609         u8 *mc_addr;
5610
5611         *vmdq = 0;
5612         mc_addr = *mc_addr_ptr;
5613         *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
5614         return mc_addr;
5615 }
5616
5617 static int
5618 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
5619                           struct ether_addr *mc_addr_set,
5620                           uint32_t nb_mc_addr)
5621 {
5622         struct ixgbe_hw *hw;
5623         u8 *mc_addr_list;
5624
5625         hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5626         mc_addr_list = (u8 *)mc_addr_set;
5627         return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
5628                                          ixgbe_dev_addr_list_itr, TRUE);
5629 }
5630
5631 static uint64_t
5632 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
5633 {
5634         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5635         uint64_t systime_cycles;
5636
5637         switch (hw->mac.type) {
5638         case ixgbe_mac_X550:
5639                 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
5640                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5641                 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5642                                 * NSEC_PER_SEC;
5643                 break;
5644         default:
5645                 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
5646                 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
5647                                 << 32;
5648         }
5649
5650         return systime_cycles;
5651 }
5652
5653 static uint64_t
5654 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5655 {
5656         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5657         uint64_t rx_tstamp_cycles;
5658
5659         switch (hw->mac.type) {
5660         case ixgbe_mac_X550:
5661                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5662                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5663                 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5664                                 * NSEC_PER_SEC;
5665                 break;
5666         default:
5667                 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
5668                 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
5669                 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
5670                                 << 32;
5671         }
5672
5673         return rx_tstamp_cycles;
5674 }
5675
5676 static uint64_t
5677 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
5678 {
5679         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5680         uint64_t tx_tstamp_cycles;
5681
5682         switch (hw->mac.type) {
5683         case ixgbe_mac_X550:
5684                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5685                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5686                 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5687                                 * NSEC_PER_SEC;
5688                 break;
5689         default:
5690                 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
5691                 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
5692                 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
5693                                 << 32;
5694         }
5695
5696         return tx_tstamp_cycles;
5697 }
5698
5699 static void
5700 ixgbe_start_timecounters(struct rte_eth_dev *dev)
5701 {
5702         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5703         struct ixgbe_adapter *adapter =
5704                 (struct ixgbe_adapter *)dev->data->dev_private;
5705         struct rte_eth_link link;
5706         uint32_t incval = 0;
5707         uint32_t shift = 0;
5708
5709         /* Get current link speed. */
5710         memset(&link, 0, sizeof(link));
5711         ixgbe_dev_link_update(dev, 1);
5712         rte_ixgbe_dev_atomic_read_link_status(dev, &link);
5713
5714         switch (link.link_speed) {
5715         case ETH_LINK_SPEED_100:
5716                 incval = IXGBE_INCVAL_100;
5717                 shift = IXGBE_INCVAL_SHIFT_100;
5718                 break;
5719         case ETH_LINK_SPEED_1000:
5720                 incval = IXGBE_INCVAL_1GB;
5721                 shift = IXGBE_INCVAL_SHIFT_1GB;
5722                 break;
5723         case ETH_LINK_SPEED_10000:
5724         default:
5725                 incval = IXGBE_INCVAL_10GB;
5726                 shift = IXGBE_INCVAL_SHIFT_10GB;
5727                 break;
5728         }
5729
5730         switch (hw->mac.type) {
5731         case ixgbe_mac_X550:
5732                 /* Independent of link speed. */
5733                 incval = 1;
5734                 /* Cycles read will be interpreted as ns. */
5735                 shift = 0;
5736                 /* Fall-through */
5737         case ixgbe_mac_X540:
5738                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
5739                 break;
5740         case ixgbe_mac_82599EB:
5741                 incval >>= IXGBE_INCVAL_SHIFT_82599;
5742                 shift -= IXGBE_INCVAL_SHIFT_82599;
5743                 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
5744                                 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
5745                 break;
5746         default:
5747                 /* Not supported. */
5748                 return;
5749         }
5750
5751         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
5752         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5753         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
5754
5755         adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5756         adapter->systime_tc.cc_shift = shift;
5757         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
5758
5759         adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5760         adapter->rx_tstamp_tc.cc_shift = shift;
5761         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5762
5763         adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
5764         adapter->tx_tstamp_tc.cc_shift = shift;
5765         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
5766 }
5767
5768 static int
5769 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
5770 {
5771         struct ixgbe_adapter *adapter =
5772                         (struct ixgbe_adapter *)dev->data->dev_private;
5773
5774         adapter->systime_tc.nsec += delta;
5775         adapter->rx_tstamp_tc.nsec += delta;
5776         adapter->tx_tstamp_tc.nsec += delta;
5777
5778         return 0;
5779 }
5780
5781 static int
5782 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
5783 {
5784         uint64_t ns;
5785         struct ixgbe_adapter *adapter =
5786                         (struct ixgbe_adapter *)dev->data->dev_private;
5787
5788         ns = rte_timespec_to_ns(ts);
5789         /* Set the timecounters to a new value. */
5790         adapter->systime_tc.nsec = ns;
5791         adapter->rx_tstamp_tc.nsec = ns;
5792         adapter->tx_tstamp_tc.nsec = ns;
5793
5794         return 0;
5795 }
5796
5797 static int
5798 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
5799 {
5800         uint64_t ns, systime_cycles;
5801         struct ixgbe_adapter *adapter =
5802                         (struct ixgbe_adapter *)dev->data->dev_private;
5803
5804         systime_cycles = ixgbe_read_systime_cyclecounter(dev);
5805         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
5806         *ts = rte_ns_to_timespec(ns);
5807
5808         return 0;
5809 }
5810
5811 static int
5812 ixgbe_timesync_enable(struct rte_eth_dev *dev)
5813 {
5814         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5815         uint32_t tsync_ctl;
5816         uint32_t tsauxc;
5817
5818         /* Stop the timesync system time. */
5819         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
5820         /* Reset the timesync system time value. */
5821         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
5822         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
5823
5824         /* Enable system time for platforms where it isn't on by default. */
5825         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
5826         tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
5827         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
5828
5829         ixgbe_start_timecounters(dev);
5830
5831         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5832         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
5833                         (ETHER_TYPE_1588 |
5834                          IXGBE_ETQF_FILTER_EN |
5835                          IXGBE_ETQF_1588));
5836
5837         /* Enable timestamping of received PTP packets. */
5838         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5839         tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
5840         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5841
5842         /* Enable timestamping of transmitted PTP packets. */
5843         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5844         tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
5845         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5846
5847         IXGBE_WRITE_FLUSH(hw);
5848
5849         return 0;
5850 }
5851
5852 static int
5853 ixgbe_timesync_disable(struct rte_eth_dev *dev)
5854 {
5855         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5856         uint32_t tsync_ctl;
5857
5858         /* Disable timestamping of transmitted PTP packets. */
5859         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5860         tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
5861         IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
5862
5863         /* Disable timestamping of received PTP packets. */
5864         tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5865         tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
5866         IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
5867
5868         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
5869         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
5870
5871         /* Stop incrementating the System Time registers. */
5872         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
5873
5874         return 0;
5875 }
5876
5877 static int
5878 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
5879                                  struct timespec *timestamp,
5880                                  uint32_t flags __rte_unused)
5881 {
5882         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5883         struct ixgbe_adapter *adapter =
5884                 (struct ixgbe_adapter *)dev->data->dev_private;
5885         uint32_t tsync_rxctl;
5886         uint64_t rx_tstamp_cycles;
5887         uint64_t ns;
5888
5889         tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
5890         if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
5891                 return -EINVAL;
5892
5893         rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
5894         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
5895         *timestamp = rte_ns_to_timespec(ns);
5896
5897         return  0;
5898 }
5899
5900 static int
5901 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
5902                                  struct timespec *timestamp)
5903 {
5904         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5905         struct ixgbe_adapter *adapter =
5906                 (struct ixgbe_adapter *)dev->data->dev_private;
5907         uint32_t tsync_txctl;
5908         uint64_t tx_tstamp_cycles;
5909         uint64_t ns;
5910
5911         tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
5912         if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
5913                 return -EINVAL;
5914
5915         tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
5916         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
5917         *timestamp = rte_ns_to_timespec(ns);
5918
5919         return 0;
5920 }
5921
5922 static int
5923 ixgbe_get_reg_length(struct rte_eth_dev *dev)
5924 {
5925         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5926         int count = 0;
5927         int g_ind = 0;
5928         const struct reg_info *reg_group;
5929         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5930                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5931
5932         while ((reg_group = reg_set[g_ind++]))
5933                 count += ixgbe_regs_group_count(reg_group);
5934
5935         return count;
5936 }
5937
5938 static int
5939 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
5940 {
5941         int count = 0;
5942         int g_ind = 0;
5943         const struct reg_info *reg_group;
5944
5945         while ((reg_group = ixgbevf_regs[g_ind++]))
5946                 count += ixgbe_regs_group_count(reg_group);
5947
5948         return count;
5949 }
5950
5951 static int
5952 ixgbe_get_regs(struct rte_eth_dev *dev,
5953               struct rte_dev_reg_info *regs)
5954 {
5955         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5956         uint32_t *data = regs->data;
5957         int g_ind = 0;
5958         int count = 0;
5959         const struct reg_info *reg_group;
5960         const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
5961                                     ixgbe_regs_mac_82598EB : ixgbe_regs_others;
5962
5963         /* Support only full register dump */
5964         if ((regs->length == 0) ||
5965             (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
5966                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5967                         hw->device_id;
5968                 while ((reg_group = reg_set[g_ind++]))
5969                         count += ixgbe_read_regs_group(dev, &data[count],
5970                                 reg_group);
5971                 return 0;
5972         }
5973
5974         return -ENOTSUP;
5975 }
5976
5977 static int
5978 ixgbevf_get_regs(struct rte_eth_dev *dev,
5979                 struct rte_dev_reg_info *regs)
5980 {
5981         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5982         uint32_t *data = regs->data;
5983         int g_ind = 0;
5984         int count = 0;
5985         const struct reg_info *reg_group;
5986
5987         /* Support only full register dump */
5988         if ((regs->length == 0) ||
5989             (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
5990                 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
5991                         hw->device_id;
5992                 while ((reg_group = ixgbevf_regs[g_ind++]))
5993                         count += ixgbe_read_regs_group(dev, &data[count],
5994                                                       reg_group);
5995                 return 0;
5996         }
5997
5998         return -ENOTSUP;
5999 }
6000
6001 static int
6002 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6003 {
6004         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6005
6006         /* Return unit is byte count */
6007         return hw->eeprom.word_size * 2;
6008 }
6009
6010 static int
6011 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6012                 struct rte_dev_eeprom_info *in_eeprom)
6013 {
6014         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6015         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6016         uint16_t *data = in_eeprom->data;
6017         int first, length;
6018
6019         first = in_eeprom->offset >> 1;
6020         length = in_eeprom->length >> 1;
6021         if ((first > hw->eeprom.word_size) ||
6022             ((first + length) > hw->eeprom.word_size))
6023                 return -EINVAL;
6024
6025         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6026
6027         return eeprom->ops.read_buffer(hw, first, length, data);
6028 }
6029
6030 static int
6031 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6032                 struct rte_dev_eeprom_info *in_eeprom)
6033 {
6034         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6035         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6036         uint16_t *data = in_eeprom->data;
6037         int first, length;
6038
6039         first = in_eeprom->offset >> 1;
6040         length = in_eeprom->length >> 1;
6041         if ((first > hw->eeprom.word_size) ||
6042             ((first + length) > hw->eeprom.word_size))
6043                 return -EINVAL;
6044
6045         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6046
6047         return eeprom->ops.write_buffer(hw,  first, length, data);
6048 }
6049
6050 uint16_t
6051 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6052         switch (mac_type) {
6053         case ixgbe_mac_X550:
6054         case ixgbe_mac_X550EM_x:
6055                 return ETH_RSS_RETA_SIZE_512;
6056         case ixgbe_mac_X550_vf:
6057         case ixgbe_mac_X550EM_x_vf:
6058                 return ETH_RSS_RETA_SIZE_64;
6059         default:
6060                 return ETH_RSS_RETA_SIZE_128;
6061         }
6062 }
6063
6064 uint32_t
6065 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6066         switch (mac_type) {
6067         case ixgbe_mac_X550:
6068         case ixgbe_mac_X550EM_x:
6069                 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6070                         return IXGBE_RETA(reta_idx >> 2);
6071                 else
6072                         return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6073         case ixgbe_mac_X550_vf:
6074         case ixgbe_mac_X550EM_x_vf:
6075                 return IXGBE_VFRETA(reta_idx >> 2);
6076         default:
6077                 return IXGBE_RETA(reta_idx >> 2);
6078         }
6079 }
6080
6081 uint32_t
6082 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6083         switch (mac_type) {
6084         case ixgbe_mac_X550_vf:
6085         case ixgbe_mac_X550EM_x_vf:
6086                 return IXGBE_VFMRQC;
6087         default:
6088                 return IXGBE_MRQC;
6089         }
6090 }
6091
6092 uint32_t
6093 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6094         switch (mac_type) {
6095         case ixgbe_mac_X550_vf:
6096         case ixgbe_mac_X550EM_x_vf:
6097                 return IXGBE_VFRSSRK(i);
6098         default:
6099                 return IXGBE_RSSRK(i);
6100         }
6101 }
6102
6103 bool
6104 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6105         switch (mac_type) {
6106         case ixgbe_mac_82599_vf:
6107         case ixgbe_mac_X540_vf:
6108                 return 0;
6109         default:
6110                 return 1;
6111         }
6112 }
6113
6114 static int
6115 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6116                         struct rte_eth_dcb_info *dcb_info)
6117 {
6118         struct ixgbe_dcb_config *dcb_config =
6119                         IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6120         struct ixgbe_dcb_tc_config *tc;
6121         uint8_t i, j;
6122
6123         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6124                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6125         else
6126                 dcb_info->nb_tcs = 1;
6127
6128         if (dcb_config->vt_mode) { /* vt is enabled*/
6129                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6130                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6131                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6132                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6133                 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6134                         for (j = 0; j < dcb_info->nb_tcs; j++) {
6135                                 dcb_info->tc_queue.tc_rxq[i][j].base =
6136                                                 i * dcb_info->nb_tcs + j;
6137                                 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6138                                 dcb_info->tc_queue.tc_txq[i][j].base =
6139                                                 i * dcb_info->nb_tcs + j;
6140                                 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
6141                         }
6142                 }
6143         } else { /* vt is disabled*/
6144                 struct rte_eth_dcb_rx_conf *rx_conf =
6145                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
6146                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6147                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
6148                 if (dcb_info->nb_tcs == ETH_4_TCS) {
6149                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6150                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
6151                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6152                         }
6153                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6154                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
6155                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
6156                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
6157                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
6158                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6159                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6160                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6161                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
6162                         for (i = 0; i < dcb_info->nb_tcs; i++) {
6163                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
6164                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
6165                         }
6166                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
6167                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
6168                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
6169                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
6170                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
6171                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
6172                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
6173                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
6174                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
6175                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
6176                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
6177                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
6178                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
6179                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
6180                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
6181                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
6182                 }
6183         }
6184         for (i = 0; i < dcb_info->nb_tcs; i++) {
6185                 tc = &dcb_config->tc_config[i];
6186                 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
6187         }
6188         return 0;
6189 }
6190
6191 static struct rte_driver rte_ixgbe_driver = {
6192         .type = PMD_PDEV,
6193         .init = rte_ixgbe_pmd_init,
6194 };
6195
6196 static struct rte_driver rte_ixgbevf_driver = {
6197         .type = PMD_PDEV,
6198         .init = rte_ixgbevf_pmd_init,
6199 };
6200
6201 PMD_REGISTER_DRIVER(rte_ixgbe_driver);
6202 PMD_REGISTER_DRIVER(rte_ixgbevf_driver);