1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
13 #include <netinet/in.h>
14 #include <rte_byteorder.h>
15 #include <rte_common.h>
16 #include <rte_cycles.h>
18 #include <rte_interrupts.h>
20 #include <rte_debug.h>
22 #include <rte_bus_pci.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
26 #include <rte_alarm.h>
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
30 #include <rte_malloc.h>
31 #include <rte_random.h>
33 #include <rte_hash_crc.h>
34 #ifdef RTE_LIBRTE_SECURITY
35 #include <rte_security_driver.h>
38 #include "ixgbe_logs.h"
39 #include "base/ixgbe_api.h"
40 #include "base/ixgbe_vf.h"
41 #include "base/ixgbe_common.h"
42 #include "ixgbe_ethdev.h"
43 #include "ixgbe_bypass.h"
44 #include "ixgbe_rxtx.h"
45 #include "base/ixgbe_type.h"
46 #include "base/ixgbe_phy.h"
47 #include "ixgbe_regs.h"
50 * High threshold controlling when to start sending XOFF frames. Must be at
51 * least 8 bytes less than receive packet buffer size. This value is in units
54 #define IXGBE_FC_HI 0x80
57 * Low threshold controlling when to start sending XON frames. This value is
58 * in units of 1024 bytes.
60 #define IXGBE_FC_LO 0x40
62 /* Default minimum inter-interrupt interval for EITR configuration */
63 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
65 /* Timer value included in XOFF frames. */
66 #define IXGBE_FC_PAUSE 0x680
68 /*Default value of Max Rx Queue*/
69 #define IXGBE_MAX_RX_QUEUE_NUM 128
71 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
72 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
73 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
75 #define IXGBE_MMW_SIZE_DEFAULT 0x4
76 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
77 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
80 * Default values for RX/TX configuration
82 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
83 #define IXGBE_DEFAULT_RX_PTHRESH 8
84 #define IXGBE_DEFAULT_RX_HTHRESH 8
85 #define IXGBE_DEFAULT_RX_WTHRESH 0
87 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
88 #define IXGBE_DEFAULT_TX_PTHRESH 32
89 #define IXGBE_DEFAULT_TX_HTHRESH 0
90 #define IXGBE_DEFAULT_TX_WTHRESH 0
91 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
93 /* Bit shift and mask */
94 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
95 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
96 #define IXGBE_8_BIT_WIDTH CHAR_BIT
97 #define IXGBE_8_BIT_MASK UINT8_MAX
99 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
101 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
103 #define IXGBE_HKEY_MAX_INDEX 10
105 /* Additional timesync values. */
106 #define NSEC_PER_SEC 1000000000L
107 #define IXGBE_INCVAL_10GB 0x66666666
108 #define IXGBE_INCVAL_1GB 0x40000000
109 #define IXGBE_INCVAL_100 0x50000000
110 #define IXGBE_INCVAL_SHIFT_10GB 28
111 #define IXGBE_INCVAL_SHIFT_1GB 24
112 #define IXGBE_INCVAL_SHIFT_100 21
113 #define IXGBE_INCVAL_SHIFT_82599 7
114 #define IXGBE_INCPER_SHIFT_82599 24
116 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
119 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
120 #define DEFAULT_ETAG_ETYPE 0x893f
121 #define IXGBE_ETAG_ETYPE 0x00005084
122 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
123 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
124 #define IXGBE_RAH_ADTYPE 0x40000000
125 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
126 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
127 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
128 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
129 #define IXGBE_QDE_STRIP_TAG 0x00000004
130 #define IXGBE_VTEICR_MASK 0x07
132 #define IXGBE_EXVET_VET_EXT_SHIFT 16
133 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
135 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
136 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
137 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
138 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
139 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
140 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
141 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
142 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
143 static int ixgbe_dev_start(struct rte_eth_dev *dev);
144 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
145 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
146 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
147 static void ixgbe_dev_close(struct rte_eth_dev *dev);
148 static int ixgbe_dev_reset(struct rte_eth_dev *dev);
149 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
150 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
151 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
152 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
153 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
154 int wait_to_complete);
155 static int ixgbe_dev_stats_get(struct rte_eth_dev *dev,
156 struct rte_eth_stats *stats);
157 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
158 struct rte_eth_xstat *xstats, unsigned n);
159 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
160 struct rte_eth_xstat *xstats, unsigned n);
162 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
163 uint64_t *values, unsigned int n);
164 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
165 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
166 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
167 struct rte_eth_xstat_name *xstats_names,
169 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
170 struct rte_eth_xstat_name *xstats_names, unsigned limit);
171 static int ixgbe_dev_xstats_get_names_by_id(
172 struct rte_eth_dev *dev,
173 struct rte_eth_xstat_name *xstats_names,
176 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
180 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
182 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
183 struct rte_eth_dev_info *dev_info);
184 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
185 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
186 struct rte_eth_dev_info *dev_info);
187 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
189 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
190 uint16_t vlan_id, int on);
191 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
192 enum rte_vlan_type vlan_type,
194 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
195 uint16_t queue, bool on);
196 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
198 static int ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
199 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
200 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
201 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
202 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
204 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
205 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
206 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
207 struct rte_eth_fc_conf *fc_conf);
208 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
209 struct rte_eth_fc_conf *fc_conf);
210 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
211 struct rte_eth_pfc_conf *pfc_conf);
212 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
213 struct rte_eth_rss_reta_entry64 *reta_conf,
215 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
216 struct rte_eth_rss_reta_entry64 *reta_conf,
218 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
219 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
220 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
221 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
222 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
223 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
224 struct rte_intr_handle *handle);
225 static void ixgbe_dev_interrupt_handler(void *param);
226 static void ixgbe_dev_interrupt_delayed_handler(void *param);
227 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
228 uint32_t index, uint32_t pool);
229 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
230 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
231 struct ether_addr *mac_addr);
232 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
233 static bool is_device_supported(struct rte_eth_dev *dev,
234 struct rte_pci_driver *drv);
236 /* For Virtual Function support */
237 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
238 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
239 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
240 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
241 static int ixgbevf_dev_link_update(struct rte_eth_dev *dev,
242 int wait_to_complete);
243 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
244 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
245 static int ixgbevf_dev_reset(struct rte_eth_dev *dev);
246 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
247 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
248 static int ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
249 struct rte_eth_stats *stats);
250 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
251 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
252 uint16_t vlan_id, int on);
253 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 uint16_t queue, int on);
255 static int ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
257 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
259 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
261 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
262 uint8_t queue, uint8_t msix_vector);
263 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
264 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
267 /* For Eth VMDQ APIs support */
268 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
269 ether_addr * mac_addr, uint8_t on);
270 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
271 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
272 struct rte_eth_mirror_conf *mirror_conf,
273 uint8_t rule_id, uint8_t on);
274 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
276 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
278 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
280 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
281 uint8_t queue, uint8_t msix_vector);
282 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
284 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
285 struct ether_addr *mac_addr,
286 uint32_t index, uint32_t pool);
287 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
288 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
289 struct ether_addr *mac_addr);
290 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
291 struct rte_eth_syn_filter *filter);
292 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
293 enum rte_filter_op filter_op,
295 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
296 struct ixgbe_5tuple_filter *filter);
297 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
298 struct ixgbe_5tuple_filter *filter);
299 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
300 enum rte_filter_op filter_op,
302 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
303 struct rte_eth_ntuple_filter *filter);
304 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
305 enum rte_filter_op filter_op,
307 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
308 struct rte_eth_ethertype_filter *filter);
309 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
310 enum rte_filter_type filter_type,
311 enum rte_filter_op filter_op,
313 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
315 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
316 struct ether_addr *mc_addr_set,
317 uint32_t nb_mc_addr);
318 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
319 struct rte_eth_dcb_info *dcb_info);
321 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
322 static int ixgbe_get_regs(struct rte_eth_dev *dev,
323 struct rte_dev_reg_info *regs);
324 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
325 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
326 struct rte_dev_eeprom_info *eeprom);
327 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
328 struct rte_dev_eeprom_info *eeprom);
330 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
331 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
332 struct rte_dev_reg_info *regs);
334 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
335 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
336 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
337 struct timespec *timestamp,
339 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
340 struct timespec *timestamp);
341 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
342 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
343 struct timespec *timestamp);
344 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
345 const struct timespec *timestamp);
346 static void ixgbevf_dev_interrupt_handler(void *param);
348 static int ixgbe_dev_l2_tunnel_eth_type_conf
349 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
350 static int ixgbe_dev_l2_tunnel_offload_set
351 (struct rte_eth_dev *dev,
352 struct rte_eth_l2_tunnel_conf *l2_tunnel,
355 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
356 enum rte_filter_op filter_op,
359 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
360 struct rte_eth_udp_tunnel *udp_tunnel);
361 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
362 struct rte_eth_udp_tunnel *udp_tunnel);
363 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
364 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
367 * Define VF Stats MACRO for Non "cleared on read" register
369 #define UPDATE_VF_STAT(reg, last, cur) \
371 uint32_t latest = IXGBE_READ_REG(hw, reg); \
372 cur += (latest - last) & UINT_MAX; \
376 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
378 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
379 u64 new_msb = IXGBE_READ_REG(hw, msb); \
380 u64 latest = ((new_msb << 32) | new_lsb); \
381 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
385 #define IXGBE_SET_HWSTRIP(h, q) do {\
386 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
387 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
388 (h)->bitmap[idx] |= 1 << bit;\
391 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
392 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
393 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
394 (h)->bitmap[idx] &= ~(1 << bit);\
397 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
398 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
399 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
400 (r) = (h)->bitmap[idx] >> bit & 1;\
403 int ixgbe_logtype_init;
404 int ixgbe_logtype_driver;
407 * The set of PCI devices this driver supports
409 static const struct rte_pci_id pci_id_ixgbe_map[] = {
410 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
411 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
412 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
413 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
414 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
415 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
416 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
417 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
418 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
419 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
420 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
421 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
422 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
423 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
424 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
425 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
426 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
427 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
428 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
429 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
430 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
458 #ifdef RTE_LIBRTE_IXGBE_BYPASS
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
461 { .vendor_id = 0, /* sentinel */ },
465 * The set of PCI devices this driver supports (for 82599 VF)
467 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
478 { .vendor_id = 0, /* sentinel */ },
481 static const struct rte_eth_desc_lim rx_desc_lim = {
482 .nb_max = IXGBE_MAX_RING_DESC,
483 .nb_min = IXGBE_MIN_RING_DESC,
484 .nb_align = IXGBE_RXD_ALIGN,
487 static const struct rte_eth_desc_lim tx_desc_lim = {
488 .nb_max = IXGBE_MAX_RING_DESC,
489 .nb_min = IXGBE_MIN_RING_DESC,
490 .nb_align = IXGBE_TXD_ALIGN,
491 .nb_seg_max = IXGBE_TX_MAX_SEG,
492 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
495 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
496 .dev_configure = ixgbe_dev_configure,
497 .dev_start = ixgbe_dev_start,
498 .dev_stop = ixgbe_dev_stop,
499 .dev_set_link_up = ixgbe_dev_set_link_up,
500 .dev_set_link_down = ixgbe_dev_set_link_down,
501 .dev_close = ixgbe_dev_close,
502 .dev_reset = ixgbe_dev_reset,
503 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
504 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
505 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
506 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
507 .link_update = ixgbe_dev_link_update,
508 .stats_get = ixgbe_dev_stats_get,
509 .xstats_get = ixgbe_dev_xstats_get,
510 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
511 .stats_reset = ixgbe_dev_stats_reset,
512 .xstats_reset = ixgbe_dev_xstats_reset,
513 .xstats_get_names = ixgbe_dev_xstats_get_names,
514 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
515 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
516 .fw_version_get = ixgbe_fw_version_get,
517 .dev_infos_get = ixgbe_dev_info_get,
518 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
519 .mtu_set = ixgbe_dev_mtu_set,
520 .vlan_filter_set = ixgbe_vlan_filter_set,
521 .vlan_tpid_set = ixgbe_vlan_tpid_set,
522 .vlan_offload_set = ixgbe_vlan_offload_set,
523 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
524 .rx_queue_start = ixgbe_dev_rx_queue_start,
525 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
526 .tx_queue_start = ixgbe_dev_tx_queue_start,
527 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
528 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
529 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
530 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
531 .rx_queue_release = ixgbe_dev_rx_queue_release,
532 .rx_queue_count = ixgbe_dev_rx_queue_count,
533 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
534 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
535 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
536 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
537 .tx_queue_release = ixgbe_dev_tx_queue_release,
538 .dev_led_on = ixgbe_dev_led_on,
539 .dev_led_off = ixgbe_dev_led_off,
540 .flow_ctrl_get = ixgbe_flow_ctrl_get,
541 .flow_ctrl_set = ixgbe_flow_ctrl_set,
542 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
543 .mac_addr_add = ixgbe_add_rar,
544 .mac_addr_remove = ixgbe_remove_rar,
545 .mac_addr_set = ixgbe_set_default_mac_addr,
546 .uc_hash_table_set = ixgbe_uc_hash_table_set,
547 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
548 .mirror_rule_set = ixgbe_mirror_rule_set,
549 .mirror_rule_reset = ixgbe_mirror_rule_reset,
550 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
551 .reta_update = ixgbe_dev_rss_reta_update,
552 .reta_query = ixgbe_dev_rss_reta_query,
553 .rss_hash_update = ixgbe_dev_rss_hash_update,
554 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
555 .filter_ctrl = ixgbe_dev_filter_ctrl,
556 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
557 .rxq_info_get = ixgbe_rxq_info_get,
558 .txq_info_get = ixgbe_txq_info_get,
559 .timesync_enable = ixgbe_timesync_enable,
560 .timesync_disable = ixgbe_timesync_disable,
561 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
562 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
563 .get_reg = ixgbe_get_regs,
564 .get_eeprom_length = ixgbe_get_eeprom_length,
565 .get_eeprom = ixgbe_get_eeprom,
566 .set_eeprom = ixgbe_set_eeprom,
567 .get_dcb_info = ixgbe_dev_get_dcb_info,
568 .timesync_adjust_time = ixgbe_timesync_adjust_time,
569 .timesync_read_time = ixgbe_timesync_read_time,
570 .timesync_write_time = ixgbe_timesync_write_time,
571 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
572 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
573 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
574 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
575 .tm_ops_get = ixgbe_tm_ops_get,
579 * dev_ops for virtual function, bare necessities for basic vf
580 * operation have been implemented
582 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
583 .dev_configure = ixgbevf_dev_configure,
584 .dev_start = ixgbevf_dev_start,
585 .dev_stop = ixgbevf_dev_stop,
586 .link_update = ixgbevf_dev_link_update,
587 .stats_get = ixgbevf_dev_stats_get,
588 .xstats_get = ixgbevf_dev_xstats_get,
589 .stats_reset = ixgbevf_dev_stats_reset,
590 .xstats_reset = ixgbevf_dev_stats_reset,
591 .xstats_get_names = ixgbevf_dev_xstats_get_names,
592 .dev_close = ixgbevf_dev_close,
593 .dev_reset = ixgbevf_dev_reset,
594 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
595 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
596 .dev_infos_get = ixgbevf_dev_info_get,
597 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
598 .mtu_set = ixgbevf_dev_set_mtu,
599 .vlan_filter_set = ixgbevf_vlan_filter_set,
600 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
601 .vlan_offload_set = ixgbevf_vlan_offload_set,
602 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
603 .rx_queue_release = ixgbe_dev_rx_queue_release,
604 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
605 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
606 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
607 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
608 .tx_queue_release = ixgbe_dev_tx_queue_release,
609 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
610 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
611 .mac_addr_add = ixgbevf_add_mac_addr,
612 .mac_addr_remove = ixgbevf_remove_mac_addr,
613 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
614 .rxq_info_get = ixgbe_rxq_info_get,
615 .txq_info_get = ixgbe_txq_info_get,
616 .mac_addr_set = ixgbevf_set_default_mac_addr,
617 .get_reg = ixgbevf_get_regs,
618 .reta_update = ixgbe_dev_rss_reta_update,
619 .reta_query = ixgbe_dev_rss_reta_query,
620 .rss_hash_update = ixgbe_dev_rss_hash_update,
621 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
624 /* store statistics names and its offset in stats structure */
625 struct rte_ixgbe_xstats_name_off {
626 char name[RTE_ETH_XSTATS_NAME_SIZE];
630 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
631 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
632 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
633 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
634 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
635 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
636 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
637 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
638 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
639 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
640 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
641 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
642 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
643 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
644 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
645 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
647 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
649 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
650 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
651 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
652 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
653 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
654 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
655 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
656 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
657 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
658 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
659 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
660 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
661 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
662 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
663 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
664 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
665 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
667 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
669 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
670 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
671 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
672 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
674 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
676 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
678 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
680 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
682 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
684 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
687 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
688 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
689 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
691 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
692 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
693 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
694 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
695 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
697 {"rx_fcoe_no_direct_data_placement_ext_buff",
698 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
700 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
702 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
704 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
706 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
708 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
711 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
712 sizeof(rte_ixgbe_stats_strings[0]))
714 /* MACsec statistics */
715 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
716 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
718 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
719 out_pkts_encrypted)},
720 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
721 out_pkts_protected)},
722 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
723 out_octets_encrypted)},
724 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
725 out_octets_protected)},
726 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
728 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
730 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
732 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
733 in_pkts_unknownsci)},
734 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
735 in_octets_decrypted)},
736 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
737 in_octets_validated)},
738 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
740 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
742 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
744 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
746 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
748 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
750 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
752 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
753 in_pkts_notusingsa)},
756 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
757 sizeof(rte_ixgbe_macsec_strings[0]))
759 /* Per-queue statistics */
760 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
761 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
762 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
763 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
764 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
767 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
768 sizeof(rte_ixgbe_rxq_strings[0]))
769 #define IXGBE_NB_RXQ_PRIO_VALUES 8
771 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
772 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
773 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
774 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
778 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
779 sizeof(rte_ixgbe_txq_strings[0]))
780 #define IXGBE_NB_TXQ_PRIO_VALUES 8
782 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
783 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
786 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
787 sizeof(rte_ixgbevf_stats_strings[0]))
790 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
793 ixgbe_is_sfp(struct ixgbe_hw *hw)
795 switch (hw->phy.type) {
796 case ixgbe_phy_sfp_avago:
797 case ixgbe_phy_sfp_ftl:
798 case ixgbe_phy_sfp_intel:
799 case ixgbe_phy_sfp_unknown:
800 case ixgbe_phy_sfp_passive_tyco:
801 case ixgbe_phy_sfp_passive_unknown:
808 static inline int32_t
809 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
814 status = ixgbe_reset_hw(hw);
816 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
817 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
818 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
819 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
820 IXGBE_WRITE_FLUSH(hw);
822 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
823 status = IXGBE_SUCCESS;
828 ixgbe_enable_intr(struct rte_eth_dev *dev)
830 struct ixgbe_interrupt *intr =
831 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
832 struct ixgbe_hw *hw =
833 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
835 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
836 IXGBE_WRITE_FLUSH(hw);
840 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
843 ixgbe_disable_intr(struct ixgbe_hw *hw)
845 PMD_INIT_FUNC_TRACE();
847 if (hw->mac.type == ixgbe_mac_82598EB) {
848 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
850 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
851 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
852 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
854 IXGBE_WRITE_FLUSH(hw);
858 * This function resets queue statistics mapping registers.
859 * From Niantic datasheet, Initialization of Statistics section:
860 * "...if software requires the queue counters, the RQSMR and TQSM registers
861 * must be re-programmed following a device reset.
864 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
868 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
869 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
870 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
876 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
881 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
882 #define NB_QMAP_FIELDS_PER_QSM_REG 4
883 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
886 struct ixgbe_stat_mapping_registers *stat_mappings =
887 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
888 uint32_t qsmr_mask = 0;
889 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
893 if ((hw->mac.type != ixgbe_mac_82599EB) &&
894 (hw->mac.type != ixgbe_mac_X540) &&
895 (hw->mac.type != ixgbe_mac_X550) &&
896 (hw->mac.type != ixgbe_mac_X550EM_x) &&
897 (hw->mac.type != ixgbe_mac_X550EM_a))
900 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
901 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
904 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
905 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
906 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
909 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
911 /* Now clear any previous stat_idx set */
912 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
914 stat_mappings->tqsm[n] &= ~clearing_mask;
916 stat_mappings->rqsmr[n] &= ~clearing_mask;
918 q_map = (uint32_t)stat_idx;
919 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
920 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
922 stat_mappings->tqsm[n] |= qsmr_mask;
924 stat_mappings->rqsmr[n] |= qsmr_mask;
926 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
927 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
929 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
930 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
932 /* Now write the mapping in the appropriate register */
934 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
935 stat_mappings->rqsmr[n], n);
936 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
938 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
939 stat_mappings->tqsm[n], n);
940 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
946 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
948 struct ixgbe_stat_mapping_registers *stat_mappings =
949 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
950 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
953 /* write whatever was in stat mapping table to the NIC */
954 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
956 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
959 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
964 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
967 struct ixgbe_dcb_tc_config *tc;
968 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
970 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
971 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
972 for (i = 0; i < dcb_max_tc; i++) {
973 tc = &dcb_config->tc_config[i];
974 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
975 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
976 (uint8_t)(100/dcb_max_tc + (i & 1));
977 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
978 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
979 (uint8_t)(100/dcb_max_tc + (i & 1));
980 tc->pfc = ixgbe_dcb_pfc_disabled;
983 /* Initialize default user to priority mapping, UPx->TC0 */
984 tc = &dcb_config->tc_config[0];
985 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
986 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
987 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
988 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
989 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
991 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
992 dcb_config->pfc_mode_enable = false;
993 dcb_config->vt_mode = true;
994 dcb_config->round_robin_enable = false;
995 /* support all DCB capabilities in 82599 */
996 dcb_config->support.capabilities = 0xFF;
998 /*we only support 4 Tcs for X540, X550 */
999 if (hw->mac.type == ixgbe_mac_X540 ||
1000 hw->mac.type == ixgbe_mac_X550 ||
1001 hw->mac.type == ixgbe_mac_X550EM_x ||
1002 hw->mac.type == ixgbe_mac_X550EM_a) {
1003 dcb_config->num_tcs.pg_tcs = 4;
1004 dcb_config->num_tcs.pfc_tcs = 4;
1009 * Ensure that all locks are released before first NVM or PHY access
1012 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1017 * Phy lock should not fail in this early stage. If this is the case,
1018 * it is due to an improper exit of the application.
1019 * So force the release of the faulty lock. Release of common lock
1020 * is done automatically by swfw_sync function.
1022 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1023 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1024 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1026 ixgbe_release_swfw_semaphore(hw, mask);
1029 * These ones are more tricky since they are common to all ports; but
1030 * swfw_sync retries last long enough (1s) to be almost sure that if
1031 * lock can not be taken it is due to an improper lock of the
1034 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1035 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1036 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1038 ixgbe_release_swfw_semaphore(hw, mask);
1042 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1043 * It returns 0 on success.
1046 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1048 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1049 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1050 struct ixgbe_hw *hw =
1051 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1052 struct ixgbe_vfta *shadow_vfta =
1053 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1054 struct ixgbe_hwstrip *hwstrip =
1055 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1056 struct ixgbe_dcb_config *dcb_config =
1057 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1058 struct ixgbe_filter_info *filter_info =
1059 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1060 struct ixgbe_bw_conf *bw_conf =
1061 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1066 PMD_INIT_FUNC_TRACE();
1068 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1069 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1070 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1071 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1074 * For secondary processes, we don't initialise any further as primary
1075 * has already done this work. Only check we don't need a different
1076 * RX and TX function.
1078 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1079 struct ixgbe_tx_queue *txq;
1080 /* TX queue function in primary, set by last queue initialized
1081 * Tx queue may not initialized by primary process
1083 if (eth_dev->data->tx_queues) {
1084 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1085 ixgbe_set_tx_function(eth_dev, txq);
1087 /* Use default TX function if we get here */
1088 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1089 "Using default TX function.");
1092 ixgbe_set_rx_function(eth_dev);
1097 rte_eth_copy_pci_info(eth_dev, pci_dev);
1099 /* Vendor and Device ID need to be set before init of shared code */
1100 hw->device_id = pci_dev->id.device_id;
1101 hw->vendor_id = pci_dev->id.vendor_id;
1102 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1103 hw->allow_unsupported_sfp = 1;
1105 /* Initialize the shared code (base driver) */
1106 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1107 diag = ixgbe_bypass_init_shared_code(hw);
1109 diag = ixgbe_init_shared_code(hw);
1110 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1112 if (diag != IXGBE_SUCCESS) {
1113 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1117 /* pick up the PCI bus settings for reporting later */
1118 ixgbe_get_bus_info(hw);
1120 /* Unlock any pending hardware semaphore */
1121 ixgbe_swfw_lock_reset(hw);
1123 #ifdef RTE_LIBRTE_SECURITY
1124 /* Initialize security_ctx only for primary process*/
1125 if (ixgbe_ipsec_ctx_create(eth_dev))
1129 /* Initialize DCB configuration*/
1130 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1131 ixgbe_dcb_init(hw, dcb_config);
1132 /* Get Hardware Flow Control setting */
1133 hw->fc.requested_mode = ixgbe_fc_full;
1134 hw->fc.current_mode = ixgbe_fc_full;
1135 hw->fc.pause_time = IXGBE_FC_PAUSE;
1136 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1137 hw->fc.low_water[i] = IXGBE_FC_LO;
1138 hw->fc.high_water[i] = IXGBE_FC_HI;
1140 hw->fc.send_xon = 1;
1142 /* Make sure we have a good EEPROM before we read from it */
1143 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1144 if (diag != IXGBE_SUCCESS) {
1145 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1149 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1150 diag = ixgbe_bypass_init_hw(hw);
1152 diag = ixgbe_init_hw(hw);
1153 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1156 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1157 * is called too soon after the kernel driver unbinding/binding occurs.
1158 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1159 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1160 * also called. See ixgbe_identify_phy_82599(). The reason for the
1161 * failure is not known, and only occuts when virtualisation features
1162 * are disabled in the bios. A delay of 100ms was found to be enough by
1163 * trial-and-error, and is doubled to be safe.
1165 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1167 diag = ixgbe_init_hw(hw);
1170 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1171 diag = IXGBE_SUCCESS;
1173 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1174 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1175 "LOM. Please be aware there may be issues associated "
1176 "with your hardware.");
1177 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1178 "please contact your Intel or hardware representative "
1179 "who provided you with this hardware.");
1180 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1181 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1183 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1187 /* Reset the hw statistics */
1188 ixgbe_dev_stats_reset(eth_dev);
1190 /* disable interrupt */
1191 ixgbe_disable_intr(hw);
1193 /* reset mappings for queue statistics hw counters*/
1194 ixgbe_reset_qstat_mappings(hw);
1196 /* Allocate memory for storing MAC addresses */
1197 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1198 hw->mac.num_rar_entries, 0);
1199 if (eth_dev->data->mac_addrs == NULL) {
1201 "Failed to allocate %u bytes needed to store "
1203 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1206 /* Copy the permanent MAC address */
1207 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1208 ð_dev->data->mac_addrs[0]);
1210 /* Allocate memory for storing hash filter MAC addresses */
1211 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1212 IXGBE_VMDQ_NUM_UC_MAC, 0);
1213 if (eth_dev->data->hash_mac_addrs == NULL) {
1215 "Failed to allocate %d bytes needed to store MAC addresses",
1216 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1220 /* initialize the vfta */
1221 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1223 /* initialize the hw strip bitmap*/
1224 memset(hwstrip, 0, sizeof(*hwstrip));
1226 /* initialize PF if max_vfs not zero */
1227 ixgbe_pf_host_init(eth_dev);
1229 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1230 /* let hardware know driver is loaded */
1231 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1232 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1233 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1234 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1235 IXGBE_WRITE_FLUSH(hw);
1237 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1238 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1239 (int) hw->mac.type, (int) hw->phy.type,
1240 (int) hw->phy.sfp_type);
1242 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1243 (int) hw->mac.type, (int) hw->phy.type);
1245 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1246 eth_dev->data->port_id, pci_dev->id.vendor_id,
1247 pci_dev->id.device_id);
1249 rte_intr_callback_register(intr_handle,
1250 ixgbe_dev_interrupt_handler, eth_dev);
1252 /* enable uio/vfio intr/eventfd mapping */
1253 rte_intr_enable(intr_handle);
1255 /* enable support intr */
1256 ixgbe_enable_intr(eth_dev);
1258 /* initialize filter info */
1259 memset(filter_info, 0,
1260 sizeof(struct ixgbe_filter_info));
1262 /* initialize 5tuple filter list */
1263 TAILQ_INIT(&filter_info->fivetuple_list);
1265 /* initialize flow director filter list & hash */
1266 ixgbe_fdir_filter_init(eth_dev);
1268 /* initialize l2 tunnel filter list & hash */
1269 ixgbe_l2_tn_filter_init(eth_dev);
1271 /* initialize flow filter lists */
1272 ixgbe_filterlist_init();
1274 /* initialize bandwidth configuration info */
1275 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1277 /* initialize Traffic Manager configuration */
1278 ixgbe_tm_conf_init(eth_dev);
1284 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1286 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1287 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1288 struct ixgbe_hw *hw;
1292 PMD_INIT_FUNC_TRACE();
1294 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1297 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1299 if (hw->adapter_stopped == 0)
1300 ixgbe_dev_close(eth_dev);
1302 eth_dev->dev_ops = NULL;
1303 eth_dev->rx_pkt_burst = NULL;
1304 eth_dev->tx_pkt_burst = NULL;
1306 /* Unlock any pending hardware semaphore */
1307 ixgbe_swfw_lock_reset(hw);
1309 /* disable uio intr before callback unregister */
1310 rte_intr_disable(intr_handle);
1313 ret = rte_intr_callback_unregister(intr_handle,
1314 ixgbe_dev_interrupt_handler, eth_dev);
1317 } else if (ret != -EAGAIN) {
1319 "intr callback unregister failed: %d",
1324 } while (retries++ < (10 + IXGBE_LINK_UP_TIME));
1326 /* uninitialize PF if max_vfs not zero */
1327 ixgbe_pf_host_uninit(eth_dev);
1329 rte_free(eth_dev->data->mac_addrs);
1330 eth_dev->data->mac_addrs = NULL;
1332 rte_free(eth_dev->data->hash_mac_addrs);
1333 eth_dev->data->hash_mac_addrs = NULL;
1335 /* remove all the fdir filters & hash */
1336 ixgbe_fdir_filter_uninit(eth_dev);
1338 /* remove all the L2 tunnel filters & hash */
1339 ixgbe_l2_tn_filter_uninit(eth_dev);
1341 /* Remove all ntuple filters of the device */
1342 ixgbe_ntuple_filter_uninit(eth_dev);
1344 /* clear all the filters list */
1345 ixgbe_filterlist_flush();
1347 /* Remove all Traffic Manager configuration */
1348 ixgbe_tm_conf_uninit(eth_dev);
1350 #ifdef RTE_LIBRTE_SECURITY
1351 rte_free(eth_dev->security_ctx);
1357 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1359 struct ixgbe_filter_info *filter_info =
1360 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1361 struct ixgbe_5tuple_filter *p_5tuple;
1363 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1364 TAILQ_REMOVE(&filter_info->fivetuple_list,
1369 memset(filter_info->fivetuple_mask, 0,
1370 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1375 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1377 struct ixgbe_hw_fdir_info *fdir_info =
1378 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1379 struct ixgbe_fdir_filter *fdir_filter;
1381 if (fdir_info->hash_map)
1382 rte_free(fdir_info->hash_map);
1383 if (fdir_info->hash_handle)
1384 rte_hash_free(fdir_info->hash_handle);
1386 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1387 TAILQ_REMOVE(&fdir_info->fdir_list,
1390 rte_free(fdir_filter);
1396 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1398 struct ixgbe_l2_tn_info *l2_tn_info =
1399 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1400 struct ixgbe_l2_tn_filter *l2_tn_filter;
1402 if (l2_tn_info->hash_map)
1403 rte_free(l2_tn_info->hash_map);
1404 if (l2_tn_info->hash_handle)
1405 rte_hash_free(l2_tn_info->hash_handle);
1407 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1408 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1411 rte_free(l2_tn_filter);
1417 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1419 struct ixgbe_hw_fdir_info *fdir_info =
1420 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1421 char fdir_hash_name[RTE_HASH_NAMESIZE];
1422 struct rte_hash_parameters fdir_hash_params = {
1423 .name = fdir_hash_name,
1424 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1425 .key_len = sizeof(union ixgbe_atr_input),
1426 .hash_func = rte_hash_crc,
1427 .hash_func_init_val = 0,
1428 .socket_id = rte_socket_id(),
1431 TAILQ_INIT(&fdir_info->fdir_list);
1432 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1433 "fdir_%s", eth_dev->device->name);
1434 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1435 if (!fdir_info->hash_handle) {
1436 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1439 fdir_info->hash_map = rte_zmalloc("ixgbe",
1440 sizeof(struct ixgbe_fdir_filter *) *
1441 IXGBE_MAX_FDIR_FILTER_NUM,
1443 if (!fdir_info->hash_map) {
1445 "Failed to allocate memory for fdir hash map!");
1448 fdir_info->mask_added = FALSE;
1453 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1455 struct ixgbe_l2_tn_info *l2_tn_info =
1456 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1457 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1458 struct rte_hash_parameters l2_tn_hash_params = {
1459 .name = l2_tn_hash_name,
1460 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1461 .key_len = sizeof(struct ixgbe_l2_tn_key),
1462 .hash_func = rte_hash_crc,
1463 .hash_func_init_val = 0,
1464 .socket_id = rte_socket_id(),
1467 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1468 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1469 "l2_tn_%s", eth_dev->device->name);
1470 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1471 if (!l2_tn_info->hash_handle) {
1472 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1475 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1476 sizeof(struct ixgbe_l2_tn_filter *) *
1477 IXGBE_MAX_L2_TN_FILTER_NUM,
1479 if (!l2_tn_info->hash_map) {
1481 "Failed to allocate memory for L2 TN hash map!");
1484 l2_tn_info->e_tag_en = FALSE;
1485 l2_tn_info->e_tag_fwd_en = FALSE;
1486 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1491 * Negotiate mailbox API version with the PF.
1492 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1493 * Then we try to negotiate starting with the most recent one.
1494 * If all negotiation attempts fail, then we will proceed with
1495 * the default one (ixgbe_mbox_api_10).
1498 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1502 /* start with highest supported, proceed down */
1503 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1510 i != RTE_DIM(sup_ver) &&
1511 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1517 generate_random_mac_addr(struct ether_addr *mac_addr)
1521 /* Set Organizationally Unique Identifier (OUI) prefix. */
1522 mac_addr->addr_bytes[0] = 0x00;
1523 mac_addr->addr_bytes[1] = 0x09;
1524 mac_addr->addr_bytes[2] = 0xC0;
1525 /* Force indication of locally assigned MAC address. */
1526 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1527 /* Generate the last 3 bytes of the MAC address with a random number. */
1528 random = rte_rand();
1529 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1533 * Virtual Function device init
1536 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1540 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1541 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1542 struct ixgbe_hw *hw =
1543 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1544 struct ixgbe_vfta *shadow_vfta =
1545 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1546 struct ixgbe_hwstrip *hwstrip =
1547 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1548 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1550 PMD_INIT_FUNC_TRACE();
1552 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1553 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1554 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1556 /* for secondary processes, we don't initialise any further as primary
1557 * has already done this work. Only check we don't need a different
1560 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1561 struct ixgbe_tx_queue *txq;
1562 /* TX queue function in primary, set by last queue initialized
1563 * Tx queue may not initialized by primary process
1565 if (eth_dev->data->tx_queues) {
1566 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1567 ixgbe_set_tx_function(eth_dev, txq);
1569 /* Use default TX function if we get here */
1570 PMD_INIT_LOG(NOTICE,
1571 "No TX queues configured yet. Using default TX function.");
1574 ixgbe_set_rx_function(eth_dev);
1579 rte_eth_copy_pci_info(eth_dev, pci_dev);
1581 hw->device_id = pci_dev->id.device_id;
1582 hw->vendor_id = pci_dev->id.vendor_id;
1583 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1585 /* initialize the vfta */
1586 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1588 /* initialize the hw strip bitmap*/
1589 memset(hwstrip, 0, sizeof(*hwstrip));
1591 /* Initialize the shared code (base driver) */
1592 diag = ixgbe_init_shared_code(hw);
1593 if (diag != IXGBE_SUCCESS) {
1594 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1598 /* init_mailbox_params */
1599 hw->mbx.ops.init_params(hw);
1601 /* Reset the hw statistics */
1602 ixgbevf_dev_stats_reset(eth_dev);
1604 /* Disable the interrupts for VF */
1605 ixgbevf_intr_disable(hw);
1607 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1608 diag = hw->mac.ops.reset_hw(hw);
1611 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1612 * the underlying PF driver has not assigned a MAC address to the VF.
1613 * In this case, assign a random MAC address.
1615 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1616 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1620 /* negotiate mailbox API version to use with the PF. */
1621 ixgbevf_negotiate_api(hw);
1623 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1624 ixgbevf_get_queues(hw, &tcs, &tc);
1626 /* Allocate memory for storing MAC addresses */
1627 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1628 hw->mac.num_rar_entries, 0);
1629 if (eth_dev->data->mac_addrs == NULL) {
1631 "Failed to allocate %u bytes needed to store "
1633 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1637 /* Generate a random MAC address, if none was assigned by PF. */
1638 if (is_zero_ether_addr(perm_addr)) {
1639 generate_random_mac_addr(perm_addr);
1640 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1642 rte_free(eth_dev->data->mac_addrs);
1643 eth_dev->data->mac_addrs = NULL;
1646 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1647 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1648 "%02x:%02x:%02x:%02x:%02x:%02x",
1649 perm_addr->addr_bytes[0],
1650 perm_addr->addr_bytes[1],
1651 perm_addr->addr_bytes[2],
1652 perm_addr->addr_bytes[3],
1653 perm_addr->addr_bytes[4],
1654 perm_addr->addr_bytes[5]);
1657 /* Copy the permanent MAC address */
1658 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1660 /* reset the hardware with the new settings */
1661 diag = hw->mac.ops.start_hw(hw);
1667 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671 rte_intr_callback_register(intr_handle,
1672 ixgbevf_dev_interrupt_handler, eth_dev);
1673 rte_intr_enable(intr_handle);
1674 ixgbevf_intr_enable(hw);
1676 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1677 eth_dev->data->port_id, pci_dev->id.vendor_id,
1678 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1683 /* Virtual Function device uninit */
1686 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1688 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690 struct ixgbe_hw *hw;
1692 PMD_INIT_FUNC_TRACE();
1694 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1697 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1699 if (hw->adapter_stopped == 0)
1700 ixgbevf_dev_close(eth_dev);
1702 eth_dev->dev_ops = NULL;
1703 eth_dev->rx_pkt_burst = NULL;
1704 eth_dev->tx_pkt_burst = NULL;
1706 /* Disable the interrupts for VF */
1707 ixgbevf_intr_disable(hw);
1709 rte_free(eth_dev->data->mac_addrs);
1710 eth_dev->data->mac_addrs = NULL;
1712 rte_intr_disable(intr_handle);
1713 rte_intr_callback_unregister(intr_handle,
1714 ixgbevf_dev_interrupt_handler, eth_dev);
1719 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1720 struct rte_pci_device *pci_dev)
1722 return rte_eth_dev_pci_generic_probe(pci_dev,
1723 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1726 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1728 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1731 static struct rte_pci_driver rte_ixgbe_pmd = {
1732 .id_table = pci_id_ixgbe_map,
1733 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
1734 RTE_PCI_DRV_IOVA_AS_VA,
1735 .probe = eth_ixgbe_pci_probe,
1736 .remove = eth_ixgbe_pci_remove,
1739 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1740 struct rte_pci_device *pci_dev)
1742 return rte_eth_dev_pci_generic_probe(pci_dev,
1743 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1746 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1748 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1752 * virtual function driver struct
1754 static struct rte_pci_driver rte_ixgbevf_pmd = {
1755 .id_table = pci_id_ixgbevf_map,
1756 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1757 .probe = eth_ixgbevf_pci_probe,
1758 .remove = eth_ixgbevf_pci_remove,
1762 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1764 struct ixgbe_hw *hw =
1765 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766 struct ixgbe_vfta *shadow_vfta =
1767 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1772 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1773 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1774 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1779 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1781 /* update local VFTA copy */
1782 shadow_vfta->vfta[vid_idx] = vfta;
1788 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1791 ixgbe_vlan_hw_strip_enable(dev, queue);
1793 ixgbe_vlan_hw_strip_disable(dev, queue);
1797 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1798 enum rte_vlan_type vlan_type,
1801 struct ixgbe_hw *hw =
1802 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1807 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1808 qinq &= IXGBE_DMATXCTL_GDV;
1810 switch (vlan_type) {
1811 case ETH_VLAN_TYPE_INNER:
1813 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1814 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1815 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1816 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1817 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1818 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1819 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1822 PMD_DRV_LOG(ERR, "Inner type is not supported"
1826 case ETH_VLAN_TYPE_OUTER:
1828 /* Only the high 16-bits is valid */
1829 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1830 IXGBE_EXVET_VET_EXT_SHIFT);
1832 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1833 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1834 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1835 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1836 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1837 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1838 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1844 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1852 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1854 struct ixgbe_hw *hw =
1855 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1858 PMD_INIT_FUNC_TRACE();
1860 /* Filter Table Disable */
1861 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1862 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1864 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1868 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1870 struct ixgbe_hw *hw =
1871 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1872 struct ixgbe_vfta *shadow_vfta =
1873 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1877 PMD_INIT_FUNC_TRACE();
1879 /* Filter Table Enable */
1880 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1881 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1882 vlnctrl |= IXGBE_VLNCTRL_VFE;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1886 /* write whatever is in local vfta copy */
1887 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1888 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1892 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1894 struct ixgbe_hwstrip *hwstrip =
1895 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1896 struct ixgbe_rx_queue *rxq;
1898 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1902 IXGBE_SET_HWSTRIP(hwstrip, queue);
1904 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1906 if (queue >= dev->data->nb_rx_queues)
1909 rxq = dev->data->rx_queues[queue];
1912 rxq->vlan_flags = PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1914 rxq->vlan_flags = PKT_RX_VLAN;
1918 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1924 PMD_INIT_FUNC_TRACE();
1926 if (hw->mac.type == ixgbe_mac_82598EB) {
1927 /* No queue level support */
1928 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1932 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1933 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1934 ctrl &= ~IXGBE_RXDCTL_VME;
1935 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1937 /* record those setting for HW strip per queue */
1938 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1942 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1944 struct ixgbe_hw *hw =
1945 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1948 PMD_INIT_FUNC_TRACE();
1950 if (hw->mac.type == ixgbe_mac_82598EB) {
1951 /* No queue level supported */
1952 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1956 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1957 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1958 ctrl |= IXGBE_RXDCTL_VME;
1959 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1961 /* record those setting for HW strip per queue */
1962 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1966 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1968 struct ixgbe_hw *hw =
1969 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1972 PMD_INIT_FUNC_TRACE();
1974 /* DMATXCTRL: Geric Double VLAN Disable */
1975 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1976 ctrl &= ~IXGBE_DMATXCTL_GDV;
1977 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
1979 /* CTRL_EXT: Global Double VLAN Disable */
1980 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1981 ctrl &= ~IXGBE_EXTENDED_VLAN;
1982 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
1987 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1989 struct ixgbe_hw *hw =
1990 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1993 PMD_INIT_FUNC_TRACE();
1995 /* DMATXCTRL: Geric Double VLAN Enable */
1996 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1997 ctrl |= IXGBE_DMATXCTL_GDV;
1998 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2000 /* CTRL_EXT: Global Double VLAN Enable */
2001 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2002 ctrl |= IXGBE_EXTENDED_VLAN;
2003 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2005 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2006 if (hw->mac.type == ixgbe_mac_X550 ||
2007 hw->mac.type == ixgbe_mac_X550EM_x ||
2008 hw->mac.type == ixgbe_mac_X550EM_a) {
2009 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2010 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2011 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2015 * VET EXT field in the EXVET register = 0x8100 by default
2016 * So no need to change. Same to VT field of DMATXCTL register
2021 ixgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
2023 struct ixgbe_hw *hw =
2024 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2028 struct ixgbe_rx_queue *rxq;
2031 PMD_INIT_FUNC_TRACE();
2033 if (hw->mac.type == ixgbe_mac_82598EB) {
2034 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2035 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2036 ctrl |= IXGBE_VLNCTRL_VME;
2037 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2039 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2040 ctrl &= ~IXGBE_VLNCTRL_VME;
2041 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2045 * Other 10G NIC, the VLAN strip can be setup
2046 * per queue in RXDCTL
2048 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2049 rxq = dev->data->rx_queues[i];
2050 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2051 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
2052 ctrl |= IXGBE_RXDCTL_VME;
2055 ctrl &= ~IXGBE_RXDCTL_VME;
2058 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2060 /* record those setting for HW strip per queue */
2061 ixgbe_vlan_hw_strip_bitmap_set(dev, i, on);
2067 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2069 struct rte_eth_rxmode *rxmode;
2070 rxmode = &dev->data->dev_conf.rxmode;
2072 if (mask & ETH_VLAN_STRIP_MASK) {
2073 ixgbe_vlan_hw_strip_config(dev);
2076 if (mask & ETH_VLAN_FILTER_MASK) {
2077 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2078 ixgbe_vlan_hw_filter_enable(dev);
2080 ixgbe_vlan_hw_filter_disable(dev);
2083 if (mask & ETH_VLAN_EXTEND_MASK) {
2084 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2085 ixgbe_vlan_hw_extend_enable(dev);
2087 ixgbe_vlan_hw_extend_disable(dev);
2094 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2096 struct ixgbe_hw *hw =
2097 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2098 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2099 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2101 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2102 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2106 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2108 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2113 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2116 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2122 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
2123 IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2124 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
2125 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2130 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2132 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2133 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2134 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2135 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2137 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2138 /* check multi-queue mode */
2139 switch (dev_conf->rxmode.mq_mode) {
2140 case ETH_MQ_RX_VMDQ_DCB:
2141 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2143 case ETH_MQ_RX_VMDQ_DCB_RSS:
2144 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2145 PMD_INIT_LOG(ERR, "SRIOV active,"
2146 " unsupported mq_mode rx %d.",
2147 dev_conf->rxmode.mq_mode);
2150 case ETH_MQ_RX_VMDQ_RSS:
2151 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2152 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2153 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2154 PMD_INIT_LOG(ERR, "SRIOV is active,"
2155 " invalid queue number"
2156 " for VMDQ RSS, allowed"
2157 " value are 1, 2 or 4.");
2161 case ETH_MQ_RX_VMDQ_ONLY:
2162 case ETH_MQ_RX_NONE:
2163 /* if nothing mq mode configure, use default scheme */
2164 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2166 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2167 /* SRIOV only works in VMDq enable mode */
2168 PMD_INIT_LOG(ERR, "SRIOV is active,"
2169 " wrong mq_mode rx %d.",
2170 dev_conf->rxmode.mq_mode);
2174 switch (dev_conf->txmode.mq_mode) {
2175 case ETH_MQ_TX_VMDQ_DCB:
2176 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2177 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2179 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2180 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2184 /* check valid queue number */
2185 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2186 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2187 PMD_INIT_LOG(ERR, "SRIOV is active,"
2188 " nb_rx_q=%d nb_tx_q=%d queue number"
2189 " must be less than or equal to %d.",
2191 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2195 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2196 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2200 /* check configuration for vmdb+dcb mode */
2201 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2202 const struct rte_eth_vmdq_dcb_conf *conf;
2204 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2205 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2206 IXGBE_VMDQ_DCB_NB_QUEUES);
2209 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2210 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2211 conf->nb_queue_pools == ETH_32_POOLS)) {
2212 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2213 " nb_queue_pools must be %d or %d.",
2214 ETH_16_POOLS, ETH_32_POOLS);
2218 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2219 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2221 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2222 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2223 IXGBE_VMDQ_DCB_NB_QUEUES);
2226 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2227 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2228 conf->nb_queue_pools == ETH_32_POOLS)) {
2229 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2230 " nb_queue_pools != %d and"
2231 " nb_queue_pools != %d.",
2232 ETH_16_POOLS, ETH_32_POOLS);
2237 /* For DCB mode check our configuration before we go further */
2238 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2239 const struct rte_eth_dcb_rx_conf *conf;
2241 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2242 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2243 IXGBE_DCB_NB_QUEUES);
2246 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2247 if (!(conf->nb_tcs == ETH_4_TCS ||
2248 conf->nb_tcs == ETH_8_TCS)) {
2249 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2250 " and nb_tcs != %d.",
2251 ETH_4_TCS, ETH_8_TCS);
2256 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2257 const struct rte_eth_dcb_tx_conf *conf;
2259 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2260 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2261 IXGBE_DCB_NB_QUEUES);
2264 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2265 if (!(conf->nb_tcs == ETH_4_TCS ||
2266 conf->nb_tcs == ETH_8_TCS)) {
2267 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2268 " and nb_tcs != %d.",
2269 ETH_4_TCS, ETH_8_TCS);
2275 * When DCB/VT is off, maximum number of queues changes,
2276 * except for 82598EB, which remains constant.
2278 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2279 hw->mac.type != ixgbe_mac_82598EB) {
2280 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2282 "Neither VT nor DCB are enabled, "
2284 IXGBE_NONE_MODE_TX_NB_QUEUES);
2293 ixgbe_dev_configure(struct rte_eth_dev *dev)
2295 struct ixgbe_interrupt *intr =
2296 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2297 struct ixgbe_adapter *adapter =
2298 (struct ixgbe_adapter *)dev->data->dev_private;
2299 struct rte_eth_dev_info dev_info;
2300 uint64_t rx_offloads;
2303 PMD_INIT_FUNC_TRACE();
2304 /* multipe queue mode checking */
2305 ret = ixgbe_check_mq_mode(dev);
2307 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2312 ixgbe_dev_info_get(dev, &dev_info);
2313 rx_offloads = dev->data->dev_conf.rxmode.offloads;
2314 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
2315 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
2316 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
2317 rx_offloads, dev_info.rx_offload_capa);
2321 /* set flag to update link status after init */
2322 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2325 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2326 * allocation or vector Rx preconditions we will reset it.
2328 adapter->rx_bulk_alloc_allowed = true;
2329 adapter->rx_vec_allowed = true;
2335 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2337 struct ixgbe_hw *hw =
2338 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339 struct ixgbe_interrupt *intr =
2340 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2343 /* only set up it on X550EM_X */
2344 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2345 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2346 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2347 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2348 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2349 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2354 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2355 uint16_t tx_rate, uint64_t q_msk)
2357 struct ixgbe_hw *hw;
2358 struct ixgbe_vf_info *vfinfo;
2359 struct rte_eth_link link;
2360 uint8_t nb_q_per_pool;
2361 uint32_t queue_stride;
2362 uint32_t queue_idx, idx = 0, vf_idx;
2364 uint16_t total_rate = 0;
2365 struct rte_pci_device *pci_dev;
2367 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2368 rte_eth_link_get_nowait(dev->data->port_id, &link);
2370 if (vf >= pci_dev->max_vfs)
2373 if (tx_rate > link.link_speed)
2379 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2380 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2381 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2382 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2383 queue_idx = vf * queue_stride;
2384 queue_end = queue_idx + nb_q_per_pool - 1;
2385 if (queue_end >= hw->mac.max_tx_queues)
2389 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2392 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2394 total_rate += vfinfo[vf_idx].tx_rate[idx];
2400 /* Store tx_rate for this vf. */
2401 for (idx = 0; idx < nb_q_per_pool; idx++) {
2402 if (((uint64_t)0x1 << idx) & q_msk) {
2403 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2404 vfinfo[vf].tx_rate[idx] = tx_rate;
2405 total_rate += tx_rate;
2409 if (total_rate > dev->data->dev_link.link_speed) {
2410 /* Reset stored TX rate of the VF if it causes exceed
2413 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2417 /* Set RTTBCNRC of each queue/pool for vf X */
2418 for (; queue_idx <= queue_end; queue_idx++) {
2420 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2428 * Configure device link speed and setup link.
2429 * It returns 0 on success.
2432 ixgbe_dev_start(struct rte_eth_dev *dev)
2434 struct ixgbe_hw *hw =
2435 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436 struct ixgbe_vf_info *vfinfo =
2437 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2438 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2439 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2440 uint32_t intr_vector = 0;
2441 int err, link_up = 0, negotiate = 0;
2446 uint32_t *link_speeds;
2447 struct ixgbe_tm_conf *tm_conf =
2448 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2450 PMD_INIT_FUNC_TRACE();
2452 /* IXGBE devices don't support:
2453 * - half duplex (checked afterwards for valid speeds)
2454 * - fixed speed: TODO implement
2456 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2458 "Invalid link_speeds for port %u, fix speed not supported",
2459 dev->data->port_id);
2463 /* disable uio/vfio intr/eventfd mapping */
2464 rte_intr_disable(intr_handle);
2467 hw->adapter_stopped = 0;
2468 ixgbe_stop_adapter(hw);
2470 /* reinitialize adapter
2471 * this calls reset and start
2473 status = ixgbe_pf_reset_hw(hw);
2476 hw->mac.ops.start_hw(hw);
2477 hw->mac.get_link_status = true;
2479 /* configure PF module if SRIOV enabled */
2480 ixgbe_pf_host_configure(dev);
2482 ixgbe_dev_phy_intr_setup(dev);
2484 /* check and configure queue intr-vector mapping */
2485 if ((rte_intr_cap_multiple(intr_handle) ||
2486 !RTE_ETH_DEV_SRIOV(dev).active) &&
2487 dev->data->dev_conf.intr_conf.rxq != 0) {
2488 intr_vector = dev->data->nb_rx_queues;
2489 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2490 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2491 IXGBE_MAX_INTR_QUEUE_NUM);
2494 if (rte_intr_efd_enable(intr_handle, intr_vector))
2498 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2499 intr_handle->intr_vec =
2500 rte_zmalloc("intr_vec",
2501 dev->data->nb_rx_queues * sizeof(int), 0);
2502 if (intr_handle->intr_vec == NULL) {
2503 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2504 " intr_vec", dev->data->nb_rx_queues);
2509 /* confiugre msix for sleep until rx interrupt */
2510 ixgbe_configure_msix(dev);
2512 /* initialize transmission unit */
2513 ixgbe_dev_tx_init(dev);
2515 /* This can fail when allocating mbufs for descriptor rings */
2516 err = ixgbe_dev_rx_init(dev);
2518 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2522 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2523 ETH_VLAN_EXTEND_MASK;
2524 err = ixgbe_vlan_offload_set(dev, mask);
2526 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2530 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2531 /* Enable vlan filtering for VMDq */
2532 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2535 /* Configure DCB hw */
2536 ixgbe_configure_dcb(dev);
2538 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2539 err = ixgbe_fdir_configure(dev);
2544 /* Restore vf rate limit */
2545 if (vfinfo != NULL) {
2546 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2547 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2548 if (vfinfo[vf].tx_rate[idx] != 0)
2549 ixgbe_set_vf_rate_limit(
2551 vfinfo[vf].tx_rate[idx],
2555 ixgbe_restore_statistics_mapping(dev);
2557 err = ixgbe_dev_rxtx_start(dev);
2559 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2563 /* Skip link setup if loopback mode is enabled for 82599. */
2564 if (hw->mac.type == ixgbe_mac_82599EB &&
2565 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2566 goto skip_link_setup;
2568 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2569 err = hw->mac.ops.setup_sfp(hw);
2574 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2575 /* Turn on the copper */
2576 ixgbe_set_phy_power(hw, true);
2578 /* Turn on the laser */
2579 ixgbe_enable_tx_laser(hw);
2582 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2585 dev->data->dev_link.link_status = link_up;
2587 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2591 link_speeds = &dev->data->dev_conf.link_speeds;
2592 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2593 ETH_LINK_SPEED_10G)) {
2594 PMD_INIT_LOG(ERR, "Invalid link setting");
2599 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2600 switch (hw->mac.type) {
2601 case ixgbe_mac_82598EB:
2602 speed = IXGBE_LINK_SPEED_82598_AUTONEG;
2604 case ixgbe_mac_82599EB:
2605 case ixgbe_mac_X540:
2606 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2608 case ixgbe_mac_X550:
2609 case ixgbe_mac_X550EM_x:
2610 case ixgbe_mac_X550EM_a:
2611 speed = IXGBE_LINK_SPEED_X550_AUTONEG;
2614 speed = IXGBE_LINK_SPEED_82599_AUTONEG;
2617 if (*link_speeds & ETH_LINK_SPEED_10G)
2618 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2619 if (*link_speeds & ETH_LINK_SPEED_1G)
2620 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2621 if (*link_speeds & ETH_LINK_SPEED_100M)
2622 speed |= IXGBE_LINK_SPEED_100_FULL;
2625 err = ixgbe_setup_link(hw, speed, link_up);
2631 if (rte_intr_allow_others(intr_handle)) {
2632 /* check if lsc interrupt is enabled */
2633 if (dev->data->dev_conf.intr_conf.lsc != 0)
2634 ixgbe_dev_lsc_interrupt_setup(dev, TRUE);
2636 ixgbe_dev_lsc_interrupt_setup(dev, FALSE);
2637 ixgbe_dev_macsec_interrupt_setup(dev);
2639 rte_intr_callback_unregister(intr_handle,
2640 ixgbe_dev_interrupt_handler, dev);
2641 if (dev->data->dev_conf.intr_conf.lsc != 0)
2642 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2643 " no intr multiplex");
2646 /* check if rxq interrupt is enabled */
2647 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2648 rte_intr_dp_is_en(intr_handle))
2649 ixgbe_dev_rxq_interrupt_setup(dev);
2651 /* enable uio/vfio intr/eventfd mapping */
2652 rte_intr_enable(intr_handle);
2654 /* resume enabled intr since hw reset */
2655 ixgbe_enable_intr(dev);
2656 ixgbe_l2_tunnel_conf(dev);
2657 ixgbe_filter_restore(dev);
2659 if (tm_conf->root && !tm_conf->committed)
2660 PMD_DRV_LOG(WARNING,
2661 "please call hierarchy_commit() "
2662 "before starting the port");
2667 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2668 ixgbe_dev_clear_queues(dev);
2673 * Stop device: disable rx and tx functions to allow for reconfiguring.
2676 ixgbe_dev_stop(struct rte_eth_dev *dev)
2678 struct rte_eth_link link;
2679 struct ixgbe_hw *hw =
2680 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 struct ixgbe_vf_info *vfinfo =
2682 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2683 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2684 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2686 struct ixgbe_tm_conf *tm_conf =
2687 IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private);
2689 PMD_INIT_FUNC_TRACE();
2691 /* disable interrupts */
2692 ixgbe_disable_intr(hw);
2695 ixgbe_pf_reset_hw(hw);
2696 hw->adapter_stopped = 0;
2699 ixgbe_stop_adapter(hw);
2701 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2702 vfinfo[vf].clear_to_send = false;
2704 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2705 /* Turn off the copper */
2706 ixgbe_set_phy_power(hw, false);
2708 /* Turn off the laser */
2709 ixgbe_disable_tx_laser(hw);
2712 ixgbe_dev_clear_queues(dev);
2714 /* Clear stored conf */
2715 dev->data->scattered_rx = 0;
2718 /* Clear recorded link status */
2719 memset(&link, 0, sizeof(link));
2720 rte_eth_linkstatus_set(dev, &link);
2722 if (!rte_intr_allow_others(intr_handle))
2723 /* resume to the default handler */
2724 rte_intr_callback_register(intr_handle,
2725 ixgbe_dev_interrupt_handler,
2728 /* Clean datapath event and queue/vec mapping */
2729 rte_intr_efd_disable(intr_handle);
2730 if (intr_handle->intr_vec != NULL) {
2731 rte_free(intr_handle->intr_vec);
2732 intr_handle->intr_vec = NULL;
2735 /* reset hierarchy commit */
2736 tm_conf->committed = false;
2740 * Set device link up: enable tx.
2743 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2745 struct ixgbe_hw *hw =
2746 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2747 if (hw->mac.type == ixgbe_mac_82599EB) {
2748 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2749 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2750 /* Not suported in bypass mode */
2751 PMD_INIT_LOG(ERR, "Set link up is not supported "
2752 "by device id 0x%x", hw->device_id);
2758 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2759 /* Turn on the copper */
2760 ixgbe_set_phy_power(hw, true);
2762 /* Turn on the laser */
2763 ixgbe_enable_tx_laser(hw);
2770 * Set device link down: disable tx.
2773 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2775 struct ixgbe_hw *hw =
2776 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2777 if (hw->mac.type == ixgbe_mac_82599EB) {
2778 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2779 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2780 /* Not suported in bypass mode */
2781 PMD_INIT_LOG(ERR, "Set link down is not supported "
2782 "by device id 0x%x", hw->device_id);
2788 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2789 /* Turn off the copper */
2790 ixgbe_set_phy_power(hw, false);
2792 /* Turn off the laser */
2793 ixgbe_disable_tx_laser(hw);
2800 * Reset and stop device.
2803 ixgbe_dev_close(struct rte_eth_dev *dev)
2805 struct ixgbe_hw *hw =
2806 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808 PMD_INIT_FUNC_TRACE();
2810 ixgbe_pf_reset_hw(hw);
2812 ixgbe_dev_stop(dev);
2813 hw->adapter_stopped = 1;
2815 ixgbe_dev_free_queues(dev);
2817 ixgbe_disable_pcie_master(hw);
2819 /* reprogram the RAR[0] in case user changed it. */
2820 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2827 ixgbe_dev_reset(struct rte_eth_dev *dev)
2831 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2832 * its VF to make them align with it. The detailed notification
2833 * mechanism is PMD specific. As to ixgbe PF, it is rather complex.
2834 * To avoid unexpected behavior in VF, currently reset of PF with
2835 * SR-IOV activation is not supported. It might be supported later.
2837 if (dev->data->sriov.active)
2840 ret = eth_ixgbe_dev_uninit(dev);
2844 ret = eth_ixgbe_dev_init(dev);
2850 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2851 struct ixgbe_hw_stats *hw_stats,
2852 struct ixgbe_macsec_stats *macsec_stats,
2853 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2854 uint64_t *total_qprc, uint64_t *total_qprdc)
2856 uint32_t bprc, lxon, lxoff, total;
2857 uint32_t delta_gprc = 0;
2859 /* Workaround for RX byte count not including CRC bytes when CRC
2860 * strip is enabled. CRC bytes are removed from counters when crc_strip
2863 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2864 IXGBE_HLREG0_RXCRCSTRP);
2866 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2867 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2868 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2869 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2871 for (i = 0; i < 8; i++) {
2872 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2874 /* global total per queue */
2875 hw_stats->mpc[i] += mp;
2876 /* Running comprehensive total for stats display */
2877 *total_missed_rx += hw_stats->mpc[i];
2878 if (hw->mac.type == ixgbe_mac_82598EB) {
2879 hw_stats->rnbc[i] +=
2880 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2881 hw_stats->pxonrxc[i] +=
2882 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2883 hw_stats->pxoffrxc[i] +=
2884 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2886 hw_stats->pxonrxc[i] +=
2887 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2888 hw_stats->pxoffrxc[i] +=
2889 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2890 hw_stats->pxon2offc[i] +=
2891 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2893 hw_stats->pxontxc[i] +=
2894 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2895 hw_stats->pxofftxc[i] +=
2896 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2898 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2899 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2900 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2901 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2903 delta_gprc += delta_qprc;
2905 hw_stats->qprc[i] += delta_qprc;
2906 hw_stats->qptc[i] += delta_qptc;
2908 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2909 hw_stats->qbrc[i] +=
2910 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2912 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2914 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2915 hw_stats->qbtc[i] +=
2916 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2918 hw_stats->qprdc[i] += delta_qprdc;
2919 *total_qprdc += hw_stats->qprdc[i];
2921 *total_qprc += hw_stats->qprc[i];
2922 *total_qbrc += hw_stats->qbrc[i];
2924 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2925 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2926 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2929 * An errata states that gprc actually counts good + missed packets:
2930 * Workaround to set gprc to summated queue packet receives
2932 hw_stats->gprc = *total_qprc;
2934 if (hw->mac.type != ixgbe_mac_82598EB) {
2935 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2936 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2937 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2938 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2939 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2940 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2941 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2942 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2944 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2945 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2946 /* 82598 only has a counter in the high register */
2947 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2948 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2949 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2951 uint64_t old_tpr = hw_stats->tpr;
2953 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2954 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2957 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2959 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2960 hw_stats->gptc += delta_gptc;
2961 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2962 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2965 * Workaround: mprc hardware is incorrectly counting
2966 * broadcasts, so for now we subtract those.
2968 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2969 hw_stats->bprc += bprc;
2970 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2971 if (hw->mac.type == ixgbe_mac_82598EB)
2972 hw_stats->mprc -= bprc;
2974 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2975 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2976 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2977 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2978 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2979 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2981 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2982 hw_stats->lxontxc += lxon;
2983 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2984 hw_stats->lxofftxc += lxoff;
2985 total = lxon + lxoff;
2987 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2988 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2989 hw_stats->gptc -= total;
2990 hw_stats->mptc -= total;
2991 hw_stats->ptc64 -= total;
2992 hw_stats->gotc -= total * ETHER_MIN_LEN;
2994 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2995 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2996 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2997 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2998 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2999 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
3000 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
3001 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3002 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3003 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3004 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3005 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3006 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3007 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3008 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3009 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3010 /* Only read FCOE on 82599 */
3011 if (hw->mac.type != ixgbe_mac_82598EB) {
3012 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3013 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3014 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3015 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3016 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3019 /* Flow Director Stats registers */
3020 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3021 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3023 /* MACsec Stats registers */
3024 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3025 macsec_stats->out_pkts_encrypted +=
3026 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3027 macsec_stats->out_pkts_protected +=
3028 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3029 macsec_stats->out_octets_encrypted +=
3030 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3031 macsec_stats->out_octets_protected +=
3032 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3033 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3034 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3035 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3036 macsec_stats->in_pkts_unknownsci +=
3037 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3038 macsec_stats->in_octets_decrypted +=
3039 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3040 macsec_stats->in_octets_validated +=
3041 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3042 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3043 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3044 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3045 for (i = 0; i < 2; i++) {
3046 macsec_stats->in_pkts_ok +=
3047 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3048 macsec_stats->in_pkts_invalid +=
3049 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3050 macsec_stats->in_pkts_notvalid +=
3051 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3053 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3054 macsec_stats->in_pkts_notusingsa +=
3055 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3059 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3062 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3064 struct ixgbe_hw *hw =
3065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3066 struct ixgbe_hw_stats *hw_stats =
3067 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3068 struct ixgbe_macsec_stats *macsec_stats =
3069 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3070 dev->data->dev_private);
3071 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3074 total_missed_rx = 0;
3079 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3080 &total_qbrc, &total_qprc, &total_qprdc);
3085 /* Fill out the rte_eth_stats statistics structure */
3086 stats->ipackets = total_qprc;
3087 stats->ibytes = total_qbrc;
3088 stats->opackets = hw_stats->gptc;
3089 stats->obytes = hw_stats->gotc;
3091 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3092 stats->q_ipackets[i] = hw_stats->qprc[i];
3093 stats->q_opackets[i] = hw_stats->qptc[i];
3094 stats->q_ibytes[i] = hw_stats->qbrc[i];
3095 stats->q_obytes[i] = hw_stats->qbtc[i];
3096 stats->q_errors[i] = hw_stats->qprdc[i];
3100 stats->imissed = total_missed_rx;
3101 stats->ierrors = hw_stats->crcerrs +
3118 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3120 struct ixgbe_hw_stats *stats =
3121 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3123 /* HW registers are cleared on read */
3124 ixgbe_dev_stats_get(dev, NULL);
3126 /* Reset software totals */
3127 memset(stats, 0, sizeof(*stats));
3130 /* This function calculates the number of xstats based on the current config */
3132 ixgbe_xstats_calc_num(void) {
3133 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3134 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3135 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3138 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3139 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3141 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3142 unsigned stat, i, count;
3144 if (xstats_names != NULL) {
3147 /* Note: limit >= cnt_stats checked upstream
3148 * in rte_eth_xstats_names()
3151 /* Extended stats from ixgbe_hw_stats */
3152 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3153 snprintf(xstats_names[count].name,
3154 sizeof(xstats_names[count].name),
3156 rte_ixgbe_stats_strings[i].name);
3161 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3162 snprintf(xstats_names[count].name,
3163 sizeof(xstats_names[count].name),
3165 rte_ixgbe_macsec_strings[i].name);
3169 /* RX Priority Stats */
3170 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3171 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3172 snprintf(xstats_names[count].name,
3173 sizeof(xstats_names[count].name),
3174 "rx_priority%u_%s", i,
3175 rte_ixgbe_rxq_strings[stat].name);
3180 /* TX Priority Stats */
3181 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3182 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3183 snprintf(xstats_names[count].name,
3184 sizeof(xstats_names[count].name),
3185 "tx_priority%u_%s", i,
3186 rte_ixgbe_txq_strings[stat].name);
3194 static int ixgbe_dev_xstats_get_names_by_id(
3195 struct rte_eth_dev *dev,
3196 struct rte_eth_xstat_name *xstats_names,
3197 const uint64_t *ids,
3201 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3202 unsigned int stat, i, count;
3204 if (xstats_names != NULL) {
3207 /* Note: limit >= cnt_stats checked upstream
3208 * in rte_eth_xstats_names()
3211 /* Extended stats from ixgbe_hw_stats */
3212 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3213 snprintf(xstats_names[count].name,
3214 sizeof(xstats_names[count].name),
3216 rte_ixgbe_stats_strings[i].name);
3221 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3222 snprintf(xstats_names[count].name,
3223 sizeof(xstats_names[count].name),
3225 rte_ixgbe_macsec_strings[i].name);
3229 /* RX Priority Stats */
3230 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3231 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3232 snprintf(xstats_names[count].name,
3233 sizeof(xstats_names[count].name),
3234 "rx_priority%u_%s", i,
3235 rte_ixgbe_rxq_strings[stat].name);
3240 /* TX Priority Stats */
3241 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3242 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3243 snprintf(xstats_names[count].name,
3244 sizeof(xstats_names[count].name),
3245 "tx_priority%u_%s", i,
3246 rte_ixgbe_txq_strings[stat].name);
3255 uint16_t size = ixgbe_xstats_calc_num();
3256 struct rte_eth_xstat_name xstats_names_copy[size];
3258 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3261 for (i = 0; i < limit; i++) {
3262 if (ids[i] >= size) {
3263 PMD_INIT_LOG(ERR, "id value isn't valid");
3266 strcpy(xstats_names[i].name,
3267 xstats_names_copy[ids[i]].name);
3272 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3273 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3277 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3280 if (xstats_names != NULL)
3281 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3282 snprintf(xstats_names[i].name,
3283 sizeof(xstats_names[i].name),
3284 "%s", rte_ixgbevf_stats_strings[i].name);
3285 return IXGBEVF_NB_XSTATS;
3289 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3292 struct ixgbe_hw *hw =
3293 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294 struct ixgbe_hw_stats *hw_stats =
3295 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3296 struct ixgbe_macsec_stats *macsec_stats =
3297 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3298 dev->data->dev_private);
3299 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3300 unsigned i, stat, count = 0;
3302 count = ixgbe_xstats_calc_num();
3307 total_missed_rx = 0;
3312 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3313 &total_qbrc, &total_qprc, &total_qprdc);
3315 /* If this is a reset xstats is NULL, and we have cleared the
3316 * registers by reading them.
3321 /* Extended stats from ixgbe_hw_stats */
3323 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3324 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3325 rte_ixgbe_stats_strings[i].offset);
3326 xstats[count].id = count;
3331 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3332 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3333 rte_ixgbe_macsec_strings[i].offset);
3334 xstats[count].id = count;
3338 /* RX Priority Stats */
3339 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3340 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3341 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3342 rte_ixgbe_rxq_strings[stat].offset +
3343 (sizeof(uint64_t) * i));
3344 xstats[count].id = count;
3349 /* TX Priority Stats */
3350 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3351 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3352 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3353 rte_ixgbe_txq_strings[stat].offset +
3354 (sizeof(uint64_t) * i));
3355 xstats[count].id = count;
3363 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3364 uint64_t *values, unsigned int n)
3367 struct ixgbe_hw *hw =
3368 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3369 struct ixgbe_hw_stats *hw_stats =
3370 IXGBE_DEV_PRIVATE_TO_STATS(
3371 dev->data->dev_private);
3372 struct ixgbe_macsec_stats *macsec_stats =
3373 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3374 dev->data->dev_private);
3375 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3376 unsigned int i, stat, count = 0;
3378 count = ixgbe_xstats_calc_num();
3380 if (!ids && n < count)
3383 total_missed_rx = 0;
3388 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3389 &total_missed_rx, &total_qbrc, &total_qprc,
3392 /* If this is a reset xstats is NULL, and we have cleared the
3393 * registers by reading them.
3395 if (!ids && !values)
3398 /* Extended stats from ixgbe_hw_stats */
3400 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3401 values[count] = *(uint64_t *)(((char *)hw_stats) +
3402 rte_ixgbe_stats_strings[i].offset);
3407 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3408 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3409 rte_ixgbe_macsec_strings[i].offset);
3413 /* RX Priority Stats */
3414 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3415 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3417 *(uint64_t *)(((char *)hw_stats) +
3418 rte_ixgbe_rxq_strings[stat].offset +
3419 (sizeof(uint64_t) * i));
3424 /* TX Priority Stats */
3425 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3426 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3428 *(uint64_t *)(((char *)hw_stats) +
3429 rte_ixgbe_txq_strings[stat].offset +
3430 (sizeof(uint64_t) * i));
3438 uint16_t size = ixgbe_xstats_calc_num();
3439 uint64_t values_copy[size];
3441 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3443 for (i = 0; i < n; i++) {
3444 if (ids[i] >= size) {
3445 PMD_INIT_LOG(ERR, "id value isn't valid");
3448 values[i] = values_copy[ids[i]];
3454 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3456 struct ixgbe_hw_stats *stats =
3457 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3458 struct ixgbe_macsec_stats *macsec_stats =
3459 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3460 dev->data->dev_private);
3462 unsigned count = ixgbe_xstats_calc_num();
3464 /* HW registers are cleared on read */
3465 ixgbe_dev_xstats_get(dev, NULL, count);
3467 /* Reset software totals */
3468 memset(stats, 0, sizeof(*stats));
3469 memset(macsec_stats, 0, sizeof(*macsec_stats));
3473 ixgbevf_update_stats(struct rte_eth_dev *dev)
3475 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3477 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3479 /* Good Rx packet, include VF loopback */
3480 UPDATE_VF_STAT(IXGBE_VFGPRC,
3481 hw_stats->last_vfgprc, hw_stats->vfgprc);
3483 /* Good Rx octets, include VF loopback */
3484 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3485 hw_stats->last_vfgorc, hw_stats->vfgorc);
3487 /* Good Tx packet, include VF loopback */
3488 UPDATE_VF_STAT(IXGBE_VFGPTC,
3489 hw_stats->last_vfgptc, hw_stats->vfgptc);
3491 /* Good Tx octets, include VF loopback */
3492 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3493 hw_stats->last_vfgotc, hw_stats->vfgotc);
3495 /* Rx Multicst Packet */
3496 UPDATE_VF_STAT(IXGBE_VFMPRC,
3497 hw_stats->last_vfmprc, hw_stats->vfmprc);
3501 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3504 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3505 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3508 if (n < IXGBEVF_NB_XSTATS)
3509 return IXGBEVF_NB_XSTATS;
3511 ixgbevf_update_stats(dev);
3516 /* Extended stats */
3517 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3519 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3520 rte_ixgbevf_stats_strings[i].offset);
3523 return IXGBEVF_NB_XSTATS;
3527 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3529 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3530 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3532 ixgbevf_update_stats(dev);
3537 stats->ipackets = hw_stats->vfgprc;
3538 stats->ibytes = hw_stats->vfgorc;
3539 stats->opackets = hw_stats->vfgptc;
3540 stats->obytes = hw_stats->vfgotc;
3545 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3547 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3548 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3550 /* Sync HW register to the last stats */
3551 ixgbevf_dev_stats_get(dev, NULL);
3553 /* reset HW current stats*/
3554 hw_stats->vfgprc = 0;
3555 hw_stats->vfgorc = 0;
3556 hw_stats->vfgptc = 0;
3557 hw_stats->vfgotc = 0;
3561 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3563 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3564 u16 eeprom_verh, eeprom_verl;
3568 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3569 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3571 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3572 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3574 ret += 1; /* add the size of '\0' */
3575 if (fw_size < (u32)ret)
3582 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3584 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3585 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3586 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3588 dev_info->pci_dev = pci_dev;
3589 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3590 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3591 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3593 * When DCB/VT is off, maximum number of queues changes,
3594 * except for 82598EB, which remains constant.
3596 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3597 hw->mac.type != ixgbe_mac_82598EB)
3598 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3600 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3601 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3602 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3603 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3604 dev_info->max_vfs = pci_dev->max_vfs;
3605 if (hw->mac.type == ixgbe_mac_82598EB)
3606 dev_info->max_vmdq_pools = ETH_16_POOLS;
3608 dev_info->max_vmdq_pools = ETH_64_POOLS;
3609 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3610 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3611 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3612 dev_info->rx_queue_offload_capa);
3614 dev_info->tx_offload_capa =
3615 DEV_TX_OFFLOAD_VLAN_INSERT |
3616 DEV_TX_OFFLOAD_IPV4_CKSUM |
3617 DEV_TX_OFFLOAD_UDP_CKSUM |
3618 DEV_TX_OFFLOAD_TCP_CKSUM |
3619 DEV_TX_OFFLOAD_SCTP_CKSUM |
3620 DEV_TX_OFFLOAD_TCP_TSO;
3622 if (hw->mac.type == ixgbe_mac_82599EB ||
3623 hw->mac.type == ixgbe_mac_X540)
3624 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3626 if (hw->mac.type == ixgbe_mac_X550 ||
3627 hw->mac.type == ixgbe_mac_X550EM_x ||
3628 hw->mac.type == ixgbe_mac_X550EM_a)
3629 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3631 #ifdef RTE_LIBRTE_SECURITY
3632 if (dev->security_ctx)
3633 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_SECURITY;
3636 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3638 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3639 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3640 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3642 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3647 dev_info->default_txconf = (struct rte_eth_txconf) {
3649 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3650 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3651 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3653 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3654 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3655 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3656 ETH_TXQ_FLAGS_NOOFFLOADS,
3659 dev_info->rx_desc_lim = rx_desc_lim;
3660 dev_info->tx_desc_lim = tx_desc_lim;
3662 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3663 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3664 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3666 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3667 if (hw->mac.type == ixgbe_mac_X540 ||
3668 hw->mac.type == ixgbe_mac_X540_vf ||
3669 hw->mac.type == ixgbe_mac_X550 ||
3670 hw->mac.type == ixgbe_mac_X550_vf) {
3671 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3673 if (hw->mac.type == ixgbe_mac_X550) {
3674 dev_info->speed_capa |= ETH_LINK_SPEED_2_5G;
3675 dev_info->speed_capa |= ETH_LINK_SPEED_5G;
3679 static const uint32_t *
3680 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3682 static const uint32_t ptypes[] = {
3683 /* For non-vec functions,
3684 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3685 * for vec functions,
3686 * refers to _recv_raw_pkts_vec().
3690 RTE_PTYPE_L3_IPV4_EXT,
3692 RTE_PTYPE_L3_IPV6_EXT,
3696 RTE_PTYPE_TUNNEL_IP,
3697 RTE_PTYPE_INNER_L3_IPV6,
3698 RTE_PTYPE_INNER_L3_IPV6_EXT,
3699 RTE_PTYPE_INNER_L4_TCP,
3700 RTE_PTYPE_INNER_L4_UDP,
3704 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3705 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3706 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3707 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3710 #if defined(RTE_ARCH_X86)
3711 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3712 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3719 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3720 struct rte_eth_dev_info *dev_info)
3722 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3723 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725 dev_info->pci_dev = pci_dev;
3726 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3727 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3728 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3729 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3730 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3731 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3732 dev_info->max_vfs = pci_dev->max_vfs;
3733 if (hw->mac.type == ixgbe_mac_82598EB)
3734 dev_info->max_vmdq_pools = ETH_16_POOLS;
3736 dev_info->max_vmdq_pools = ETH_64_POOLS;
3737 dev_info->rx_queue_offload_capa = ixgbe_get_rx_queue_offloads(dev);
3738 dev_info->rx_offload_capa = (ixgbe_get_rx_port_offloads(dev) |
3739 dev_info->rx_queue_offload_capa);
3740 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3741 DEV_TX_OFFLOAD_IPV4_CKSUM |
3742 DEV_TX_OFFLOAD_UDP_CKSUM |
3743 DEV_TX_OFFLOAD_TCP_CKSUM |
3744 DEV_TX_OFFLOAD_SCTP_CKSUM |
3745 DEV_TX_OFFLOAD_TCP_TSO;
3747 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3749 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3750 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3751 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3753 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3758 dev_info->default_txconf = (struct rte_eth_txconf) {
3760 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3761 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3762 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3764 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3765 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3766 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3767 ETH_TXQ_FLAGS_NOOFFLOADS,
3770 dev_info->rx_desc_lim = rx_desc_lim;
3771 dev_info->tx_desc_lim = tx_desc_lim;
3775 ixgbevf_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3776 int *link_up, int wait_to_complete)
3779 * for a quick link status checking, wait_to_compelet == 0,
3780 * skip PF link status checking
3782 bool no_pflink_check = wait_to_complete == 0;
3783 struct ixgbe_mbx_info *mbx = &hw->mbx;
3784 struct ixgbe_mac_info *mac = &hw->mac;
3785 uint32_t links_reg, in_msg;
3788 /* If we were hit with a reset drop the link */
3789 if (!mbx->ops.check_for_rst(hw, 0) || !mbx->timeout)
3790 mac->get_link_status = true;
3792 if (!mac->get_link_status)
3795 /* if link status is down no point in checking to see if pf is up */
3796 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3797 if (!(links_reg & IXGBE_LINKS_UP))
3800 /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
3801 * before the link status is correct
3803 if (mac->type == ixgbe_mac_82599_vf) {
3806 for (i = 0; i < 5; i++) {
3808 links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
3810 if (!(links_reg & IXGBE_LINKS_UP))
3815 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
3816 case IXGBE_LINKS_SPEED_10G_82599:
3817 *speed = IXGBE_LINK_SPEED_10GB_FULL;
3818 if (hw->mac.type >= ixgbe_mac_X550) {
3819 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3820 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
3823 case IXGBE_LINKS_SPEED_1G_82599:
3824 *speed = IXGBE_LINK_SPEED_1GB_FULL;
3826 case IXGBE_LINKS_SPEED_100_82599:
3827 *speed = IXGBE_LINK_SPEED_100_FULL;
3828 if (hw->mac.type == ixgbe_mac_X550) {
3829 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
3830 *speed = IXGBE_LINK_SPEED_5GB_FULL;
3833 case IXGBE_LINKS_SPEED_10_X550EM_A:
3834 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3835 /* Since Reserved in older MAC's */
3836 if (hw->mac.type >= ixgbe_mac_X550)
3837 *speed = IXGBE_LINK_SPEED_10_FULL;
3840 *speed = IXGBE_LINK_SPEED_UNKNOWN;
3843 if (no_pflink_check) {
3844 if (*speed == IXGBE_LINK_SPEED_UNKNOWN)
3845 mac->get_link_status = true;
3847 mac->get_link_status = false;
3851 /* if the read failed it could just be a mailbox collision, best wait
3852 * until we are called again and don't report an error
3854 if (mbx->ops.read(hw, &in_msg, 1, 0))
3857 if (!(in_msg & IXGBE_VT_MSGTYPE_CTS)) {
3858 /* msg is not CTS and is NACK we must have lost CTS status */
3859 if (in_msg & IXGBE_VT_MSGTYPE_NACK)
3864 /* the pf is talking, if we timed out in the past we reinit */
3865 if (!mbx->timeout) {
3870 /* if we passed all the tests above then the link is up and we no
3871 * longer need to check for link
3873 mac->get_link_status = false;
3876 *link_up = !mac->get_link_status;
3880 /* return 0 means link status changed, -1 means not changed */
3882 ixgbe_dev_link_update_share(struct rte_eth_dev *dev,
3883 int wait_to_complete, int vf)
3885 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3886 struct rte_eth_link link;
3887 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3888 struct ixgbe_interrupt *intr =
3889 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3894 bool autoneg = false;
3896 memset(&link, 0, sizeof(link));
3897 link.link_status = ETH_LINK_DOWN;
3898 link.link_speed = 0;
3899 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3900 link.link_autoneg = ETH_LINK_AUTONEG;
3902 hw->mac.get_link_status = true;
3904 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3905 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3906 speed = hw->phy.autoneg_advertised;
3908 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3909 ixgbe_setup_link(hw, speed, true);
3912 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3913 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3917 diag = ixgbevf_check_link(hw, &link_speed, &link_up, wait);
3919 diag = ixgbe_check_link(hw, &link_speed, &link_up, wait);
3922 link.link_speed = ETH_SPEED_NUM_100M;
3923 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3924 return rte_eth_linkstatus_set(dev, &link);
3928 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3929 return rte_eth_linkstatus_set(dev, &link);
3932 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3933 link.link_status = ETH_LINK_UP;
3934 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3936 switch (link_speed) {
3938 case IXGBE_LINK_SPEED_UNKNOWN:
3939 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3940 link.link_speed = ETH_SPEED_NUM_100M;
3943 case IXGBE_LINK_SPEED_100_FULL:
3944 link.link_speed = ETH_SPEED_NUM_100M;
3947 case IXGBE_LINK_SPEED_1GB_FULL:
3948 link.link_speed = ETH_SPEED_NUM_1G;
3951 case IXGBE_LINK_SPEED_2_5GB_FULL:
3952 link.link_speed = ETH_SPEED_NUM_2_5G;
3955 case IXGBE_LINK_SPEED_5GB_FULL:
3956 link.link_speed = ETH_SPEED_NUM_5G;
3959 case IXGBE_LINK_SPEED_10GB_FULL:
3960 link.link_speed = ETH_SPEED_NUM_10G;
3964 return rte_eth_linkstatus_set(dev, &link);
3968 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3970 return ixgbe_dev_link_update_share(dev, wait_to_complete, 0);
3974 ixgbevf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3976 return ixgbe_dev_link_update_share(dev, wait_to_complete, 1);
3980 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3982 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3985 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3986 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3987 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3991 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3993 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3996 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3997 fctrl &= (~IXGBE_FCTRL_UPE);
3998 if (dev->data->all_multicast == 1)
3999 fctrl |= IXGBE_FCTRL_MPE;
4001 fctrl &= (~IXGBE_FCTRL_MPE);
4002 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4006 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
4008 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4011 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4012 fctrl |= IXGBE_FCTRL_MPE;
4013 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4017 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
4019 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4022 if (dev->data->promiscuous == 1)
4023 return; /* must remain in all_multicast mode */
4025 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4026 fctrl &= (~IXGBE_FCTRL_MPE);
4027 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4031 * It clears the interrupt causes and enables the interrupt.
4032 * It will be called once only during nic initialized.
4035 * Pointer to struct rte_eth_dev.
4037 * Enable or Disable.
4040 * - On success, zero.
4041 * - On failure, a negative value.
4044 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
4046 struct ixgbe_interrupt *intr =
4047 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4049 ixgbe_dev_link_status_print(dev);
4051 intr->mask |= IXGBE_EICR_LSC;
4053 intr->mask &= ~IXGBE_EICR_LSC;
4059 * It clears the interrupt causes and enables the interrupt.
4060 * It will be called once only during nic initialized.
4063 * Pointer to struct rte_eth_dev.
4066 * - On success, zero.
4067 * - On failure, a negative value.
4070 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
4072 struct ixgbe_interrupt *intr =
4073 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4075 intr->mask |= IXGBE_EICR_RTX_QUEUE;
4081 * It clears the interrupt causes and enables the interrupt.
4082 * It will be called once only during nic initialized.
4085 * Pointer to struct rte_eth_dev.
4088 * - On success, zero.
4089 * - On failure, a negative value.
4092 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
4094 struct ixgbe_interrupt *intr =
4095 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4097 intr->mask |= IXGBE_EICR_LINKSEC;
4103 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
4106 * Pointer to struct rte_eth_dev.
4109 * - On success, zero.
4110 * - On failure, a negative value.
4113 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
4116 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4117 struct ixgbe_interrupt *intr =
4118 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4120 /* clear all cause mask */
4121 ixgbe_disable_intr(hw);
4123 /* read-on-clear nic registers here */
4124 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4125 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4129 /* set flag for async link update */
4130 if (eicr & IXGBE_EICR_LSC)
4131 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4133 if (eicr & IXGBE_EICR_MAILBOX)
4134 intr->flags |= IXGBE_FLAG_MAILBOX;
4136 if (eicr & IXGBE_EICR_LINKSEC)
4137 intr->flags |= IXGBE_FLAG_MACSEC;
4139 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4140 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4141 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4142 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4148 * It gets and then prints the link status.
4151 * Pointer to struct rte_eth_dev.
4154 * - On success, zero.
4155 * - On failure, a negative value.
4158 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4160 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4161 struct rte_eth_link link;
4163 rte_eth_linkstatus_get(dev, &link);
4165 if (link.link_status) {
4166 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4167 (int)(dev->data->port_id),
4168 (unsigned)link.link_speed,
4169 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4170 "full-duplex" : "half-duplex");
4172 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4173 (int)(dev->data->port_id));
4175 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4176 pci_dev->addr.domain,
4178 pci_dev->addr.devid,
4179 pci_dev->addr.function);
4183 * It executes link_update after knowing an interrupt occurred.
4186 * Pointer to struct rte_eth_dev.
4189 * - On success, zero.
4190 * - On failure, a negative value.
4193 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4194 struct rte_intr_handle *intr_handle)
4196 struct ixgbe_interrupt *intr =
4197 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4199 struct ixgbe_hw *hw =
4200 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4202 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4204 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4205 ixgbe_pf_mbx_process(dev);
4206 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4209 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4210 ixgbe_handle_lasi(hw);
4211 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4214 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4215 struct rte_eth_link link;
4217 /* get the link status before link update, for predicting later */
4218 rte_eth_linkstatus_get(dev, &link);
4220 ixgbe_dev_link_update(dev, 0);
4223 if (!link.link_status)
4224 /* handle it 1 sec later, wait it being stable */
4225 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4226 /* likely to down */
4228 /* handle it 4 sec later, wait it being stable */
4229 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4231 ixgbe_dev_link_status_print(dev);
4232 if (rte_eal_alarm_set(timeout * 1000,
4233 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4234 PMD_DRV_LOG(ERR, "Error setting alarm");
4236 /* remember original mask */
4237 intr->mask_original = intr->mask;
4238 /* only disable lsc interrupt */
4239 intr->mask &= ~IXGBE_EIMS_LSC;
4243 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4244 ixgbe_enable_intr(dev);
4245 rte_intr_enable(intr_handle);
4251 * Interrupt handler which shall be registered for alarm callback for delayed
4252 * handling specific interrupt to wait for the stable nic state. As the
4253 * NIC interrupt state is not stable for ixgbe after link is just down,
4254 * it needs to wait 4 seconds to get the stable status.
4257 * Pointer to interrupt handle.
4259 * The address of parameter (struct rte_eth_dev *) regsitered before.
4265 ixgbe_dev_interrupt_delayed_handler(void *param)
4267 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4268 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4269 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4270 struct ixgbe_interrupt *intr =
4271 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4272 struct ixgbe_hw *hw =
4273 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4276 ixgbe_disable_intr(hw);
4278 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4279 if (eicr & IXGBE_EICR_MAILBOX)
4280 ixgbe_pf_mbx_process(dev);
4282 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4283 ixgbe_handle_lasi(hw);
4284 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4287 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4288 ixgbe_dev_link_update(dev, 0);
4289 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4290 ixgbe_dev_link_status_print(dev);
4291 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4295 if (intr->flags & IXGBE_FLAG_MACSEC) {
4296 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4298 intr->flags &= ~IXGBE_FLAG_MACSEC;
4301 /* restore original mask */
4302 intr->mask = intr->mask_original;
4303 intr->mask_original = 0;
4305 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4306 ixgbe_enable_intr(dev);
4307 rte_intr_enable(intr_handle);
4311 * Interrupt handler triggered by NIC for handling
4312 * specific interrupt.
4315 * Pointer to interrupt handle.
4317 * The address of parameter (struct rte_eth_dev *) regsitered before.
4323 ixgbe_dev_interrupt_handler(void *param)
4325 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4327 ixgbe_dev_interrupt_get_status(dev);
4328 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4332 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4334 struct ixgbe_hw *hw;
4336 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4337 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4341 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4343 struct ixgbe_hw *hw;
4345 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4346 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4350 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4352 struct ixgbe_hw *hw;
4358 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4360 fc_conf->pause_time = hw->fc.pause_time;
4361 fc_conf->high_water = hw->fc.high_water[0];
4362 fc_conf->low_water = hw->fc.low_water[0];
4363 fc_conf->send_xon = hw->fc.send_xon;
4364 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4367 * Return rx_pause status according to actual setting of
4370 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4371 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4377 * Return tx_pause status according to actual setting of
4380 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4381 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4386 if (rx_pause && tx_pause)
4387 fc_conf->mode = RTE_FC_FULL;
4389 fc_conf->mode = RTE_FC_RX_PAUSE;
4391 fc_conf->mode = RTE_FC_TX_PAUSE;
4393 fc_conf->mode = RTE_FC_NONE;
4399 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4401 struct ixgbe_hw *hw;
4403 uint32_t rx_buf_size;
4404 uint32_t max_high_water;
4406 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4413 PMD_INIT_FUNC_TRACE();
4415 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4416 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4417 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4420 * At least reserve one Ethernet frame for watermark
4421 * high_water/low_water in kilo bytes for ixgbe
4423 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4424 if ((fc_conf->high_water > max_high_water) ||
4425 (fc_conf->high_water < fc_conf->low_water)) {
4426 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4427 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4431 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4432 hw->fc.pause_time = fc_conf->pause_time;
4433 hw->fc.high_water[0] = fc_conf->high_water;
4434 hw->fc.low_water[0] = fc_conf->low_water;
4435 hw->fc.send_xon = fc_conf->send_xon;
4436 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4438 err = ixgbe_fc_enable(hw);
4440 /* Not negotiated is not an error case */
4441 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4443 /* check if we want to forward MAC frames - driver doesn't have native
4444 * capability to do that, so we'll write the registers ourselves */
4446 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4448 /* set or clear MFLCN.PMCF bit depending on configuration */
4449 if (fc_conf->mac_ctrl_frame_fwd != 0)
4450 mflcn |= IXGBE_MFLCN_PMCF;
4452 mflcn &= ~IXGBE_MFLCN_PMCF;
4454 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4455 IXGBE_WRITE_FLUSH(hw);
4460 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4465 * ixgbe_pfc_enable_generic - Enable flow control
4466 * @hw: pointer to hardware structure
4467 * @tc_num: traffic class number
4468 * Enable flow control according to the current settings.
4471 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4474 uint32_t mflcn_reg, fccfg_reg;
4476 uint32_t fcrtl, fcrth;
4480 /* Validate the water mark configuration */
4481 if (!hw->fc.pause_time) {
4482 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4486 /* Low water mark of zero causes XOFF floods */
4487 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4488 /* High/Low water can not be 0 */
4489 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4490 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4491 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4495 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4496 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4497 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4501 /* Negotiate the fc mode to use */
4502 ixgbe_fc_autoneg(hw);
4504 /* Disable any previous flow control settings */
4505 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4506 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4508 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4509 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4511 switch (hw->fc.current_mode) {
4514 * If the count of enabled RX Priority Flow control >1,
4515 * and the TX pause can not be disabled
4518 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4519 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4520 if (reg & IXGBE_FCRTH_FCEN)
4524 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4526 case ixgbe_fc_rx_pause:
4528 * Rx Flow control is enabled and Tx Flow control is
4529 * disabled by software override. Since there really
4530 * isn't a way to advertise that we are capable of RX
4531 * Pause ONLY, we will advertise that we support both
4532 * symmetric and asymmetric Rx PAUSE. Later, we will
4533 * disable the adapter's ability to send PAUSE frames.
4535 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4537 * If the count of enabled RX Priority Flow control >1,
4538 * and the TX pause can not be disabled
4541 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4542 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4543 if (reg & IXGBE_FCRTH_FCEN)
4547 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4549 case ixgbe_fc_tx_pause:
4551 * Tx Flow control is enabled, and Rx Flow control is
4552 * disabled by software override.
4554 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4557 /* Flow control (both Rx and Tx) is enabled by SW override. */
4558 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4559 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4562 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4563 ret_val = IXGBE_ERR_CONFIG;
4567 /* Set 802.3x based flow control settings. */
4568 mflcn_reg |= IXGBE_MFLCN_DPF;
4569 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4570 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4572 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4573 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4574 hw->fc.high_water[tc_num]) {
4575 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4576 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4577 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4579 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4581 * In order to prevent Tx hangs when the internal Tx
4582 * switch is enabled we must set the high water mark
4583 * to the maximum FCRTH value. This allows the Tx
4584 * switch to function even under heavy Rx workloads.
4586 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4588 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4590 /* Configure pause time (2 TCs per register) */
4591 reg = hw->fc.pause_time * 0x00010001;
4592 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4593 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4595 /* Configure flow control refresh threshold value */
4596 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4603 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4605 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4606 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4608 if (hw->mac.type != ixgbe_mac_82598EB) {
4609 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4615 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4618 uint32_t rx_buf_size;
4619 uint32_t max_high_water;
4621 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4622 struct ixgbe_hw *hw =
4623 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4624 struct ixgbe_dcb_config *dcb_config =
4625 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4627 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4634 PMD_INIT_FUNC_TRACE();
4636 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4637 tc_num = map[pfc_conf->priority];
4638 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4639 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4641 * At least reserve one Ethernet frame for watermark
4642 * high_water/low_water in kilo bytes for ixgbe
4644 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4645 if ((pfc_conf->fc.high_water > max_high_water) ||
4646 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4647 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4648 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4652 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4653 hw->fc.pause_time = pfc_conf->fc.pause_time;
4654 hw->fc.send_xon = pfc_conf->fc.send_xon;
4655 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4656 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4658 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4660 /* Not negotiated is not an error case */
4661 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4664 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4669 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4670 struct rte_eth_rss_reta_entry64 *reta_conf,
4673 uint16_t i, sp_reta_size;
4676 uint16_t idx, shift;
4677 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4680 PMD_INIT_FUNC_TRACE();
4682 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4683 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4688 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4689 if (reta_size != sp_reta_size) {
4690 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4691 "(%d) doesn't match the number hardware can supported "
4692 "(%d)", reta_size, sp_reta_size);
4696 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4697 idx = i / RTE_RETA_GROUP_SIZE;
4698 shift = i % RTE_RETA_GROUP_SIZE;
4699 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4703 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4704 if (mask == IXGBE_4_BIT_MASK)
4707 r = IXGBE_READ_REG(hw, reta_reg);
4708 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4709 if (mask & (0x1 << j))
4710 reta |= reta_conf[idx].reta[shift + j] <<
4713 reta |= r & (IXGBE_8_BIT_MASK <<
4716 IXGBE_WRITE_REG(hw, reta_reg, reta);
4723 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4724 struct rte_eth_rss_reta_entry64 *reta_conf,
4727 uint16_t i, sp_reta_size;
4730 uint16_t idx, shift;
4731 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4734 PMD_INIT_FUNC_TRACE();
4735 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4736 if (reta_size != sp_reta_size) {
4737 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4738 "(%d) doesn't match the number hardware can supported "
4739 "(%d)", reta_size, sp_reta_size);
4743 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4744 idx = i / RTE_RETA_GROUP_SIZE;
4745 shift = i % RTE_RETA_GROUP_SIZE;
4746 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4751 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4752 reta = IXGBE_READ_REG(hw, reta_reg);
4753 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4754 if (mask & (0x1 << j))
4755 reta_conf[idx].reta[shift + j] =
4756 ((reta >> (CHAR_BIT * j)) &
4765 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4766 uint32_t index, uint32_t pool)
4768 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4769 uint32_t enable_addr = 1;
4771 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4776 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4780 ixgbe_clear_rar(hw, index);
4784 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4786 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4788 ixgbe_remove_rar(dev, 0);
4790 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4794 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4796 if (strcmp(dev->device->driver->name, drv->driver.name))
4803 is_ixgbe_supported(struct rte_eth_dev *dev)
4805 return is_device_supported(dev, &rte_ixgbe_pmd);
4809 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4813 struct ixgbe_hw *hw;
4814 struct rte_eth_dev_info dev_info;
4815 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4816 struct rte_eth_dev_data *dev_data = dev->data;
4818 ixgbe_dev_info_get(dev, &dev_info);
4820 /* check that mtu is within the allowed range */
4821 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4824 /* If device is started, refuse mtu that requires the support of
4825 * scattered packets when this feature has not been enabled before.
4827 if (dev_data->dev_started && !dev_data->scattered_rx &&
4828 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4829 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
4830 PMD_INIT_LOG(ERR, "Stop port first.");
4834 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4835 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4837 /* switch to jumbo mode if needed */
4838 if (frame_size > ETHER_MAX_LEN) {
4839 dev->data->dev_conf.rxmode.offloads |=
4840 DEV_RX_OFFLOAD_JUMBO_FRAME;
4841 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4843 dev->data->dev_conf.rxmode.offloads &=
4844 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
4845 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4847 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4849 /* update max frame size */
4850 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4852 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4853 maxfrs &= 0x0000FFFF;
4854 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4855 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4861 * Virtual Function operations
4864 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4866 PMD_INIT_FUNC_TRACE();
4868 /* Clear interrupt mask to stop from interrupts being generated */
4869 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4871 IXGBE_WRITE_FLUSH(hw);
4875 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4877 PMD_INIT_FUNC_TRACE();
4879 /* VF enable interrupt autoclean */
4880 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4881 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4882 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4884 IXGBE_WRITE_FLUSH(hw);
4888 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4890 struct rte_eth_conf *conf = &dev->data->dev_conf;
4891 struct ixgbe_adapter *adapter =
4892 (struct ixgbe_adapter *)dev->data->dev_private;
4893 struct rte_eth_dev_info dev_info;
4894 uint64_t rx_offloads;
4896 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4897 dev->data->port_id);
4899 ixgbevf_dev_info_get(dev, &dev_info);
4900 rx_offloads = dev->data->dev_conf.rxmode.offloads;
4901 if ((rx_offloads & dev_info.rx_offload_capa) != rx_offloads) {
4902 PMD_DRV_LOG(ERR, "Some Rx offloads are not supported "
4903 "requested 0x%" PRIx64 " supported 0x%" PRIx64,
4904 rx_offloads, dev_info.rx_offload_capa);
4909 * VF has no ability to enable/disable HW CRC
4910 * Keep the persistent behavior the same as Host PF
4912 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4913 if (!(conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
4914 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4915 conf->rxmode.offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
4918 if (conf->rxmode.offloads & DEV_RX_OFFLOAD_CRC_STRIP) {
4919 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4920 conf->rxmode.offloads &= ~DEV_RX_OFFLOAD_CRC_STRIP;
4925 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4926 * allocation or vector Rx preconditions we will reset it.
4928 adapter->rx_bulk_alloc_allowed = true;
4929 adapter->rx_vec_allowed = true;
4935 ixgbevf_dev_start(struct rte_eth_dev *dev)
4937 struct ixgbe_hw *hw =
4938 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939 uint32_t intr_vector = 0;
4940 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4941 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4945 PMD_INIT_FUNC_TRACE();
4947 err = hw->mac.ops.reset_hw(hw);
4949 PMD_INIT_LOG(ERR, "Unable to reset vf hardware (%d)", err);
4952 hw->mac.get_link_status = true;
4954 /* negotiate mailbox API version to use with the PF. */
4955 ixgbevf_negotiate_api(hw);
4957 ixgbevf_dev_tx_init(dev);
4959 /* This can fail when allocating mbufs for descriptor rings */
4960 err = ixgbevf_dev_rx_init(dev);
4962 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4963 ixgbe_dev_clear_queues(dev);
4968 ixgbevf_set_vfta_all(dev, 1);
4971 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4972 ETH_VLAN_EXTEND_MASK;
4973 err = ixgbevf_vlan_offload_set(dev, mask);
4975 PMD_INIT_LOG(ERR, "Unable to set VLAN offload (%d)", err);
4976 ixgbe_dev_clear_queues(dev);
4980 ixgbevf_dev_rxtx_start(dev);
4982 /* check and configure queue intr-vector mapping */
4983 if (rte_intr_cap_multiple(intr_handle) &&
4984 dev->data->dev_conf.intr_conf.rxq) {
4985 /* According to datasheet, only vector 0/1/2 can be used,
4986 * now only one vector is used for Rx queue
4989 if (rte_intr_efd_enable(intr_handle, intr_vector))
4993 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4994 intr_handle->intr_vec =
4995 rte_zmalloc("intr_vec",
4996 dev->data->nb_rx_queues * sizeof(int), 0);
4997 if (intr_handle->intr_vec == NULL) {
4998 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4999 " intr_vec", dev->data->nb_rx_queues);
5003 ixgbevf_configure_msix(dev);
5005 /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
5006 * is mapped to VFIO vector 0 in eth_ixgbevf_dev_init( ).
5007 * If previous VFIO interrupt mapping setting in eth_ixgbevf_dev_init( )
5008 * is not cleared, it will fail when following rte_intr_enable( ) tries
5009 * to map Rx queue interrupt to other VFIO vectors.
5010 * So clear uio/vfio intr/evevnfd first to avoid failure.
5012 rte_intr_disable(intr_handle);
5014 rte_intr_enable(intr_handle);
5016 /* Re-enable interrupt for VF */
5017 ixgbevf_intr_enable(hw);
5023 ixgbevf_dev_stop(struct rte_eth_dev *dev)
5025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5026 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5027 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5029 PMD_INIT_FUNC_TRACE();
5031 ixgbevf_intr_disable(hw);
5033 hw->adapter_stopped = 1;
5034 ixgbe_stop_adapter(hw);
5037 * Clear what we set, but we still keep shadow_vfta to
5038 * restore after device starts
5040 ixgbevf_set_vfta_all(dev, 0);
5042 /* Clear stored conf */
5043 dev->data->scattered_rx = 0;
5045 ixgbe_dev_clear_queues(dev);
5047 /* Clean datapath event and queue/vec mapping */
5048 rte_intr_efd_disable(intr_handle);
5049 if (intr_handle->intr_vec != NULL) {
5050 rte_free(intr_handle->intr_vec);
5051 intr_handle->intr_vec = NULL;
5056 ixgbevf_dev_close(struct rte_eth_dev *dev)
5058 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5060 PMD_INIT_FUNC_TRACE();
5064 ixgbevf_dev_stop(dev);
5066 ixgbe_dev_free_queues(dev);
5069 * Remove the VF MAC address ro ensure
5070 * that the VF traffic goes to the PF
5071 * after stop, close and detach of the VF
5073 ixgbevf_remove_mac_addr(dev, 0);
5080 ixgbevf_dev_reset(struct rte_eth_dev *dev)
5084 ret = eth_ixgbevf_dev_uninit(dev);
5088 ret = eth_ixgbevf_dev_init(dev);
5093 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
5095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5096 struct ixgbe_vfta *shadow_vfta =
5097 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5098 int i = 0, j = 0, vfta = 0, mask = 1;
5100 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
5101 vfta = shadow_vfta->vfta[i];
5104 for (j = 0; j < 32; j++) {
5106 ixgbe_set_vfta(hw, (i<<5)+j, 0,
5116 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
5118 struct ixgbe_hw *hw =
5119 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5120 struct ixgbe_vfta *shadow_vfta =
5121 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
5122 uint32_t vid_idx = 0;
5123 uint32_t vid_bit = 0;
5126 PMD_INIT_FUNC_TRACE();
5128 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
5129 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
5131 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
5134 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
5135 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
5137 /* Save what we set and retore it after device reset */
5139 shadow_vfta->vfta[vid_idx] |= vid_bit;
5141 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
5147 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
5149 struct ixgbe_hw *hw =
5150 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5153 PMD_INIT_FUNC_TRACE();
5155 if (queue >= hw->mac.max_rx_queues)
5158 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
5160 ctrl |= IXGBE_RXDCTL_VME;
5162 ctrl &= ~IXGBE_RXDCTL_VME;
5163 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
5165 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
5169 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
5171 struct ixgbe_hw *hw =
5172 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5173 struct ixgbe_rx_queue *rxq;
5177 /* VF function only support hw strip feature, others are not support */
5178 if (mask & ETH_VLAN_STRIP_MASK) {
5179 for (i = 0; i < hw->mac.max_rx_queues; i++) {
5180 rxq = dev->data->rx_queues[i];
5181 on = !!(rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP);
5182 ixgbevf_vlan_strip_queue_set(dev, i, on);
5190 ixgbe_vt_check(struct ixgbe_hw *hw)
5194 /* if Virtualization Technology is enabled */
5195 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5196 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5197 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5205 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5207 uint32_t vector = 0;
5209 switch (hw->mac.mc_filter_type) {
5210 case 0: /* use bits [47:36] of the address */
5211 vector = ((uc_addr->addr_bytes[4] >> 4) |
5212 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5214 case 1: /* use bits [46:35] of the address */
5215 vector = ((uc_addr->addr_bytes[4] >> 3) |
5216 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5218 case 2: /* use bits [45:34] of the address */
5219 vector = ((uc_addr->addr_bytes[4] >> 2) |
5220 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5222 case 3: /* use bits [43:32] of the address */
5223 vector = ((uc_addr->addr_bytes[4]) |
5224 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5226 default: /* Invalid mc_filter_type */
5230 /* vector can only be 12-bits or boundary will be exceeded */
5236 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5244 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5245 const uint32_t ixgbe_uta_bit_shift = 5;
5246 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5247 const uint32_t bit1 = 0x1;
5249 struct ixgbe_hw *hw =
5250 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5251 struct ixgbe_uta_info *uta_info =
5252 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5254 /* The UTA table only exists on 82599 hardware and newer */
5255 if (hw->mac.type < ixgbe_mac_82599EB)
5258 vector = ixgbe_uta_vector(hw, mac_addr);
5259 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5260 uta_shift = vector & ixgbe_uta_bit_mask;
5262 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5266 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5268 uta_info->uta_in_use++;
5269 reg_val |= (bit1 << uta_shift);
5270 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5272 uta_info->uta_in_use--;
5273 reg_val &= ~(bit1 << uta_shift);
5274 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5277 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5279 if (uta_info->uta_in_use > 0)
5280 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5281 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5283 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5289 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5292 struct ixgbe_hw *hw =
5293 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5294 struct ixgbe_uta_info *uta_info =
5295 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5297 /* The UTA table only exists on 82599 hardware and newer */
5298 if (hw->mac.type < ixgbe_mac_82599EB)
5302 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5303 uta_info->uta_shadow[i] = ~0;
5304 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5307 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5308 uta_info->uta_shadow[i] = 0;
5309 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5317 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5319 uint32_t new_val = orig_val;
5321 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5322 new_val |= IXGBE_VMOLR_AUPE;
5323 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5324 new_val |= IXGBE_VMOLR_ROMPE;
5325 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5326 new_val |= IXGBE_VMOLR_ROPE;
5327 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5328 new_val |= IXGBE_VMOLR_BAM;
5329 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5330 new_val |= IXGBE_VMOLR_MPE;
5335 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5336 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5337 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5338 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5339 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5340 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5341 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5344 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5345 struct rte_eth_mirror_conf *mirror_conf,
5346 uint8_t rule_id, uint8_t on)
5348 uint32_t mr_ctl, vlvf;
5349 uint32_t mp_lsb = 0;
5350 uint32_t mv_msb = 0;
5351 uint32_t mv_lsb = 0;
5352 uint32_t mp_msb = 0;
5355 uint64_t vlan_mask = 0;
5357 const uint8_t pool_mask_offset = 32;
5358 const uint8_t vlan_mask_offset = 32;
5359 const uint8_t dst_pool_offset = 8;
5360 const uint8_t rule_mr_offset = 4;
5361 const uint8_t mirror_rule_mask = 0x0F;
5363 struct ixgbe_mirror_info *mr_info =
5364 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5365 struct ixgbe_hw *hw =
5366 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5367 uint8_t mirror_type = 0;
5369 if (ixgbe_vt_check(hw) < 0)
5372 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5375 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5376 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5377 mirror_conf->rule_type);
5381 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5382 mirror_type |= IXGBE_MRCTL_VLME;
5383 /* Check if vlan id is valid and find conresponding VLAN ID
5386 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5387 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5388 /* search vlan id related pool vlan filter
5391 reg_index = ixgbe_find_vlvf_slot(
5393 mirror_conf->vlan.vlan_id[i],
5397 vlvf = IXGBE_READ_REG(hw,
5398 IXGBE_VLVF(reg_index));
5399 if ((vlvf & IXGBE_VLVF_VIEN) &&
5400 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5401 mirror_conf->vlan.vlan_id[i]))
5402 vlan_mask |= (1ULL << reg_index);
5409 mv_lsb = vlan_mask & 0xFFFFFFFF;
5410 mv_msb = vlan_mask >> vlan_mask_offset;
5412 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5413 mirror_conf->vlan.vlan_mask;
5414 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5415 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5416 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5417 mirror_conf->vlan.vlan_id[i];
5422 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5423 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5424 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5429 * if enable pool mirror, write related pool mask register,if disable
5430 * pool mirror, clear PFMRVM register
5432 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5433 mirror_type |= IXGBE_MRCTL_VPME;
5435 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5436 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5437 mr_info->mr_conf[rule_id].pool_mask =
5438 mirror_conf->pool_mask;
5443 mr_info->mr_conf[rule_id].pool_mask = 0;
5446 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5447 mirror_type |= IXGBE_MRCTL_UPME;
5448 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5449 mirror_type |= IXGBE_MRCTL_DPME;
5451 /* read mirror control register and recalculate it */
5452 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5455 mr_ctl |= mirror_type;
5456 mr_ctl &= mirror_rule_mask;
5457 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5459 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5462 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5463 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5465 /* write mirrror control register */
5466 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5468 /* write pool mirrror control register */
5469 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5470 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5471 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5474 /* write VLAN mirrror control register */
5475 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5476 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5477 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5485 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5488 uint32_t lsb_val = 0;
5489 uint32_t msb_val = 0;
5490 const uint8_t rule_mr_offset = 4;
5492 struct ixgbe_hw *hw =
5493 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5494 struct ixgbe_mirror_info *mr_info =
5495 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5497 if (ixgbe_vt_check(hw) < 0)
5500 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5503 memset(&mr_info->mr_conf[rule_id], 0,
5504 sizeof(struct rte_eth_mirror_conf));
5506 /* clear PFVMCTL register */
5507 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5509 /* clear pool mask register */
5510 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5511 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5513 /* clear vlan mask register */
5514 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5515 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5521 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5526 struct ixgbe_hw *hw =
5527 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5528 uint32_t vec = IXGBE_MISC_VEC_ID;
5530 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5531 if (rte_intr_allow_others(intr_handle))
5532 vec = IXGBE_RX_VEC_START;
5534 RTE_SET_USED(queue_id);
5535 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5537 rte_intr_enable(intr_handle);
5543 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5546 struct ixgbe_hw *hw =
5547 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5549 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5550 uint32_t vec = IXGBE_MISC_VEC_ID;
5552 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5553 if (rte_intr_allow_others(intr_handle))
5554 vec = IXGBE_RX_VEC_START;
5555 mask &= ~(1 << vec);
5556 RTE_SET_USED(queue_id);
5557 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5563 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5565 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5566 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5568 struct ixgbe_hw *hw =
5569 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5570 struct ixgbe_interrupt *intr =
5571 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5573 if (queue_id < 16) {
5574 ixgbe_disable_intr(hw);
5575 intr->mask |= (1 << queue_id);
5576 ixgbe_enable_intr(dev);
5577 } else if (queue_id < 32) {
5578 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5579 mask &= (1 << queue_id);
5580 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5581 } else if (queue_id < 64) {
5582 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5583 mask &= (1 << (queue_id - 32));
5584 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5586 rte_intr_enable(intr_handle);
5592 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5595 struct ixgbe_hw *hw =
5596 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5597 struct ixgbe_interrupt *intr =
5598 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5600 if (queue_id < 16) {
5601 ixgbe_disable_intr(hw);
5602 intr->mask &= ~(1 << queue_id);
5603 ixgbe_enable_intr(dev);
5604 } else if (queue_id < 32) {
5605 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5606 mask &= ~(1 << queue_id);
5607 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5608 } else if (queue_id < 64) {
5609 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5610 mask &= ~(1 << (queue_id - 32));
5611 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5618 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5619 uint8_t queue, uint8_t msix_vector)
5623 if (direction == -1) {
5625 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5626 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5629 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5631 /* rx or tx cause */
5632 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5633 idx = ((16 * (queue & 1)) + (8 * direction));
5634 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5635 tmp &= ~(0xFF << idx);
5636 tmp |= (msix_vector << idx);
5637 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5642 * set the IVAR registers, mapping interrupt causes to vectors
5644 * pointer to ixgbe_hw struct
5646 * 0 for Rx, 1 for Tx, -1 for other causes
5648 * queue to map the corresponding interrupt to
5650 * the vector to map to the corresponding queue
5653 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5654 uint8_t queue, uint8_t msix_vector)
5658 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5659 if (hw->mac.type == ixgbe_mac_82598EB) {
5660 if (direction == -1)
5662 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5663 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5664 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5665 tmp |= (msix_vector << (8 * (queue & 0x3)));
5666 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5667 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5668 (hw->mac.type == ixgbe_mac_X540) ||
5669 (hw->mac.type == ixgbe_mac_X550)) {
5670 if (direction == -1) {
5672 idx = ((queue & 1) * 8);
5673 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5674 tmp &= ~(0xFF << idx);
5675 tmp |= (msix_vector << idx);
5676 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5678 /* rx or tx causes */
5679 idx = ((16 * (queue & 1)) + (8 * direction));
5680 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5681 tmp &= ~(0xFF << idx);
5682 tmp |= (msix_vector << idx);
5683 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5689 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5691 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5692 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5693 struct ixgbe_hw *hw =
5694 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5697 uint32_t base = IXGBE_MISC_VEC_ID;
5699 /* Configure VF other cause ivar */
5700 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5702 /* won't configure msix register if no mapping is done
5703 * between intr vector and event fd.
5705 if (!rte_intr_dp_is_en(intr_handle))
5708 if (rte_intr_allow_others(intr_handle)) {
5709 base = IXGBE_RX_VEC_START;
5710 vector_idx = IXGBE_RX_VEC_START;
5713 /* Configure all RX queues of VF */
5714 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5715 /* Force all queue use vector 0,
5716 * as IXGBE_VF_MAXMSIVECOTR = 1
5718 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5719 intr_handle->intr_vec[q_idx] = vector_idx;
5720 if (vector_idx < base + intr_handle->nb_efd - 1)
5726 * Sets up the hardware to properly generate MSI-X interrupts
5728 * board private structure
5731 ixgbe_configure_msix(struct rte_eth_dev *dev)
5733 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5734 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5735 struct ixgbe_hw *hw =
5736 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5737 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5738 uint32_t vec = IXGBE_MISC_VEC_ID;
5742 /* won't configure msix register if no mapping is done
5743 * between intr vector and event fd
5745 if (!rte_intr_dp_is_en(intr_handle))
5748 if (rte_intr_allow_others(intr_handle))
5749 vec = base = IXGBE_RX_VEC_START;
5751 /* setup GPIE for MSI-x mode */
5752 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5753 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5754 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5755 /* auto clearing and auto setting corresponding bits in EIMS
5756 * when MSI-X interrupt is triggered
5758 if (hw->mac.type == ixgbe_mac_82598EB) {
5759 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5761 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5762 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5764 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5766 /* Populate the IVAR table and set the ITR values to the
5767 * corresponding register.
5769 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5771 /* by default, 1:1 mapping */
5772 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5773 intr_handle->intr_vec[queue_id] = vec;
5774 if (vec < base + intr_handle->nb_efd - 1)
5778 switch (hw->mac.type) {
5779 case ixgbe_mac_82598EB:
5780 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5783 case ixgbe_mac_82599EB:
5784 case ixgbe_mac_X540:
5785 case ixgbe_mac_X550:
5786 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5791 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5792 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5794 /* set up to autoclear timer, and the vectors */
5795 mask = IXGBE_EIMS_ENABLE_MASK;
5796 mask &= ~(IXGBE_EIMS_OTHER |
5797 IXGBE_EIMS_MAILBOX |
5800 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5804 ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5805 uint16_t queue_idx, uint16_t tx_rate)
5807 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5808 struct rte_eth_rxmode *rxmode;
5809 uint32_t rf_dec, rf_int;
5811 uint16_t link_speed = dev->data->dev_link.link_speed;
5813 if (queue_idx >= hw->mac.max_tx_queues)
5817 /* Calculate the rate factor values to set */
5818 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5819 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5820 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5822 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5823 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5824 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5825 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5830 rxmode = &dev->data->dev_conf.rxmode;
5832 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5833 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5836 if ((rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) &&
5837 (rxmode->max_rx_pkt_len >= IXGBE_MAX_JUMBO_FRAME_SIZE))
5838 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5839 IXGBE_MMW_SIZE_JUMBO_FRAME);
5841 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5842 IXGBE_MMW_SIZE_DEFAULT);
5844 /* Set RTTBCNRC of queue X */
5845 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5846 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5847 IXGBE_WRITE_FLUSH(hw);
5853 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5854 __attribute__((unused)) uint32_t index,
5855 __attribute__((unused)) uint32_t pool)
5857 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5861 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5862 * operation. Trap this case to avoid exhausting the [very limited]
5863 * set of PF resources used to store VF MAC addresses.
5865 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5867 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5869 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5870 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5871 mac_addr->addr_bytes[0],
5872 mac_addr->addr_bytes[1],
5873 mac_addr->addr_bytes[2],
5874 mac_addr->addr_bytes[3],
5875 mac_addr->addr_bytes[4],
5876 mac_addr->addr_bytes[5],
5882 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5884 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5885 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5886 struct ether_addr *mac_addr;
5891 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5892 * not support the deletion of a given MAC address.
5893 * Instead, it imposes to delete all MAC addresses, then to add again
5894 * all MAC addresses with the exception of the one to be deleted.
5896 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5899 * Add again all MAC addresses, with the exception of the deleted one
5900 * and of the permanent MAC address.
5902 for (i = 0, mac_addr = dev->data->mac_addrs;
5903 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5904 /* Skip the deleted MAC address */
5907 /* Skip NULL MAC addresses */
5908 if (is_zero_ether_addr(mac_addr))
5910 /* Skip the permanent MAC address */
5911 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5913 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5916 "Adding again MAC address "
5917 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5919 mac_addr->addr_bytes[0],
5920 mac_addr->addr_bytes[1],
5921 mac_addr->addr_bytes[2],
5922 mac_addr->addr_bytes[3],
5923 mac_addr->addr_bytes[4],
5924 mac_addr->addr_bytes[5],
5930 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5932 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5934 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5938 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5939 struct rte_eth_syn_filter *filter,
5942 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943 struct ixgbe_filter_info *filter_info =
5944 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5948 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5951 syn_info = filter_info->syn_info;
5954 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5956 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5957 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5959 if (filter->hig_pri)
5960 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5962 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5964 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5965 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5967 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5970 filter_info->syn_info = synqf;
5971 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5972 IXGBE_WRITE_FLUSH(hw);
5977 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5978 struct rte_eth_syn_filter *filter)
5980 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5981 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5983 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5984 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5985 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5992 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5993 enum rte_filter_op filter_op,
5996 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5999 MAC_TYPE_FILTER_SUP(hw->mac.type);
6001 if (filter_op == RTE_ETH_FILTER_NOP)
6005 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6010 switch (filter_op) {
6011 case RTE_ETH_FILTER_ADD:
6012 ret = ixgbe_syn_filter_set(dev,
6013 (struct rte_eth_syn_filter *)arg,
6016 case RTE_ETH_FILTER_DELETE:
6017 ret = ixgbe_syn_filter_set(dev,
6018 (struct rte_eth_syn_filter *)arg,
6021 case RTE_ETH_FILTER_GET:
6022 ret = ixgbe_syn_filter_get(dev,
6023 (struct rte_eth_syn_filter *)arg);
6026 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
6035 static inline enum ixgbe_5tuple_protocol
6036 convert_protocol_type(uint8_t protocol_value)
6038 if (protocol_value == IPPROTO_TCP)
6039 return IXGBE_FILTER_PROTOCOL_TCP;
6040 else if (protocol_value == IPPROTO_UDP)
6041 return IXGBE_FILTER_PROTOCOL_UDP;
6042 else if (protocol_value == IPPROTO_SCTP)
6043 return IXGBE_FILTER_PROTOCOL_SCTP;
6045 return IXGBE_FILTER_PROTOCOL_NONE;
6048 /* inject a 5-tuple filter to HW */
6050 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
6051 struct ixgbe_5tuple_filter *filter)
6053 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6055 uint32_t ftqf, sdpqf;
6056 uint32_t l34timir = 0;
6057 uint8_t mask = 0xff;
6061 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
6062 IXGBE_SDPQF_DSTPORT_SHIFT);
6063 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
6065 ftqf = (uint32_t)(filter->filter_info.proto &
6066 IXGBE_FTQF_PROTOCOL_MASK);
6067 ftqf |= (uint32_t)((filter->filter_info.priority &
6068 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
6069 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
6070 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
6071 if (filter->filter_info.dst_ip_mask == 0)
6072 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
6073 if (filter->filter_info.src_port_mask == 0)
6074 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
6075 if (filter->filter_info.dst_port_mask == 0)
6076 mask &= IXGBE_FTQF_DEST_PORT_MASK;
6077 if (filter->filter_info.proto_mask == 0)
6078 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
6079 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
6080 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
6081 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
6083 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
6084 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
6085 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
6086 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
6088 l34timir |= IXGBE_L34T_IMIR_RESERVE;
6089 l34timir |= (uint32_t)(filter->queue <<
6090 IXGBE_L34T_IMIR_QUEUE_SHIFT);
6091 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
6095 * add a 5tuple filter
6098 * dev: Pointer to struct rte_eth_dev.
6099 * index: the index the filter allocates.
6100 * filter: ponter to the filter that will be added.
6101 * rx_queue: the queue id the filter assigned to.
6104 * - On success, zero.
6105 * - On failure, a negative value.
6108 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
6109 struct ixgbe_5tuple_filter *filter)
6111 struct ixgbe_filter_info *filter_info =
6112 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6116 * look for an unused 5tuple filter index,
6117 * and insert the filter to list.
6119 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
6120 idx = i / (sizeof(uint32_t) * NBBY);
6121 shift = i % (sizeof(uint32_t) * NBBY);
6122 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
6123 filter_info->fivetuple_mask[idx] |= 1 << shift;
6125 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
6131 if (i >= IXGBE_MAX_FTQF_FILTERS) {
6132 PMD_DRV_LOG(ERR, "5tuple filters are full.");
6136 ixgbe_inject_5tuple_filter(dev, filter);
6142 * remove a 5tuple filter
6145 * dev: Pointer to struct rte_eth_dev.
6146 * filter: the pointer of the filter will be removed.
6149 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
6150 struct ixgbe_5tuple_filter *filter)
6152 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6153 struct ixgbe_filter_info *filter_info =
6154 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6155 uint16_t index = filter->index;
6157 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
6158 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
6159 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
6162 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
6163 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
6164 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
6165 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
6166 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
6170 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
6172 struct ixgbe_hw *hw;
6173 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
6174 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
6176 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6178 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
6181 /* refuse mtu that requires the support of scattered packets when this
6182 * feature has not been enabled before.
6184 if (!(rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) &&
6185 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
6186 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
6190 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
6191 * request of the version 2.0 of the mailbox API.
6192 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
6193 * of the mailbox API.
6194 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
6195 * prior to 3.11.33 which contains the following change:
6196 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
6198 ixgbevf_rlpml_set_vf(hw, max_frame);
6200 /* update max frame size */
6201 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
6205 static inline struct ixgbe_5tuple_filter *
6206 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
6207 struct ixgbe_5tuple_filter_info *key)
6209 struct ixgbe_5tuple_filter *it;
6211 TAILQ_FOREACH(it, filter_list, entries) {
6212 if (memcmp(key, &it->filter_info,
6213 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6220 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6222 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6223 struct ixgbe_5tuple_filter_info *filter_info)
6225 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6226 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6227 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6230 switch (filter->dst_ip_mask) {
6232 filter_info->dst_ip_mask = 0;
6233 filter_info->dst_ip = filter->dst_ip;
6236 filter_info->dst_ip_mask = 1;
6239 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6243 switch (filter->src_ip_mask) {
6245 filter_info->src_ip_mask = 0;
6246 filter_info->src_ip = filter->src_ip;
6249 filter_info->src_ip_mask = 1;
6252 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6256 switch (filter->dst_port_mask) {
6258 filter_info->dst_port_mask = 0;
6259 filter_info->dst_port = filter->dst_port;
6262 filter_info->dst_port_mask = 1;
6265 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6269 switch (filter->src_port_mask) {
6271 filter_info->src_port_mask = 0;
6272 filter_info->src_port = filter->src_port;
6275 filter_info->src_port_mask = 1;
6278 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6282 switch (filter->proto_mask) {
6284 filter_info->proto_mask = 0;
6285 filter_info->proto =
6286 convert_protocol_type(filter->proto);
6289 filter_info->proto_mask = 1;
6292 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6296 filter_info->priority = (uint8_t)filter->priority;
6301 * add or delete a ntuple filter
6304 * dev: Pointer to struct rte_eth_dev.
6305 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6306 * add: if true, add filter, if false, remove filter
6309 * - On success, zero.
6310 * - On failure, a negative value.
6313 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6314 struct rte_eth_ntuple_filter *ntuple_filter,
6317 struct ixgbe_filter_info *filter_info =
6318 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6319 struct ixgbe_5tuple_filter_info filter_5tuple;
6320 struct ixgbe_5tuple_filter *filter;
6323 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6324 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6328 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6329 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6333 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6335 if (filter != NULL && add) {
6336 PMD_DRV_LOG(ERR, "filter exists.");
6339 if (filter == NULL && !add) {
6340 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6345 filter = rte_zmalloc("ixgbe_5tuple_filter",
6346 sizeof(struct ixgbe_5tuple_filter), 0);
6349 rte_memcpy(&filter->filter_info,
6351 sizeof(struct ixgbe_5tuple_filter_info));
6352 filter->queue = ntuple_filter->queue;
6353 ret = ixgbe_add_5tuple_filter(dev, filter);
6359 ixgbe_remove_5tuple_filter(dev, filter);
6365 * get a ntuple filter
6368 * dev: Pointer to struct rte_eth_dev.
6369 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6372 * - On success, zero.
6373 * - On failure, a negative value.
6376 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6377 struct rte_eth_ntuple_filter *ntuple_filter)
6379 struct ixgbe_filter_info *filter_info =
6380 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6381 struct ixgbe_5tuple_filter_info filter_5tuple;
6382 struct ixgbe_5tuple_filter *filter;
6385 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6386 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6390 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6391 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6395 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6397 if (filter == NULL) {
6398 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6401 ntuple_filter->queue = filter->queue;
6406 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6407 * @dev: pointer to rte_eth_dev structure
6408 * @filter_op:operation will be taken.
6409 * @arg: a pointer to specific structure corresponding to the filter_op
6412 * - On success, zero.
6413 * - On failure, a negative value.
6416 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6417 enum rte_filter_op filter_op,
6420 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6425 if (filter_op == RTE_ETH_FILTER_NOP)
6429 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6434 switch (filter_op) {
6435 case RTE_ETH_FILTER_ADD:
6436 ret = ixgbe_add_del_ntuple_filter(dev,
6437 (struct rte_eth_ntuple_filter *)arg,
6440 case RTE_ETH_FILTER_DELETE:
6441 ret = ixgbe_add_del_ntuple_filter(dev,
6442 (struct rte_eth_ntuple_filter *)arg,
6445 case RTE_ETH_FILTER_GET:
6446 ret = ixgbe_get_ntuple_filter(dev,
6447 (struct rte_eth_ntuple_filter *)arg);
6450 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6458 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6459 struct rte_eth_ethertype_filter *filter,
6462 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6463 struct ixgbe_filter_info *filter_info =
6464 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6468 struct ixgbe_ethertype_filter ethertype_filter;
6470 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6473 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6474 filter->ether_type == ETHER_TYPE_IPv6) {
6475 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6476 " ethertype filter.", filter->ether_type);
6480 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6481 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6484 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6485 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6489 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6490 if (ret >= 0 && add) {
6491 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6492 filter->ether_type);
6495 if (ret < 0 && !add) {
6496 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6497 filter->ether_type);
6502 etqf = IXGBE_ETQF_FILTER_EN;
6503 etqf |= (uint32_t)filter->ether_type;
6504 etqs |= (uint32_t)((filter->queue <<
6505 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6506 IXGBE_ETQS_RX_QUEUE);
6507 etqs |= IXGBE_ETQS_QUEUE_EN;
6509 ethertype_filter.ethertype = filter->ether_type;
6510 ethertype_filter.etqf = etqf;
6511 ethertype_filter.etqs = etqs;
6512 ethertype_filter.conf = FALSE;
6513 ret = ixgbe_ethertype_filter_insert(filter_info,
6516 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6520 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6524 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6525 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6526 IXGBE_WRITE_FLUSH(hw);
6532 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6533 struct rte_eth_ethertype_filter *filter)
6535 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6536 struct ixgbe_filter_info *filter_info =
6537 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6538 uint32_t etqf, etqs;
6541 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6543 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6544 filter->ether_type);
6548 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6549 if (etqf & IXGBE_ETQF_FILTER_EN) {
6550 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6551 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6553 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6554 IXGBE_ETQS_RX_QUEUE_SHIFT;
6561 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6562 * @dev: pointer to rte_eth_dev structure
6563 * @filter_op:operation will be taken.
6564 * @arg: a pointer to specific structure corresponding to the filter_op
6567 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6568 enum rte_filter_op filter_op,
6571 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6574 MAC_TYPE_FILTER_SUP(hw->mac.type);
6576 if (filter_op == RTE_ETH_FILTER_NOP)
6580 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6585 switch (filter_op) {
6586 case RTE_ETH_FILTER_ADD:
6587 ret = ixgbe_add_del_ethertype_filter(dev,
6588 (struct rte_eth_ethertype_filter *)arg,
6591 case RTE_ETH_FILTER_DELETE:
6592 ret = ixgbe_add_del_ethertype_filter(dev,
6593 (struct rte_eth_ethertype_filter *)arg,
6596 case RTE_ETH_FILTER_GET:
6597 ret = ixgbe_get_ethertype_filter(dev,
6598 (struct rte_eth_ethertype_filter *)arg);
6601 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6609 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6610 enum rte_filter_type filter_type,
6611 enum rte_filter_op filter_op,
6616 switch (filter_type) {
6617 case RTE_ETH_FILTER_NTUPLE:
6618 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6620 case RTE_ETH_FILTER_ETHERTYPE:
6621 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6623 case RTE_ETH_FILTER_SYN:
6624 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6626 case RTE_ETH_FILTER_FDIR:
6627 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6629 case RTE_ETH_FILTER_L2_TUNNEL:
6630 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6632 case RTE_ETH_FILTER_GENERIC:
6633 if (filter_op != RTE_ETH_FILTER_GET)
6635 *(const void **)arg = &ixgbe_flow_ops;
6638 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6648 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6649 u8 **mc_addr_ptr, u32 *vmdq)
6654 mc_addr = *mc_addr_ptr;
6655 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6660 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6661 struct ether_addr *mc_addr_set,
6662 uint32_t nb_mc_addr)
6664 struct ixgbe_hw *hw;
6667 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6668 mc_addr_list = (u8 *)mc_addr_set;
6669 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6670 ixgbe_dev_addr_list_itr, TRUE);
6674 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6677 uint64_t systime_cycles;
6679 switch (hw->mac.type) {
6680 case ixgbe_mac_X550:
6681 case ixgbe_mac_X550EM_x:
6682 case ixgbe_mac_X550EM_a:
6683 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6684 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6685 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6689 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6690 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6694 return systime_cycles;
6698 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6700 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6701 uint64_t rx_tstamp_cycles;
6703 switch (hw->mac.type) {
6704 case ixgbe_mac_X550:
6705 case ixgbe_mac_X550EM_x:
6706 case ixgbe_mac_X550EM_a:
6707 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6708 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6709 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6713 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6714 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6715 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6719 return rx_tstamp_cycles;
6723 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6725 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6726 uint64_t tx_tstamp_cycles;
6728 switch (hw->mac.type) {
6729 case ixgbe_mac_X550:
6730 case ixgbe_mac_X550EM_x:
6731 case ixgbe_mac_X550EM_a:
6732 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6733 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6734 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6738 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6739 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6740 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6744 return tx_tstamp_cycles;
6748 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6750 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6751 struct ixgbe_adapter *adapter =
6752 (struct ixgbe_adapter *)dev->data->dev_private;
6753 struct rte_eth_link link;
6754 uint32_t incval = 0;
6757 /* Get current link speed. */
6758 ixgbe_dev_link_update(dev, 1);
6759 rte_eth_linkstatus_get(dev, &link);
6761 switch (link.link_speed) {
6762 case ETH_SPEED_NUM_100M:
6763 incval = IXGBE_INCVAL_100;
6764 shift = IXGBE_INCVAL_SHIFT_100;
6766 case ETH_SPEED_NUM_1G:
6767 incval = IXGBE_INCVAL_1GB;
6768 shift = IXGBE_INCVAL_SHIFT_1GB;
6770 case ETH_SPEED_NUM_10G:
6772 incval = IXGBE_INCVAL_10GB;
6773 shift = IXGBE_INCVAL_SHIFT_10GB;
6777 switch (hw->mac.type) {
6778 case ixgbe_mac_X550:
6779 case ixgbe_mac_X550EM_x:
6780 case ixgbe_mac_X550EM_a:
6781 /* Independent of link speed. */
6783 /* Cycles read will be interpreted as ns. */
6786 case ixgbe_mac_X540:
6787 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6789 case ixgbe_mac_82599EB:
6790 incval >>= IXGBE_INCVAL_SHIFT_82599;
6791 shift -= IXGBE_INCVAL_SHIFT_82599;
6792 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6793 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6796 /* Not supported. */
6800 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6801 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6802 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6804 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6805 adapter->systime_tc.cc_shift = shift;
6806 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6808 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6809 adapter->rx_tstamp_tc.cc_shift = shift;
6810 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6812 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6813 adapter->tx_tstamp_tc.cc_shift = shift;
6814 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6818 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6820 struct ixgbe_adapter *adapter =
6821 (struct ixgbe_adapter *)dev->data->dev_private;
6823 adapter->systime_tc.nsec += delta;
6824 adapter->rx_tstamp_tc.nsec += delta;
6825 adapter->tx_tstamp_tc.nsec += delta;
6831 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6834 struct ixgbe_adapter *adapter =
6835 (struct ixgbe_adapter *)dev->data->dev_private;
6837 ns = rte_timespec_to_ns(ts);
6838 /* Set the timecounters to a new value. */
6839 adapter->systime_tc.nsec = ns;
6840 adapter->rx_tstamp_tc.nsec = ns;
6841 adapter->tx_tstamp_tc.nsec = ns;
6847 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6849 uint64_t ns, systime_cycles;
6850 struct ixgbe_adapter *adapter =
6851 (struct ixgbe_adapter *)dev->data->dev_private;
6853 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6854 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6855 *ts = rte_ns_to_timespec(ns);
6861 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867 /* Stop the timesync system time. */
6868 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6869 /* Reset the timesync system time value. */
6870 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6871 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6873 /* Enable system time for platforms where it isn't on by default. */
6874 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6875 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6876 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6878 ixgbe_start_timecounters(dev);
6880 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6881 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6883 IXGBE_ETQF_FILTER_EN |
6886 /* Enable timestamping of received PTP packets. */
6887 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6888 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6889 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6891 /* Enable timestamping of transmitted PTP packets. */
6892 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6893 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6894 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6896 IXGBE_WRITE_FLUSH(hw);
6902 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6904 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6907 /* Disable timestamping of transmitted PTP packets. */
6908 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6909 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6910 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6912 /* Disable timestamping of received PTP packets. */
6913 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6914 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6915 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6917 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6918 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6920 /* Stop incrementating the System Time registers. */
6921 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6927 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6928 struct timespec *timestamp,
6929 uint32_t flags __rte_unused)
6931 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6932 struct ixgbe_adapter *adapter =
6933 (struct ixgbe_adapter *)dev->data->dev_private;
6934 uint32_t tsync_rxctl;
6935 uint64_t rx_tstamp_cycles;
6938 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6939 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6942 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6943 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6944 *timestamp = rte_ns_to_timespec(ns);
6950 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6951 struct timespec *timestamp)
6953 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6954 struct ixgbe_adapter *adapter =
6955 (struct ixgbe_adapter *)dev->data->dev_private;
6956 uint32_t tsync_txctl;
6957 uint64_t tx_tstamp_cycles;
6960 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6961 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6964 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6965 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6966 *timestamp = rte_ns_to_timespec(ns);
6972 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6974 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6977 const struct reg_info *reg_group;
6978 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6979 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6981 while ((reg_group = reg_set[g_ind++]))
6982 count += ixgbe_regs_group_count(reg_group);
6988 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6992 const struct reg_info *reg_group;
6994 while ((reg_group = ixgbevf_regs[g_ind++]))
6995 count += ixgbe_regs_group_count(reg_group);
7001 ixgbe_get_regs(struct rte_eth_dev *dev,
7002 struct rte_dev_reg_info *regs)
7004 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7005 uint32_t *data = regs->data;
7008 const struct reg_info *reg_group;
7009 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
7010 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
7013 regs->length = ixgbe_get_reg_length(dev);
7014 regs->width = sizeof(uint32_t);
7018 /* Support only full register dump */
7019 if ((regs->length == 0) ||
7020 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
7021 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7023 while ((reg_group = reg_set[g_ind++]))
7024 count += ixgbe_read_regs_group(dev, &data[count],
7033 ixgbevf_get_regs(struct rte_eth_dev *dev,
7034 struct rte_dev_reg_info *regs)
7036 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7037 uint32_t *data = regs->data;
7040 const struct reg_info *reg_group;
7043 regs->length = ixgbevf_get_reg_length(dev);
7044 regs->width = sizeof(uint32_t);
7048 /* Support only full register dump */
7049 if ((regs->length == 0) ||
7050 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
7051 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
7053 while ((reg_group = ixgbevf_regs[g_ind++]))
7054 count += ixgbe_read_regs_group(dev, &data[count],
7063 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
7065 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7067 /* Return unit is byte count */
7068 return hw->eeprom.word_size * 2;
7072 ixgbe_get_eeprom(struct rte_eth_dev *dev,
7073 struct rte_dev_eeprom_info *in_eeprom)
7075 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7076 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7077 uint16_t *data = in_eeprom->data;
7080 first = in_eeprom->offset >> 1;
7081 length = in_eeprom->length >> 1;
7082 if ((first > hw->eeprom.word_size) ||
7083 ((first + length) > hw->eeprom.word_size))
7086 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7088 return eeprom->ops.read_buffer(hw, first, length, data);
7092 ixgbe_set_eeprom(struct rte_eth_dev *dev,
7093 struct rte_dev_eeprom_info *in_eeprom)
7095 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7096 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
7097 uint16_t *data = in_eeprom->data;
7100 first = in_eeprom->offset >> 1;
7101 length = in_eeprom->length >> 1;
7102 if ((first > hw->eeprom.word_size) ||
7103 ((first + length) > hw->eeprom.word_size))
7106 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
7108 return eeprom->ops.write_buffer(hw, first, length, data);
7112 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
7114 case ixgbe_mac_X550:
7115 case ixgbe_mac_X550EM_x:
7116 case ixgbe_mac_X550EM_a:
7117 return ETH_RSS_RETA_SIZE_512;
7118 case ixgbe_mac_X550_vf:
7119 case ixgbe_mac_X550EM_x_vf:
7120 case ixgbe_mac_X550EM_a_vf:
7121 return ETH_RSS_RETA_SIZE_64;
7123 return ETH_RSS_RETA_SIZE_128;
7128 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
7130 case ixgbe_mac_X550:
7131 case ixgbe_mac_X550EM_x:
7132 case ixgbe_mac_X550EM_a:
7133 if (reta_idx < ETH_RSS_RETA_SIZE_128)
7134 return IXGBE_RETA(reta_idx >> 2);
7136 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
7137 case ixgbe_mac_X550_vf:
7138 case ixgbe_mac_X550EM_x_vf:
7139 case ixgbe_mac_X550EM_a_vf:
7140 return IXGBE_VFRETA(reta_idx >> 2);
7142 return IXGBE_RETA(reta_idx >> 2);
7147 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
7149 case ixgbe_mac_X550_vf:
7150 case ixgbe_mac_X550EM_x_vf:
7151 case ixgbe_mac_X550EM_a_vf:
7152 return IXGBE_VFMRQC;
7159 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
7161 case ixgbe_mac_X550_vf:
7162 case ixgbe_mac_X550EM_x_vf:
7163 case ixgbe_mac_X550EM_a_vf:
7164 return IXGBE_VFRSSRK(i);
7166 return IXGBE_RSSRK(i);
7171 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
7173 case ixgbe_mac_82599_vf:
7174 case ixgbe_mac_X540_vf:
7182 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
7183 struct rte_eth_dcb_info *dcb_info)
7185 struct ixgbe_dcb_config *dcb_config =
7186 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
7187 struct ixgbe_dcb_tc_config *tc;
7188 struct rte_eth_dcb_tc_queue_mapping *tc_queue;
7192 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
7193 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
7195 dcb_info->nb_tcs = 1;
7197 tc_queue = &dcb_info->tc_queue;
7198 nb_tcs = dcb_info->nb_tcs;
7200 if (dcb_config->vt_mode) { /* vt is enabled*/
7201 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
7202 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
7203 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7204 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
7205 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
7206 for (j = 0; j < nb_tcs; j++) {
7207 tc_queue->tc_rxq[0][j].base = j;
7208 tc_queue->tc_rxq[0][j].nb_queue = 1;
7209 tc_queue->tc_txq[0][j].base = j;
7210 tc_queue->tc_txq[0][j].nb_queue = 1;
7213 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
7214 for (j = 0; j < nb_tcs; j++) {
7215 tc_queue->tc_rxq[i][j].base =
7217 tc_queue->tc_rxq[i][j].nb_queue = 1;
7218 tc_queue->tc_txq[i][j].base =
7220 tc_queue->tc_txq[i][j].nb_queue = 1;
7224 } else { /* vt is disabled*/
7225 struct rte_eth_dcb_rx_conf *rx_conf =
7226 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7227 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7228 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7229 if (dcb_info->nb_tcs == ETH_4_TCS) {
7230 for (i = 0; i < dcb_info->nb_tcs; i++) {
7231 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7232 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7234 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7235 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7236 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7237 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7238 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7239 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7240 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7241 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7242 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7243 for (i = 0; i < dcb_info->nb_tcs; i++) {
7244 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7245 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7247 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7248 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7249 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7250 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7251 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7252 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7253 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7254 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7255 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7256 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7257 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7258 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7259 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7260 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7261 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7262 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7265 for (i = 0; i < dcb_info->nb_tcs; i++) {
7266 tc = &dcb_config->tc_config[i];
7267 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7272 /* Update e-tag ether type */
7274 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7275 uint16_t ether_type)
7277 uint32_t etag_etype;
7279 if (hw->mac.type != ixgbe_mac_X550 &&
7280 hw->mac.type != ixgbe_mac_X550EM_x &&
7281 hw->mac.type != ixgbe_mac_X550EM_a) {
7285 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7286 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7287 etag_etype |= ether_type;
7288 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7289 IXGBE_WRITE_FLUSH(hw);
7294 /* Config l2 tunnel ether type */
7296 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7297 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7300 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7301 struct ixgbe_l2_tn_info *l2_tn_info =
7302 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7304 if (l2_tunnel == NULL)
7307 switch (l2_tunnel->l2_tunnel_type) {
7308 case RTE_L2_TUNNEL_TYPE_E_TAG:
7309 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7310 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7313 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7321 /* Enable e-tag tunnel */
7323 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7325 uint32_t etag_etype;
7327 if (hw->mac.type != ixgbe_mac_X550 &&
7328 hw->mac.type != ixgbe_mac_X550EM_x &&
7329 hw->mac.type != ixgbe_mac_X550EM_a) {
7333 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7334 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7335 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7336 IXGBE_WRITE_FLUSH(hw);
7341 /* Enable l2 tunnel */
7343 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7344 enum rte_eth_tunnel_type l2_tunnel_type)
7347 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7348 struct ixgbe_l2_tn_info *l2_tn_info =
7349 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7351 switch (l2_tunnel_type) {
7352 case RTE_L2_TUNNEL_TYPE_E_TAG:
7353 l2_tn_info->e_tag_en = TRUE;
7354 ret = ixgbe_e_tag_enable(hw);
7357 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7365 /* Disable e-tag tunnel */
7367 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7369 uint32_t etag_etype;
7371 if (hw->mac.type != ixgbe_mac_X550 &&
7372 hw->mac.type != ixgbe_mac_X550EM_x &&
7373 hw->mac.type != ixgbe_mac_X550EM_a) {
7377 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7378 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7379 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7380 IXGBE_WRITE_FLUSH(hw);
7385 /* Disable l2 tunnel */
7387 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7388 enum rte_eth_tunnel_type l2_tunnel_type)
7391 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7392 struct ixgbe_l2_tn_info *l2_tn_info =
7393 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7395 switch (l2_tunnel_type) {
7396 case RTE_L2_TUNNEL_TYPE_E_TAG:
7397 l2_tn_info->e_tag_en = FALSE;
7398 ret = ixgbe_e_tag_disable(hw);
7401 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7410 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7411 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7414 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7415 uint32_t i, rar_entries;
7416 uint32_t rar_low, rar_high;
7418 if (hw->mac.type != ixgbe_mac_X550 &&
7419 hw->mac.type != ixgbe_mac_X550EM_x &&
7420 hw->mac.type != ixgbe_mac_X550EM_a) {
7424 rar_entries = ixgbe_get_num_rx_addrs(hw);
7426 for (i = 1; i < rar_entries; i++) {
7427 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7428 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7429 if ((rar_high & IXGBE_RAH_AV) &&
7430 (rar_high & IXGBE_RAH_ADTYPE) &&
7431 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7432 l2_tunnel->tunnel_id)) {
7433 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7434 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7436 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7446 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7447 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7450 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7451 uint32_t i, rar_entries;
7452 uint32_t rar_low, rar_high;
7454 if (hw->mac.type != ixgbe_mac_X550 &&
7455 hw->mac.type != ixgbe_mac_X550EM_x &&
7456 hw->mac.type != ixgbe_mac_X550EM_a) {
7460 /* One entry for one tunnel. Try to remove potential existing entry. */
7461 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7463 rar_entries = ixgbe_get_num_rx_addrs(hw);
7465 for (i = 1; i < rar_entries; i++) {
7466 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7467 if (rar_high & IXGBE_RAH_AV) {
7470 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7471 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7472 rar_low = l2_tunnel->tunnel_id;
7474 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7475 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7481 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7482 " Please remove a rule before adding a new one.");
7486 static inline struct ixgbe_l2_tn_filter *
7487 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7488 struct ixgbe_l2_tn_key *key)
7492 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7496 return l2_tn_info->hash_map[ret];
7500 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7501 struct ixgbe_l2_tn_filter *l2_tn_filter)
7505 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7506 &l2_tn_filter->key);
7510 "Failed to insert L2 tunnel filter"
7511 " to hash table %d!",
7516 l2_tn_info->hash_map[ret] = l2_tn_filter;
7518 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7524 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7525 struct ixgbe_l2_tn_key *key)
7528 struct ixgbe_l2_tn_filter *l2_tn_filter;
7530 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7534 "No such L2 tunnel filter to delete %d!",
7539 l2_tn_filter = l2_tn_info->hash_map[ret];
7540 l2_tn_info->hash_map[ret] = NULL;
7542 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7543 rte_free(l2_tn_filter);
7548 /* Add l2 tunnel filter */
7550 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7551 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7555 struct ixgbe_l2_tn_info *l2_tn_info =
7556 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7557 struct ixgbe_l2_tn_key key;
7558 struct ixgbe_l2_tn_filter *node;
7561 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7562 key.tn_id = l2_tunnel->tunnel_id;
7564 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7568 "The L2 tunnel filter already exists!");
7572 node = rte_zmalloc("ixgbe_l2_tn",
7573 sizeof(struct ixgbe_l2_tn_filter),
7578 rte_memcpy(&node->key,
7580 sizeof(struct ixgbe_l2_tn_key));
7581 node->pool = l2_tunnel->pool;
7582 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7589 switch (l2_tunnel->l2_tunnel_type) {
7590 case RTE_L2_TUNNEL_TYPE_E_TAG:
7591 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7594 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7599 if ((!restore) && (ret < 0))
7600 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7605 /* Delete l2 tunnel filter */
7607 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7608 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7611 struct ixgbe_l2_tn_info *l2_tn_info =
7612 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7613 struct ixgbe_l2_tn_key key;
7615 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7616 key.tn_id = l2_tunnel->tunnel_id;
7617 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7621 switch (l2_tunnel->l2_tunnel_type) {
7622 case RTE_L2_TUNNEL_TYPE_E_TAG:
7623 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7626 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7635 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7636 * @dev: pointer to rte_eth_dev structure
7637 * @filter_op:operation will be taken.
7638 * @arg: a pointer to specific structure corresponding to the filter_op
7641 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7642 enum rte_filter_op filter_op,
7647 if (filter_op == RTE_ETH_FILTER_NOP)
7651 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7656 switch (filter_op) {
7657 case RTE_ETH_FILTER_ADD:
7658 ret = ixgbe_dev_l2_tunnel_filter_add
7660 (struct rte_eth_l2_tunnel_conf *)arg,
7663 case RTE_ETH_FILTER_DELETE:
7664 ret = ixgbe_dev_l2_tunnel_filter_del
7666 (struct rte_eth_l2_tunnel_conf *)arg);
7669 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7677 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7681 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7683 if (hw->mac.type != ixgbe_mac_X550 &&
7684 hw->mac.type != ixgbe_mac_X550EM_x &&
7685 hw->mac.type != ixgbe_mac_X550EM_a) {
7689 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7690 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7692 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7693 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7698 /* Enable l2 tunnel forwarding */
7700 ixgbe_dev_l2_tunnel_forwarding_enable
7701 (struct rte_eth_dev *dev,
7702 enum rte_eth_tunnel_type l2_tunnel_type)
7704 struct ixgbe_l2_tn_info *l2_tn_info =
7705 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7708 switch (l2_tunnel_type) {
7709 case RTE_L2_TUNNEL_TYPE_E_TAG:
7710 l2_tn_info->e_tag_fwd_en = TRUE;
7711 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7714 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7722 /* Disable l2 tunnel forwarding */
7724 ixgbe_dev_l2_tunnel_forwarding_disable
7725 (struct rte_eth_dev *dev,
7726 enum rte_eth_tunnel_type l2_tunnel_type)
7728 struct ixgbe_l2_tn_info *l2_tn_info =
7729 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7732 switch (l2_tunnel_type) {
7733 case RTE_L2_TUNNEL_TYPE_E_TAG:
7734 l2_tn_info->e_tag_fwd_en = FALSE;
7735 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7738 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7747 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7748 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7753 uint32_t vmtir, vmvir;
7754 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7756 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7758 "VF id %u should be less than %u",
7764 if (hw->mac.type != ixgbe_mac_X550 &&
7765 hw->mac.type != ixgbe_mac_X550EM_x &&
7766 hw->mac.type != ixgbe_mac_X550EM_a) {
7771 vmtir = l2_tunnel->tunnel_id;
7775 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7777 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7778 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7780 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7781 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7786 /* Enable l2 tunnel tag insertion */
7788 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7789 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7793 switch (l2_tunnel->l2_tunnel_type) {
7794 case RTE_L2_TUNNEL_TYPE_E_TAG:
7795 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7798 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7806 /* Disable l2 tunnel tag insertion */
7808 ixgbe_dev_l2_tunnel_insertion_disable
7809 (struct rte_eth_dev *dev,
7810 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7814 switch (l2_tunnel->l2_tunnel_type) {
7815 case RTE_L2_TUNNEL_TYPE_E_TAG:
7816 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7819 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7828 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7833 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7835 if (hw->mac.type != ixgbe_mac_X550 &&
7836 hw->mac.type != ixgbe_mac_X550EM_x &&
7837 hw->mac.type != ixgbe_mac_X550EM_a) {
7841 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7843 qde |= IXGBE_QDE_STRIP_TAG;
7845 qde &= ~IXGBE_QDE_STRIP_TAG;
7846 qde &= ~IXGBE_QDE_READ;
7847 qde |= IXGBE_QDE_WRITE;
7848 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7853 /* Enable l2 tunnel tag stripping */
7855 ixgbe_dev_l2_tunnel_stripping_enable
7856 (struct rte_eth_dev *dev,
7857 enum rte_eth_tunnel_type l2_tunnel_type)
7861 switch (l2_tunnel_type) {
7862 case RTE_L2_TUNNEL_TYPE_E_TAG:
7863 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7866 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7874 /* Disable l2 tunnel tag stripping */
7876 ixgbe_dev_l2_tunnel_stripping_disable
7877 (struct rte_eth_dev *dev,
7878 enum rte_eth_tunnel_type l2_tunnel_type)
7882 switch (l2_tunnel_type) {
7883 case RTE_L2_TUNNEL_TYPE_E_TAG:
7884 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7887 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7895 /* Enable/disable l2 tunnel offload functions */
7897 ixgbe_dev_l2_tunnel_offload_set
7898 (struct rte_eth_dev *dev,
7899 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7905 if (l2_tunnel == NULL)
7909 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7911 ret = ixgbe_dev_l2_tunnel_enable(
7913 l2_tunnel->l2_tunnel_type);
7915 ret = ixgbe_dev_l2_tunnel_disable(
7917 l2_tunnel->l2_tunnel_type);
7920 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7922 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7926 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7931 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7933 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7935 l2_tunnel->l2_tunnel_type);
7937 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7939 l2_tunnel->l2_tunnel_type);
7942 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7944 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7946 l2_tunnel->l2_tunnel_type);
7948 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7950 l2_tunnel->l2_tunnel_type);
7957 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7960 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7961 IXGBE_WRITE_FLUSH(hw);
7966 /* There's only one register for VxLAN UDP port.
7967 * So, we cannot add several ports. Will update it.
7970 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7974 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7978 return ixgbe_update_vxlan_port(hw, port);
7981 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7982 * UDP port, it must have a value.
7983 * So, will reset it to the original value 0.
7986 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7991 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7993 if (cur_port != port) {
7994 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7998 return ixgbe_update_vxlan_port(hw, 0);
8001 /* Add UDP tunneling port */
8003 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8004 struct rte_eth_udp_tunnel *udp_tunnel)
8007 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009 if (hw->mac.type != ixgbe_mac_X550 &&
8010 hw->mac.type != ixgbe_mac_X550EM_x &&
8011 hw->mac.type != ixgbe_mac_X550EM_a) {
8015 if (udp_tunnel == NULL)
8018 switch (udp_tunnel->prot_type) {
8019 case RTE_TUNNEL_TYPE_VXLAN:
8020 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
8023 case RTE_TUNNEL_TYPE_GENEVE:
8024 case RTE_TUNNEL_TYPE_TEREDO:
8025 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8030 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8038 /* Remove UDP tunneling port */
8040 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8041 struct rte_eth_udp_tunnel *udp_tunnel)
8044 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046 if (hw->mac.type != ixgbe_mac_X550 &&
8047 hw->mac.type != ixgbe_mac_X550EM_x &&
8048 hw->mac.type != ixgbe_mac_X550EM_a) {
8052 if (udp_tunnel == NULL)
8055 switch (udp_tunnel->prot_type) {
8056 case RTE_TUNNEL_TYPE_VXLAN:
8057 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
8059 case RTE_TUNNEL_TYPE_GENEVE:
8060 case RTE_TUNNEL_TYPE_TEREDO:
8061 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8065 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8074 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
8076 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8078 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
8082 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
8084 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8086 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
8089 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
8091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8094 /* peek the message first */
8095 in_msg = IXGBE_READ_REG(hw, IXGBE_VFMBMEM);
8097 /* PF reset VF event */
8098 if (in_msg == IXGBE_PF_CONTROL_MSG) {
8099 /* dummy mbx read to ack pf */
8100 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
8102 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
8108 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
8111 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8112 struct ixgbe_interrupt *intr =
8113 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8114 ixgbevf_intr_disable(hw);
8116 /* read-on-clear nic registers here */
8117 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
8120 /* only one misc vector supported - mailbox */
8121 eicr &= IXGBE_VTEICR_MASK;
8122 if (eicr == IXGBE_MISC_VEC_ID)
8123 intr->flags |= IXGBE_FLAG_MAILBOX;
8129 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
8131 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8132 struct ixgbe_interrupt *intr =
8133 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
8135 if (intr->flags & IXGBE_FLAG_MAILBOX) {
8136 ixgbevf_mbx_process(dev);
8137 intr->flags &= ~IXGBE_FLAG_MAILBOX;
8140 ixgbevf_intr_enable(hw);
8146 ixgbevf_dev_interrupt_handler(void *param)
8148 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
8150 ixgbevf_dev_interrupt_get_status(dev);
8151 ixgbevf_dev_interrupt_action(dev);
8155 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
8156 * @hw: pointer to hardware structure
8158 * Stops the transmit data path and waits for the HW to internally empty
8159 * the Tx security block
8161 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
8163 #define IXGBE_MAX_SECTX_POLL 40
8168 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8169 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
8170 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8171 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
8172 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
8173 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
8175 /* Use interrupt-safe sleep just in case */
8179 /* For informational purposes only */
8180 if (i >= IXGBE_MAX_SECTX_POLL)
8181 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
8182 "path fully disabled. Continuing with init.");
8184 return IXGBE_SUCCESS;
8188 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
8189 * @hw: pointer to hardware structure
8191 * Enables the transmit data path.
8193 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
8197 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
8198 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
8199 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
8200 IXGBE_WRITE_FLUSH(hw);
8202 return IXGBE_SUCCESS;
8205 /* restore n-tuple filter */
8207 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
8209 struct ixgbe_filter_info *filter_info =
8210 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8211 struct ixgbe_5tuple_filter *node;
8213 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
8214 ixgbe_inject_5tuple_filter(dev, node);
8218 /* restore ethernet type filter */
8220 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
8222 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8223 struct ixgbe_filter_info *filter_info =
8224 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8227 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8228 if (filter_info->ethertype_mask & (1 << i)) {
8229 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8230 filter_info->ethertype_filters[i].etqf);
8231 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8232 filter_info->ethertype_filters[i].etqs);
8233 IXGBE_WRITE_FLUSH(hw);
8238 /* restore SYN filter */
8240 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8242 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8243 struct ixgbe_filter_info *filter_info =
8244 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8247 synqf = filter_info->syn_info;
8249 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8250 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8251 IXGBE_WRITE_FLUSH(hw);
8255 /* restore L2 tunnel filter */
8257 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8259 struct ixgbe_l2_tn_info *l2_tn_info =
8260 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8261 struct ixgbe_l2_tn_filter *node;
8262 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8264 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8265 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8266 l2_tn_conf.tunnel_id = node->key.tn_id;
8267 l2_tn_conf.pool = node->pool;
8268 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8272 /* restore rss filter */
8274 ixgbe_rss_filter_restore(struct rte_eth_dev *dev)
8276 struct ixgbe_filter_info *filter_info =
8277 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8279 if (filter_info->rss_info.num)
8280 ixgbe_config_rss_filter(dev,
8281 &filter_info->rss_info, TRUE);
8285 ixgbe_filter_restore(struct rte_eth_dev *dev)
8287 ixgbe_ntuple_filter_restore(dev);
8288 ixgbe_ethertype_filter_restore(dev);
8289 ixgbe_syn_filter_restore(dev);
8290 ixgbe_fdir_filter_restore(dev);
8291 ixgbe_l2_tn_filter_restore(dev);
8292 ixgbe_rss_filter_restore(dev);
8298 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8300 struct ixgbe_l2_tn_info *l2_tn_info =
8301 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8302 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8304 if (l2_tn_info->e_tag_en)
8305 (void)ixgbe_e_tag_enable(hw);
8307 if (l2_tn_info->e_tag_fwd_en)
8308 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8310 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8313 /* remove all the n-tuple filters */
8315 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8317 struct ixgbe_filter_info *filter_info =
8318 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8319 struct ixgbe_5tuple_filter *p_5tuple;
8321 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8322 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8325 /* remove all the ether type filters */
8327 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8329 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8330 struct ixgbe_filter_info *filter_info =
8331 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8334 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8335 if (filter_info->ethertype_mask & (1 << i) &&
8336 !filter_info->ethertype_filters[i].conf) {
8337 (void)ixgbe_ethertype_filter_remove(filter_info,
8339 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8340 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8341 IXGBE_WRITE_FLUSH(hw);
8346 /* remove the SYN filter */
8348 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8350 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8351 struct ixgbe_filter_info *filter_info =
8352 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8354 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8355 filter_info->syn_info = 0;
8357 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8358 IXGBE_WRITE_FLUSH(hw);
8362 /* remove all the L2 tunnel filters */
8364 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8366 struct ixgbe_l2_tn_info *l2_tn_info =
8367 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8368 struct ixgbe_l2_tn_filter *l2_tn_filter;
8369 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8372 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8373 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8374 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8375 l2_tn_conf.pool = l2_tn_filter->pool;
8376 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8384 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8385 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8386 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8387 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8388 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8389 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");
8391 RTE_INIT(ixgbe_init_log);
8393 ixgbe_init_log(void)
8395 ixgbe_logtype_init = rte_log_register("pmd.net.ixgbe.init");
8396 if (ixgbe_logtype_init >= 0)
8397 rte_log_set_level(ixgbe_logtype_init, RTE_LOG_NOTICE);
8398 ixgbe_logtype_driver = rte_log_register("pmd.net.ixgbe.driver");
8399 if (ixgbe_logtype_driver >= 0)
8400 rte_log_set_level(ixgbe_logtype_driver, RTE_LOG_NOTICE);