4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
43 #include <rte_byteorder.h>
44 #include <rte_common.h>
45 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
64 #include <rte_hash_crc.h>
66 #include "ixgbe_logs.h"
67 #include "base/ixgbe_api.h"
68 #include "base/ixgbe_vf.h"
69 #include "base/ixgbe_common.h"
70 #include "ixgbe_ethdev.h"
71 #include "ixgbe_bypass.h"
72 #include "ixgbe_rxtx.h"
73 #include "base/ixgbe_type.h"
74 #include "base/ixgbe_phy.h"
75 #include "ixgbe_regs.h"
78 * High threshold controlling when to start sending XOFF frames. Must be at
79 * least 8 bytes less than receive packet buffer size. This value is in units
82 #define IXGBE_FC_HI 0x80
85 * Low threshold controlling when to start sending XON frames. This value is
86 * in units of 1024 bytes.
88 #define IXGBE_FC_LO 0x40
90 /* Default minimum inter-interrupt interval for EITR configuration */
91 #define IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT 0x79E
93 /* Timer value included in XOFF frames. */
94 #define IXGBE_FC_PAUSE 0x680
96 #define IXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
97 #define IXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
98 #define IXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
100 #define IXGBE_MMW_SIZE_DEFAULT 0x4
101 #define IXGBE_MMW_SIZE_JUMBO_FRAME 0x14
102 #define IXGBE_MAX_RING_DESC 4096 /* replicate define from rxtx */
105 * Default values for RX/TX configuration
107 #define IXGBE_DEFAULT_RX_FREE_THRESH 32
108 #define IXGBE_DEFAULT_RX_PTHRESH 8
109 #define IXGBE_DEFAULT_RX_HTHRESH 8
110 #define IXGBE_DEFAULT_RX_WTHRESH 0
112 #define IXGBE_DEFAULT_TX_FREE_THRESH 32
113 #define IXGBE_DEFAULT_TX_PTHRESH 32
114 #define IXGBE_DEFAULT_TX_HTHRESH 0
115 #define IXGBE_DEFAULT_TX_WTHRESH 0
116 #define IXGBE_DEFAULT_TX_RSBIT_THRESH 32
118 /* Bit shift and mask */
119 #define IXGBE_4_BIT_WIDTH (CHAR_BIT / 2)
120 #define IXGBE_4_BIT_MASK RTE_LEN2MASK(IXGBE_4_BIT_WIDTH, uint8_t)
121 #define IXGBE_8_BIT_WIDTH CHAR_BIT
122 #define IXGBE_8_BIT_MASK UINT8_MAX
124 #define IXGBEVF_PMD_NAME "rte_ixgbevf_pmd" /* PMD name */
126 #define IXGBE_QUEUE_STAT_COUNTERS (sizeof(hw_stats->qprc) / sizeof(hw_stats->qprc[0]))
128 #define IXGBE_HKEY_MAX_INDEX 10
130 /* Additional timesync values. */
131 #define NSEC_PER_SEC 1000000000L
132 #define IXGBE_INCVAL_10GB 0x66666666
133 #define IXGBE_INCVAL_1GB 0x40000000
134 #define IXGBE_INCVAL_100 0x50000000
135 #define IXGBE_INCVAL_SHIFT_10GB 28
136 #define IXGBE_INCVAL_SHIFT_1GB 24
137 #define IXGBE_INCVAL_SHIFT_100 21
138 #define IXGBE_INCVAL_SHIFT_82599 7
139 #define IXGBE_INCPER_SHIFT_82599 24
141 #define IXGBE_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 #define IXGBE_VT_CTL_POOLING_MODE_MASK 0x00030000
144 #define IXGBE_VT_CTL_POOLING_MODE_ETAG 0x00010000
145 #define DEFAULT_ETAG_ETYPE 0x893f
146 #define IXGBE_ETAG_ETYPE 0x00005084
147 #define IXGBE_ETAG_ETYPE_MASK 0x0000ffff
148 #define IXGBE_ETAG_ETYPE_VALID 0x80000000
149 #define IXGBE_RAH_ADTYPE 0x40000000
150 #define IXGBE_RAL_ETAG_FILTER_MASK 0x00003fff
151 #define IXGBE_VMVIR_TAGA_MASK 0x18000000
152 #define IXGBE_VMVIR_TAGA_ETAG_INSERT 0x08000000
153 #define IXGBE_VMTIR(_i) (0x00017000 + ((_i) * 4)) /* 64 of these (0-63) */
154 #define IXGBE_QDE_STRIP_TAG 0x00000004
155 #define IXGBE_VTEICR_MASK 0x07
157 #define IXGBE_EXVET_VET_EXT_SHIFT 16
158 #define IXGBE_DMATXCTL_VT_MASK 0xFFFF0000
160 static int eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev);
161 static int eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev);
162 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
163 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
164 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
165 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
166 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev);
167 static int ixgbe_dev_configure(struct rte_eth_dev *dev);
168 static int ixgbe_dev_start(struct rte_eth_dev *dev);
169 static void ixgbe_dev_stop(struct rte_eth_dev *dev);
170 static int ixgbe_dev_set_link_up(struct rte_eth_dev *dev);
171 static int ixgbe_dev_set_link_down(struct rte_eth_dev *dev);
172 static void ixgbe_dev_close(struct rte_eth_dev *dev);
173 static void ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev);
174 static void ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev);
175 static void ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev);
176 static void ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev);
177 static int ixgbe_dev_link_update(struct rte_eth_dev *dev,
178 int wait_to_complete);
179 static void ixgbe_dev_stats_get(struct rte_eth_dev *dev,
180 struct rte_eth_stats *stats);
181 static int ixgbe_dev_xstats_get(struct rte_eth_dev *dev,
182 struct rte_eth_xstat *xstats, unsigned n);
183 static int ixgbevf_dev_xstats_get(struct rte_eth_dev *dev,
184 struct rte_eth_xstat *xstats, unsigned n);
186 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
187 uint64_t *values, unsigned int n);
188 static void ixgbe_dev_stats_reset(struct rte_eth_dev *dev);
189 static void ixgbe_dev_xstats_reset(struct rte_eth_dev *dev);
190 static int ixgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
191 struct rte_eth_xstat_name *xstats_names,
193 static int ixgbevf_dev_xstats_get_names(struct rte_eth_dev *dev,
194 struct rte_eth_xstat_name *xstats_names, unsigned limit);
195 static int ixgbe_dev_xstats_get_names_by_id(
196 struct rte_eth_dev *dev,
197 struct rte_eth_xstat_name *xstats_names,
200 static int ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
204 static int ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
206 static void ixgbe_dev_info_get(struct rte_eth_dev *dev,
207 struct rte_eth_dev_info *dev_info);
208 static const uint32_t *ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev);
209 static void ixgbevf_dev_info_get(struct rte_eth_dev *dev,
210 struct rte_eth_dev_info *dev_info);
211 static int ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
213 static int ixgbe_vlan_filter_set(struct rte_eth_dev *dev,
214 uint16_t vlan_id, int on);
215 static int ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
216 enum rte_vlan_type vlan_type,
218 static void ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev,
219 uint16_t queue, bool on);
220 static void ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue,
222 static void ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask);
223 static void ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
224 static void ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue);
225 static void ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev);
226 static void ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev);
228 static int ixgbe_dev_led_on(struct rte_eth_dev *dev);
229 static int ixgbe_dev_led_off(struct rte_eth_dev *dev);
230 static int ixgbe_flow_ctrl_get(struct rte_eth_dev *dev,
231 struct rte_eth_fc_conf *fc_conf);
232 static int ixgbe_flow_ctrl_set(struct rte_eth_dev *dev,
233 struct rte_eth_fc_conf *fc_conf);
234 static int ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
235 struct rte_eth_pfc_conf *pfc_conf);
236 static int ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
237 struct rte_eth_rss_reta_entry64 *reta_conf,
239 static int ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
240 struct rte_eth_rss_reta_entry64 *reta_conf,
242 static void ixgbe_dev_link_status_print(struct rte_eth_dev *dev);
243 static int ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev);
244 static int ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
245 static int ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
246 static int ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
247 static int ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
248 struct rte_intr_handle *handle);
249 static void ixgbe_dev_interrupt_handler(void *param);
250 static void ixgbe_dev_interrupt_delayed_handler(void *param);
251 static int ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
252 uint32_t index, uint32_t pool);
253 static void ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index);
254 static void ixgbe_set_default_mac_addr(struct rte_eth_dev *dev,
255 struct ether_addr *mac_addr);
256 static void ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config);
257 static bool is_device_supported(struct rte_eth_dev *dev,
258 struct rte_pci_driver *drv);
260 /* For Virtual Function support */
261 static int eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev);
262 static int eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev);
263 static int ixgbevf_dev_configure(struct rte_eth_dev *dev);
264 static int ixgbevf_dev_start(struct rte_eth_dev *dev);
265 static void ixgbevf_dev_stop(struct rte_eth_dev *dev);
266 static void ixgbevf_dev_close(struct rte_eth_dev *dev);
267 static void ixgbevf_intr_disable(struct ixgbe_hw *hw);
268 static void ixgbevf_intr_enable(struct ixgbe_hw *hw);
269 static void ixgbevf_dev_stats_get(struct rte_eth_dev *dev,
270 struct rte_eth_stats *stats);
271 static void ixgbevf_dev_stats_reset(struct rte_eth_dev *dev);
272 static int ixgbevf_vlan_filter_set(struct rte_eth_dev *dev,
273 uint16_t vlan_id, int on);
274 static void ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev,
275 uint16_t queue, int on);
276 static void ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
277 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on);
278 static int ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
280 static int ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
282 static void ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
283 uint8_t queue, uint8_t msix_vector);
284 static void ixgbevf_configure_msix(struct rte_eth_dev *dev);
285 static void ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev);
286 static void ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev);
288 /* For Eth VMDQ APIs support */
289 static int ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct
290 ether_addr * mac_addr, uint8_t on);
291 static int ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on);
292 static int ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
293 struct rte_eth_mirror_conf *mirror_conf,
294 uint8_t rule_id, uint8_t on);
295 static int ixgbe_mirror_rule_reset(struct rte_eth_dev *dev,
297 static int ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
299 static int ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
301 static void ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
302 uint8_t queue, uint8_t msix_vector);
303 static void ixgbe_configure_msix(struct rte_eth_dev *dev);
305 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
306 uint16_t queue_idx, uint16_t tx_rate);
308 static int ixgbevf_add_mac_addr(struct rte_eth_dev *dev,
309 struct ether_addr *mac_addr,
310 uint32_t index, uint32_t pool);
311 static void ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index);
312 static void ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev,
313 struct ether_addr *mac_addr);
314 static int ixgbe_syn_filter_get(struct rte_eth_dev *dev,
315 struct rte_eth_syn_filter *filter);
316 static int ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
317 enum rte_filter_op filter_op,
319 static int ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
320 struct ixgbe_5tuple_filter *filter);
321 static void ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
322 struct ixgbe_5tuple_filter *filter);
323 static int ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
324 enum rte_filter_op filter_op,
326 static int ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
327 struct rte_eth_ntuple_filter *filter);
328 static int ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
329 enum rte_filter_op filter_op,
331 static int ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
332 struct rte_eth_ethertype_filter *filter);
333 static int ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
334 enum rte_filter_type filter_type,
335 enum rte_filter_op filter_op,
337 static int ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
339 static int ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
340 struct ether_addr *mc_addr_set,
341 uint32_t nb_mc_addr);
342 static int ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
343 struct rte_eth_dcb_info *dcb_info);
345 static int ixgbe_get_reg_length(struct rte_eth_dev *dev);
346 static int ixgbe_get_regs(struct rte_eth_dev *dev,
347 struct rte_dev_reg_info *regs);
348 static int ixgbe_get_eeprom_length(struct rte_eth_dev *dev);
349 static int ixgbe_get_eeprom(struct rte_eth_dev *dev,
350 struct rte_dev_eeprom_info *eeprom);
351 static int ixgbe_set_eeprom(struct rte_eth_dev *dev,
352 struct rte_dev_eeprom_info *eeprom);
354 static int ixgbevf_get_reg_length(struct rte_eth_dev *dev);
355 static int ixgbevf_get_regs(struct rte_eth_dev *dev,
356 struct rte_dev_reg_info *regs);
358 static int ixgbe_timesync_enable(struct rte_eth_dev *dev);
359 static int ixgbe_timesync_disable(struct rte_eth_dev *dev);
360 static int ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
361 struct timespec *timestamp,
363 static int ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp);
365 static int ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
366 static int ixgbe_timesync_read_time(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static int ixgbe_timesync_write_time(struct rte_eth_dev *dev,
369 const struct timespec *timestamp);
370 static void ixgbevf_dev_interrupt_handler(void *param);
372 static int ixgbe_dev_l2_tunnel_eth_type_conf
373 (struct rte_eth_dev *dev, struct rte_eth_l2_tunnel_conf *l2_tunnel);
374 static int ixgbe_dev_l2_tunnel_offload_set
375 (struct rte_eth_dev *dev,
376 struct rte_eth_l2_tunnel_conf *l2_tunnel,
379 static int ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
380 enum rte_filter_op filter_op,
383 static int ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int ixgbe_filter_restore(struct rte_eth_dev *dev);
388 static void ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
391 * Define VF Stats MACRO for Non "cleared on read" register
393 #define UPDATE_VF_STAT(reg, last, cur) \
395 uint32_t latest = IXGBE_READ_REG(hw, reg); \
396 cur += (latest - last) & UINT_MAX; \
400 #define UPDATE_VF_STAT_36BIT(lsb, msb, last, cur) \
402 u64 new_lsb = IXGBE_READ_REG(hw, lsb); \
403 u64 new_msb = IXGBE_READ_REG(hw, msb); \
404 u64 latest = ((new_msb << 32) | new_lsb); \
405 cur += (0x1000000000LL + latest - last) & 0xFFFFFFFFFLL; \
409 #define IXGBE_SET_HWSTRIP(h, q) do {\
410 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
411 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
412 (h)->bitmap[idx] |= 1 << bit;\
415 #define IXGBE_CLEAR_HWSTRIP(h, q) do {\
416 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
417 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
418 (h)->bitmap[idx] &= ~(1 << bit);\
421 #define IXGBE_GET_HWSTRIP(h, q, r) do {\
422 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
423 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
424 (r) = (h)->bitmap[idx] >> bit & 1;\
428 * The set of PCI devices this driver supports
430 static const struct rte_pci_id pci_id_ixgbe_map[] = {
431 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598) },
432 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_BX) },
433 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_DUAL_PORT) },
434 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AF_SINGLE_PORT) },
435 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT) },
436 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598AT2) },
437 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_SFP_LOM) },
438 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_CX4) },
439 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_CX4_DUAL_PORT) },
440 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_DA_DUAL_PORT) },
441 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) },
442 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82598EB_XF_LR) },
443 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4) },
444 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KX4_MEZZ) },
445 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_KR) },
446 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_COMBO_BACKPLANE) },
447 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) },
448 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_CX4) },
449 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP) },
450 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_SFP) },
451 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_RNDC) },
452 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_560FLR) },
453 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_SUBDEV_ID_82599_ECNA_DP) },
454 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BACKPLANE_FCOE) },
455 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE) },
456 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_EM) },
457 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2) },
458 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP) },
459 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_QSFP_SF_QP) },
460 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP) },
461 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_XAUI_LOM) },
462 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_T3_LOM) },
463 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_LS) },
464 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T) },
465 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1) },
466 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_SFP) },
467 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_10G_T) },
468 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_1G_T) },
469 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T) },
470 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550T1) },
471 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR) },
472 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_KR_L) },
473 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP_N) },
474 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII) },
475 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SGMII_L) },
476 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_10G_T) },
477 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP) },
478 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_QSFP_N) },
479 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_SFP) },
480 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T) },
481 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_1G_T_L) },
482 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KX4) },
483 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_KR) },
484 #ifdef RTE_LIBRTE_IXGBE_BYPASS
485 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_BYPASS) },
487 { .vendor_id = 0, /* sentinel */ },
491 * The set of PCI devices this driver supports (for 82599 VF)
493 static const struct rte_pci_id pci_id_ixgbevf_map[] = {
494 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF) },
495 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_VF_HV) },
496 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF) },
497 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540_VF_HV) },
498 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF_HV) },
499 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550_VF) },
500 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF) },
501 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_A_VF_HV) },
502 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF) },
503 { RTE_PCI_DEVICE(IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X550EM_X_VF_HV) },
504 { .vendor_id = 0, /* sentinel */ },
507 static const struct rte_eth_desc_lim rx_desc_lim = {
508 .nb_max = IXGBE_MAX_RING_DESC,
509 .nb_min = IXGBE_MIN_RING_DESC,
510 .nb_align = IXGBE_RXD_ALIGN,
513 static const struct rte_eth_desc_lim tx_desc_lim = {
514 .nb_max = IXGBE_MAX_RING_DESC,
515 .nb_min = IXGBE_MIN_RING_DESC,
516 .nb_align = IXGBE_TXD_ALIGN,
517 .nb_seg_max = IXGBE_TX_MAX_SEG,
518 .nb_mtu_seg_max = IXGBE_TX_MAX_SEG,
521 static const struct eth_dev_ops ixgbe_eth_dev_ops = {
522 .dev_configure = ixgbe_dev_configure,
523 .dev_start = ixgbe_dev_start,
524 .dev_stop = ixgbe_dev_stop,
525 .dev_set_link_up = ixgbe_dev_set_link_up,
526 .dev_set_link_down = ixgbe_dev_set_link_down,
527 .dev_close = ixgbe_dev_close,
528 .promiscuous_enable = ixgbe_dev_promiscuous_enable,
529 .promiscuous_disable = ixgbe_dev_promiscuous_disable,
530 .allmulticast_enable = ixgbe_dev_allmulticast_enable,
531 .allmulticast_disable = ixgbe_dev_allmulticast_disable,
532 .link_update = ixgbe_dev_link_update,
533 .stats_get = ixgbe_dev_stats_get,
534 .xstats_get = ixgbe_dev_xstats_get,
535 .xstats_get_by_id = ixgbe_dev_xstats_get_by_id,
536 .stats_reset = ixgbe_dev_stats_reset,
537 .xstats_reset = ixgbe_dev_xstats_reset,
538 .xstats_get_names = ixgbe_dev_xstats_get_names,
539 .xstats_get_names_by_id = ixgbe_dev_xstats_get_names_by_id,
540 .queue_stats_mapping_set = ixgbe_dev_queue_stats_mapping_set,
541 .fw_version_get = ixgbe_fw_version_get,
542 .dev_infos_get = ixgbe_dev_info_get,
543 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
544 .mtu_set = ixgbe_dev_mtu_set,
545 .vlan_filter_set = ixgbe_vlan_filter_set,
546 .vlan_tpid_set = ixgbe_vlan_tpid_set,
547 .vlan_offload_set = ixgbe_vlan_offload_set,
548 .vlan_strip_queue_set = ixgbe_vlan_strip_queue_set,
549 .rx_queue_start = ixgbe_dev_rx_queue_start,
550 .rx_queue_stop = ixgbe_dev_rx_queue_stop,
551 .tx_queue_start = ixgbe_dev_tx_queue_start,
552 .tx_queue_stop = ixgbe_dev_tx_queue_stop,
553 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
554 .rx_queue_intr_enable = ixgbe_dev_rx_queue_intr_enable,
555 .rx_queue_intr_disable = ixgbe_dev_rx_queue_intr_disable,
556 .rx_queue_release = ixgbe_dev_rx_queue_release,
557 .rx_queue_count = ixgbe_dev_rx_queue_count,
558 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
559 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
560 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
561 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
562 .tx_queue_release = ixgbe_dev_tx_queue_release,
563 .dev_led_on = ixgbe_dev_led_on,
564 .dev_led_off = ixgbe_dev_led_off,
565 .flow_ctrl_get = ixgbe_flow_ctrl_get,
566 .flow_ctrl_set = ixgbe_flow_ctrl_set,
567 .priority_flow_ctrl_set = ixgbe_priority_flow_ctrl_set,
568 .mac_addr_add = ixgbe_add_rar,
569 .mac_addr_remove = ixgbe_remove_rar,
570 .mac_addr_set = ixgbe_set_default_mac_addr,
571 .uc_hash_table_set = ixgbe_uc_hash_table_set,
572 .uc_all_hash_table_set = ixgbe_uc_all_hash_table_set,
573 .mirror_rule_set = ixgbe_mirror_rule_set,
574 .mirror_rule_reset = ixgbe_mirror_rule_reset,
575 .set_queue_rate_limit = ixgbe_set_queue_rate_limit,
576 .reta_update = ixgbe_dev_rss_reta_update,
577 .reta_query = ixgbe_dev_rss_reta_query,
578 .rss_hash_update = ixgbe_dev_rss_hash_update,
579 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
580 .filter_ctrl = ixgbe_dev_filter_ctrl,
581 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
582 .rxq_info_get = ixgbe_rxq_info_get,
583 .txq_info_get = ixgbe_txq_info_get,
584 .timesync_enable = ixgbe_timesync_enable,
585 .timesync_disable = ixgbe_timesync_disable,
586 .timesync_read_rx_timestamp = ixgbe_timesync_read_rx_timestamp,
587 .timesync_read_tx_timestamp = ixgbe_timesync_read_tx_timestamp,
588 .get_reg = ixgbe_get_regs,
589 .get_eeprom_length = ixgbe_get_eeprom_length,
590 .get_eeprom = ixgbe_get_eeprom,
591 .set_eeprom = ixgbe_set_eeprom,
592 .get_dcb_info = ixgbe_dev_get_dcb_info,
593 .timesync_adjust_time = ixgbe_timesync_adjust_time,
594 .timesync_read_time = ixgbe_timesync_read_time,
595 .timesync_write_time = ixgbe_timesync_write_time,
596 .l2_tunnel_eth_type_conf = ixgbe_dev_l2_tunnel_eth_type_conf,
597 .l2_tunnel_offload_set = ixgbe_dev_l2_tunnel_offload_set,
598 .udp_tunnel_port_add = ixgbe_dev_udp_tunnel_port_add,
599 .udp_tunnel_port_del = ixgbe_dev_udp_tunnel_port_del,
603 * dev_ops for virtual function, bare necessities for basic vf
604 * operation have been implemented
606 static const struct eth_dev_ops ixgbevf_eth_dev_ops = {
607 .dev_configure = ixgbevf_dev_configure,
608 .dev_start = ixgbevf_dev_start,
609 .dev_stop = ixgbevf_dev_stop,
610 .link_update = ixgbe_dev_link_update,
611 .stats_get = ixgbevf_dev_stats_get,
612 .xstats_get = ixgbevf_dev_xstats_get,
613 .stats_reset = ixgbevf_dev_stats_reset,
614 .xstats_reset = ixgbevf_dev_stats_reset,
615 .xstats_get_names = ixgbevf_dev_xstats_get_names,
616 .dev_close = ixgbevf_dev_close,
617 .allmulticast_enable = ixgbevf_dev_allmulticast_enable,
618 .allmulticast_disable = ixgbevf_dev_allmulticast_disable,
619 .dev_infos_get = ixgbevf_dev_info_get,
620 .dev_supported_ptypes_get = ixgbe_dev_supported_ptypes_get,
621 .mtu_set = ixgbevf_dev_set_mtu,
622 .vlan_filter_set = ixgbevf_vlan_filter_set,
623 .vlan_strip_queue_set = ixgbevf_vlan_strip_queue_set,
624 .vlan_offload_set = ixgbevf_vlan_offload_set,
625 .rx_queue_setup = ixgbe_dev_rx_queue_setup,
626 .rx_queue_release = ixgbe_dev_rx_queue_release,
627 .rx_descriptor_done = ixgbe_dev_rx_descriptor_done,
628 .rx_descriptor_status = ixgbe_dev_rx_descriptor_status,
629 .tx_descriptor_status = ixgbe_dev_tx_descriptor_status,
630 .tx_queue_setup = ixgbe_dev_tx_queue_setup,
631 .tx_queue_release = ixgbe_dev_tx_queue_release,
632 .rx_queue_intr_enable = ixgbevf_dev_rx_queue_intr_enable,
633 .rx_queue_intr_disable = ixgbevf_dev_rx_queue_intr_disable,
634 .mac_addr_add = ixgbevf_add_mac_addr,
635 .mac_addr_remove = ixgbevf_remove_mac_addr,
636 .set_mc_addr_list = ixgbe_dev_set_mc_addr_list,
637 .rxq_info_get = ixgbe_rxq_info_get,
638 .txq_info_get = ixgbe_txq_info_get,
639 .mac_addr_set = ixgbevf_set_default_mac_addr,
640 .get_reg = ixgbevf_get_regs,
641 .reta_update = ixgbe_dev_rss_reta_update,
642 .reta_query = ixgbe_dev_rss_reta_query,
643 .rss_hash_update = ixgbe_dev_rss_hash_update,
644 .rss_hash_conf_get = ixgbe_dev_rss_hash_conf_get,
647 /* store statistics names and its offset in stats structure */
648 struct rte_ixgbe_xstats_name_off {
649 char name[RTE_ETH_XSTATS_NAME_SIZE];
653 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_stats_strings[] = {
654 {"rx_crc_errors", offsetof(struct ixgbe_hw_stats, crcerrs)},
655 {"rx_illegal_byte_errors", offsetof(struct ixgbe_hw_stats, illerrc)},
656 {"rx_error_bytes", offsetof(struct ixgbe_hw_stats, errbc)},
657 {"mac_local_errors", offsetof(struct ixgbe_hw_stats, mlfc)},
658 {"mac_remote_errors", offsetof(struct ixgbe_hw_stats, mrfc)},
659 {"rx_length_errors", offsetof(struct ixgbe_hw_stats, rlec)},
660 {"tx_xon_packets", offsetof(struct ixgbe_hw_stats, lxontxc)},
661 {"rx_xon_packets", offsetof(struct ixgbe_hw_stats, lxonrxc)},
662 {"tx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxofftxc)},
663 {"rx_xoff_packets", offsetof(struct ixgbe_hw_stats, lxoffrxc)},
664 {"rx_size_64_packets", offsetof(struct ixgbe_hw_stats, prc64)},
665 {"rx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, prc127)},
666 {"rx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, prc255)},
667 {"rx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, prc511)},
668 {"rx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
670 {"rx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
672 {"rx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bprc)},
673 {"rx_multicast_packets", offsetof(struct ixgbe_hw_stats, mprc)},
674 {"rx_fragment_errors", offsetof(struct ixgbe_hw_stats, rfc)},
675 {"rx_undersize_errors", offsetof(struct ixgbe_hw_stats, ruc)},
676 {"rx_oversize_errors", offsetof(struct ixgbe_hw_stats, roc)},
677 {"rx_jabber_errors", offsetof(struct ixgbe_hw_stats, rjc)},
678 {"rx_management_packets", offsetof(struct ixgbe_hw_stats, mngprc)},
679 {"rx_management_dropped", offsetof(struct ixgbe_hw_stats, mngpdc)},
680 {"tx_management_packets", offsetof(struct ixgbe_hw_stats, mngptc)},
681 {"rx_total_packets", offsetof(struct ixgbe_hw_stats, tpr)},
682 {"rx_total_bytes", offsetof(struct ixgbe_hw_stats, tor)},
683 {"tx_total_packets", offsetof(struct ixgbe_hw_stats, tpt)},
684 {"tx_size_64_packets", offsetof(struct ixgbe_hw_stats, ptc64)},
685 {"tx_size_65_to_127_packets", offsetof(struct ixgbe_hw_stats, ptc127)},
686 {"tx_size_128_to_255_packets", offsetof(struct ixgbe_hw_stats, ptc255)},
687 {"tx_size_256_to_511_packets", offsetof(struct ixgbe_hw_stats, ptc511)},
688 {"tx_size_512_to_1023_packets", offsetof(struct ixgbe_hw_stats,
690 {"tx_size_1024_to_max_packets", offsetof(struct ixgbe_hw_stats,
692 {"tx_multicast_packets", offsetof(struct ixgbe_hw_stats, mptc)},
693 {"tx_broadcast_packets", offsetof(struct ixgbe_hw_stats, bptc)},
694 {"rx_mac_short_packet_dropped", offsetof(struct ixgbe_hw_stats, mspdc)},
695 {"rx_l3_l4_xsum_error", offsetof(struct ixgbe_hw_stats, xec)},
697 {"flow_director_added_filters", offsetof(struct ixgbe_hw_stats,
699 {"flow_director_removed_filters", offsetof(struct ixgbe_hw_stats,
701 {"flow_director_filter_add_errors", offsetof(struct ixgbe_hw_stats,
703 {"flow_director_filter_remove_errors", offsetof(struct ixgbe_hw_stats,
705 {"flow_director_matched_filters", offsetof(struct ixgbe_hw_stats,
707 {"flow_director_missed_filters", offsetof(struct ixgbe_hw_stats,
710 {"rx_fcoe_crc_errors", offsetof(struct ixgbe_hw_stats, fccrc)},
711 {"rx_fcoe_dropped", offsetof(struct ixgbe_hw_stats, fcoerpdc)},
712 {"rx_fcoe_mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats,
714 {"rx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeprc)},
715 {"tx_fcoe_packets", offsetof(struct ixgbe_hw_stats, fcoeptc)},
716 {"rx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwrc)},
717 {"tx_fcoe_bytes", offsetof(struct ixgbe_hw_stats, fcoedwtc)},
718 {"rx_fcoe_no_direct_data_placement", offsetof(struct ixgbe_hw_stats,
720 {"rx_fcoe_no_direct_data_placement_ext_buff",
721 offsetof(struct ixgbe_hw_stats, fcoe_noddp_ext_buff)},
723 {"tx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
725 {"rx_flow_control_xon_packets", offsetof(struct ixgbe_hw_stats,
727 {"tx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
729 {"rx_flow_control_xoff_packets", offsetof(struct ixgbe_hw_stats,
731 {"rx_total_missed_packets", offsetof(struct ixgbe_hw_stats, mpctotal)},
734 #define IXGBE_NB_HW_STATS (sizeof(rte_ixgbe_stats_strings) / \
735 sizeof(rte_ixgbe_stats_strings[0]))
737 /* MACsec statistics */
738 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_macsec_strings[] = {
739 {"out_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
741 {"out_pkts_encrypted", offsetof(struct ixgbe_macsec_stats,
742 out_pkts_encrypted)},
743 {"out_pkts_protected", offsetof(struct ixgbe_macsec_stats,
744 out_pkts_protected)},
745 {"out_octets_encrypted", offsetof(struct ixgbe_macsec_stats,
746 out_octets_encrypted)},
747 {"out_octets_protected", offsetof(struct ixgbe_macsec_stats,
748 out_octets_protected)},
749 {"in_pkts_untagged", offsetof(struct ixgbe_macsec_stats,
751 {"in_pkts_badtag", offsetof(struct ixgbe_macsec_stats,
753 {"in_pkts_nosci", offsetof(struct ixgbe_macsec_stats,
755 {"in_pkts_unknownsci", offsetof(struct ixgbe_macsec_stats,
756 in_pkts_unknownsci)},
757 {"in_octets_decrypted", offsetof(struct ixgbe_macsec_stats,
758 in_octets_decrypted)},
759 {"in_octets_validated", offsetof(struct ixgbe_macsec_stats,
760 in_octets_validated)},
761 {"in_pkts_unchecked", offsetof(struct ixgbe_macsec_stats,
763 {"in_pkts_delayed", offsetof(struct ixgbe_macsec_stats,
765 {"in_pkts_late", offsetof(struct ixgbe_macsec_stats,
767 {"in_pkts_ok", offsetof(struct ixgbe_macsec_stats,
769 {"in_pkts_invalid", offsetof(struct ixgbe_macsec_stats,
771 {"in_pkts_notvalid", offsetof(struct ixgbe_macsec_stats,
773 {"in_pkts_unusedsa", offsetof(struct ixgbe_macsec_stats,
775 {"in_pkts_notusingsa", offsetof(struct ixgbe_macsec_stats,
776 in_pkts_notusingsa)},
779 #define IXGBE_NB_MACSEC_STATS (sizeof(rte_ixgbe_macsec_strings) / \
780 sizeof(rte_ixgbe_macsec_strings[0]))
782 /* Per-queue statistics */
783 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_rxq_strings[] = {
784 {"mbuf_allocation_errors", offsetof(struct ixgbe_hw_stats, rnbc)},
785 {"dropped", offsetof(struct ixgbe_hw_stats, mpc)},
786 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxonrxc)},
787 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxoffrxc)},
790 #define IXGBE_NB_RXQ_PRIO_STATS (sizeof(rte_ixgbe_rxq_strings) / \
791 sizeof(rte_ixgbe_rxq_strings[0]))
792 #define IXGBE_NB_RXQ_PRIO_VALUES 8
794 static const struct rte_ixgbe_xstats_name_off rte_ixgbe_txq_strings[] = {
795 {"xon_packets", offsetof(struct ixgbe_hw_stats, pxontxc)},
796 {"xoff_packets", offsetof(struct ixgbe_hw_stats, pxofftxc)},
797 {"xon_to_xoff_packets", offsetof(struct ixgbe_hw_stats,
801 #define IXGBE_NB_TXQ_PRIO_STATS (sizeof(rte_ixgbe_txq_strings) / \
802 sizeof(rte_ixgbe_txq_strings[0]))
803 #define IXGBE_NB_TXQ_PRIO_VALUES 8
805 static const struct rte_ixgbe_xstats_name_off rte_ixgbevf_stats_strings[] = {
806 {"rx_multicast_packets", offsetof(struct ixgbevf_hw_stats, vfmprc)},
809 #define IXGBEVF_NB_XSTATS (sizeof(rte_ixgbevf_stats_strings) / \
810 sizeof(rte_ixgbevf_stats_strings[0]))
813 * Atomically reads the link status information from global
814 * structure rte_eth_dev.
817 * - Pointer to the structure rte_eth_dev to read from.
818 * - Pointer to the buffer to be saved with the link status.
821 * - On success, zero.
822 * - On failure, negative value.
825 rte_ixgbe_dev_atomic_read_link_status(struct rte_eth_dev *dev,
826 struct rte_eth_link *link)
828 struct rte_eth_link *dst = link;
829 struct rte_eth_link *src = &(dev->data->dev_link);
831 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
832 *(uint64_t *)src) == 0)
839 * Atomically writes the link status information into global
840 * structure rte_eth_dev.
843 * - Pointer to the structure rte_eth_dev to read from.
844 * - Pointer to the buffer to be saved with the link status.
847 * - On success, zero.
848 * - On failure, negative value.
851 rte_ixgbe_dev_atomic_write_link_status(struct rte_eth_dev *dev,
852 struct rte_eth_link *link)
854 struct rte_eth_link *dst = &(dev->data->dev_link);
855 struct rte_eth_link *src = link;
857 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
858 *(uint64_t *)src) == 0)
865 * This function is the same as ixgbe_is_sfp() in base/ixgbe.h.
868 ixgbe_is_sfp(struct ixgbe_hw *hw)
870 switch (hw->phy.type) {
871 case ixgbe_phy_sfp_avago:
872 case ixgbe_phy_sfp_ftl:
873 case ixgbe_phy_sfp_intel:
874 case ixgbe_phy_sfp_unknown:
875 case ixgbe_phy_sfp_passive_tyco:
876 case ixgbe_phy_sfp_passive_unknown:
883 static inline int32_t
884 ixgbe_pf_reset_hw(struct ixgbe_hw *hw)
889 status = ixgbe_reset_hw(hw);
891 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
892 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
893 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
894 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
895 IXGBE_WRITE_FLUSH(hw);
897 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
898 status = IXGBE_SUCCESS;
903 ixgbe_enable_intr(struct rte_eth_dev *dev)
905 struct ixgbe_interrupt *intr =
906 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
907 struct ixgbe_hw *hw =
908 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
910 IXGBE_WRITE_REG(hw, IXGBE_EIMS, intr->mask);
911 IXGBE_WRITE_FLUSH(hw);
915 * This function is based on ixgbe_disable_intr() in base/ixgbe.h.
918 ixgbe_disable_intr(struct ixgbe_hw *hw)
920 PMD_INIT_FUNC_TRACE();
922 if (hw->mac.type == ixgbe_mac_82598EB) {
923 IXGBE_WRITE_REG(hw, IXGBE_EIMC, ~0);
925 IXGBE_WRITE_REG(hw, IXGBE_EIMC, 0xFFFF0000);
926 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), ~0);
927 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), ~0);
929 IXGBE_WRITE_FLUSH(hw);
933 * This function resets queue statistics mapping registers.
934 * From Niantic datasheet, Initialization of Statistics section:
935 * "...if software requires the queue counters, the RQSMR and TQSM registers
936 * must be re-programmed following a device reset.
939 ixgbe_reset_qstat_mappings(struct ixgbe_hw *hw)
943 for (i = 0; i != IXGBE_NB_STAT_MAPPING_REGS; i++) {
944 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), 0);
945 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), 0);
951 ixgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
956 #define QSM_REG_NB_BITS_PER_QMAP_FIELD 8
957 #define NB_QMAP_FIELDS_PER_QSM_REG 4
958 #define QMAP_FIELD_RESERVED_BITS_MASK 0x0f
960 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
961 struct ixgbe_stat_mapping_registers *stat_mappings =
962 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(eth_dev->data->dev_private);
963 uint32_t qsmr_mask = 0;
964 uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
968 if ((hw->mac.type != ixgbe_mac_82599EB) &&
969 (hw->mac.type != ixgbe_mac_X540) &&
970 (hw->mac.type != ixgbe_mac_X550) &&
971 (hw->mac.type != ixgbe_mac_X550EM_x) &&
972 (hw->mac.type != ixgbe_mac_X550EM_a))
975 PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
976 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
979 n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
980 if (n >= IXGBE_NB_STAT_MAPPING_REGS) {
981 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
984 offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
986 /* Now clear any previous stat_idx set */
987 clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
989 stat_mappings->tqsm[n] &= ~clearing_mask;
991 stat_mappings->rqsmr[n] &= ~clearing_mask;
993 q_map = (uint32_t)stat_idx;
994 q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
995 qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
997 stat_mappings->tqsm[n] |= qsmr_mask;
999 stat_mappings->rqsmr[n] |= qsmr_mask;
1001 PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
1002 (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
1003 queue_id, stat_idx);
1004 PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
1005 is_rx ? stat_mappings->rqsmr[n] : stat_mappings->tqsm[n]);
1007 /* Now write the mapping in the appropriate register */
1009 PMD_INIT_LOG(DEBUG, "Write 0x%x to RX IXGBE stat mapping reg:%d",
1010 stat_mappings->rqsmr[n], n);
1011 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(n), stat_mappings->rqsmr[n]);
1013 PMD_INIT_LOG(DEBUG, "Write 0x%x to TX IXGBE stat mapping reg:%d",
1014 stat_mappings->tqsm[n], n);
1015 IXGBE_WRITE_REG(hw, IXGBE_TQSM(n), stat_mappings->tqsm[n]);
1021 ixgbe_restore_statistics_mapping(struct rte_eth_dev *dev)
1023 struct ixgbe_stat_mapping_registers *stat_mappings =
1024 IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(dev->data->dev_private);
1025 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028 /* write whatever was in stat mapping table to the NIC */
1029 for (i = 0; i < IXGBE_NB_STAT_MAPPING_REGS; i++) {
1031 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), stat_mappings->rqsmr[i]);
1034 IXGBE_WRITE_REG(hw, IXGBE_TQSM(i), stat_mappings->tqsm[i]);
1039 ixgbe_dcb_init(struct ixgbe_hw *hw, struct ixgbe_dcb_config *dcb_config)
1042 struct ixgbe_dcb_tc_config *tc;
1043 uint8_t dcb_max_tc = IXGBE_DCB_MAX_TRAFFIC_CLASS;
1045 dcb_config->num_tcs.pg_tcs = dcb_max_tc;
1046 dcb_config->num_tcs.pfc_tcs = dcb_max_tc;
1047 for (i = 0; i < dcb_max_tc; i++) {
1048 tc = &dcb_config->tc_config[i];
1049 tc->path[IXGBE_DCB_TX_CONFIG].bwg_id = i;
1050 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
1051 (uint8_t)(100/dcb_max_tc + (i & 1));
1052 tc->path[IXGBE_DCB_RX_CONFIG].bwg_id = i;
1053 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
1054 (uint8_t)(100/dcb_max_tc + (i & 1));
1055 tc->pfc = ixgbe_dcb_pfc_disabled;
1058 /* Initialize default user to priority mapping, UPx->TC0 */
1059 tc = &dcb_config->tc_config[0];
1060 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
1061 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
1062 for (i = 0; i < IXGBE_DCB_MAX_BW_GROUP; i++) {
1063 dcb_config->bw_percentage[IXGBE_DCB_TX_CONFIG][i] = 100;
1064 dcb_config->bw_percentage[IXGBE_DCB_RX_CONFIG][i] = 100;
1066 dcb_config->rx_pba_cfg = ixgbe_dcb_pba_equal;
1067 dcb_config->pfc_mode_enable = false;
1068 dcb_config->vt_mode = true;
1069 dcb_config->round_robin_enable = false;
1070 /* support all DCB capabilities in 82599 */
1071 dcb_config->support.capabilities = 0xFF;
1073 /*we only support 4 Tcs for X540, X550 */
1074 if (hw->mac.type == ixgbe_mac_X540 ||
1075 hw->mac.type == ixgbe_mac_X550 ||
1076 hw->mac.type == ixgbe_mac_X550EM_x ||
1077 hw->mac.type == ixgbe_mac_X550EM_a) {
1078 dcb_config->num_tcs.pg_tcs = 4;
1079 dcb_config->num_tcs.pfc_tcs = 4;
1084 * Ensure that all locks are released before first NVM or PHY access
1087 ixgbe_swfw_lock_reset(struct ixgbe_hw *hw)
1092 * Phy lock should not fail in this early stage. If this is the case,
1093 * it is due to an improper exit of the application.
1094 * So force the release of the faulty lock. Release of common lock
1095 * is done automatically by swfw_sync function.
1097 mask = IXGBE_GSSR_PHY0_SM << hw->bus.func;
1098 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1099 PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released", hw->bus.func);
1101 ixgbe_release_swfw_semaphore(hw, mask);
1104 * These ones are more tricky since they are common to all ports; but
1105 * swfw_sync retries last long enough (1s) to be almost sure that if
1106 * lock can not be taken it is due to an improper lock of the
1109 mask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_MAC_CSR_SM | IXGBE_GSSR_SW_MNG_SM;
1110 if (ixgbe_acquire_swfw_semaphore(hw, mask) < 0) {
1111 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1113 ixgbe_release_swfw_semaphore(hw, mask);
1117 * This function is based on code in ixgbe_attach() in base/ixgbe.c.
1118 * It returns 0 on success.
1121 eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev)
1123 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1124 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1125 struct ixgbe_hw *hw =
1126 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1127 struct ixgbe_vfta *shadow_vfta =
1128 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1129 struct ixgbe_hwstrip *hwstrip =
1130 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1131 struct ixgbe_dcb_config *dcb_config =
1132 IXGBE_DEV_PRIVATE_TO_DCB_CFG(eth_dev->data->dev_private);
1133 struct ixgbe_filter_info *filter_info =
1134 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1135 struct ixgbe_bw_conf *bw_conf =
1136 IXGBE_DEV_PRIVATE_TO_BW_CONF(eth_dev->data->dev_private);
1141 PMD_INIT_FUNC_TRACE();
1143 eth_dev->dev_ops = &ixgbe_eth_dev_ops;
1144 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1145 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1146 eth_dev->tx_pkt_prepare = &ixgbe_prep_pkts;
1149 * For secondary processes, we don't initialise any further as primary
1150 * has already done this work. Only check we don't need a different
1151 * RX and TX function.
1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1154 struct ixgbe_tx_queue *txq;
1155 /* TX queue function in primary, set by last queue initialized
1156 * Tx queue may not initialized by primary process
1158 if (eth_dev->data->tx_queues) {
1159 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues-1];
1160 ixgbe_set_tx_function(eth_dev, txq);
1162 /* Use default TX function if we get here */
1163 PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
1164 "Using default TX function.");
1167 ixgbe_set_rx_function(eth_dev);
1172 rte_eth_copy_pci_info(eth_dev, pci_dev);
1173 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1175 /* Vendor and Device ID need to be set before init of shared code */
1176 hw->device_id = pci_dev->id.device_id;
1177 hw->vendor_id = pci_dev->id.vendor_id;
1178 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1179 hw->allow_unsupported_sfp = 1;
1181 /* Initialize the shared code (base driver) */
1182 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1183 diag = ixgbe_bypass_init_shared_code(hw);
1185 diag = ixgbe_init_shared_code(hw);
1186 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1188 if (diag != IXGBE_SUCCESS) {
1189 PMD_INIT_LOG(ERR, "Shared code init failed: %d", diag);
1193 /* pick up the PCI bus settings for reporting later */
1194 ixgbe_get_bus_info(hw);
1196 /* Unlock any pending hardware semaphore */
1197 ixgbe_swfw_lock_reset(hw);
1199 /* Initialize DCB configuration*/
1200 memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config));
1201 ixgbe_dcb_init(hw, dcb_config);
1202 /* Get Hardware Flow Control setting */
1203 hw->fc.requested_mode = ixgbe_fc_full;
1204 hw->fc.current_mode = ixgbe_fc_full;
1205 hw->fc.pause_time = IXGBE_FC_PAUSE;
1206 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
1207 hw->fc.low_water[i] = IXGBE_FC_LO;
1208 hw->fc.high_water[i] = IXGBE_FC_HI;
1210 hw->fc.send_xon = 1;
1212 /* Make sure we have a good EEPROM before we read from it */
1213 diag = ixgbe_validate_eeprom_checksum(hw, &csum);
1214 if (diag != IXGBE_SUCCESS) {
1215 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", diag);
1219 #ifdef RTE_LIBRTE_IXGBE_BYPASS
1220 diag = ixgbe_bypass_init_hw(hw);
1222 diag = ixgbe_init_hw(hw);
1223 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
1226 * Devices with copper phys will fail to initialise if ixgbe_init_hw()
1227 * is called too soon after the kernel driver unbinding/binding occurs.
1228 * The failure occurs in ixgbe_identify_phy_generic() for all devices,
1229 * but for non-copper devies, ixgbe_identify_sfp_module_generic() is
1230 * also called. See ixgbe_identify_phy_82599(). The reason for the
1231 * failure is not known, and only occuts when virtualisation features
1232 * are disabled in the bios. A delay of 100ms was found to be enough by
1233 * trial-and-error, and is doubled to be safe.
1235 if (diag && (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)) {
1237 diag = ixgbe_init_hw(hw);
1240 if (diag == IXGBE_ERR_SFP_NOT_PRESENT)
1241 diag = IXGBE_SUCCESS;
1243 if (diag == IXGBE_ERR_EEPROM_VERSION) {
1244 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
1245 "LOM. Please be aware there may be issues associated "
1246 "with your hardware.");
1247 PMD_INIT_LOG(ERR, "If you are experiencing problems "
1248 "please contact your Intel or hardware representative "
1249 "who provided you with this hardware.");
1250 } else if (diag == IXGBE_ERR_SFP_NOT_SUPPORTED)
1251 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
1253 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", diag);
1257 /* Reset the hw statistics */
1258 ixgbe_dev_stats_reset(eth_dev);
1260 /* disable interrupt */
1261 ixgbe_disable_intr(hw);
1263 /* reset mappings for queue statistics hw counters*/
1264 ixgbe_reset_qstat_mappings(hw);
1266 /* Allocate memory for storing MAC addresses */
1267 eth_dev->data->mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1268 hw->mac.num_rar_entries, 0);
1269 if (eth_dev->data->mac_addrs == NULL) {
1271 "Failed to allocate %u bytes needed to store "
1273 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1276 /* Copy the permanent MAC address */
1277 ether_addr_copy((struct ether_addr *) hw->mac.perm_addr,
1278 ð_dev->data->mac_addrs[0]);
1280 /* Allocate memory for storing hash filter MAC addresses */
1281 eth_dev->data->hash_mac_addrs = rte_zmalloc("ixgbe", ETHER_ADDR_LEN *
1282 IXGBE_VMDQ_NUM_UC_MAC, 0);
1283 if (eth_dev->data->hash_mac_addrs == NULL) {
1285 "Failed to allocate %d bytes needed to store MAC addresses",
1286 ETHER_ADDR_LEN * IXGBE_VMDQ_NUM_UC_MAC);
1290 /* initialize the vfta */
1291 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1293 /* initialize the hw strip bitmap*/
1294 memset(hwstrip, 0, sizeof(*hwstrip));
1296 /* initialize PF if max_vfs not zero */
1297 ixgbe_pf_host_init(eth_dev);
1299 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
1300 /* let hardware know driver is loaded */
1301 ctrl_ext |= IXGBE_CTRL_EXT_DRV_LOAD;
1302 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
1303 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
1304 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
1305 IXGBE_WRITE_FLUSH(hw);
1307 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
1308 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
1309 (int) hw->mac.type, (int) hw->phy.type,
1310 (int) hw->phy.sfp_type);
1312 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
1313 (int) hw->mac.type, (int) hw->phy.type);
1315 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
1316 eth_dev->data->port_id, pci_dev->id.vendor_id,
1317 pci_dev->id.device_id);
1319 rte_intr_callback_register(intr_handle,
1320 ixgbe_dev_interrupt_handler, eth_dev);
1322 /* enable uio/vfio intr/eventfd mapping */
1323 rte_intr_enable(intr_handle);
1325 /* enable support intr */
1326 ixgbe_enable_intr(eth_dev);
1328 /* initialize filter info */
1329 memset(filter_info, 0,
1330 sizeof(struct ixgbe_filter_info));
1332 /* initialize 5tuple filter list */
1333 TAILQ_INIT(&filter_info->fivetuple_list);
1335 /* initialize flow director filter list & hash */
1336 ixgbe_fdir_filter_init(eth_dev);
1338 /* initialize l2 tunnel filter list & hash */
1339 ixgbe_l2_tn_filter_init(eth_dev);
1341 TAILQ_INIT(&filter_ntuple_list);
1342 TAILQ_INIT(&filter_ethertype_list);
1343 TAILQ_INIT(&filter_syn_list);
1344 TAILQ_INIT(&filter_fdir_list);
1345 TAILQ_INIT(&filter_l2_tunnel_list);
1346 TAILQ_INIT(&ixgbe_flow_list);
1348 /* initialize bandwidth configuration info */
1349 memset(bw_conf, 0, sizeof(struct ixgbe_bw_conf));
1355 eth_ixgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1357 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1358 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1359 struct ixgbe_hw *hw;
1361 PMD_INIT_FUNC_TRACE();
1363 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1366 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1368 if (hw->adapter_stopped == 0)
1369 ixgbe_dev_close(eth_dev);
1371 eth_dev->dev_ops = NULL;
1372 eth_dev->rx_pkt_burst = NULL;
1373 eth_dev->tx_pkt_burst = NULL;
1375 /* Unlock any pending hardware semaphore */
1376 ixgbe_swfw_lock_reset(hw);
1378 /* disable uio intr before callback unregister */
1379 rte_intr_disable(intr_handle);
1380 rte_intr_callback_unregister(intr_handle,
1381 ixgbe_dev_interrupt_handler, eth_dev);
1383 /* uninitialize PF if max_vfs not zero */
1384 ixgbe_pf_host_uninit(eth_dev);
1386 rte_free(eth_dev->data->mac_addrs);
1387 eth_dev->data->mac_addrs = NULL;
1389 rte_free(eth_dev->data->hash_mac_addrs);
1390 eth_dev->data->hash_mac_addrs = NULL;
1392 /* remove all the fdir filters & hash */
1393 ixgbe_fdir_filter_uninit(eth_dev);
1395 /* remove all the L2 tunnel filters & hash */
1396 ixgbe_l2_tn_filter_uninit(eth_dev);
1398 /* Remove all ntuple filters of the device */
1399 ixgbe_ntuple_filter_uninit(eth_dev);
1401 /* clear all the filters list */
1402 ixgbe_filterlist_flush();
1407 static int ixgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
1409 struct ixgbe_filter_info *filter_info =
1410 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
1411 struct ixgbe_5tuple_filter *p_5tuple;
1413 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
1414 TAILQ_REMOVE(&filter_info->fivetuple_list,
1419 memset(filter_info->fivetuple_mask, 0,
1420 sizeof(uint32_t) * IXGBE_5TUPLE_ARRAY_SIZE);
1425 static int ixgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
1427 struct ixgbe_hw_fdir_info *fdir_info =
1428 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1429 struct ixgbe_fdir_filter *fdir_filter;
1431 if (fdir_info->hash_map)
1432 rte_free(fdir_info->hash_map);
1433 if (fdir_info->hash_handle)
1434 rte_hash_free(fdir_info->hash_handle);
1436 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1437 TAILQ_REMOVE(&fdir_info->fdir_list,
1440 rte_free(fdir_filter);
1446 static int ixgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
1448 struct ixgbe_l2_tn_info *l2_tn_info =
1449 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1450 struct ixgbe_l2_tn_filter *l2_tn_filter;
1452 if (l2_tn_info->hash_map)
1453 rte_free(l2_tn_info->hash_map);
1454 if (l2_tn_info->hash_handle)
1455 rte_hash_free(l2_tn_info->hash_handle);
1457 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
1458 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
1461 rte_free(l2_tn_filter);
1467 static int ixgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
1469 struct ixgbe_hw_fdir_info *fdir_info =
1470 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(eth_dev->data->dev_private);
1471 char fdir_hash_name[RTE_HASH_NAMESIZE];
1472 struct rte_hash_parameters fdir_hash_params = {
1473 .name = fdir_hash_name,
1474 .entries = IXGBE_MAX_FDIR_FILTER_NUM,
1475 .key_len = sizeof(union ixgbe_atr_input),
1476 .hash_func = rte_hash_crc,
1477 .hash_func_init_val = 0,
1478 .socket_id = rte_socket_id(),
1481 TAILQ_INIT(&fdir_info->fdir_list);
1482 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1483 "fdir_%s", eth_dev->device->name);
1484 fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
1485 if (!fdir_info->hash_handle) {
1486 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1489 fdir_info->hash_map = rte_zmalloc("ixgbe",
1490 sizeof(struct ixgbe_fdir_filter *) *
1491 IXGBE_MAX_FDIR_FILTER_NUM,
1493 if (!fdir_info->hash_map) {
1495 "Failed to allocate memory for fdir hash map!");
1498 fdir_info->mask_added = FALSE;
1503 static int ixgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
1505 struct ixgbe_l2_tn_info *l2_tn_info =
1506 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(eth_dev->data->dev_private);
1507 char l2_tn_hash_name[RTE_HASH_NAMESIZE];
1508 struct rte_hash_parameters l2_tn_hash_params = {
1509 .name = l2_tn_hash_name,
1510 .entries = IXGBE_MAX_L2_TN_FILTER_NUM,
1511 .key_len = sizeof(struct ixgbe_l2_tn_key),
1512 .hash_func = rte_hash_crc,
1513 .hash_func_init_val = 0,
1514 .socket_id = rte_socket_id(),
1517 TAILQ_INIT(&l2_tn_info->l2_tn_list);
1518 snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
1519 "l2_tn_%s", eth_dev->device->name);
1520 l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
1521 if (!l2_tn_info->hash_handle) {
1522 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
1525 l2_tn_info->hash_map = rte_zmalloc("ixgbe",
1526 sizeof(struct ixgbe_l2_tn_filter *) *
1527 IXGBE_MAX_L2_TN_FILTER_NUM,
1529 if (!l2_tn_info->hash_map) {
1531 "Failed to allocate memory for L2 TN hash map!");
1534 l2_tn_info->e_tag_en = FALSE;
1535 l2_tn_info->e_tag_fwd_en = FALSE;
1536 l2_tn_info->e_tag_ether_type = DEFAULT_ETAG_ETYPE;
1541 * Negotiate mailbox API version with the PF.
1542 * After reset API version is always set to the basic one (ixgbe_mbox_api_10).
1543 * Then we try to negotiate starting with the most recent one.
1544 * If all negotiation attempts fail, then we will proceed with
1545 * the default one (ixgbe_mbox_api_10).
1548 ixgbevf_negotiate_api(struct ixgbe_hw *hw)
1552 /* start with highest supported, proceed down */
1553 static const enum ixgbe_pfvf_api_rev sup_ver[] = {
1560 i != RTE_DIM(sup_ver) &&
1561 ixgbevf_negotiate_api_version(hw, sup_ver[i]) != 0;
1567 generate_random_mac_addr(struct ether_addr *mac_addr)
1571 /* Set Organizationally Unique Identifier (OUI) prefix. */
1572 mac_addr->addr_bytes[0] = 0x00;
1573 mac_addr->addr_bytes[1] = 0x09;
1574 mac_addr->addr_bytes[2] = 0xC0;
1575 /* Force indication of locally assigned MAC address. */
1576 mac_addr->addr_bytes[0] |= ETHER_LOCAL_ADMIN_ADDR;
1577 /* Generate the last 3 bytes of the MAC address with a random number. */
1578 random = rte_rand();
1579 memcpy(&mac_addr->addr_bytes[3], &random, 3);
1583 * Virtual Function device init
1586 eth_ixgbevf_dev_init(struct rte_eth_dev *eth_dev)
1590 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1591 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1592 struct ixgbe_hw *hw =
1593 IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1594 struct ixgbe_vfta *shadow_vfta =
1595 IXGBE_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
1596 struct ixgbe_hwstrip *hwstrip =
1597 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(eth_dev->data->dev_private);
1598 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
1600 PMD_INIT_FUNC_TRACE();
1602 eth_dev->dev_ops = &ixgbevf_eth_dev_ops;
1603 eth_dev->rx_pkt_burst = &ixgbe_recv_pkts;
1604 eth_dev->tx_pkt_burst = &ixgbe_xmit_pkts;
1606 /* for secondary processes, we don't initialise any further as primary
1607 * has already done this work. Only check we don't need a different
1610 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1611 struct ixgbe_tx_queue *txq;
1612 /* TX queue function in primary, set by last queue initialized
1613 * Tx queue may not initialized by primary process
1615 if (eth_dev->data->tx_queues) {
1616 txq = eth_dev->data->tx_queues[eth_dev->data->nb_tx_queues - 1];
1617 ixgbe_set_tx_function(eth_dev, txq);
1619 /* Use default TX function if we get here */
1620 PMD_INIT_LOG(NOTICE,
1621 "No TX queues configured yet. Using default TX function.");
1624 ixgbe_set_rx_function(eth_dev);
1629 rte_eth_copy_pci_info(eth_dev, pci_dev);
1630 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1632 hw->device_id = pci_dev->id.device_id;
1633 hw->vendor_id = pci_dev->id.vendor_id;
1634 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1636 /* initialize the vfta */
1637 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
1639 /* initialize the hw strip bitmap*/
1640 memset(hwstrip, 0, sizeof(*hwstrip));
1642 /* Initialize the shared code (base driver) */
1643 diag = ixgbe_init_shared_code(hw);
1644 if (diag != IXGBE_SUCCESS) {
1645 PMD_INIT_LOG(ERR, "Shared code init failed for ixgbevf: %d", diag);
1649 /* init_mailbox_params */
1650 hw->mbx.ops.init_params(hw);
1652 /* Reset the hw statistics */
1653 ixgbevf_dev_stats_reset(eth_dev);
1655 /* Disable the interrupts for VF */
1656 ixgbevf_intr_disable(hw);
1658 hw->mac.num_rar_entries = 128; /* The MAX of the underlying PF */
1659 diag = hw->mac.ops.reset_hw(hw);
1662 * The VF reset operation returns the IXGBE_ERR_INVALID_MAC_ADDR when
1663 * the underlying PF driver has not assigned a MAC address to the VF.
1664 * In this case, assign a random MAC address.
1666 if ((diag != IXGBE_SUCCESS) && (diag != IXGBE_ERR_INVALID_MAC_ADDR)) {
1667 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1671 /* negotiate mailbox API version to use with the PF. */
1672 ixgbevf_negotiate_api(hw);
1674 /* Get Rx/Tx queue count via mailbox, which is ready after reset_hw */
1675 ixgbevf_get_queues(hw, &tcs, &tc);
1677 /* Allocate memory for storing MAC addresses */
1678 eth_dev->data->mac_addrs = rte_zmalloc("ixgbevf", ETHER_ADDR_LEN *
1679 hw->mac.num_rar_entries, 0);
1680 if (eth_dev->data->mac_addrs == NULL) {
1682 "Failed to allocate %u bytes needed to store "
1684 ETHER_ADDR_LEN * hw->mac.num_rar_entries);
1688 /* Generate a random MAC address, if none was assigned by PF. */
1689 if (is_zero_ether_addr(perm_addr)) {
1690 generate_random_mac_addr(perm_addr);
1691 diag = ixgbe_set_rar_vf(hw, 1, perm_addr->addr_bytes, 0, 1);
1693 rte_free(eth_dev->data->mac_addrs);
1694 eth_dev->data->mac_addrs = NULL;
1697 PMD_INIT_LOG(INFO, "\tVF MAC address not assigned by Host PF");
1698 PMD_INIT_LOG(INFO, "\tAssign randomly generated MAC address "
1699 "%02x:%02x:%02x:%02x:%02x:%02x",
1700 perm_addr->addr_bytes[0],
1701 perm_addr->addr_bytes[1],
1702 perm_addr->addr_bytes[2],
1703 perm_addr->addr_bytes[3],
1704 perm_addr->addr_bytes[4],
1705 perm_addr->addr_bytes[5]);
1708 /* Copy the permanent MAC address */
1709 ether_addr_copy(perm_addr, ð_dev->data->mac_addrs[0]);
1711 /* reset the hardware with the new settings */
1712 diag = hw->mac.ops.start_hw(hw);
1718 PMD_INIT_LOG(ERR, "VF Initialization Failure: %d", diag);
1722 rte_intr_callback_register(intr_handle,
1723 ixgbevf_dev_interrupt_handler, eth_dev);
1724 rte_intr_enable(intr_handle);
1725 ixgbevf_intr_enable(hw);
1727 PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x mac.type=%s",
1728 eth_dev->data->port_id, pci_dev->id.vendor_id,
1729 pci_dev->id.device_id, "ixgbe_mac_82599_vf");
1734 /* Virtual Function device uninit */
1737 eth_ixgbevf_dev_uninit(struct rte_eth_dev *eth_dev)
1739 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1740 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1741 struct ixgbe_hw *hw;
1743 PMD_INIT_FUNC_TRACE();
1745 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1748 hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1750 if (hw->adapter_stopped == 0)
1751 ixgbevf_dev_close(eth_dev);
1753 eth_dev->dev_ops = NULL;
1754 eth_dev->rx_pkt_burst = NULL;
1755 eth_dev->tx_pkt_burst = NULL;
1757 /* Disable the interrupts for VF */
1758 ixgbevf_intr_disable(hw);
1760 rte_free(eth_dev->data->mac_addrs);
1761 eth_dev->data->mac_addrs = NULL;
1763 rte_intr_disable(intr_handle);
1764 rte_intr_callback_unregister(intr_handle,
1765 ixgbevf_dev_interrupt_handler, eth_dev);
1770 static int eth_ixgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1771 struct rte_pci_device *pci_dev)
1773 return rte_eth_dev_pci_generic_probe(pci_dev,
1774 sizeof(struct ixgbe_adapter), eth_ixgbe_dev_init);
1777 static int eth_ixgbe_pci_remove(struct rte_pci_device *pci_dev)
1779 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbe_dev_uninit);
1782 static struct rte_pci_driver rte_ixgbe_pmd = {
1783 .id_table = pci_id_ixgbe_map,
1784 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1785 .probe = eth_ixgbe_pci_probe,
1786 .remove = eth_ixgbe_pci_remove,
1789 static int eth_ixgbevf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1790 struct rte_pci_device *pci_dev)
1792 return rte_eth_dev_pci_generic_probe(pci_dev,
1793 sizeof(struct ixgbe_adapter), eth_ixgbevf_dev_init);
1796 static int eth_ixgbevf_pci_remove(struct rte_pci_device *pci_dev)
1798 return rte_eth_dev_pci_generic_remove(pci_dev, eth_ixgbevf_dev_uninit);
1802 * virtual function driver struct
1804 static struct rte_pci_driver rte_ixgbevf_pmd = {
1805 .id_table = pci_id_ixgbevf_map,
1806 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1807 .probe = eth_ixgbevf_pci_probe,
1808 .remove = eth_ixgbevf_pci_remove,
1812 ixgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1814 struct ixgbe_hw *hw =
1815 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816 struct ixgbe_vfta *shadow_vfta =
1817 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1822 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
1823 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
1824 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(vid_idx));
1829 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vid_idx), vfta);
1831 /* update local VFTA copy */
1832 shadow_vfta->vfta[vid_idx] = vfta;
1838 ixgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
1841 ixgbe_vlan_hw_strip_enable(dev, queue);
1843 ixgbe_vlan_hw_strip_disable(dev, queue);
1847 ixgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1848 enum rte_vlan_type vlan_type,
1851 struct ixgbe_hw *hw =
1852 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857 qinq = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1858 qinq &= IXGBE_DMATXCTL_GDV;
1860 switch (vlan_type) {
1861 case ETH_VLAN_TYPE_INNER:
1863 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1864 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1865 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1866 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1867 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1868 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1869 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1872 PMD_DRV_LOG(ERR, "Inner type is not supported"
1876 case ETH_VLAN_TYPE_OUTER:
1878 /* Only the high 16-bits is valid */
1879 IXGBE_WRITE_REG(hw, IXGBE_EXVET, (uint32_t)tpid <<
1880 IXGBE_EXVET_VET_EXT_SHIFT);
1882 reg = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1883 reg = (reg & (~IXGBE_VLNCTRL_VET)) | (uint32_t)tpid;
1884 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, reg);
1885 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1886 reg = (reg & (~IXGBE_DMATXCTL_VT_MASK))
1887 | ((uint32_t)tpid << IXGBE_DMATXCTL_VT_SHIFT);
1888 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg);
1894 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1902 ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1904 struct ixgbe_hw *hw =
1905 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1908 PMD_INIT_FUNC_TRACE();
1910 /* Filter Table Disable */
1911 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1912 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1914 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1918 ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1920 struct ixgbe_hw *hw =
1921 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922 struct ixgbe_vfta *shadow_vfta =
1923 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1927 PMD_INIT_FUNC_TRACE();
1929 /* Filter Table Enable */
1930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1931 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
1932 vlnctrl |= IXGBE_VLNCTRL_VFE;
1934 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1936 /* write whatever is in local vfta copy */
1937 for (i = 0; i < IXGBE_VFTA_SIZE; i++)
1938 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), shadow_vfta->vfta[i]);
1942 ixgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1944 struct ixgbe_hwstrip *hwstrip =
1945 IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(dev->data->dev_private);
1946 struct ixgbe_rx_queue *rxq;
1948 if (queue >= IXGBE_MAX_RX_QUEUE_NUM)
1952 IXGBE_SET_HWSTRIP(hwstrip, queue);
1954 IXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1956 if (queue >= dev->data->nb_rx_queues)
1959 rxq = dev->data->rx_queues[queue];
1962 rxq->vlan_flags = PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
1964 rxq->vlan_flags = PKT_RX_VLAN_PKT;
1968 ixgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1970 struct ixgbe_hw *hw =
1971 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974 PMD_INIT_FUNC_TRACE();
1976 if (hw->mac.type == ixgbe_mac_82598EB) {
1977 /* No queue level support */
1978 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
1982 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
1983 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
1984 ctrl &= ~IXGBE_RXDCTL_VME;
1985 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
1987 /* record those setting for HW strip per queue */
1988 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1992 ixgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1994 struct ixgbe_hw *hw =
1995 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1998 PMD_INIT_FUNC_TRACE();
2000 if (hw->mac.type == ixgbe_mac_82598EB) {
2001 /* No queue level supported */
2002 PMD_INIT_LOG(NOTICE, "82598EB not support queue level hw strip");
2006 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2007 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
2008 ctrl |= IXGBE_RXDCTL_VME;
2009 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
2011 /* record those setting for HW strip per queue */
2012 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
2016 ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev)
2018 struct ixgbe_hw *hw =
2019 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2022 struct ixgbe_rx_queue *rxq;
2024 PMD_INIT_FUNC_TRACE();
2026 if (hw->mac.type == ixgbe_mac_82598EB) {
2027 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2028 ctrl &= ~IXGBE_VLNCTRL_VME;
2029 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2031 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2032 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2033 rxq = dev->data->rx_queues[i];
2034 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2035 ctrl &= ~IXGBE_RXDCTL_VME;
2036 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2038 /* record those setting for HW strip per queue */
2039 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 0);
2045 ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev)
2047 struct ixgbe_hw *hw =
2048 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2051 struct ixgbe_rx_queue *rxq;
2053 PMD_INIT_FUNC_TRACE();
2055 if (hw->mac.type == ixgbe_mac_82598EB) {
2056 ctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2057 ctrl |= IXGBE_VLNCTRL_VME;
2058 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, ctrl);
2060 /* Other 10G NIC, the VLAN strip can be setup per queue in RXDCTL */
2061 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2062 rxq = dev->data->rx_queues[i];
2063 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
2064 ctrl |= IXGBE_RXDCTL_VME;
2065 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), ctrl);
2067 /* record those setting for HW strip per queue */
2068 ixgbe_vlan_hw_strip_bitmap_set(dev, i, 1);
2074 ixgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2076 struct ixgbe_hw *hw =
2077 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2080 PMD_INIT_FUNC_TRACE();
2082 /* DMATXCTRL: Geric Double VLAN Disable */
2083 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2084 ctrl &= ~IXGBE_DMATXCTL_GDV;
2085 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2087 /* CTRL_EXT: Global Double VLAN Disable */
2088 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2089 ctrl &= ~IXGBE_EXTENDED_VLAN;
2090 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2095 ixgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2097 struct ixgbe_hw *hw =
2098 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2101 PMD_INIT_FUNC_TRACE();
2103 /* DMATXCTRL: Geric Double VLAN Enable */
2104 ctrl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2105 ctrl |= IXGBE_DMATXCTL_GDV;
2106 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, ctrl);
2108 /* CTRL_EXT: Global Double VLAN Enable */
2109 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
2110 ctrl |= IXGBE_EXTENDED_VLAN;
2111 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl);
2113 /* Clear pooling mode of PFVTCTL. It's required by X550. */
2114 if (hw->mac.type == ixgbe_mac_X550 ||
2115 hw->mac.type == ixgbe_mac_X550EM_x ||
2116 hw->mac.type == ixgbe_mac_X550EM_a) {
2117 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2118 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
2119 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
2123 * VET EXT field in the EXVET register = 0x8100 by default
2124 * So no need to change. Same to VT field of DMATXCTL register
2129 ixgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2131 if (mask & ETH_VLAN_STRIP_MASK) {
2132 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2133 ixgbe_vlan_hw_strip_enable_all(dev);
2135 ixgbe_vlan_hw_strip_disable_all(dev);
2138 if (mask & ETH_VLAN_FILTER_MASK) {
2139 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2140 ixgbe_vlan_hw_filter_enable(dev);
2142 ixgbe_vlan_hw_filter_disable(dev);
2145 if (mask & ETH_VLAN_EXTEND_MASK) {
2146 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2147 ixgbe_vlan_hw_extend_enable(dev);
2149 ixgbe_vlan_hw_extend_disable(dev);
2154 ixgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2156 struct ixgbe_hw *hw =
2157 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2159 uint32_t vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2161 vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
2162 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2166 ixgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
2168 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2173 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
2176 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
2182 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = nb_rx_q;
2183 RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx = pci_dev->max_vfs * nb_rx_q;
2189 ixgbe_check_mq_mode(struct rte_eth_dev *dev)
2191 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
2192 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193 uint16_t nb_rx_q = dev->data->nb_rx_queues;
2194 uint16_t nb_tx_q = dev->data->nb_tx_queues;
2196 if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
2197 /* check multi-queue mode */
2198 switch (dev_conf->rxmode.mq_mode) {
2199 case ETH_MQ_RX_VMDQ_DCB:
2200 PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
2202 case ETH_MQ_RX_VMDQ_DCB_RSS:
2203 /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
2204 PMD_INIT_LOG(ERR, "SRIOV active,"
2205 " unsupported mq_mode rx %d.",
2206 dev_conf->rxmode.mq_mode);
2209 case ETH_MQ_RX_VMDQ_RSS:
2210 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
2211 if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
2212 if (ixgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
2213 PMD_INIT_LOG(ERR, "SRIOV is active,"
2214 " invalid queue number"
2215 " for VMDQ RSS, allowed"
2216 " value are 1, 2 or 4.");
2220 case ETH_MQ_RX_VMDQ_ONLY:
2221 case ETH_MQ_RX_NONE:
2222 /* if nothing mq mode configure, use default scheme */
2223 dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_ONLY;
2224 if (RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool > 1)
2225 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool = 1;
2227 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
2228 /* SRIOV only works in VMDq enable mode */
2229 PMD_INIT_LOG(ERR, "SRIOV is active,"
2230 " wrong mq_mode rx %d.",
2231 dev_conf->rxmode.mq_mode);
2235 switch (dev_conf->txmode.mq_mode) {
2236 case ETH_MQ_TX_VMDQ_DCB:
2237 PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
2238 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
2240 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
2241 dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_ONLY;
2245 /* check valid queue number */
2246 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
2247 (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
2248 PMD_INIT_LOG(ERR, "SRIOV is active,"
2249 " nb_rx_q=%d nb_tx_q=%d queue number"
2250 " must be less than or equal to %d.",
2252 RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
2256 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
2257 PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
2261 /* check configuration for vmdb+dcb mode */
2262 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
2263 const struct rte_eth_vmdq_dcb_conf *conf;
2265 if (nb_rx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2266 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
2267 IXGBE_VMDQ_DCB_NB_QUEUES);
2270 conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
2271 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2272 conf->nb_queue_pools == ETH_32_POOLS)) {
2273 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2274 " nb_queue_pools must be %d or %d.",
2275 ETH_16_POOLS, ETH_32_POOLS);
2279 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
2280 const struct rte_eth_vmdq_dcb_tx_conf *conf;
2282 if (nb_tx_q != IXGBE_VMDQ_DCB_NB_QUEUES) {
2283 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
2284 IXGBE_VMDQ_DCB_NB_QUEUES);
2287 conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
2288 if (!(conf->nb_queue_pools == ETH_16_POOLS ||
2289 conf->nb_queue_pools == ETH_32_POOLS)) {
2290 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
2291 " nb_queue_pools != %d and"
2292 " nb_queue_pools != %d.",
2293 ETH_16_POOLS, ETH_32_POOLS);
2298 /* For DCB mode check our configuration before we go further */
2299 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
2300 const struct rte_eth_dcb_rx_conf *conf;
2302 if (nb_rx_q != IXGBE_DCB_NB_QUEUES) {
2303 PMD_INIT_LOG(ERR, "DCB selected, nb_rx_q != %d.",
2304 IXGBE_DCB_NB_QUEUES);
2307 conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
2308 if (!(conf->nb_tcs == ETH_4_TCS ||
2309 conf->nb_tcs == ETH_8_TCS)) {
2310 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2311 " and nb_tcs != %d.",
2312 ETH_4_TCS, ETH_8_TCS);
2317 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
2318 const struct rte_eth_dcb_tx_conf *conf;
2320 if (nb_tx_q != IXGBE_DCB_NB_QUEUES) {
2321 PMD_INIT_LOG(ERR, "DCB, nb_tx_q != %d.",
2322 IXGBE_DCB_NB_QUEUES);
2325 conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
2326 if (!(conf->nb_tcs == ETH_4_TCS ||
2327 conf->nb_tcs == ETH_8_TCS)) {
2328 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
2329 " and nb_tcs != %d.",
2330 ETH_4_TCS, ETH_8_TCS);
2336 * When DCB/VT is off, maximum number of queues changes,
2337 * except for 82598EB, which remains constant.
2339 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
2340 hw->mac.type != ixgbe_mac_82598EB) {
2341 if (nb_tx_q > IXGBE_NONE_MODE_TX_NB_QUEUES) {
2343 "Neither VT nor DCB are enabled, "
2345 IXGBE_NONE_MODE_TX_NB_QUEUES);
2354 ixgbe_dev_configure(struct rte_eth_dev *dev)
2356 struct ixgbe_interrupt *intr =
2357 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2358 struct ixgbe_adapter *adapter =
2359 (struct ixgbe_adapter *)dev->data->dev_private;
2362 PMD_INIT_FUNC_TRACE();
2363 /* multipe queue mode checking */
2364 ret = ixgbe_check_mq_mode(dev);
2366 PMD_DRV_LOG(ERR, "ixgbe_check_mq_mode fails with %d.",
2371 /* set flag to update link status after init */
2372 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2375 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
2376 * allocation or vector Rx preconditions we will reset it.
2378 adapter->rx_bulk_alloc_allowed = true;
2379 adapter->rx_vec_allowed = true;
2385 ixgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
2387 struct ixgbe_hw *hw =
2388 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2389 struct ixgbe_interrupt *intr =
2390 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
2393 /* only set up it on X550EM_X */
2394 if (hw->mac.type == ixgbe_mac_X550EM_x) {
2395 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2396 gpie |= IXGBE_SDP0_GPIEN_X550EM_x;
2397 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2398 if (hw->phy.type == ixgbe_phy_x550em_ext_t)
2399 intr->mask |= IXGBE_EICR_GPI_SDP0_X550EM_x;
2404 ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
2405 uint16_t tx_rate, uint64_t q_msk)
2407 struct ixgbe_hw *hw;
2408 struct ixgbe_vf_info *vfinfo;
2409 struct rte_eth_link link;
2410 uint8_t nb_q_per_pool;
2411 uint32_t queue_stride;
2412 uint32_t queue_idx, idx = 0, vf_idx;
2414 uint16_t total_rate = 0;
2415 struct rte_pci_device *pci_dev;
2417 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2418 rte_eth_link_get_nowait(dev->data->port_id, &link);
2420 if (vf >= pci_dev->max_vfs)
2423 if (tx_rate > link.link_speed)
2429 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2430 vfinfo = *(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
2431 nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
2432 queue_stride = IXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
2433 queue_idx = vf * queue_stride;
2434 queue_end = queue_idx + nb_q_per_pool - 1;
2435 if (queue_end >= hw->mac.max_tx_queues)
2439 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
2442 for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
2444 total_rate += vfinfo[vf_idx].tx_rate[idx];
2450 /* Store tx_rate for this vf. */
2451 for (idx = 0; idx < nb_q_per_pool; idx++) {
2452 if (((uint64_t)0x1 << idx) & q_msk) {
2453 if (vfinfo[vf].tx_rate[idx] != tx_rate)
2454 vfinfo[vf].tx_rate[idx] = tx_rate;
2455 total_rate += tx_rate;
2459 if (total_rate > dev->data->dev_link.link_speed) {
2460 /* Reset stored TX rate of the VF if it causes exceed
2463 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
2467 /* Set RTTBCNRC of each queue/pool for vf X */
2468 for (; queue_idx <= queue_end; queue_idx++) {
2470 ixgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
2478 * Configure device link speed and setup link.
2479 * It returns 0 on success.
2482 ixgbe_dev_start(struct rte_eth_dev *dev)
2484 struct ixgbe_hw *hw =
2485 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2486 struct ixgbe_vf_info *vfinfo =
2487 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2488 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2489 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2490 uint32_t intr_vector = 0;
2491 int err, link_up = 0, negotiate = 0;
2496 uint32_t *link_speeds;
2498 PMD_INIT_FUNC_TRACE();
2500 /* IXGBE devices don't support:
2501 * - half duplex (checked afterwards for valid speeds)
2502 * - fixed speed: TODO implement
2504 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2505 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; fix speed not supported",
2506 dev->data->port_id);
2510 /* disable uio/vfio intr/eventfd mapping */
2511 rte_intr_disable(intr_handle);
2514 hw->adapter_stopped = 0;
2515 ixgbe_stop_adapter(hw);
2517 /* reinitialize adapter
2518 * this calls reset and start
2520 status = ixgbe_pf_reset_hw(hw);
2523 hw->mac.ops.start_hw(hw);
2524 hw->mac.get_link_status = true;
2526 /* configure PF module if SRIOV enabled */
2527 ixgbe_pf_host_configure(dev);
2529 ixgbe_dev_phy_intr_setup(dev);
2531 /* check and configure queue intr-vector mapping */
2532 if ((rte_intr_cap_multiple(intr_handle) ||
2533 !RTE_ETH_DEV_SRIOV(dev).active) &&
2534 dev->data->dev_conf.intr_conf.rxq != 0) {
2535 intr_vector = dev->data->nb_rx_queues;
2536 if (intr_vector > IXGBE_MAX_INTR_QUEUE_NUM) {
2537 PMD_INIT_LOG(ERR, "At most %d intr queues supported",
2538 IXGBE_MAX_INTR_QUEUE_NUM);
2541 if (rte_intr_efd_enable(intr_handle, intr_vector))
2545 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2546 intr_handle->intr_vec =
2547 rte_zmalloc("intr_vec",
2548 dev->data->nb_rx_queues * sizeof(int), 0);
2549 if (intr_handle->intr_vec == NULL) {
2550 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2551 " intr_vec", dev->data->nb_rx_queues);
2556 /* confiugre msix for sleep until rx interrupt */
2557 ixgbe_configure_msix(dev);
2559 /* initialize transmission unit */
2560 ixgbe_dev_tx_init(dev);
2562 /* This can fail when allocating mbufs for descriptor rings */
2563 err = ixgbe_dev_rx_init(dev);
2565 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
2569 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2570 ETH_VLAN_EXTEND_MASK;
2571 ixgbe_vlan_offload_set(dev, mask);
2573 if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
2574 /* Enable vlan filtering for VMDq */
2575 ixgbe_vmdq_vlan_hw_filter_enable(dev);
2578 /* Configure DCB hw */
2579 ixgbe_configure_dcb(dev);
2581 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
2582 err = ixgbe_fdir_configure(dev);
2587 /* Restore vf rate limit */
2588 if (vfinfo != NULL) {
2589 for (vf = 0; vf < pci_dev->max_vfs; vf++)
2590 for (idx = 0; idx < IXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
2591 if (vfinfo[vf].tx_rate[idx] != 0)
2592 ixgbe_set_vf_rate_limit(
2594 vfinfo[vf].tx_rate[idx],
2598 ixgbe_restore_statistics_mapping(dev);
2600 err = ixgbe_dev_rxtx_start(dev);
2602 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
2606 /* Skip link setup if loopback mode is enabled for 82599. */
2607 if (hw->mac.type == ixgbe_mac_82599EB &&
2608 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
2609 goto skip_link_setup;
2611 if (ixgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
2612 err = hw->mac.ops.setup_sfp(hw);
2617 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2618 /* Turn on the copper */
2619 ixgbe_set_phy_power(hw, true);
2621 /* Turn on the laser */
2622 ixgbe_enable_tx_laser(hw);
2625 err = ixgbe_check_link(hw, &speed, &link_up, 0);
2628 dev->data->dev_link.link_status = link_up;
2630 err = ixgbe_get_link_capabilities(hw, &speed, &negotiate);
2634 link_speeds = &dev->data->dev_conf.link_speeds;
2635 if (*link_speeds & ~(ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
2636 ETH_LINK_SPEED_10G)) {
2637 PMD_INIT_LOG(ERR, "Invalid link setting");
2642 if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
2643 speed = (hw->mac.type != ixgbe_mac_82598EB) ?
2644 IXGBE_LINK_SPEED_82599_AUTONEG :
2645 IXGBE_LINK_SPEED_82598_AUTONEG;
2647 if (*link_speeds & ETH_LINK_SPEED_10G)
2648 speed |= IXGBE_LINK_SPEED_10GB_FULL;
2649 if (*link_speeds & ETH_LINK_SPEED_1G)
2650 speed |= IXGBE_LINK_SPEED_1GB_FULL;
2651 if (*link_speeds & ETH_LINK_SPEED_100M)
2652 speed |= IXGBE_LINK_SPEED_100_FULL;
2655 err = ixgbe_setup_link(hw, speed, link_up);
2661 if (rte_intr_allow_others(intr_handle)) {
2662 /* check if lsc interrupt is enabled */
2663 if (dev->data->dev_conf.intr_conf.lsc != 0)
2664 ixgbe_dev_lsc_interrupt_setup(dev);
2665 ixgbe_dev_macsec_interrupt_setup(dev);
2667 rte_intr_callback_unregister(intr_handle,
2668 ixgbe_dev_interrupt_handler, dev);
2669 if (dev->data->dev_conf.intr_conf.lsc != 0)
2670 PMD_INIT_LOG(INFO, "lsc won't enable because of"
2671 " no intr multiplex");
2674 /* check if rxq interrupt is enabled */
2675 if (dev->data->dev_conf.intr_conf.rxq != 0 &&
2676 rte_intr_dp_is_en(intr_handle))
2677 ixgbe_dev_rxq_interrupt_setup(dev);
2679 /* enable uio/vfio intr/eventfd mapping */
2680 rte_intr_enable(intr_handle);
2682 /* resume enabled intr since hw reset */
2683 ixgbe_enable_intr(dev);
2684 ixgbe_l2_tunnel_conf(dev);
2685 ixgbe_filter_restore(dev);
2690 PMD_INIT_LOG(ERR, "failure in ixgbe_dev_start(): %d", err);
2691 ixgbe_dev_clear_queues(dev);
2696 * Stop device: disable rx and tx functions to allow for reconfiguring.
2699 ixgbe_dev_stop(struct rte_eth_dev *dev)
2701 struct rte_eth_link link;
2702 struct ixgbe_hw *hw =
2703 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2704 struct ixgbe_vf_info *vfinfo =
2705 *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
2706 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2707 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2710 PMD_INIT_FUNC_TRACE();
2712 /* disable interrupts */
2713 ixgbe_disable_intr(hw);
2716 ixgbe_pf_reset_hw(hw);
2717 hw->adapter_stopped = 0;
2720 ixgbe_stop_adapter(hw);
2722 for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
2723 vfinfo[vf].clear_to_send = false;
2725 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2726 /* Turn off the copper */
2727 ixgbe_set_phy_power(hw, false);
2729 /* Turn off the laser */
2730 ixgbe_disable_tx_laser(hw);
2733 ixgbe_dev_clear_queues(dev);
2735 /* Clear stored conf */
2736 dev->data->scattered_rx = 0;
2739 /* Clear recorded link status */
2740 memset(&link, 0, sizeof(link));
2741 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
2743 if (!rte_intr_allow_others(intr_handle))
2744 /* resume to the default handler */
2745 rte_intr_callback_register(intr_handle,
2746 ixgbe_dev_interrupt_handler,
2749 /* Clean datapath event and queue/vec mapping */
2750 rte_intr_efd_disable(intr_handle);
2751 if (intr_handle->intr_vec != NULL) {
2752 rte_free(intr_handle->intr_vec);
2753 intr_handle->intr_vec = NULL;
2758 * Set device link up: enable tx.
2761 ixgbe_dev_set_link_up(struct rte_eth_dev *dev)
2763 struct ixgbe_hw *hw =
2764 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2765 if (hw->mac.type == ixgbe_mac_82599EB) {
2766 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2767 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2768 /* Not suported in bypass mode */
2769 PMD_INIT_LOG(ERR, "Set link up is not supported "
2770 "by device id 0x%x", hw->device_id);
2776 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2777 /* Turn on the copper */
2778 ixgbe_set_phy_power(hw, true);
2780 /* Turn on the laser */
2781 ixgbe_enable_tx_laser(hw);
2788 * Set device link down: disable tx.
2791 ixgbe_dev_set_link_down(struct rte_eth_dev *dev)
2793 struct ixgbe_hw *hw =
2794 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 if (hw->mac.type == ixgbe_mac_82599EB) {
2796 #ifdef RTE_LIBRTE_IXGBE_BYPASS
2797 if (hw->device_id == IXGBE_DEV_ID_82599_BYPASS) {
2798 /* Not suported in bypass mode */
2799 PMD_INIT_LOG(ERR, "Set link down is not supported "
2800 "by device id 0x%x", hw->device_id);
2806 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) {
2807 /* Turn off the copper */
2808 ixgbe_set_phy_power(hw, false);
2810 /* Turn off the laser */
2811 ixgbe_disable_tx_laser(hw);
2818 * Reest and stop device.
2821 ixgbe_dev_close(struct rte_eth_dev *dev)
2823 struct ixgbe_hw *hw =
2824 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2826 PMD_INIT_FUNC_TRACE();
2828 ixgbe_pf_reset_hw(hw);
2830 ixgbe_dev_stop(dev);
2831 hw->adapter_stopped = 1;
2833 ixgbe_dev_free_queues(dev);
2835 ixgbe_disable_pcie_master(hw);
2837 /* reprogram the RAR[0] in case user changed it. */
2838 ixgbe_set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2842 ixgbe_read_stats_registers(struct ixgbe_hw *hw,
2843 struct ixgbe_hw_stats *hw_stats,
2844 struct ixgbe_macsec_stats *macsec_stats,
2845 uint64_t *total_missed_rx, uint64_t *total_qbrc,
2846 uint64_t *total_qprc, uint64_t *total_qprdc)
2848 uint32_t bprc, lxon, lxoff, total;
2849 uint32_t delta_gprc = 0;
2851 /* Workaround for RX byte count not including CRC bytes when CRC
2852 * strip is enabled. CRC bytes are removed from counters when crc_strip
2855 int crc_strip = (IXGBE_READ_REG(hw, IXGBE_HLREG0) &
2856 IXGBE_HLREG0_RXCRCSTRP);
2858 hw_stats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
2859 hw_stats->illerrc += IXGBE_READ_REG(hw, IXGBE_ILLERRC);
2860 hw_stats->errbc += IXGBE_READ_REG(hw, IXGBE_ERRBC);
2861 hw_stats->mspdc += IXGBE_READ_REG(hw, IXGBE_MSPDC);
2863 for (i = 0; i < 8; i++) {
2864 uint32_t mp = IXGBE_READ_REG(hw, IXGBE_MPC(i));
2866 /* global total per queue */
2867 hw_stats->mpc[i] += mp;
2868 /* Running comprehensive total for stats display */
2869 *total_missed_rx += hw_stats->mpc[i];
2870 if (hw->mac.type == ixgbe_mac_82598EB) {
2871 hw_stats->rnbc[i] +=
2872 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
2873 hw_stats->pxonrxc[i] +=
2874 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
2875 hw_stats->pxoffrxc[i] +=
2876 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
2878 hw_stats->pxonrxc[i] +=
2879 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
2880 hw_stats->pxoffrxc[i] +=
2881 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
2882 hw_stats->pxon2offc[i] +=
2883 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
2885 hw_stats->pxontxc[i] +=
2886 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
2887 hw_stats->pxofftxc[i] +=
2888 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
2890 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
2891 uint32_t delta_qprc = IXGBE_READ_REG(hw, IXGBE_QPRC(i));
2892 uint32_t delta_qptc = IXGBE_READ_REG(hw, IXGBE_QPTC(i));
2893 uint32_t delta_qprdc = IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
2895 delta_gprc += delta_qprc;
2897 hw_stats->qprc[i] += delta_qprc;
2898 hw_stats->qptc[i] += delta_qptc;
2900 hw_stats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
2901 hw_stats->qbrc[i] +=
2902 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)) << 32);
2904 hw_stats->qbrc[i] -= delta_qprc * ETHER_CRC_LEN;
2906 hw_stats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
2907 hw_stats->qbtc[i] +=
2908 ((uint64_t)IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)) << 32);
2910 hw_stats->qprdc[i] += delta_qprdc;
2911 *total_qprdc += hw_stats->qprdc[i];
2913 *total_qprc += hw_stats->qprc[i];
2914 *total_qbrc += hw_stats->qbrc[i];
2916 hw_stats->mlfc += IXGBE_READ_REG(hw, IXGBE_MLFC);
2917 hw_stats->mrfc += IXGBE_READ_REG(hw, IXGBE_MRFC);
2918 hw_stats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
2921 * An errata states that gprc actually counts good + missed packets:
2922 * Workaround to set gprc to summated queue packet receives
2924 hw_stats->gprc = *total_qprc;
2926 if (hw->mac.type != ixgbe_mac_82598EB) {
2927 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
2928 hw_stats->gorc += ((u64)IXGBE_READ_REG(hw, IXGBE_GORCH) << 32);
2929 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
2930 hw_stats->gotc += ((u64)IXGBE_READ_REG(hw, IXGBE_GOTCH) << 32);
2931 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
2932 hw_stats->tor += ((u64)IXGBE_READ_REG(hw, IXGBE_TORH) << 32);
2933 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
2934 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
2936 hw_stats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
2937 hw_stats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
2938 /* 82598 only has a counter in the high register */
2939 hw_stats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
2940 hw_stats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
2941 hw_stats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
2943 uint64_t old_tpr = hw_stats->tpr;
2945 hw_stats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
2946 hw_stats->tpt += IXGBE_READ_REG(hw, IXGBE_TPT);
2949 hw_stats->gorc -= delta_gprc * ETHER_CRC_LEN;
2951 uint64_t delta_gptc = IXGBE_READ_REG(hw, IXGBE_GPTC);
2952 hw_stats->gptc += delta_gptc;
2953 hw_stats->gotc -= delta_gptc * ETHER_CRC_LEN;
2954 hw_stats->tor -= (hw_stats->tpr - old_tpr) * ETHER_CRC_LEN;
2957 * Workaround: mprc hardware is incorrectly counting
2958 * broadcasts, so for now we subtract those.
2960 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
2961 hw_stats->bprc += bprc;
2962 hw_stats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
2963 if (hw->mac.type == ixgbe_mac_82598EB)
2964 hw_stats->mprc -= bprc;
2966 hw_stats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
2967 hw_stats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
2968 hw_stats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
2969 hw_stats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
2970 hw_stats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
2971 hw_stats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
2973 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
2974 hw_stats->lxontxc += lxon;
2975 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
2976 hw_stats->lxofftxc += lxoff;
2977 total = lxon + lxoff;
2979 hw_stats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
2980 hw_stats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
2981 hw_stats->gptc -= total;
2982 hw_stats->mptc -= total;
2983 hw_stats->ptc64 -= total;
2984 hw_stats->gotc -= total * ETHER_MIN_LEN;
2986 hw_stats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
2987 hw_stats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
2988 hw_stats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
2989 hw_stats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
2990 hw_stats->mngprc += IXGBE_READ_REG(hw, IXGBE_MNGPRC);
2991 hw_stats->mngpdc += IXGBE_READ_REG(hw, IXGBE_MNGPDC);
2992 hw_stats->mngptc += IXGBE_READ_REG(hw, IXGBE_MNGPTC);
2993 hw_stats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
2994 hw_stats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
2995 hw_stats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
2996 hw_stats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
2997 hw_stats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
2998 hw_stats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
2999 hw_stats->xec += IXGBE_READ_REG(hw, IXGBE_XEC);
3000 hw_stats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
3001 hw_stats->fclast += IXGBE_READ_REG(hw, IXGBE_FCLAST);
3002 /* Only read FCOE on 82599 */
3003 if (hw->mac.type != ixgbe_mac_82598EB) {
3004 hw_stats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
3005 hw_stats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
3006 hw_stats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
3007 hw_stats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
3008 hw_stats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
3011 /* Flow Director Stats registers */
3012 hw_stats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
3013 hw_stats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
3015 /* MACsec Stats registers */
3016 macsec_stats->out_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECTXUT);
3017 macsec_stats->out_pkts_encrypted +=
3018 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTE);
3019 macsec_stats->out_pkts_protected +=
3020 IXGBE_READ_REG(hw, IXGBE_LSECTXPKTP);
3021 macsec_stats->out_octets_encrypted +=
3022 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTE);
3023 macsec_stats->out_octets_protected +=
3024 IXGBE_READ_REG(hw, IXGBE_LSECTXOCTP);
3025 macsec_stats->in_pkts_untagged += IXGBE_READ_REG(hw, IXGBE_LSECRXUT);
3026 macsec_stats->in_pkts_badtag += IXGBE_READ_REG(hw, IXGBE_LSECRXBAD);
3027 macsec_stats->in_pkts_nosci += IXGBE_READ_REG(hw, IXGBE_LSECRXNOSCI);
3028 macsec_stats->in_pkts_unknownsci +=
3029 IXGBE_READ_REG(hw, IXGBE_LSECRXUNSCI);
3030 macsec_stats->in_octets_decrypted +=
3031 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTD);
3032 macsec_stats->in_octets_validated +=
3033 IXGBE_READ_REG(hw, IXGBE_LSECRXOCTV);
3034 macsec_stats->in_pkts_unchecked += IXGBE_READ_REG(hw, IXGBE_LSECRXUNCH);
3035 macsec_stats->in_pkts_delayed += IXGBE_READ_REG(hw, IXGBE_LSECRXDELAY);
3036 macsec_stats->in_pkts_late += IXGBE_READ_REG(hw, IXGBE_LSECRXLATE);
3037 for (i = 0; i < 2; i++) {
3038 macsec_stats->in_pkts_ok +=
3039 IXGBE_READ_REG(hw, IXGBE_LSECRXOK(i));
3040 macsec_stats->in_pkts_invalid +=
3041 IXGBE_READ_REG(hw, IXGBE_LSECRXINV(i));
3042 macsec_stats->in_pkts_notvalid +=
3043 IXGBE_READ_REG(hw, IXGBE_LSECRXNV(i));
3045 macsec_stats->in_pkts_unusedsa += IXGBE_READ_REG(hw, IXGBE_LSECRXUNSA);
3046 macsec_stats->in_pkts_notusingsa +=
3047 IXGBE_READ_REG(hw, IXGBE_LSECRXNUSA);
3051 * This function is based on ixgbe_update_stats_counters() in ixgbe/ixgbe.c
3054 ixgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3056 struct ixgbe_hw *hw =
3057 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058 struct ixgbe_hw_stats *hw_stats =
3059 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3060 struct ixgbe_macsec_stats *macsec_stats =
3061 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3062 dev->data->dev_private);
3063 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3066 total_missed_rx = 0;
3071 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3072 &total_qbrc, &total_qprc, &total_qprdc);
3077 /* Fill out the rte_eth_stats statistics structure */
3078 stats->ipackets = total_qprc;
3079 stats->ibytes = total_qbrc;
3080 stats->opackets = hw_stats->gptc;
3081 stats->obytes = hw_stats->gotc;
3083 for (i = 0; i < IXGBE_QUEUE_STAT_COUNTERS; i++) {
3084 stats->q_ipackets[i] = hw_stats->qprc[i];
3085 stats->q_opackets[i] = hw_stats->qptc[i];
3086 stats->q_ibytes[i] = hw_stats->qbrc[i];
3087 stats->q_obytes[i] = hw_stats->qbtc[i];
3088 stats->q_errors[i] = hw_stats->qprdc[i];
3092 stats->imissed = total_missed_rx;
3093 stats->ierrors = hw_stats->crcerrs +
3109 ixgbe_dev_stats_reset(struct rte_eth_dev *dev)
3111 struct ixgbe_hw_stats *stats =
3112 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3114 /* HW registers are cleared on read */
3115 ixgbe_dev_stats_get(dev, NULL);
3117 /* Reset software totals */
3118 memset(stats, 0, sizeof(*stats));
3121 /* This function calculates the number of xstats based on the current config */
3123 ixgbe_xstats_calc_num(void) {
3124 return IXGBE_NB_HW_STATS + IXGBE_NB_MACSEC_STATS +
3125 (IXGBE_NB_RXQ_PRIO_STATS * IXGBE_NB_RXQ_PRIO_VALUES) +
3126 (IXGBE_NB_TXQ_PRIO_STATS * IXGBE_NB_TXQ_PRIO_VALUES);
3129 static int ixgbe_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3130 struct rte_eth_xstat_name *xstats_names, __rte_unused unsigned int size)
3132 const unsigned cnt_stats = ixgbe_xstats_calc_num();
3133 unsigned stat, i, count;
3135 if (xstats_names != NULL) {
3138 /* Note: limit >= cnt_stats checked upstream
3139 * in rte_eth_xstats_names()
3142 /* Extended stats from ixgbe_hw_stats */
3143 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3144 snprintf(xstats_names[count].name,
3145 sizeof(xstats_names[count].name),
3147 rte_ixgbe_stats_strings[i].name);
3152 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3153 snprintf(xstats_names[count].name,
3154 sizeof(xstats_names[count].name),
3156 rte_ixgbe_macsec_strings[i].name);
3160 /* RX Priority Stats */
3161 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3162 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3163 snprintf(xstats_names[count].name,
3164 sizeof(xstats_names[count].name),
3165 "rx_priority%u_%s", i,
3166 rte_ixgbe_rxq_strings[stat].name);
3171 /* TX Priority Stats */
3172 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3173 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3174 snprintf(xstats_names[count].name,
3175 sizeof(xstats_names[count].name),
3176 "tx_priority%u_%s", i,
3177 rte_ixgbe_txq_strings[stat].name);
3185 static int ixgbe_dev_xstats_get_names_by_id(
3186 struct rte_eth_dev *dev,
3187 struct rte_eth_xstat_name *xstats_names,
3188 const uint64_t *ids,
3192 const unsigned int cnt_stats = ixgbe_xstats_calc_num();
3193 unsigned int stat, i, count;
3195 if (xstats_names != NULL) {
3198 /* Note: limit >= cnt_stats checked upstream
3199 * in rte_eth_xstats_names()
3202 /* Extended stats from ixgbe_hw_stats */
3203 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3204 snprintf(xstats_names[count].name,
3205 sizeof(xstats_names[count].name),
3207 rte_ixgbe_stats_strings[i].name);
3212 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3213 snprintf(xstats_names[count].name,
3214 sizeof(xstats_names[count].name),
3216 rte_ixgbe_macsec_strings[i].name);
3220 /* RX Priority Stats */
3221 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3222 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3223 snprintf(xstats_names[count].name,
3224 sizeof(xstats_names[count].name),
3225 "rx_priority%u_%s", i,
3226 rte_ixgbe_rxq_strings[stat].name);
3231 /* TX Priority Stats */
3232 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3233 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3234 snprintf(xstats_names[count].name,
3235 sizeof(xstats_names[count].name),
3236 "tx_priority%u_%s", i,
3237 rte_ixgbe_txq_strings[stat].name);
3246 uint16_t size = ixgbe_xstats_calc_num();
3247 struct rte_eth_xstat_name xstats_names_copy[size];
3249 ixgbe_dev_xstats_get_names_by_id(dev, xstats_names_copy, NULL,
3252 for (i = 0; i < limit; i++) {
3253 if (ids[i] >= size) {
3254 PMD_INIT_LOG(ERR, "id value isn't valid");
3257 strcpy(xstats_names[i].name,
3258 xstats_names_copy[ids[i]].name);
3263 static int ixgbevf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3264 struct rte_eth_xstat_name *xstats_names, unsigned limit)
3268 if (limit < IXGBEVF_NB_XSTATS && xstats_names != NULL)
3271 if (xstats_names != NULL)
3272 for (i = 0; i < IXGBEVF_NB_XSTATS; i++)
3273 snprintf(xstats_names[i].name,
3274 sizeof(xstats_names[i].name),
3275 "%s", rte_ixgbevf_stats_strings[i].name);
3276 return IXGBEVF_NB_XSTATS;
3280 ixgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3283 struct ixgbe_hw *hw =
3284 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3285 struct ixgbe_hw_stats *hw_stats =
3286 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3287 struct ixgbe_macsec_stats *macsec_stats =
3288 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3289 dev->data->dev_private);
3290 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3291 unsigned i, stat, count = 0;
3293 count = ixgbe_xstats_calc_num();
3298 total_missed_rx = 0;
3303 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats, &total_missed_rx,
3304 &total_qbrc, &total_qprc, &total_qprdc);
3306 /* If this is a reset xstats is NULL, and we have cleared the
3307 * registers by reading them.
3312 /* Extended stats from ixgbe_hw_stats */
3314 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3315 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3316 rte_ixgbe_stats_strings[i].offset);
3317 xstats[count].id = count;
3322 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3323 xstats[count].value = *(uint64_t *)(((char *)macsec_stats) +
3324 rte_ixgbe_macsec_strings[i].offset);
3325 xstats[count].id = count;
3329 /* RX Priority Stats */
3330 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3331 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3332 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3333 rte_ixgbe_rxq_strings[stat].offset +
3334 (sizeof(uint64_t) * i));
3335 xstats[count].id = count;
3340 /* TX Priority Stats */
3341 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3342 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3343 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3344 rte_ixgbe_txq_strings[stat].offset +
3345 (sizeof(uint64_t) * i));
3346 xstats[count].id = count;
3354 ixgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
3355 uint64_t *values, unsigned int n)
3358 struct ixgbe_hw *hw =
3359 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 struct ixgbe_hw_stats *hw_stats =
3361 IXGBE_DEV_PRIVATE_TO_STATS(
3362 dev->data->dev_private);
3363 struct ixgbe_macsec_stats *macsec_stats =
3364 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3365 dev->data->dev_private);
3366 uint64_t total_missed_rx, total_qbrc, total_qprc, total_qprdc;
3367 unsigned int i, stat, count = 0;
3369 count = ixgbe_xstats_calc_num();
3371 if (!ids && n < count)
3374 total_missed_rx = 0;
3379 ixgbe_read_stats_registers(hw, hw_stats, macsec_stats,
3380 &total_missed_rx, &total_qbrc, &total_qprc,
3383 /* If this is a reset xstats is NULL, and we have cleared the
3384 * registers by reading them.
3386 if (!ids && !values)
3389 /* Extended stats from ixgbe_hw_stats */
3391 for (i = 0; i < IXGBE_NB_HW_STATS; i++) {
3392 values[count] = *(uint64_t *)(((char *)hw_stats) +
3393 rte_ixgbe_stats_strings[i].offset);
3398 for (i = 0; i < IXGBE_NB_MACSEC_STATS; i++) {
3399 values[count] = *(uint64_t *)(((char *)macsec_stats) +
3400 rte_ixgbe_macsec_strings[i].offset);
3404 /* RX Priority Stats */
3405 for (stat = 0; stat < IXGBE_NB_RXQ_PRIO_STATS; stat++) {
3406 for (i = 0; i < IXGBE_NB_RXQ_PRIO_VALUES; i++) {
3408 *(uint64_t *)(((char *)hw_stats) +
3409 rte_ixgbe_rxq_strings[stat].offset +
3410 (sizeof(uint64_t) * i));
3415 /* TX Priority Stats */
3416 for (stat = 0; stat < IXGBE_NB_TXQ_PRIO_STATS; stat++) {
3417 for (i = 0; i < IXGBE_NB_TXQ_PRIO_VALUES; i++) {
3419 *(uint64_t *)(((char *)hw_stats) +
3420 rte_ixgbe_txq_strings[stat].offset +
3421 (sizeof(uint64_t) * i));
3429 uint16_t size = ixgbe_xstats_calc_num();
3430 uint64_t values_copy[size];
3432 ixgbe_dev_xstats_get_by_id(dev, NULL, values_copy, size);
3434 for (i = 0; i < n; i++) {
3435 if (ids[i] >= size) {
3436 PMD_INIT_LOG(ERR, "id value isn't valid");
3439 values[i] = values_copy[ids[i]];
3445 ixgbe_dev_xstats_reset(struct rte_eth_dev *dev)
3447 struct ixgbe_hw_stats *stats =
3448 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3449 struct ixgbe_macsec_stats *macsec_stats =
3450 IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(
3451 dev->data->dev_private);
3453 unsigned count = ixgbe_xstats_calc_num();
3455 /* HW registers are cleared on read */
3456 ixgbe_dev_xstats_get(dev, NULL, count);
3458 /* Reset software totals */
3459 memset(stats, 0, sizeof(*stats));
3460 memset(macsec_stats, 0, sizeof(*macsec_stats));
3464 ixgbevf_update_stats(struct rte_eth_dev *dev)
3466 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3467 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3468 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3470 /* Good Rx packet, include VF loopback */
3471 UPDATE_VF_STAT(IXGBE_VFGPRC,
3472 hw_stats->last_vfgprc, hw_stats->vfgprc);
3474 /* Good Rx octets, include VF loopback */
3475 UPDATE_VF_STAT_36BIT(IXGBE_VFGORC_LSB, IXGBE_VFGORC_MSB,
3476 hw_stats->last_vfgorc, hw_stats->vfgorc);
3478 /* Good Tx packet, include VF loopback */
3479 UPDATE_VF_STAT(IXGBE_VFGPTC,
3480 hw_stats->last_vfgptc, hw_stats->vfgptc);
3482 /* Good Tx octets, include VF loopback */
3483 UPDATE_VF_STAT_36BIT(IXGBE_VFGOTC_LSB, IXGBE_VFGOTC_MSB,
3484 hw_stats->last_vfgotc, hw_stats->vfgotc);
3486 /* Rx Multicst Packet */
3487 UPDATE_VF_STAT(IXGBE_VFMPRC,
3488 hw_stats->last_vfmprc, hw_stats->vfmprc);
3492 ixgbevf_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3495 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3496 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3499 if (n < IXGBEVF_NB_XSTATS)
3500 return IXGBEVF_NB_XSTATS;
3502 ixgbevf_update_stats(dev);
3507 /* Extended stats */
3508 for (i = 0; i < IXGBEVF_NB_XSTATS; i++) {
3510 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
3511 rte_ixgbevf_stats_strings[i].offset);
3514 return IXGBEVF_NB_XSTATS;
3518 ixgbevf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3520 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3521 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3523 ixgbevf_update_stats(dev);
3528 stats->ipackets = hw_stats->vfgprc;
3529 stats->ibytes = hw_stats->vfgorc;
3530 stats->opackets = hw_stats->vfgptc;
3531 stats->obytes = hw_stats->vfgotc;
3535 ixgbevf_dev_stats_reset(struct rte_eth_dev *dev)
3537 struct ixgbevf_hw_stats *hw_stats = (struct ixgbevf_hw_stats *)
3538 IXGBE_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
3540 /* Sync HW register to the last stats */
3541 ixgbevf_dev_stats_get(dev, NULL);
3543 /* reset HW current stats*/
3544 hw_stats->vfgprc = 0;
3545 hw_stats->vfgorc = 0;
3546 hw_stats->vfgptc = 0;
3547 hw_stats->vfgotc = 0;
3551 ixgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3553 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3554 u16 eeprom_verh, eeprom_verl;
3558 ixgbe_read_eeprom(hw, 0x2e, &eeprom_verh);
3559 ixgbe_read_eeprom(hw, 0x2d, &eeprom_verl);
3561 etrack_id = (eeprom_verh << 16) | eeprom_verl;
3562 ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
3564 ret += 1; /* add the size of '\0' */
3565 if (fw_size < (u32)ret)
3572 ixgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3574 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3575 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3576 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
3578 dev_info->pci_dev = pci_dev;
3579 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3580 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3581 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3583 * When DCB/VT is off, maximum number of queues changes,
3584 * except for 82598EB, which remains constant.
3586 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_NONE &&
3587 hw->mac.type != ixgbe_mac_82598EB)
3588 dev_info->max_tx_queues = IXGBE_NONE_MODE_TX_NB_QUEUES;
3590 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL register */
3591 dev_info->max_rx_pktlen = 15872; /* includes CRC, cf MAXFRS register */
3592 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3593 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3594 dev_info->max_vfs = pci_dev->max_vfs;
3595 if (hw->mac.type == ixgbe_mac_82598EB)
3596 dev_info->max_vmdq_pools = ETH_16_POOLS;
3598 dev_info->max_vmdq_pools = ETH_64_POOLS;
3599 dev_info->vmdq_queue_num = dev_info->max_rx_queues;
3600 dev_info->rx_offload_capa =
3601 DEV_RX_OFFLOAD_VLAN_STRIP |
3602 DEV_RX_OFFLOAD_IPV4_CKSUM |
3603 DEV_RX_OFFLOAD_UDP_CKSUM |
3604 DEV_RX_OFFLOAD_TCP_CKSUM;
3607 * RSC is only supported by 82599 and x540 PF devices in a non-SR-IOV
3610 if ((hw->mac.type == ixgbe_mac_82599EB ||
3611 hw->mac.type == ixgbe_mac_X540) &&
3612 !RTE_ETH_DEV_SRIOV(dev).active)
3613 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TCP_LRO;
3615 if (hw->mac.type == ixgbe_mac_82599EB ||
3616 hw->mac.type == ixgbe_mac_X540)
3617 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_MACSEC_STRIP;
3619 if (hw->mac.type == ixgbe_mac_X550 ||
3620 hw->mac.type == ixgbe_mac_X550EM_x ||
3621 hw->mac.type == ixgbe_mac_X550EM_a)
3622 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
3624 dev_info->tx_offload_capa =
3625 DEV_TX_OFFLOAD_VLAN_INSERT |
3626 DEV_TX_OFFLOAD_IPV4_CKSUM |
3627 DEV_TX_OFFLOAD_UDP_CKSUM |
3628 DEV_TX_OFFLOAD_TCP_CKSUM |
3629 DEV_TX_OFFLOAD_SCTP_CKSUM |
3630 DEV_TX_OFFLOAD_TCP_TSO;
3632 if (hw->mac.type == ixgbe_mac_82599EB ||
3633 hw->mac.type == ixgbe_mac_X540)
3634 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_MACSEC_INSERT;
3636 if (hw->mac.type == ixgbe_mac_X550 ||
3637 hw->mac.type == ixgbe_mac_X550EM_x ||
3638 hw->mac.type == ixgbe_mac_X550EM_a)
3639 dev_info->tx_offload_capa |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
3641 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3643 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3644 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3645 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3647 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3651 dev_info->default_txconf = (struct rte_eth_txconf) {
3653 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3654 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3655 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3657 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3658 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3659 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3660 ETH_TXQ_FLAGS_NOOFFLOADS,
3663 dev_info->rx_desc_lim = rx_desc_lim;
3664 dev_info->tx_desc_lim = tx_desc_lim;
3666 dev_info->hash_key_size = IXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
3667 dev_info->reta_size = ixgbe_reta_size_get(hw->mac.type);
3668 dev_info->flow_type_rss_offloads = IXGBE_RSS_OFFLOAD_ALL;
3670 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3671 if (hw->mac.type == ixgbe_mac_X540 ||
3672 hw->mac.type == ixgbe_mac_X540_vf ||
3673 hw->mac.type == ixgbe_mac_X550 ||
3674 hw->mac.type == ixgbe_mac_X550_vf) {
3675 dev_info->speed_capa |= ETH_LINK_SPEED_100M;
3679 static const uint32_t *
3680 ixgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
3682 static const uint32_t ptypes[] = {
3683 /* For non-vec functions,
3684 * refers to ixgbe_rxd_pkt_info_to_pkt_type();
3685 * for vec functions,
3686 * refers to _recv_raw_pkts_vec().
3690 RTE_PTYPE_L3_IPV4_EXT,
3692 RTE_PTYPE_L3_IPV6_EXT,
3696 RTE_PTYPE_TUNNEL_IP,
3697 RTE_PTYPE_INNER_L3_IPV6,
3698 RTE_PTYPE_INNER_L3_IPV6_EXT,
3699 RTE_PTYPE_INNER_L4_TCP,
3700 RTE_PTYPE_INNER_L4_UDP,
3704 if (dev->rx_pkt_burst == ixgbe_recv_pkts ||
3705 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_single_alloc ||
3706 dev->rx_pkt_burst == ixgbe_recv_pkts_lro_bulk_alloc ||
3707 dev->rx_pkt_burst == ixgbe_recv_pkts_bulk_alloc)
3710 #if defined(RTE_ARCH_X86)
3711 if (dev->rx_pkt_burst == ixgbe_recv_pkts_vec ||
3712 dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec)
3719 ixgbevf_dev_info_get(struct rte_eth_dev *dev,
3720 struct rte_eth_dev_info *dev_info)
3722 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3723 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3725 dev_info->pci_dev = pci_dev;
3726 dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
3727 dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
3728 dev_info->min_rx_bufsize = 1024; /* cf BSIZEPACKET in SRRCTL reg */
3729 dev_info->max_rx_pktlen = 9728; /* includes CRC, cf MAXFRS reg */
3730 dev_info->max_mac_addrs = hw->mac.num_rar_entries;
3731 dev_info->max_hash_mac_addrs = IXGBE_VMDQ_NUM_UC_MAC;
3732 dev_info->max_vfs = pci_dev->max_vfs;
3733 if (hw->mac.type == ixgbe_mac_82598EB)
3734 dev_info->max_vmdq_pools = ETH_16_POOLS;
3736 dev_info->max_vmdq_pools = ETH_64_POOLS;
3737 dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP |
3738 DEV_RX_OFFLOAD_IPV4_CKSUM |
3739 DEV_RX_OFFLOAD_UDP_CKSUM |
3740 DEV_RX_OFFLOAD_TCP_CKSUM;
3741 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT |
3742 DEV_TX_OFFLOAD_IPV4_CKSUM |
3743 DEV_TX_OFFLOAD_UDP_CKSUM |
3744 DEV_TX_OFFLOAD_TCP_CKSUM |
3745 DEV_TX_OFFLOAD_SCTP_CKSUM |
3746 DEV_TX_OFFLOAD_TCP_TSO;
3748 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3750 .pthresh = IXGBE_DEFAULT_RX_PTHRESH,
3751 .hthresh = IXGBE_DEFAULT_RX_HTHRESH,
3752 .wthresh = IXGBE_DEFAULT_RX_WTHRESH,
3754 .rx_free_thresh = IXGBE_DEFAULT_RX_FREE_THRESH,
3758 dev_info->default_txconf = (struct rte_eth_txconf) {
3760 .pthresh = IXGBE_DEFAULT_TX_PTHRESH,
3761 .hthresh = IXGBE_DEFAULT_TX_HTHRESH,
3762 .wthresh = IXGBE_DEFAULT_TX_WTHRESH,
3764 .tx_free_thresh = IXGBE_DEFAULT_TX_FREE_THRESH,
3765 .tx_rs_thresh = IXGBE_DEFAULT_TX_RSBIT_THRESH,
3766 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3767 ETH_TXQ_FLAGS_NOOFFLOADS,
3770 dev_info->rx_desc_lim = rx_desc_lim;
3771 dev_info->tx_desc_lim = tx_desc_lim;
3774 /* return 0 means link status changed, -1 means not changed */
3776 ixgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3778 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3779 struct rte_eth_link link, old;
3780 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
3781 struct ixgbe_interrupt *intr =
3782 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3786 bool autoneg = false;
3788 link.link_status = ETH_LINK_DOWN;
3789 link.link_speed = 0;
3790 link.link_duplex = ETH_LINK_HALF_DUPLEX;
3791 memset(&old, 0, sizeof(old));
3792 rte_ixgbe_dev_atomic_read_link_status(dev, &old);
3794 hw->mac.get_link_status = true;
3796 if ((intr->flags & IXGBE_FLAG_NEED_LINK_CONFIG) &&
3797 ixgbe_get_media_type(hw) == ixgbe_media_type_fiber) {
3798 speed = hw->phy.autoneg_advertised;
3800 ixgbe_get_link_capabilities(hw, &speed, &autoneg);
3801 ixgbe_setup_link(hw, speed, true);
3804 /* check if it needs to wait to complete, if lsc interrupt is enabled */
3805 if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
3806 diag = ixgbe_check_link(hw, &link_speed, &link_up, 0);
3808 diag = ixgbe_check_link(hw, &link_speed, &link_up, 1);
3811 link.link_speed = ETH_SPEED_NUM_100M;
3812 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3813 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3814 if (link.link_status == old.link_status)
3820 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3821 intr->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
3822 if (link.link_status == old.link_status)
3826 intr->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3827 link.link_status = ETH_LINK_UP;
3828 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3830 switch (link_speed) {
3832 case IXGBE_LINK_SPEED_UNKNOWN:
3833 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3834 link.link_speed = ETH_SPEED_NUM_100M;
3837 case IXGBE_LINK_SPEED_100_FULL:
3838 link.link_speed = ETH_SPEED_NUM_100M;
3841 case IXGBE_LINK_SPEED_1GB_FULL:
3842 link.link_speed = ETH_SPEED_NUM_1G;
3845 case IXGBE_LINK_SPEED_10GB_FULL:
3846 link.link_speed = ETH_SPEED_NUM_10G;
3849 rte_ixgbe_dev_atomic_write_link_status(dev, &link);
3851 if (link.link_status == old.link_status)
3858 ixgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
3860 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3863 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3864 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3865 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3869 ixgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
3871 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3874 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3875 fctrl &= (~IXGBE_FCTRL_UPE);
3876 if (dev->data->all_multicast == 1)
3877 fctrl |= IXGBE_FCTRL_MPE;
3879 fctrl &= (~IXGBE_FCTRL_MPE);
3880 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3884 ixgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
3886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3889 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3890 fctrl |= IXGBE_FCTRL_MPE;
3891 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3895 ixgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
3897 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3900 if (dev->data->promiscuous == 1)
3901 return; /* must remain in all_multicast mode */
3903 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3904 fctrl &= (~IXGBE_FCTRL_MPE);
3905 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3909 * It clears the interrupt causes and enables the interrupt.
3910 * It will be called once only during nic initialized.
3913 * Pointer to struct rte_eth_dev.
3916 * - On success, zero.
3917 * - On failure, a negative value.
3920 ixgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev)
3922 struct ixgbe_interrupt *intr =
3923 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3925 ixgbe_dev_link_status_print(dev);
3926 intr->mask |= IXGBE_EICR_LSC;
3932 * It clears the interrupt causes and enables the interrupt.
3933 * It will be called once only during nic initialized.
3936 * Pointer to struct rte_eth_dev.
3939 * - On success, zero.
3940 * - On failure, a negative value.
3943 ixgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
3945 struct ixgbe_interrupt *intr =
3946 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3948 intr->mask |= IXGBE_EICR_RTX_QUEUE;
3954 * It clears the interrupt causes and enables the interrupt.
3955 * It will be called once only during nic initialized.
3958 * Pointer to struct rte_eth_dev.
3961 * - On success, zero.
3962 * - On failure, a negative value.
3965 ixgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
3967 struct ixgbe_interrupt *intr =
3968 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3970 intr->mask |= IXGBE_EICR_LINKSEC;
3976 * It reads ICR and sets flag (IXGBE_EICR_LSC) for the link_update.
3979 * Pointer to struct rte_eth_dev.
3982 * - On success, zero.
3983 * - On failure, a negative value.
3986 ixgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
3989 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3990 struct ixgbe_interrupt *intr =
3991 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
3993 /* clear all cause mask */
3994 ixgbe_disable_intr(hw);
3996 /* read-on-clear nic registers here */
3997 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3998 PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
4002 /* set flag for async link update */
4003 if (eicr & IXGBE_EICR_LSC)
4004 intr->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4006 if (eicr & IXGBE_EICR_MAILBOX)
4007 intr->flags |= IXGBE_FLAG_MAILBOX;
4009 if (eicr & IXGBE_EICR_LINKSEC)
4010 intr->flags |= IXGBE_FLAG_MACSEC;
4012 if (hw->mac.type == ixgbe_mac_X550EM_x &&
4013 hw->phy.type == ixgbe_phy_x550em_ext_t &&
4014 (eicr & IXGBE_EICR_GPI_SDP0_X550EM_x))
4015 intr->flags |= IXGBE_FLAG_PHY_INTERRUPT;
4021 * It gets and then prints the link status.
4024 * Pointer to struct rte_eth_dev.
4027 * - On success, zero.
4028 * - On failure, a negative value.
4031 ixgbe_dev_link_status_print(struct rte_eth_dev *dev)
4033 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4034 struct rte_eth_link link;
4036 memset(&link, 0, sizeof(link));
4037 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4038 if (link.link_status) {
4039 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
4040 (int)(dev->data->port_id),
4041 (unsigned)link.link_speed,
4042 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
4043 "full-duplex" : "half-duplex");
4045 PMD_INIT_LOG(INFO, " Port %d: Link Down",
4046 (int)(dev->data->port_id));
4048 PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
4049 pci_dev->addr.domain,
4051 pci_dev->addr.devid,
4052 pci_dev->addr.function);
4056 * It executes link_update after knowing an interrupt occurred.
4059 * Pointer to struct rte_eth_dev.
4062 * - On success, zero.
4063 * - On failure, a negative value.
4066 ixgbe_dev_interrupt_action(struct rte_eth_dev *dev,
4067 struct rte_intr_handle *intr_handle)
4069 struct ixgbe_interrupt *intr =
4070 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4072 struct rte_eth_link link;
4073 struct ixgbe_hw *hw =
4074 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4076 PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
4078 if (intr->flags & IXGBE_FLAG_MAILBOX) {
4079 ixgbe_pf_mbx_process(dev);
4080 intr->flags &= ~IXGBE_FLAG_MAILBOX;
4083 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4084 ixgbe_handle_lasi(hw);
4085 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4088 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4089 /* get the link status before link update, for predicting later */
4090 memset(&link, 0, sizeof(link));
4091 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
4093 ixgbe_dev_link_update(dev, 0);
4096 if (!link.link_status)
4097 /* handle it 1 sec later, wait it being stable */
4098 timeout = IXGBE_LINK_UP_CHECK_TIMEOUT;
4099 /* likely to down */
4101 /* handle it 4 sec later, wait it being stable */
4102 timeout = IXGBE_LINK_DOWN_CHECK_TIMEOUT;
4104 ixgbe_dev_link_status_print(dev);
4105 if (rte_eal_alarm_set(timeout * 1000,
4106 ixgbe_dev_interrupt_delayed_handler, (void *)dev) < 0)
4107 PMD_DRV_LOG(ERR, "Error setting alarm");
4109 /* remember original mask */
4110 intr->mask_original = intr->mask;
4111 /* only disable lsc interrupt */
4112 intr->mask &= ~IXGBE_EIMS_LSC;
4116 PMD_DRV_LOG(DEBUG, "enable intr immediately");
4117 ixgbe_enable_intr(dev);
4118 rte_intr_enable(intr_handle);
4124 * Interrupt handler which shall be registered for alarm callback for delayed
4125 * handling specific interrupt to wait for the stable nic state. As the
4126 * NIC interrupt state is not stable for ixgbe after link is just down,
4127 * it needs to wait 4 seconds to get the stable status.
4130 * Pointer to interrupt handle.
4132 * The address of parameter (struct rte_eth_dev *) regsitered before.
4138 ixgbe_dev_interrupt_delayed_handler(void *param)
4140 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4141 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4142 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4143 struct ixgbe_interrupt *intr =
4144 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
4145 struct ixgbe_hw *hw =
4146 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4149 ixgbe_disable_intr(hw);
4151 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
4152 if (eicr & IXGBE_EICR_MAILBOX)
4153 ixgbe_pf_mbx_process(dev);
4155 if (intr->flags & IXGBE_FLAG_PHY_INTERRUPT) {
4156 ixgbe_handle_lasi(hw);
4157 intr->flags &= ~IXGBE_FLAG_PHY_INTERRUPT;
4160 if (intr->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4161 ixgbe_dev_link_update(dev, 0);
4162 intr->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4163 ixgbe_dev_link_status_print(dev);
4164 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
4168 if (intr->flags & IXGBE_FLAG_MACSEC) {
4169 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
4171 intr->flags &= ~IXGBE_FLAG_MACSEC;
4174 /* restore original mask */
4175 intr->mask = intr->mask_original;
4176 intr->mask_original = 0;
4178 PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
4179 ixgbe_enable_intr(dev);
4180 rte_intr_enable(intr_handle);
4184 * Interrupt handler triggered by NIC for handling
4185 * specific interrupt.
4188 * Pointer to interrupt handle.
4190 * The address of parameter (struct rte_eth_dev *) regsitered before.
4196 ixgbe_dev_interrupt_handler(void *param)
4198 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4200 ixgbe_dev_interrupt_get_status(dev);
4201 ixgbe_dev_interrupt_action(dev, dev->intr_handle);
4205 ixgbe_dev_led_on(struct rte_eth_dev *dev)
4207 struct ixgbe_hw *hw;
4209 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4210 return ixgbe_led_on(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4214 ixgbe_dev_led_off(struct rte_eth_dev *dev)
4216 struct ixgbe_hw *hw;
4218 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4219 return ixgbe_led_off(hw, 0) == IXGBE_SUCCESS ? 0 : -ENOTSUP;
4223 ixgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4225 struct ixgbe_hw *hw;
4231 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4233 fc_conf->pause_time = hw->fc.pause_time;
4234 fc_conf->high_water = hw->fc.high_water[0];
4235 fc_conf->low_water = hw->fc.low_water[0];
4236 fc_conf->send_xon = hw->fc.send_xon;
4237 fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
4240 * Return rx_pause status according to actual setting of
4243 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4244 if (mflcn_reg & (IXGBE_MFLCN_RPFCE | IXGBE_MFLCN_RFCE))
4250 * Return tx_pause status according to actual setting of
4253 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4254 if (fccfg_reg & (IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY))
4259 if (rx_pause && tx_pause)
4260 fc_conf->mode = RTE_FC_FULL;
4262 fc_conf->mode = RTE_FC_RX_PAUSE;
4264 fc_conf->mode = RTE_FC_TX_PAUSE;
4266 fc_conf->mode = RTE_FC_NONE;
4272 ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4274 struct ixgbe_hw *hw;
4276 uint32_t rx_buf_size;
4277 uint32_t max_high_water;
4279 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4286 PMD_INIT_FUNC_TRACE();
4288 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4289 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0));
4290 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4293 * At least reserve one Ethernet frame for watermark
4294 * high_water/low_water in kilo bytes for ixgbe
4296 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4297 if ((fc_conf->high_water > max_high_water) ||
4298 (fc_conf->high_water < fc_conf->low_water)) {
4299 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4300 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4304 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[fc_conf->mode];
4305 hw->fc.pause_time = fc_conf->pause_time;
4306 hw->fc.high_water[0] = fc_conf->high_water;
4307 hw->fc.low_water[0] = fc_conf->low_water;
4308 hw->fc.send_xon = fc_conf->send_xon;
4309 hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
4311 err = ixgbe_fc_enable(hw);
4313 /* Not negotiated is not an error case */
4314 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) {
4316 /* check if we want to forward MAC frames - driver doesn't have native
4317 * capability to do that, so we'll write the registers ourselves */
4319 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4321 /* set or clear MFLCN.PMCF bit depending on configuration */
4322 if (fc_conf->mac_ctrl_frame_fwd != 0)
4323 mflcn |= IXGBE_MFLCN_PMCF;
4325 mflcn &= ~IXGBE_MFLCN_PMCF;
4327 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn);
4328 IXGBE_WRITE_FLUSH(hw);
4333 PMD_INIT_LOG(ERR, "ixgbe_fc_enable = 0x%x", err);
4338 * ixgbe_pfc_enable_generic - Enable flow control
4339 * @hw: pointer to hardware structure
4340 * @tc_num: traffic class number
4341 * Enable flow control according to the current settings.
4344 ixgbe_dcb_pfc_enable_generic(struct ixgbe_hw *hw, uint8_t tc_num)
4347 uint32_t mflcn_reg, fccfg_reg;
4349 uint32_t fcrtl, fcrth;
4353 /* Validate the water mark configuration */
4354 if (!hw->fc.pause_time) {
4355 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4359 /* Low water mark of zero causes XOFF floods */
4360 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
4361 /* High/Low water can not be 0 */
4362 if ((!hw->fc.high_water[tc_num]) || (!hw->fc.low_water[tc_num])) {
4363 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4364 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4368 if (hw->fc.low_water[tc_num] >= hw->fc.high_water[tc_num]) {
4369 PMD_INIT_LOG(ERR, "Invalid water mark configuration");
4370 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
4374 /* Negotiate the fc mode to use */
4375 ixgbe_fc_autoneg(hw);
4377 /* Disable any previous flow control settings */
4378 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4379 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_SHIFT | IXGBE_MFLCN_RFCE|IXGBE_MFLCN_RPFCE);
4381 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4382 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
4384 switch (hw->fc.current_mode) {
4387 * If the count of enabled RX Priority Flow control >1,
4388 * and the TX pause can not be disabled
4391 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4392 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4393 if (reg & IXGBE_FCRTH_FCEN)
4397 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4399 case ixgbe_fc_rx_pause:
4401 * Rx Flow control is enabled and Tx Flow control is
4402 * disabled by software override. Since there really
4403 * isn't a way to advertise that we are capable of RX
4404 * Pause ONLY, we will advertise that we support both
4405 * symmetric and asymmetric Rx PAUSE. Later, we will
4406 * disable the adapter's ability to send PAUSE frames.
4408 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4410 * If the count of enabled RX Priority Flow control >1,
4411 * and the TX pause can not be disabled
4414 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
4415 reg = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
4416 if (reg & IXGBE_FCRTH_FCEN)
4420 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4422 case ixgbe_fc_tx_pause:
4424 * Tx Flow control is enabled, and Rx Flow control is
4425 * disabled by software override.
4427 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4430 /* Flow control (both Rx and Tx) is enabled by SW override. */
4431 mflcn_reg |= IXGBE_MFLCN_RPFCE;
4432 fccfg_reg |= IXGBE_FCCFG_TFCE_PRIORITY;
4435 PMD_DRV_LOG(DEBUG, "Flow control param set incorrectly");
4436 ret_val = IXGBE_ERR_CONFIG;
4440 /* Set 802.3x based flow control settings. */
4441 mflcn_reg |= IXGBE_MFLCN_DPF;
4442 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
4443 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
4445 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
4446 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
4447 hw->fc.high_water[tc_num]) {
4448 fcrtl = (hw->fc.low_water[tc_num] << 10) | IXGBE_FCRTL_XONE;
4449 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), fcrtl);
4450 fcrth = (hw->fc.high_water[tc_num] << 10) | IXGBE_FCRTH_FCEN;
4452 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(tc_num), 0);
4454 * In order to prevent Tx hangs when the internal Tx
4455 * switch is enabled we must set the high water mark
4456 * to the maximum FCRTH value. This allows the Tx
4457 * switch to function even under heavy Rx workloads.
4459 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num)) - 32;
4461 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(tc_num), fcrth);
4463 /* Configure pause time (2 TCs per register) */
4464 reg = hw->fc.pause_time * 0x00010001;
4465 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
4466 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
4468 /* Configure flow control refresh threshold value */
4469 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
4476 ixgbe_dcb_pfc_enable(struct rte_eth_dev *dev, uint8_t tc_num)
4478 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4479 int32_t ret_val = IXGBE_NOT_IMPLEMENTED;
4481 if (hw->mac.type != ixgbe_mac_82598EB) {
4482 ret_val = ixgbe_dcb_pfc_enable_generic(hw, tc_num);
4488 ixgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_pfc_conf *pfc_conf)
4491 uint32_t rx_buf_size;
4492 uint32_t max_high_water;
4494 uint8_t map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
4495 struct ixgbe_hw *hw =
4496 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497 struct ixgbe_dcb_config *dcb_config =
4498 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
4500 enum ixgbe_fc_mode rte_fcmode_2_ixgbe_fcmode[] = {
4507 PMD_INIT_FUNC_TRACE();
4509 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
4510 tc_num = map[pfc_conf->priority];
4511 rx_buf_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc_num));
4512 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
4514 * At least reserve one Ethernet frame for watermark
4515 * high_water/low_water in kilo bytes for ixgbe
4517 max_high_water = (rx_buf_size - ETHER_MAX_LEN) >> IXGBE_RXPBSIZE_SHIFT;
4518 if ((pfc_conf->fc.high_water > max_high_water) ||
4519 (pfc_conf->fc.high_water <= pfc_conf->fc.low_water)) {
4520 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
4521 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
4525 hw->fc.requested_mode = rte_fcmode_2_ixgbe_fcmode[pfc_conf->fc.mode];
4526 hw->fc.pause_time = pfc_conf->fc.pause_time;
4527 hw->fc.send_xon = pfc_conf->fc.send_xon;
4528 hw->fc.low_water[tc_num] = pfc_conf->fc.low_water;
4529 hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
4531 err = ixgbe_dcb_pfc_enable(dev, tc_num);
4533 /* Not negotiated is not an error case */
4534 if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED))
4537 PMD_INIT_LOG(ERR, "ixgbe_dcb_pfc_enable = 0x%x", err);
4542 ixgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
4543 struct rte_eth_rss_reta_entry64 *reta_conf,
4546 uint16_t i, sp_reta_size;
4549 uint16_t idx, shift;
4550 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4553 PMD_INIT_FUNC_TRACE();
4555 if (!ixgbe_rss_update_sp(hw->mac.type)) {
4556 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
4561 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4562 if (reta_size != sp_reta_size) {
4563 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4564 "(%d) doesn't match the number hardware can supported "
4565 "(%d)", reta_size, sp_reta_size);
4569 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4570 idx = i / RTE_RETA_GROUP_SIZE;
4571 shift = i % RTE_RETA_GROUP_SIZE;
4572 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4576 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4577 if (mask == IXGBE_4_BIT_MASK)
4580 r = IXGBE_READ_REG(hw, reta_reg);
4581 for (j = 0, reta = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4582 if (mask & (0x1 << j))
4583 reta |= reta_conf[idx].reta[shift + j] <<
4586 reta |= r & (IXGBE_8_BIT_MASK <<
4589 IXGBE_WRITE_REG(hw, reta_reg, reta);
4596 ixgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
4597 struct rte_eth_rss_reta_entry64 *reta_conf,
4600 uint16_t i, sp_reta_size;
4603 uint16_t idx, shift;
4604 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4607 PMD_INIT_FUNC_TRACE();
4608 sp_reta_size = ixgbe_reta_size_get(hw->mac.type);
4609 if (reta_size != sp_reta_size) {
4610 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
4611 "(%d) doesn't match the number hardware can supported "
4612 "(%d)", reta_size, sp_reta_size);
4616 for (i = 0; i < reta_size; i += IXGBE_4_BIT_WIDTH) {
4617 idx = i / RTE_RETA_GROUP_SIZE;
4618 shift = i % RTE_RETA_GROUP_SIZE;
4619 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
4624 reta_reg = ixgbe_reta_reg_get(hw->mac.type, i);
4625 reta = IXGBE_READ_REG(hw, reta_reg);
4626 for (j = 0; j < IXGBE_4_BIT_WIDTH; j++) {
4627 if (mask & (0x1 << j))
4628 reta_conf[idx].reta[shift + j] =
4629 ((reta >> (CHAR_BIT * j)) &
4638 ixgbe_add_rar(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
4639 uint32_t index, uint32_t pool)
4641 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4642 uint32_t enable_addr = 1;
4644 return ixgbe_set_rar(hw, index, mac_addr->addr_bytes,
4649 ixgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
4651 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4653 ixgbe_clear_rar(hw, index);
4657 ixgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
4659 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4661 ixgbe_remove_rar(dev, 0);
4663 ixgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
4667 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
4669 if (strcmp(dev->device->driver->name, drv->driver.name))
4676 is_ixgbe_supported(struct rte_eth_dev *dev)
4678 return is_device_supported(dev, &rte_ixgbe_pmd);
4682 ixgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
4686 struct ixgbe_hw *hw;
4687 struct rte_eth_dev_info dev_info;
4688 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
4689 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4691 ixgbe_dev_info_get(dev, &dev_info);
4693 /* check that mtu is within the allowed range */
4694 if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
4697 /* refuse mtu that requires the support of scattered packets when this
4698 * feature has not been enabled before.
4700 if (!rx_conf->enable_scatter &&
4701 (frame_size + 2 * IXGBE_VLAN_TAG_SIZE >
4702 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
4705 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4706 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4708 /* switch to jumbo mode if needed */
4709 if (frame_size > ETHER_MAX_LEN) {
4710 dev->data->dev_conf.rxmode.jumbo_frame = 1;
4711 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4713 dev->data->dev_conf.rxmode.jumbo_frame = 0;
4714 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4716 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4718 /* update max frame size */
4719 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
4721 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4722 maxfrs &= 0x0000FFFF;
4723 maxfrs |= (dev->data->dev_conf.rxmode.max_rx_pkt_len << 16);
4724 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4730 * Virtual Function operations
4733 ixgbevf_intr_disable(struct ixgbe_hw *hw)
4735 PMD_INIT_FUNC_TRACE();
4737 /* Clear interrupt mask to stop from interrupts being generated */
4738 IXGBE_WRITE_REG(hw, IXGBE_VTEIMC, IXGBE_VF_IRQ_CLEAR_MASK);
4740 IXGBE_WRITE_FLUSH(hw);
4744 ixgbevf_intr_enable(struct ixgbe_hw *hw)
4746 PMD_INIT_FUNC_TRACE();
4748 /* VF enable interrupt autoclean */
4749 IXGBE_WRITE_REG(hw, IXGBE_VTEIAM, IXGBE_VF_IRQ_ENABLE_MASK);
4750 IXGBE_WRITE_REG(hw, IXGBE_VTEIAC, IXGBE_VF_IRQ_ENABLE_MASK);
4751 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, IXGBE_VF_IRQ_ENABLE_MASK);
4753 IXGBE_WRITE_FLUSH(hw);
4757 ixgbevf_dev_configure(struct rte_eth_dev *dev)
4759 struct rte_eth_conf *conf = &dev->data->dev_conf;
4760 struct ixgbe_adapter *adapter =
4761 (struct ixgbe_adapter *)dev->data->dev_private;
4763 PMD_INIT_LOG(DEBUG, "Configured Virtual Function port id: %d",
4764 dev->data->port_id);
4767 * VF has no ability to enable/disable HW CRC
4768 * Keep the persistent behavior the same as Host PF
4770 #ifndef RTE_LIBRTE_IXGBE_PF_DISABLE_STRIP_CRC
4771 if (!conf->rxmode.hw_strip_crc) {
4772 PMD_INIT_LOG(NOTICE, "VF can't disable HW CRC Strip");
4773 conf->rxmode.hw_strip_crc = 1;
4776 if (conf->rxmode.hw_strip_crc) {
4777 PMD_INIT_LOG(NOTICE, "VF can't enable HW CRC Strip");
4778 conf->rxmode.hw_strip_crc = 0;
4783 * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
4784 * allocation or vector Rx preconditions we will reset it.
4786 adapter->rx_bulk_alloc_allowed = true;
4787 adapter->rx_vec_allowed = true;
4793 ixgbevf_dev_start(struct rte_eth_dev *dev)
4795 struct ixgbe_hw *hw =
4796 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4797 uint32_t intr_vector = 0;
4798 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4799 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4803 PMD_INIT_FUNC_TRACE();
4805 hw->mac.ops.reset_hw(hw);
4806 hw->mac.get_link_status = true;
4808 /* negotiate mailbox API version to use with the PF. */
4809 ixgbevf_negotiate_api(hw);
4811 ixgbevf_dev_tx_init(dev);
4813 /* This can fail when allocating mbufs for descriptor rings */
4814 err = ixgbevf_dev_rx_init(dev);
4816 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware (%d)", err);
4817 ixgbe_dev_clear_queues(dev);
4822 ixgbevf_set_vfta_all(dev, 1);
4825 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
4826 ETH_VLAN_EXTEND_MASK;
4827 ixgbevf_vlan_offload_set(dev, mask);
4829 ixgbevf_dev_rxtx_start(dev);
4831 /* check and configure queue intr-vector mapping */
4832 if (dev->data->dev_conf.intr_conf.rxq != 0) {
4833 intr_vector = dev->data->nb_rx_queues;
4834 if (rte_intr_efd_enable(intr_handle, intr_vector))
4838 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
4839 intr_handle->intr_vec =
4840 rte_zmalloc("intr_vec",
4841 dev->data->nb_rx_queues * sizeof(int), 0);
4842 if (intr_handle->intr_vec == NULL) {
4843 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
4844 " intr_vec", dev->data->nb_rx_queues);
4848 ixgbevf_configure_msix(dev);
4850 rte_intr_enable(intr_handle);
4852 /* Re-enable interrupt for VF */
4853 ixgbevf_intr_enable(hw);
4859 ixgbevf_dev_stop(struct rte_eth_dev *dev)
4861 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4862 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4863 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4865 PMD_INIT_FUNC_TRACE();
4867 ixgbevf_intr_disable(hw);
4869 hw->adapter_stopped = 1;
4870 ixgbe_stop_adapter(hw);
4873 * Clear what we set, but we still keep shadow_vfta to
4874 * restore after device starts
4876 ixgbevf_set_vfta_all(dev, 0);
4878 /* Clear stored conf */
4879 dev->data->scattered_rx = 0;
4881 ixgbe_dev_clear_queues(dev);
4883 /* Clean datapath event and queue/vec mapping */
4884 rte_intr_efd_disable(intr_handle);
4885 if (intr_handle->intr_vec != NULL) {
4886 rte_free(intr_handle->intr_vec);
4887 intr_handle->intr_vec = NULL;
4892 ixgbevf_dev_close(struct rte_eth_dev *dev)
4894 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4896 PMD_INIT_FUNC_TRACE();
4900 ixgbevf_dev_stop(dev);
4902 ixgbe_dev_free_queues(dev);
4905 * Remove the VF MAC address ro ensure
4906 * that the VF traffic goes to the PF
4907 * after stop, close and detach of the VF
4909 ixgbevf_remove_mac_addr(dev, 0);
4912 static void ixgbevf_set_vfta_all(struct rte_eth_dev *dev, bool on)
4914 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4915 struct ixgbe_vfta *shadow_vfta =
4916 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4917 int i = 0, j = 0, vfta = 0, mask = 1;
4919 for (i = 0; i < IXGBE_VFTA_SIZE; i++) {
4920 vfta = shadow_vfta->vfta[i];
4923 for (j = 0; j < 32; j++) {
4925 ixgbe_set_vfta(hw, (i<<5)+j, 0,
4935 ixgbevf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
4937 struct ixgbe_hw *hw =
4938 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4939 struct ixgbe_vfta *shadow_vfta =
4940 IXGBE_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
4941 uint32_t vid_idx = 0;
4942 uint32_t vid_bit = 0;
4945 PMD_INIT_FUNC_TRACE();
4947 /* vind is not used in VF driver, set to 0, check ixgbe_set_vfta_vf */
4948 ret = ixgbe_set_vfta(hw, vlan_id, 0, !!on, false);
4950 PMD_INIT_LOG(ERR, "Unable to set VF vlan");
4953 vid_idx = (uint32_t) ((vlan_id >> 5) & 0x7F);
4954 vid_bit = (uint32_t) (1 << (vlan_id & 0x1F));
4956 /* Save what we set and retore it after device reset */
4958 shadow_vfta->vfta[vid_idx] |= vid_bit;
4960 shadow_vfta->vfta[vid_idx] &= ~vid_bit;
4966 ixgbevf_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
4968 struct ixgbe_hw *hw =
4969 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4972 PMD_INIT_FUNC_TRACE();
4974 if (queue >= hw->mac.max_rx_queues)
4977 ctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(queue));
4979 ctrl |= IXGBE_RXDCTL_VME;
4981 ctrl &= ~IXGBE_RXDCTL_VME;
4982 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(queue), ctrl);
4984 ixgbe_vlan_hw_strip_bitmap_set(dev, queue, on);
4988 ixgbevf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4990 struct ixgbe_hw *hw =
4991 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4995 /* VF function only support hw strip feature, others are not support */
4996 if (mask & ETH_VLAN_STRIP_MASK) {
4997 on = !!(dev->data->dev_conf.rxmode.hw_vlan_strip);
4999 for (i = 0; i < hw->mac.max_rx_queues; i++)
5000 ixgbevf_vlan_strip_queue_set(dev, i, on);
5005 ixgbe_vt_check(struct ixgbe_hw *hw)
5009 /* if Virtualization Technology is enabled */
5010 reg_val = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
5011 if (!(reg_val & IXGBE_VT_CTL_VT_ENABLE)) {
5012 PMD_INIT_LOG(ERR, "VT must be enabled for this setting");
5020 ixgbe_uta_vector(struct ixgbe_hw *hw, struct ether_addr *uc_addr)
5022 uint32_t vector = 0;
5024 switch (hw->mac.mc_filter_type) {
5025 case 0: /* use bits [47:36] of the address */
5026 vector = ((uc_addr->addr_bytes[4] >> 4) |
5027 (((uint16_t)uc_addr->addr_bytes[5]) << 4));
5029 case 1: /* use bits [46:35] of the address */
5030 vector = ((uc_addr->addr_bytes[4] >> 3) |
5031 (((uint16_t)uc_addr->addr_bytes[5]) << 5));
5033 case 2: /* use bits [45:34] of the address */
5034 vector = ((uc_addr->addr_bytes[4] >> 2) |
5035 (((uint16_t)uc_addr->addr_bytes[5]) << 6));
5037 case 3: /* use bits [43:32] of the address */
5038 vector = ((uc_addr->addr_bytes[4]) |
5039 (((uint16_t)uc_addr->addr_bytes[5]) << 8));
5041 default: /* Invalid mc_filter_type */
5045 /* vector can only be 12-bits or boundary will be exceeded */
5051 ixgbe_uc_hash_table_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5059 const uint32_t ixgbe_uta_idx_mask = 0x7F;
5060 const uint32_t ixgbe_uta_bit_shift = 5;
5061 const uint32_t ixgbe_uta_bit_mask = (0x1 << ixgbe_uta_bit_shift) - 1;
5062 const uint32_t bit1 = 0x1;
5064 struct ixgbe_hw *hw =
5065 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5066 struct ixgbe_uta_info *uta_info =
5067 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5069 /* The UTA table only exists on 82599 hardware and newer */
5070 if (hw->mac.type < ixgbe_mac_82599EB)
5073 vector = ixgbe_uta_vector(hw, mac_addr);
5074 uta_idx = (vector >> ixgbe_uta_bit_shift) & ixgbe_uta_idx_mask;
5075 uta_shift = vector & ixgbe_uta_bit_mask;
5077 rc = ((uta_info->uta_shadow[uta_idx] >> uta_shift & bit1) != 0);
5081 reg_val = IXGBE_READ_REG(hw, IXGBE_UTA(uta_idx));
5083 uta_info->uta_in_use++;
5084 reg_val |= (bit1 << uta_shift);
5085 uta_info->uta_shadow[uta_idx] |= (bit1 << uta_shift);
5087 uta_info->uta_in_use--;
5088 reg_val &= ~(bit1 << uta_shift);
5089 uta_info->uta_shadow[uta_idx] &= ~(bit1 << uta_shift);
5092 IXGBE_WRITE_REG(hw, IXGBE_UTA(uta_idx), reg_val);
5094 if (uta_info->uta_in_use > 0)
5095 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
5096 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
5098 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
5104 ixgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
5107 struct ixgbe_hw *hw =
5108 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5109 struct ixgbe_uta_info *uta_info =
5110 IXGBE_DEV_PRIVATE_TO_UTA(dev->data->dev_private);
5112 /* The UTA table only exists on 82599 hardware and newer */
5113 if (hw->mac.type < ixgbe_mac_82599EB)
5117 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5118 uta_info->uta_shadow[i] = ~0;
5119 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
5122 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
5123 uta_info->uta_shadow[i] = 0;
5124 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
5132 ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
5134 uint32_t new_val = orig_val;
5136 if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
5137 new_val |= IXGBE_VMOLR_AUPE;
5138 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
5139 new_val |= IXGBE_VMOLR_ROMPE;
5140 if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
5141 new_val |= IXGBE_VMOLR_ROPE;
5142 if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
5143 new_val |= IXGBE_VMOLR_BAM;
5144 if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
5145 new_val |= IXGBE_VMOLR_MPE;
5150 #define IXGBE_MRCTL_VPME 0x01 /* Virtual Pool Mirroring. */
5151 #define IXGBE_MRCTL_UPME 0x02 /* Uplink Port Mirroring. */
5152 #define IXGBE_MRCTL_DPME 0x04 /* Downlink Port Mirroring. */
5153 #define IXGBE_MRCTL_VLME 0x08 /* VLAN Mirroring. */
5154 #define IXGBE_INVALID_MIRROR_TYPE(mirror_type) \
5155 ((mirror_type) & ~(uint8_t)(ETH_MIRROR_VIRTUAL_POOL_UP | \
5156 ETH_MIRROR_UPLINK_PORT | ETH_MIRROR_DOWNLINK_PORT | ETH_MIRROR_VLAN))
5159 ixgbe_mirror_rule_set(struct rte_eth_dev *dev,
5160 struct rte_eth_mirror_conf *mirror_conf,
5161 uint8_t rule_id, uint8_t on)
5163 uint32_t mr_ctl, vlvf;
5164 uint32_t mp_lsb = 0;
5165 uint32_t mv_msb = 0;
5166 uint32_t mv_lsb = 0;
5167 uint32_t mp_msb = 0;
5170 uint64_t vlan_mask = 0;
5172 const uint8_t pool_mask_offset = 32;
5173 const uint8_t vlan_mask_offset = 32;
5174 const uint8_t dst_pool_offset = 8;
5175 const uint8_t rule_mr_offset = 4;
5176 const uint8_t mirror_rule_mask = 0x0F;
5178 struct ixgbe_mirror_info *mr_info =
5179 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5180 struct ixgbe_hw *hw =
5181 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5182 uint8_t mirror_type = 0;
5184 if (ixgbe_vt_check(hw) < 0)
5187 if (rule_id >= IXGBE_MAX_MIRROR_RULES)
5190 if (IXGBE_INVALID_MIRROR_TYPE(mirror_conf->rule_type)) {
5191 PMD_DRV_LOG(ERR, "unsupported mirror type 0x%x.",
5192 mirror_conf->rule_type);
5196 if (mirror_conf->rule_type & ETH_MIRROR_VLAN) {
5197 mirror_type |= IXGBE_MRCTL_VLME;
5198 /* Check if vlan id is valid and find conresponding VLAN ID
5201 for (i = 0; i < IXGBE_VLVF_ENTRIES; i++) {
5202 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
5203 /* search vlan id related pool vlan filter
5206 reg_index = ixgbe_find_vlvf_slot(
5208 mirror_conf->vlan.vlan_id[i],
5212 vlvf = IXGBE_READ_REG(hw,
5213 IXGBE_VLVF(reg_index));
5214 if ((vlvf & IXGBE_VLVF_VIEN) &&
5215 ((vlvf & IXGBE_VLVF_VLANID_MASK) ==
5216 mirror_conf->vlan.vlan_id[i]))
5217 vlan_mask |= (1ULL << reg_index);
5224 mv_lsb = vlan_mask & 0xFFFFFFFF;
5225 mv_msb = vlan_mask >> vlan_mask_offset;
5227 mr_info->mr_conf[rule_id].vlan.vlan_mask =
5228 mirror_conf->vlan.vlan_mask;
5229 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++) {
5230 if (mirror_conf->vlan.vlan_mask & (1ULL << i))
5231 mr_info->mr_conf[rule_id].vlan.vlan_id[i] =
5232 mirror_conf->vlan.vlan_id[i];
5237 mr_info->mr_conf[rule_id].vlan.vlan_mask = 0;
5238 for (i = 0; i < ETH_VMDQ_MAX_VLAN_FILTERS; i++)
5239 mr_info->mr_conf[rule_id].vlan.vlan_id[i] = 0;
5244 * if enable pool mirror, write related pool mask register,if disable
5245 * pool mirror, clear PFMRVM register
5247 if (mirror_conf->rule_type & ETH_MIRROR_VIRTUAL_POOL_UP) {
5248 mirror_type |= IXGBE_MRCTL_VPME;
5250 mp_lsb = mirror_conf->pool_mask & 0xFFFFFFFF;
5251 mp_msb = mirror_conf->pool_mask >> pool_mask_offset;
5252 mr_info->mr_conf[rule_id].pool_mask =
5253 mirror_conf->pool_mask;
5258 mr_info->mr_conf[rule_id].pool_mask = 0;
5261 if (mirror_conf->rule_type & ETH_MIRROR_UPLINK_PORT)
5262 mirror_type |= IXGBE_MRCTL_UPME;
5263 if (mirror_conf->rule_type & ETH_MIRROR_DOWNLINK_PORT)
5264 mirror_type |= IXGBE_MRCTL_DPME;
5266 /* read mirror control register and recalculate it */
5267 mr_ctl = IXGBE_READ_REG(hw, IXGBE_MRCTL(rule_id));
5270 mr_ctl |= mirror_type;
5271 mr_ctl &= mirror_rule_mask;
5272 mr_ctl |= mirror_conf->dst_pool << dst_pool_offset;
5274 mr_ctl &= ~(mirror_conf->rule_type & mirror_rule_mask);
5277 mr_info->mr_conf[rule_id].rule_type = mirror_conf->rule_type;
5278 mr_info->mr_conf[rule_id].dst_pool = mirror_conf->dst_pool;
5280 /* write mirrror control register */
5281 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5283 /* write pool mirrror control register */
5284 if (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) {
5285 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), mp_lsb);
5286 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset),
5289 /* write VLAN mirrror control register */
5290 if (mirror_conf->rule_type == ETH_MIRROR_VLAN) {
5291 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), mv_lsb);
5292 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset),
5300 ixgbe_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t rule_id)
5303 uint32_t lsb_val = 0;
5304 uint32_t msb_val = 0;
5305 const uint8_t rule_mr_offset = 4;
5307 struct ixgbe_hw *hw =
5308 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5309 struct ixgbe_mirror_info *mr_info =
5310 (IXGBE_DEV_PRIVATE_TO_PFDATA(dev->data->dev_private));
5312 if (ixgbe_vt_check(hw) < 0)
5315 memset(&mr_info->mr_conf[rule_id], 0,
5316 sizeof(struct rte_eth_mirror_conf));
5318 /* clear PFVMCTL register */
5319 IXGBE_WRITE_REG(hw, IXGBE_MRCTL(rule_id), mr_ctl);
5321 /* clear pool mask register */
5322 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id), lsb_val);
5323 IXGBE_WRITE_REG(hw, IXGBE_VMRVM(rule_id + rule_mr_offset), msb_val);
5325 /* clear vlan mask register */
5326 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id), lsb_val);
5327 IXGBE_WRITE_REG(hw, IXGBE_VMRVLAN(rule_id + rule_mr_offset), msb_val);
5333 ixgbevf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5335 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5336 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5338 struct ixgbe_hw *hw =
5339 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5341 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5342 mask |= (1 << IXGBE_MISC_VEC_ID);
5343 RTE_SET_USED(queue_id);
5344 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5346 rte_intr_enable(intr_handle);
5352 ixgbevf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5355 struct ixgbe_hw *hw =
5356 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5358 mask = IXGBE_READ_REG(hw, IXGBE_VTEIMS);
5359 mask &= ~(1 << IXGBE_MISC_VEC_ID);
5360 RTE_SET_USED(queue_id);
5361 IXGBE_WRITE_REG(hw, IXGBE_VTEIMS, mask);
5367 ixgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
5369 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5370 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5372 struct ixgbe_hw *hw =
5373 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5374 struct ixgbe_interrupt *intr =
5375 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5377 if (queue_id < 16) {
5378 ixgbe_disable_intr(hw);
5379 intr->mask |= (1 << queue_id);
5380 ixgbe_enable_intr(dev);
5381 } else if (queue_id < 32) {
5382 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5383 mask &= (1 << queue_id);
5384 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5385 } else if (queue_id < 64) {
5386 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5387 mask &= (1 << (queue_id - 32));
5388 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5390 rte_intr_enable(intr_handle);
5396 ixgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
5399 struct ixgbe_hw *hw =
5400 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5401 struct ixgbe_interrupt *intr =
5402 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
5404 if (queue_id < 16) {
5405 ixgbe_disable_intr(hw);
5406 intr->mask &= ~(1 << queue_id);
5407 ixgbe_enable_intr(dev);
5408 } else if (queue_id < 32) {
5409 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(0));
5410 mask &= ~(1 << queue_id);
5411 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
5412 } else if (queue_id < 64) {
5413 mask = IXGBE_READ_REG(hw, IXGBE_EIMS_EX(1));
5414 mask &= ~(1 << (queue_id - 32));
5415 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
5422 ixgbevf_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5423 uint8_t queue, uint8_t msix_vector)
5427 if (direction == -1) {
5429 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5430 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR_MISC);
5433 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR_MISC, tmp);
5435 /* rx or tx cause */
5436 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5437 idx = ((16 * (queue & 1)) + (8 * direction));
5438 tmp = IXGBE_READ_REG(hw, IXGBE_VTIVAR(queue >> 1));
5439 tmp &= ~(0xFF << idx);
5440 tmp |= (msix_vector << idx);
5441 IXGBE_WRITE_REG(hw, IXGBE_VTIVAR(queue >> 1), tmp);
5446 * set the IVAR registers, mapping interrupt causes to vectors
5448 * pointer to ixgbe_hw struct
5450 * 0 for Rx, 1 for Tx, -1 for other causes
5452 * queue to map the corresponding interrupt to
5454 * the vector to map to the corresponding queue
5457 ixgbe_set_ivar_map(struct ixgbe_hw *hw, int8_t direction,
5458 uint8_t queue, uint8_t msix_vector)
5462 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
5463 if (hw->mac.type == ixgbe_mac_82598EB) {
5464 if (direction == -1)
5466 idx = (((direction * 64) + queue) >> 2) & 0x1F;
5467 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(idx));
5468 tmp &= ~(0xFF << (8 * (queue & 0x3)));
5469 tmp |= (msix_vector << (8 * (queue & 0x3)));
5470 IXGBE_WRITE_REG(hw, IXGBE_IVAR(idx), tmp);
5471 } else if ((hw->mac.type == ixgbe_mac_82599EB) ||
5472 (hw->mac.type == ixgbe_mac_X540)) {
5473 if (direction == -1) {
5475 idx = ((queue & 1) * 8);
5476 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
5477 tmp &= ~(0xFF << idx);
5478 tmp |= (msix_vector << idx);
5479 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, tmp);
5481 /* rx or tx causes */
5482 idx = ((16 * (queue & 1)) + (8 * direction));
5483 tmp = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
5484 tmp &= ~(0xFF << idx);
5485 tmp |= (msix_vector << idx);
5486 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), tmp);
5492 ixgbevf_configure_msix(struct rte_eth_dev *dev)
5494 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5495 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5496 struct ixgbe_hw *hw =
5497 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5499 uint32_t vector_idx = IXGBE_MISC_VEC_ID;
5501 /* Configure VF other cause ivar */
5502 ixgbevf_set_ivar_map(hw, -1, 1, vector_idx);
5504 /* won't configure msix register if no mapping is done
5505 * between intr vector and event fd.
5507 if (!rte_intr_dp_is_en(intr_handle))
5510 /* Configure all RX queues of VF */
5511 for (q_idx = 0; q_idx < dev->data->nb_rx_queues; q_idx++) {
5512 /* Force all queue use vector 0,
5513 * as IXGBE_VF_MAXMSIVECOTR = 1
5515 ixgbevf_set_ivar_map(hw, 0, q_idx, vector_idx);
5516 intr_handle->intr_vec[q_idx] = vector_idx;
5521 * Sets up the hardware to properly generate MSI-X interrupts
5523 * board private structure
5526 ixgbe_configure_msix(struct rte_eth_dev *dev)
5528 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
5529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
5530 struct ixgbe_hw *hw =
5531 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5532 uint32_t queue_id, base = IXGBE_MISC_VEC_ID;
5533 uint32_t vec = IXGBE_MISC_VEC_ID;
5537 /* won't configure msix register if no mapping is done
5538 * between intr vector and event fd
5540 if (!rte_intr_dp_is_en(intr_handle))
5543 if (rte_intr_allow_others(intr_handle))
5544 vec = base = IXGBE_RX_VEC_START;
5546 /* setup GPIE for MSI-x mode */
5547 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
5548 gpie |= IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5549 IXGBE_GPIE_OCD | IXGBE_GPIE_EIAME;
5550 /* auto clearing and auto setting corresponding bits in EIMS
5551 * when MSI-X interrupt is triggered
5553 if (hw->mac.type == ixgbe_mac_82598EB) {
5554 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5556 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5557 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5559 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5561 /* Populate the IVAR table and set the ITR values to the
5562 * corresponding register.
5564 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
5566 /* by default, 1:1 mapping */
5567 ixgbe_set_ivar_map(hw, 0, queue_id, vec);
5568 intr_handle->intr_vec[queue_id] = vec;
5569 if (vec < base + intr_handle->nb_efd - 1)
5573 switch (hw->mac.type) {
5574 case ixgbe_mac_82598EB:
5575 ixgbe_set_ivar_map(hw, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
5578 case ixgbe_mac_82599EB:
5579 case ixgbe_mac_X540:
5580 ixgbe_set_ivar_map(hw, -1, 1, IXGBE_MISC_VEC_ID);
5585 IXGBE_WRITE_REG(hw, IXGBE_EITR(IXGBE_MISC_VEC_ID),
5586 IXGBE_MIN_INTER_INTERRUPT_INTERVAL_DEFAULT & 0xFFF);
5588 /* set up to autoclear timer, and the vectors */
5589 mask = IXGBE_EIMS_ENABLE_MASK;
5590 mask &= ~(IXGBE_EIMS_OTHER |
5591 IXGBE_EIMS_MAILBOX |
5594 IXGBE_WRITE_REG(hw, IXGBE_EIAC, mask);
5597 static int ixgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
5598 uint16_t queue_idx, uint16_t tx_rate)
5600 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5601 uint32_t rf_dec, rf_int;
5603 uint16_t link_speed = dev->data->dev_link.link_speed;
5605 if (queue_idx >= hw->mac.max_tx_queues)
5609 /* Calculate the rate factor values to set */
5610 rf_int = (uint32_t)link_speed / (uint32_t)tx_rate;
5611 rf_dec = (uint32_t)link_speed % (uint32_t)tx_rate;
5612 rf_dec = (rf_dec << IXGBE_RTTBCNRC_RF_INT_SHIFT) / tx_rate;
5614 bcnrc_val = IXGBE_RTTBCNRC_RS_ENA;
5615 bcnrc_val |= ((rf_int << IXGBE_RTTBCNRC_RF_INT_SHIFT) &
5616 IXGBE_RTTBCNRC_RF_INT_MASK_M);
5617 bcnrc_val |= (rf_dec & IXGBE_RTTBCNRC_RF_DEC_MASK);
5623 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
5624 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported, otherwise
5627 if ((dev->data->dev_conf.rxmode.jumbo_frame == 1) &&
5628 (dev->data->dev_conf.rxmode.max_rx_pkt_len >=
5629 IXGBE_MAX_JUMBO_FRAME_SIZE))
5630 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5631 IXGBE_MMW_SIZE_JUMBO_FRAME);
5633 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRM,
5634 IXGBE_MMW_SIZE_DEFAULT);
5636 /* Set RTTBCNRC of queue X */
5637 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_idx);
5638 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
5639 IXGBE_WRITE_FLUSH(hw);
5645 ixgbevf_add_mac_addr(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
5646 __attribute__((unused)) uint32_t index,
5647 __attribute__((unused)) uint32_t pool)
5649 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5653 * On a 82599 VF, adding again the same MAC addr is not an idempotent
5654 * operation. Trap this case to avoid exhausting the [very limited]
5655 * set of PF resources used to store VF MAC addresses.
5657 if (memcmp(hw->mac.perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5659 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5661 PMD_DRV_LOG(ERR, "Unable to add MAC address "
5662 "%02x:%02x:%02x:%02x:%02x:%02x - diag=%d",
5663 mac_addr->addr_bytes[0],
5664 mac_addr->addr_bytes[1],
5665 mac_addr->addr_bytes[2],
5666 mac_addr->addr_bytes[3],
5667 mac_addr->addr_bytes[4],
5668 mac_addr->addr_bytes[5],
5674 ixgbevf_remove_mac_addr(struct rte_eth_dev *dev, uint32_t index)
5676 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5677 struct ether_addr *perm_addr = (struct ether_addr *) hw->mac.perm_addr;
5678 struct ether_addr *mac_addr;
5683 * The IXGBE_VF_SET_MACVLAN command of the ixgbe-pf driver does
5684 * not support the deletion of a given MAC address.
5685 * Instead, it imposes to delete all MAC addresses, then to add again
5686 * all MAC addresses with the exception of the one to be deleted.
5688 (void) ixgbevf_set_uc_addr_vf(hw, 0, NULL);
5691 * Add again all MAC addresses, with the exception of the deleted one
5692 * and of the permanent MAC address.
5694 for (i = 0, mac_addr = dev->data->mac_addrs;
5695 i < hw->mac.num_rar_entries; i++, mac_addr++) {
5696 /* Skip the deleted MAC address */
5699 /* Skip NULL MAC addresses */
5700 if (is_zero_ether_addr(mac_addr))
5702 /* Skip the permanent MAC address */
5703 if (memcmp(perm_addr, mac_addr, sizeof(struct ether_addr)) == 0)
5705 diag = ixgbevf_set_uc_addr_vf(hw, 2, mac_addr->addr_bytes);
5708 "Adding again MAC address "
5709 "%02x:%02x:%02x:%02x:%02x:%02x failed "
5711 mac_addr->addr_bytes[0],
5712 mac_addr->addr_bytes[1],
5713 mac_addr->addr_bytes[2],
5714 mac_addr->addr_bytes[3],
5715 mac_addr->addr_bytes[4],
5716 mac_addr->addr_bytes[5],
5722 ixgbevf_set_default_mac_addr(struct rte_eth_dev *dev, struct ether_addr *addr)
5724 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5726 hw->mac.ops.set_rar(hw, 0, (void *)addr, 0, 0);
5730 ixgbe_syn_filter_set(struct rte_eth_dev *dev,
5731 struct rte_eth_syn_filter *filter,
5734 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5735 struct ixgbe_filter_info *filter_info =
5736 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5740 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
5743 syn_info = filter_info->syn_info;
5746 if (syn_info & IXGBE_SYN_FILTER_ENABLE)
5748 synqf = (uint32_t)(((filter->queue << IXGBE_SYN_FILTER_QUEUE_SHIFT) &
5749 IXGBE_SYN_FILTER_QUEUE) | IXGBE_SYN_FILTER_ENABLE);
5751 if (filter->hig_pri)
5752 synqf |= IXGBE_SYN_FILTER_SYNQFP;
5754 synqf &= ~IXGBE_SYN_FILTER_SYNQFP;
5756 synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5757 if (!(syn_info & IXGBE_SYN_FILTER_ENABLE))
5759 synqf &= ~(IXGBE_SYN_FILTER_QUEUE | IXGBE_SYN_FILTER_ENABLE);
5762 filter_info->syn_info = synqf;
5763 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
5764 IXGBE_WRITE_FLUSH(hw);
5769 ixgbe_syn_filter_get(struct rte_eth_dev *dev,
5770 struct rte_eth_syn_filter *filter)
5772 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5773 uint32_t synqf = IXGBE_READ_REG(hw, IXGBE_SYNQF);
5775 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
5776 filter->hig_pri = (synqf & IXGBE_SYN_FILTER_SYNQFP) ? 1 : 0;
5777 filter->queue = (uint16_t)((synqf & IXGBE_SYN_FILTER_QUEUE) >> 1);
5784 ixgbe_syn_filter_handle(struct rte_eth_dev *dev,
5785 enum rte_filter_op filter_op,
5788 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5791 MAC_TYPE_FILTER_SUP(hw->mac.type);
5793 if (filter_op == RTE_ETH_FILTER_NOP)
5797 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5802 switch (filter_op) {
5803 case RTE_ETH_FILTER_ADD:
5804 ret = ixgbe_syn_filter_set(dev,
5805 (struct rte_eth_syn_filter *)arg,
5808 case RTE_ETH_FILTER_DELETE:
5809 ret = ixgbe_syn_filter_set(dev,
5810 (struct rte_eth_syn_filter *)arg,
5813 case RTE_ETH_FILTER_GET:
5814 ret = ixgbe_syn_filter_get(dev,
5815 (struct rte_eth_syn_filter *)arg);
5818 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
5827 static inline enum ixgbe_5tuple_protocol
5828 convert_protocol_type(uint8_t protocol_value)
5830 if (protocol_value == IPPROTO_TCP)
5831 return IXGBE_FILTER_PROTOCOL_TCP;
5832 else if (protocol_value == IPPROTO_UDP)
5833 return IXGBE_FILTER_PROTOCOL_UDP;
5834 else if (protocol_value == IPPROTO_SCTP)
5835 return IXGBE_FILTER_PROTOCOL_SCTP;
5837 return IXGBE_FILTER_PROTOCOL_NONE;
5840 /* inject a 5-tuple filter to HW */
5842 ixgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
5843 struct ixgbe_5tuple_filter *filter)
5845 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5847 uint32_t ftqf, sdpqf;
5848 uint32_t l34timir = 0;
5849 uint8_t mask = 0xff;
5853 sdpqf = (uint32_t)(filter->filter_info.dst_port <<
5854 IXGBE_SDPQF_DSTPORT_SHIFT);
5855 sdpqf = sdpqf | (filter->filter_info.src_port & IXGBE_SDPQF_SRCPORT);
5857 ftqf = (uint32_t)(filter->filter_info.proto &
5858 IXGBE_FTQF_PROTOCOL_MASK);
5859 ftqf |= (uint32_t)((filter->filter_info.priority &
5860 IXGBE_FTQF_PRIORITY_MASK) << IXGBE_FTQF_PRIORITY_SHIFT);
5861 if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
5862 mask &= IXGBE_FTQF_SOURCE_ADDR_MASK;
5863 if (filter->filter_info.dst_ip_mask == 0)
5864 mask &= IXGBE_FTQF_DEST_ADDR_MASK;
5865 if (filter->filter_info.src_port_mask == 0)
5866 mask &= IXGBE_FTQF_SOURCE_PORT_MASK;
5867 if (filter->filter_info.dst_port_mask == 0)
5868 mask &= IXGBE_FTQF_DEST_PORT_MASK;
5869 if (filter->filter_info.proto_mask == 0)
5870 mask &= IXGBE_FTQF_PROTOCOL_COMP_MASK;
5871 ftqf |= mask << IXGBE_FTQF_5TUPLE_MASK_SHIFT;
5872 ftqf |= IXGBE_FTQF_POOL_MASK_EN;
5873 ftqf |= IXGBE_FTQF_QUEUE_ENABLE;
5875 IXGBE_WRITE_REG(hw, IXGBE_DAQF(i), filter->filter_info.dst_ip);
5876 IXGBE_WRITE_REG(hw, IXGBE_SAQF(i), filter->filter_info.src_ip);
5877 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(i), sdpqf);
5878 IXGBE_WRITE_REG(hw, IXGBE_FTQF(i), ftqf);
5880 l34timir |= IXGBE_L34T_IMIR_RESERVE;
5881 l34timir |= (uint32_t)(filter->queue <<
5882 IXGBE_L34T_IMIR_QUEUE_SHIFT);
5883 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(i), l34timir);
5887 * add a 5tuple filter
5890 * dev: Pointer to struct rte_eth_dev.
5891 * index: the index the filter allocates.
5892 * filter: ponter to the filter that will be added.
5893 * rx_queue: the queue id the filter assigned to.
5896 * - On success, zero.
5897 * - On failure, a negative value.
5900 ixgbe_add_5tuple_filter(struct rte_eth_dev *dev,
5901 struct ixgbe_5tuple_filter *filter)
5903 struct ixgbe_filter_info *filter_info =
5904 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5908 * look for an unused 5tuple filter index,
5909 * and insert the filter to list.
5911 for (i = 0; i < IXGBE_MAX_FTQF_FILTERS; i++) {
5912 idx = i / (sizeof(uint32_t) * NBBY);
5913 shift = i % (sizeof(uint32_t) * NBBY);
5914 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
5915 filter_info->fivetuple_mask[idx] |= 1 << shift;
5917 TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
5923 if (i >= IXGBE_MAX_FTQF_FILTERS) {
5924 PMD_DRV_LOG(ERR, "5tuple filters are full.");
5928 ixgbe_inject_5tuple_filter(dev, filter);
5934 * remove a 5tuple filter
5937 * dev: Pointer to struct rte_eth_dev.
5938 * filter: the pointer of the filter will be removed.
5941 ixgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
5942 struct ixgbe_5tuple_filter *filter)
5944 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5945 struct ixgbe_filter_info *filter_info =
5946 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
5947 uint16_t index = filter->index;
5949 filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
5950 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
5951 TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
5954 IXGBE_WRITE_REG(hw, IXGBE_DAQF(index), 0);
5955 IXGBE_WRITE_REG(hw, IXGBE_SAQF(index), 0);
5956 IXGBE_WRITE_REG(hw, IXGBE_SDPQF(index), 0);
5957 IXGBE_WRITE_REG(hw, IXGBE_FTQF(index), 0);
5958 IXGBE_WRITE_REG(hw, IXGBE_L34T_IMIR(index), 0);
5962 ixgbevf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
5964 struct ixgbe_hw *hw;
5965 uint32_t max_frame = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
5966 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
5968 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5970 if ((mtu < ETHER_MIN_MTU) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
5973 /* refuse mtu that requires the support of scattered packets when this
5974 * feature has not been enabled before.
5976 if (!rx_conf->enable_scatter &&
5977 (max_frame + 2 * IXGBE_VLAN_TAG_SIZE >
5978 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM))
5982 * When supported by the underlying PF driver, use the IXGBE_VF_SET_MTU
5983 * request of the version 2.0 of the mailbox API.
5984 * For now, use the IXGBE_VF_SET_LPE request of the version 1.0
5985 * of the mailbox API.
5986 * This call to IXGBE_SET_LPE action won't work with ixgbe pf drivers
5987 * prior to 3.11.33 which contains the following change:
5988 * "ixgbe: Enable jumbo frames support w/ SR-IOV"
5990 ixgbevf_rlpml_set_vf(hw, max_frame);
5992 /* update max frame size */
5993 dev->data->dev_conf.rxmode.max_rx_pkt_len = max_frame;
5997 static inline struct ixgbe_5tuple_filter *
5998 ixgbe_5tuple_filter_lookup(struct ixgbe_5tuple_filter_list *filter_list,
5999 struct ixgbe_5tuple_filter_info *key)
6001 struct ixgbe_5tuple_filter *it;
6003 TAILQ_FOREACH(it, filter_list, entries) {
6004 if (memcmp(key, &it->filter_info,
6005 sizeof(struct ixgbe_5tuple_filter_info)) == 0) {
6012 /* translate elements in struct rte_eth_ntuple_filter to struct ixgbe_5tuple_filter_info*/
6014 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
6015 struct ixgbe_5tuple_filter_info *filter_info)
6017 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM ||
6018 filter->priority > IXGBE_5TUPLE_MAX_PRI ||
6019 filter->priority < IXGBE_5TUPLE_MIN_PRI)
6022 switch (filter->dst_ip_mask) {
6024 filter_info->dst_ip_mask = 0;
6025 filter_info->dst_ip = filter->dst_ip;
6028 filter_info->dst_ip_mask = 1;
6031 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
6035 switch (filter->src_ip_mask) {
6037 filter_info->src_ip_mask = 0;
6038 filter_info->src_ip = filter->src_ip;
6041 filter_info->src_ip_mask = 1;
6044 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
6048 switch (filter->dst_port_mask) {
6050 filter_info->dst_port_mask = 0;
6051 filter_info->dst_port = filter->dst_port;
6054 filter_info->dst_port_mask = 1;
6057 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
6061 switch (filter->src_port_mask) {
6063 filter_info->src_port_mask = 0;
6064 filter_info->src_port = filter->src_port;
6067 filter_info->src_port_mask = 1;
6070 PMD_DRV_LOG(ERR, "invalid src_port mask.");
6074 switch (filter->proto_mask) {
6076 filter_info->proto_mask = 0;
6077 filter_info->proto =
6078 convert_protocol_type(filter->proto);
6081 filter_info->proto_mask = 1;
6084 PMD_DRV_LOG(ERR, "invalid protocol mask.");
6088 filter_info->priority = (uint8_t)filter->priority;
6093 * add or delete a ntuple filter
6096 * dev: Pointer to struct rte_eth_dev.
6097 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6098 * add: if true, add filter, if false, remove filter
6101 * - On success, zero.
6102 * - On failure, a negative value.
6105 ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
6106 struct rte_eth_ntuple_filter *ntuple_filter,
6109 struct ixgbe_filter_info *filter_info =
6110 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6111 struct ixgbe_5tuple_filter_info filter_5tuple;
6112 struct ixgbe_5tuple_filter *filter;
6115 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6116 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6120 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6121 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6125 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6127 if (filter != NULL && add) {
6128 PMD_DRV_LOG(ERR, "filter exists.");
6131 if (filter == NULL && !add) {
6132 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6137 filter = rte_zmalloc("ixgbe_5tuple_filter",
6138 sizeof(struct ixgbe_5tuple_filter), 0);
6141 (void)rte_memcpy(&filter->filter_info,
6143 sizeof(struct ixgbe_5tuple_filter_info));
6144 filter->queue = ntuple_filter->queue;
6145 ret = ixgbe_add_5tuple_filter(dev, filter);
6151 ixgbe_remove_5tuple_filter(dev, filter);
6157 * get a ntuple filter
6160 * dev: Pointer to struct rte_eth_dev.
6161 * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
6164 * - On success, zero.
6165 * - On failure, a negative value.
6168 ixgbe_get_ntuple_filter(struct rte_eth_dev *dev,
6169 struct rte_eth_ntuple_filter *ntuple_filter)
6171 struct ixgbe_filter_info *filter_info =
6172 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6173 struct ixgbe_5tuple_filter_info filter_5tuple;
6174 struct ixgbe_5tuple_filter *filter;
6177 if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
6178 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
6182 memset(&filter_5tuple, 0, sizeof(struct ixgbe_5tuple_filter_info));
6183 ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
6187 filter = ixgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
6189 if (filter == NULL) {
6190 PMD_DRV_LOG(ERR, "filter doesn't exist.");
6193 ntuple_filter->queue = filter->queue;
6198 * ixgbe_ntuple_filter_handle - Handle operations for ntuple filter.
6199 * @dev: pointer to rte_eth_dev structure
6200 * @filter_op:operation will be taken.
6201 * @arg: a pointer to specific structure corresponding to the filter_op
6204 * - On success, zero.
6205 * - On failure, a negative value.
6208 ixgbe_ntuple_filter_handle(struct rte_eth_dev *dev,
6209 enum rte_filter_op filter_op,
6212 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6215 MAC_TYPE_FILTER_SUP_EXT(hw->mac.type);
6217 if (filter_op == RTE_ETH_FILTER_NOP)
6221 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6226 switch (filter_op) {
6227 case RTE_ETH_FILTER_ADD:
6228 ret = ixgbe_add_del_ntuple_filter(dev,
6229 (struct rte_eth_ntuple_filter *)arg,
6232 case RTE_ETH_FILTER_DELETE:
6233 ret = ixgbe_add_del_ntuple_filter(dev,
6234 (struct rte_eth_ntuple_filter *)arg,
6237 case RTE_ETH_FILTER_GET:
6238 ret = ixgbe_get_ntuple_filter(dev,
6239 (struct rte_eth_ntuple_filter *)arg);
6242 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6250 ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
6251 struct rte_eth_ethertype_filter *filter,
6254 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6255 struct ixgbe_filter_info *filter_info =
6256 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6260 struct ixgbe_ethertype_filter ethertype_filter;
6262 if (filter->queue >= IXGBE_MAX_RX_QUEUE_NUM)
6265 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6266 filter->ether_type == ETHER_TYPE_IPv6) {
6267 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6268 " ethertype filter.", filter->ether_type);
6272 if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
6273 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
6276 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
6277 PMD_DRV_LOG(ERR, "drop option is unsupported.");
6281 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6282 if (ret >= 0 && add) {
6283 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
6284 filter->ether_type);
6287 if (ret < 0 && !add) {
6288 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6289 filter->ether_type);
6294 etqf = IXGBE_ETQF_FILTER_EN;
6295 etqf |= (uint32_t)filter->ether_type;
6296 etqs |= (uint32_t)((filter->queue <<
6297 IXGBE_ETQS_RX_QUEUE_SHIFT) &
6298 IXGBE_ETQS_RX_QUEUE);
6299 etqs |= IXGBE_ETQS_QUEUE_EN;
6301 ethertype_filter.ethertype = filter->ether_type;
6302 ethertype_filter.etqf = etqf;
6303 ethertype_filter.etqs = etqs;
6304 ethertype_filter.conf = FALSE;
6305 ret = ixgbe_ethertype_filter_insert(filter_info,
6308 PMD_DRV_LOG(ERR, "ethertype filters are full.");
6312 ret = ixgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
6316 IXGBE_WRITE_REG(hw, IXGBE_ETQF(ret), etqf);
6317 IXGBE_WRITE_REG(hw, IXGBE_ETQS(ret), etqs);
6318 IXGBE_WRITE_FLUSH(hw);
6324 ixgbe_get_ethertype_filter(struct rte_eth_dev *dev,
6325 struct rte_eth_ethertype_filter *filter)
6327 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6328 struct ixgbe_filter_info *filter_info =
6329 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
6330 uint32_t etqf, etqs;
6333 ret = ixgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
6335 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
6336 filter->ether_type);
6340 etqf = IXGBE_READ_REG(hw, IXGBE_ETQF(ret));
6341 if (etqf & IXGBE_ETQF_FILTER_EN) {
6342 etqs = IXGBE_READ_REG(hw, IXGBE_ETQS(ret));
6343 filter->ether_type = etqf & IXGBE_ETQF_ETHERTYPE;
6345 filter->queue = (etqs & IXGBE_ETQS_RX_QUEUE) >>
6346 IXGBE_ETQS_RX_QUEUE_SHIFT;
6353 * ixgbe_ethertype_filter_handle - Handle operations for ethertype filter.
6354 * @dev: pointer to rte_eth_dev structure
6355 * @filter_op:operation will be taken.
6356 * @arg: a pointer to specific structure corresponding to the filter_op
6359 ixgbe_ethertype_filter_handle(struct rte_eth_dev *dev,
6360 enum rte_filter_op filter_op,
6363 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6366 MAC_TYPE_FILTER_SUP(hw->mac.type);
6368 if (filter_op == RTE_ETH_FILTER_NOP)
6372 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
6377 switch (filter_op) {
6378 case RTE_ETH_FILTER_ADD:
6379 ret = ixgbe_add_del_ethertype_filter(dev,
6380 (struct rte_eth_ethertype_filter *)arg,
6383 case RTE_ETH_FILTER_DELETE:
6384 ret = ixgbe_add_del_ethertype_filter(dev,
6385 (struct rte_eth_ethertype_filter *)arg,
6388 case RTE_ETH_FILTER_GET:
6389 ret = ixgbe_get_ethertype_filter(dev,
6390 (struct rte_eth_ethertype_filter *)arg);
6393 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
6401 ixgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
6402 enum rte_filter_type filter_type,
6403 enum rte_filter_op filter_op,
6408 switch (filter_type) {
6409 case RTE_ETH_FILTER_NTUPLE:
6410 ret = ixgbe_ntuple_filter_handle(dev, filter_op, arg);
6412 case RTE_ETH_FILTER_ETHERTYPE:
6413 ret = ixgbe_ethertype_filter_handle(dev, filter_op, arg);
6415 case RTE_ETH_FILTER_SYN:
6416 ret = ixgbe_syn_filter_handle(dev, filter_op, arg);
6418 case RTE_ETH_FILTER_FDIR:
6419 ret = ixgbe_fdir_ctrl_func(dev, filter_op, arg);
6421 case RTE_ETH_FILTER_L2_TUNNEL:
6422 ret = ixgbe_dev_l2_tunnel_filter_handle(dev, filter_op, arg);
6424 case RTE_ETH_FILTER_GENERIC:
6425 if (filter_op != RTE_ETH_FILTER_GET)
6427 *(const void **)arg = &ixgbe_flow_ops;
6430 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
6440 ixgbe_dev_addr_list_itr(__attribute__((unused)) struct ixgbe_hw *hw,
6441 u8 **mc_addr_ptr, u32 *vmdq)
6446 mc_addr = *mc_addr_ptr;
6447 *mc_addr_ptr = (mc_addr + sizeof(struct ether_addr));
6452 ixgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
6453 struct ether_addr *mc_addr_set,
6454 uint32_t nb_mc_addr)
6456 struct ixgbe_hw *hw;
6459 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6460 mc_addr_list = (u8 *)mc_addr_set;
6461 return ixgbe_update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
6462 ixgbe_dev_addr_list_itr, TRUE);
6466 ixgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
6468 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6469 uint64_t systime_cycles;
6471 switch (hw->mac.type) {
6472 case ixgbe_mac_X550:
6473 case ixgbe_mac_X550EM_x:
6474 case ixgbe_mac_X550EM_a:
6475 /* SYSTIMEL stores ns and SYSTIMEH stores seconds. */
6476 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6477 systime_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6481 systime_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
6482 systime_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_SYSTIMH)
6486 return systime_cycles;
6490 ixgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6492 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6493 uint64_t rx_tstamp_cycles;
6495 switch (hw->mac.type) {
6496 case ixgbe_mac_X550:
6497 case ixgbe_mac_X550EM_x:
6498 case ixgbe_mac_X550EM_a:
6499 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6500 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6501 rx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6505 /* RXSTMPL stores ns and RXSTMPH stores seconds. */
6506 rx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
6507 rx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_RXSTMPH)
6511 return rx_tstamp_cycles;
6515 ixgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
6517 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6518 uint64_t tx_tstamp_cycles;
6520 switch (hw->mac.type) {
6521 case ixgbe_mac_X550:
6522 case ixgbe_mac_X550EM_x:
6523 case ixgbe_mac_X550EM_a:
6524 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6525 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6526 tx_tstamp_cycles += (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6530 /* TXSTMPL stores ns and TXSTMPH stores seconds. */
6531 tx_tstamp_cycles = (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
6532 tx_tstamp_cycles |= (uint64_t)IXGBE_READ_REG(hw, IXGBE_TXSTMPH)
6536 return tx_tstamp_cycles;
6540 ixgbe_start_timecounters(struct rte_eth_dev *dev)
6542 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6543 struct ixgbe_adapter *adapter =
6544 (struct ixgbe_adapter *)dev->data->dev_private;
6545 struct rte_eth_link link;
6546 uint32_t incval = 0;
6549 /* Get current link speed. */
6550 memset(&link, 0, sizeof(link));
6551 ixgbe_dev_link_update(dev, 1);
6552 rte_ixgbe_dev_atomic_read_link_status(dev, &link);
6554 switch (link.link_speed) {
6555 case ETH_SPEED_NUM_100M:
6556 incval = IXGBE_INCVAL_100;
6557 shift = IXGBE_INCVAL_SHIFT_100;
6559 case ETH_SPEED_NUM_1G:
6560 incval = IXGBE_INCVAL_1GB;
6561 shift = IXGBE_INCVAL_SHIFT_1GB;
6563 case ETH_SPEED_NUM_10G:
6565 incval = IXGBE_INCVAL_10GB;
6566 shift = IXGBE_INCVAL_SHIFT_10GB;
6570 switch (hw->mac.type) {
6571 case ixgbe_mac_X550:
6572 case ixgbe_mac_X550EM_x:
6573 case ixgbe_mac_X550EM_a:
6574 /* Independent of link speed. */
6576 /* Cycles read will be interpreted as ns. */
6579 case ixgbe_mac_X540:
6580 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
6582 case ixgbe_mac_82599EB:
6583 incval >>= IXGBE_INCVAL_SHIFT_82599;
6584 shift -= IXGBE_INCVAL_SHIFT_82599;
6585 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
6586 (1 << IXGBE_INCPER_SHIFT_82599) | incval);
6589 /* Not supported. */
6593 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
6594 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6595 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
6597 adapter->systime_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6598 adapter->systime_tc.cc_shift = shift;
6599 adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
6601 adapter->rx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6602 adapter->rx_tstamp_tc.cc_shift = shift;
6603 adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6605 adapter->tx_tstamp_tc.cc_mask = IXGBE_CYCLECOUNTER_MASK;
6606 adapter->tx_tstamp_tc.cc_shift = shift;
6607 adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
6611 ixgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
6613 struct ixgbe_adapter *adapter =
6614 (struct ixgbe_adapter *)dev->data->dev_private;
6616 adapter->systime_tc.nsec += delta;
6617 adapter->rx_tstamp_tc.nsec += delta;
6618 adapter->tx_tstamp_tc.nsec += delta;
6624 ixgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
6627 struct ixgbe_adapter *adapter =
6628 (struct ixgbe_adapter *)dev->data->dev_private;
6630 ns = rte_timespec_to_ns(ts);
6631 /* Set the timecounters to a new value. */
6632 adapter->systime_tc.nsec = ns;
6633 adapter->rx_tstamp_tc.nsec = ns;
6634 adapter->tx_tstamp_tc.nsec = ns;
6640 ixgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
6642 uint64_t ns, systime_cycles;
6643 struct ixgbe_adapter *adapter =
6644 (struct ixgbe_adapter *)dev->data->dev_private;
6646 systime_cycles = ixgbe_read_systime_cyclecounter(dev);
6647 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
6648 *ts = rte_ns_to_timespec(ns);
6654 ixgbe_timesync_enable(struct rte_eth_dev *dev)
6656 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6660 /* Stop the timesync system time. */
6661 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0x0);
6662 /* Reset the timesync system time value. */
6663 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x0);
6664 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x0);
6666 /* Enable system time for platforms where it isn't on by default. */
6667 tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
6668 tsauxc &= ~IXGBE_TSAUXC_DISABLE_SYSTIME;
6669 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
6671 ixgbe_start_timecounters(dev);
6673 /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6674 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
6676 IXGBE_ETQF_FILTER_EN |
6679 /* Enable timestamping of received PTP packets. */
6680 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6681 tsync_ctl |= IXGBE_TSYNCRXCTL_ENABLED;
6682 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6684 /* Enable timestamping of transmitted PTP packets. */
6685 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6686 tsync_ctl |= IXGBE_TSYNCTXCTL_ENABLED;
6687 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6689 IXGBE_WRITE_FLUSH(hw);
6695 ixgbe_timesync_disable(struct rte_eth_dev *dev)
6697 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6700 /* Disable timestamping of transmitted PTP packets. */
6701 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6702 tsync_ctl &= ~IXGBE_TSYNCTXCTL_ENABLED;
6703 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, tsync_ctl);
6705 /* Disable timestamping of received PTP packets. */
6706 tsync_ctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6707 tsync_ctl &= ~IXGBE_TSYNCRXCTL_ENABLED;
6708 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, tsync_ctl);
6710 /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
6711 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
6713 /* Stop incrementating the System Time registers. */
6714 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, 0);
6720 ixgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6721 struct timespec *timestamp,
6722 uint32_t flags __rte_unused)
6724 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6725 struct ixgbe_adapter *adapter =
6726 (struct ixgbe_adapter *)dev->data->dev_private;
6727 uint32_t tsync_rxctl;
6728 uint64_t rx_tstamp_cycles;
6731 tsync_rxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
6732 if ((tsync_rxctl & IXGBE_TSYNCRXCTL_VALID) == 0)
6735 rx_tstamp_cycles = ixgbe_read_rx_tstamp_cyclecounter(dev);
6736 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
6737 *timestamp = rte_ns_to_timespec(ns);
6743 ixgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6744 struct timespec *timestamp)
6746 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6747 struct ixgbe_adapter *adapter =
6748 (struct ixgbe_adapter *)dev->data->dev_private;
6749 uint32_t tsync_txctl;
6750 uint64_t tx_tstamp_cycles;
6753 tsync_txctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
6754 if ((tsync_txctl & IXGBE_TSYNCTXCTL_VALID) == 0)
6757 tx_tstamp_cycles = ixgbe_read_tx_tstamp_cyclecounter(dev);
6758 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
6759 *timestamp = rte_ns_to_timespec(ns);
6765 ixgbe_get_reg_length(struct rte_eth_dev *dev)
6767 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6770 const struct reg_info *reg_group;
6771 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6772 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6774 while ((reg_group = reg_set[g_ind++]))
6775 count += ixgbe_regs_group_count(reg_group);
6781 ixgbevf_get_reg_length(struct rte_eth_dev *dev __rte_unused)
6785 const struct reg_info *reg_group;
6787 while ((reg_group = ixgbevf_regs[g_ind++]))
6788 count += ixgbe_regs_group_count(reg_group);
6794 ixgbe_get_regs(struct rte_eth_dev *dev,
6795 struct rte_dev_reg_info *regs)
6797 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6798 uint32_t *data = regs->data;
6801 const struct reg_info *reg_group;
6802 const struct reg_info **reg_set = (hw->mac.type == ixgbe_mac_82598EB) ?
6803 ixgbe_regs_mac_82598EB : ixgbe_regs_others;
6806 regs->length = ixgbe_get_reg_length(dev);
6807 regs->width = sizeof(uint32_t);
6811 /* Support only full register dump */
6812 if ((regs->length == 0) ||
6813 (regs->length == (uint32_t)ixgbe_get_reg_length(dev))) {
6814 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6816 while ((reg_group = reg_set[g_ind++]))
6817 count += ixgbe_read_regs_group(dev, &data[count],
6826 ixgbevf_get_regs(struct rte_eth_dev *dev,
6827 struct rte_dev_reg_info *regs)
6829 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6830 uint32_t *data = regs->data;
6833 const struct reg_info *reg_group;
6836 regs->length = ixgbevf_get_reg_length(dev);
6837 regs->width = sizeof(uint32_t);
6841 /* Support only full register dump */
6842 if ((regs->length == 0) ||
6843 (regs->length == (uint32_t)ixgbevf_get_reg_length(dev))) {
6844 regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
6846 while ((reg_group = ixgbevf_regs[g_ind++]))
6847 count += ixgbe_read_regs_group(dev, &data[count],
6856 ixgbe_get_eeprom_length(struct rte_eth_dev *dev)
6858 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6860 /* Return unit is byte count */
6861 return hw->eeprom.word_size * 2;
6865 ixgbe_get_eeprom(struct rte_eth_dev *dev,
6866 struct rte_dev_eeprom_info *in_eeprom)
6868 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6869 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6870 uint16_t *data = in_eeprom->data;
6873 first = in_eeprom->offset >> 1;
6874 length = in_eeprom->length >> 1;
6875 if ((first > hw->eeprom.word_size) ||
6876 ((first + length) > hw->eeprom.word_size))
6879 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6881 return eeprom->ops.read_buffer(hw, first, length, data);
6885 ixgbe_set_eeprom(struct rte_eth_dev *dev,
6886 struct rte_dev_eeprom_info *in_eeprom)
6888 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6889 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
6890 uint16_t *data = in_eeprom->data;
6893 first = in_eeprom->offset >> 1;
6894 length = in_eeprom->length >> 1;
6895 if ((first > hw->eeprom.word_size) ||
6896 ((first + length) > hw->eeprom.word_size))
6899 in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
6901 return eeprom->ops.write_buffer(hw, first, length, data);
6905 ixgbe_reta_size_get(enum ixgbe_mac_type mac_type) {
6907 case ixgbe_mac_X550:
6908 case ixgbe_mac_X550EM_x:
6909 case ixgbe_mac_X550EM_a:
6910 return ETH_RSS_RETA_SIZE_512;
6911 case ixgbe_mac_X550_vf:
6912 case ixgbe_mac_X550EM_x_vf:
6913 case ixgbe_mac_X550EM_a_vf:
6914 return ETH_RSS_RETA_SIZE_64;
6916 return ETH_RSS_RETA_SIZE_128;
6921 ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx) {
6923 case ixgbe_mac_X550:
6924 case ixgbe_mac_X550EM_x:
6925 case ixgbe_mac_X550EM_a:
6926 if (reta_idx < ETH_RSS_RETA_SIZE_128)
6927 return IXGBE_RETA(reta_idx >> 2);
6929 return IXGBE_ERETA((reta_idx - ETH_RSS_RETA_SIZE_128) >> 2);
6930 case ixgbe_mac_X550_vf:
6931 case ixgbe_mac_X550EM_x_vf:
6932 case ixgbe_mac_X550EM_a_vf:
6933 return IXGBE_VFRETA(reta_idx >> 2);
6935 return IXGBE_RETA(reta_idx >> 2);
6940 ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type) {
6942 case ixgbe_mac_X550_vf:
6943 case ixgbe_mac_X550EM_x_vf:
6944 case ixgbe_mac_X550EM_a_vf:
6945 return IXGBE_VFMRQC;
6952 ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i) {
6954 case ixgbe_mac_X550_vf:
6955 case ixgbe_mac_X550EM_x_vf:
6956 case ixgbe_mac_X550EM_a_vf:
6957 return IXGBE_VFRSSRK(i);
6959 return IXGBE_RSSRK(i);
6964 ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type) {
6966 case ixgbe_mac_82599_vf:
6967 case ixgbe_mac_X540_vf:
6975 ixgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
6976 struct rte_eth_dcb_info *dcb_info)
6978 struct ixgbe_dcb_config *dcb_config =
6979 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
6980 struct ixgbe_dcb_tc_config *tc;
6983 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
6984 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
6986 dcb_info->nb_tcs = 1;
6988 if (dcb_config->vt_mode) { /* vt is enabled*/
6989 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
6990 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
6991 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
6992 dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
6993 for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
6994 for (j = 0; j < dcb_info->nb_tcs; j++) {
6995 dcb_info->tc_queue.tc_rxq[i][j].base =
6996 i * dcb_info->nb_tcs + j;
6997 dcb_info->tc_queue.tc_rxq[i][j].nb_queue = 1;
6998 dcb_info->tc_queue.tc_txq[i][j].base =
6999 i * dcb_info->nb_tcs + j;
7000 dcb_info->tc_queue.tc_txq[i][j].nb_queue = 1;
7003 } else { /* vt is disabled*/
7004 struct rte_eth_dcb_rx_conf *rx_conf =
7005 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7006 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
7007 dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
7008 if (dcb_info->nb_tcs == ETH_4_TCS) {
7009 for (i = 0; i < dcb_info->nb_tcs; i++) {
7010 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
7011 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7013 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7014 dcb_info->tc_queue.tc_txq[0][1].base = 64;
7015 dcb_info->tc_queue.tc_txq[0][2].base = 96;
7016 dcb_info->tc_queue.tc_txq[0][3].base = 112;
7017 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
7018 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7019 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7020 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7021 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
7022 for (i = 0; i < dcb_info->nb_tcs; i++) {
7023 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
7024 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
7026 dcb_info->tc_queue.tc_txq[0][0].base = 0;
7027 dcb_info->tc_queue.tc_txq[0][1].base = 32;
7028 dcb_info->tc_queue.tc_txq[0][2].base = 64;
7029 dcb_info->tc_queue.tc_txq[0][3].base = 80;
7030 dcb_info->tc_queue.tc_txq[0][4].base = 96;
7031 dcb_info->tc_queue.tc_txq[0][5].base = 104;
7032 dcb_info->tc_queue.tc_txq[0][6].base = 112;
7033 dcb_info->tc_queue.tc_txq[0][7].base = 120;
7034 dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
7035 dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
7036 dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
7037 dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
7038 dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
7039 dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
7040 dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
7041 dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
7044 for (i = 0; i < dcb_info->nb_tcs; i++) {
7045 tc = &dcb_config->tc_config[i];
7046 dcb_info->tc_bws[i] = tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent;
7051 /* Update e-tag ether type */
7053 ixgbe_update_e_tag_eth_type(struct ixgbe_hw *hw,
7054 uint16_t ether_type)
7056 uint32_t etag_etype;
7058 if (hw->mac.type != ixgbe_mac_X550 &&
7059 hw->mac.type != ixgbe_mac_X550EM_x &&
7060 hw->mac.type != ixgbe_mac_X550EM_a) {
7064 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7065 etag_etype &= ~IXGBE_ETAG_ETYPE_MASK;
7066 etag_etype |= ether_type;
7067 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7068 IXGBE_WRITE_FLUSH(hw);
7073 /* Config l2 tunnel ether type */
7075 ixgbe_dev_l2_tunnel_eth_type_conf(struct rte_eth_dev *dev,
7076 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7079 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7080 struct ixgbe_l2_tn_info *l2_tn_info =
7081 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7083 if (l2_tunnel == NULL)
7086 switch (l2_tunnel->l2_tunnel_type) {
7087 case RTE_L2_TUNNEL_TYPE_E_TAG:
7088 l2_tn_info->e_tag_ether_type = l2_tunnel->ether_type;
7089 ret = ixgbe_update_e_tag_eth_type(hw, l2_tunnel->ether_type);
7092 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7100 /* Enable e-tag tunnel */
7102 ixgbe_e_tag_enable(struct ixgbe_hw *hw)
7104 uint32_t etag_etype;
7106 if (hw->mac.type != ixgbe_mac_X550 &&
7107 hw->mac.type != ixgbe_mac_X550EM_x &&
7108 hw->mac.type != ixgbe_mac_X550EM_a) {
7112 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7113 etag_etype |= IXGBE_ETAG_ETYPE_VALID;
7114 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7115 IXGBE_WRITE_FLUSH(hw);
7120 /* Enable l2 tunnel */
7122 ixgbe_dev_l2_tunnel_enable(struct rte_eth_dev *dev,
7123 enum rte_eth_tunnel_type l2_tunnel_type)
7126 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7127 struct ixgbe_l2_tn_info *l2_tn_info =
7128 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7130 switch (l2_tunnel_type) {
7131 case RTE_L2_TUNNEL_TYPE_E_TAG:
7132 l2_tn_info->e_tag_en = TRUE;
7133 ret = ixgbe_e_tag_enable(hw);
7136 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7144 /* Disable e-tag tunnel */
7146 ixgbe_e_tag_disable(struct ixgbe_hw *hw)
7148 uint32_t etag_etype;
7150 if (hw->mac.type != ixgbe_mac_X550 &&
7151 hw->mac.type != ixgbe_mac_X550EM_x &&
7152 hw->mac.type != ixgbe_mac_X550EM_a) {
7156 etag_etype = IXGBE_READ_REG(hw, IXGBE_ETAG_ETYPE);
7157 etag_etype &= ~IXGBE_ETAG_ETYPE_VALID;
7158 IXGBE_WRITE_REG(hw, IXGBE_ETAG_ETYPE, etag_etype);
7159 IXGBE_WRITE_FLUSH(hw);
7164 /* Disable l2 tunnel */
7166 ixgbe_dev_l2_tunnel_disable(struct rte_eth_dev *dev,
7167 enum rte_eth_tunnel_type l2_tunnel_type)
7170 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7171 struct ixgbe_l2_tn_info *l2_tn_info =
7172 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7174 switch (l2_tunnel_type) {
7175 case RTE_L2_TUNNEL_TYPE_E_TAG:
7176 l2_tn_info->e_tag_en = FALSE;
7177 ret = ixgbe_e_tag_disable(hw);
7180 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7189 ixgbe_e_tag_filter_del(struct rte_eth_dev *dev,
7190 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7193 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7194 uint32_t i, rar_entries;
7195 uint32_t rar_low, rar_high;
7197 if (hw->mac.type != ixgbe_mac_X550 &&
7198 hw->mac.type != ixgbe_mac_X550EM_x &&
7199 hw->mac.type != ixgbe_mac_X550EM_a) {
7203 rar_entries = ixgbe_get_num_rx_addrs(hw);
7205 for (i = 1; i < rar_entries; i++) {
7206 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7207 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(i));
7208 if ((rar_high & IXGBE_RAH_AV) &&
7209 (rar_high & IXGBE_RAH_ADTYPE) &&
7210 ((rar_low & IXGBE_RAL_ETAG_FILTER_MASK) ==
7211 l2_tunnel->tunnel_id)) {
7212 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
7213 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
7215 ixgbe_clear_vmdq(hw, i, IXGBE_CLEAR_VMDQ_ALL);
7225 ixgbe_e_tag_filter_add(struct rte_eth_dev *dev,
7226 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7229 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7230 uint32_t i, rar_entries;
7231 uint32_t rar_low, rar_high;
7233 if (hw->mac.type != ixgbe_mac_X550 &&
7234 hw->mac.type != ixgbe_mac_X550EM_x &&
7235 hw->mac.type != ixgbe_mac_X550EM_a) {
7239 /* One entry for one tunnel. Try to remove potential existing entry. */
7240 ixgbe_e_tag_filter_del(dev, l2_tunnel);
7242 rar_entries = ixgbe_get_num_rx_addrs(hw);
7244 for (i = 1; i < rar_entries; i++) {
7245 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(i));
7246 if (rar_high & IXGBE_RAH_AV) {
7249 ixgbe_set_vmdq(hw, i, l2_tunnel->pool);
7250 rar_high = IXGBE_RAH_AV | IXGBE_RAH_ADTYPE;
7251 rar_low = l2_tunnel->tunnel_id;
7253 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), rar_low);
7254 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), rar_high);
7260 PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
7261 " Please remove a rule before adding a new one.");
7265 static inline struct ixgbe_l2_tn_filter *
7266 ixgbe_l2_tn_filter_lookup(struct ixgbe_l2_tn_info *l2_tn_info,
7267 struct ixgbe_l2_tn_key *key)
7271 ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
7275 return l2_tn_info->hash_map[ret];
7279 ixgbe_insert_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7280 struct ixgbe_l2_tn_filter *l2_tn_filter)
7284 ret = rte_hash_add_key(l2_tn_info->hash_handle,
7285 &l2_tn_filter->key);
7289 "Failed to insert L2 tunnel filter"
7290 " to hash table %d!",
7295 l2_tn_info->hash_map[ret] = l2_tn_filter;
7297 TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7303 ixgbe_remove_l2_tn_filter(struct ixgbe_l2_tn_info *l2_tn_info,
7304 struct ixgbe_l2_tn_key *key)
7307 struct ixgbe_l2_tn_filter *l2_tn_filter;
7309 ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
7313 "No such L2 tunnel filter to delete %d!",
7318 l2_tn_filter = l2_tn_info->hash_map[ret];
7319 l2_tn_info->hash_map[ret] = NULL;
7321 TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
7322 rte_free(l2_tn_filter);
7327 /* Add l2 tunnel filter */
7329 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
7330 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7334 struct ixgbe_l2_tn_info *l2_tn_info =
7335 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7336 struct ixgbe_l2_tn_key key;
7337 struct ixgbe_l2_tn_filter *node;
7340 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7341 key.tn_id = l2_tunnel->tunnel_id;
7343 node = ixgbe_l2_tn_filter_lookup(l2_tn_info, &key);
7347 "The L2 tunnel filter already exists!");
7351 node = rte_zmalloc("ixgbe_l2_tn",
7352 sizeof(struct ixgbe_l2_tn_filter),
7357 (void)rte_memcpy(&node->key,
7359 sizeof(struct ixgbe_l2_tn_key));
7360 node->pool = l2_tunnel->pool;
7361 ret = ixgbe_insert_l2_tn_filter(l2_tn_info, node);
7368 switch (l2_tunnel->l2_tunnel_type) {
7369 case RTE_L2_TUNNEL_TYPE_E_TAG:
7370 ret = ixgbe_e_tag_filter_add(dev, l2_tunnel);
7373 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7378 if ((!restore) && (ret < 0))
7379 (void)ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7384 /* Delete l2 tunnel filter */
7386 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
7387 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7390 struct ixgbe_l2_tn_info *l2_tn_info =
7391 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7392 struct ixgbe_l2_tn_key key;
7394 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
7395 key.tn_id = l2_tunnel->tunnel_id;
7396 ret = ixgbe_remove_l2_tn_filter(l2_tn_info, &key);
7400 switch (l2_tunnel->l2_tunnel_type) {
7401 case RTE_L2_TUNNEL_TYPE_E_TAG:
7402 ret = ixgbe_e_tag_filter_del(dev, l2_tunnel);
7405 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7414 * ixgbe_dev_l2_tunnel_filter_handle - Handle operations for l2 tunnel filter.
7415 * @dev: pointer to rte_eth_dev structure
7416 * @filter_op:operation will be taken.
7417 * @arg: a pointer to specific structure corresponding to the filter_op
7420 ixgbe_dev_l2_tunnel_filter_handle(struct rte_eth_dev *dev,
7421 enum rte_filter_op filter_op,
7426 if (filter_op == RTE_ETH_FILTER_NOP)
7430 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.",
7435 switch (filter_op) {
7436 case RTE_ETH_FILTER_ADD:
7437 ret = ixgbe_dev_l2_tunnel_filter_add
7439 (struct rte_eth_l2_tunnel_conf *)arg,
7442 case RTE_ETH_FILTER_DELETE:
7443 ret = ixgbe_dev_l2_tunnel_filter_del
7445 (struct rte_eth_l2_tunnel_conf *)arg);
7448 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op);
7456 ixgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
7460 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7462 if (hw->mac.type != ixgbe_mac_X550 &&
7463 hw->mac.type != ixgbe_mac_X550EM_x &&
7464 hw->mac.type != ixgbe_mac_X550EM_a) {
7468 ctrl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
7469 ctrl &= ~IXGBE_VT_CTL_POOLING_MODE_MASK;
7471 ctrl |= IXGBE_VT_CTL_POOLING_MODE_ETAG;
7472 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, ctrl);
7477 /* Enable l2 tunnel forwarding */
7479 ixgbe_dev_l2_tunnel_forwarding_enable
7480 (struct rte_eth_dev *dev,
7481 enum rte_eth_tunnel_type l2_tunnel_type)
7483 struct ixgbe_l2_tn_info *l2_tn_info =
7484 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7487 switch (l2_tunnel_type) {
7488 case RTE_L2_TUNNEL_TYPE_E_TAG:
7489 l2_tn_info->e_tag_fwd_en = TRUE;
7490 ret = ixgbe_e_tag_forwarding_en_dis(dev, 1);
7493 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7501 /* Disable l2 tunnel forwarding */
7503 ixgbe_dev_l2_tunnel_forwarding_disable
7504 (struct rte_eth_dev *dev,
7505 enum rte_eth_tunnel_type l2_tunnel_type)
7507 struct ixgbe_l2_tn_info *l2_tn_info =
7508 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
7511 switch (l2_tunnel_type) {
7512 case RTE_L2_TUNNEL_TYPE_E_TAG:
7513 l2_tn_info->e_tag_fwd_en = FALSE;
7514 ret = ixgbe_e_tag_forwarding_en_dis(dev, 0);
7517 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7526 ixgbe_e_tag_insertion_en_dis(struct rte_eth_dev *dev,
7527 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7530 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
7532 uint32_t vmtir, vmvir;
7533 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7535 if (l2_tunnel->vf_id >= pci_dev->max_vfs) {
7537 "VF id %u should be less than %u",
7543 if (hw->mac.type != ixgbe_mac_X550 &&
7544 hw->mac.type != ixgbe_mac_X550EM_x &&
7545 hw->mac.type != ixgbe_mac_X550EM_a) {
7550 vmtir = l2_tunnel->tunnel_id;
7554 IXGBE_WRITE_REG(hw, IXGBE_VMTIR(l2_tunnel->vf_id), vmtir);
7556 vmvir = IXGBE_READ_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id));
7557 vmvir &= ~IXGBE_VMVIR_TAGA_MASK;
7559 vmvir |= IXGBE_VMVIR_TAGA_ETAG_INSERT;
7560 IXGBE_WRITE_REG(hw, IXGBE_VMVIR(l2_tunnel->vf_id), vmvir);
7565 /* Enable l2 tunnel tag insertion */
7567 ixgbe_dev_l2_tunnel_insertion_enable(struct rte_eth_dev *dev,
7568 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7572 switch (l2_tunnel->l2_tunnel_type) {
7573 case RTE_L2_TUNNEL_TYPE_E_TAG:
7574 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 1);
7577 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7585 /* Disable l2 tunnel tag insertion */
7587 ixgbe_dev_l2_tunnel_insertion_disable
7588 (struct rte_eth_dev *dev,
7589 struct rte_eth_l2_tunnel_conf *l2_tunnel)
7593 switch (l2_tunnel->l2_tunnel_type) {
7594 case RTE_L2_TUNNEL_TYPE_E_TAG:
7595 ret = ixgbe_e_tag_insertion_en_dis(dev, l2_tunnel, 0);
7598 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7607 ixgbe_e_tag_stripping_en_dis(struct rte_eth_dev *dev,
7612 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7614 if (hw->mac.type != ixgbe_mac_X550 &&
7615 hw->mac.type != ixgbe_mac_X550EM_x &&
7616 hw->mac.type != ixgbe_mac_X550EM_a) {
7620 qde = IXGBE_READ_REG(hw, IXGBE_QDE);
7622 qde |= IXGBE_QDE_STRIP_TAG;
7624 qde &= ~IXGBE_QDE_STRIP_TAG;
7625 qde &= ~IXGBE_QDE_READ;
7626 qde |= IXGBE_QDE_WRITE;
7627 IXGBE_WRITE_REG(hw, IXGBE_QDE, qde);
7632 /* Enable l2 tunnel tag stripping */
7634 ixgbe_dev_l2_tunnel_stripping_enable
7635 (struct rte_eth_dev *dev,
7636 enum rte_eth_tunnel_type l2_tunnel_type)
7640 switch (l2_tunnel_type) {
7641 case RTE_L2_TUNNEL_TYPE_E_TAG:
7642 ret = ixgbe_e_tag_stripping_en_dis(dev, 1);
7645 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7653 /* Disable l2 tunnel tag stripping */
7655 ixgbe_dev_l2_tunnel_stripping_disable
7656 (struct rte_eth_dev *dev,
7657 enum rte_eth_tunnel_type l2_tunnel_type)
7661 switch (l2_tunnel_type) {
7662 case RTE_L2_TUNNEL_TYPE_E_TAG:
7663 ret = ixgbe_e_tag_stripping_en_dis(dev, 0);
7666 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7674 /* Enable/disable l2 tunnel offload functions */
7676 ixgbe_dev_l2_tunnel_offload_set
7677 (struct rte_eth_dev *dev,
7678 struct rte_eth_l2_tunnel_conf *l2_tunnel,
7684 if (l2_tunnel == NULL)
7688 if (mask & ETH_L2_TUNNEL_ENABLE_MASK) {
7690 ret = ixgbe_dev_l2_tunnel_enable(
7692 l2_tunnel->l2_tunnel_type);
7694 ret = ixgbe_dev_l2_tunnel_disable(
7696 l2_tunnel->l2_tunnel_type);
7699 if (mask & ETH_L2_TUNNEL_INSERTION_MASK) {
7701 ret = ixgbe_dev_l2_tunnel_insertion_enable(
7705 ret = ixgbe_dev_l2_tunnel_insertion_disable(
7710 if (mask & ETH_L2_TUNNEL_STRIPPING_MASK) {
7712 ret = ixgbe_dev_l2_tunnel_stripping_enable(
7714 l2_tunnel->l2_tunnel_type);
7716 ret = ixgbe_dev_l2_tunnel_stripping_disable(
7718 l2_tunnel->l2_tunnel_type);
7721 if (mask & ETH_L2_TUNNEL_FORWARDING_MASK) {
7723 ret = ixgbe_dev_l2_tunnel_forwarding_enable(
7725 l2_tunnel->l2_tunnel_type);
7727 ret = ixgbe_dev_l2_tunnel_forwarding_disable(
7729 l2_tunnel->l2_tunnel_type);
7736 ixgbe_update_vxlan_port(struct ixgbe_hw *hw,
7739 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, port);
7740 IXGBE_WRITE_FLUSH(hw);
7745 /* There's only one register for VxLAN UDP port.
7746 * So, we cannot add several ports. Will update it.
7749 ixgbe_add_vxlan_port(struct ixgbe_hw *hw,
7753 PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
7757 return ixgbe_update_vxlan_port(hw, port);
7760 /* We cannot delete the VxLAN port. For there's a register for VxLAN
7761 * UDP port, it must have a value.
7762 * So, will reset it to the original value 0.
7765 ixgbe_del_vxlan_port(struct ixgbe_hw *hw,
7770 cur_port = (uint16_t)IXGBE_READ_REG(hw, IXGBE_VXLANCTRL);
7772 if (cur_port != port) {
7773 PMD_DRV_LOG(ERR, "Port %u does not exist.", port);
7777 return ixgbe_update_vxlan_port(hw, 0);
7780 /* Add UDP tunneling port */
7782 ixgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7783 struct rte_eth_udp_tunnel *udp_tunnel)
7786 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7788 if (hw->mac.type != ixgbe_mac_X550 &&
7789 hw->mac.type != ixgbe_mac_X550EM_x &&
7790 hw->mac.type != ixgbe_mac_X550EM_a) {
7794 if (udp_tunnel == NULL)
7797 switch (udp_tunnel->prot_type) {
7798 case RTE_TUNNEL_TYPE_VXLAN:
7799 ret = ixgbe_add_vxlan_port(hw, udp_tunnel->udp_port);
7802 case RTE_TUNNEL_TYPE_GENEVE:
7803 case RTE_TUNNEL_TYPE_TEREDO:
7804 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7809 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7817 /* Remove UDP tunneling port */
7819 ixgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7820 struct rte_eth_udp_tunnel *udp_tunnel)
7823 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7825 if (hw->mac.type != ixgbe_mac_X550 &&
7826 hw->mac.type != ixgbe_mac_X550EM_x &&
7827 hw->mac.type != ixgbe_mac_X550EM_a) {
7831 if (udp_tunnel == NULL)
7834 switch (udp_tunnel->prot_type) {
7835 case RTE_TUNNEL_TYPE_VXLAN:
7836 ret = ixgbe_del_vxlan_port(hw, udp_tunnel->udp_port);
7838 case RTE_TUNNEL_TYPE_GENEVE:
7839 case RTE_TUNNEL_TYPE_TEREDO:
7840 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7844 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7853 ixgbevf_dev_allmulticast_enable(struct rte_eth_dev *dev)
7855 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7857 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_ALLMULTI);
7861 ixgbevf_dev_allmulticast_disable(struct rte_eth_dev *dev)
7863 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7865 hw->mac.ops.update_xcast_mode(hw, IXGBEVF_XCAST_MODE_MULTI);
7868 static void ixgbevf_mbx_process(struct rte_eth_dev *dev)
7870 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7873 if (ixgbe_read_mbx(hw, &in_msg, 1, 0))
7876 /* PF reset VF event */
7877 if (in_msg == IXGBE_PF_CONTROL_MSG)
7878 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
7883 ixgbevf_dev_interrupt_get_status(struct rte_eth_dev *dev)
7886 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7887 struct ixgbe_interrupt *intr =
7888 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7889 ixgbevf_intr_disable(hw);
7891 /* read-on-clear nic registers here */
7892 eicr = IXGBE_READ_REG(hw, IXGBE_VTEICR);
7895 /* only one misc vector supported - mailbox */
7896 eicr &= IXGBE_VTEICR_MASK;
7897 if (eicr == IXGBE_MISC_VEC_ID)
7898 intr->flags |= IXGBE_FLAG_MAILBOX;
7904 ixgbevf_dev_interrupt_action(struct rte_eth_dev *dev)
7906 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7907 struct ixgbe_interrupt *intr =
7908 IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
7910 if (intr->flags & IXGBE_FLAG_MAILBOX) {
7911 ixgbevf_mbx_process(dev);
7912 intr->flags &= ~IXGBE_FLAG_MAILBOX;
7915 ixgbevf_intr_enable(hw);
7921 ixgbevf_dev_interrupt_handler(void *param)
7923 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
7925 ixgbevf_dev_interrupt_get_status(dev);
7926 ixgbevf_dev_interrupt_action(dev);
7930 * ixgbe_disable_sec_tx_path_generic - Stops the transmit data path
7931 * @hw: pointer to hardware structure
7933 * Stops the transmit data path and waits for the HW to internally empty
7934 * the Tx security block
7936 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw)
7938 #define IXGBE_MAX_SECTX_POLL 40
7943 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7944 sectxreg |= IXGBE_SECTXCTRL_TX_DIS;
7945 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7946 for (i = 0; i < IXGBE_MAX_SECTX_POLL; i++) {
7947 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT);
7948 if (sectxreg & IXGBE_SECTXSTAT_SECTX_RDY)
7950 /* Use interrupt-safe sleep just in case */
7954 /* For informational purposes only */
7955 if (i >= IXGBE_MAX_SECTX_POLL)
7956 PMD_DRV_LOG(DEBUG, "Tx unit being enabled before security "
7957 "path fully disabled. Continuing with init.");
7959 return IXGBE_SUCCESS;
7963 * ixgbe_enable_sec_tx_path_generic - Enables the transmit data path
7964 * @hw: pointer to hardware structure
7966 * Enables the transmit data path.
7968 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw)
7972 sectxreg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
7973 sectxreg &= ~IXGBE_SECTXCTRL_TX_DIS;
7974 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, sectxreg);
7975 IXGBE_WRITE_FLUSH(hw);
7977 return IXGBE_SUCCESS;
7980 /* restore n-tuple filter */
7982 ixgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
7984 struct ixgbe_filter_info *filter_info =
7985 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
7986 struct ixgbe_5tuple_filter *node;
7988 TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
7989 ixgbe_inject_5tuple_filter(dev, node);
7993 /* restore ethernet type filter */
7995 ixgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
7997 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7998 struct ixgbe_filter_info *filter_info =
7999 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8002 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8003 if (filter_info->ethertype_mask & (1 << i)) {
8004 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
8005 filter_info->ethertype_filters[i].etqf);
8006 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i),
8007 filter_info->ethertype_filters[i].etqs);
8008 IXGBE_WRITE_FLUSH(hw);
8013 /* restore SYN filter */
8015 ixgbe_syn_filter_restore(struct rte_eth_dev *dev)
8017 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8018 struct ixgbe_filter_info *filter_info =
8019 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8022 synqf = filter_info->syn_info;
8024 if (synqf & IXGBE_SYN_FILTER_ENABLE) {
8025 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, synqf);
8026 IXGBE_WRITE_FLUSH(hw);
8030 /* restore L2 tunnel filter */
8032 ixgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
8034 struct ixgbe_l2_tn_info *l2_tn_info =
8035 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8036 struct ixgbe_l2_tn_filter *node;
8037 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8039 TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
8040 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
8041 l2_tn_conf.tunnel_id = node->key.tn_id;
8042 l2_tn_conf.pool = node->pool;
8043 (void)ixgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
8048 ixgbe_filter_restore(struct rte_eth_dev *dev)
8050 ixgbe_ntuple_filter_restore(dev);
8051 ixgbe_ethertype_filter_restore(dev);
8052 ixgbe_syn_filter_restore(dev);
8053 ixgbe_fdir_filter_restore(dev);
8054 ixgbe_l2_tn_filter_restore(dev);
8060 ixgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
8062 struct ixgbe_l2_tn_info *l2_tn_info =
8063 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8064 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8066 if (l2_tn_info->e_tag_en)
8067 (void)ixgbe_e_tag_enable(hw);
8069 if (l2_tn_info->e_tag_fwd_en)
8070 (void)ixgbe_e_tag_forwarding_en_dis(dev, 1);
8072 (void)ixgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
8075 /* remove all the n-tuple filters */
8077 ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
8079 struct ixgbe_filter_info *filter_info =
8080 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8081 struct ixgbe_5tuple_filter *p_5tuple;
8083 while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
8084 ixgbe_remove_5tuple_filter(dev, p_5tuple);
8087 /* remove all the ether type filters */
8089 ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
8091 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8092 struct ixgbe_filter_info *filter_info =
8093 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8096 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
8097 if (filter_info->ethertype_mask & (1 << i) &&
8098 !filter_info->ethertype_filters[i].conf) {
8099 (void)ixgbe_ethertype_filter_remove(filter_info,
8101 IXGBE_WRITE_REG(hw, IXGBE_ETQF(i), 0);
8102 IXGBE_WRITE_REG(hw, IXGBE_ETQS(i), 0);
8103 IXGBE_WRITE_FLUSH(hw);
8108 /* remove the SYN filter */
8110 ixgbe_clear_syn_filter(struct rte_eth_dev *dev)
8112 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8113 struct ixgbe_filter_info *filter_info =
8114 IXGBE_DEV_PRIVATE_TO_FILTER_INFO(dev->data->dev_private);
8116 if (filter_info->syn_info & IXGBE_SYN_FILTER_ENABLE) {
8117 filter_info->syn_info = 0;
8119 IXGBE_WRITE_REG(hw, IXGBE_SYNQF, 0);
8120 IXGBE_WRITE_FLUSH(hw);
8124 /* remove all the L2 tunnel filters */
8126 ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
8128 struct ixgbe_l2_tn_info *l2_tn_info =
8129 IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(dev->data->dev_private);
8130 struct ixgbe_l2_tn_filter *l2_tn_filter;
8131 struct rte_eth_l2_tunnel_conf l2_tn_conf;
8134 while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
8135 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
8136 l2_tn_conf.tunnel_id = l2_tn_filter->key.tn_id;
8137 l2_tn_conf.pool = l2_tn_filter->pool;
8138 ret = ixgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
8146 RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd);
8147 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map);
8148 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe, "* igb_uio | uio_pci_generic | vfio-pci");
8149 RTE_PMD_REGISTER_PCI(net_ixgbe_vf, rte_ixgbevf_pmd);
8150 RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe_vf, pci_id_ixgbevf_map);
8151 RTE_PMD_REGISTER_KMOD_DEP(net_ixgbe_vf, "* igb_uio | vfio-pci");