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34 #ifndef _IXGBE_ETHDEV_H_
35 #define _IXGBE_ETHDEV_H_
36 #include "base/ixgbe_dcb.h"
37 #include "base/ixgbe_dcb_82599.h"
38 #include "base/ixgbe_dcb_82598.h"
39 #include "ixgbe_bypass.h"
44 /* need update link, bit flag */
45 #define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
46 #define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
47 #define IXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
48 #define IXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
49 #define IXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
52 * Defines that were not part of ixgbe_type.h as they are not used by the
55 #define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
56 #define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
57 #define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
58 #define IXGBE_RXDADV_ERR_CKSUM_BIT 30
59 #define IXGBE_RXDADV_ERR_CKSUM_MSK 3
60 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
61 #define IXGBE_NB_STAT_MAPPING_REGS 32
62 #define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
63 #define IXGBE_VFTA_SIZE 128
64 #define IXGBE_VLAN_TAG_SIZE 4
65 #define IXGBE_MAX_RX_QUEUE_NUM 128
66 #define IXGBE_MAX_INTR_QUEUE_NUM 15
67 #define IXGBE_VMDQ_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
68 #define IXGBE_DCB_NB_QUEUES IXGBE_MAX_RX_QUEUE_NUM
69 #define IXGBE_NONE_MODE_TX_NB_QUEUES 64
72 #define NBBY 8 /* number of bits in a byte */
74 #define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
76 /* EITR Interval is in 2048ns uinits for 1G and 10G link */
77 #define IXGBE_EITR_INTERVAL_UNIT_NS 2048
78 #define IXGBE_EITR_ITR_INT_SHIFT 3
79 #define IXGBE_EITR_INTERVAL_US(us) \
80 (((us) * 1000 / IXGBE_EITR_INTERVAL_UNIT_NS << IXGBE_EITR_ITR_INT_SHIFT) & \
81 IXGBE_EITR_ITR_INT_MASK)
84 /* Loopback operation modes */
85 /* 82599 specific loopback operation types */
86 #define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
87 #define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
89 #define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
91 #define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
92 #define IXGBE_RTTBCNRC_RF_INT_MASK_M \
93 (IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
95 #define IXGBE_MAX_QUEUE_NUM_PER_VF 8
97 #define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
98 #define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
99 #define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
100 #define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
102 #define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
103 #define IXGBE_ETQF_SHIFT 16
104 #define IXGBE_ETQF_UP_EN 0x00080000
105 #define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
106 #define IXGBE_ETQF_MAX_PRI 7
108 #define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
109 #define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
110 #define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
112 #define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
113 #define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
114 #define IXGBE_L34T_IMIR_LLI 0x00100000
115 #define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
116 #define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
117 #define IXGBE_5TUPLE_MAX_PRI 7
118 #define IXGBE_5TUPLE_MIN_PRI 1
120 #define IXGBE_RSS_OFFLOAD_ALL ( \
122 ETH_RSS_NONFRAG_IPV4_TCP | \
123 ETH_RSS_NONFRAG_IPV4_UDP | \
125 ETH_RSS_NONFRAG_IPV6_TCP | \
126 ETH_RSS_NONFRAG_IPV6_UDP | \
128 ETH_RSS_IPV6_TCP_EX | \
131 #define IXGBE_VF_IRQ_ENABLE_MASK 3 /* vf irq enable mask */
132 #define IXGBE_VF_MAXMSIVECTOR 1
134 #define IXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
135 #define IXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
137 #define IXGBE_SECTX_MINSECIFG_MASK 0x0000000F
139 #define IXGBE_MACSEC_PNTHRSH 0xFFFFFE00
141 #define IXGBE_MAX_FDIR_FILTER_NUM (1024 * 32)
142 #define IXGBE_MAX_L2_TN_FILTER_NUM 128
144 #define MAC_TYPE_FILTER_SUP_EXT(type) do {\
145 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540)\
149 #define MAC_TYPE_FILTER_SUP(type) do {\
150 if ((type) != ixgbe_mac_82599EB && (type) != ixgbe_mac_X540 &&\
151 (type) != ixgbe_mac_X550 && (type) != ixgbe_mac_X550EM_x &&\
152 (type) != ixgbe_mac_X550EM_a)\
157 * Information about the fdir mode.
159 struct ixgbe_hw_fdir_mask {
160 uint16_t vlan_tci_mask;
161 uint32_t src_ipv4_mask;
162 uint32_t dst_ipv4_mask;
163 uint16_t src_ipv6_mask;
164 uint16_t dst_ipv6_mask;
165 uint16_t src_port_mask;
166 uint16_t dst_port_mask;
167 uint16_t flex_bytes_mask;
168 uint8_t mac_addr_byte_mask;
169 uint32_t tunnel_id_mask;
170 uint8_t tunnel_type_mask;
173 struct ixgbe_fdir_filter {
174 TAILQ_ENTRY(ixgbe_fdir_filter) entries;
175 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
176 uint32_t fdirflags; /* drop or forward */
177 uint32_t fdirhash; /* hash value for fdir */
178 uint8_t queue; /* assigned rx queue */
181 /* list of fdir filters */
182 TAILQ_HEAD(ixgbe_fdir_filter_list, ixgbe_fdir_filter);
184 struct ixgbe_fdir_rule {
185 struct ixgbe_hw_fdir_mask mask;
186 union ixgbe_atr_input ixgbe_fdir; /* key of fdir filter*/
187 bool b_spec; /* If TRUE, ixgbe_fdir, fdirflags, queue have meaning. */
188 bool b_mask; /* If TRUE, mask has meaning. */
189 enum rte_fdir_mode mode; /* IP, MAC VLAN, Tunnel */
190 uint32_t fdirflags; /* drop or forward */
191 uint32_t soft_id; /* an unique value for this rule */
192 uint8_t queue; /* assigned rx queue */
193 uint8_t flex_bytes_offset;
196 struct ixgbe_hw_fdir_info {
197 struct ixgbe_hw_fdir_mask mask;
198 uint8_t flex_bytes_offset;
207 struct ixgbe_fdir_filter_list fdir_list; /* filter list*/
208 /* store the pointers of the filters, index is the hash value. */
209 struct ixgbe_fdir_filter **hash_map;
210 struct rte_hash *hash_handle; /* cuckoo hash handler */
211 bool mask_added; /* If already got mask from consistent filter */
214 /* structure for interrupt relative data */
215 struct ixgbe_interrupt {
218 /*to save original mask during delayed handler */
219 uint32_t mask_original;
222 struct ixgbe_stat_mapping_registers {
223 uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
224 uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
228 uint32_t vfta[IXGBE_VFTA_SIZE];
231 struct ixgbe_hwstrip {
232 uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
236 * VF data which used by PF host only
238 #define IXGBE_MAX_VF_MC_ENTRIES 30
239 #define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
240 #define IXGBE_MAX_UTA 128
242 struct ixgbe_uta_info {
243 uint8_t uc_filter_type;
245 uint32_t uta_shadow[IXGBE_MAX_UTA];
248 #define IXGBE_MAX_MIRROR_RULES 4 /* Maximum nb. of mirror rules. */
250 struct ixgbe_mirror_info {
251 struct rte_eth_mirror_conf mr_conf[IXGBE_MAX_MIRROR_RULES];
252 /**< store PF mirror rules configuration*/
255 struct ixgbe_vf_info {
256 uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
257 uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
258 uint16_t num_vf_mc_hashes;
259 uint16_t default_vf_vlan_id;
260 uint16_t vlans_enabled;
262 uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
264 uint8_t spoofchk_enabled;
269 * Possible l4type of 5tuple filters.
271 enum ixgbe_5tuple_protocol {
272 IXGBE_FILTER_PROTOCOL_TCP = 0,
273 IXGBE_FILTER_PROTOCOL_UDP,
274 IXGBE_FILTER_PROTOCOL_SCTP,
275 IXGBE_FILTER_PROTOCOL_NONE,
278 TAILQ_HEAD(ixgbe_5tuple_filter_list, ixgbe_5tuple_filter);
280 struct ixgbe_5tuple_filter_info {
285 enum ixgbe_5tuple_protocol proto; /* l4 protocol. */
286 uint8_t priority; /* seven levels (001b-111b), 111b is highest,
287 used when more than one filter matches. */
288 uint8_t dst_ip_mask:1, /* if mask is 1b, do not compare dst ip. */
289 src_ip_mask:1, /* if mask is 1b, do not compare src ip. */
290 dst_port_mask:1, /* if mask is 1b, do not compare dst port. */
291 src_port_mask:1, /* if mask is 1b, do not compare src port. */
292 proto_mask:1; /* if mask is 1b, do not compare protocol. */
295 /* 5tuple filter structure */
296 struct ixgbe_5tuple_filter {
297 TAILQ_ENTRY(ixgbe_5tuple_filter) entries;
298 uint16_t index; /* the index of 5tuple filter */
299 struct ixgbe_5tuple_filter_info filter_info;
300 uint16_t queue; /* rx queue assigned to */
303 #define IXGBE_5TUPLE_ARRAY_SIZE \
304 (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \
305 (sizeof(uint32_t) * NBBY))
307 struct ixgbe_ethertype_filter {
312 * If this filter is added by configuration,
313 * it should not be removed.
319 * Structure to store filters' info.
321 struct ixgbe_filter_info {
322 uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
323 /* store used ethertype filters*/
324 struct ixgbe_ethertype_filter ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
325 /* Bit mask for every used 5tuple filter */
326 uint32_t fivetuple_mask[IXGBE_5TUPLE_ARRAY_SIZE];
327 struct ixgbe_5tuple_filter_list fivetuple_list;
328 /* store the SYN filter info */
332 struct ixgbe_l2_tn_key {
333 enum rte_eth_tunnel_type l2_tn_type;
337 struct ixgbe_l2_tn_filter {
338 TAILQ_ENTRY(ixgbe_l2_tn_filter) entries;
339 struct ixgbe_l2_tn_key key;
343 TAILQ_HEAD(ixgbe_l2_tn_filter_list, ixgbe_l2_tn_filter);
345 struct ixgbe_l2_tn_info {
346 struct ixgbe_l2_tn_filter_list l2_tn_list;
347 struct ixgbe_l2_tn_filter **hash_map;
348 struct rte_hash *hash_handle;
349 bool e_tag_en; /* e-tag enabled */
350 bool e_tag_fwd_en; /* e-tag based forwarding enabled */
351 bool e_tag_ether_type; /* ether type for e-tag */
355 enum rte_filter_type filter_type;
358 /* ntuple filter list structure */
359 struct ixgbe_ntuple_filter_ele {
360 TAILQ_ENTRY(ixgbe_ntuple_filter_ele) entries;
361 struct rte_eth_ntuple_filter filter_info;
363 /* ethertype filter list structure */
364 struct ixgbe_ethertype_filter_ele {
365 TAILQ_ENTRY(ixgbe_ethertype_filter_ele) entries;
366 struct rte_eth_ethertype_filter filter_info;
368 /* syn filter list structure */
369 struct ixgbe_eth_syn_filter_ele {
370 TAILQ_ENTRY(ixgbe_eth_syn_filter_ele) entries;
371 struct rte_eth_syn_filter filter_info;
373 /* fdir filter list structure */
374 struct ixgbe_fdir_rule_ele {
375 TAILQ_ENTRY(ixgbe_fdir_rule_ele) entries;
376 struct ixgbe_fdir_rule filter_info;
378 /* l2_tunnel filter list structure */
379 struct ixgbe_eth_l2_tunnel_conf_ele {
380 TAILQ_ENTRY(ixgbe_eth_l2_tunnel_conf_ele) entries;
381 struct rte_eth_l2_tunnel_conf filter_info;
383 /* ixgbe_flow memory list structure */
384 struct ixgbe_flow_mem {
385 TAILQ_ENTRY(ixgbe_flow_mem) entries;
386 struct rte_flow *flow;
389 TAILQ_HEAD(ixgbe_ntuple_filter_list, ixgbe_ntuple_filter_ele);
390 struct ixgbe_ntuple_filter_list filter_ntuple_list;
391 TAILQ_HEAD(ixgbe_ethertype_filter_list, ixgbe_ethertype_filter_ele);
392 struct ixgbe_ethertype_filter_list filter_ethertype_list;
393 TAILQ_HEAD(ixgbe_syn_filter_list, ixgbe_eth_syn_filter_ele);
394 struct ixgbe_syn_filter_list filter_syn_list;
395 TAILQ_HEAD(ixgbe_fdir_rule_filter_list, ixgbe_fdir_rule_ele);
396 struct ixgbe_fdir_rule_filter_list filter_fdir_list;
397 TAILQ_HEAD(ixgbe_l2_tunnel_filter_list, ixgbe_eth_l2_tunnel_conf_ele);
398 struct ixgbe_l2_tunnel_filter_list filter_l2_tunnel_list;
399 TAILQ_HEAD(ixgbe_flow_mem_list, ixgbe_flow_mem);
400 struct ixgbe_flow_mem_list ixgbe_flow_list;
403 * Statistics counters collected by the MACsec
405 struct ixgbe_macsec_stats {
406 /* TX port statistics */
407 uint64_t out_pkts_untagged;
408 uint64_t out_pkts_encrypted;
409 uint64_t out_pkts_protected;
410 uint64_t out_octets_encrypted;
411 uint64_t out_octets_protected;
413 /* RX port statistics */
414 uint64_t in_pkts_untagged;
415 uint64_t in_pkts_badtag;
416 uint64_t in_pkts_nosci;
417 uint64_t in_pkts_unknownsci;
418 uint64_t in_octets_decrypted;
419 uint64_t in_octets_validated;
421 /* RX SC statistics */
422 uint64_t in_pkts_unchecked;
423 uint64_t in_pkts_delayed;
424 uint64_t in_pkts_late;
426 /* RX SA statistics */
428 uint64_t in_pkts_invalid;
429 uint64_t in_pkts_notvalid;
430 uint64_t in_pkts_unusedsa;
431 uint64_t in_pkts_notusingsa;
434 /* The configuration of bandwidth */
435 struct ixgbe_bw_conf {
436 uint8_t tc_num; /* Number of TCs. */
440 * Structure to store private data for each driver instance (for each port).
442 struct ixgbe_adapter {
444 struct ixgbe_hw_stats stats;
445 struct ixgbe_macsec_stats macsec_stats;
446 struct ixgbe_hw_fdir_info fdir;
447 struct ixgbe_interrupt intr;
448 struct ixgbe_stat_mapping_registers stat_mappings;
449 struct ixgbe_vfta shadow_vfta;
450 struct ixgbe_hwstrip hwstrip;
451 struct ixgbe_dcb_config dcb_config;
452 struct ixgbe_mirror_info mr_data;
453 struct ixgbe_vf_info *vfdata;
454 struct ixgbe_uta_info uta_info;
455 #ifdef RTE_LIBRTE_IXGBE_BYPASS
456 struct ixgbe_bypass_info bps;
457 #endif /* RTE_LIBRTE_IXGBE_BYPASS */
458 struct ixgbe_filter_info filter;
459 struct ixgbe_l2_tn_info l2_tn;
460 struct ixgbe_bw_conf bw_conf;
462 bool rx_bulk_alloc_allowed;
464 struct rte_timecounter systime_tc;
465 struct rte_timecounter rx_tstamp_tc;
466 struct rte_timecounter tx_tstamp_tc;
469 #define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
470 (&((struct ixgbe_adapter *)adapter)->hw)
472 #define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
473 (&((struct ixgbe_adapter *)adapter)->stats)
475 #define IXGBE_DEV_PRIVATE_TO_MACSEC_STATS(adapter) \
476 (&((struct ixgbe_adapter *)adapter)->macsec_stats)
478 #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
479 (&((struct ixgbe_adapter *)adapter)->intr)
481 #define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
482 (&((struct ixgbe_adapter *)adapter)->fdir)
484 #define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
485 (&((struct ixgbe_adapter *)adapter)->stat_mappings)
487 #define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
488 (&((struct ixgbe_adapter *)adapter)->shadow_vfta)
490 #define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
491 (&((struct ixgbe_adapter *)adapter)->hwstrip)
493 #define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
494 (&((struct ixgbe_adapter *)adapter)->dcb_config)
496 #define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
497 (&((struct ixgbe_adapter *)adapter)->vfdata)
499 #define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
500 (&((struct ixgbe_adapter *)adapter)->mr_data)
502 #define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
503 (&((struct ixgbe_adapter *)adapter)->uta_info)
505 #define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
506 (&((struct ixgbe_adapter *)adapter)->filter)
508 #define IXGBE_DEV_PRIVATE_TO_L2_TN_INFO(adapter) \
509 (&((struct ixgbe_adapter *)adapter)->l2_tn)
511 #define IXGBE_DEV_PRIVATE_TO_BW_CONF(adapter) \
512 (&((struct ixgbe_adapter *)adapter)->bw_conf)
515 * RX/TX function prototypes
517 void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
519 void ixgbe_dev_free_queues(struct rte_eth_dev *dev);
521 void ixgbe_dev_rx_queue_release(void *rxq);
523 void ixgbe_dev_tx_queue_release(void *txq);
525 int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
526 uint16_t nb_rx_desc, unsigned int socket_id,
527 const struct rte_eth_rxconf *rx_conf,
528 struct rte_mempool *mb_pool);
530 int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
531 uint16_t nb_tx_desc, unsigned int socket_id,
532 const struct rte_eth_txconf *tx_conf);
534 uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
535 uint16_t rx_queue_id);
537 int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
539 int ixgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
540 int ixgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
542 int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
544 void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
546 int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
548 int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
550 int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
552 int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
554 int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
556 void ixgbe_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
557 struct rte_eth_rxq_info *qinfo);
559 void ixgbe_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
560 struct rte_eth_txq_info *qinfo);
562 int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
564 void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
566 void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
568 uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
571 uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
574 uint16_t ixgbe_recv_pkts_lro_single_alloc(void *rx_queue,
575 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
576 uint16_t ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue,
577 struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
579 uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
582 uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
585 uint16_t ixgbe_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
588 int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
589 struct rte_eth_rss_conf *rss_conf);
591 int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
592 struct rte_eth_rss_conf *rss_conf);
594 uint16_t ixgbe_reta_size_get(enum ixgbe_mac_type mac_type);
596 uint32_t ixgbe_reta_reg_get(enum ixgbe_mac_type mac_type, uint16_t reta_idx);
598 uint32_t ixgbe_mrqc_reg_get(enum ixgbe_mac_type mac_type);
600 uint32_t ixgbe_rssrk_reg_get(enum ixgbe_mac_type mac_type, uint8_t i);
602 bool ixgbe_rss_update_sp(enum ixgbe_mac_type mac_type);
604 int ixgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
605 struct rte_eth_ntuple_filter *filter,
607 int ixgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
608 struct rte_eth_ethertype_filter *filter,
610 int ixgbe_syn_filter_set(struct rte_eth_dev *dev,
611 struct rte_eth_syn_filter *filter,
614 ixgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
615 struct rte_eth_l2_tunnel_conf *l2_tunnel,
618 ixgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
619 struct rte_eth_l2_tunnel_conf *l2_tunnel);
620 void ixgbe_filterlist_flush(void);
622 * Flow director function prototypes
624 int ixgbe_fdir_configure(struct rte_eth_dev *dev);
625 int ixgbe_fdir_set_input_mask(struct rte_eth_dev *dev);
626 int ixgbe_fdir_set_flexbytes_offset(struct rte_eth_dev *dev,
628 int ixgbe_fdir_filter_program(struct rte_eth_dev *dev,
629 struct ixgbe_fdir_rule *rule,
630 bool del, bool update);
632 void ixgbe_configure_dcb(struct rte_eth_dev *dev);
635 * misc function prototypes
637 void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
639 void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
641 void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
643 void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
645 void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
647 void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev);
649 void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
651 int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
653 uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
655 int ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
656 enum rte_filter_op filter_op, void *arg);
657 void ixgbe_fdir_filter_restore(struct rte_eth_dev *dev);
658 int ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev);
660 extern const struct rte_flow_ops ixgbe_flow_ops;
662 void ixgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev);
663 void ixgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev);
664 void ixgbe_clear_syn_filter(struct rte_eth_dev *dev);
665 int ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev);
667 int ixgbe_disable_sec_tx_path_generic(struct ixgbe_hw *hw);
669 int ixgbe_enable_sec_tx_path_generic(struct ixgbe_hw *hw);
671 int ixgbe_vt_check(struct ixgbe_hw *hw);
672 int ixgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
673 uint16_t tx_rate, uint64_t q_msk);
674 bool is_ixgbe_supported(struct rte_eth_dev *dev);
677 ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info,
682 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
683 if (filter_info->ethertype_filters[i].ethertype == ethertype &&
684 (filter_info->ethertype_mask & (1 << i)))
691 ixgbe_ethertype_filter_insert(struct ixgbe_filter_info *filter_info,
692 struct ixgbe_ethertype_filter *ethertype_filter)
696 for (i = 0; i < IXGBE_MAX_ETQF_FILTERS; i++) {
697 if (!(filter_info->ethertype_mask & (1 << i))) {
698 filter_info->ethertype_mask |= 1 << i;
699 filter_info->ethertype_filters[i].ethertype =
700 ethertype_filter->ethertype;
701 filter_info->ethertype_filters[i].etqf =
702 ethertype_filter->etqf;
703 filter_info->ethertype_filters[i].etqs =
704 ethertype_filter->etqs;
705 filter_info->ethertype_filters[i].conf =
706 ethertype_filter->conf;
714 ixgbe_ethertype_filter_remove(struct ixgbe_filter_info *filter_info,
717 if (idx >= IXGBE_MAX_ETQF_FILTERS)
719 filter_info->ethertype_mask &= ~(1 << idx);
720 filter_info->ethertype_filters[idx].ethertype = 0;
721 filter_info->ethertype_filters[idx].etqf = 0;
722 filter_info->ethertype_filters[idx].etqs = 0;
723 filter_info->ethertype_filters[idx].etqs = FALSE;
727 #endif /* _IXGBE_ETHDEV_H_ */