drivers/net/ixgbe/ixgbe_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdint.h>
  36 #include <stdarg.h>
  37 #include <errno.h>
  38 #include <sys/queue.h>
  39
  40 #include <rte_interrupts.h>
  41 #include <rte_log.h>
  42 #include <rte_debug.h>
  43 #include <rte_pci.h>
  44 #include <rte_ether.h>
  45 #include <rte_ethdev.h>
  46 #include <rte_malloc.h>
  47
  48 #include "ixgbe_logs.h"
  49 #include "base/ixgbe_api.h"
  50 #include "base/ixgbe_common.h"
  51 #include "ixgbe_ethdev.h"
  52
  53 /* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
  54 #define FDIRCTRL_PBALLOC_MASK           0x03
  55
  56 /* For calculating memory required for FDIR filters */
  57 #define PBALLOC_SIZE_SHIFT              15
  58
  59 /* Number of bits used to mask bucket hash for different pballoc sizes */
  60 #define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
  61 #define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
  62 #define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
  63 #define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
  64 #define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
  65 #define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
  66 #define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
  67 #define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
  68 #define IXGBE_MAX_FLX_SOURCE_OFF        62
  69 #define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
  70 #define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
  71
  72 #define IXGBE_FDIR_FLOW_TYPES ( \
  73         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  74         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  75         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  76         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  77         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  78         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  79         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  80         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
  81
  82 #define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
  83         uint8_t ipv6_addr[16]; \
  84         uint8_t i; \
  85         rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
  86         (ipv6m) = 0; \
  87         for (i = 0; i < sizeof(ipv6_addr); i++) { \
  88                 if (ipv6_addr[i] == UINT8_MAX) \
  89                         (ipv6m) |= 1 << i; \
  90                 else if (ipv6_addr[i] != 0) { \
  91                         PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
  92                         return -EINVAL; \
  93                 } \
  94         } \
  95 } while (0)
  96
  97 #define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
  98         uint8_t ipv6_addr[16]; \
  99         uint8_t i; \
 100         for (i = 0; i < sizeof(ipv6_addr); i++) { \
 101                 if ((ipv6m) & (1 << i)) \
 102                         ipv6_addr[i] = UINT8_MAX; \
 103                 else \
 104                         ipv6_addr[i] = 0; \
 105         } \
 106         rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
 107 } while (0)
 108
 109 #define DEFAULT_VXLAN_PORT 4789
 110 #define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
 111
 112 static int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
 113 static int fdir_set_input_mask(struct rte_eth_dev *dev,
 114                                const struct rte_eth_fdir_masks *input_mask);
 115 static int fdir_set_input_mask_82599(struct rte_eth_dev *dev,
 116                 const struct rte_eth_fdir_masks *input_mask);
 117 static int fdir_set_input_mask_x550(struct rte_eth_dev *dev,
 118                                     const struct rte_eth_fdir_masks *input_mask);
 119 static int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 120                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
 121 static int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
 122 static int ixgbe_fdir_filter_to_atr_input(
 123                 const struct rte_eth_fdir_filter *fdir_filter,
 124                 union ixgbe_atr_input *input,
 125                 enum rte_fdir_mode mode);
 126 static uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 127                                  uint32_t key);
 128 static uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 129                 enum rte_fdir_pballoc_type pballoc);
 130 static uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 131                 enum rte_fdir_pballoc_type pballoc);
 132 static int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 133                         union ixgbe_atr_input *input, uint8_t queue,
 134                         uint32_t fdircmd, uint32_t fdirhash,
 135                         enum rte_fdir_mode mode);
 136 static int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
 137                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
 138                 uint32_t fdirhash);
 139 static int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
 140                               const struct rte_eth_fdir_filter *fdir_filter,
 141                               bool del,
 142                               bool update);
 143 static int ixgbe_fdir_flush(struct rte_eth_dev *dev);
 144 static void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
 145                         struct rte_eth_fdir_info *fdir_info);
 146 static void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
 147                         struct rte_eth_fdir_stats *fdir_stats);
 148
 149 /**
 150  * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
 151  * It adds extra configuration of fdirctrl that is common for all filter types.
 152  *
 153  *  Initialize Flow Director control registers
 154  *  @hw: pointer to hardware structure
 155  *  @fdirctrl: value to write to flow director control register
 156  **/
 157 static int
 158 fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
 159 {
 160         int i;
 161
 162         PMD_INIT_FUNC_TRACE();
 163
 164         /* Prime the keys for hashing */
 165         IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
 166         IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 167
 168         /*
 169          * Continue setup of fdirctrl register bits:
 170          *  Set the maximum length per hash bucket to 0xA filters
 171          *  Send interrupt when 64 filters are left
 172          */
 173         fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 174                     (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 175
 176         /*
 177          * Poll init-done after we write the register.  Estimated times:
 178          *      10G: PBALLOC = 11b, timing is 60us
 179          *       1G: PBALLOC = 11b, timing is 600us
 180          *     100M: PBALLOC = 11b, timing is 6ms
 181          *
 182          *     Multiple these timings by 4 if under full Rx load
 183          *
 184          * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 185          * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 186          * this might not finish in our poll time, but we can live with that
 187          * for now.
 188          */
 189         IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 190         IXGBE_WRITE_FLUSH(hw);
 191         for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 192                 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 193                                    IXGBE_FDIRCTRL_INIT_DONE)
 194                         break;
 195                 msec_delay(1);
 196         }
 197
 198         if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 199                 PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
 200                 return -ETIMEDOUT;
 201         }
 202         return 0;
 203 }
 204
 205 /*
 206  * Set appropriate bits in fdirctrl for: variable reporting levels, moving
 207  * flexbytes matching field, and drop queue (only for perfect matching mode).
 208  */
 209 static inline int
 210 configure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
 211 {
 212         *fdirctrl = 0;
 213
 214         switch (conf->pballoc) {
 215         case RTE_FDIR_PBALLOC_64K:
 216                 /* 8k - 1 signature filters */
 217                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
 218                 break;
 219         case RTE_FDIR_PBALLOC_128K:
 220                 /* 16k - 1 signature filters */
 221                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
 222                 break;
 223         case RTE_FDIR_PBALLOC_256K:
 224                 /* 32k - 1 signature filters */
 225                 *fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
 226                 break;
 227         default:
 228                 /* bad value */
 229                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
 230                 return -EINVAL;
 231         };
 232
 233         /* status flags: write hash & swindex in the rx descriptor */
 234         switch (conf->status) {
 235         case RTE_FDIR_NO_REPORT_STATUS:
 236                 /* do nothing, default mode */
 237                 break;
 238         case RTE_FDIR_REPORT_STATUS:
 239                 /* report status when the packet matches a fdir rule */
 240                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
 241                 break;
 242         case RTE_FDIR_REPORT_STATUS_ALWAYS:
 243                 /* always report status */
 244                 *fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
 245                 break;
 246         default:
 247                 /* bad value */
 248                 PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
 249                 return -EINVAL;
 250         };
 251
 252         *fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
 253                      IXGBE_FDIRCTRL_FLEX_SHIFT;
 254
 255         if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
 256             conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 257                 *fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
 258                 *fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
 259                 if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 260                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
 261                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 262                 else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 263                         *fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
 264                                         << IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
 265         }
 266
 267         return 0;
 268 }
 269
 270 /**
 271  * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
 272  *
 273  *  @hi_dword: Bits 31:16 mask to be bit swapped.
 274  *  @lo_dword: Bits 15:0  mask to be bit swapped.
 275  *
 276  *  Flow director uses several registers to store 2 x 16 bit masks with the
 277  *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
 278  *  mask affects the MS bit/byte of the target. This function reverses the
 279  *  bits in these masks.
 280  *  **/
 281 static inline uint32_t
 282 reverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
 283 {
 284         uint32_t mask = hi_dword << 16;
 285
 286         mask |= lo_dword;
 287         mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 288         mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
 289         mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
 290         return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 291 }
 292
 293 /*
 294  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 295  * but makes use of the rte_fdir_masks structure to see which bits to set.
 296  */
 297 static int
 298 fdir_set_input_mask_82599(struct rte_eth_dev *dev,
 299                 const struct rte_eth_fdir_masks *input_mask)
 300 {
 301         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 302         struct ixgbe_hw_fdir_info *info =
 303                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 304         /*
 305          * mask VM pool and DIPv6 since there are currently not supported
 306          * mask FLEX byte, it will be set in flex_conf
 307          */
 308         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
 309         uint32_t fdirtcpm;  /* TCP source and destination port masks. */
 310         uint32_t fdiripv6m; /* IPv6 source and destination masks. */
 311         uint16_t dst_ipv6m = 0;
 312         uint16_t src_ipv6m = 0;
 313         volatile uint32_t *reg;
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         /*
 318          * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 319          * are zero, then assume a full mask for that field. Also assume that
 320          * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 321          * cannot be masked out in this implementation.
 322          */
 323         if (input_mask->dst_port_mask == 0 && input_mask->src_port_mask == 0)
 324                 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
 325                 fdirm |= IXGBE_FDIRM_L4P;
 326
 327         if (input_mask->vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 328                 /* mask VLAN Priority */
 329                 fdirm |= IXGBE_FDIRM_VLANP;
 330         else if (input_mask->vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 331                 /* mask VLAN ID */
 332                 fdirm |= IXGBE_FDIRM_VLANID;
 333         else if (input_mask->vlan_tci_mask == 0)
 334                 /* mask VLAN ID and Priority */
 335                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 336         else if (input_mask->vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 337                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 338                 return -EINVAL;
 339         }
 340         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 341
 342         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 343
 344         /* store the TCP/UDP port masks, bit reversed from port layout */
 345         fdirtcpm = reverse_fdir_bitmasks(
 346                         rte_be_to_cpu_16(input_mask->dst_port_mask),
 347                         rte_be_to_cpu_16(input_mask->src_port_mask));
 348
 349         /* write all the same so that UDP, TCP and SCTP use the same mask
 350          * (little-endian)
 351          */
 352         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 353         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
 354         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
 355         info->mask.src_port_mask = input_mask->src_port_mask;
 356         info->mask.dst_port_mask = input_mask->dst_port_mask;
 357
 358         /* Store source and destination IPv4 masks (big-endian),
 359          * can not use IXGBE_WRITE_REG.
 360          */
 361         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
 362         *reg = ~(input_mask->ipv4_mask.src_ip);
 363         reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
 364         *reg = ~(input_mask->ipv4_mask.dst_ip);
 365         info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
 366         info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
 367
 368         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
 369                 /*
 370                  * Store source and destination IPv6 masks (bit reversed)
 371                  */
 372                 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
 373                 IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
 374                 fdiripv6m = (dst_ipv6m << 16) | src_ipv6m;
 375
 376                 IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
 377                 info->mask.src_ipv6_mask = src_ipv6m;
 378                 info->mask.dst_ipv6_mask = dst_ipv6m;
 379         }
 380
 381         return IXGBE_SUCCESS;
 382 }
 383
 384 /*
 385  * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
 386  * but makes use of the rte_fdir_masks structure to see which bits to set.
 387  */
 388 static int
 389 fdir_set_input_mask_x550(struct rte_eth_dev *dev,
 390                          const struct rte_eth_fdir_masks *input_mask)
 391 {
 392         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 393         struct ixgbe_hw_fdir_info *info =
 394                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 395         /* mask VM pool and DIPv6 since there are currently not supported
 396          * mask FLEX byte, it will be set in flex_conf
 397          */
 398         uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
 399                          IXGBE_FDIRM_FLEX;
 400         uint32_t fdiripv6m;
 401         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 402         uint16_t mac_mask;
 403
 404         PMD_INIT_FUNC_TRACE();
 405
 406         /* set the default UDP port for VxLAN */
 407         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
 408                 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, DEFAULT_VXLAN_PORT);
 409
 410         /* some bits must be set for mac vlan or tunnel mode */
 411         fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
 412
 413         if (input_mask->vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
 414                 /* mask VLAN Priority */
 415                 fdirm |= IXGBE_FDIRM_VLANP;
 416         else if (input_mask->vlan_tci_mask == rte_cpu_to_be_16(0xE000))
 417                 /* mask VLAN ID */
 418                 fdirm |= IXGBE_FDIRM_VLANID;
 419         else if (input_mask->vlan_tci_mask == 0)
 420                 /* mask VLAN ID and Priority */
 421                 fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
 422         else if (input_mask->vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
 423                 PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
 424                 return -EINVAL;
 425         }
 426         info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
 427
 428         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 429
 430         fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
 431         fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
 432         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
 433                 fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
 434                                 IXGBE_FDIRIP6M_TNI_VNI;
 435
 436         if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 437                 mac_mask = input_mask->mac_addr_byte_mask;
 438                 fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
 439                                 & IXGBE_FDIRIP6M_INNER_MAC;
 440                 info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
 441
 442                 switch (input_mask->tunnel_type_mask) {
 443                 case 0:
 444                         /* Mask turnnel type */
 445                         fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
 446                         break;
 447                 case 1:
 448                         break;
 449                 default:
 450                         PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
 451                         return -EINVAL;
 452                 }
 453                 info->mask.tunnel_type_mask =
 454                         input_mask->tunnel_type_mask;
 455
 456                 switch (rte_be_to_cpu_32(input_mask->tunnel_id_mask)) {
 457                 case 0x0:
 458                         /* Mask vxlan id */
 459                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
 460                         break;
 461                 case 0x00FFFFFF:
 462                         fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
 463                         break;
 464                 case 0xFFFFFFFF:
 465                         break;
 466                 default:
 467                         PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
 468                         return -EINVAL;
 469                 }
 470                 info->mask.tunnel_id_mask =
 471                         input_mask->tunnel_id_mask;
 472         }
 473
 474         IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
 475         IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF);
 476         IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF);
 477         IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);
 478         IXGBE_WRITE_REG(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF);
 479         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF);
 480
 481         return IXGBE_SUCCESS;
 482 }
 483
 484 static int
 485 fdir_set_input_mask(struct rte_eth_dev *dev,
 486                     const struct rte_eth_fdir_masks *input_mask)
 487 {
 488         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 489
 490         if (mode >= RTE_FDIR_MODE_SIGNATURE &&
 491             mode <= RTE_FDIR_MODE_PERFECT)
 492                 return fdir_set_input_mask_82599(dev, input_mask);
 493         else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 494                  mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
 495                 return fdir_set_input_mask_x550(dev, input_mask);
 496
 497         PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
 498         return -ENOTSUP;
 499 }
 500
 501 /*
 502  * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
 503  * arguments are valid
 504  */
 505 static int
 506 ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
 507                 const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
 508 {
 509         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 510         struct ixgbe_hw_fdir_info *info =
 511                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
 512         const struct rte_eth_flex_payload_cfg *flex_cfg;
 513         const struct rte_eth_fdir_flex_mask *flex_mask;
 514         uint32_t fdirm;
 515         uint16_t flexbytes = 0;
 516         uint16_t i;
 517
 518         fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
 519
 520         if (conf == NULL) {
 521                 PMD_DRV_LOG(ERR, "NULL pointer.");
 522                 return -EINVAL;
 523         }
 524
 525         for (i = 0; i < conf->nb_payloads; i++) {
 526                 flex_cfg = &conf->flex_set[i];
 527                 if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
 528                         PMD_DRV_LOG(ERR, "unsupported payload type.");
 529                         return -EINVAL;
 530                 }
 531                 if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
 532                     (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
 533                     (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
 534                         *fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
 535                         *fdirctrl |=
 536                                 (flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
 537                                         IXGBE_FDIRCTRL_FLEX_SHIFT;
 538                 } else {
 539                         PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
 540                         return -EINVAL;
 541                 }
 542         }
 543
 544         for (i = 0; i < conf->nb_flexmasks; i++) {
 545                 flex_mask = &conf->flex_mask[i];
 546                 if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
 547                         PMD_DRV_LOG(ERR, "flexmask should be set globally.");
 548                         return -EINVAL;
 549                 }
 550                 flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
 551                                         ((flex_mask->mask[1]) & 0xFF));
 552                 if (flexbytes == UINT16_MAX)
 553                         fdirm &= ~IXGBE_FDIRM_FLEX;
 554                 else if (flexbytes != 0) {
 555                         /* IXGBE_FDIRM_FLEX is set by default when set mask */
 556                         PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
 557                         return -EINVAL;
 558                 }
 559         }
 560         IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 561         info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
 562         info->flex_bytes_offset = (uint8_t)((*fdirctrl &
 563                                             IXGBE_FDIRCTRL_FLEX_MASK) >>
 564                                             IXGBE_FDIRCTRL_FLEX_SHIFT);
 565         return 0;
 566 }
 567
 568 int
 569 ixgbe_fdir_configure(struct rte_eth_dev *dev)
 570 {
 571         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 572         int err;
 573         uint32_t fdirctrl, pbsize;
 574         int i;
 575         enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
 576
 577         PMD_INIT_FUNC_TRACE();
 578
 579         if (hw->mac.type != ixgbe_mac_82599EB &&
 580                 hw->mac.type != ixgbe_mac_X540 &&
 581                 hw->mac.type != ixgbe_mac_X550 &&
 582                 hw->mac.type != ixgbe_mac_X550EM_x &&
 583                 hw->mac.type != ixgbe_mac_X550EM_a)
 584                 return -ENOSYS;
 585
 586         /* x550 supports mac-vlan and tunnel mode but other NICs not */
 587         if (hw->mac.type != ixgbe_mac_X550 &&
 588             hw->mac.type != ixgbe_mac_X550EM_x &&
 589             hw->mac.type != ixgbe_mac_X550EM_a &&
 590             mode != RTE_FDIR_MODE_SIGNATURE &&
 591             mode != RTE_FDIR_MODE_PERFECT)
 592                 return -ENOSYS;
 593
 594         err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
 595         if (err)
 596                 return err;
 597
 598         /*
 599          * Before enabling Flow Director, the Rx Packet Buffer size
 600          * must be reduced.  The new value is the current size minus
 601          * flow director memory usage size.
 602          */
 603         pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
 604         IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
 605             (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
 606
 607         /*
 608          * The defaults in the HW for RX PB 1-7 are not zero and so should be
 609          * intialized to zero for non DCB mode otherwise actual total RX PB
 610          * would be bigger than programmed and filter space would run into
 611          * the PB 0 region.
 612          */
 613         for (i = 1; i < 8; i++)
 614                 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
 615
 616         err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
 617         if (err < 0) {
 618                 PMD_INIT_LOG(ERR, " Error on setting FD mask");
 619                 return err;
 620         }
 621         err = ixgbe_set_fdir_flex_conf(dev,
 622                 &dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
 623         if (err < 0) {
 624                 PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
 625                 return err;
 626         }
 627
 628         err = fdir_enable_82599(hw, fdirctrl);
 629         if (err < 0) {
 630                 PMD_INIT_LOG(ERR, " Error on enabling FD.");
 631                 return err;
 632         }
 633         return 0;
 634 }
 635
 636 /*
 637  * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
 638  * by the IXGBE driver code.
 639  */
 640 static int
 641 ixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
 642                 union ixgbe_atr_input *input, enum rte_fdir_mode mode)
 643 {
 644         input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
 645         input->formatted.flex_bytes = (uint16_t)(
 646                 (fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
 647                 (fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
 648
 649         switch (fdir_filter->input.flow_type) {
 650         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 651                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
 652                 break;
 653         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 654                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
 655                 break;
 656         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 657                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
 658                 break;
 659         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 660                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
 661                 break;
 662         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 663                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
 664                 break;
 665         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 666                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
 667                 break;
 668         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 669                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
 670                 break;
 671         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 672                 input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
 673                 break;
 674         default:
 675                 break;
 676         }
 677
 678         switch (fdir_filter->input.flow_type) {
 679         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 680         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 681                 input->formatted.src_port =
 682                         fdir_filter->input.flow.udp4_flow.src_port;
 683                 input->formatted.dst_port =
 684                         fdir_filter->input.flow.udp4_flow.dst_port;
 685         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 686         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 687         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 688                 input->formatted.src_ip[0] =
 689                         fdir_filter->input.flow.ip4_flow.src_ip;
 690                 input->formatted.dst_ip[0] =
 691                         fdir_filter->input.flow.ip4_flow.dst_ip;
 692                 break;
 693
 694         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 695         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 696                 input->formatted.src_port =
 697                         fdir_filter->input.flow.udp6_flow.src_port;
 698                 input->formatted.dst_port =
 699                         fdir_filter->input.flow.udp6_flow.dst_port;
 700         /*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
 701         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 702         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 703                 rte_memcpy(input->formatted.src_ip,
 704                            fdir_filter->input.flow.ipv6_flow.src_ip,
 705                            sizeof(input->formatted.src_ip));
 706                 rte_memcpy(input->formatted.dst_ip,
 707                            fdir_filter->input.flow.ipv6_flow.dst_ip,
 708                            sizeof(input->formatted.dst_ip));
 709                 break;
 710         default:
 711                 break;
 712         }
 713
 714         if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 715                 rte_memcpy(
 716                         input->formatted.inner_mac,
 717                         fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
 718                         sizeof(input->formatted.inner_mac));
 719         } else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
 720                 rte_memcpy(
 721                         input->formatted.inner_mac,
 722                         fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
 723                         sizeof(input->formatted.inner_mac));
 724                 input->formatted.tunnel_type =
 725                         fdir_filter->input.flow.tunnel_flow.tunnel_type;
 726                 input->formatted.tni_vni =
 727                         fdir_filter->input.flow.tunnel_flow.tunnel_id;
 728         }
 729
 730         return 0;
 731 }
 732
 733 /*
 734  * The below function is taken from the FreeBSD IXGBE drivers release
 735  * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
 736  * before returning, as the signature hash can use 16bits.
 737  *
 738  * The newer driver has optimised functions for calculating bucket and
 739  * signature hashes. However they don't support IPv6 type packets for signature
 740  * filters so are not used here.
 741  *
 742  * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
 743  * set.
 744  *
 745  * Compute the hashes for SW ATR
 746  *  @stream: input bitstream to compute the hash on
 747  *  @key: 32-bit hash key
 748  **/
 749 static uint32_t
 750 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
 751                                  uint32_t key)
 752 {
 753         /*
 754          * The algorithm is as follows:
 755          *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
 756          *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
 757          *    and A[n] x B[n] is bitwise AND between same length strings
 758          *
 759          *    K[n] is 16 bits, defined as:
 760          *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
 761          *       for n modulo 32 < 15, K[n] =
 762          *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
 763          *
 764          *    S[n] is 16 bits, defined as:
 765          *       for n >= 15, S[n] = S[n:n - 15]
 766          *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
 767          *
 768          *    To simplify for programming, the algorithm is implemented
 769          *    in software this way:
 770          *
 771          *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
 772          *
 773          *    for (i = 0; i < 352; i+=32)
 774          *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
 775          *
 776          *    lo_hash_dword[15:0]  ^= Stream[15:0];
 777          *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
 778          *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
 779          *
 780          *    hi_hash_dword[31:0]  ^= Stream[351:320];
 781          *
 782          *    if (key[0])
 783          *        hash[15:0] ^= Stream[15:0];
 784          *
 785          *    for (i = 0; i < 16; i++) {
 786          *        if (key[i])
 787          *            hash[15:0] ^= lo_hash_dword[(i+15):i];
 788          *        if (key[i + 16])
 789          *            hash[15:0] ^= hi_hash_dword[(i+15):i];
 790          *    }
 791          *
 792          */
 793         __be32 common_hash_dword = 0;
 794         u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 795         u32 hash_result = 0;
 796         u8 i;
 797
 798         /* record the flow_vm_vlan bits as they are a key part to the hash */
 799         flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
 800
 801         /* generate common hash dword */
 802         for (i = 1; i <= 13; i++)
 803                 common_hash_dword ^= atr_input->dword_stream[i];
 804
 805         hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
 806
 807         /* low dword is word swapped version of common */
 808         lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 809
 810         /* apply flow ID/VM pool/VLAN ID bits to hash words */
 811         hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 812
 813         /* Process bits 0 and 16 */
 814         if (key & 0x0001)
 815                 hash_result ^= lo_hash_dword;
 816         if (key & 0x00010000)
 817                 hash_result ^= hi_hash_dword;
 818
 819         /*
 820          * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 821          * delay this because bit 0 of the stream should not be processed
 822          * so we do not add the vlan until after bit 0 was processed
 823          */
 824         lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 825
 826
 827         /* process the remaining 30 bits in the key 2 bits at a time */
 828         for (i = 15; i; i--) {
 829                 if (key & (0x0001 << i))
 830                         hash_result ^= lo_hash_dword >> i;
 831                 if (key & (0x00010000 << i))
 832                         hash_result ^= hi_hash_dword >> i;
 833         }
 834
 835         return hash_result;
 836 }
 837
 838 static uint32_t
 839 atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 840                 enum rte_fdir_pballoc_type pballoc)
 841 {
 842         if (pballoc == RTE_FDIR_PBALLOC_256K)
 843                 return ixgbe_atr_compute_hash_82599(input,
 844                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 845                                 PERFECT_BUCKET_256KB_HASH_MASK;
 846         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 847                 return ixgbe_atr_compute_hash_82599(input,
 848                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 849                                 PERFECT_BUCKET_128KB_HASH_MASK;
 850         else
 851                 return ixgbe_atr_compute_hash_82599(input,
 852                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 853                                 PERFECT_BUCKET_64KB_HASH_MASK;
 854 }
 855
 856 /**
 857  * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
 858  * @hw: pointer to hardware structure
 859  */
 860 static inline int
 861 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
 862 {
 863         int i;
 864
 865         for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 866                 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
 867                 if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
 868                         return 0;
 869                 rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
 870         }
 871
 872         return -ETIMEDOUT;
 873 }
 874
 875 /*
 876  * Calculate the hash value needed for signature-match filters. In the FreeBSD
 877  * driver, this is done by the optimised function
 878  * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
 879  * doesn't support calculating a hash for an IPv6 filter.
 880  */
 881 static uint32_t
 882 atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
 883                 enum rte_fdir_pballoc_type pballoc)
 884 {
 885         uint32_t bucket_hash, sig_hash;
 886
 887         if (pballoc == RTE_FDIR_PBALLOC_256K)
 888                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 889                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 890                                 SIG_BUCKET_256KB_HASH_MASK;
 891         else if (pballoc == RTE_FDIR_PBALLOC_128K)
 892                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 893                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 894                                 SIG_BUCKET_128KB_HASH_MASK;
 895         else
 896                 bucket_hash = ixgbe_atr_compute_hash_82599(input,
 897                                 IXGBE_ATR_BUCKET_HASH_KEY) &
 898                                 SIG_BUCKET_64KB_HASH_MASK;
 899
 900         sig_hash = ixgbe_atr_compute_hash_82599(input,
 901                         IXGBE_ATR_SIGNATURE_HASH_KEY);
 902
 903         return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
 904 }
 905
 906 /*
 907  * This is based on ixgbe_fdir_write_perfect_filter_82599() in
 908  * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
 909  * added, and IPv6 support also added. The hash value is also pre-calculated
 910  * as the pballoc value is needed to do it.
 911  */
 912 static int
 913 fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 914                         union ixgbe_atr_input *input, uint8_t queue,
 915                         uint32_t fdircmd, uint32_t fdirhash,
 916                         enum rte_fdir_mode mode)
 917 {
 918         uint32_t fdirport, fdirvlan;
 919         u32 addr_low, addr_high;
 920         u32 tunnel_type = 0;
 921         int err = 0;
 922         volatile uint32_t *reg;
 923
 924         if (mode == RTE_FDIR_MODE_PERFECT) {
 925                 /* record the IPv4 address (big-endian)
 926                  * can not use IXGBE_WRITE_REG.
 927                  */
 928                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
 929                 *reg = input->formatted.src_ip[0];
 930                 reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
 931                 *reg = input->formatted.dst_ip[0];
 932
 933                 /* record source and destination port (little-endian)*/
 934                 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
 935                 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
 936                 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
 937                 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
 938         } else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
 939                    mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
 940                 /* for mac vlan and tunnel modes */
 941                 addr_low = ((u32)input->formatted.inner_mac[0] |
 942                             ((u32)input->formatted.inner_mac[1] << 8) |
 943                             ((u32)input->formatted.inner_mac[2] << 16) |
 944                             ((u32)input->formatted.inner_mac[3] << 24));
 945                 addr_high = ((u32)input->formatted.inner_mac[4] |
 946                              ((u32)input->formatted.inner_mac[5] << 8));
 947
 948                 if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
 949                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
 950                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
 951                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
 952                 } else {
 953                         /* tunnel mode */
 954                         if (input->formatted.tunnel_type !=
 955                                 RTE_FDIR_TUNNEL_TYPE_NVGRE)
 956                                 tunnel_type = 0x80000000;
 957                         tunnel_type |= addr_high;
 958                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
 959                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
 960                         IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
 961                                         input->formatted.tni_vni);
 962                 }
 963         }
 964
 965         /* record vlan (little-endian) and flex_bytes(big-endian) */
 966         fdirvlan = input->formatted.flex_bytes;
 967         fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
 968         fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
 969         IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
 970
 971         /* configure FDIRHASH register */
 972         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 973
 974         /*
 975          * flush all previous writes to make certain registers are
 976          * programmed prior to issuing the command
 977          */
 978         IXGBE_WRITE_FLUSH(hw);
 979
 980         /* configure FDIRCMD register */
 981         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
 982                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
 983         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
 984         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 985         fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
 986
 987         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
 988
 989         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
 990
 991         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
 992         if (err < 0)
 993                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
 994
 995         return err;
 996 }
 997
 998 /**
 999  * This function is based on ixgbe_atr_add_signature_filter_82599() in
1000  * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1001  * setting extra fields in the FDIRCMD register, and removes the code that was
1002  * verifying the flow_type field. According to the documentation, a flow type of
1003  * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1004  * work ok...
1005  *
1006  *  Adds a signature hash filter
1007  *  @hw: pointer to hardware structure
1008  *  @input: unique input dword
1009  *  @queue: queue index to direct traffic to
1010  *  @fdircmd: any extra flags to set in fdircmd register
1011  *  @fdirhash: pre-calculated hash value for the filter
1012  **/
1013 static int
1014 fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1015                 union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1016                 uint32_t fdirhash)
1017 {
1018         int err = 0;
1019
1020         PMD_INIT_FUNC_TRACE();
1021
1022         /* configure FDIRCMD register */
1023         fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1024                   IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1025         fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1026         fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1027
1028         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1029         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1030
1031         PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1032
1033         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1034         if (err < 0)
1035                 PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1036
1037         return err;
1038 }
1039
1040 /*
1041  * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1042  * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1043  * that it can be used for removing signature and perfect filters.
1044  */
1045 static int
1046 fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1047 {
1048         uint32_t fdircmd = 0;
1049         int err = 0;
1050
1051         IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1052
1053         /* flush hash to HW */
1054         IXGBE_WRITE_FLUSH(hw);
1055
1056         /* Query if filter is present */
1057         IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1058
1059         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1060         if (err < 0) {
1061                 PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1062                 return err;
1063         }
1064
1065         /* if filter exists in hardware then remove it */
1066         if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1067                 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1068                 IXGBE_WRITE_FLUSH(hw);
1069                 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1070                                 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1071         }
1072         err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1073         if (err < 0)
1074                 PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1075         return err;
1076
1077 }
1078
1079 static inline struct ixgbe_fdir_filter *
1080 ixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
1081                          union ixgbe_atr_input *key)
1082 {
1083         int ret;
1084
1085         ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
1086         if (ret < 0)
1087                 return NULL;
1088
1089         return fdir_info->hash_map[ret];
1090 }
1091
1092 static inline int
1093 ixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1094                          struct ixgbe_fdir_filter *fdir_filter)
1095 {
1096         int ret;
1097
1098         ret = rte_hash_add_key(fdir_info->hash_handle,
1099                                &fdir_filter->ixgbe_fdir);
1100
1101         if (ret < 0) {
1102                 PMD_DRV_LOG(ERR,
1103                             "Failed to insert fdir filter to hash table %d!",
1104                             ret);
1105                 return ret;
1106         }
1107
1108         fdir_info->hash_map[ret] = fdir_filter;
1109
1110         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
1111
1112         return 0;
1113 }
1114
1115 static inline int
1116 ixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
1117                          union ixgbe_atr_input *key)
1118 {
1119         int ret;
1120         struct ixgbe_fdir_filter *fdir_filter;
1121
1122         ret = rte_hash_del_key(fdir_info->hash_handle, key);
1123
1124         if (ret < 0) {
1125                 PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
1126                 return ret;
1127         }
1128
1129         fdir_filter = fdir_info->hash_map[ret];
1130         fdir_info->hash_map[ret] = NULL;
1131
1132         TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
1133         rte_free(fdir_filter);
1134
1135         return 0;
1136 }
1137
1138 /*
1139  * ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
1140  * @dev: pointer to the structure rte_eth_dev
1141  * @fdir_filter: fdir filter entry
1142  * @del: 1 - delete, 0 - add
1143  * @update: 1 - update
1144  */
1145 static int
1146 ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
1147                           const struct rte_eth_fdir_filter *fdir_filter,
1148                           bool del,
1149                           bool update)
1150 {
1151         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1152         uint32_t fdircmd_flags;
1153         uint32_t fdirhash;
1154         union ixgbe_atr_input input;
1155         uint8_t queue;
1156         bool is_perfect = FALSE;
1157         int err;
1158         struct ixgbe_hw_fdir_info *info =
1159                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1160         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1161         struct ixgbe_fdir_filter *node;
1162         bool add_node = FALSE;
1163
1164         if (fdir_mode == RTE_FDIR_MODE_NONE)
1165                 return -ENOTSUP;
1166
1167         /*
1168          * Sanity check for x550.
1169          * When adding a new filter with flow type set to IPv4-other,
1170          * the flow director mask should be configed before,
1171          * and the L4 protocol and ports are masked.
1172          */
1173         if ((!del) &&
1174             (hw->mac.type == ixgbe_mac_X550 ||
1175              hw->mac.type == ixgbe_mac_X550EM_x ||
1176              hw->mac.type == ixgbe_mac_X550EM_a) &&
1177             (fdir_filter->input.flow_type ==
1178              RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) &&
1179             (info->mask.src_port_mask != 0 ||
1180              info->mask.dst_port_mask != 0)) {
1181                 PMD_DRV_LOG(ERR, "By this device,"
1182                             " IPv4-other is not supported without"
1183                             " L4 protocol and ports masked!");
1184                 return -ENOTSUP;
1185         }
1186
1187         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1188             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1189                 is_perfect = TRUE;
1190
1191         memset(&input, 0, sizeof(input));
1192
1193         err = ixgbe_fdir_filter_to_atr_input(fdir_filter, &input,
1194                                              fdir_mode);
1195         if (err)
1196                 return err;
1197
1198         if (is_perfect) {
1199                 if (input.formatted.flow_type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
1200                         PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1201                                     " perfect mode!");
1202                         return -ENOTSUP;
1203                 }
1204                 fdirhash = atr_compute_perfect_hash_82599(&input,
1205                                                           dev->data->dev_conf.fdir_conf.pballoc);
1206                 fdirhash |= fdir_filter->soft_id <<
1207                         IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1208         } else
1209                 fdirhash = atr_compute_sig_hash_82599(&input,
1210                                                       dev->data->dev_conf.fdir_conf.pballoc);
1211
1212         if (del) {
1213                 err = ixgbe_remove_fdir_filter(info, &input);
1214                 if (err < 0)
1215                         return err;
1216
1217                 err = fdir_erase_filter_82599(hw, fdirhash);
1218                 if (err < 0)
1219                         PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1220                 else
1221                         PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1222                 return err;
1223         }
1224         /* add or update an fdir filter*/
1225         fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
1226         if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT) {
1227                 if (is_perfect) {
1228                         queue = dev->data->dev_conf.fdir_conf.drop_queue;
1229                         fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1230                 } else {
1231                         PMD_DRV_LOG(ERR, "Drop option is not supported in"
1232                                     " signature mode.");
1233                         return -EINVAL;
1234                 }
1235         } else if (fdir_filter->action.behavior == RTE_ETH_FDIR_ACCEPT &&
1236                    fdir_filter->action.rx_queue < IXGBE_MAX_RX_QUEUE_NUM)
1237                 queue = (uint8_t)fdir_filter->action.rx_queue;
1238         else
1239                 return -EINVAL;
1240
1241         node = ixgbe_fdir_filter_lookup(info, &input);
1242         if (node) {
1243                 if (update) {
1244                         node->fdirflags = fdircmd_flags;
1245                         node->fdirhash = fdirhash;
1246                         node->queue = queue;
1247                 } else {
1248                         PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
1249                         return -EINVAL;
1250                 }
1251         } else {
1252                 add_node = TRUE;
1253                 node = rte_zmalloc("ixgbe_fdir",
1254                                    sizeof(struct ixgbe_fdir_filter),
1255                                    0);
1256                 if (!node)
1257                         return -ENOMEM;
1258                 (void)rte_memcpy(&node->ixgbe_fdir,
1259                                  &input,
1260                                  sizeof(union ixgbe_atr_input));
1261                 node->fdirflags = fdircmd_flags;
1262                 node->fdirhash = fdirhash;
1263                 node->queue = queue;
1264
1265                 err = ixgbe_insert_fdir_filter(info, node);
1266                 if (err < 0) {
1267                         rte_free(node);
1268                         return err;
1269                 }
1270         }
1271
1272         if (is_perfect) {
1273                 err = fdir_write_perfect_filter_82599(hw, &input, queue,
1274                                                       fdircmd_flags, fdirhash,
1275                                                       fdir_mode);
1276         } else {
1277                 err = fdir_add_signature_filter_82599(hw, &input, queue,
1278                                                       fdircmd_flags, fdirhash);
1279         }
1280         if (err < 0) {
1281                 PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
1282
1283                 if (add_node)
1284                         (void)ixgbe_remove_fdir_filter(info, &input);
1285         } else {
1286                 PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
1287         }
1288
1289         return err;
1290 }
1291
1292 static int
1293 ixgbe_fdir_flush(struct rte_eth_dev *dev)
1294 {
1295         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1296         struct ixgbe_hw_fdir_info *info =
1297                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1298         int ret;
1299
1300         ret = ixgbe_reinit_fdir_tables_82599(hw);
1301         if (ret < 0) {
1302                 PMD_INIT_LOG(ERR, "Failed to re-initialize FD table.");
1303                 return ret;
1304         }
1305
1306         info->f_add = 0;
1307         info->f_remove = 0;
1308         info->add = 0;
1309         info->remove = 0;
1310
1311         return ret;
1312 }
1313
1314 #define FDIRENTRIES_NUM_SHIFT 10
1315 static void
1316 ixgbe_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info)
1317 {
1318         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1319         struct ixgbe_hw_fdir_info *info =
1320                         IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1321         uint32_t fdirctrl, max_num;
1322         uint8_t offset;
1323
1324         fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1325         offset = ((fdirctrl & IXGBE_FDIRCTRL_FLEX_MASK) >>
1326                         IXGBE_FDIRCTRL_FLEX_SHIFT) * sizeof(uint16_t);
1327
1328         fdir_info->mode = dev->data->dev_conf.fdir_conf.mode;
1329         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1330                         (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
1331         if (fdir_info->mode >= RTE_FDIR_MODE_PERFECT &&
1332             fdir_info->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1333                 fdir_info->guarant_spc = max_num;
1334         else if (fdir_info->mode == RTE_FDIR_MODE_SIGNATURE)
1335                 fdir_info->guarant_spc = max_num * 4;
1336
1337         fdir_info->mask.vlan_tci_mask = info->mask.vlan_tci_mask;
1338         fdir_info->mask.ipv4_mask.src_ip = info->mask.src_ipv4_mask;
1339         fdir_info->mask.ipv4_mask.dst_ip = info->mask.dst_ipv4_mask;
1340         IPV6_MASK_TO_ADDR(info->mask.src_ipv6_mask,
1341                         fdir_info->mask.ipv6_mask.src_ip);
1342         IPV6_MASK_TO_ADDR(info->mask.dst_ipv6_mask,
1343                         fdir_info->mask.ipv6_mask.dst_ip);
1344         fdir_info->mask.src_port_mask = info->mask.src_port_mask;
1345         fdir_info->mask.dst_port_mask = info->mask.dst_port_mask;
1346         fdir_info->mask.mac_addr_byte_mask = info->mask.mac_addr_byte_mask;
1347         fdir_info->mask.tunnel_id_mask = info->mask.tunnel_id_mask;
1348         fdir_info->mask.tunnel_type_mask = info->mask.tunnel_type_mask;
1349         fdir_info->max_flexpayload = IXGBE_FDIR_MAX_FLEX_LEN;
1350
1351         if (fdir_info->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN ||
1352             fdir_info->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
1353                 fdir_info->flow_types_mask[0] = 0;
1354         else
1355                 fdir_info->flow_types_mask[0] = IXGBE_FDIR_FLOW_TYPES;
1356
1357         fdir_info->flex_payload_unit = sizeof(uint16_t);
1358         fdir_info->max_flex_payload_segment_num = 1;
1359         fdir_info->flex_payload_limit = IXGBE_MAX_FLX_SOURCE_OFF;
1360         fdir_info->flex_conf.nb_payloads = 1;
1361         fdir_info->flex_conf.flex_set[0].type = RTE_ETH_RAW_PAYLOAD;
1362         fdir_info->flex_conf.flex_set[0].src_offset[0] = offset;
1363         fdir_info->flex_conf.flex_set[0].src_offset[1] = offset + 1;
1364         fdir_info->flex_conf.nb_flexmasks = 1;
1365         fdir_info->flex_conf.flex_mask[0].flow_type = RTE_ETH_FLOW_UNKNOWN;
1366         fdir_info->flex_conf.flex_mask[0].mask[0] =
1367                         (uint8_t)(info->mask.flex_bytes_mask & 0x00FF);
1368         fdir_info->flex_conf.flex_mask[0].mask[1] =
1369                         (uint8_t)((info->mask.flex_bytes_mask & 0xFF00) >> 8);
1370 }
1371
1372 static void
1373 ixgbe_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *fdir_stats)
1374 {
1375         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1376         struct ixgbe_hw_fdir_info *info =
1377                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1378         uint32_t reg, max_num;
1379         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1380
1381         /* Get the information from registers */
1382         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFREE);
1383         info->collision = (uint16_t)((reg & IXGBE_FDIRFREE_COLL_MASK) >>
1384                                      IXGBE_FDIRFREE_COLL_SHIFT);
1385         info->free = (uint16_t)((reg & IXGBE_FDIRFREE_FREE_MASK) >>
1386                                 IXGBE_FDIRFREE_FREE_SHIFT);
1387
1388         reg = IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1389         info->maxhash = (uint16_t)((reg & IXGBE_FDIRLEN_MAXHASH_MASK) >>
1390                                    IXGBE_FDIRLEN_MAXHASH_SHIFT);
1391         info->maxlen  = (uint8_t)((reg & IXGBE_FDIRLEN_MAXLEN_MASK) >>
1392                                   IXGBE_FDIRLEN_MAXLEN_SHIFT);
1393
1394         reg = IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1395         info->remove += (reg & IXGBE_FDIRUSTAT_REMOVE_MASK) >>
1396                 IXGBE_FDIRUSTAT_REMOVE_SHIFT;
1397         info->add += (reg & IXGBE_FDIRUSTAT_ADD_MASK) >>
1398                 IXGBE_FDIRUSTAT_ADD_SHIFT;
1399
1400         reg = IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT) & 0xFFFF;
1401         info->f_remove += (reg & IXGBE_FDIRFSTAT_FREMOVE_MASK) >>
1402                 IXGBE_FDIRFSTAT_FREMOVE_SHIFT;
1403         info->f_add += (reg & IXGBE_FDIRFSTAT_FADD_MASK) >>
1404                 IXGBE_FDIRFSTAT_FADD_SHIFT;
1405
1406         /*  Copy the new information in the fdir parameter */
1407         fdir_stats->collision = info->collision;
1408         fdir_stats->free = info->free;
1409         fdir_stats->maxhash = info->maxhash;
1410         fdir_stats->maxlen = info->maxlen;
1411         fdir_stats->remove = info->remove;
1412         fdir_stats->add = info->add;
1413         fdir_stats->f_remove = info->f_remove;
1414         fdir_stats->f_add = info->f_add;
1415
1416         reg = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1417         max_num = (1 << (FDIRENTRIES_NUM_SHIFT +
1418                          (reg & FDIRCTRL_PBALLOC_MASK)));
1419         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1420             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1421                 fdir_stats->guarant_cnt = max_num - fdir_stats->free;
1422         else if (fdir_mode == RTE_FDIR_MODE_SIGNATURE)
1423                 fdir_stats->guarant_cnt = max_num * 4 - fdir_stats->free;
1424
1425 }
1426
1427 /*
1428  * ixgbe_fdir_ctrl_func - deal with all operations on flow director.
1429  * @dev: pointer to the structure rte_eth_dev
1430  * @filter_op:operation will be taken
1431  * @arg: a pointer to specific structure corresponding to the filter_op
1432  */
1433 int
1434 ixgbe_fdir_ctrl_func(struct rte_eth_dev *dev,
1435                         enum rte_filter_op filter_op, void *arg)
1436 {
1437         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1438         int ret = 0;
1439
1440         if (hw->mac.type != ixgbe_mac_82599EB &&
1441                 hw->mac.type != ixgbe_mac_X540 &&
1442                 hw->mac.type != ixgbe_mac_X550 &&
1443                 hw->mac.type != ixgbe_mac_X550EM_x &&
1444                 hw->mac.type != ixgbe_mac_X550EM_a)
1445                 return -ENOTSUP;
1446
1447         if (filter_op == RTE_ETH_FILTER_NOP)
1448                 return 0;
1449
1450         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1451                 return -EINVAL;
1452
1453         switch (filter_op) {
1454         case RTE_ETH_FILTER_ADD:
1455                 ret = ixgbe_add_del_fdir_filter(dev,
1456                         (struct rte_eth_fdir_filter *)arg, FALSE, FALSE);
1457                 break;
1458         case RTE_ETH_FILTER_UPDATE:
1459                 ret = ixgbe_add_del_fdir_filter(dev,
1460                         (struct rte_eth_fdir_filter *)arg, FALSE, TRUE);
1461                 break;
1462         case RTE_ETH_FILTER_DELETE:
1463                 ret = ixgbe_add_del_fdir_filter(dev,
1464                         (struct rte_eth_fdir_filter *)arg, TRUE, FALSE);
1465                 break;
1466         case RTE_ETH_FILTER_FLUSH:
1467                 ret = ixgbe_fdir_flush(dev);
1468                 break;
1469         case RTE_ETH_FILTER_INFO:
1470                 ixgbe_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1471                 break;
1472         case RTE_ETH_FILTER_STATS:
1473                 ixgbe_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1474                 break;
1475         default:
1476                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
1477                 ret = -EINVAL;
1478                 break;
1479         }
1480         return ret;
1481 }
1482
1483 /* restore flow director filter */
1484 void
1485 ixgbe_fdir_filter_restore(struct rte_eth_dev *dev)
1486 {
1487         struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488         struct ixgbe_hw_fdir_info *fdir_info =
1489                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1490         struct ixgbe_fdir_filter *node;
1491         bool is_perfect = FALSE;
1492         enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
1493
1494         if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1495             fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1496                 is_perfect = TRUE;
1497
1498         if (is_perfect) {
1499                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1500                         (void)fdir_write_perfect_filter_82599(hw,
1501                                                               &node->ixgbe_fdir,
1502                                                               node->queue,
1503                                                               node->fdirflags,
1504                                                               node->fdirhash,
1505                                                               fdir_mode);
1506                 }
1507         } else {
1508                 TAILQ_FOREACH(node, &fdir_info->fdir_list, entries) {
1509                         (void)fdir_add_signature_filter_82599(hw,
1510                                                               &node->ixgbe_fdir,
1511                                                               node->queue,
1512                                                               node->fdirflags,
1513                                                               node->fdirhash);
1514                 }
1515         }
1516 }
1517
1518 /* remove all the flow director filters */
1519 int
1520 ixgbe_clear_all_fdir_filter(struct rte_eth_dev *dev)
1521 {
1522         struct ixgbe_hw_fdir_info *fdir_info =
1523                 IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1524         struct ixgbe_fdir_filter *fdir_filter;
1525         int ret = 0;
1526
1527         /* flush flow director */
1528         rte_hash_reset(fdir_info->hash_handle);
1529         memset(fdir_info->hash_map, 0,
1530                sizeof(struct ixgbe_fdir_filter *) * IXGBE_MAX_FDIR_FILTER_NUM);
1531         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
1532                 TAILQ_REMOVE(&fdir_info->fdir_list,
1533                              fdir_filter,
1534                              entries);
1535                 rte_free(fdir_filter);
1536         }
1537         ret = ixgbe_fdir_flush(dev);
1538
1539         return ret;
1540 }