4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5 * Copyright 2014 6WIND S.A.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * * Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
18 * * Neither the name of Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #include <sys/queue.h>
46 #include <rte_byteorder.h>
47 #include <rte_common.h>
48 #include <rte_cycles.h>
50 #include <rte_debug.h>
51 #include <rte_interrupts.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_launch.h>
57 #include <rte_per_lcore.h>
58 #include <rte_lcore.h>
59 #include <rte_atomic.h>
60 #include <rte_branch_prediction.h>
62 #include <rte_mempool.h>
63 #include <rte_malloc.h>
65 #include <rte_ether.h>
66 #include <rte_ethdev.h>
67 #include <rte_prefetch.h>
71 #include <rte_string_fns.h>
72 #include <rte_errno.h>
75 #include "ixgbe_logs.h"
76 #include "base/ixgbe_api.h"
77 #include "base/ixgbe_vf.h"
78 #include "ixgbe_ethdev.h"
79 #include "base/ixgbe_dcb.h"
80 #include "base/ixgbe_common.h"
81 #include "ixgbe_rxtx.h"
83 /* Bit Mask to indicate what bits required for building TX context */
84 #define IXGBE_TX_OFFLOAD_MASK ( \
90 static inline struct rte_mbuf *
91 rte_rxmbuf_alloc(struct rte_mempool *mp)
95 m = __rte_mbuf_raw_alloc(mp);
96 __rte_mbuf_sanity_check_raw(m, 0);
102 #define RTE_PMD_USE_PREFETCH
105 #ifdef RTE_PMD_USE_PREFETCH
107 * Prefetch a cache line into all cache levels.
109 #define rte_ixgbe_prefetch(p) rte_prefetch0(p)
111 #define rte_ixgbe_prefetch(p) do {} while(0)
114 /*********************************************************************
118 **********************************************************************/
121 * Check for descriptors with their DD bit set and free mbufs.
122 * Return the total number of buffers freed.
124 static inline int __attribute__((always_inline))
125 ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
127 struct ixgbe_tx_entry *txep;
131 /* check DD bit on threshold descriptor */
132 status = txq->tx_ring[txq->tx_next_dd].wb.status;
133 if (! (status & IXGBE_ADVTXD_STAT_DD))
137 * first buffer to free from S/W ring is at index
138 * tx_next_dd - (tx_rs_thresh-1)
140 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
142 /* free buffers one at a time */
143 if ((txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) != 0) {
144 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
145 txep->mbuf->next = NULL;
146 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
150 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
151 rte_pktmbuf_free_seg(txep->mbuf);
156 /* buffers were freed, update counters */
157 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
158 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
159 if (txq->tx_next_dd >= txq->nb_tx_desc)
160 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
162 return txq->tx_rs_thresh;
165 /* Populate 4 descriptors with data from 4 mbufs */
167 tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
169 uint64_t buf_dma_addr;
173 for (i = 0; i < 4; ++i, ++txdp, ++pkts) {
174 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
175 pkt_len = (*pkts)->data_len;
177 /* write data to descriptor */
178 txdp->read.buffer_addr = buf_dma_addr;
179 txdp->read.cmd_type_len =
180 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
181 txdp->read.olinfo_status =
182 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
183 rte_prefetch0(&(*pkts)->pool);
187 /* Populate 1 descriptor with data from 1 mbuf */
189 tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
191 uint64_t buf_dma_addr;
194 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
195 pkt_len = (*pkts)->data_len;
197 /* write data to descriptor */
198 txdp->read.buffer_addr = buf_dma_addr;
199 txdp->read.cmd_type_len =
200 ((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
201 txdp->read.olinfo_status =
202 (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
203 rte_prefetch0(&(*pkts)->pool);
207 * Fill H/W descriptor ring with mbuf data.
208 * Copy mbuf pointers to the S/W ring.
211 ixgbe_tx_fill_hw_ring(struct ixgbe_tx_queue *txq, struct rte_mbuf **pkts,
214 volatile union ixgbe_adv_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
215 struct ixgbe_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
216 const int N_PER_LOOP = 4;
217 const int N_PER_LOOP_MASK = N_PER_LOOP-1;
218 int mainpart, leftover;
222 * Process most of the packets in chunks of N pkts. Any
223 * leftover packets will get processed one at a time.
225 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
226 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
227 for (i = 0; i < mainpart; i += N_PER_LOOP) {
228 /* Copy N mbuf pointers to the S/W ring */
229 for (j = 0; j < N_PER_LOOP; ++j) {
230 (txep + i + j)->mbuf = *(pkts + i + j);
232 tx4(txdp + i, pkts + i);
235 if (unlikely(leftover > 0)) {
236 for (i = 0; i < leftover; ++i) {
237 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
238 tx1(txdp + mainpart + i, pkts + mainpart + i);
243 static inline uint16_t
244 tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
247 struct ixgbe_tx_queue *txq = (struct ixgbe_tx_queue *)tx_queue;
248 volatile union ixgbe_adv_tx_desc *tx_r = txq->tx_ring;
252 * Begin scanning the H/W ring for done descriptors when the
253 * number of available descriptors drops below tx_free_thresh. For
254 * each done descriptor, free the associated buffer.
256 if (txq->nb_tx_free < txq->tx_free_thresh)
257 ixgbe_tx_free_bufs(txq);
259 /* Only use descriptors that are available */
260 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
261 if (unlikely(nb_pkts == 0))
264 /* Use exactly nb_pkts descriptors */
265 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
268 * At this point, we know there are enough descriptors in the
269 * ring to transmit all the packets. This assumes that each
270 * mbuf contains a single segment, and that no new offloads
271 * are expected, which would require a new context descriptor.
275 * See if we're going to wrap-around. If so, handle the top
276 * of the descriptor ring first, then do the bottom. If not,
277 * the processing looks just like the "bottom" part anyway...
279 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
280 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
281 ixgbe_tx_fill_hw_ring(txq, tx_pkts, n);
284 * We know that the last descriptor in the ring will need to
285 * have its RS bit set because tx_rs_thresh has to be
286 * a divisor of the ring size
288 tx_r[txq->tx_next_rs].read.cmd_type_len |=
289 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
295 /* Fill H/W descriptor ring with mbuf data */
296 ixgbe_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
297 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
300 * Determine if RS bit should be set
301 * This is what we actually want:
302 * if ((txq->tx_tail - 1) >= txq->tx_next_rs)
303 * but instead of subtracting 1 and doing >=, we can just do
304 * greater than without subtracting.
306 if (txq->tx_tail > txq->tx_next_rs) {
307 tx_r[txq->tx_next_rs].read.cmd_type_len |=
308 rte_cpu_to_le_32(IXGBE_ADVTXD_DCMD_RS);
309 txq->tx_next_rs = (uint16_t)(txq->tx_next_rs +
311 if (txq->tx_next_rs >= txq->nb_tx_desc)
312 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
316 * Check for wrap-around. This would only happen if we used
317 * up to the last descriptor in the ring, no more, no less.
319 if (txq->tx_tail >= txq->nb_tx_desc)
322 /* update tail pointer */
324 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
330 ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
335 /* Try to transmit at least chunks of TX_MAX_BURST pkts */
336 if (likely(nb_pkts <= RTE_PMD_IXGBE_TX_MAX_BURST))
337 return tx_xmit_pkts(tx_queue, tx_pkts, nb_pkts);
339 /* transmit more than the max burst, in chunks of TX_MAX_BURST */
343 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_TX_MAX_BURST);
344 ret = tx_xmit_pkts(tx_queue, &(tx_pkts[nb_tx]), n);
345 nb_tx = (uint16_t)(nb_tx + ret);
346 nb_pkts = (uint16_t)(nb_pkts - ret);
355 ixgbe_set_xmit_ctx(struct ixgbe_tx_queue *txq,
356 volatile struct ixgbe_adv_tx_context_desc *ctx_txd,
357 uint64_t ol_flags, union ixgbe_tx_offload tx_offload)
359 uint32_t type_tucmd_mlhl;
360 uint32_t mss_l4len_idx = 0;
362 uint32_t vlan_macip_lens;
363 union ixgbe_tx_offload tx_offload_mask;
365 ctx_idx = txq->ctx_curr;
366 tx_offload_mask.data = 0;
369 /* Specify which HW CTX to upload. */
370 mss_l4len_idx |= (ctx_idx << IXGBE_ADVTXD_IDX_SHIFT);
372 if (ol_flags & PKT_TX_VLAN_PKT) {
373 tx_offload_mask.vlan_tci |= ~0;
376 /* check if TCP segmentation required for this packet */
377 if (ol_flags & PKT_TX_TCP_SEG) {
378 /* implies IP cksum in IPv4 */
379 if (ol_flags & PKT_TX_IP_CKSUM)
380 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4 |
381 IXGBE_ADVTXD_TUCMD_L4T_TCP |
382 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
384 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV6 |
385 IXGBE_ADVTXD_TUCMD_L4T_TCP |
386 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
388 tx_offload_mask.l2_len |= ~0;
389 tx_offload_mask.l3_len |= ~0;
390 tx_offload_mask.l4_len |= ~0;
391 tx_offload_mask.tso_segsz |= ~0;
392 mss_l4len_idx |= tx_offload.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT;
393 mss_l4len_idx |= tx_offload.l4_len << IXGBE_ADVTXD_L4LEN_SHIFT;
394 } else { /* no TSO, check if hardware checksum is needed */
395 if (ol_flags & PKT_TX_IP_CKSUM) {
396 type_tucmd_mlhl = IXGBE_ADVTXD_TUCMD_IPV4;
397 tx_offload_mask.l2_len |= ~0;
398 tx_offload_mask.l3_len |= ~0;
401 switch (ol_flags & PKT_TX_L4_MASK) {
402 case PKT_TX_UDP_CKSUM:
403 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_UDP |
404 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
405 mss_l4len_idx |= sizeof(struct udp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
406 tx_offload_mask.l2_len |= ~0;
407 tx_offload_mask.l3_len |= ~0;
409 case PKT_TX_TCP_CKSUM:
410 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP |
411 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
412 mss_l4len_idx |= sizeof(struct tcp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
413 tx_offload_mask.l2_len |= ~0;
414 tx_offload_mask.l3_len |= ~0;
415 tx_offload_mask.l4_len |= ~0;
417 case PKT_TX_SCTP_CKSUM:
418 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_SCTP |
419 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
420 mss_l4len_idx |= sizeof(struct sctp_hdr) << IXGBE_ADVTXD_L4LEN_SHIFT;
421 tx_offload_mask.l2_len |= ~0;
422 tx_offload_mask.l3_len |= ~0;
425 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_RSV |
426 IXGBE_ADVTXD_DTYP_CTXT | IXGBE_ADVTXD_DCMD_DEXT;
431 txq->ctx_cache[ctx_idx].flags = ol_flags;
432 txq->ctx_cache[ctx_idx].tx_offload.data =
433 tx_offload_mask.data & tx_offload.data;
434 txq->ctx_cache[ctx_idx].tx_offload_mask = tx_offload_mask;
436 ctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);
437 vlan_macip_lens = tx_offload.l3_len;
438 vlan_macip_lens |= (tx_offload.l2_len << IXGBE_ADVTXD_MACLEN_SHIFT);
439 vlan_macip_lens |= ((uint32_t)tx_offload.vlan_tci << IXGBE_ADVTXD_VLAN_SHIFT);
440 ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);
441 ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);
442 ctx_txd->seqnum_seed = 0;
446 * Check which hardware context can be used. Use the existing match
447 * or create a new context descriptor.
449 static inline uint32_t
450 what_advctx_update(struct ixgbe_tx_queue *txq, uint64_t flags,
451 union ixgbe_tx_offload tx_offload)
453 /* If match with the current used context */
454 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
455 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
456 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
457 return txq->ctx_curr;
460 /* What if match with the next context */
462 if (likely((txq->ctx_cache[txq->ctx_curr].flags == flags) &&
463 (txq->ctx_cache[txq->ctx_curr].tx_offload.data ==
464 (txq->ctx_cache[txq->ctx_curr].tx_offload_mask.data & tx_offload.data)))) {
465 return txq->ctx_curr;
468 /* Mismatch, use the previous context */
469 return (IXGBE_CTX_NUM);
472 static inline uint32_t
473 tx_desc_cksum_flags_to_olinfo(uint64_t ol_flags)
476 if ((ol_flags & PKT_TX_L4_MASK) != PKT_TX_L4_NO_CKSUM)
477 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
478 if (ol_flags & PKT_TX_IP_CKSUM)
479 tmp |= IXGBE_ADVTXD_POPTS_IXSM;
480 if (ol_flags & PKT_TX_TCP_SEG)
481 tmp |= IXGBE_ADVTXD_POPTS_TXSM;
485 static inline uint32_t
486 tx_desc_ol_flags_to_cmdtype(uint64_t ol_flags)
488 uint32_t cmdtype = 0;
489 if (ol_flags & PKT_TX_VLAN_PKT)
490 cmdtype |= IXGBE_ADVTXD_DCMD_VLE;
491 if (ol_flags & PKT_TX_TCP_SEG)
492 cmdtype |= IXGBE_ADVTXD_DCMD_TSE;
496 /* Default RS bit threshold values */
497 #ifndef DEFAULT_TX_RS_THRESH
498 #define DEFAULT_TX_RS_THRESH 32
500 #ifndef DEFAULT_TX_FREE_THRESH
501 #define DEFAULT_TX_FREE_THRESH 32
504 /* Reset transmit descriptors after they have been used */
506 ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
508 struct ixgbe_tx_entry *sw_ring = txq->sw_ring;
509 volatile union ixgbe_adv_tx_desc *txr = txq->tx_ring;
510 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
511 uint16_t nb_tx_desc = txq->nb_tx_desc;
512 uint16_t desc_to_clean_to;
513 uint16_t nb_tx_to_clean;
515 /* Determine the last descriptor needing to be cleaned */
516 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
517 if (desc_to_clean_to >= nb_tx_desc)
518 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
520 /* Check to make sure the last descriptor to clean is done */
521 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
522 if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
524 PMD_TX_FREE_LOG(DEBUG,
525 "TX descriptor %4u is not done"
526 "(port=%d queue=%d)",
528 txq->port_id, txq->queue_id);
529 /* Failed to clean any descriptors, better luck next time */
533 /* Figure out how many descriptors will be cleaned */
534 if (last_desc_cleaned > desc_to_clean_to)
535 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
538 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
541 PMD_TX_FREE_LOG(DEBUG,
542 "Cleaning %4u TX descriptors: %4u to %4u "
543 "(port=%d queue=%d)",
544 nb_tx_to_clean, last_desc_cleaned, desc_to_clean_to,
545 txq->port_id, txq->queue_id);
548 * The last descriptor to clean is done, so that means all the
549 * descriptors from the last descriptor that was cleaned
550 * up to the last descriptor with the RS bit set
551 * are done. Only reset the threshold descriptor.
553 txr[desc_to_clean_to].wb.status = 0;
555 /* Update the txq to reflect the last descriptor that was cleaned */
556 txq->last_desc_cleaned = desc_to_clean_to;
557 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
564 ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
567 struct ixgbe_tx_queue *txq;
568 struct ixgbe_tx_entry *sw_ring;
569 struct ixgbe_tx_entry *txe, *txn;
570 volatile union ixgbe_adv_tx_desc *txr;
571 volatile union ixgbe_adv_tx_desc *txd;
572 struct rte_mbuf *tx_pkt;
573 struct rte_mbuf *m_seg;
574 uint64_t buf_dma_addr;
575 uint32_t olinfo_status;
576 uint32_t cmd_type_len;
587 union ixgbe_tx_offload tx_offload = {0};
590 sw_ring = txq->sw_ring;
592 tx_id = txq->tx_tail;
593 txe = &sw_ring[tx_id];
595 /* Determine if the descriptor ring needs to be cleaned. */
596 if (txq->nb_tx_free < txq->tx_free_thresh)
597 ixgbe_xmit_cleanup(txq);
599 rte_prefetch0(&txe->mbuf->pool);
602 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
605 pkt_len = tx_pkt->pkt_len;
608 * Determine how many (if any) context descriptors
609 * are needed for offload functionality.
611 ol_flags = tx_pkt->ol_flags;
613 /* If hardware offload required */
614 tx_ol_req = ol_flags & IXGBE_TX_OFFLOAD_MASK;
616 tx_offload.l2_len = tx_pkt->l2_len;
617 tx_offload.l3_len = tx_pkt->l3_len;
618 tx_offload.l4_len = tx_pkt->l4_len;
619 tx_offload.vlan_tci = tx_pkt->vlan_tci;
620 tx_offload.tso_segsz = tx_pkt->tso_segsz;
622 /* If new context need be built or reuse the exist ctx. */
623 ctx = what_advctx_update(txq, tx_ol_req,
625 /* Only allocate context descriptor if required*/
626 new_ctx = (ctx == IXGBE_CTX_NUM);
631 * Keep track of how many descriptors are used this loop
632 * This will always be the number of segments + the number of
633 * Context descriptors required to transmit the packet
635 nb_used = (uint16_t)(tx_pkt->nb_segs + new_ctx);
638 * The number of descriptors that must be allocated for a
639 * packet is the number of segments of that packet, plus 1
640 * Context Descriptor for the hardware offload, if any.
641 * Determine the last TX descriptor to allocate in the TX ring
642 * for the packet, starting from the current position (tx_id)
645 tx_last = (uint16_t) (tx_id + nb_used - 1);
648 if (tx_last >= txq->nb_tx_desc)
649 tx_last = (uint16_t) (tx_last - txq->nb_tx_desc);
651 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u pktlen=%u"
652 " tx_first=%u tx_last=%u",
653 (unsigned) txq->port_id,
654 (unsigned) txq->queue_id,
660 * Make sure there are enough TX descriptors available to
661 * transmit the entire packet.
662 * nb_used better be less than or equal to txq->tx_rs_thresh
664 if (nb_used > txq->nb_tx_free) {
665 PMD_TX_FREE_LOG(DEBUG,
666 "Not enough free TX descriptors "
667 "nb_used=%4u nb_free=%4u "
668 "(port=%d queue=%d)",
669 nb_used, txq->nb_tx_free,
670 txq->port_id, txq->queue_id);
672 if (ixgbe_xmit_cleanup(txq) != 0) {
673 /* Could not clean any descriptors */
679 /* nb_used better be <= txq->tx_rs_thresh */
680 if (unlikely(nb_used > txq->tx_rs_thresh)) {
681 PMD_TX_FREE_LOG(DEBUG,
682 "The number of descriptors needed to "
683 "transmit the packet exceeds the "
684 "RS bit threshold. This will impact "
686 "nb_used=%4u nb_free=%4u "
688 "(port=%d queue=%d)",
689 nb_used, txq->nb_tx_free,
691 txq->port_id, txq->queue_id);
693 * Loop here until there are enough TX
694 * descriptors or until the ring cannot be
697 while (nb_used > txq->nb_tx_free) {
698 if (ixgbe_xmit_cleanup(txq) != 0) {
700 * Could not clean any
712 * By now there are enough free TX descriptors to transmit
717 * Set common flags of all TX Data Descriptors.
719 * The following bits must be set in all Data Descriptors:
720 * - IXGBE_ADVTXD_DTYP_DATA
721 * - IXGBE_ADVTXD_DCMD_DEXT
723 * The following bits must be set in the first Data Descriptor
724 * and are ignored in the other ones:
725 * - IXGBE_ADVTXD_DCMD_IFCS
726 * - IXGBE_ADVTXD_MAC_1588
727 * - IXGBE_ADVTXD_DCMD_VLE
729 * The following bits must only be set in the last Data
731 * - IXGBE_TXD_CMD_EOP
733 * The following bits can be set in any Data Descriptor, but
734 * are only set in the last Data Descriptor:
737 cmd_type_len = IXGBE_ADVTXD_DTYP_DATA |
738 IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
740 #ifdef RTE_LIBRTE_IEEE1588
741 if (ol_flags & PKT_TX_IEEE1588_TMST)
742 cmd_type_len |= IXGBE_ADVTXD_MAC_1588;
748 if (ol_flags & PKT_TX_TCP_SEG) {
749 /* when TSO is on, paylen in descriptor is the
750 * not the packet len but the tcp payload len */
751 pkt_len -= (tx_offload.l2_len +
752 tx_offload.l3_len + tx_offload.l4_len);
756 * Setup the TX Advanced Context Descriptor if required
759 volatile struct ixgbe_adv_tx_context_desc *
762 ctx_txd = (volatile struct
763 ixgbe_adv_tx_context_desc *)
766 txn = &sw_ring[txe->next_id];
767 rte_prefetch0(&txn->mbuf->pool);
769 if (txe->mbuf != NULL) {
770 rte_pktmbuf_free_seg(txe->mbuf);
774 ixgbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req,
777 txe->last_id = tx_last;
778 tx_id = txe->next_id;
783 * Setup the TX Advanced Data Descriptor,
784 * This path will go through
785 * whatever new/reuse the context descriptor
787 cmd_type_len |= tx_desc_ol_flags_to_cmdtype(ol_flags);
788 olinfo_status |= tx_desc_cksum_flags_to_olinfo(ol_flags);
789 olinfo_status |= ctx << IXGBE_ADVTXD_IDX_SHIFT;
792 olinfo_status |= (pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
797 txn = &sw_ring[txe->next_id];
798 rte_prefetch0(&txn->mbuf->pool);
800 if (txe->mbuf != NULL)
801 rte_pktmbuf_free_seg(txe->mbuf);
805 * Set up Transmit Data Descriptor.
807 slen = m_seg->data_len;
808 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
809 txd->read.buffer_addr =
810 rte_cpu_to_le_64(buf_dma_addr);
811 txd->read.cmd_type_len =
812 rte_cpu_to_le_32(cmd_type_len | slen);
813 txd->read.olinfo_status =
814 rte_cpu_to_le_32(olinfo_status);
815 txe->last_id = tx_last;
816 tx_id = txe->next_id;
819 } while (m_seg != NULL);
822 * The last packet data descriptor needs End Of Packet (EOP)
824 cmd_type_len |= IXGBE_TXD_CMD_EOP;
825 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
826 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
828 /* Set RS bit only on threshold packets' last descriptor */
829 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
830 PMD_TX_FREE_LOG(DEBUG,
831 "Setting RS bit on TXD id="
832 "%4u (port=%d queue=%d)",
833 tx_last, txq->port_id, txq->queue_id);
835 cmd_type_len |= IXGBE_TXD_CMD_RS;
837 /* Update txq RS bit counters */
840 txd->read.cmd_type_len |= rte_cpu_to_le_32(cmd_type_len);
846 * Set the Transmit Descriptor Tail (TDT)
848 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
849 (unsigned) txq->port_id, (unsigned) txq->queue_id,
850 (unsigned) tx_id, (unsigned) nb_tx);
851 IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, tx_id);
852 txq->tx_tail = tx_id;
857 /*********************************************************************
861 **********************************************************************/
863 #define IXGBE_PACKET_TYPE_IPV4 0X01
864 #define IXGBE_PACKET_TYPE_IPV4_TCP 0X11
865 #define IXGBE_PACKET_TYPE_IPV4_UDP 0X21
866 #define IXGBE_PACKET_TYPE_IPV4_SCTP 0X41
867 #define IXGBE_PACKET_TYPE_IPV4_EXT 0X03
868 #define IXGBE_PACKET_TYPE_IPV4_EXT_SCTP 0X43
869 #define IXGBE_PACKET_TYPE_IPV6 0X04
870 #define IXGBE_PACKET_TYPE_IPV6_TCP 0X14
871 #define IXGBE_PACKET_TYPE_IPV6_UDP 0X24
872 #define IXGBE_PACKET_TYPE_IPV6_EXT 0X0C
873 #define IXGBE_PACKET_TYPE_IPV6_EXT_TCP 0X1C
874 #define IXGBE_PACKET_TYPE_IPV6_EXT_UDP 0X2C
875 #define IXGBE_PACKET_TYPE_IPV4_IPV6 0X05
876 #define IXGBE_PACKET_TYPE_IPV4_IPV6_TCP 0X15
877 #define IXGBE_PACKET_TYPE_IPV4_IPV6_UDP 0X25
878 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
879 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
880 #define IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
881 #define IXGBE_PACKET_TYPE_MAX 0X80
882 #define IXGBE_PACKET_TYPE_MASK 0X7F
883 #define IXGBE_PACKET_TYPE_SHIFT 0X04
884 static inline uint32_t
885 ixgbe_rxd_pkt_info_to_pkt_type(uint16_t pkt_info)
887 static const uint32_t
888 ptype_table[IXGBE_PACKET_TYPE_MAX] __rte_cache_aligned = {
889 [IXGBE_PACKET_TYPE_IPV4] = RTE_PTYPE_L2_ETHER |
891 [IXGBE_PACKET_TYPE_IPV4_EXT] = RTE_PTYPE_L2_ETHER |
892 RTE_PTYPE_L3_IPV4_EXT,
893 [IXGBE_PACKET_TYPE_IPV6] = RTE_PTYPE_L2_ETHER |
895 [IXGBE_PACKET_TYPE_IPV4_IPV6] = RTE_PTYPE_L2_ETHER |
896 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
897 RTE_PTYPE_INNER_L3_IPV6,
898 [IXGBE_PACKET_TYPE_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
899 RTE_PTYPE_L3_IPV6_EXT,
900 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT] = RTE_PTYPE_L2_ETHER |
901 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
902 RTE_PTYPE_INNER_L3_IPV6_EXT,
903 [IXGBE_PACKET_TYPE_IPV4_TCP] = RTE_PTYPE_L2_ETHER |
904 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
905 [IXGBE_PACKET_TYPE_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
906 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
907 [IXGBE_PACKET_TYPE_IPV4_IPV6_TCP] = RTE_PTYPE_L2_ETHER |
908 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
909 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_TCP,
910 [IXGBE_PACKET_TYPE_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
911 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_TCP,
912 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_TCP] = RTE_PTYPE_L2_ETHER |
913 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
914 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_TCP,
915 [IXGBE_PACKET_TYPE_IPV4_UDP] = RTE_PTYPE_L2_ETHER |
916 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
917 [IXGBE_PACKET_TYPE_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
918 RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
919 [IXGBE_PACKET_TYPE_IPV4_IPV6_UDP] = RTE_PTYPE_L2_ETHER |
920 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
921 RTE_PTYPE_INNER_L3_IPV6 | RTE_PTYPE_INNER_L4_UDP,
922 [IXGBE_PACKET_TYPE_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
923 RTE_PTYPE_L3_IPV6_EXT | RTE_PTYPE_L4_UDP,
924 [IXGBE_PACKET_TYPE_IPV4_IPV6_EXT_UDP] = RTE_PTYPE_L2_ETHER |
925 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_TUNNEL_IP |
926 RTE_PTYPE_INNER_L3_IPV6_EXT | RTE_PTYPE_INNER_L4_UDP,
927 [IXGBE_PACKET_TYPE_IPV4_SCTP] = RTE_PTYPE_L2_ETHER |
928 RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_SCTP,
929 [IXGBE_PACKET_TYPE_IPV4_EXT_SCTP] = RTE_PTYPE_L2_ETHER |
930 RTE_PTYPE_L3_IPV4_EXT | RTE_PTYPE_L4_SCTP,
932 if (unlikely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
933 return RTE_PTYPE_UNKNOWN;
935 pkt_info = (pkt_info >> IXGBE_PACKET_TYPE_SHIFT) &
936 IXGBE_PACKET_TYPE_MASK;
938 return ptype_table[pkt_info];
941 static inline uint64_t
942 ixgbe_rxd_pkt_info_to_pkt_flags(uint16_t pkt_info)
944 static uint64_t ip_rss_types_map[16] __rte_cache_aligned = {
945 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
946 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
947 PKT_RX_RSS_HASH, 0, 0, 0,
948 0, 0, 0, PKT_RX_FDIR,
950 #ifdef RTE_LIBRTE_IEEE1588
951 static uint64_t ip_pkt_etqf_map[8] = {
952 0, 0, 0, PKT_RX_IEEE1588_PTP,
956 if (likely(pkt_info & IXGBE_RXDADV_PKTTYPE_ETQF))
957 return ip_pkt_etqf_map[(pkt_info >> 4) & 0X07] |
958 ip_rss_types_map[pkt_info & 0XF];
960 return ip_rss_types_map[pkt_info & 0XF];
962 return ip_rss_types_map[pkt_info & 0XF];
965 #else /* RTE_NEXT_ABI */
966 static inline uint64_t
967 rx_desc_hlen_type_rss_to_pkt_flags(uint32_t hl_tp_rs)
971 static const uint64_t ip_pkt_types_map[16] = {
972 0, PKT_RX_IPV4_HDR, PKT_RX_IPV4_HDR_EXT, PKT_RX_IPV4_HDR_EXT,
973 PKT_RX_IPV6_HDR, 0, 0, 0,
974 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
975 PKT_RX_IPV6_HDR_EXT, 0, 0, 0,
978 static const uint64_t ip_rss_types_map[16] = {
979 0, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH, PKT_RX_RSS_HASH,
980 0, PKT_RX_RSS_HASH, 0, PKT_RX_RSS_HASH,
981 PKT_RX_RSS_HASH, 0, 0, 0,
982 0, 0, 0, PKT_RX_FDIR,
985 #ifdef RTE_LIBRTE_IEEE1588
986 static uint64_t ip_pkt_etqf_map[8] = {
987 0, 0, 0, PKT_RX_IEEE1588_PTP,
991 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ?
992 ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07] :
993 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
995 pkt_flags = (hl_tp_rs & IXGBE_RXDADV_PKTTYPE_ETQF) ? 0 :
996 ip_pkt_types_map[(hl_tp_rs >> 4) & 0x0F];
999 return pkt_flags | ip_rss_types_map[hl_tp_rs & 0xF];
1001 #endif /* RTE_NEXT_ABI */
1003 static inline uint64_t
1004 rx_desc_status_to_pkt_flags(uint32_t rx_status)
1009 * Check if VLAN present only.
1010 * Do not check whether L3/L4 rx checksum done by NIC or not,
1011 * That can be found from rte_eth_rxmode.hw_ip_checksum flag
1013 pkt_flags = (rx_status & IXGBE_RXD_STAT_VP) ? PKT_RX_VLAN_PKT : 0;
1015 #ifdef RTE_LIBRTE_IEEE1588
1016 if (rx_status & IXGBE_RXD_STAT_TMST)
1017 pkt_flags = pkt_flags | PKT_RX_IEEE1588_TMST;
1022 static inline uint64_t
1023 rx_desc_error_to_pkt_flags(uint32_t rx_status)
1026 * Bit 31: IPE, IPv4 checksum error
1027 * Bit 30: L4I, L4I integrity error
1029 static uint64_t error_to_pkt_flags_map[4] = {
1030 0, PKT_RX_L4_CKSUM_BAD, PKT_RX_IP_CKSUM_BAD,
1031 PKT_RX_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD
1033 return error_to_pkt_flags_map[(rx_status >>
1034 IXGBE_RXDADV_ERR_CKSUM_BIT) & IXGBE_RXDADV_ERR_CKSUM_MSK];
1037 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1039 * LOOK_AHEAD defines how many desc statuses to check beyond the
1040 * current descriptor.
1041 * It must be a pound define for optimal performance.
1042 * Do not change the value of LOOK_AHEAD, as the ixgbe_rx_scan_hw_ring
1043 * function only works with LOOK_AHEAD=8.
1045 #define LOOK_AHEAD 8
1046 #if (LOOK_AHEAD != 8)
1047 #error "PMD IXGBE: LOOK_AHEAD must be 8\n"
1050 ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
1052 volatile union ixgbe_adv_rx_desc *rxdp;
1053 struct ixgbe_rx_entry *rxep;
1054 struct rte_mbuf *mb;
1059 uint32_t s[LOOK_AHEAD];
1060 uint16_t pkt_info[LOOK_AHEAD];
1062 int s[LOOK_AHEAD], nb_dd;
1063 #endif /* RTE_NEXT_ABI */
1064 int i, j, nb_rx = 0;
1067 /* get references to current descriptor and S/W ring entry */
1068 rxdp = &rxq->rx_ring[rxq->rx_tail];
1069 rxep = &rxq->sw_ring[rxq->rx_tail];
1071 /* check to make sure there is at least 1 packet to receive */
1072 if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
1076 * Scan LOOK_AHEAD descriptors at a time to determine which descriptors
1077 * reference packets that are ready to be received.
1079 for (i = 0; i < RTE_PMD_IXGBE_RX_MAX_BURST;
1080 i += LOOK_AHEAD, rxdp += LOOK_AHEAD, rxep += LOOK_AHEAD)
1082 /* Read desc statuses backwards to avoid race condition */
1083 for (j = LOOK_AHEAD-1; j >= 0; --j)
1084 s[j] = rxdp[j].wb.upper.status_error;
1087 for (j = LOOK_AHEAD - 1; j >= 0; --j)
1088 pkt_info[j] = rxdp[j].wb.lower.lo_dword.
1090 #endif /* RTE_NEXT_ABI */
1092 /* Compute how many status bits were set */
1094 for (j = 0; j < LOOK_AHEAD; ++j)
1095 nb_dd += s[j] & IXGBE_RXDADV_STAT_DD;
1099 /* Translate descriptor info to mbuf format */
1100 for (j = 0; j < nb_dd; ++j) {
1102 pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
1103 mb->data_len = pkt_len;
1104 mb->pkt_len = pkt_len;
1105 mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
1107 /* convert descriptor fields to rte mbuf flags */
1109 pkt_flags = rx_desc_status_to_pkt_flags(s[j]);
1110 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1112 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info[j]);
1113 mb->ol_flags = pkt_flags;
1115 ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
1116 #else /* RTE_NEXT_ABI */
1117 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
1118 rxdp[j].wb.lower.lo_dword.data);
1119 /* reuse status field from scan list */
1120 pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
1121 pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
1122 mb->ol_flags = pkt_flags;
1123 #endif /* RTE_NEXT_ABI */
1125 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1126 mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
1127 else if (pkt_flags & PKT_RX_FDIR) {
1128 mb->hash.fdir.hash =
1129 (uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
1130 & IXGBE_ATR_HASH_MASK);
1131 mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
1135 /* Move mbuf pointers from the S/W ring to the stage */
1136 for (j = 0; j < LOOK_AHEAD; ++j) {
1137 rxq->rx_stage[i + j] = rxep[j].mbuf;
1140 /* stop if all requested packets could not be received */
1141 if (nb_dd != LOOK_AHEAD)
1145 /* clear software ring entries so we can cleanup correctly */
1146 for (i = 0; i < nb_rx; ++i) {
1147 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1155 ixgbe_rx_alloc_bufs(struct ixgbe_rx_queue *rxq, bool reset_mbuf)
1157 volatile union ixgbe_adv_rx_desc *rxdp;
1158 struct ixgbe_rx_entry *rxep;
1159 struct rte_mbuf *mb;
1164 /* allocate buffers in bulk directly into the S/W ring */
1165 alloc_idx = rxq->rx_free_trigger - (rxq->rx_free_thresh - 1);
1166 rxep = &rxq->sw_ring[alloc_idx];
1167 diag = rte_mempool_get_bulk(rxq->mb_pool, (void *)rxep,
1168 rxq->rx_free_thresh);
1169 if (unlikely(diag != 0))
1172 rxdp = &rxq->rx_ring[alloc_idx];
1173 for (i = 0; i < rxq->rx_free_thresh; ++i) {
1174 /* populate the static rte mbuf fields */
1179 mb->port = rxq->port_id;
1182 rte_mbuf_refcnt_set(mb, 1);
1183 mb->data_off = RTE_PKTMBUF_HEADROOM;
1185 /* populate the descriptors */
1186 dma_addr = rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1187 rxdp[i].read.hdr_addr = dma_addr;
1188 rxdp[i].read.pkt_addr = dma_addr;
1191 /* update state of internal queue structure */
1192 rxq->rx_free_trigger = rxq->rx_free_trigger + rxq->rx_free_thresh;
1193 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1194 rxq->rx_free_trigger = rxq->rx_free_thresh - 1;
1200 static inline uint16_t
1201 ixgbe_rx_fill_from_stage(struct ixgbe_rx_queue *rxq, struct rte_mbuf **rx_pkts,
1204 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1207 /* how many packets are ready to return? */
1208 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1210 /* copy mbuf pointers to the application's packet list */
1211 for (i = 0; i < nb_pkts; ++i)
1212 rx_pkts[i] = stage[i];
1214 /* update internal queue state */
1215 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1216 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1221 static inline uint16_t
1222 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1225 struct ixgbe_rx_queue *rxq = (struct ixgbe_rx_queue *)rx_queue;
1228 /* Any previously recv'd pkts will be returned from the Rx stage */
1229 if (rxq->rx_nb_avail)
1230 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1232 /* Scan the H/W ring for packets to receive */
1233 nb_rx = (uint16_t)ixgbe_rx_scan_hw_ring(rxq);
1235 /* update internal queue state */
1236 rxq->rx_next_avail = 0;
1237 rxq->rx_nb_avail = nb_rx;
1238 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1240 /* if required, allocate new buffers to replenish descriptors */
1241 if (rxq->rx_tail > rxq->rx_free_trigger) {
1242 uint16_t cur_free_trigger = rxq->rx_free_trigger;
1244 if (ixgbe_rx_alloc_bufs(rxq, true) != 0) {
1246 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1247 "queue_id=%u", (unsigned) rxq->port_id,
1248 (unsigned) rxq->queue_id);
1250 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
1251 rxq->rx_free_thresh;
1254 * Need to rewind any previous receives if we cannot
1255 * allocate new buffers to replenish the old ones.
1257 rxq->rx_nb_avail = 0;
1258 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1259 for (i = 0, j = rxq->rx_tail; i < nb_rx; ++i, ++j)
1260 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1265 /* update tail pointer */
1267 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, cur_free_trigger);
1270 if (rxq->rx_tail >= rxq->nb_rx_desc)
1273 /* received any packets this loop? */
1274 if (rxq->rx_nb_avail)
1275 return ixgbe_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1280 /* split requests into chunks of size RTE_PMD_IXGBE_RX_MAX_BURST */
1282 ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1287 if (unlikely(nb_pkts == 0))
1290 if (likely(nb_pkts <= RTE_PMD_IXGBE_RX_MAX_BURST))
1291 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1293 /* request is relatively large, chunk it up */
1297 n = (uint16_t)RTE_MIN(nb_pkts, RTE_PMD_IXGBE_RX_MAX_BURST);
1298 ret = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1299 nb_rx = (uint16_t)(nb_rx + ret);
1300 nb_pkts = (uint16_t)(nb_pkts - ret);
1310 /* Stub to avoid extra ifdefs */
1312 ixgbe_recv_pkts_bulk_alloc(__rte_unused void *rx_queue,
1313 __rte_unused struct rte_mbuf **rx_pkts, __rte_unused uint16_t nb_pkts)
1319 ixgbe_rx_alloc_bufs(__rte_unused struct ixgbe_rx_queue *rxq,
1320 __rte_unused bool reset_mbuf)
1324 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
1327 ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1330 struct ixgbe_rx_queue *rxq;
1331 volatile union ixgbe_adv_rx_desc *rx_ring;
1332 volatile union ixgbe_adv_rx_desc *rxdp;
1333 struct ixgbe_rx_entry *sw_ring;
1334 struct ixgbe_rx_entry *rxe;
1335 struct rte_mbuf *rxm;
1336 struct rte_mbuf *nmb;
1337 union ixgbe_adv_rx_desc rxd;
1343 uint32_t hlen_type_rss;
1354 rx_id = rxq->rx_tail;
1355 rx_ring = rxq->rx_ring;
1356 sw_ring = rxq->sw_ring;
1357 while (nb_rx < nb_pkts) {
1359 * The order of operations here is important as the DD status
1360 * bit must not be read after any other descriptor fields.
1361 * rx_ring and rxdp are pointing to volatile data so the order
1362 * of accesses cannot be reordered by the compiler. If they were
1363 * not volatile, they could be reordered which could lead to
1364 * using invalid descriptor fields when read from rxd.
1366 rxdp = &rx_ring[rx_id];
1367 staterr = rxdp->wb.upper.status_error;
1368 if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
1375 * If the IXGBE_RXDADV_STAT_EOP flag is not set, the RX packet
1376 * is likely to be invalid and to be dropped by the various
1377 * validation checks performed by the network stack.
1379 * Allocate a new mbuf to replenish the RX ring descriptor.
1380 * If the allocation fails:
1381 * - arrange for that RX descriptor to be the first one
1382 * being parsed the next time the receive function is
1383 * invoked [on the same queue].
1385 * - Stop parsing the RX ring and return immediately.
1387 * This policy do not drop the packet received in the RX
1388 * descriptor for which the allocation of a new mbuf failed.
1389 * Thus, it allows that packet to be later retrieved if
1390 * mbuf have been freed in the mean time.
1391 * As a side effect, holding RX descriptors instead of
1392 * systematically giving them back to the NIC may lead to
1393 * RX ring exhaustion situations.
1394 * However, the NIC can gracefully prevent such situations
1395 * to happen by sending specific "back-pressure" flow control
1396 * frames to its peer(s).
1398 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1399 "ext_err_stat=0x%08x pkt_len=%u",
1400 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1401 (unsigned) rx_id, (unsigned) staterr,
1402 (unsigned) rte_le_to_cpu_16(rxd.wb.upper.length));
1404 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1406 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1407 "queue_id=%u", (unsigned) rxq->port_id,
1408 (unsigned) rxq->queue_id);
1409 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1414 rxe = &sw_ring[rx_id];
1416 if (rx_id == rxq->nb_rx_desc)
1419 /* Prefetch next mbuf while processing current one. */
1420 rte_ixgbe_prefetch(sw_ring[rx_id].mbuf);
1423 * When next RX descriptor is on a cache-line boundary,
1424 * prefetch the next 4 RX descriptors and the next 8 pointers
1427 if ((rx_id & 0x3) == 0) {
1428 rte_ixgbe_prefetch(&rx_ring[rx_id]);
1429 rte_ixgbe_prefetch(&sw_ring[rx_id]);
1435 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1436 rxdp->read.hdr_addr = dma_addr;
1437 rxdp->read.pkt_addr = dma_addr;
1440 * Initialize the returned mbuf.
1441 * 1) setup generic mbuf fields:
1442 * - number of segments,
1445 * - RX port identifier.
1446 * 2) integrate hardware offload data, if any:
1447 * - RSS flag & hash,
1448 * - IP checksum flag,
1449 * - VLAN TCI, if any,
1452 pkt_len = (uint16_t) (rte_le_to_cpu_16(rxd.wb.upper.length) -
1454 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1455 rte_packet_prefetch((char *)rxm->buf_addr + rxm->data_off);
1458 rxm->pkt_len = pkt_len;
1459 rxm->data_len = pkt_len;
1460 rxm->port = rxq->port_id;
1463 pkt_info = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.hs_rss.
1465 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1466 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1468 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1469 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1470 pkt_flags = pkt_flags |
1471 ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1472 rxm->ol_flags = pkt_flags;
1473 rxm->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1474 #else /* RTE_NEXT_ABI */
1475 hlen_type_rss = rte_le_to_cpu_32(rxd.wb.lower.lo_dword.data);
1476 /* Only valid if PKT_RX_VLAN_PKT set in pkt_flags */
1477 rxm->vlan_tci = rte_le_to_cpu_16(rxd.wb.upper.vlan);
1479 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1480 pkt_flags = pkt_flags | rx_desc_status_to_pkt_flags(staterr);
1481 pkt_flags = pkt_flags | rx_desc_error_to_pkt_flags(staterr);
1482 rxm->ol_flags = pkt_flags;
1483 #endif /* RTE_NEXT_ABI */
1485 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1486 rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
1487 else if (pkt_flags & PKT_RX_FDIR) {
1488 rxm->hash.fdir.hash =
1489 (uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
1490 & IXGBE_ATR_HASH_MASK);
1491 rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
1494 * Store the mbuf address into the next entry of the array
1495 * of returned packets.
1497 rx_pkts[nb_rx++] = rxm;
1499 rxq->rx_tail = rx_id;
1502 * If the number of free RX descriptors is greater than the RX free
1503 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1505 * Update the RDT with the value of the last processed RX descriptor
1506 * minus 1, to guarantee that the RDT register is never equal to the
1507 * RDH register, which creates a "full" ring situtation from the
1508 * hardware point of view...
1510 nb_hold = (uint16_t) (nb_hold + rxq->nb_rx_hold);
1511 if (nb_hold > rxq->rx_free_thresh) {
1512 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1513 "nb_hold=%u nb_rx=%u",
1514 (unsigned) rxq->port_id, (unsigned) rxq->queue_id,
1515 (unsigned) rx_id, (unsigned) nb_hold,
1517 rx_id = (uint16_t) ((rx_id == 0) ?
1518 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1519 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
1522 rxq->nb_rx_hold = nb_hold;
1527 * Detect an RSC descriptor.
1529 static inline uint32_t
1530 ixgbe_rsc_count(union ixgbe_adv_rx_desc *rx)
1532 return (rte_le_to_cpu_32(rx->wb.lower.lo_dword.data) &
1533 IXGBE_RXDADV_RSCCNT_MASK) >> IXGBE_RXDADV_RSCCNT_SHIFT;
1537 * ixgbe_fill_cluster_head_buf - fill the first mbuf of the returned packet
1539 * Fill the following info in the HEAD buffer of the Rx cluster:
1540 * - RX port identifier
1541 * - hardware offload data, if any:
1543 * - IP checksum flag
1544 * - VLAN TCI, if any
1546 * @head HEAD of the packet cluster
1547 * @desc HW descriptor to get data from
1548 * @port_id Port ID of the Rx queue
1551 ixgbe_fill_cluster_head_buf(
1552 struct rte_mbuf *head,
1553 union ixgbe_adv_rx_desc *desc,
1561 head->port = port_id;
1563 /* The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1564 * set in the pkt_flags field.
1566 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1567 pkt_info = rte_le_to_cpu_32(desc->wb.lower.lo_dword.hs_rss.pkt_info);
1568 pkt_flags = rx_desc_status_to_pkt_flags(staterr);
1569 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1570 pkt_flags |= ixgbe_rxd_pkt_info_to_pkt_flags(pkt_info);
1571 head->ol_flags = pkt_flags;
1572 head->packet_type = ixgbe_rxd_pkt_info_to_pkt_type(pkt_info);
1573 #else /* RTE_NEXT_ABI */
1574 uint32_t hlen_type_rss;
1577 head->port = port_id;
1580 * The vlan_tci field is only valid when PKT_RX_VLAN_PKT is
1581 * set in the pkt_flags field.
1583 head->vlan_tci = rte_le_to_cpu_16(desc->wb.upper.vlan);
1584 hlen_type_rss = rte_le_to_cpu_32(desc->wb.lower.lo_dword.data);
1585 pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(hlen_type_rss);
1586 pkt_flags |= rx_desc_status_to_pkt_flags(staterr);
1587 pkt_flags |= rx_desc_error_to_pkt_flags(staterr);
1588 head->ol_flags = pkt_flags;
1589 #endif /* RTE_NEXT_ABI */
1591 if (likely(pkt_flags & PKT_RX_RSS_HASH))
1592 head->hash.rss = rte_le_to_cpu_32(desc->wb.lower.hi_dword.rss);
1593 else if (pkt_flags & PKT_RX_FDIR) {
1594 head->hash.fdir.hash =
1595 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.csum)
1596 & IXGBE_ATR_HASH_MASK;
1597 head->hash.fdir.id =
1598 rte_le_to_cpu_16(desc->wb.lower.hi_dword.csum_ip.ip_id);
1603 * ixgbe_recv_pkts_lro - receive handler for and LRO case.
1605 * @rx_queue Rx queue handle
1606 * @rx_pkts table of received packets
1607 * @nb_pkts size of rx_pkts table
1608 * @bulk_alloc if TRUE bulk allocation is used for a HW ring refilling
1610 * Handles the Rx HW ring completions when RSC feature is configured. Uses an
1611 * additional ring of ixgbe_rsc_entry's that will hold the relevant RSC info.
1613 * We use the same logic as in Linux and in FreeBSD ixgbe drivers:
1614 * 1) When non-EOP RSC completion arrives:
1615 * a) Update the HEAD of the current RSC aggregation cluster with the new
1616 * segment's data length.
1617 * b) Set the "next" pointer of the current segment to point to the segment
1618 * at the NEXTP index.
1619 * c) Pass the HEAD of RSC aggregation cluster on to the next NEXTP entry
1620 * in the sw_rsc_ring.
1621 * 2) When EOP arrives we just update the cluster's total length and offload
1622 * flags and deliver the cluster up to the upper layers. In our case - put it
1623 * in the rx_pkts table.
1625 * Returns the number of received packets/clusters (according to the "bulk
1626 * receive" interface).
1628 static inline uint16_t
1629 ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
1632 struct ixgbe_rx_queue *rxq = rx_queue;
1633 volatile union ixgbe_adv_rx_desc *rx_ring = rxq->rx_ring;
1634 struct ixgbe_rx_entry *sw_ring = rxq->sw_ring;
1635 struct ixgbe_scattered_rx_entry *sw_sc_ring = rxq->sw_sc_ring;
1636 uint16_t rx_id = rxq->rx_tail;
1638 uint16_t nb_hold = rxq->nb_rx_hold;
1639 uint16_t prev_id = rxq->rx_tail;
1641 while (nb_rx < nb_pkts) {
1643 struct ixgbe_rx_entry *rxe;
1644 struct ixgbe_scattered_rx_entry *sc_entry;
1645 struct ixgbe_scattered_rx_entry *next_sc_entry;
1646 struct ixgbe_rx_entry *next_rxe;
1647 struct rte_mbuf *first_seg;
1648 struct rte_mbuf *rxm;
1649 struct rte_mbuf *nmb;
1650 union ixgbe_adv_rx_desc rxd;
1653 volatile union ixgbe_adv_rx_desc *rxdp;
1658 * The code in this whole file uses the volatile pointer to
1659 * ensure the read ordering of the status and the rest of the
1660 * descriptor fields (on the compiler level only!!!). This is so
1661 * UGLY - why not to just use the compiler barrier instead? DPDK
1662 * even has the rte_compiler_barrier() for that.
1664 * But most importantly this is just wrong because this doesn't
1665 * ensure memory ordering in a general case at all. For
1666 * instance, DPDK is supposed to work on Power CPUs where
1667 * compiler barrier may just not be enough!
1669 * I tried to write only this function properly to have a
1670 * starting point (as a part of an LRO/RSC series) but the
1671 * compiler cursed at me when I tried to cast away the
1672 * "volatile" from rx_ring (yes, it's volatile too!!!). So, I'm
1673 * keeping it the way it is for now.
1675 * The code in this file is broken in so many other places and
1676 * will just not work on a big endian CPU anyway therefore the
1677 * lines below will have to be revisited together with the rest
1681 * - Get rid of "volatile" crap and let the compiler do its
1683 * - Use the proper memory barrier (rte_rmb()) to ensure the
1684 * memory ordering below.
1686 rxdp = &rx_ring[rx_id];
1687 staterr = rte_le_to_cpu_32(rxdp->wb.upper.status_error);
1689 if (!(staterr & IXGBE_RXDADV_STAT_DD))
1694 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_id=%u "
1695 "staterr=0x%x data_len=%u",
1696 rxq->port_id, rxq->queue_id, rx_id, staterr,
1697 rte_le_to_cpu_16(rxd.wb.upper.length));
1700 nmb = rte_rxmbuf_alloc(rxq->mb_pool);
1702 PMD_RX_LOG(DEBUG, "RX mbuf alloc failed "
1703 "port_id=%u queue_id=%u",
1704 rxq->port_id, rxq->queue_id);
1706 rte_eth_devices[rxq->port_id].data->
1707 rx_mbuf_alloc_failed++;
1711 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
1712 else if (nb_hold > rxq->rx_free_thresh) {
1713 uint16_t next_rdt = rxq->rx_free_trigger;
1715 if (!ixgbe_rx_alloc_bufs(rxq, false)) {
1717 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr,
1719 nb_hold -= rxq->rx_free_thresh;
1721 PMD_RX_LOG(DEBUG, "RX bulk alloc failed "
1722 "port_id=%u queue_id=%u",
1723 rxq->port_id, rxq->queue_id);
1725 rte_eth_devices[rxq->port_id].data->
1726 rx_mbuf_alloc_failed++;
1733 rxe = &sw_ring[rx_id];
1734 eop = staterr & IXGBE_RXDADV_STAT_EOP;
1736 next_id = rx_id + 1;
1737 if (next_id == rxq->nb_rx_desc)
1740 /* Prefetch next mbuf while processing current one. */
1741 rte_ixgbe_prefetch(sw_ring[next_id].mbuf);
1744 * When next RX descriptor is on a cache-line boundary,
1745 * prefetch the next 4 RX descriptors and the next 4 pointers
1748 if ((next_id & 0x3) == 0) {
1749 rte_ixgbe_prefetch(&rx_ring[next_id]);
1750 rte_ixgbe_prefetch(&sw_ring[next_id]);
1757 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1759 * Update RX descriptor with the physical address of the
1760 * new data buffer of the new allocated mbuf.
1764 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1765 rxdp->read.hdr_addr = dma;
1766 rxdp->read.pkt_addr = dma;
1771 * Set data length & data buffer address of mbuf.
1773 data_len = rte_le_to_cpu_16(rxd.wb.upper.length);
1774 rxm->data_len = data_len;
1779 * Get next descriptor index:
1780 * - For RSC it's in the NEXTP field.
1781 * - For a scattered packet - it's just a following
1784 if (ixgbe_rsc_count(&rxd))
1786 (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1787 IXGBE_RXDADV_NEXTP_SHIFT;
1791 next_sc_entry = &sw_sc_ring[nextp_id];
1792 next_rxe = &sw_ring[nextp_id];
1793 rte_ixgbe_prefetch(next_rxe);
1796 sc_entry = &sw_sc_ring[rx_id];
1797 first_seg = sc_entry->fbuf;
1798 sc_entry->fbuf = NULL;
1801 * If this is the first buffer of the received packet,
1802 * set the pointer to the first mbuf of the packet and
1803 * initialize its context.
1804 * Otherwise, update the total length and the number of segments
1805 * of the current scattered packet, and update the pointer to
1806 * the last mbuf of the current packet.
1808 if (first_seg == NULL) {
1810 first_seg->pkt_len = data_len;
1811 first_seg->nb_segs = 1;
1813 first_seg->pkt_len += data_len;
1814 first_seg->nb_segs++;
1821 * If this is not the last buffer of the received packet, update
1822 * the pointer to the first mbuf at the NEXTP entry in the
1823 * sw_sc_ring and continue to parse the RX ring.
1826 rxm->next = next_rxe->mbuf;
1827 next_sc_entry->fbuf = first_seg;
1832 * This is the last buffer of the received packet - return
1833 * the current cluster to the user.
1837 /* Initialize the first mbuf of the returned packet */
1838 ixgbe_fill_cluster_head_buf(first_seg, &rxd, rxq->port_id,
1841 /* Prefetch data of first segment, if configured to do so. */
1842 rte_packet_prefetch((char *)first_seg->buf_addr +
1843 first_seg->data_off);
1846 * Store the mbuf address into the next entry of the array
1847 * of returned packets.
1849 rx_pkts[nb_rx++] = first_seg;
1853 * Record index of the next RX descriptor to probe.
1855 rxq->rx_tail = rx_id;
1858 * If the number of free RX descriptors is greater than the RX free
1859 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1861 * Update the RDT with the value of the last processed RX descriptor
1862 * minus 1, to guarantee that the RDT register is never equal to the
1863 * RDH register, which creates a "full" ring situtation from the
1864 * hardware point of view...
1866 if (!bulk_alloc && nb_hold > rxq->rx_free_thresh) {
1867 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
1868 "nb_hold=%u nb_rx=%u",
1869 rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
1872 IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, prev_id);
1876 rxq->nb_rx_hold = nb_hold;
1881 ixgbe_recv_pkts_lro_single_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1884 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, false);
1888 ixgbe_recv_pkts_lro_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
1891 return ixgbe_recv_pkts_lro(rx_queue, rx_pkts, nb_pkts, true);
1894 /*********************************************************************
1896 * Queue management functions
1898 **********************************************************************/
1901 * Rings setup and release.
1903 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
1904 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
1905 * also optimize cache line size effect. H/W supports up to cache line size 128.
1907 #define IXGBE_ALIGN 128
1910 * Maximum number of Ring Descriptors.
1912 * Since RDLEN/TDLEN should be multiple of 128 bytes, the number of ring
1913 * descriptors should meet the following condition:
1914 * (num_ring_desc * sizeof(rx/tx descriptor)) % 128 == 0
1916 #define IXGBE_MIN_RING_DESC 32
1917 #define IXGBE_MAX_RING_DESC 4096
1920 * Create memzone for HW rings. malloc can't be used as the physical address is
1921 * needed. If the memzone is already created, then this function returns a ptr
1924 static const struct rte_memzone * __attribute__((cold))
1925 ring_dma_zone_reserve(struct rte_eth_dev *dev, const char *ring_name,
1926 uint16_t queue_id, uint32_t ring_size, int socket_id)
1928 char z_name[RTE_MEMZONE_NAMESIZE];
1929 const struct rte_memzone *mz;
1931 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1932 dev->driver->pci_drv.name, ring_name,
1933 dev->data->port_id, queue_id);
1935 mz = rte_memzone_lookup(z_name);
1939 #ifdef RTE_LIBRTE_XEN_DOM0
1940 return rte_memzone_reserve_bounded(z_name, ring_size,
1941 socket_id, 0, IXGBE_ALIGN, RTE_PGSIZE_2M);
1943 return rte_memzone_reserve_aligned(z_name, ring_size,
1944 socket_id, 0, IXGBE_ALIGN);
1948 static void __attribute__((cold))
1949 ixgbe_tx_queue_release_mbufs(struct ixgbe_tx_queue *txq)
1953 if (txq->sw_ring != NULL) {
1954 for (i = 0; i < txq->nb_tx_desc; i++) {
1955 if (txq->sw_ring[i].mbuf != NULL) {
1956 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
1957 txq->sw_ring[i].mbuf = NULL;
1963 static void __attribute__((cold))
1964 ixgbe_tx_free_swring(struct ixgbe_tx_queue *txq)
1967 txq->sw_ring != NULL)
1968 rte_free(txq->sw_ring);
1971 static void __attribute__((cold))
1972 ixgbe_tx_queue_release(struct ixgbe_tx_queue *txq)
1974 if (txq != NULL && txq->ops != NULL) {
1975 txq->ops->release_mbufs(txq);
1976 txq->ops->free_swring(txq);
1981 void __attribute__((cold))
1982 ixgbe_dev_tx_queue_release(void *txq)
1984 ixgbe_tx_queue_release(txq);
1987 /* (Re)set dynamic ixgbe_tx_queue fields to defaults */
1988 static void __attribute__((cold))
1989 ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
1991 static const union ixgbe_adv_tx_desc zeroed_desc = {{0}};
1992 struct ixgbe_tx_entry *txe = txq->sw_ring;
1995 /* Zero out HW ring memory */
1996 for (i = 0; i < txq->nb_tx_desc; i++) {
1997 txq->tx_ring[i] = zeroed_desc;
2000 /* Initialize SW ring entries */
2001 prev = (uint16_t) (txq->nb_tx_desc - 1);
2002 for (i = 0; i < txq->nb_tx_desc; i++) {
2003 volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
2004 txd->wb.status = IXGBE_TXD_STAT_DD;
2007 txe[prev].next_id = i;
2011 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2012 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2015 txq->nb_tx_used = 0;
2017 * Always allow 1 descriptor to be un-allocated to avoid
2018 * a H/W race condition
2020 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2021 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2023 memset((void*)&txq->ctx_cache, 0,
2024 IXGBE_CTX_NUM * sizeof(struct ixgbe_advctx_info));
2027 static const struct ixgbe_txq_ops def_txq_ops = {
2028 .release_mbufs = ixgbe_tx_queue_release_mbufs,
2029 .free_swring = ixgbe_tx_free_swring,
2030 .reset = ixgbe_reset_tx_queue,
2033 /* Takes an ethdev and a queue and sets up the tx function to be used based on
2034 * the queue parameters. Used in tx_queue_setup by primary process and then
2035 * in dev_init by secondary process when attaching to an existing ethdev.
2037 void __attribute__((cold))
2038 ixgbe_set_tx_function(struct rte_eth_dev *dev, struct ixgbe_tx_queue *txq)
2040 /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2041 if (((txq->txq_flags & IXGBE_SIMPLE_FLAGS) == IXGBE_SIMPLE_FLAGS)
2042 && (txq->tx_rs_thresh >= RTE_PMD_IXGBE_TX_MAX_BURST)) {
2043 PMD_INIT_LOG(INFO, "Using simple tx code path");
2044 #ifdef RTE_IXGBE_INC_VECTOR
2045 if (txq->tx_rs_thresh <= RTE_IXGBE_TX_MAX_FREE_BUF_SZ &&
2046 (rte_eal_process_type() != RTE_PROC_PRIMARY ||
2047 ixgbe_txq_vec_setup(txq) == 0)) {
2048 PMD_INIT_LOG(INFO, "Vector tx enabled.");
2049 dev->tx_pkt_burst = ixgbe_xmit_pkts_vec;
2052 dev->tx_pkt_burst = ixgbe_xmit_pkts_simple;
2054 PMD_INIT_LOG(INFO, "Using full-featured tx code path");
2056 " - txq_flags = %lx " "[IXGBE_SIMPLE_FLAGS=%lx]",
2057 (unsigned long)txq->txq_flags,
2058 (unsigned long)IXGBE_SIMPLE_FLAGS);
2060 " - tx_rs_thresh = %lu " "[RTE_PMD_IXGBE_TX_MAX_BURST=%lu]",
2061 (unsigned long)txq->tx_rs_thresh,
2062 (unsigned long)RTE_PMD_IXGBE_TX_MAX_BURST);
2063 dev->tx_pkt_burst = ixgbe_xmit_pkts;
2067 int __attribute__((cold))
2068 ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev,
2071 unsigned int socket_id,
2072 const struct rte_eth_txconf *tx_conf)
2074 const struct rte_memzone *tz;
2075 struct ixgbe_tx_queue *txq;
2076 struct ixgbe_hw *hw;
2077 uint16_t tx_rs_thresh, tx_free_thresh;
2079 PMD_INIT_FUNC_TRACE();
2080 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2083 * Validate number of transmit descriptors.
2084 * It must not exceed hardware maximum, and must be multiple
2087 if (((nb_desc * sizeof(union ixgbe_adv_tx_desc)) % IXGBE_ALIGN) != 0 ||
2088 (nb_desc > IXGBE_MAX_RING_DESC) ||
2089 (nb_desc < IXGBE_MIN_RING_DESC)) {
2094 * The following two parameters control the setting of the RS bit on
2095 * transmit descriptors.
2096 * TX descriptors will have their RS bit set after txq->tx_rs_thresh
2097 * descriptors have been used.
2098 * The TX descriptor ring will be cleaned after txq->tx_free_thresh
2099 * descriptors are used or if the number of descriptors required
2100 * to transmit a packet is greater than the number of free TX
2102 * The following constraints must be satisfied:
2103 * tx_rs_thresh must be greater than 0.
2104 * tx_rs_thresh must be less than the size of the ring minus 2.
2105 * tx_rs_thresh must be less than or equal to tx_free_thresh.
2106 * tx_rs_thresh must be a divisor of the ring size.
2107 * tx_free_thresh must be greater than 0.
2108 * tx_free_thresh must be less than the size of the ring minus 3.
2109 * One descriptor in the TX ring is used as a sentinel to avoid a
2110 * H/W race condition, hence the maximum threshold constraints.
2111 * When set to zero use default values.
2113 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2114 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2115 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2116 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2117 if (tx_rs_thresh >= (nb_desc - 2)) {
2118 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the number "
2119 "of TX descriptors minus 2. (tx_rs_thresh=%u "
2120 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2121 (int)dev->data->port_id, (int)queue_idx);
2124 if (tx_free_thresh >= (nb_desc - 3)) {
2125 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2126 "tx_free_thresh must be less than the number of "
2127 "TX descriptors minus 3. (tx_free_thresh=%u "
2128 "port=%d queue=%d)",
2129 (unsigned int)tx_free_thresh,
2130 (int)dev->data->port_id, (int)queue_idx);
2133 if (tx_rs_thresh > tx_free_thresh) {
2134 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or equal to "
2135 "tx_free_thresh. (tx_free_thresh=%u "
2136 "tx_rs_thresh=%u port=%d queue=%d)",
2137 (unsigned int)tx_free_thresh,
2138 (unsigned int)tx_rs_thresh,
2139 (int)dev->data->port_id,
2143 if ((nb_desc % tx_rs_thresh) != 0) {
2144 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2145 "number of TX descriptors. (tx_rs_thresh=%u "
2146 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2147 (int)dev->data->port_id, (int)queue_idx);
2152 * If rs_bit_thresh is greater than 1, then TX WTHRESH should be
2153 * set to 0. If WTHRESH is greater than zero, the RS bit is ignored
2154 * by the NIC and all descriptors are written back after the NIC
2155 * accumulates WTHRESH descriptors.
2157 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2158 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2159 "tx_rs_thresh is greater than 1. (tx_rs_thresh=%u "
2160 "port=%d queue=%d)", (unsigned int)tx_rs_thresh,
2161 (int)dev->data->port_id, (int)queue_idx);
2165 /* Free memory prior to re-allocation if needed... */
2166 if (dev->data->tx_queues[queue_idx] != NULL) {
2167 ixgbe_tx_queue_release(dev->data->tx_queues[queue_idx]);
2168 dev->data->tx_queues[queue_idx] = NULL;
2171 /* First allocate the tx queue data structure */
2172 txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct ixgbe_tx_queue),
2173 RTE_CACHE_LINE_SIZE, socket_id);
2178 * Allocate TX ring hardware descriptors. A memzone large enough to
2179 * handle the maximum ring size is allocated in order to allow for
2180 * resizing in later calls to the queue setup function.
2182 tz = ring_dma_zone_reserve(dev, "tx_ring", queue_idx,
2183 sizeof(union ixgbe_adv_tx_desc) * IXGBE_MAX_RING_DESC,
2186 ixgbe_tx_queue_release(txq);
2190 txq->nb_tx_desc = nb_desc;
2191 txq->tx_rs_thresh = tx_rs_thresh;
2192 txq->tx_free_thresh = tx_free_thresh;
2193 txq->pthresh = tx_conf->tx_thresh.pthresh;
2194 txq->hthresh = tx_conf->tx_thresh.hthresh;
2195 txq->wthresh = tx_conf->tx_thresh.wthresh;
2196 txq->queue_id = queue_idx;
2197 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2198 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2199 txq->port_id = dev->data->port_id;
2200 txq->txq_flags = tx_conf->txq_flags;
2201 txq->ops = &def_txq_ops;
2202 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2205 * Modification to set VFTDT for virtual function if vf is detected
2207 if (hw->mac.type == ixgbe_mac_82599_vf ||
2208 hw->mac.type == ixgbe_mac_X540_vf ||
2209 hw->mac.type == ixgbe_mac_X550_vf ||
2210 hw->mac.type == ixgbe_mac_X550EM_x_vf)
2211 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_VFTDT(queue_idx));
2213 txq->tdt_reg_addr = IXGBE_PCI_REG_ADDR(hw, IXGBE_TDT(txq->reg_idx));
2214 #ifndef RTE_LIBRTE_XEN_DOM0
2215 txq->tx_ring_phys_addr = (uint64_t) tz->phys_addr;
2217 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2219 txq->tx_ring = (union ixgbe_adv_tx_desc *) tz->addr;
2221 /* Allocate software ring */
2222 txq->sw_ring = rte_zmalloc_socket("txq->sw_ring",
2223 sizeof(struct ixgbe_tx_entry) * nb_desc,
2224 RTE_CACHE_LINE_SIZE, socket_id);
2225 if (txq->sw_ring == NULL) {
2226 ixgbe_tx_queue_release(txq);
2229 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64,
2230 txq->sw_ring, txq->tx_ring, txq->tx_ring_phys_addr);
2232 /* set up vector or scalar TX function as appropriate */
2233 ixgbe_set_tx_function(dev, txq);
2235 txq->ops->reset(txq);
2237 dev->data->tx_queues[queue_idx] = txq;
2244 * ixgbe_free_sc_cluster - free the not-yet-completed scattered cluster
2246 * The "next" pointer of the last segment of (not-yet-completed) RSC clusters
2247 * in the sw_rsc_ring is not set to NULL but rather points to the next
2248 * mbuf of this RSC aggregation (that has not been completed yet and still
2249 * resides on the HW ring). So, instead of calling for rte_pktmbuf_free() we
2250 * will just free first "nb_segs" segments of the cluster explicitly by calling
2251 * an rte_pktmbuf_free_seg().
2253 * @m scattered cluster head
2255 static void __attribute__((cold))
2256 ixgbe_free_sc_cluster(struct rte_mbuf *m)
2258 uint8_t i, nb_segs = m->nb_segs;
2259 struct rte_mbuf *next_seg;
2261 for (i = 0; i < nb_segs; i++) {
2263 rte_pktmbuf_free_seg(m);
2268 static void __attribute__((cold))
2269 ixgbe_rx_queue_release_mbufs(struct ixgbe_rx_queue *rxq)
2273 #ifdef RTE_IXGBE_INC_VECTOR
2274 /* SSE Vector driver has a different way of releasing mbufs. */
2275 if (rxq->rx_using_sse) {
2276 ixgbe_rx_queue_release_mbufs_vec(rxq);
2281 if (rxq->sw_ring != NULL) {
2282 for (i = 0; i < rxq->nb_rx_desc; i++) {
2283 if (rxq->sw_ring[i].mbuf != NULL) {
2284 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2285 rxq->sw_ring[i].mbuf = NULL;
2288 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2289 if (rxq->rx_nb_avail) {
2290 for (i = 0; i < rxq->rx_nb_avail; ++i) {
2291 struct rte_mbuf *mb;
2292 mb = rxq->rx_stage[rxq->rx_next_avail + i];
2293 rte_pktmbuf_free_seg(mb);
2295 rxq->rx_nb_avail = 0;
2300 if (rxq->sw_sc_ring)
2301 for (i = 0; i < rxq->nb_rx_desc; i++)
2302 if (rxq->sw_sc_ring[i].fbuf) {
2303 ixgbe_free_sc_cluster(rxq->sw_sc_ring[i].fbuf);
2304 rxq->sw_sc_ring[i].fbuf = NULL;
2308 static void __attribute__((cold))
2309 ixgbe_rx_queue_release(struct ixgbe_rx_queue *rxq)
2312 ixgbe_rx_queue_release_mbufs(rxq);
2313 rte_free(rxq->sw_ring);
2314 rte_free(rxq->sw_sc_ring);
2319 void __attribute__((cold))
2320 ixgbe_dev_rx_queue_release(void *rxq)
2322 ixgbe_rx_queue_release(rxq);
2326 * Check if Rx Burst Bulk Alloc function can be used.
2328 * 0: the preconditions are satisfied and the bulk allocation function
2330 * -EINVAL: the preconditions are NOT satisfied and the default Rx burst
2331 * function must be used.
2333 static inline int __attribute__((cold))
2334 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2335 check_rx_burst_bulk_alloc_preconditions(struct ixgbe_rx_queue *rxq)
2337 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct ixgbe_rx_queue *rxq)
2343 * Make sure the following pre-conditions are satisfied:
2344 * rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST
2345 * rxq->rx_free_thresh < rxq->nb_rx_desc
2346 * (rxq->nb_rx_desc % rxq->rx_free_thresh) == 0
2347 * rxq->nb_rx_desc<(IXGBE_MAX_RING_DESC-RTE_PMD_IXGBE_RX_MAX_BURST)
2348 * Scattered packets are not supported. This should be checked
2349 * outside of this function.
2351 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2352 if (!(rxq->rx_free_thresh >= RTE_PMD_IXGBE_RX_MAX_BURST)) {
2353 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2354 "rxq->rx_free_thresh=%d, "
2355 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2356 rxq->rx_free_thresh, RTE_PMD_IXGBE_RX_MAX_BURST);
2358 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
2359 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2360 "rxq->rx_free_thresh=%d, "
2361 "rxq->nb_rx_desc=%d",
2362 rxq->rx_free_thresh, rxq->nb_rx_desc);
2364 } else if (!((rxq->nb_rx_desc % rxq->rx_free_thresh) == 0)) {
2365 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2366 "rxq->nb_rx_desc=%d, "
2367 "rxq->rx_free_thresh=%d",
2368 rxq->nb_rx_desc, rxq->rx_free_thresh);
2370 } else if (!(rxq->nb_rx_desc <
2371 (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST))) {
2372 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
2373 "rxq->nb_rx_desc=%d, "
2374 "IXGBE_MAX_RING_DESC=%d, "
2375 "RTE_PMD_IXGBE_RX_MAX_BURST=%d",
2376 rxq->nb_rx_desc, IXGBE_MAX_RING_DESC,
2377 RTE_PMD_IXGBE_RX_MAX_BURST);
2387 /* Reset dynamic ixgbe_rx_queue fields back to defaults */
2388 static void __attribute__((cold))
2389 ixgbe_reset_rx_queue(struct ixgbe_adapter *adapter, struct ixgbe_rx_queue *rxq)
2391 static const union ixgbe_adv_rx_desc zeroed_desc = {{0}};
2393 uint16_t len = rxq->nb_rx_desc;
2396 * By default, the Rx queue setup function allocates enough memory for
2397 * IXGBE_MAX_RING_DESC. The Rx Burst bulk allocation function requires
2398 * extra memory at the end of the descriptor ring to be zero'd out. A
2399 * pre-condition for using the Rx burst bulk alloc function is that the
2400 * number of descriptors is less than or equal to
2401 * (IXGBE_MAX_RING_DESC - RTE_PMD_IXGBE_RX_MAX_BURST). Check all the
2402 * constraints here to see if we need to zero out memory after the end
2403 * of the H/W descriptor ring.
2405 if (adapter->rx_bulk_alloc_allowed)
2406 /* zero out extra memory */
2407 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2410 * Zero out HW ring memory. Zero out extra memory at the end of
2411 * the H/W ring so look-ahead logic in Rx Burst bulk alloc function
2412 * reads extra memory as zeros.
2414 for (i = 0; i < len; i++) {
2415 rxq->rx_ring[i] = zeroed_desc;
2418 #ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
2420 * initialize extra software ring entries. Space for these extra
2421 * entries is always allocated
2423 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2424 for (i = rxq->nb_rx_desc; i < len; ++i) {
2425 rxq->sw_ring[i].mbuf = &rxq->fake_mbuf;
2428 rxq->rx_nb_avail = 0;
2429 rxq->rx_next_avail = 0;
2430 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2431 #endif /* RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC */
2433 rxq->nb_rx_hold = 0;
2434 rxq->pkt_first_seg = NULL;
2435 rxq->pkt_last_seg = NULL;
2438 int __attribute__((cold))
2439 ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev,
2442 unsigned int socket_id,
2443 const struct rte_eth_rxconf *rx_conf,
2444 struct rte_mempool *mp)
2446 const struct rte_memzone *rz;
2447 struct ixgbe_rx_queue *rxq;
2448 struct ixgbe_hw *hw;
2450 struct ixgbe_adapter *adapter =
2451 (struct ixgbe_adapter *)dev->data->dev_private;
2453 PMD_INIT_FUNC_TRACE();
2454 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2457 * Validate number of receive descriptors.
2458 * It must not exceed hardware maximum, and must be multiple
2461 if (((nb_desc * sizeof(union ixgbe_adv_rx_desc)) % IXGBE_ALIGN) != 0 ||
2462 (nb_desc > IXGBE_MAX_RING_DESC) ||
2463 (nb_desc < IXGBE_MIN_RING_DESC)) {
2467 /* Free memory prior to re-allocation if needed... */
2468 if (dev->data->rx_queues[queue_idx] != NULL) {
2469 ixgbe_rx_queue_release(dev->data->rx_queues[queue_idx]);
2470 dev->data->rx_queues[queue_idx] = NULL;
2473 /* First allocate the rx queue data structure */
2474 rxq = rte_zmalloc_socket("ethdev RX queue", sizeof(struct ixgbe_rx_queue),
2475 RTE_CACHE_LINE_SIZE, socket_id);
2479 rxq->nb_rx_desc = nb_desc;
2480 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2481 rxq->queue_id = queue_idx;
2482 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ?
2483 queue_idx : RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx + queue_idx);
2484 rxq->port_id = dev->data->port_id;
2485 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2487 rxq->drop_en = rx_conf->rx_drop_en;
2488 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2491 * Allocate RX ring hardware descriptors. A memzone large enough to
2492 * handle the maximum ring size is allocated in order to allow for
2493 * resizing in later calls to the queue setup function.
2495 rz = ring_dma_zone_reserve(dev, "rx_ring", queue_idx,
2496 RX_RING_SZ, socket_id);
2498 ixgbe_rx_queue_release(rxq);
2503 * Zero init all the descriptors in the ring.
2505 memset (rz->addr, 0, RX_RING_SZ);
2508 * Modified to setup VFRDT for Virtual Function
2510 if (hw->mac.type == ixgbe_mac_82599_vf ||
2511 hw->mac.type == ixgbe_mac_X540_vf ||
2512 hw->mac.type == ixgbe_mac_X550_vf ||
2513 hw->mac.type == ixgbe_mac_X550EM_x_vf) {
2515 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDT(queue_idx));
2517 IXGBE_PCI_REG_ADDR(hw, IXGBE_VFRDH(queue_idx));
2521 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDT(rxq->reg_idx));
2523 IXGBE_PCI_REG_ADDR(hw, IXGBE_RDH(rxq->reg_idx));
2525 #ifndef RTE_LIBRTE_XEN_DOM0
2526 rxq->rx_ring_phys_addr = (uint64_t) rz->phys_addr;
2528 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2530 rxq->rx_ring = (union ixgbe_adv_rx_desc *) rz->addr;
2533 * Certain constraints must be met in order to use the bulk buffer
2534 * allocation Rx burst function. If any of Rx queues doesn't meet them
2535 * the feature should be disabled for the whole port.
2537 if (check_rx_burst_bulk_alloc_preconditions(rxq)) {
2538 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Rx Bulk Alloc "
2539 "preconditions - canceling the feature for "
2540 "the whole port[%d]",
2541 rxq->queue_id, rxq->port_id);
2542 adapter->rx_bulk_alloc_allowed = false;
2546 * Allocate software ring. Allow for space at the end of the
2547 * S/W ring to make sure look-ahead logic in bulk alloc Rx burst
2548 * function does not access an invalid memory region.
2551 if (adapter->rx_bulk_alloc_allowed)
2552 len += RTE_PMD_IXGBE_RX_MAX_BURST;
2554 rxq->sw_ring = rte_zmalloc_socket("rxq->sw_ring",
2555 sizeof(struct ixgbe_rx_entry) * len,
2556 RTE_CACHE_LINE_SIZE, socket_id);
2557 if (!rxq->sw_ring) {
2558 ixgbe_rx_queue_release(rxq);
2563 * Always allocate even if it's not going to be needed in order to
2564 * simplify the code.
2566 * This ring is used in LRO and Scattered Rx cases and Scattered Rx may
2567 * be requested in ixgbe_dev_rx_init(), which is called later from
2571 rte_zmalloc_socket("rxq->sw_sc_ring",
2572 sizeof(struct ixgbe_scattered_rx_entry) * len,
2573 RTE_CACHE_LINE_SIZE, socket_id);
2574 if (!rxq->sw_sc_ring) {
2575 ixgbe_rx_queue_release(rxq);
2579 PMD_INIT_LOG(DEBUG, "sw_ring=%p sw_sc_ring=%p hw_ring=%p "
2580 "dma_addr=0x%"PRIx64,
2581 rxq->sw_ring, rxq->sw_sc_ring, rxq->rx_ring,
2582 rxq->rx_ring_phys_addr);
2584 if (!rte_is_power_of_2(nb_desc)) {
2585 PMD_INIT_LOG(DEBUG, "queue[%d] doesn't meet Vector Rx "
2586 "preconditions - canceling the feature for "
2587 "the whole port[%d]",
2588 rxq->queue_id, rxq->port_id);
2589 adapter->rx_vec_allowed = false;
2591 ixgbe_rxq_vec_setup(rxq);
2593 dev->data->rx_queues[queue_idx] = rxq;
2595 ixgbe_reset_rx_queue(adapter, rxq);
2601 ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2603 #define IXGBE_RXQ_SCAN_INTERVAL 4
2604 volatile union ixgbe_adv_rx_desc *rxdp;
2605 struct ixgbe_rx_queue *rxq;
2608 if (rx_queue_id >= dev->data->nb_rx_queues) {
2609 PMD_RX_LOG(ERR, "Invalid RX queue id=%d", rx_queue_id);
2613 rxq = dev->data->rx_queues[rx_queue_id];
2614 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2616 while ((desc < rxq->nb_rx_desc) &&
2617 (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
2618 desc += IXGBE_RXQ_SCAN_INTERVAL;
2619 rxdp += IXGBE_RXQ_SCAN_INTERVAL;
2620 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2621 rxdp = &(rxq->rx_ring[rxq->rx_tail +
2622 desc - rxq->nb_rx_desc]);
2629 ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2631 volatile union ixgbe_adv_rx_desc *rxdp;
2632 struct ixgbe_rx_queue *rxq = rx_queue;
2635 if (unlikely(offset >= rxq->nb_rx_desc))
2637 desc = rxq->rx_tail + offset;
2638 if (desc >= rxq->nb_rx_desc)
2639 desc -= rxq->nb_rx_desc;
2641 rxdp = &rxq->rx_ring[desc];
2642 return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
2645 void __attribute__((cold))
2646 ixgbe_dev_clear_queues(struct rte_eth_dev *dev)
2649 struct ixgbe_adapter *adapter =
2650 (struct ixgbe_adapter *)dev->data->dev_private;
2652 PMD_INIT_FUNC_TRACE();
2654 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2655 struct ixgbe_tx_queue *txq = dev->data->tx_queues[i];
2657 txq->ops->release_mbufs(txq);
2658 txq->ops->reset(txq);
2662 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2663 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
2665 ixgbe_rx_queue_release_mbufs(rxq);
2666 ixgbe_reset_rx_queue(adapter, rxq);
2672 ixgbe_dev_free_queues(struct rte_eth_dev *dev)
2676 PMD_INIT_FUNC_TRACE();
2678 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2679 ixgbe_dev_rx_queue_release(dev->data->rx_queues[i]);
2680 dev->data->rx_queues[i] = NULL;
2682 dev->data->nb_rx_queues = 0;
2684 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2685 ixgbe_dev_tx_queue_release(dev->data->tx_queues[i]);
2686 dev->data->tx_queues[i] = NULL;
2688 dev->data->nb_tx_queues = 0;
2691 /*********************************************************************
2693 * Device RX/TX init functions
2695 **********************************************************************/
2698 * Receive Side Scaling (RSS)
2699 * See section 7.1.2.8 in the following document:
2700 * "Intel 82599 10 GbE Controller Datasheet" - Revision 2.1 October 2009
2703 * The source and destination IP addresses of the IP header and the source
2704 * and destination ports of TCP/UDP headers, if any, of received packets are
2705 * hashed against a configurable random key to compute a 32-bit RSS hash result.
2706 * The seven (7) LSBs of the 32-bit hash result are used as an index into a
2707 * 128-entry redirection table (RETA). Each entry of the RETA provides a 3-bit
2708 * RSS output index which is used as the RX queue index where to store the
2710 * The following output is supplied in the RX write-back descriptor:
2711 * - 32-bit result of the Microsoft RSS hash function,
2712 * - 4-bit RSS type field.
2716 * RSS random key supplied in section 7.1.2.8.3 of the Intel 82599 datasheet.
2717 * Used as the default key.
2719 static uint8_t rss_intel_key[40] = {
2720 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
2721 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
2722 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
2723 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
2724 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
2728 ixgbe_rss_disable(struct rte_eth_dev *dev)
2730 struct ixgbe_hw *hw;
2733 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2734 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2735 mrqc &= ~IXGBE_MRQC_RSSEN;
2736 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2740 ixgbe_hw_rss_hash_set(struct ixgbe_hw *hw, struct rte_eth_rss_conf *rss_conf)
2748 hash_key = rss_conf->rss_key;
2749 if (hash_key != NULL) {
2750 /* Fill in RSS hash key */
2751 for (i = 0; i < 10; i++) {
2752 rss_key = hash_key[(i * 4)];
2753 rss_key |= hash_key[(i * 4) + 1] << 8;
2754 rss_key |= hash_key[(i * 4) + 2] << 16;
2755 rss_key |= hash_key[(i * 4) + 3] << 24;
2756 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_RSSRK(0), i, rss_key);
2760 /* Set configured hashing protocols in MRQC register */
2761 rss_hf = rss_conf->rss_hf;
2762 mrqc = IXGBE_MRQC_RSSEN; /* Enable RSS */
2763 if (rss_hf & ETH_RSS_IPV4)
2764 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4;
2765 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
2766 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_TCP;
2767 if (rss_hf & ETH_RSS_IPV6)
2768 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6;
2769 if (rss_hf & ETH_RSS_IPV6_EX)
2770 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX;
2771 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
2772 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2773 if (rss_hf & ETH_RSS_IPV6_TCP_EX)
2774 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP;
2775 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
2776 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2777 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
2778 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2779 if (rss_hf & ETH_RSS_IPV6_UDP_EX)
2780 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
2781 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2785 ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
2786 struct rte_eth_rss_conf *rss_conf)
2788 struct ixgbe_hw *hw;
2792 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 * Excerpt from section 7.1.2.8 Receive-Side Scaling (RSS):
2796 * "RSS enabling cannot be done dynamically while it must be
2797 * preceded by a software reset"
2798 * Before changing anything, first check that the update RSS operation
2799 * does not attempt to disable RSS, if RSS was enabled at
2800 * initialization time, or does not attempt to enable RSS, if RSS was
2801 * disabled at initialization time.
2803 rss_hf = rss_conf->rss_hf & IXGBE_RSS_OFFLOAD_ALL;
2804 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2805 if (!(mrqc & IXGBE_MRQC_RSSEN)) { /* RSS disabled */
2806 if (rss_hf != 0) /* Enable RSS */
2808 return 0; /* Nothing to do */
2811 if (rss_hf == 0) /* Disable RSS */
2813 ixgbe_hw_rss_hash_set(hw, rss_conf);
2818 ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2819 struct rte_eth_rss_conf *rss_conf)
2821 struct ixgbe_hw *hw;
2828 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2829 hash_key = rss_conf->rss_key;
2830 if (hash_key != NULL) {
2831 /* Return RSS hash key */
2832 for (i = 0; i < 10; i++) {
2833 rss_key = IXGBE_READ_REG_ARRAY(hw, IXGBE_RSSRK(0), i);
2834 hash_key[(i * 4)] = rss_key & 0x000000FF;
2835 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF;
2836 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF;
2837 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF;
2841 /* Get RSS functions configured in MRQC register */
2842 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2843 if ((mrqc & IXGBE_MRQC_RSSEN) == 0) { /* RSS is disabled */
2844 rss_conf->rss_hf = 0;
2848 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4)
2849 rss_hf |= ETH_RSS_IPV4;
2850 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_TCP)
2851 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2852 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6)
2853 rss_hf |= ETH_RSS_IPV6;
2854 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX)
2855 rss_hf |= ETH_RSS_IPV6_EX;
2856 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_TCP)
2857 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2858 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP)
2859 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2860 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV4_UDP)
2861 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2862 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_UDP)
2863 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2864 if (mrqc & IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP)
2865 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2866 rss_conf->rss_hf = rss_hf;
2871 ixgbe_rss_configure(struct rte_eth_dev *dev)
2873 struct rte_eth_rss_conf rss_conf;
2874 struct ixgbe_hw *hw;
2879 PMD_INIT_FUNC_TRACE();
2880 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2883 * Fill in redirection table
2884 * The byte-swap is needed because NIC registers are in
2885 * little-endian order.
2888 for (i = 0, j = 0; i < 128; i++, j++) {
2889 if (j == dev->data->nb_rx_queues)
2891 reta = (reta << 8) | j;
2893 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2),
2898 * Configure the RSS key and the RSS protocols used to compute
2899 * the RSS hash of input packets.
2901 rss_conf = dev->data->dev_conf.rx_adv_conf.rss_conf;
2902 if ((rss_conf.rss_hf & IXGBE_RSS_OFFLOAD_ALL) == 0) {
2903 ixgbe_rss_disable(dev);
2906 if (rss_conf.rss_key == NULL)
2907 rss_conf.rss_key = rss_intel_key; /* Default hash key */
2908 ixgbe_hw_rss_hash_set(hw, &rss_conf);
2911 #define NUM_VFTA_REGISTERS 128
2912 #define NIC_RX_BUFFER_SIZE 0x200
2915 ixgbe_vmdq_dcb_configure(struct rte_eth_dev *dev)
2917 struct rte_eth_vmdq_dcb_conf *cfg;
2918 struct ixgbe_hw *hw;
2919 enum rte_eth_nb_pools num_pools;
2920 uint32_t mrqc, vt_ctl, queue_mapping, vlanctrl;
2922 uint8_t nb_tcs; /* number of traffic classes */
2925 PMD_INIT_FUNC_TRACE();
2926 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2927 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
2928 num_pools = cfg->nb_queue_pools;
2929 /* Check we have a valid number of pools */
2930 if (num_pools != ETH_16_POOLS && num_pools != ETH_32_POOLS) {
2931 ixgbe_rss_disable(dev);
2934 /* 16 pools -> 8 traffic classes, 32 pools -> 4 traffic classes */
2935 nb_tcs = (uint8_t)(ETH_VMDQ_DCB_NUM_QUEUES / (int)num_pools);
2939 * split rx buffer up into sections, each for 1 traffic class
2941 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
2942 for (i = 0 ; i < nb_tcs; i++) {
2943 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2944 rxpbsize &= (~(0x3FF << IXGBE_RXPBSIZE_SHIFT));
2945 /* clear 10 bits. */
2946 rxpbsize |= (pbsize << IXGBE_RXPBSIZE_SHIFT); /* set value */
2947 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2949 /* zero alloc all unused TCs */
2950 for (i = nb_tcs; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
2951 uint32_t rxpbsize = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
2952 rxpbsize &= (~( 0x3FF << IXGBE_RXPBSIZE_SHIFT ));
2953 /* clear 10 bits. */
2954 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
2957 /* MRQC: enable vmdq and dcb */
2958 mrqc = ((num_pools == ETH_16_POOLS) ? \
2959 IXGBE_MRQC_VMDQRT8TCEN : IXGBE_MRQC_VMDQRT4TCEN );
2960 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2962 /* PFVTCTL: turn on virtualisation and set the default pool */
2963 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
2964 if (cfg->enable_default_pool) {
2965 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
2967 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
2970 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
2972 /* RTRUP2TC: mapping user priorities to traffic classes (TCs) */
2974 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
2976 * mapping is done with 3 bits per priority,
2977 * so shift by i*3 each time
2979 queue_mapping |= ((cfg->dcb_queue[i] & 0x07) << (i * 3));
2981 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, queue_mapping);
2983 /* RTRPCS: DCB related */
2984 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, IXGBE_RMCS_RRM);
2986 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
2987 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2988 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
2989 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
2991 /* VFTA - enable all vlan filters */
2992 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
2993 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
2996 /* VFRE: pool enabling for receive - 16 or 32 */
2997 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), \
2998 num_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3001 * MPSAR - allow pools to read specific mac addresses
3002 * In this case, all pools should be able to read from mac addr 0
3004 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), 0xFFFFFFFF);
3005 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), 0xFFFFFFFF);
3007 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3008 for (i = 0; i < cfg->nb_pool_maps; i++) {
3009 /* set vlan id in VF register and set the valid bit */
3010 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3011 (cfg->pool_map[i].vlan_id & 0xFFF)));
3013 * Put the allowed pools in VFB reg. As we only have 16 or 32
3014 * pools, we only need to use the first half of the register
3017 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), cfg->pool_map[i].pools);
3022 * ixgbe_dcb_config_tx_hw_config - Configure general DCB TX parameters
3023 * @hw: pointer to hardware structure
3024 * @dcb_config: pointer to ixgbe_dcb_config structure
3027 ixgbe_dcb_tx_hw_config(struct ixgbe_hw *hw,
3028 struct ixgbe_dcb_config *dcb_config)
3033 PMD_INIT_FUNC_TRACE();
3034 if (hw->mac.type != ixgbe_mac_82598EB) {
3035 /* Disable the Tx desc arbiter so that MTQC can be changed */
3036 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3037 reg |= IXGBE_RTTDCS_ARBDIS;
3038 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3040 /* Enable DCB for Tx with 8 TCs */
3041 if (dcb_config->num_tcs.pg_tcs == 8) {
3042 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3045 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3047 if (dcb_config->vt_mode)
3048 reg |= IXGBE_MTQC_VT_ENA;
3049 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3051 /* Disable drop for all queues */
3052 for (q = 0; q < 128; q++)
3053 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3054 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3056 /* Enable the Tx desc arbiter */
3057 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3058 reg &= ~IXGBE_RTTDCS_ARBDIS;
3059 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3061 /* Enable Security TX Buffer IFG for DCB */
3062 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3063 reg |= IXGBE_SECTX_DCB;
3064 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
3070 * ixgbe_vmdq_dcb_hw_tx_config - Configure general VMDQ+DCB TX parameters
3071 * @dev: pointer to rte_eth_dev structure
3072 * @dcb_config: pointer to ixgbe_dcb_config structure
3075 ixgbe_vmdq_dcb_hw_tx_config(struct rte_eth_dev *dev,
3076 struct ixgbe_dcb_config *dcb_config)
3078 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3079 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3080 struct ixgbe_hw *hw =
3081 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3083 PMD_INIT_FUNC_TRACE();
3084 if (hw->mac.type != ixgbe_mac_82598EB)
3085 /*PF VF Transmit Enable*/
3086 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0),
3087 vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ? 0xFFFF : 0xFFFFFFFF);
3089 /*Configure general DCB TX parameters*/
3090 ixgbe_dcb_tx_hw_config(hw,dcb_config);
3095 ixgbe_vmdq_dcb_rx_config(struct rte_eth_dev *dev,
3096 struct ixgbe_dcb_config *dcb_config)
3098 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
3099 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
3100 struct ixgbe_dcb_tc_config *tc;
3103 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3104 if (vmdq_rx_conf->nb_queue_pools == ETH_16_POOLS ) {
3105 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3106 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3109 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3110 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3112 /* User Priority to Traffic Class mapping */
3113 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3114 j = vmdq_rx_conf->dcb_queue[i];
3115 tc = &dcb_config->tc_config[j];
3116 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3122 ixgbe_dcb_vt_tx_config(struct rte_eth_dev *dev,
3123 struct ixgbe_dcb_config *dcb_config)
3125 struct rte_eth_vmdq_dcb_tx_conf *vmdq_tx_conf =
3126 &dev->data->dev_conf.tx_adv_conf.vmdq_dcb_tx_conf;
3127 struct ixgbe_dcb_tc_config *tc;
3130 /* convert rte_eth_conf.rx_adv_conf to struct ixgbe_dcb_config */
3131 if (vmdq_tx_conf->nb_queue_pools == ETH_16_POOLS ) {
3132 dcb_config->num_tcs.pg_tcs = ETH_8_TCS;
3133 dcb_config->num_tcs.pfc_tcs = ETH_8_TCS;
3136 dcb_config->num_tcs.pg_tcs = ETH_4_TCS;
3137 dcb_config->num_tcs.pfc_tcs = ETH_4_TCS;
3140 /* User Priority to Traffic Class mapping */
3141 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3142 j = vmdq_tx_conf->dcb_queue[i];
3143 tc = &dcb_config->tc_config[j];
3144 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3151 ixgbe_dcb_rx_config(struct rte_eth_dev *dev,
3152 struct ixgbe_dcb_config *dcb_config)
3154 struct rte_eth_dcb_rx_conf *rx_conf =
3155 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
3156 struct ixgbe_dcb_tc_config *tc;
3159 dcb_config->num_tcs.pg_tcs = (uint8_t)rx_conf->nb_tcs;
3160 dcb_config->num_tcs.pfc_tcs = (uint8_t)rx_conf->nb_tcs;
3162 /* User Priority to Traffic Class mapping */
3163 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3164 j = rx_conf->dcb_queue[i];
3165 tc = &dcb_config->tc_config[j];
3166 tc->path[IXGBE_DCB_RX_CONFIG].up_to_tc_bitmap =
3172 ixgbe_dcb_tx_config(struct rte_eth_dev *dev,
3173 struct ixgbe_dcb_config *dcb_config)
3175 struct rte_eth_dcb_tx_conf *tx_conf =
3176 &dev->data->dev_conf.tx_adv_conf.dcb_tx_conf;
3177 struct ixgbe_dcb_tc_config *tc;
3180 dcb_config->num_tcs.pg_tcs = (uint8_t)tx_conf->nb_tcs;
3181 dcb_config->num_tcs.pfc_tcs = (uint8_t)tx_conf->nb_tcs;
3183 /* User Priority to Traffic Class mapping */
3184 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3185 j = tx_conf->dcb_queue[i];
3186 tc = &dcb_config->tc_config[j];
3187 tc->path[IXGBE_DCB_TX_CONFIG].up_to_tc_bitmap =
3193 * ixgbe_dcb_rx_hw_config - Configure general DCB RX HW parameters
3194 * @hw: pointer to hardware structure
3195 * @dcb_config: pointer to ixgbe_dcb_config structure
3198 ixgbe_dcb_rx_hw_config(struct ixgbe_hw *hw,
3199 struct ixgbe_dcb_config *dcb_config)
3205 PMD_INIT_FUNC_TRACE();
3207 * Disable the arbiter before changing parameters
3208 * (always enable recycle mode; WSP)
3210 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS;
3211 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3213 if (hw->mac.type != ixgbe_mac_82598EB) {
3214 reg = IXGBE_READ_REG(hw, IXGBE_MRQC);
3215 if (dcb_config->num_tcs.pg_tcs == 4) {
3216 if (dcb_config->vt_mode)
3217 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3218 IXGBE_MRQC_VMDQRT4TCEN;
3220 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3221 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3225 if (dcb_config->num_tcs.pg_tcs == 8) {
3226 if (dcb_config->vt_mode)
3227 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3228 IXGBE_MRQC_VMDQRT8TCEN;
3230 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, 0);
3231 reg = (reg & ~IXGBE_MRQC_MRQE_MASK) |
3236 IXGBE_WRITE_REG(hw, IXGBE_MRQC, reg);
3239 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3240 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3241 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3242 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3244 /* VFTA - enable all vlan filters */
3245 for (i = 0; i < NUM_VFTA_REGISTERS; i++) {
3246 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
3250 * Configure Rx packet plane (recycle mode; WSP) and
3253 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC;
3254 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg);
3260 ixgbe_dcb_hw_arbite_rx_config(struct ixgbe_hw *hw, uint16_t *refill,
3261 uint16_t *max,uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3263 switch (hw->mac.type) {
3264 case ixgbe_mac_82598EB:
3265 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
3267 case ixgbe_mac_82599EB:
3268 case ixgbe_mac_X540:
3269 case ixgbe_mac_X550:
3270 case ixgbe_mac_X550EM_x:
3271 ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
3280 ixgbe_dcb_hw_arbite_tx_config(struct ixgbe_hw *hw, uint16_t *refill, uint16_t *max,
3281 uint8_t *bwg_id, uint8_t *tsa, uint8_t *map)
3283 switch (hw->mac.type) {
3284 case ixgbe_mac_82598EB:
3285 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,tsa);
3286 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,tsa);
3288 case ixgbe_mac_82599EB:
3289 case ixgbe_mac_X540:
3290 case ixgbe_mac_X550:
3291 case ixgbe_mac_X550EM_x:
3292 ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,tsa);
3293 ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,tsa, map);
3300 #define DCB_RX_CONFIG 1
3301 #define DCB_TX_CONFIG 1
3302 #define DCB_TX_PB 1024
3304 * ixgbe_dcb_hw_configure - Enable DCB and configure
3305 * general DCB in VT mode and non-VT mode parameters
3306 * @dev: pointer to rte_eth_dev structure
3307 * @dcb_config: pointer to ixgbe_dcb_config structure
3310 ixgbe_dcb_hw_configure(struct rte_eth_dev *dev,
3311 struct ixgbe_dcb_config *dcb_config)
3314 uint8_t i,pfc_en,nb_tcs;
3316 uint8_t config_dcb_rx = 0;
3317 uint8_t config_dcb_tx = 0;
3318 uint8_t tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3319 uint8_t bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3320 uint16_t refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3321 uint16_t max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3322 uint8_t map[IXGBE_DCB_MAX_TRAFFIC_CLASS] = {0};
3323 struct ixgbe_dcb_tc_config *tc;
3324 uint32_t max_frame = dev->data->mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
3325 struct ixgbe_hw *hw =
3326 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3328 switch(dev->data->dev_conf.rxmode.mq_mode){
3329 case ETH_MQ_RX_VMDQ_DCB:
3330 dcb_config->vt_mode = true;
3331 if (hw->mac.type != ixgbe_mac_82598EB) {
3332 config_dcb_rx = DCB_RX_CONFIG;
3334 *get dcb and VT rx configuration parameters
3337 ixgbe_vmdq_dcb_rx_config(dev,dcb_config);
3338 /*Configure general VMDQ and DCB RX parameters*/
3339 ixgbe_vmdq_dcb_configure(dev);
3343 dcb_config->vt_mode = false;
3344 config_dcb_rx = DCB_RX_CONFIG;
3345 /* Get dcb TX configuration parameters from rte_eth_conf */
3346 ixgbe_dcb_rx_config(dev,dcb_config);
3347 /*Configure general DCB RX parameters*/
3348 ixgbe_dcb_rx_hw_config(hw, dcb_config);
3351 PMD_INIT_LOG(ERR, "Incorrect DCB RX mode configuration");
3354 switch (dev->data->dev_conf.txmode.mq_mode) {
3355 case ETH_MQ_TX_VMDQ_DCB:
3356 dcb_config->vt_mode = true;
3357 config_dcb_tx = DCB_TX_CONFIG;
3358 /* get DCB and VT TX configuration parameters from rte_eth_conf */
3359 ixgbe_dcb_vt_tx_config(dev,dcb_config);
3360 /*Configure general VMDQ and DCB TX parameters*/
3361 ixgbe_vmdq_dcb_hw_tx_config(dev,dcb_config);
3365 dcb_config->vt_mode = false;
3366 config_dcb_tx = DCB_TX_CONFIG;
3367 /*get DCB TX configuration parameters from rte_eth_conf*/
3368 ixgbe_dcb_tx_config(dev,dcb_config);
3369 /*Configure general DCB TX parameters*/
3370 ixgbe_dcb_tx_hw_config(hw, dcb_config);
3373 PMD_INIT_LOG(ERR, "Incorrect DCB TX mode configuration");
3377 nb_tcs = dcb_config->num_tcs.pfc_tcs;
3379 ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_RX_CONFIG, map);
3380 if(nb_tcs == ETH_4_TCS) {
3381 /* Avoid un-configured priority mapping to TC0 */
3383 uint8_t mask = 0xFF;
3384 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES - 4; i++)
3385 mask = (uint8_t)(mask & (~ (1 << map[i])));
3386 for (i = 0; mask && (i < IXGBE_DCB_MAX_TRAFFIC_CLASS); i++) {
3387 if ((mask & 0x1) && (j < ETH_DCB_NUM_USER_PRIORITIES))
3391 /* Re-configure 4 TCs BW */
3392 for (i = 0; i < nb_tcs; i++) {
3393 tc = &dcb_config->tc_config[i];
3394 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent =
3395 (uint8_t)(100 / nb_tcs);
3396 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent =
3397 (uint8_t)(100 / nb_tcs);
3399 for (; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
3400 tc = &dcb_config->tc_config[i];
3401 tc->path[IXGBE_DCB_TX_CONFIG].bwg_percent = 0;
3402 tc->path[IXGBE_DCB_RX_CONFIG].bwg_percent = 0;
3407 /* Set RX buffer size */
3408 pbsize = (uint16_t)(NIC_RX_BUFFER_SIZE / nb_tcs);
3409 uint32_t rxpbsize = pbsize << IXGBE_RXPBSIZE_SHIFT;
3410 for (i = 0 ; i < nb_tcs; i++) {
3411 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpbsize);
3413 /* zero alloc all unused TCs */
3414 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3415 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
3419 /* Only support an equally distributed Tx packet buffer strategy. */
3420 uint32_t txpktsize = IXGBE_TXPBSIZE_MAX / nb_tcs;
3421 uint32_t txpbthresh = (txpktsize / DCB_TX_PB) - IXGBE_TXPKT_SIZE_MAX;
3422 for (i = 0; i < nb_tcs; i++) {
3423 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
3424 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
3426 /* Clear unused TCs, if any, to zero buffer size*/
3427 for (; i < ETH_DCB_NUM_USER_PRIORITIES; i++) {
3428 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
3429 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
3433 /*Calculates traffic class credits*/
3434 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3435 IXGBE_DCB_TX_CONFIG);
3436 ixgbe_dcb_calculate_tc_credits_cee(hw, dcb_config,max_frame,
3437 IXGBE_DCB_RX_CONFIG);
3440 /* Unpack CEE standard containers */
3441 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_RX_CONFIG, refill);
3442 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3443 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_RX_CONFIG, bwgid);
3444 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_RX_CONFIG, tsa);
3445 /* Configure PG(ETS) RX */
3446 ixgbe_dcb_hw_arbite_rx_config(hw,refill,max,bwgid,tsa,map);
3450 /* Unpack CEE standard containers */
3451 ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
3452 ixgbe_dcb_unpack_max_cee(dcb_config, max);
3453 ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
3454 ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
3455 /* Configure PG(ETS) TX */
3456 ixgbe_dcb_hw_arbite_tx_config(hw,refill,max,bwgid,tsa,map);
3459 /*Configure queue statistics registers*/
3460 ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
3462 /* Check if the PFC is supported */
3463 if(dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
3464 pbsize = (uint16_t) (NIC_RX_BUFFER_SIZE / nb_tcs);
3465 for (i = 0; i < nb_tcs; i++) {
3467 * If the TC count is 8,and the default high_water is 48,
3468 * the low_water is 16 as default.
3470 hw->fc.high_water[i] = (pbsize * 3 ) / 4;
3471 hw->fc.low_water[i] = pbsize / 4;
3472 /* Enable pfc for this TC */
3473 tc = &dcb_config->tc_config[i];
3474 tc->pfc = ixgbe_dcb_pfc_enabled;
3476 ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
3477 if(dcb_config->num_tcs.pfc_tcs == ETH_4_TCS)
3479 ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
3486 * ixgbe_configure_dcb - Configure DCB Hardware
3487 * @dev: pointer to rte_eth_dev
3489 void ixgbe_configure_dcb(struct rte_eth_dev *dev)
3491 struct ixgbe_dcb_config *dcb_cfg =
3492 IXGBE_DEV_PRIVATE_TO_DCB_CFG(dev->data->dev_private);
3493 struct rte_eth_conf *dev_conf = &(dev->data->dev_conf);
3495 PMD_INIT_FUNC_TRACE();
3497 /* check support mq_mode for DCB */
3498 if ((dev_conf->rxmode.mq_mode != ETH_MQ_RX_VMDQ_DCB) &&
3499 (dev_conf->rxmode.mq_mode != ETH_MQ_RX_DCB))
3502 if (dev->data->nb_rx_queues != ETH_DCB_NUM_QUEUES)
3505 /** Configure DCB hardware **/
3506 ixgbe_dcb_hw_configure(dev,dcb_cfg);
3512 * VMDq only support for 10 GbE NIC.
3515 ixgbe_vmdq_rx_hw_configure(struct rte_eth_dev *dev)
3517 struct rte_eth_vmdq_rx_conf *cfg;
3518 struct ixgbe_hw *hw;
3519 enum rte_eth_nb_pools num_pools;
3520 uint32_t mrqc, vt_ctl, vlanctrl;
3524 PMD_INIT_FUNC_TRACE();
3525 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3526 cfg = &dev->data->dev_conf.rx_adv_conf.vmdq_rx_conf;
3527 num_pools = cfg->nb_queue_pools;
3529 ixgbe_rss_disable(dev);
3531 /* MRQC: enable vmdq */
3532 mrqc = IXGBE_MRQC_VMDQEN;
3533 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3535 /* PFVTCTL: turn on virtualisation and set the default pool */
3536 vt_ctl = IXGBE_VT_CTL_VT_ENABLE | IXGBE_VT_CTL_REPLEN;
3537 if (cfg->enable_default_pool)
3538 vt_ctl |= (cfg->default_pool << IXGBE_VT_CTL_POOL_SHIFT);
3540 vt_ctl |= IXGBE_VT_CTL_DIS_DEFPL;
3542 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vt_ctl);
3544 for (i = 0; i < (int)num_pools; i++) {
3545 vmolr = ixgbe_convert_vm_rx_mask_to_val(cfg->rx_mode, vmolr);
3546 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
3549 /* VLNCTRL: enable vlan filtering and allow all vlan tags through */
3550 vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3551 vlanctrl |= IXGBE_VLNCTRL_VFE ; /* enable vlan filters */
3552 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
3554 /* VFTA - enable all vlan filters */
3555 for (i = 0; i < NUM_VFTA_REGISTERS; i++)
3556 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), UINT32_MAX);
3558 /* VFRE: pool enabling for receive - 64 */
3559 IXGBE_WRITE_REG(hw, IXGBE_VFRE(0), UINT32_MAX);
3560 if (num_pools == ETH_64_POOLS)
3561 IXGBE_WRITE_REG(hw, IXGBE_VFRE(1), UINT32_MAX);
3564 * MPSAR - allow pools to read specific mac addresses
3565 * In this case, all pools should be able to read from mac addr 0
3567 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(0), UINT32_MAX);
3568 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(0), UINT32_MAX);
3570 /* PFVLVF, PFVLVFB: set up filters for vlan tags as configured */
3571 for (i = 0; i < cfg->nb_pool_maps; i++) {
3572 /* set vlan id in VF register and set the valid bit */
3573 IXGBE_WRITE_REG(hw, IXGBE_VLVF(i), (IXGBE_VLVF_VIEN | \
3574 (cfg->pool_map[i].vlan_id & IXGBE_RXD_VLAN_ID_MASK)));
3576 * Put the allowed pools in VFB reg. As we only have 16 or 64
3577 * pools, we only need to use the first half of the register
3580 if (((cfg->pool_map[i].pools >> 32) & UINT32_MAX) == 0)
3581 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(i*2), \
3582 (cfg->pool_map[i].pools & UINT32_MAX));
3584 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((i*2+1)), \
3585 ((cfg->pool_map[i].pools >> 32) \
3590 /* PFDMA Tx General Switch Control Enables VMDQ loopback */
3591 if (cfg->enable_loop_back) {
3592 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3593 for (i = 0; i < RTE_IXGBE_VMTXSW_REGISTER_COUNT; i++)
3594 IXGBE_WRITE_REG(hw, IXGBE_VMTXSW(i), UINT32_MAX);
3597 IXGBE_WRITE_FLUSH(hw);
3601 * ixgbe_dcb_config_tx_hw_config - Configure general VMDq TX parameters
3602 * @hw: pointer to hardware structure
3605 ixgbe_vmdq_tx_hw_configure(struct ixgbe_hw *hw)
3610 PMD_INIT_FUNC_TRACE();
3611 /*PF VF Transmit Enable*/
3612 IXGBE_WRITE_REG(hw, IXGBE_VFTE(0), UINT32_MAX);
3613 IXGBE_WRITE_REG(hw, IXGBE_VFTE(1), UINT32_MAX);
3615 /* Disable the Tx desc arbiter so that MTQC can be changed */
3616 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3617 reg |= IXGBE_RTTDCS_ARBDIS;
3618 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3620 reg = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3621 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
3623 /* Disable drop for all queues */
3624 for (q = 0; q < IXGBE_MAX_RX_QUEUE_NUM; q++)
3625 IXGBE_WRITE_REG(hw, IXGBE_QDE,
3626 (IXGBE_QDE_WRITE | (q << IXGBE_QDE_IDX_SHIFT)));
3628 /* Enable the Tx desc arbiter */
3629 reg = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3630 reg &= ~IXGBE_RTTDCS_ARBDIS;
3631 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, reg);
3633 IXGBE_WRITE_FLUSH(hw);
3638 static int __attribute__((cold))
3639 ixgbe_alloc_rx_queue_mbufs(struct ixgbe_rx_queue *rxq)
3641 struct ixgbe_rx_entry *rxe = rxq->sw_ring;
3645 /* Initialize software ring entries */
3646 for (i = 0; i < rxq->nb_rx_desc; i++) {
3647 volatile union ixgbe_adv_rx_desc *rxd;
3648 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mb_pool);
3650 PMD_INIT_LOG(ERR, "RX mbuf alloc failed queue_id=%u",
3651 (unsigned) rxq->queue_id);
3655 rte_mbuf_refcnt_set(mbuf, 1);
3657 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
3659 mbuf->port = rxq->port_id;
3662 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
3663 rxd = &rxq->rx_ring[i];
3664 rxd->read.hdr_addr = dma_addr;
3665 rxd->read.pkt_addr = dma_addr;
3673 ixgbe_config_vf_rss(struct rte_eth_dev *dev)
3675 struct ixgbe_hw *hw;
3678 ixgbe_rss_configure(dev);
3680 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3682 /* MRQC: enable VF RSS */
3683 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
3684 mrqc &= ~IXGBE_MRQC_MRQE_MASK;
3685 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3687 mrqc |= IXGBE_MRQC_VMDQRSS64EN;
3691 mrqc |= IXGBE_MRQC_VMDQRSS32EN;
3695 PMD_INIT_LOG(ERR, "Invalid pool number in IOV mode with VMDQ RSS");
3699 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3705 ixgbe_config_vf_default(struct rte_eth_dev *dev)
3707 struct ixgbe_hw *hw =
3708 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3712 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3717 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3718 IXGBE_MRQC_VMDQRT4TCEN);
3722 IXGBE_WRITE_REG(hw, IXGBE_MRQC,
3723 IXGBE_MRQC_VMDQRT8TCEN);
3727 "invalid pool number in IOV mode");
3734 ixgbe_dev_mq_rx_configure(struct rte_eth_dev *dev)
3736 struct ixgbe_hw *hw =
3737 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3739 if (hw->mac.type == ixgbe_mac_82598EB)
3742 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3744 * SRIOV inactive scheme
3745 * any DCB/RSS w/o VMDq multi-queue setting
3747 switch (dev->data->dev_conf.rxmode.mq_mode) {
3749 ixgbe_rss_configure(dev);
3752 case ETH_MQ_RX_VMDQ_DCB:
3753 ixgbe_vmdq_dcb_configure(dev);
3756 case ETH_MQ_RX_VMDQ_ONLY:
3757 ixgbe_vmdq_rx_hw_configure(dev);
3760 case ETH_MQ_RX_NONE:
3761 /* if mq_mode is none, disable rss mode.*/
3762 default: ixgbe_rss_disable(dev);
3766 * SRIOV active scheme
3767 * Support RSS together with VMDq & SRIOV
3769 switch (dev->data->dev_conf.rxmode.mq_mode) {
3771 case ETH_MQ_RX_VMDQ_RSS:
3772 ixgbe_config_vf_rss(dev);
3775 /* FIXME if support DCB/RSS together with VMDq & SRIOV */
3776 case ETH_MQ_RX_VMDQ_DCB:
3777 case ETH_MQ_RX_VMDQ_DCB_RSS:
3779 "Could not support DCB with VMDq & SRIOV");
3782 ixgbe_config_vf_default(dev);
3791 ixgbe_dev_mq_tx_configure(struct rte_eth_dev *dev)
3793 struct ixgbe_hw *hw =
3794 IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3798 if (hw->mac.type == ixgbe_mac_82598EB)
3801 /* disable arbiter before setting MTQC */
3802 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3803 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3804 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3806 if (RTE_ETH_DEV_SRIOV(dev).active == 0) {
3808 * SRIOV inactive scheme
3809 * any DCB w/o VMDq multi-queue setting
3811 if (dev->data->dev_conf.txmode.mq_mode == ETH_MQ_TX_VMDQ_ONLY)
3812 ixgbe_vmdq_tx_hw_configure(hw);
3814 mtqc = IXGBE_MTQC_64Q_1PB;
3815 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3818 switch (RTE_ETH_DEV_SRIOV(dev).active) {
3821 * SRIOV active scheme
3822 * FIXME if support DCB together with VMDq & SRIOV
3825 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF;
3828 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_32VF;
3831 mtqc = IXGBE_MTQC_VT_ENA | IXGBE_MTQC_RT_ENA |
3835 mtqc = IXGBE_MTQC_64Q_1PB;
3836 PMD_INIT_LOG(ERR, "invalid pool number in IOV mode");
3838 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3841 /* re-enable arbiter */
3842 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3843 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3849 * ixgbe_get_rscctl_maxdesc - Calculate the RSCCTL[n].MAXDESC for PF
3851 * Return the RSCCTL[n].MAXDESC for 82599 and x540 PF devices according to the
3852 * spec rev. 3.0 chapter 8.2.3.8.13.
3854 * @pool Memory pool of the Rx queue
3856 static inline uint32_t
3857 ixgbe_get_rscctl_maxdesc(struct rte_mempool *pool)
3859 struct rte_pktmbuf_pool_private *mp_priv = rte_mempool_get_priv(pool);
3861 /* MAXDESC * SRRCTL.BSIZEPKT must not exceed 64 KB minus one */
3864 (mp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM);
3867 return IXGBE_RSCCTL_MAXDESC_16;
3868 else if (maxdesc >= 8)
3869 return IXGBE_RSCCTL_MAXDESC_8;
3870 else if (maxdesc >= 4)
3871 return IXGBE_RSCCTL_MAXDESC_4;
3873 return IXGBE_RSCCTL_MAXDESC_1;
3877 * ixgbe_set_ivar - Setup the correct IVAR register for a particular MSIX
3880 * (Taken from FreeBSD tree)
3881 * (yes this is all very magic and confusing :)
3884 * @entry the register array entry
3885 * @vector the MSIX vector for this queue
3889 ixgbe_set_ivar(struct rte_eth_dev *dev, u8 entry, u8 vector, s8 type)
3891 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3894 vector |= IXGBE_IVAR_ALLOC_VAL;
3896 switch (hw->mac.type) {
3898 case ixgbe_mac_82598EB:
3900 entry = IXGBE_IVAR_OTHER_CAUSES_INDEX;
3902 entry += (type * 64);
3903 index = (entry >> 2) & 0x1F;
3904 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
3905 ivar &= ~(0xFF << (8 * (entry & 0x3)));
3906 ivar |= (vector << (8 * (entry & 0x3)));
3907 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
3910 case ixgbe_mac_82599EB:
3911 case ixgbe_mac_X540:
3912 if (type == -1) { /* MISC IVAR */
3913 index = (entry & 1) * 8;
3914 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR_MISC);
3915 ivar &= ~(0xFF << index);
3916 ivar |= (vector << index);
3917 IXGBE_WRITE_REG(hw, IXGBE_IVAR_MISC, ivar);
3918 } else { /* RX/TX IVARS */
3919 index = (16 * (entry & 1)) + (8 * type);
3920 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(entry >> 1));
3921 ivar &= ~(0xFF << index);
3922 ivar |= (vector << index);
3923 IXGBE_WRITE_REG(hw, IXGBE_IVAR(entry >> 1), ivar);
3933 void __attribute__((cold))
3934 ixgbe_set_rx_function(struct rte_eth_dev *dev)
3936 uint16_t i, rx_using_sse;
3937 struct ixgbe_adapter *adapter =
3938 (struct ixgbe_adapter *)dev->data->dev_private;
3941 * In order to allow Vector Rx there are a few configuration
3942 * conditions to be met and Rx Bulk Allocation should be allowed.
3944 if (ixgbe_rx_vec_dev_conf_condition_check(dev) ||
3945 !adapter->rx_bulk_alloc_allowed) {
3946 PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet Vector Rx "
3947 "preconditions or RTE_IXGBE_INC_VECTOR is "
3949 dev->data->port_id);
3951 adapter->rx_vec_allowed = false;
3955 * Initialize the appropriate LRO callback.
3957 * If all queues satisfy the bulk allocation preconditions
3958 * (hw->rx_bulk_alloc_allowed is TRUE) then we may use bulk allocation.
3959 * Otherwise use a single allocation version.
3961 if (dev->data->lro) {
3962 if (adapter->rx_bulk_alloc_allowed) {
3963 PMD_INIT_LOG(INFO, "LRO is requested. Using a bulk "
3964 "allocation version");
3965 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3967 PMD_INIT_LOG(INFO, "LRO is requested. Using a single "
3968 "allocation version");
3969 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3971 } else if (dev->data->scattered_rx) {
3973 * Set the non-LRO scattered callback: there are Vector and
3974 * single allocation versions.
3976 if (adapter->rx_vec_allowed) {
3977 PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3978 "callback (port=%d).",
3979 dev->data->port_id);
3981 dev->rx_pkt_burst = ixgbe_recv_scattered_pkts_vec;
3982 } else if (adapter->rx_bulk_alloc_allowed) {
3983 PMD_INIT_LOG(INFO, "Using a Scattered with bulk "
3984 "allocation callback (port=%d).",
3985 dev->data->port_id);
3986 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_bulk_alloc;
3988 PMD_INIT_LOG(DEBUG, "Using Regualr (non-vector, "
3989 "single allocation) "
3990 "Scattered Rx callback "
3992 dev->data->port_id);
3994 dev->rx_pkt_burst = ixgbe_recv_pkts_lro_single_alloc;
3997 * Below we set "simple" callbacks according to port/queues parameters.
3998 * If parameters allow we are going to choose between the following
4002 * - Single buffer allocation (the simplest one)
4004 } else if (adapter->rx_vec_allowed) {
4005 PMD_INIT_LOG(INFO, "Vector rx enabled, please make sure RX "
4006 "burst size no less than 32.");
4008 dev->rx_pkt_burst = ixgbe_recv_pkts_vec;
4009 } else if (adapter->rx_bulk_alloc_allowed) {
4010 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
4011 "satisfied. Rx Burst Bulk Alloc function "
4012 "will be used on port=%d.",
4013 dev->data->port_id);
4015 dev->rx_pkt_burst = ixgbe_recv_pkts_bulk_alloc;
4017 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
4018 "satisfied, or Scattered Rx is requested, "
4019 "or RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC "
4020 "is not enabled (port=%d).",
4021 dev->data->port_id);
4023 dev->rx_pkt_burst = ixgbe_recv_pkts;
4026 /* Propagate information about RX function choice through all queues. */
4029 (dev->rx_pkt_burst == ixgbe_recv_scattered_pkts_vec ||
4030 dev->rx_pkt_burst == ixgbe_recv_pkts_vec);
4032 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4033 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4034 rxq->rx_using_sse = rx_using_sse;
4039 * ixgbe_set_rsc - configure RSC related port HW registers
4041 * Configures the port's RSC related registers according to the 4.6.7.2 chapter
4042 * of 82599 Spec (x540 configuration is virtually the same).
4046 * Returns 0 in case of success or a non-zero error code
4049 ixgbe_set_rsc(struct rte_eth_dev *dev)
4051 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4052 struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4053 struct rte_eth_dev_info dev_info = { 0 };
4054 bool rsc_capable = false;
4059 dev->dev_ops->dev_infos_get(dev, &dev_info);
4060 if (dev_info.rx_offload_capa & DEV_RX_OFFLOAD_TCP_LRO)
4063 if (!rsc_capable && rx_conf->enable_lro) {
4064 PMD_INIT_LOG(CRIT, "LRO is requested on HW that doesn't "
4069 /* RSC global configuration (chapter 4.6.7.2.1 of 82599 Spec) */
4071 if (!rx_conf->hw_strip_crc && rx_conf->enable_lro) {
4073 * According to chapter of 4.6.7.2.1 of the Spec Rev.
4074 * 3.0 RSC configuration requires HW CRC stripping being
4075 * enabled. If user requested both HW CRC stripping off
4076 * and RSC on - return an error.
4078 PMD_INIT_LOG(CRIT, "LRO can't be enabled when HW CRC "
4083 /* RFCTL configuration */
4085 uint32_t rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4086 if (rx_conf->enable_lro)
4088 * Since NFS packets coalescing is not supported - clear
4089 * RFCTL.NFSW_DIS and RFCTL.NFSR_DIS when RSC is
4092 rfctl &= ~(IXGBE_RFCTL_RSC_DIS | IXGBE_RFCTL_NFSW_DIS |
4093 IXGBE_RFCTL_NFSR_DIS);
4095 rfctl |= IXGBE_RFCTL_RSC_DIS;
4097 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4100 /* If LRO hasn't been requested - we are done here. */
4101 if (!rx_conf->enable_lro)
4104 /* Set RDRXCTL.RSCACKC bit */
4105 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4106 rdrxctl |= IXGBE_RDRXCTL_RSCACKC;
4107 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4109 /* Per-queue RSC configuration (chapter 4.6.7.2.2 of 82599 Spec) */
4110 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4111 struct ixgbe_rx_queue *rxq = dev->data->rx_queues[i];
4113 IXGBE_READ_REG(hw, IXGBE_SRRCTL(rxq->reg_idx));
4115 IXGBE_READ_REG(hw, IXGBE_RSCCTL(rxq->reg_idx));
4117 IXGBE_READ_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx));
4119 IXGBE_READ_REG(hw, IXGBE_EITR(rxq->reg_idx));
4122 * ixgbe PMD doesn't support header-split at the moment.
4124 * Following the 4.6.7.2.1 chapter of the 82599/x540
4125 * Spec if RSC is enabled the SRRCTL[n].BSIZEHEADER
4126 * should be configured even if header split is not
4127 * enabled. We will configure it 128 bytes following the
4128 * recommendation in the spec.
4130 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
4131 srrctl |= (128 << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4132 IXGBE_SRRCTL_BSIZEHDR_MASK;
4135 * TODO: Consider setting the Receive Descriptor Minimum
4136 * Threshold Size for an RSC case. This is not an obviously
4137 * beneficiary option but the one worth considering...
4140 rscctl |= IXGBE_RSCCTL_RSCEN;
4141 rscctl |= ixgbe_get_rscctl_maxdesc(rxq->mb_pool);
4142 psrtype |= IXGBE_PSRTYPE_TCPHDR;
4145 * RSC: Set ITR interval corresponding to 2K ints/s.
4147 * Full-sized RSC aggregations for a 10Gb/s link will
4148 * arrive at about 20K aggregation/s rate.
4150 * 2K inst/s rate will make only 10% of the
4151 * aggregations to be closed due to the interrupt timer
4152 * expiration for a streaming at wire-speed case.
4154 * For a sparse streaming case this setting will yield
4155 * at most 500us latency for a single RSC aggregation.
4157 eitr &= ~IXGBE_EITR_ITR_INT_MASK;
4158 eitr |= IXGBE_EITR_INTERVAL_US(500) | IXGBE_EITR_CNT_WDIS;
4160 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4161 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(rxq->reg_idx), rscctl);
4162 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4163 IXGBE_WRITE_REG(hw, IXGBE_EITR(rxq->reg_idx), eitr);
4166 * RSC requires the mapping of the queue to the
4169 ixgbe_set_ivar(dev, rxq->reg_idx, i, 0);
4174 PMD_INIT_LOG(INFO, "enabling LRO mode");
4180 * Initializes Receive Unit.
4182 int __attribute__((cold))
4183 ixgbe_dev_rx_init(struct rte_eth_dev *dev)
4185 struct ixgbe_hw *hw;
4186 struct ixgbe_rx_queue *rxq;
4197 struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
4200 PMD_INIT_FUNC_TRACE();
4201 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4204 * Make sure receives are disabled while setting
4205 * up the RX context (registers, descriptor rings, etc.).
4207 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4208 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4210 /* Enable receipt of broadcasted frames */
4211 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4212 fctrl |= IXGBE_FCTRL_BAM;
4213 fctrl |= IXGBE_FCTRL_DPF;
4214 fctrl |= IXGBE_FCTRL_PMCF;
4215 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4218 * Configure CRC stripping, if any.
4220 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4221 if (rx_conf->hw_strip_crc)
4222 hlreg0 |= IXGBE_HLREG0_RXCRCSTRP;
4224 hlreg0 &= ~IXGBE_HLREG0_RXCRCSTRP;
4227 * Configure jumbo frame support, if any.
4229 if (rx_conf->jumbo_frame == 1) {
4230 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4231 maxfrs = IXGBE_READ_REG(hw, IXGBE_MAXFRS);
4232 maxfrs &= 0x0000FFFF;
4233 maxfrs |= (rx_conf->max_rx_pkt_len << 16);
4234 IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, maxfrs);
4236 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
4239 * If loopback mode is configured for 82599, set LPBK bit.
4241 if (hw->mac.type == ixgbe_mac_82599EB &&
4242 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4243 hlreg0 |= IXGBE_HLREG0_LPBK;
4245 hlreg0 &= ~IXGBE_HLREG0_LPBK;
4247 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4249 /* Setup RX queues */
4250 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4251 rxq = dev->data->rx_queues[i];
4254 * Reset crc_len in case it was changed after queue setup by a
4255 * call to configure.
4257 rxq->crc_len = rx_conf->hw_strip_crc ? 0 : ETHER_CRC_LEN;
4259 /* Setup the Base and Length of the Rx Descriptor Rings */
4260 bus_addr = rxq->rx_ring_phys_addr;
4261 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(rxq->reg_idx),
4262 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4263 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(rxq->reg_idx),
4264 (uint32_t)(bus_addr >> 32));
4265 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(rxq->reg_idx),
4266 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4267 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4268 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), 0);
4270 /* Configure the SRRCTL register */
4271 #ifdef RTE_HEADER_SPLIT_ENABLE
4273 * Configure Header Split
4275 if (rx_conf->header_split) {
4276 if (hw->mac.type == ixgbe_mac_82599EB) {
4277 /* Must setup the PSRTYPE register */
4279 psrtype = IXGBE_PSRTYPE_TCPHDR |
4280 IXGBE_PSRTYPE_UDPHDR |
4281 IXGBE_PSRTYPE_IPV4HDR |
4282 IXGBE_PSRTYPE_IPV6HDR;
4283 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(rxq->reg_idx), psrtype);
4285 srrctl = ((rx_conf->split_hdr_size <<
4286 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4287 IXGBE_SRRCTL_BSIZEHDR_MASK);
4288 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4291 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4293 /* Set if packets are dropped when no descriptors available */
4295 srrctl |= IXGBE_SRRCTL_DROP_EN;
4298 * Configure the RX buffer size in the BSIZEPACKET field of
4299 * the SRRCTL register of the queue.
4300 * The value is in 1 KB resolution. Valid values can be from
4303 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4304 RTE_PKTMBUF_HEADROOM);
4305 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4306 IXGBE_SRRCTL_BSIZEPKT_MASK);
4308 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(rxq->reg_idx), srrctl);
4310 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4311 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4313 /* It adds dual VLAN length for supporting dual VLAN */
4314 if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4315 2 * IXGBE_VLAN_TAG_SIZE > buf_size)
4316 dev->data->scattered_rx = 1;
4319 if (rx_conf->enable_scatter)
4320 dev->data->scattered_rx = 1;
4323 * Device configured with multiple RX queues.
4325 ixgbe_dev_mq_rx_configure(dev);
4328 * Setup the Checksum Register.
4329 * Disable Full-Packet Checksum which is mutually exclusive with RSS.
4330 * Enable IP/L4 checkum computation by hardware if requested to do so.
4332 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
4333 rxcsum |= IXGBE_RXCSUM_PCSD;
4334 if (rx_conf->hw_ip_checksum)
4335 rxcsum |= IXGBE_RXCSUM_IPPCSE;
4337 rxcsum &= ~IXGBE_RXCSUM_IPPCSE;
4339 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
4341 if (hw->mac.type == ixgbe_mac_82599EB ||
4342 hw->mac.type == ixgbe_mac_X540) {
4343 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4344 if (rx_conf->hw_strip_crc)
4345 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4347 rdrxctl &= ~IXGBE_RDRXCTL_CRCSTRIP;
4348 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4349 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4352 rc = ixgbe_set_rsc(dev);
4356 ixgbe_set_rx_function(dev);
4362 * Initializes Transmit Unit.
4364 void __attribute__((cold))
4365 ixgbe_dev_tx_init(struct rte_eth_dev *dev)
4367 struct ixgbe_hw *hw;
4368 struct ixgbe_tx_queue *txq;
4374 PMD_INIT_FUNC_TRACE();
4375 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4377 /* Enable TX CRC (checksum offload requirement) and hw padding
4378 * (TSO requirement) */
4379 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4380 hlreg0 |= (IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_TXPADEN);
4381 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4383 /* Setup the Base and Length of the Tx Descriptor Rings */
4384 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4385 txq = dev->data->tx_queues[i];
4387 bus_addr = txq->tx_ring_phys_addr;
4388 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(txq->reg_idx),
4389 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4390 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(txq->reg_idx),
4391 (uint32_t)(bus_addr >> 32));
4392 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(txq->reg_idx),
4393 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4394 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4395 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4396 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4399 * Disable Tx Head Writeback RO bit, since this hoses
4400 * bookkeeping if things aren't delivered in order.
4402 switch (hw->mac.type) {
4403 case ixgbe_mac_82598EB:
4404 txctrl = IXGBE_READ_REG(hw,
4405 IXGBE_DCA_TXCTRL(txq->reg_idx));
4406 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4407 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(txq->reg_idx),
4411 case ixgbe_mac_82599EB:
4412 case ixgbe_mac_X540:
4413 case ixgbe_mac_X550:
4414 case ixgbe_mac_X550EM_x:
4416 txctrl = IXGBE_READ_REG(hw,
4417 IXGBE_DCA_TXCTRL_82599(txq->reg_idx));
4418 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4419 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(txq->reg_idx),
4425 /* Device configured with multiple TX queues. */
4426 ixgbe_dev_mq_tx_configure(dev);
4430 * Set up link for 82599 loopback mode Tx->Rx.
4432 static inline void __attribute__((cold))
4433 ixgbe_setup_loopback_link_82599(struct ixgbe_hw *hw)
4435 PMD_INIT_FUNC_TRACE();
4437 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
4438 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM) !=
4440 PMD_INIT_LOG(ERR, "Could not enable loopback mode");
4449 IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU);
4450 ixgbe_reset_pipeline_82599(hw);
4452 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
4458 * Start Transmit and Receive Units.
4460 int __attribute__((cold))
4461 ixgbe_dev_rxtx_start(struct rte_eth_dev *dev)
4463 struct ixgbe_hw *hw;
4464 struct ixgbe_tx_queue *txq;
4465 struct ixgbe_rx_queue *rxq;
4472 PMD_INIT_FUNC_TRACE();
4473 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4475 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4476 txq = dev->data->tx_queues[i];
4477 /* Setup Transmit Threshold Registers */
4478 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4479 txdctl |= txq->pthresh & 0x7F;
4480 txdctl |= ((txq->hthresh & 0x7F) << 8);
4481 txdctl |= ((txq->wthresh & 0x7F) << 16);
4482 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4485 if (hw->mac.type != ixgbe_mac_82598EB) {
4486 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
4487 dmatxctl |= IXGBE_DMATXCTL_TE;
4488 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
4491 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4492 txq = dev->data->tx_queues[i];
4493 if (!txq->tx_deferred_start) {
4494 ret = ixgbe_dev_tx_queue_start(dev, i);
4500 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4501 rxq = dev->data->rx_queues[i];
4502 if (!rxq->rx_deferred_start) {
4503 ret = ixgbe_dev_rx_queue_start(dev, i);
4509 /* Enable Receive engine */
4510 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4511 if (hw->mac.type == ixgbe_mac_82598EB)
4512 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4513 rxctrl |= IXGBE_RXCTRL_RXEN;
4514 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4516 /* If loopback mode is enabled for 82599, set up the link accordingly */
4517 if (hw->mac.type == ixgbe_mac_82599EB &&
4518 dev->data->dev_conf.lpbk_mode == IXGBE_LPBK_82599_TX_RX)
4519 ixgbe_setup_loopback_link_82599(hw);
4525 * Start Receive Units for specified queue.
4527 int __attribute__((cold))
4528 ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4530 struct ixgbe_hw *hw;
4531 struct ixgbe_rx_queue *rxq;
4535 PMD_INIT_FUNC_TRACE();
4536 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4538 if (rx_queue_id < dev->data->nb_rx_queues) {
4539 rxq = dev->data->rx_queues[rx_queue_id];
4541 /* Allocate buffers for descriptor rings */
4542 if (ixgbe_alloc_rx_queue_mbufs(rxq) != 0) {
4543 PMD_INIT_LOG(ERR, "Could not alloc mbuf for queue:%d",
4547 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4548 rxdctl |= IXGBE_RXDCTL_ENABLE;
4549 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4551 /* Wait until RX Enable ready */
4552 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4555 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4556 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4558 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d",
4561 IXGBE_WRITE_REG(hw, IXGBE_RDH(rxq->reg_idx), 0);
4562 IXGBE_WRITE_REG(hw, IXGBE_RDT(rxq->reg_idx), rxq->nb_rx_desc - 1);
4570 * Stop Receive Units for specified queue.
4572 int __attribute__((cold))
4573 ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
4575 struct ixgbe_hw *hw;
4576 struct ixgbe_adapter *adapter =
4577 (struct ixgbe_adapter *)dev->data->dev_private;
4578 struct ixgbe_rx_queue *rxq;
4582 PMD_INIT_FUNC_TRACE();
4583 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4585 if (rx_queue_id < dev->data->nb_rx_queues) {
4586 rxq = dev->data->rx_queues[rx_queue_id];
4588 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4589 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4590 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rxq->reg_idx), rxdctl);
4592 /* Wait until RX Enable ready */
4593 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4596 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rxq->reg_idx));
4597 } while (--poll_ms && (rxdctl | IXGBE_RXDCTL_ENABLE));
4599 PMD_INIT_LOG(ERR, "Could not disable Rx Queue %d",
4602 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4604 ixgbe_rx_queue_release_mbufs(rxq);
4605 ixgbe_reset_rx_queue(adapter, rxq);
4614 * Start Transmit Units for specified queue.
4616 int __attribute__((cold))
4617 ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4619 struct ixgbe_hw *hw;
4620 struct ixgbe_tx_queue *txq;
4624 PMD_INIT_FUNC_TRACE();
4625 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4627 if (tx_queue_id < dev->data->nb_tx_queues) {
4628 txq = dev->data->tx_queues[tx_queue_id];
4629 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4630 txdctl |= IXGBE_TXDCTL_ENABLE;
4631 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4633 /* Wait until TX Enable ready */
4634 if (hw->mac.type == ixgbe_mac_82599EB) {
4635 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4638 txdctl = IXGBE_READ_REG(hw,
4639 IXGBE_TXDCTL(txq->reg_idx));
4640 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4642 PMD_INIT_LOG(ERR, "Could not enable "
4643 "Tx Queue %d", tx_queue_id);
4646 IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0);
4647 IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0);
4655 * Stop Transmit Units for specified queue.
4657 int __attribute__((cold))
4658 ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
4660 struct ixgbe_hw *hw;
4661 struct ixgbe_tx_queue *txq;
4663 uint32_t txtdh, txtdt;
4666 PMD_INIT_FUNC_TRACE();
4667 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4669 if (tx_queue_id < dev->data->nb_tx_queues) {
4670 txq = dev->data->tx_queues[tx_queue_id];
4672 /* Wait until TX queue is empty */
4673 if (hw->mac.type == ixgbe_mac_82599EB) {
4674 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4676 rte_delay_us(RTE_IXGBE_WAIT_100_US);
4677 txtdh = IXGBE_READ_REG(hw,
4678 IXGBE_TDH(txq->reg_idx));
4679 txtdt = IXGBE_READ_REG(hw,
4680 IXGBE_TDT(txq->reg_idx));
4681 } while (--poll_ms && (txtdh != txtdt));
4683 PMD_INIT_LOG(ERR, "Tx Queue %d is not empty "
4684 "when stopping.", tx_queue_id);
4687 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx));
4688 txdctl &= ~IXGBE_TXDCTL_ENABLE;
4689 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl);
4691 /* Wait until TX Enable ready */
4692 if (hw->mac.type == ixgbe_mac_82599EB) {
4693 poll_ms = RTE_IXGBE_REGISTER_POLL_WAIT_10_MS;
4696 txdctl = IXGBE_READ_REG(hw,
4697 IXGBE_TXDCTL(txq->reg_idx));
4698 } while (--poll_ms && (txdctl | IXGBE_TXDCTL_ENABLE));
4700 PMD_INIT_LOG(ERR, "Could not disable "
4701 "Tx Queue %d", tx_queue_id);
4704 if (txq->ops != NULL) {
4705 txq->ops->release_mbufs(txq);
4706 txq->ops->reset(txq);
4715 * [VF] Initializes Receive Unit.
4717 int __attribute__((cold))
4718 ixgbevf_dev_rx_init(struct rte_eth_dev *dev)
4720 struct ixgbe_hw *hw;
4721 struct ixgbe_rx_queue *rxq;
4723 uint32_t srrctl, psrtype = 0;
4728 PMD_INIT_FUNC_TRACE();
4729 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731 if (rte_is_power_of_2(dev->data->nb_rx_queues) == 0) {
4732 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4733 "it should be power of 2");
4737 if (dev->data->nb_rx_queues > hw->mac.max_rx_queues) {
4738 PMD_INIT_LOG(ERR, "The number of Rx queue invalid, "
4739 "it should be equal to or less than %d",
4740 hw->mac.max_rx_queues);
4745 * When the VF driver issues a IXGBE_VF_RESET request, the PF driver
4746 * disables the VF receipt of packets if the PF MTU is > 1500.
4747 * This is done to deal with 82599 limitations that imposes
4748 * the PF and all VFs to share the same MTU.
4749 * Then, the PF driver enables again the VF receipt of packet when
4750 * the VF driver issues a IXGBE_VF_SET_LPE request.
4751 * In the meantime, the VF device cannot be used, even if the VF driver
4752 * and the Guest VM network stack are ready to accept packets with a
4753 * size up to the PF MTU.
4754 * As a work-around to this PF behaviour, force the call to
4755 * ixgbevf_rlpml_set_vf even if jumbo frames are not used. This way,
4756 * VF packets received can work in all cases.
4758 ixgbevf_rlpml_set_vf(hw,
4759 (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len);
4761 /* Setup RX queues */
4762 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4763 rxq = dev->data->rx_queues[i];
4765 /* Allocate buffers for descriptor rings */
4766 ret = ixgbe_alloc_rx_queue_mbufs(rxq);
4770 /* Setup the Base and Length of the Rx Descriptor Rings */
4771 bus_addr = rxq->rx_ring_phys_addr;
4773 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(i),
4774 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4775 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(i),
4776 (uint32_t)(bus_addr >> 32));
4777 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(i),
4778 rxq->nb_rx_desc * sizeof(union ixgbe_adv_rx_desc));
4779 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(i), 0);
4780 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), 0);
4783 /* Configure the SRRCTL register */
4784 #ifdef RTE_HEADER_SPLIT_ENABLE
4786 * Configure Header Split
4788 if (dev->data->dev_conf.rxmode.header_split) {
4789 srrctl = ((dev->data->dev_conf.rxmode.split_hdr_size <<
4790 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
4791 IXGBE_SRRCTL_BSIZEHDR_MASK);
4792 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
4795 srrctl = IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
4797 /* Set if packets are dropped when no descriptors available */
4799 srrctl |= IXGBE_SRRCTL_DROP_EN;
4802 * Configure the RX buffer size in the BSIZEPACKET field of
4803 * the SRRCTL register of the queue.
4804 * The value is in 1 KB resolution. Valid values can be from
4807 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
4808 RTE_PKTMBUF_HEADROOM);
4809 srrctl |= ((buf_size >> IXGBE_SRRCTL_BSIZEPKT_SHIFT) &
4810 IXGBE_SRRCTL_BSIZEPKT_MASK);
4813 * VF modification to write virtual function SRRCTL register
4815 IXGBE_WRITE_REG(hw, IXGBE_VFSRRCTL(i), srrctl);
4817 buf_size = (uint16_t) ((srrctl & IXGBE_SRRCTL_BSIZEPKT_MASK) <<
4818 IXGBE_SRRCTL_BSIZEPKT_SHIFT);
4820 if (dev->data->dev_conf.rxmode.enable_scatter ||
4821 /* It adds dual VLAN length for supporting dual VLAN */
4822 (dev->data->dev_conf.rxmode.max_rx_pkt_len +
4823 2 * IXGBE_VLAN_TAG_SIZE) > buf_size) {
4824 if (!dev->data->scattered_rx)
4825 PMD_INIT_LOG(DEBUG, "forcing scatter mode");
4826 dev->data->scattered_rx = 1;
4830 #ifdef RTE_HEADER_SPLIT_ENABLE
4831 if (dev->data->dev_conf.rxmode.header_split)
4832 /* Must setup the PSRTYPE register */
4833 psrtype = IXGBE_PSRTYPE_TCPHDR |
4834 IXGBE_PSRTYPE_UDPHDR |
4835 IXGBE_PSRTYPE_IPV4HDR |
4836 IXGBE_PSRTYPE_IPV6HDR;
4839 /* Set RQPL for VF RSS according to max Rx queue */
4840 psrtype |= (dev->data->nb_rx_queues >> 1) <<
4841 IXGBE_PSRTYPE_RQPL_SHIFT;
4842 IXGBE_WRITE_REG(hw, IXGBE_VFPSRTYPE, psrtype);
4844 ixgbe_set_rx_function(dev);
4850 * [VF] Initializes Transmit Unit.
4852 void __attribute__((cold))
4853 ixgbevf_dev_tx_init(struct rte_eth_dev *dev)
4855 struct ixgbe_hw *hw;
4856 struct ixgbe_tx_queue *txq;
4861 PMD_INIT_FUNC_TRACE();
4862 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4864 /* Setup the Base and Length of the Tx Descriptor Rings */
4865 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4866 txq = dev->data->tx_queues[i];
4867 bus_addr = txq->tx_ring_phys_addr;
4868 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(i),
4869 (uint32_t)(bus_addr & 0x00000000ffffffffULL));
4870 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(i),
4871 (uint32_t)(bus_addr >> 32));
4872 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(i),
4873 txq->nb_tx_desc * sizeof(union ixgbe_adv_tx_desc));
4874 /* Setup the HW Tx Head and TX Tail descriptor pointers */
4875 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(i), 0);
4876 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(i), 0);
4879 * Disable Tx Head Writeback RO bit, since this hoses
4880 * bookkeeping if things aren't delivered in order.
4882 txctrl = IXGBE_READ_REG(hw,
4883 IXGBE_VFDCA_TXCTRL(i));
4884 txctrl &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4885 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(i),
4891 * [VF] Start Transmit and Receive Units.
4893 void __attribute__((cold))
4894 ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev)
4896 struct ixgbe_hw *hw;
4897 struct ixgbe_tx_queue *txq;
4898 struct ixgbe_rx_queue *rxq;
4904 PMD_INIT_FUNC_TRACE();
4905 hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4907 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4908 txq = dev->data->tx_queues[i];
4909 /* Setup Transmit Threshold Registers */
4910 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4911 txdctl |= txq->pthresh & 0x7F;
4912 txdctl |= ((txq->hthresh & 0x7F) << 8);
4913 txdctl |= ((txq->wthresh & 0x7F) << 16);
4914 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4917 for (i = 0; i < dev->data->nb_tx_queues; i++) {
4919 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4920 txdctl |= IXGBE_TXDCTL_ENABLE;
4921 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(i), txdctl);
4924 /* Wait until TX Enable ready */
4927 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(i));
4928 } while (--poll_ms && !(txdctl & IXGBE_TXDCTL_ENABLE));
4930 PMD_INIT_LOG(ERR, "Could not enable Tx Queue %d", i);
4932 for (i = 0; i < dev->data->nb_rx_queues; i++) {
4934 rxq = dev->data->rx_queues[i];
4936 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4937 rxdctl |= IXGBE_RXDCTL_ENABLE;
4938 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(i), rxdctl);
4940 /* Wait until RX Enable ready */
4944 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(i));
4945 } while (--poll_ms && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4947 PMD_INIT_LOG(ERR, "Could not enable Rx Queue %d", i);
4949 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(i), rxq->nb_rx_desc - 1);
4954 /* Stubs needed for linkage when CONFIG_RTE_IXGBE_INC_VECTOR is set to 'n' */
4955 int __attribute__((weak))
4956 ixgbe_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
4961 uint16_t __attribute__((weak))
4962 ixgbe_recv_pkts_vec(
4963 void __rte_unused *rx_queue,
4964 struct rte_mbuf __rte_unused **rx_pkts,
4965 uint16_t __rte_unused nb_pkts)
4970 uint16_t __attribute__((weak))
4971 ixgbe_recv_scattered_pkts_vec(
4972 void __rte_unused *rx_queue,
4973 struct rte_mbuf __rte_unused **rx_pkts,
4974 uint16_t __rte_unused nb_pkts)
4979 int __attribute__((weak))
4980 ixgbe_rxq_vec_setup(struct ixgbe_rx_queue __rte_unused *rxq)