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34 #ifndef _LIO_HW_DEFS_H_
35 #define _LIO_HW_DEFS_H_
39 #ifndef PCI_VENDOR_ID_CAVIUM
40 #define PCI_VENDOR_ID_CAVIUM 0x177D
43 #define LIO_CN23XX_VF_VID 0x9712
45 /* CN23xx subsystem device ids */
46 #define PCI_SUBSYS_DEV_ID_CN2350_210 0x0004
47 #define PCI_SUBSYS_DEV_ID_CN2360_210 0x0005
48 #define PCI_SUBSYS_DEV_ID_CN2360_225 0x0006
49 #define PCI_SUBSYS_DEV_ID_CN2350_225 0x0007
50 #define PCI_SUBSYS_DEV_ID_CN2350_210SVPN3 0x0008
51 #define PCI_SUBSYS_DEV_ID_CN2360_210SVPN3 0x0009
52 #define PCI_SUBSYS_DEV_ID_CN2350_210SVPT 0x000a
53 #define PCI_SUBSYS_DEV_ID_CN2360_210SVPT 0x000b
55 /* --------------------------CONFIG VALUES------------------------ */
57 /* CN23xx IQ configuration macros */
58 #define CN23XX_MAX_RINGS_PER_PF 64
59 #define CN23XX_MAX_RINGS_PER_VF 8
61 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
62 #define CN23XX_MAX_IQ_DESCRIPTORS 512
63 #define CN23XX_MIN_IQ_DESCRIPTORS 128
65 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
66 #define CN23XX_MAX_OQ_DESCRIPTORS 512
67 #define CN23XX_MIN_OQ_DESCRIPTORS 128
68 #define CN23XX_OQ_BUF_SIZE 1536
70 #define CN23XX_OQ_REFIL_THRESHOLD 16
72 #define CN23XX_DEFAULT_NUM_PORTS 1
74 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
76 /* common OCTEON configuration macros */
77 #define OCTEON_64BYTE_INSTR 64
78 #define OCTEON_OQ_INFOPTR_MODE 1
80 /* Max IOQs per LIO Link */
81 #define LIO_MAX_IOQS_PER_IF 64
87 #define LIO_23XX_NAME "23xx"
89 #define LIO_DEV_RUNNING 0xc
91 #define LIO_OQ_REFILL_THRESHOLD_CFG(cfg) \
92 ((cfg)->default_config->oq.refill_threshold)
93 #define LIO_NUM_DEF_TX_DESCS_CFG(cfg) \
94 ((cfg)->default_config->num_def_tx_descs)
96 #define LIO_IQ_INSTR_TYPE(cfg) ((cfg)->default_config->iq.instr_type)
98 /* The following config values are fixed and should not be modified. */
100 /* Maximum number of Instruction queues */
101 #define LIO_MAX_INSTR_QUEUES(lio_dev) CN23XX_MAX_RINGS_PER_VF
103 #define LIO_MAX_POSSIBLE_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
104 #define LIO_MAX_POSSIBLE_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
106 #define LIO_DEVICE_NAME_LEN 32
107 #define LIO_BASE_MAJOR_VERSION 1
108 #define LIO_BASE_MINOR_VERSION 5
109 #define LIO_BASE_MICRO_VERSION 1
111 #define LIO_FW_VERSION_LENGTH 32
113 #define LIO_VF_TRUST_MIN_VERSION "1.7.1"
115 /** Tag types used by Octeon cores in its work. */
116 enum octeon_tag_type {
117 OCTEON_ORDERED_TAG = 0,
118 OCTEON_ATOMIC_TAG = 1,
121 /* pre-defined host->NIC tag values */
122 #define LIO_CONTROL (0x11111110)
123 #define LIO_DATA(i) (0x11111111 + (i))
125 /* used for NIC operations */
128 /* Subcodes are used by host driver/apps to identify the sub-operation
129 * for the core. They only need to by unique for a given subsystem.
131 #define LIO_OPCODE_SUBCODE(op, sub) \
132 ((((op) & 0x0f) << 8) | ((sub) & 0x7f))
134 /** LIO_OPCODE subcodes */
135 /* This subcode is sent by core PCI driver to indicate cores are ready. */
136 #define LIO_OPCODE_NW_DATA 0x02 /* network packet data */
137 #define LIO_OPCODE_CMD 0x03
138 #define LIO_OPCODE_INFO 0x04
139 #define LIO_OPCODE_PORT_STATS 0x05
140 #define LIO_OPCODE_IF_CFG 0x09
142 #define LIO_MIN_RX_BUF_SIZE 64
143 #define LIO_MAX_RX_PKTLEN (64 * 1024)
145 /* NIC Command types */
146 #define LIO_CMD_CHANGE_MTU 0x1
147 #define LIO_CMD_CHANGE_DEVFLAGS 0x3
148 #define LIO_CMD_RX_CTL 0x4
149 #define LIO_CMD_CLEAR_STATS 0x6
150 #define LIO_CMD_SET_RSS 0xD
151 #define LIO_CMD_TNL_RX_CSUM_CTL 0x10
152 #define LIO_CMD_TNL_TX_CSUM_CTL 0x11
153 #define LIO_CMD_ADD_VLAN_FILTER 0x17
154 #define LIO_CMD_DEL_VLAN_FILTER 0x18
155 #define LIO_CMD_VXLAN_PORT_CONFIG 0x19
157 #define LIO_CMD_VXLAN_PORT_ADD 0x0
158 #define LIO_CMD_VXLAN_PORT_DEL 0x1
159 #define LIO_CMD_RXCSUM_ENABLE 0x0
160 #define LIO_CMD_TXCSUM_ENABLE 0x0
162 /* RX(packets coming from wire) Checksum verification flags */
164 #define LIO_L4_CSUM_VERIFIED 0x1
165 #define LIO_IP_CSUM_VERIFIED 0x2
168 #define LIO_RSS_PARAM_DISABLE_RSS 0x10
169 #define LIO_RSS_PARAM_HASH_KEY_UNCHANGED 0x08
170 #define LIO_RSS_PARAM_ITABLE_UNCHANGED 0x04
171 #define LIO_RSS_PARAM_HASH_INFO_UNCHANGED 0x02
173 #define LIO_RSS_HASH_IPV4 0x100
174 #define LIO_RSS_HASH_TCP_IPV4 0x200
175 #define LIO_RSS_HASH_IPV6 0x400
176 #define LIO_RSS_HASH_TCP_IPV6 0x1000
177 #define LIO_RSS_HASH_IPV6_EX 0x800
178 #define LIO_RSS_HASH_TCP_IPV6_EX 0x2000
180 #define LIO_RSS_OFFLOAD_ALL ( \
181 LIO_RSS_HASH_IPV4 | \
182 LIO_RSS_HASH_TCP_IPV4 | \
183 LIO_RSS_HASH_IPV6 | \
184 LIO_RSS_HASH_TCP_IPV6 | \
185 LIO_RSS_HASH_IPV6_EX | \
186 LIO_RSS_HASH_TCP_IPV6_EX)
188 #define LIO_RSS_MAX_TABLE_SZ 128
189 #define LIO_RSS_MAX_KEY_SZ 40
190 #define LIO_RSS_PARAM_SIZE 16
192 /* Interface flags communicated between host driver and core app. */
194 LIO_IFFLAG_PROMISC = 0x01,
195 LIO_IFFLAG_ALLMULTI = 0x02,
196 LIO_IFFLAG_UNICAST = 0x10
199 /* Routines for reading and writing CSRs */
200 #ifdef RTE_LIBRTE_LIO_DEBUG_REGS
201 #define lio_write_csr(lio_dev, reg_off, value) \
203 typeof(lio_dev) _dev = lio_dev; \
204 typeof(reg_off) _reg_off = reg_off; \
205 typeof(value) _value = value; \
207 "Write32: Reg: 0x%08lx Val: 0x%08lx\n", \
208 (unsigned long)_reg_off, \
209 (unsigned long)_value); \
210 rte_write32(_value, _dev->hw_addr + _reg_off); \
213 #define lio_write_csr64(lio_dev, reg_off, val64) \
215 typeof(lio_dev) _dev = lio_dev; \
216 typeof(reg_off) _reg_off = reg_off; \
217 typeof(val64) _val64 = val64; \
220 "Write64: Reg: 0x%08lx Val: 0x%016llx\n", \
221 (unsigned long)_reg_off, \
222 (unsigned long long)_val64); \
223 rte_write64(_val64, _dev->hw_addr + _reg_off); \
226 #define lio_read_csr(lio_dev, reg_off) \
228 typeof(lio_dev) _dev = lio_dev; \
229 typeof(reg_off) _reg_off = reg_off; \
230 uint32_t val = rte_read32(_dev->hw_addr + _reg_off); \
232 "Read32: Reg: 0x%08lx Val: 0x%08lx\n", \
233 (unsigned long)_reg_off, \
234 (unsigned long)val); \
238 #define lio_read_csr64(lio_dev, reg_off) \
240 typeof(lio_dev) _dev = lio_dev; \
241 typeof(reg_off) _reg_off = reg_off; \
242 uint64_t val64 = rte_read64(_dev->hw_addr + _reg_off); \
245 "Read64: Reg: 0x%08lx Val: 0x%016llx\n", \
246 (unsigned long)_reg_off, \
247 (unsigned long long)val64); \
251 #define lio_write_csr(lio_dev, reg_off, value) \
252 rte_write32(value, (lio_dev)->hw_addr + (reg_off))
254 #define lio_write_csr64(lio_dev, reg_off, val64) \
255 rte_write64(val64, (lio_dev)->hw_addr + (reg_off))
257 #define lio_read_csr(lio_dev, reg_off) \
258 rte_read32((lio_dev)->hw_addr + (reg_off))
260 #define lio_read_csr64(lio_dev, reg_off) \
261 rte_read64((lio_dev)->hw_addr + (reg_off))
263 #endif /* _LIO_HW_DEFS_H_ */