1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2017 6WIND S.A.
3 * Copyright 2017 Mellanox
8 * Tx queues configuration for mlx4 driver.
18 /* Verbs headers do not support -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_common.h>
28 #include <rte_errno.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_malloc.h>
32 #include <rte_mempool.h>
36 #include "mlx4_rxtx.h"
37 #include "mlx4_utils.h"
40 * Free Tx queue elements.
43 * Pointer to Tx queue structure.
46 mlx4_txq_free_elts(struct txq *txq)
48 unsigned int elts_head = txq->elts_head;
49 unsigned int elts_tail = txq->elts_tail;
50 struct txq_elt (*elts)[txq->elts_n] = txq->elts;
51 unsigned int elts_m = txq->elts_n - 1;
53 DEBUG("%p: freeing WRs", (void *)txq);
54 while (elts_tail != elts_head) {
55 struct txq_elt *elt = &(*elts)[elts_tail++ & elts_m];
57 assert(elt->buf != NULL);
58 rte_pktmbuf_free(elt->buf);
62 txq->elts_tail = txq->elts_head;
65 struct txq_mp2mr_mbuf_check_data {
70 * Callback function for rte_mempool_obj_iter() to check whether a given
71 * mempool object looks like a mbuf.
76 * Context data (struct mlx4_txq_mp2mr_mbuf_check_data). Contains the
81 * Object index, unused.
84 mlx4_txq_mp2mr_mbuf_check(struct rte_mempool *mp, void *arg, void *obj,
87 struct txq_mp2mr_mbuf_check_data *data = arg;
88 struct rte_mbuf *buf = obj;
92 * Check whether mbuf structure fits element size and whether mempool
95 if (sizeof(*buf) > mp->elt_size || buf->pool != mp)
100 * Iterator function for rte_mempool_walk() to register existing mempools and
101 * fill the MP to MR cache of a Tx queue.
104 * Memory Pool to register.
106 * Pointer to Tx queue structure.
109 mlx4_txq_mp2mr_iter(struct rte_mempool *mp, void *arg)
111 struct txq *txq = arg;
112 struct txq_mp2mr_mbuf_check_data data = {
116 /* Register mempool only if the first element looks like a mbuf. */
117 if (rte_mempool_obj_iter(mp, mlx4_txq_mp2mr_mbuf_check, &data) == 0 ||
120 mlx4_txq_mp2mr(txq, mp);
124 * Retrieves information needed in order to directly access the Tx queue.
127 * Pointer to Tx queue structure.
129 * Pointer to device information for this Tx queue.
132 mlx4_txq_fill_dv_obj_info(struct txq *txq, struct mlx4dv_obj *mlxdv)
134 struct mlx4_sq *sq = &txq->msq;
135 struct mlx4_cq *cq = &txq->mcq;
136 struct mlx4dv_qp *dqp = mlxdv->qp.out;
137 struct mlx4dv_cq *dcq = mlxdv->cq.out;
139 /* Total length, including headroom and spare WQEs. */
140 sq->size = (uint32_t)dqp->rq.offset - (uint32_t)dqp->sq.offset;
141 sq->buf = (uint8_t *)dqp->buf.buf + dqp->sq.offset;
142 sq->eob = sq->buf + sq->size;
143 uint32_t headroom_size = 2048 + (1 << dqp->sq.wqe_shift);
144 /* Continuous headroom size bytes must always stay freed. */
145 sq->remain_size = sq->size - headroom_size;
146 sq->owner_opcode = MLX4_OPCODE_SEND | (0 << MLX4_SQ_OWNER_BIT);
147 sq->stamp = rte_cpu_to_be_32(MLX4_SQ_STAMP_VAL |
148 (0 << MLX4_SQ_OWNER_BIT));
150 sq->doorbell_qpn = dqp->doorbell_qpn;
151 cq->buf = dcq->buf.buf;
152 cq->cqe_cnt = dcq->cqe_cnt;
153 cq->set_ci_db = dcq->set_ci_db;
154 cq->cqe_64 = (dcq->cqe_size & 64) ? 1 : 0;
158 * Returns the per-port supported offloads.
161 * Pointer to private structure.
164 * Supported Tx offloads.
167 mlx4_get_tx_port_offloads(struct priv *priv)
169 uint64_t offloads = DEV_TX_OFFLOAD_MULTI_SEGS;
172 offloads |= (DEV_TX_OFFLOAD_IPV4_CKSUM |
173 DEV_TX_OFFLOAD_UDP_CKSUM |
174 DEV_TX_OFFLOAD_TCP_CKSUM);
176 if (priv->hw_csum_l2tun)
177 offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
182 * Checks if the per-queue offload configuration is valid.
185 * Pointer to private structure.
187 * Per-queue offloads configuration.
190 * Nonzero when configuration is valid.
193 mlx4_check_tx_queue_offloads(struct priv *priv, uint64_t requested)
195 uint64_t mandatory = priv->dev->data->dev_conf.txmode.offloads;
196 uint64_t supported = mlx4_get_tx_port_offloads(priv);
198 return !((mandatory ^ requested) & supported);
202 * DPDK callback to configure a Tx queue.
205 * Pointer to Ethernet device structure.
209 * Number of descriptors to configure in queue.
211 * NUMA socket on which memory must be allocated.
213 * Thresholds parameters.
216 * 0 on success, negative errno value otherwise and rte_errno is set.
219 mlx4_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
220 unsigned int socket, const struct rte_eth_txconf *conf)
222 struct priv *priv = dev->data->dev_private;
223 struct mlx4dv_obj mlxdv;
224 struct mlx4dv_qp dv_qp;
225 struct mlx4dv_cq dv_cq;
226 struct txq_elt (*elts)[rte_align32pow2(desc)];
227 struct ibv_qp_init_attr qp_init_attr;
230 struct mlx4_malloc_vec vec[] = {
232 .align = RTE_CACHE_LINE_SIZE,
233 .size = sizeof(*txq),
234 .addr = (void **)&txq,
237 .align = RTE_CACHE_LINE_SIZE,
238 .size = sizeof(*elts),
239 .addr = (void **)&elts,
242 .align = RTE_CACHE_LINE_SIZE,
243 .size = MLX4_MAX_WQE_SIZE,
244 .addr = (void **)&bounce_buf,
249 DEBUG("%p: configuring queue %u for %u descriptors",
250 (void *)dev, idx, desc);
252 * Don't verify port offloads for application which
255 if ((conf->txq_flags & ETH_TXQ_FLAGS_IGNORE) &&
256 !mlx4_check_tx_queue_offloads(priv, conf->offloads)) {
258 ERROR("%p: Tx queue offloads 0x%" PRIx64 " don't match port "
259 "offloads 0x%" PRIx64 " or supported offloads 0x%" PRIx64,
260 (void *)dev, conf->offloads,
261 dev->data->dev_conf.txmode.offloads,
262 mlx4_get_tx_port_offloads(priv));
265 if (idx >= dev->data->nb_tx_queues) {
266 rte_errno = EOVERFLOW;
267 ERROR("%p: queue index out of range (%u >= %u)",
268 (void *)dev, idx, dev->data->nb_tx_queues);
271 txq = dev->data->tx_queues[idx];
274 DEBUG("%p: Tx queue %u already configured, release it first",
280 ERROR("%p: invalid number of Tx descriptors", (void *)dev);
283 if (desc != RTE_DIM(*elts)) {
284 desc = RTE_DIM(*elts);
285 WARN("%p: increased number of descriptors in Tx queue %u"
286 " to the next power of two (%u)",
287 (void *)dev, idx, desc);
289 /* Allocate and initialize Tx queue. */
290 mlx4_zmallocv_socket("TXQ", vec, RTE_DIM(vec), socket);
292 ERROR("%p: unable to allocate queue index %u",
307 * Request send completion every MLX4_PMD_TX_PER_COMP_REQ
308 * packets or at least 4 times per ring.
311 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
313 RTE_MIN(MLX4_PMD_TX_PER_COMP_REQ, desc / 4),
314 .csum = priv->hw_csum &&
315 (conf->offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
316 DEV_TX_OFFLOAD_UDP_CKSUM |
317 DEV_TX_OFFLOAD_TCP_CKSUM)),
318 .csum_l2tun = priv->hw_csum_l2tun &&
320 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM),
321 /* Enable Tx loopback for VF devices. */
323 .bounce_buf = bounce_buf,
325 txq->cq = ibv_create_cq(priv->ctx, desc, NULL, NULL, 0);
328 ERROR("%p: CQ creation failure: %s",
329 (void *)dev, strerror(rte_errno));
332 qp_init_attr = (struct ibv_qp_init_attr){
337 RTE_MIN(priv->device_attr.max_qp_wr, desc),
339 .max_inline_data = MLX4_PMD_MAX_INLINE,
341 .qp_type = IBV_QPT_RAW_PACKET,
342 /* No completion events must occur by default. */
345 txq->qp = ibv_create_qp(priv->pd, &qp_init_attr);
347 rte_errno = errno ? errno : EINVAL;
348 ERROR("%p: QP creation failure: %s",
349 (void *)dev, strerror(rte_errno));
352 txq->max_inline = qp_init_attr.cap.max_inline_data;
355 &(struct ibv_qp_attr){
356 .qp_state = IBV_QPS_INIT,
357 .port_num = priv->port,
359 IBV_QP_STATE | IBV_QP_PORT);
362 ERROR("%p: QP state to IBV_QPS_INIT failed: %s",
363 (void *)dev, strerror(rte_errno));
368 &(struct ibv_qp_attr){
369 .qp_state = IBV_QPS_RTR,
374 ERROR("%p: QP state to IBV_QPS_RTR failed: %s",
375 (void *)dev, strerror(rte_errno));
380 &(struct ibv_qp_attr){
381 .qp_state = IBV_QPS_RTS,
386 ERROR("%p: QP state to IBV_QPS_RTS failed: %s",
387 (void *)dev, strerror(rte_errno));
390 /* Retrieve device queue information. */
391 mlxdv.cq.in = txq->cq;
392 mlxdv.cq.out = &dv_cq;
393 mlxdv.qp.in = txq->qp;
394 mlxdv.qp.out = &dv_qp;
395 ret = mlx4dv_init_obj(&mlxdv, MLX4DV_OBJ_QP | MLX4DV_OBJ_CQ);
398 ERROR("%p: failed to obtain information needed for"
399 " accessing the device queues", (void *)dev);
402 mlx4_txq_fill_dv_obj_info(txq, &mlxdv);
403 /* Save first wqe pointer in the first element. */
404 (&(*txq->elts)[0])->wqe =
405 (volatile struct mlx4_wqe_ctrl_seg *)txq->msq.buf;
406 /* Pre-register known mempools. */
407 rte_mempool_walk(mlx4_txq_mp2mr_iter, txq);
408 DEBUG("%p: adding Tx queue %p to list", (void *)dev, (void *)txq);
409 dev->data->tx_queues[idx] = txq;
412 dev->data->tx_queues[idx] = NULL;
414 mlx4_tx_queue_release(txq);
416 assert(rte_errno > 0);
421 * DPDK callback to release a Tx queue.
424 * Generic Tx queue pointer.
427 mlx4_tx_queue_release(void *dpdk_txq)
429 struct txq *txq = (struct txq *)dpdk_txq;
436 for (i = 0; i != priv->dev->data->nb_tx_queues; ++i)
437 if (priv->dev->data->tx_queues[i] == txq) {
438 DEBUG("%p: removing Tx queue %p from list",
439 (void *)priv->dev, (void *)txq);
440 priv->dev->data->tx_queues[i] = NULL;
443 mlx4_txq_free_elts(txq);
445 claim_zero(ibv_destroy_qp(txq->qp));
447 claim_zero(ibv_destroy_cq(txq->cq));
448 for (i = 0; i != RTE_DIM(txq->mp2mr); ++i) {
449 if (!txq->mp2mr[i].mp)
451 assert(txq->mp2mr[i].mr);
452 mlx4_mr_put(txq->mp2mr[i].mr);