1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2020 Mellanox Technologies, Ltd
13 #include <linux/rtnetlink.h>
14 #include <linux/sockios.h>
15 #include <linux/ethtool.h>
18 #include <rte_malloc.h>
19 #include <ethdev_driver.h>
20 #include <ethdev_pci.h>
22 #include <rte_bus_pci.h>
23 #include <rte_bus_auxiliary.h>
24 #include <rte_common.h>
25 #include <rte_kvargs.h>
26 #include <rte_rwlock.h>
27 #include <rte_spinlock.h>
28 #include <rte_string_fns.h>
29 #include <rte_alarm.h>
30 #include <rte_eal_paging.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
34 #include <mlx5_common.h>
35 #include <mlx5_common_mp.h>
36 #include <mlx5_common_mr.h>
37 #include <mlx5_malloc.h>
39 #include "mlx5_defs.h"
41 #include "mlx5_common_os.h"
42 #include "mlx5_utils.h"
43 #include "mlx5_rxtx.h"
46 #include "mlx5_autoconf.h"
48 #include "mlx5_flow.h"
49 #include "rte_pmd_mlx5.h"
50 #include "mlx5_verbs.h"
52 #include "mlx5_devx.h"
54 #ifndef HAVE_IBV_MLX5_MOD_MPW
55 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
56 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
59 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
60 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
63 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
65 /* Spinlock for mlx5_shared_data allocation. */
66 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
68 /* Process local data for secondary processes. */
69 static struct mlx5_local_data mlx5_local_data;
71 /* rte flow indexed pool configuration. */
72 static struct mlx5_indexed_pool_config icfg[] = {
74 .size = sizeof(struct rte_flow),
78 .malloc = mlx5_malloc,
81 .type = "ctl_flow_ipool",
84 .size = sizeof(struct rte_flow),
90 .malloc = mlx5_malloc,
92 .per_core_cache = 1 << 14,
93 .type = "rte_flow_ipool",
96 .size = sizeof(struct rte_flow),
102 .malloc = mlx5_malloc,
105 .type = "mcp_flow_ipool",
110 * Set the completion channel file descriptor interrupt as non-blocking.
113 * Pointer to RQ channel object, which includes the channel fd
116 * The file descriptor (representing the intetrrupt) used in this channel.
119 * 0 on successfully setting the fd to non-blocking, non-zero otherwise.
122 mlx5_os_set_nonblock_channel_fd(int fd)
126 flags = fcntl(fd, F_GETFL);
127 return fcntl(fd, F_SETFL, flags | O_NONBLOCK);
131 * Get mlx5 device attributes. The glue function query_device_ex() is called
132 * with out parameter of type 'struct ibv_device_attr_ex *'. Then fill in mlx5
133 * device attributes from the glue out parameter.
136 * Pointer to ibv context.
139 * Pointer to mlx5 device attributes.
142 * 0 on success, non zero error number otherwise
145 mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
148 struct ibv_device_attr_ex attr_ex;
149 memset(device_attr, 0, sizeof(*device_attr));
150 err = mlx5_glue->query_device_ex(ctx, NULL, &attr_ex);
154 device_attr->device_cap_flags_ex = attr_ex.device_cap_flags_ex;
155 device_attr->max_qp_wr = attr_ex.orig_attr.max_qp_wr;
156 device_attr->max_sge = attr_ex.orig_attr.max_sge;
157 device_attr->max_cq = attr_ex.orig_attr.max_cq;
158 device_attr->max_cqe = attr_ex.orig_attr.max_cqe;
159 device_attr->max_mr = attr_ex.orig_attr.max_mr;
160 device_attr->max_pd = attr_ex.orig_attr.max_pd;
161 device_attr->max_qp = attr_ex.orig_attr.max_qp;
162 device_attr->max_srq = attr_ex.orig_attr.max_srq;
163 device_attr->max_srq_wr = attr_ex.orig_attr.max_srq_wr;
164 device_attr->raw_packet_caps = attr_ex.raw_packet_caps;
165 device_attr->max_rwq_indirection_table_size =
166 attr_ex.rss_caps.max_rwq_indirection_table_size;
167 device_attr->max_tso = attr_ex.tso_caps.max_tso;
168 device_attr->tso_supported_qpts = attr_ex.tso_caps.supported_qpts;
170 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
171 err = mlx5_glue->dv_query_device(ctx, &dv_attr);
175 device_attr->flags = dv_attr.flags;
176 device_attr->comp_mask = dv_attr.comp_mask;
177 #ifdef HAVE_IBV_MLX5_MOD_SWP
178 device_attr->sw_parsing_offloads =
179 dv_attr.sw_parsing_caps.sw_parsing_offloads;
181 device_attr->min_single_stride_log_num_of_bytes =
182 dv_attr.striding_rq_caps.min_single_stride_log_num_of_bytes;
183 device_attr->max_single_stride_log_num_of_bytes =
184 dv_attr.striding_rq_caps.max_single_stride_log_num_of_bytes;
185 device_attr->min_single_wqe_log_num_of_strides =
186 dv_attr.striding_rq_caps.min_single_wqe_log_num_of_strides;
187 device_attr->max_single_wqe_log_num_of_strides =
188 dv_attr.striding_rq_caps.max_single_wqe_log_num_of_strides;
189 device_attr->stride_supported_qpts =
190 dv_attr.striding_rq_caps.supported_qpts;
191 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
192 device_attr->tunnel_offloads_caps = dv_attr.tunnel_offloads_caps;
194 strlcpy(device_attr->fw_ver, attr_ex.orig_attr.fw_ver,
195 sizeof(device_attr->fw_ver));
201 * Detect misc5 support or not
204 * Device private data pointer
206 #ifdef HAVE_MLX5DV_DR
208 __mlx5_discovery_misc5_cap(struct mlx5_priv *priv)
210 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
211 /* Dummy VxLAN matcher to detect rdma-core misc5 cap
212 * Case: IPv4--->UDP--->VxLAN--->vni
215 struct mlx5_flow_dv_match_params matcher_mask;
220 uint32_t *tunnel_header_m;
221 struct mlx5dv_flow_matcher_attr dv_attr;
223 memset(&matcher_mask, 0, sizeof(matcher_mask));
224 matcher_mask.size = sizeof(matcher_mask.buf);
225 match_m = matcher_mask.buf;
226 headers_m = MLX5_ADDR_OF(fte_match_param, match_m, outer_headers);
227 misc5_m = MLX5_ADDR_OF(fte_match_param,
228 match_m, misc_parameters_5);
229 tunnel_header_m = (uint32_t *)
230 MLX5_ADDR_OF(fte_match_set_misc5,
231 misc5_m, tunnel_header_1);
232 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
233 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 4);
234 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
235 *tunnel_header_m = 0xffffff;
237 tbl = mlx5_glue->dr_create_flow_tbl(priv->sh->rx_domain, 1);
239 DRV_LOG(INFO, "No SW steering support");
242 dv_attr.type = IBV_FLOW_ATTR_NORMAL,
243 dv_attr.match_mask = (void *)&matcher_mask,
244 dv_attr.match_criteria_enable =
245 (1 << MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT) |
246 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT);
247 dv_attr.priority = 3;
248 #ifdef HAVE_MLX5DV_DR_ESWITCH
250 if (priv->config.dv_esw_en) {
251 /* FDB enabled reg_c_0 */
252 dv_attr.match_criteria_enable |=
253 (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT);
254 misc2_m = MLX5_ADDR_OF(fte_match_param,
255 match_m, misc_parameters_2);
256 MLX5_SET(fte_match_set_misc2, misc2_m,
257 metadata_reg_c_0, 0xffff);
260 matcher = mlx5_glue->dv_create_flow_matcher(priv->sh->cdev->ctx,
263 priv->sh->misc5_cap = 1;
264 mlx5_glue->dv_destroy_flow_matcher(matcher);
266 mlx5_glue->dr_destroy_flow_tbl(tbl);
274 * Initialize DR related data within private structure.
275 * Routine checks the reference counter and does actual
276 * resources creation/initialization only if counter is zero.
279 * Pointer to the private device data structure.
282 * Zero on success, positive error code otherwise.
285 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
287 struct mlx5_dev_ctx_shared *sh = priv->sh;
288 char s[MLX5_NAME_SIZE] __rte_unused;
291 MLX5_ASSERT(sh && sh->refcnt);
294 err = mlx5_alloc_table_hash_list(priv);
297 /* The resources below are only valid with DV support. */
298 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
299 /* Init port id action list. */
300 snprintf(s, sizeof(s), "%s_port_id_action_list", sh->ibdev_name);
301 sh->port_id_action_list = mlx5_list_create(s, sh, true,
302 flow_dv_port_id_create_cb,
303 flow_dv_port_id_match_cb,
304 flow_dv_port_id_remove_cb,
305 flow_dv_port_id_clone_cb,
306 flow_dv_port_id_clone_free_cb);
307 if (!sh->port_id_action_list)
309 /* Init push vlan action list. */
310 snprintf(s, sizeof(s), "%s_push_vlan_action_list", sh->ibdev_name);
311 sh->push_vlan_action_list = mlx5_list_create(s, sh, true,
312 flow_dv_push_vlan_create_cb,
313 flow_dv_push_vlan_match_cb,
314 flow_dv_push_vlan_remove_cb,
315 flow_dv_push_vlan_clone_cb,
316 flow_dv_push_vlan_clone_free_cb);
317 if (!sh->push_vlan_action_list)
319 /* Init sample action list. */
320 snprintf(s, sizeof(s), "%s_sample_action_list", sh->ibdev_name);
321 sh->sample_action_list = mlx5_list_create(s, sh, true,
322 flow_dv_sample_create_cb,
323 flow_dv_sample_match_cb,
324 flow_dv_sample_remove_cb,
325 flow_dv_sample_clone_cb,
326 flow_dv_sample_clone_free_cb);
327 if (!sh->sample_action_list)
329 /* Init dest array action list. */
330 snprintf(s, sizeof(s), "%s_dest_array_list", sh->ibdev_name);
331 sh->dest_array_list = mlx5_list_create(s, sh, true,
332 flow_dv_dest_array_create_cb,
333 flow_dv_dest_array_match_cb,
334 flow_dv_dest_array_remove_cb,
335 flow_dv_dest_array_clone_cb,
336 flow_dv_dest_array_clone_free_cb);
337 if (!sh->dest_array_list)
340 #ifdef HAVE_MLX5DV_DR
343 /* Reference counter is zero, we should initialize structures. */
344 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
345 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
347 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
351 sh->rx_domain = domain;
352 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
353 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
355 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
359 sh->tx_domain = domain;
360 #ifdef HAVE_MLX5DV_DR_ESWITCH
361 if (priv->config.dv_esw_en) {
362 domain = mlx5_glue->dr_create_domain(sh->cdev->ctx,
363 MLX5DV_DR_DOMAIN_TYPE_FDB);
365 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
369 sh->fdb_domain = domain;
372 * The drop action is just some dummy placeholder in rdma-core. It
373 * does not belong to domains and has no any attributes, and, can be
374 * shared by the entire device.
376 sh->dr_drop_action = mlx5_glue->dr_create_flow_action_drop();
377 if (!sh->dr_drop_action) {
378 DRV_LOG(ERR, "FDB mlx5dv_dr_create_flow_action_drop");
383 if (!sh->tunnel_hub && priv->config.dv_miss_info)
384 err = mlx5_alloc_tunnel_hub(sh);
386 DRV_LOG(ERR, "mlx5_alloc_tunnel_hub failed err=%d", err);
389 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) {
390 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1);
391 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1);
393 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1);
395 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
396 if (!priv->config.allow_duplicate_pattern) {
397 #ifndef HAVE_MLX5_DR_ALLOW_DUPLICATE
398 DRV_LOG(WARNING, "Disallow duplicate pattern is not supported - maybe old rdma-core version?");
400 mlx5_glue->dr_allow_duplicate_rules(sh->rx_domain, 0);
401 mlx5_glue->dr_allow_duplicate_rules(sh->tx_domain, 0);
403 mlx5_glue->dr_allow_duplicate_rules(sh->fdb_domain, 0);
406 __mlx5_discovery_misc5_cap(priv);
407 #endif /* HAVE_MLX5DV_DR */
408 sh->default_miss_action =
409 mlx5_glue->dr_create_flow_action_default_miss();
410 if (!sh->default_miss_action)
411 DRV_LOG(WARNING, "Default miss action is not supported.");
414 /* Rollback the created objects. */
416 mlx5_glue->dr_destroy_domain(sh->rx_domain);
417 sh->rx_domain = NULL;
420 mlx5_glue->dr_destroy_domain(sh->tx_domain);
421 sh->tx_domain = NULL;
423 if (sh->fdb_domain) {
424 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
425 sh->fdb_domain = NULL;
427 if (sh->dr_drop_action) {
428 mlx5_glue->destroy_flow_action(sh->dr_drop_action);
429 sh->dr_drop_action = NULL;
431 if (sh->pop_vlan_action) {
432 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
433 sh->pop_vlan_action = NULL;
435 if (sh->encaps_decaps) {
436 mlx5_hlist_destroy(sh->encaps_decaps);
437 sh->encaps_decaps = NULL;
439 if (sh->modify_cmds) {
440 mlx5_hlist_destroy(sh->modify_cmds);
441 sh->modify_cmds = NULL;
444 /* tags should be destroyed with flow before. */
445 mlx5_hlist_destroy(sh->tag_table);
446 sh->tag_table = NULL;
448 if (sh->tunnel_hub) {
449 mlx5_release_tunnel_hub(sh, priv->dev_port);
450 sh->tunnel_hub = NULL;
452 mlx5_free_table_hash_list(priv);
453 if (sh->port_id_action_list) {
454 mlx5_list_destroy(sh->port_id_action_list);
455 sh->port_id_action_list = NULL;
457 if (sh->push_vlan_action_list) {
458 mlx5_list_destroy(sh->push_vlan_action_list);
459 sh->push_vlan_action_list = NULL;
461 if (sh->sample_action_list) {
462 mlx5_list_destroy(sh->sample_action_list);
463 sh->sample_action_list = NULL;
465 if (sh->dest_array_list) {
466 mlx5_list_destroy(sh->dest_array_list);
467 sh->dest_array_list = NULL;
473 * Destroy DR related data within private structure.
476 * Pointer to the private device data structure.
479 mlx5_os_free_shared_dr(struct mlx5_priv *priv)
481 struct mlx5_dev_ctx_shared *sh = priv->sh;
483 MLX5_ASSERT(sh && sh->refcnt);
486 #ifdef HAVE_MLX5DV_DR
488 mlx5_glue->dr_destroy_domain(sh->rx_domain);
489 sh->rx_domain = NULL;
492 mlx5_glue->dr_destroy_domain(sh->tx_domain);
493 sh->tx_domain = NULL;
495 #ifdef HAVE_MLX5DV_DR_ESWITCH
496 if (sh->fdb_domain) {
497 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
498 sh->fdb_domain = NULL;
500 if (sh->dr_drop_action) {
501 mlx5_glue->destroy_flow_action(sh->dr_drop_action);
502 sh->dr_drop_action = NULL;
505 if (sh->pop_vlan_action) {
506 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
507 sh->pop_vlan_action = NULL;
509 #endif /* HAVE_MLX5DV_DR */
510 if (sh->default_miss_action)
511 mlx5_glue->destroy_flow_action
512 (sh->default_miss_action);
513 if (sh->encaps_decaps) {
514 mlx5_hlist_destroy(sh->encaps_decaps);
515 sh->encaps_decaps = NULL;
517 if (sh->modify_cmds) {
518 mlx5_hlist_destroy(sh->modify_cmds);
519 sh->modify_cmds = NULL;
522 /* tags should be destroyed with flow before. */
523 mlx5_hlist_destroy(sh->tag_table);
524 sh->tag_table = NULL;
526 if (sh->tunnel_hub) {
527 mlx5_release_tunnel_hub(sh, priv->dev_port);
528 sh->tunnel_hub = NULL;
530 mlx5_free_table_hash_list(priv);
531 if (sh->port_id_action_list) {
532 mlx5_list_destroy(sh->port_id_action_list);
533 sh->port_id_action_list = NULL;
535 if (sh->push_vlan_action_list) {
536 mlx5_list_destroy(sh->push_vlan_action_list);
537 sh->push_vlan_action_list = NULL;
539 if (sh->sample_action_list) {
540 mlx5_list_destroy(sh->sample_action_list);
541 sh->sample_action_list = NULL;
543 if (sh->dest_array_list) {
544 mlx5_list_destroy(sh->dest_array_list);
545 sh->dest_array_list = NULL;
550 * Initialize shared data between primary and secondary process.
552 * A memzone is reserved by primary process and secondary processes attach to
556 * 0 on success, a negative errno value otherwise and rte_errno is set.
559 mlx5_init_shared_data(void)
561 const struct rte_memzone *mz;
564 rte_spinlock_lock(&mlx5_shared_data_lock);
565 if (mlx5_shared_data == NULL) {
566 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
567 /* Allocate shared memory. */
568 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
569 sizeof(*mlx5_shared_data),
573 "Cannot allocate mlx5 shared data");
577 mlx5_shared_data = mz->addr;
578 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
579 rte_spinlock_init(&mlx5_shared_data->lock);
581 /* Lookup allocated shared memory. */
582 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
585 "Cannot attach mlx5 shared data");
589 mlx5_shared_data = mz->addr;
590 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
594 rte_spinlock_unlock(&mlx5_shared_data_lock);
599 * PMD global initialization.
601 * Independent from individual device, this function initializes global
602 * per-PMD data structures distinguishing primary and secondary processes.
603 * Hence, each initialization is called once per a process.
606 * 0 on success, a negative errno value otherwise and rte_errno is set.
611 struct mlx5_shared_data *sd;
612 struct mlx5_local_data *ld = &mlx5_local_data;
615 if (mlx5_init_shared_data())
617 sd = mlx5_shared_data;
619 rte_spinlock_lock(&sd->lock);
620 switch (rte_eal_process_type()) {
621 case RTE_PROC_PRIMARY:
624 LIST_INIT(&sd->mem_event_cb_list);
625 rte_rwlock_init(&sd->mem_event_rwlock);
626 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
627 mlx5_mr_mem_event_cb, NULL);
628 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
629 mlx5_mp_os_primary_handle);
632 sd->init_done = true;
634 case RTE_PROC_SECONDARY:
637 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
638 mlx5_mp_os_secondary_handle);
642 ld->init_done = true;
648 rte_spinlock_unlock(&sd->lock);
653 * Create the Tx queue DevX/Verbs object.
656 * Pointer to Ethernet device.
658 * Queue index in DPDK Tx queue array.
661 * 0 on success, a negative errno value otherwise and rte_errno is set.
664 mlx5_os_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx)
666 struct mlx5_priv *priv = dev->data->dev_private;
667 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
668 struct mlx5_txq_ctrl *txq_ctrl =
669 container_of(txq_data, struct mlx5_txq_ctrl, txq);
671 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
672 return mlx5_txq_devx_obj_new(dev, idx);
673 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET
674 if (!priv->config.dv_esw_en)
675 return mlx5_txq_devx_obj_new(dev, idx);
677 return mlx5_txq_ibv_obj_new(dev, idx);
681 * Release an Tx DevX/verbs queue object.
684 * DevX/Verbs Tx queue object.
687 mlx5_os_txq_obj_release(struct mlx5_txq_obj *txq_obj)
689 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
690 mlx5_txq_devx_obj_release(txq_obj);
693 #ifdef HAVE_MLX5DV_DEVX_UAR_OFFSET
694 if (!txq_obj->txq_ctrl->priv->config.dv_esw_en) {
695 mlx5_txq_devx_obj_release(txq_obj);
699 mlx5_txq_ibv_obj_release(txq_obj);
703 * DV flow counter mode detect and config.
706 * Pointer to rte_eth_dev structure.
710 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused)
712 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
713 struct mlx5_priv *priv = dev->data->dev_private;
714 struct mlx5_dev_ctx_shared *sh = priv->sh;
717 #ifndef HAVE_IBV_DEVX_ASYNC
721 if (!sh->devx || !priv->config.dv_flow_en ||
722 !priv->config.hca_attr.flow_counters_dump ||
723 !(priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4) ||
724 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP))
728 DRV_LOG(INFO, "Use fall-back DV counter management. Flow "
729 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.",
730 priv->config.hca_attr.flow_counters_dump,
731 priv->config.hca_attr.flow_counter_bulk_alloc_bitmap);
732 /* Initialize fallback mode only on the port initializes sh. */
734 sh->cmng.counter_fallback = fallback;
735 else if (fallback != sh->cmng.counter_fallback)
736 DRV_LOG(WARNING, "Port %d in sh has different fallback mode "
737 "with others:%d.", PORT_ID(priv), fallback);
742 * DR flow drop action support detect.
745 * Pointer to rte_eth_dev structure.
749 mlx5_flow_drop_action_config(struct rte_eth_dev *dev __rte_unused)
751 #ifdef HAVE_MLX5DV_DR
752 struct mlx5_priv *priv = dev->data->dev_private;
754 if (!priv->config.dv_flow_en || !priv->sh->dr_drop_action)
757 * DR supports drop action placeholder when it is supported;
758 * otherwise, use the queue drop action.
760 if (mlx5_flow_discover_dr_action_support(dev))
761 priv->root_drop_action = priv->drop_queue.hrxq->action;
763 priv->root_drop_action = priv->sh->dr_drop_action;
768 mlx5_queue_counter_id_prepare(struct rte_eth_dev *dev)
770 struct mlx5_priv *priv = dev->data->dev_private;
771 void *ctx = priv->sh->cdev->ctx;
773 priv->q_counters = mlx5_devx_cmd_queue_counter_alloc(ctx);
774 if (!priv->q_counters) {
775 struct ibv_cq *cq = mlx5_glue->create_cq(ctx, 1, NULL, NULL, 0);
778 DRV_LOG(DEBUG, "Port %d queue counter object cannot be created "
779 "by DevX - fall-back to use the kernel driver global "
780 "queue counter.", dev->data->port_id);
781 /* Create WQ by kernel and query its queue counter ID. */
783 wq = mlx5_glue->create_wq(ctx,
784 &(struct ibv_wq_init_attr){
785 .wq_type = IBV_WQT_RQ,
792 /* Counter is assigned only on RDY state. */
793 int ret = mlx5_glue->modify_wq(wq,
794 &(struct ibv_wq_attr){
795 .attr_mask = IBV_WQ_ATTR_STATE,
796 .wq_state = IBV_WQS_RDY,
800 mlx5_devx_cmd_wq_query(wq,
801 &priv->counter_set_id);
802 claim_zero(mlx5_glue->destroy_wq(wq));
804 claim_zero(mlx5_glue->destroy_cq(cq));
807 priv->counter_set_id = priv->q_counters->id;
809 if (priv->counter_set_id == 0)
810 DRV_LOG(INFO, "Part of the port %d statistics will not be "
811 "available.", dev->data->port_id);
815 * Check if representor spawn info match devargs.
818 * Verbs device parameters (name, port, switch_info) to spawn.
820 * Device devargs to probe.
826 mlx5_representor_match(struct mlx5_dev_spawn_data *spawn,
827 struct rte_eth_devargs *eth_da)
829 struct mlx5_switch_info *switch_info = &spawn->info;
832 uint16_t repr_id = mlx5_representor_id_encode(switch_info,
835 switch (eth_da->type) {
836 case RTE_ETH_REPRESENTOR_SF:
837 if (!(spawn->info.port_name == -1 &&
838 switch_info->name_type ==
839 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) &&
840 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFSF) {
845 case RTE_ETH_REPRESENTOR_VF:
846 /* Allows HPF representor index -1 as exception. */
847 if (!(spawn->info.port_name == -1 &&
848 switch_info->name_type ==
849 MLX5_PHYS_PORT_NAME_TYPE_PFHPF) &&
850 switch_info->name_type != MLX5_PHYS_PORT_NAME_TYPE_PFVF) {
855 case RTE_ETH_REPRESENTOR_NONE:
860 DRV_LOG(ERR, "unsupported representor type");
863 /* Check representor ID: */
864 for (p = 0; p < eth_da->nb_ports; ++p) {
865 if (spawn->pf_bond < 0) {
866 /* For non-LAG mode, allow and ignore pf. */
867 switch_info->pf_num = eth_da->ports[p];
868 repr_id = mlx5_representor_id_encode(switch_info,
871 for (f = 0; f < eth_da->nb_representor_ports; ++f) {
872 id = MLX5_REPRESENTOR_ID
873 (eth_da->ports[p], eth_da->type,
874 eth_da->representor_ports[f]);
885 * Spawn an Ethernet device from Verbs information.
888 * Backing DPDK device.
890 * Verbs device parameters (name, port, switch_info) to spawn.
892 * Device configuration parameters.
897 * A valid Ethernet device object on success, NULL otherwise and rte_errno
898 * is set. The following errors are defined:
900 * EBUSY: device is not supposed to be spawned.
901 * EEXIST: device is already spawned
903 static struct rte_eth_dev *
904 mlx5_dev_spawn(struct rte_device *dpdk_dev,
905 struct mlx5_dev_spawn_data *spawn,
906 struct mlx5_dev_config *config,
907 struct rte_eth_devargs *eth_da)
909 const struct mlx5_switch_info *switch_info = &spawn->info;
910 struct mlx5_dev_ctx_shared *sh = NULL;
911 struct ibv_port_attr port_attr;
912 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
913 struct rte_eth_dev *eth_dev = NULL;
914 struct mlx5_priv *priv = NULL;
916 unsigned int hw_padding = 0;
918 unsigned int mpls_en = 0;
919 unsigned int swp = 0;
920 unsigned int mprq = 0;
921 unsigned int mprq_min_stride_size_n = 0;
922 unsigned int mprq_max_stride_size_n = 0;
923 unsigned int mprq_min_stride_num_n = 0;
924 unsigned int mprq_max_stride_num_n = 0;
925 struct rte_ether_addr mac;
926 char name[RTE_ETH_NAME_MAX_LEN];
927 int own_domain_id = 0;
929 struct mlx5_port_info vport_info = { .query_flags = 0 };
932 /* Determine if this port representor is supposed to be spawned. */
933 if (switch_info->representor && dpdk_dev->devargs &&
934 !mlx5_representor_match(spawn, eth_da))
936 /* Build device name. */
937 if (spawn->pf_bond < 0) {
939 if (!switch_info->representor)
940 strlcpy(name, dpdk_dev->name, sizeof(name));
942 err = snprintf(name, sizeof(name), "%s_representor_%s%u",
944 switch_info->name_type ==
945 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf",
946 switch_info->port_name);
948 /* Bonding device. */
949 if (!switch_info->representor) {
950 err = snprintf(name, sizeof(name), "%s_%s",
951 dpdk_dev->name, spawn->phys_dev_name);
953 err = snprintf(name, sizeof(name), "%s_%s_representor_c%dpf%d%s%u",
954 dpdk_dev->name, spawn->phys_dev_name,
955 switch_info->ctrl_num,
957 switch_info->name_type ==
958 MLX5_PHYS_PORT_NAME_TYPE_PFSF ? "sf" : "vf",
959 switch_info->port_name);
962 if (err >= (int)sizeof(name))
963 DRV_LOG(WARNING, "device name overflow %s", name);
964 /* check if the device is already spawned */
965 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
969 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
970 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
971 struct mlx5_mp_id mp_id;
973 eth_dev = rte_eth_dev_attach_secondary(name);
974 if (eth_dev == NULL) {
975 DRV_LOG(ERR, "can not attach rte ethdev");
979 eth_dev->device = dpdk_dev;
980 eth_dev->dev_ops = &mlx5_dev_sec_ops;
981 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
982 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
983 err = mlx5_proc_priv_init(eth_dev);
986 mlx5_mp_id_init(&mp_id, eth_dev->data->port_id);
987 /* Receive command fd from primary process */
988 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
991 /* Remap UAR for Tx queues. */
992 err = mlx5_tx_uar_init_secondary(eth_dev, err);
996 * Ethdev pointer is still required as input since
997 * the primary device is not accessible from the
1000 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
1001 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
1004 mlx5_dev_close(eth_dev);
1008 * Some parameters ("tx_db_nc" in particularly) are needed in
1009 * advance to create dv/verbs device context. We proceed the
1010 * devargs here to get ones, and later proceed devargs again
1011 * to override some hardware settings.
1013 err = mlx5_args(config, dpdk_dev->devargs);
1016 DRV_LOG(ERR, "failed to process device arguments: %s",
1017 strerror(rte_errno));
1020 if (config->dv_miss_info) {
1021 if (switch_info->master || switch_info->representor)
1022 config->dv_xmeta_en = MLX5_XMETA_MODE_META16;
1024 sh = mlx5_alloc_shared_dev_ctx(spawn, config);
1027 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
1028 config->dest_tir = 1;
1030 #ifdef HAVE_IBV_MLX5_MOD_SWP
1031 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
1034 * Multi-packet send is supported by ConnectX-4 Lx PF as well
1035 * as all ConnectX-5 devices.
1037 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1038 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1040 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1041 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
1043 mlx5_glue->dv_query_device(sh->cdev->ctx, &dv_attr);
1044 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1045 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1046 DRV_LOG(DEBUG, "enhanced MPW is supported");
1047 mps = MLX5_MPW_ENHANCED;
1049 DRV_LOG(DEBUG, "MPW is supported");
1053 DRV_LOG(DEBUG, "MPW isn't supported");
1054 mps = MLX5_MPW_DISABLED;
1056 #ifdef HAVE_IBV_MLX5_MOD_SWP
1057 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1058 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
1059 DRV_LOG(DEBUG, "SWP support: %u", swp);
1061 config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
1062 MLX5_SW_PARSING_TSO_CAP);
1063 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1064 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1065 struct mlx5dv_striding_rq_caps mprq_caps =
1066 dv_attr.striding_rq_caps;
1068 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1069 mprq_caps.min_single_stride_log_num_of_bytes);
1070 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1071 mprq_caps.max_single_stride_log_num_of_bytes);
1072 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1073 mprq_caps.min_single_wqe_log_num_of_strides);
1074 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1075 mprq_caps.max_single_wqe_log_num_of_strides);
1076 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1077 mprq_caps.supported_qpts);
1078 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1080 mprq_min_stride_size_n =
1081 mprq_caps.min_single_stride_log_num_of_bytes;
1082 mprq_max_stride_size_n =
1083 mprq_caps.max_single_stride_log_num_of_bytes;
1084 mprq_min_stride_num_n =
1085 mprq_caps.min_single_wqe_log_num_of_strides;
1086 mprq_max_stride_num_n =
1087 mprq_caps.max_single_wqe_log_num_of_strides;
1090 /* Rx CQE compression is enabled by default. */
1091 config->cqe_comp = 1;
1092 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1093 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
1094 config->tunnel_en = dv_attr.tunnel_offloads_caps &
1095 (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
1096 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
1097 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
1099 if (config->tunnel_en) {
1100 DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
1102 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
1104 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
1106 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
1109 DRV_LOG(DEBUG, "tunnel offloading is not supported");
1113 "tunnel offloading disabled due to old OFED/rdma-core version");
1115 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
1116 mpls_en = ((dv_attr.tunnel_offloads_caps &
1117 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
1118 (dv_attr.tunnel_offloads_caps &
1119 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
1120 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
1121 mpls_en ? "" : "not ");
1123 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
1124 " old OFED/rdma-core version or firmware configuration");
1126 config->mpls_en = mpls_en;
1127 /* Check port status. */
1128 err = mlx5_glue->query_port(sh->cdev->ctx, spawn->phys_port,
1131 DRV_LOG(ERR, "port query failed: %s", strerror(err));
1134 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1135 DRV_LOG(ERR, "port is not configured in Ethernet mode");
1139 if (port_attr.state != IBV_PORT_ACTIVE)
1140 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
1141 mlx5_glue->port_state_str(port_attr.state),
1143 /* Allocate private eth device data. */
1144 priv = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1146 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1148 DRV_LOG(ERR, "priv allocation failure");
1153 priv->dev_port = spawn->phys_port;
1154 priv->pci_dev = spawn->pci_dev;
1155 priv->mtu = RTE_ETHER_MTU;
1156 /* Some internal functions rely on Netlink sockets, open them now. */
1157 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
1158 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
1159 priv->representor = !!switch_info->representor;
1160 priv->master = !!switch_info->master;
1161 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1162 priv->vport_meta_tag = 0;
1163 priv->vport_meta_mask = 0;
1164 priv->pf_bond = spawn->pf_bond;
1167 "dev_port=%u bus=%s pci=%s master=%d representor=%d pf_bond=%d\n",
1168 priv->dev_port, dpdk_dev->bus->name,
1169 priv->pci_dev ? priv->pci_dev->name : "NONE",
1170 priv->master, priv->representor, priv->pf_bond);
1173 * If we have E-Switch we should determine the vport attributes.
1174 * E-Switch may use either source vport field or reg_c[0] metadata
1175 * register to match on vport index. The engaged part of metadata
1176 * register is defined by mask.
1178 if (switch_info->representor || switch_info->master) {
1179 err = mlx5_glue->devx_port_query(sh->cdev->ctx,
1184 "Cannot query devx port %d on device %s",
1185 spawn->phys_port, spawn->phys_dev_name);
1186 vport_info.query_flags = 0;
1189 if (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) {
1190 priv->vport_meta_tag = vport_info.vport_meta_tag;
1191 priv->vport_meta_mask = vport_info.vport_meta_mask;
1192 if (!priv->vport_meta_mask) {
1194 "vport zero mask for port %d on bonding device %s",
1195 spawn->phys_port, spawn->phys_dev_name);
1199 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
1201 "Invalid vport tag for port %d on bonding device %s",
1202 spawn->phys_port, spawn->phys_dev_name);
1207 if (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) {
1208 priv->vport_id = vport_info.vport_id;
1209 } else if (spawn->pf_bond >= 0 &&
1210 (switch_info->representor || switch_info->master)) {
1212 "Cannot deduce vport index for port %d on bonding device %s",
1213 spawn->phys_port, spawn->phys_dev_name);
1218 * Suppose vport index in compatible way. Kernel/rdma_core
1219 * support single E-Switch per PF configurations only and
1220 * vport_id field contains the vport index for associated VF,
1221 * which is deduced from representor port name.
1222 * For example, let's have the IB device port 10, it has
1223 * attached network device eth0, which has port name attribute
1224 * pf0vf2, we can deduce the VF number as 2, and set vport index
1225 * as 3 (2+1). This assigning schema should be changed if the
1226 * multiple E-Switch instances per PF configurations or/and PCI
1227 * subfunctions are added.
1229 priv->vport_id = switch_info->representor ?
1230 switch_info->port_name + 1 : -1;
1232 priv->representor_id = mlx5_representor_id_encode(switch_info,
1235 * Look for sibling devices in order to reuse their switch domain
1236 * if any, otherwise allocate one.
1238 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
1239 const struct mlx5_priv *opriv =
1240 rte_eth_devices[port_id].data->dev_private;
1243 opriv->sh != priv->sh ||
1245 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1247 priv->domain_id = opriv->domain_id;
1248 DRV_LOG(DEBUG, "dev_port-%u inherit domain_id=%u\n",
1249 priv->dev_port, priv->domain_id);
1252 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1253 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1256 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1257 strerror(rte_errno));
1261 DRV_LOG(DEBUG, "dev_port-%u new domain_id=%u\n",
1262 priv->dev_port, priv->domain_id);
1264 /* Override some values set by hardware configuration. */
1265 mlx5_args(config, dpdk_dev->devargs);
1266 err = mlx5_dev_check_sibling_config(priv, config, dpdk_dev);
1269 config->hw_csum = !!(sh->device_attr.device_cap_flags_ex &
1270 IBV_DEVICE_RAW_IP_CSUM);
1271 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1272 (config->hw_csum ? "" : "not "));
1273 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1274 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1275 DRV_LOG(DEBUG, "counters are not supported");
1277 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
1278 if (config->dv_flow_en) {
1279 DRV_LOG(WARNING, "DV flow is not supported");
1280 config->dv_flow_en = 0;
1283 if (spawn->max_port > UINT8_MAX) {
1284 /* Verbs can't support ports larger than 255 by design. */
1285 DRV_LOG(ERR, "can't support IB ports > UINT8_MAX");
1289 config->ind_table_max_size =
1290 sh->device_attr.max_rwq_indirection_table_size;
1292 * Remove this check once DPDK supports larger/variable
1293 * indirection tables.
1295 if (config->ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1296 config->ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1297 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1298 config->ind_table_max_size);
1299 config->hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
1300 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1301 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1302 (config->hw_vlan_strip ? "" : "not "));
1303 config->hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1304 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1305 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1306 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
1307 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1308 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
1309 IBV_DEVICE_PCI_WRITE_END_PADDING);
1311 if (config->hw_padding && !hw_padding) {
1312 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1313 config->hw_padding = 0;
1314 } else if (config->hw_padding) {
1315 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1317 config->tso = (sh->device_attr.max_tso > 0 &&
1318 (sh->device_attr.tso_supported_qpts &
1319 (1 << IBV_QPT_RAW_PACKET)));
1321 config->tso_max_payload_sz = sh->device_attr.max_tso;
1323 * MPW is disabled by default, while the Enhanced MPW is enabled
1326 if (config->mps == MLX5_ARG_UNSET)
1327 config->mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1330 config->mps = config->mps ? mps : MLX5_MPW_DISABLED;
1331 DRV_LOG(INFO, "%sMPS is %s",
1332 config->mps == MLX5_MPW_ENHANCED ? "enhanced " :
1333 config->mps == MLX5_MPW ? "legacy " : "",
1334 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1336 err = mlx5_devx_cmd_query_hca_attr(sh->cdev->ctx,
1342 /* Check relax ordering support. */
1343 if (!haswell_broadwell_cpu) {
1344 sh->cmng.relaxed_ordering_write =
1345 config->hca_attr.relaxed_ordering_write;
1346 sh->cmng.relaxed_ordering_read =
1347 config->hca_attr.relaxed_ordering_read;
1349 sh->cmng.relaxed_ordering_read = 0;
1350 sh->cmng.relaxed_ordering_write = 0;
1352 sh->rq_ts_format = config->hca_attr.rq_ts_format;
1353 sh->sq_ts_format = config->hca_attr.sq_ts_format;
1354 sh->steering_format_version =
1355 config->hca_attr.steering_format_version;
1356 sh->qp_ts_format = config->hca_attr.qp_ts_format;
1357 /* Check for LRO support. */
1358 if (config->dest_tir && config->hca_attr.lro_cap &&
1359 config->dv_flow_en) {
1360 /* TBD check tunnel lro caps. */
1361 config->lro.supported = config->hca_attr.lro_cap;
1362 DRV_LOG(DEBUG, "Device supports LRO");
1364 * If LRO timeout is not configured by application,
1365 * use the minimal supported value.
1367 if (!config->lro.timeout)
1368 config->lro.timeout =
1369 config->hca_attr.lro_timer_supported_periods[0];
1370 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
1371 config->lro.timeout);
1372 DRV_LOG(DEBUG, "LRO minimal size of TCP segment "
1373 "required for coalescing is %d bytes",
1374 config->hca_attr.lro_min_mss_size);
1376 #if defined(HAVE_MLX5DV_DR) && \
1377 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \
1378 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO))
1379 if (config->hca_attr.qos.sup &&
1380 config->hca_attr.qos.flow_meter_old &&
1381 config->dv_flow_en) {
1382 uint8_t reg_c_mask =
1383 config->hca_attr.qos.flow_meter_reg_c_ids;
1385 * Meter needs two REG_C's for color match and pre-sfx
1386 * flow match. Here get the REG_C for color match.
1387 * REG_C_0 and REG_C_1 is reserved for metadata feature.
1390 if (__builtin_popcount(reg_c_mask) < 1) {
1392 DRV_LOG(WARNING, "No available register for"
1396 * The meter color register is used by the
1397 * flow-hit feature as well.
1398 * The flow-hit feature must use REG_C_3
1399 * Prefer REG_C_3 if it is available.
1401 if (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))
1402 priv->mtr_color_reg = REG_C_3;
1404 priv->mtr_color_reg = ffs(reg_c_mask)
1407 priv->mtr_reg_share =
1408 config->hca_attr.qos.flow_meter;
1409 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
1410 priv->mtr_color_reg);
1413 if (config->hca_attr.qos.sup &&
1414 config->hca_attr.qos.flow_meter_aso_sup) {
1415 uint32_t log_obj_size =
1416 rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
1418 config->hca_attr.qos.log_meter_aso_granularity &&
1420 config->hca_attr.qos.log_meter_aso_max_alloc)
1421 sh->meter_aso_en = 1;
1424 err = mlx5_aso_flow_mtrs_mng_init(priv->sh);
1430 if (config->hca_attr.flow.tunnel_header_0_1)
1431 sh->tunnel_header_0_1 = 1;
1433 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
1434 if (config->hca_attr.flow_hit_aso &&
1435 priv->mtr_color_reg == REG_C_3) {
1436 sh->flow_hit_aso_en = 1;
1437 err = mlx5_flow_aso_age_mng_init(sh);
1442 DRV_LOG(DEBUG, "Flow Hit ASO is supported.");
1444 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
1445 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO) && \
1446 defined(HAVE_MLX5_DR_ACTION_ASO_CT)
1447 if (config->hca_attr.ct_offload &&
1448 priv->mtr_color_reg == REG_C_3) {
1449 err = mlx5_flow_aso_ct_mng_init(sh);
1454 DRV_LOG(DEBUG, "CT ASO is supported.");
1457 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO && HAVE_MLX5_DR_ACTION_ASO_CT */
1458 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)
1459 if (config->hca_attr.log_max_ft_sampler_num > 0 &&
1460 config->dv_flow_en) {
1461 priv->sampler_en = 1;
1462 DRV_LOG(DEBUG, "Sampler enabled!");
1464 priv->sampler_en = 0;
1465 if (!config->hca_attr.log_max_ft_sampler_num)
1467 "No available register for sampler.");
1469 DRV_LOG(DEBUG, "DV flow is not supported!");
1473 if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 &&
1474 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) {
1475 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported");
1476 config->cqe_comp = 0;
1478 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX &&
1479 (!sh->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) {
1480 DRV_LOG(WARNING, "Flow Tag CQE compression"
1481 " format isn't supported.");
1482 config->cqe_comp = 0;
1484 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX &&
1485 (!sh->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) {
1486 DRV_LOG(WARNING, "L3/L4 Header CQE compression"
1487 " format isn't supported.");
1488 config->cqe_comp = 0;
1490 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported",
1491 config->cqe_comp ? "" : "not ");
1492 if (config->tx_pp) {
1493 DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz",
1494 config->hca_attr.dev_freq_khz);
1495 DRV_LOG(DEBUG, "Packet pacing is %ssupported",
1496 config->hca_attr.qos.packet_pacing ? "" : "not ");
1497 DRV_LOG(DEBUG, "Cross channel ops are %ssupported",
1498 config->hca_attr.cross_channel ? "" : "not ");
1499 DRV_LOG(DEBUG, "WQE index ignore is %ssupported",
1500 config->hca_attr.wqe_index_ignore ? "" : "not ");
1501 DRV_LOG(DEBUG, "Non-wire SQ feature is %ssupported",
1502 config->hca_attr.non_wire_sq ? "" : "not ");
1503 DRV_LOG(DEBUG, "Static WQE SQ feature is %ssupported (%d)",
1504 config->hca_attr.log_max_static_sq_wq ? "" : "not ",
1505 config->hca_attr.log_max_static_sq_wq);
1506 DRV_LOG(DEBUG, "WQE rate PP mode is %ssupported",
1507 config->hca_attr.qos.wqe_rate_pp ? "" : "not ");
1509 DRV_LOG(ERR, "DevX is required for packet pacing");
1513 if (!config->hca_attr.qos.packet_pacing) {
1514 DRV_LOG(ERR, "Packet pacing is not supported");
1518 if (!config->hca_attr.cross_channel) {
1519 DRV_LOG(ERR, "Cross channel operations are"
1520 " required for packet pacing");
1524 if (!config->hca_attr.wqe_index_ignore) {
1525 DRV_LOG(ERR, "WQE index ignore feature is"
1526 " required for packet pacing");
1530 if (!config->hca_attr.non_wire_sq) {
1531 DRV_LOG(ERR, "Non-wire SQ feature is"
1532 " required for packet pacing");
1536 if (!config->hca_attr.log_max_static_sq_wq) {
1537 DRV_LOG(ERR, "Static WQE SQ feature is"
1538 " required for packet pacing");
1542 if (!config->hca_attr.qos.wqe_rate_pp) {
1543 DRV_LOG(ERR, "WQE rate mode is required"
1544 " for packet pacing");
1548 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
1549 DRV_LOG(ERR, "DevX does not provide UAR offset,"
1550 " can't create queues for packet pacing");
1556 uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)];
1558 err = config->hca_attr.access_register_user ?
1559 mlx5_devx_cmd_register_read
1560 (sh->cdev->ctx, MLX5_REGISTER_ID_MTUTC, 0,
1561 reg, MLX5_ST_SZ_DW(register_mtutc)) : ENOTSUP;
1565 /* MTUTC register is read successfully. */
1566 ts_mode = MLX5_GET(register_mtutc, reg,
1568 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME)
1569 config->rt_timestamp = 1;
1571 /* Kernel does not support register reading. */
1572 if (config->hca_attr.dev_freq_khz ==
1573 (NS_PER_S / MS_PER_S))
1574 config->rt_timestamp = 1;
1578 * If HW has bug working with tunnel packet decapsulation and
1579 * scatter FCS, and decapsulation is needed, clear the hw_fcs_strip
1580 * bit. Then DEV_RX_OFFLOAD_KEEP_CRC bit will not be set anymore.
1582 if (config->hca_attr.scatter_fcs_w_decap_disable && config->decap_en)
1583 config->hw_fcs_strip = 0;
1584 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1585 (config->hw_fcs_strip ? "" : "not "));
1586 if (config->mprq.enabled && mprq) {
1587 if (config->mprq.stride_num_n &&
1588 (config->mprq.stride_num_n > mprq_max_stride_num_n ||
1589 config->mprq.stride_num_n < mprq_min_stride_num_n)) {
1590 config->mprq.stride_num_n =
1591 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1592 mprq_min_stride_num_n),
1593 mprq_max_stride_num_n);
1595 "the number of strides"
1596 " for Multi-Packet RQ is out of range,"
1597 " setting default value (%u)",
1598 1 << config->mprq.stride_num_n);
1600 if (config->mprq.stride_size_n &&
1601 (config->mprq.stride_size_n > mprq_max_stride_size_n ||
1602 config->mprq.stride_size_n < mprq_min_stride_size_n)) {
1603 config->mprq.stride_size_n =
1604 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
1605 mprq_min_stride_size_n),
1606 mprq_max_stride_size_n);
1608 "the size of a stride"
1609 " for Multi-Packet RQ is out of range,"
1610 " setting default value (%u)",
1611 1 << config->mprq.stride_size_n);
1613 config->mprq.min_stride_size_n = mprq_min_stride_size_n;
1614 config->mprq.max_stride_size_n = mprq_max_stride_size_n;
1615 } else if (config->mprq.enabled && !mprq) {
1616 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1617 config->mprq.enabled = 0;
1619 if (config->max_dump_files_num == 0)
1620 config->max_dump_files_num = 128;
1621 eth_dev = rte_eth_dev_allocate(name);
1622 if (eth_dev == NULL) {
1623 DRV_LOG(ERR, "can not allocate rte ethdev");
1627 if (priv->representor) {
1628 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1629 eth_dev->data->representor_id = priv->representor_id;
1630 MLX5_ETH_FOREACH_DEV(port_id, dpdk_dev) {
1631 struct mlx5_priv *opriv =
1632 rte_eth_devices[port_id].data->dev_private;
1635 opriv->domain_id == priv->domain_id &&
1636 opriv->sh == priv->sh) {
1637 eth_dev->data->backer_port_id = port_id;
1641 if (port_id >= RTE_MAX_ETHPORTS)
1642 eth_dev->data->backer_port_id = eth_dev->data->port_id;
1644 priv->mp_id.port_id = eth_dev->data->port_id;
1645 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
1647 * Store associated network device interface index. This index
1648 * is permanent throughout the lifetime of device. So, we may store
1649 * the ifindex here and use the cached value further.
1651 MLX5_ASSERT(spawn->ifindex);
1652 priv->if_index = spawn->ifindex;
1653 eth_dev->data->dev_private = priv;
1654 priv->dev_data = eth_dev->data;
1655 eth_dev->data->mac_addrs = priv->mac;
1656 eth_dev->device = dpdk_dev;
1657 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1658 /* Configure the first MAC address by default. */
1659 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1661 "port %u cannot get MAC address, is mlx5_en"
1662 " loaded? (errno: %s)",
1663 eth_dev->data->port_id, strerror(rte_errno));
1668 "port %u MAC address is " RTE_ETHER_ADDR_PRT_FMT,
1669 eth_dev->data->port_id, RTE_ETHER_ADDR_BYTES(&mac));
1670 #ifdef RTE_LIBRTE_MLX5_DEBUG
1672 char ifname[MLX5_NAMESIZE];
1674 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1675 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1676 eth_dev->data->port_id, ifname);
1678 DRV_LOG(DEBUG, "port %u ifname is unknown",
1679 eth_dev->data->port_id);
1682 /* Get actual MTU if possible. */
1683 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1688 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1690 /* Initialize burst functions to prevent crashes before link-up. */
1691 eth_dev->rx_pkt_burst = removed_rx_burst;
1692 eth_dev->tx_pkt_burst = removed_tx_burst;
1693 eth_dev->dev_ops = &mlx5_dev_ops;
1694 eth_dev->rx_descriptor_status = mlx5_rx_descriptor_status;
1695 eth_dev->tx_descriptor_status = mlx5_tx_descriptor_status;
1696 eth_dev->rx_queue_count = mlx5_rx_queue_count;
1697 /* Register MAC address. */
1698 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1699 if (config->vf && config->vf_nl_en)
1700 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
1701 mlx5_ifindex(eth_dev),
1702 eth_dev->data->mac_addrs,
1703 MLX5_MAX_MAC_ADDRESSES);
1704 priv->ctrl_flows = 0;
1705 rte_spinlock_init(&priv->flow_list_lock);
1706 TAILQ_INIT(&priv->flow_meters);
1707 priv->mtr_profile_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_PTR);
1708 if (!priv->mtr_profile_tbl)
1710 /* Bring Ethernet device up. */
1711 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1712 eth_dev->data->port_id);
1713 mlx5_set_link_up(eth_dev);
1715 * Even though the interrupt handler is not installed yet,
1716 * interrupts will still trigger on the async_fd from
1717 * Verbs context returned by ibv_open_device().
1719 mlx5_link_update(eth_dev, 0);
1720 #ifdef HAVE_MLX5DV_DR_ESWITCH
1721 if (!(config->hca_attr.eswitch_manager && config->dv_flow_en &&
1722 (switch_info->representor || switch_info->master)))
1723 config->dv_esw_en = 0;
1725 config->dv_esw_en = 0;
1727 /* Detect minimal data bytes to inline. */
1728 mlx5_set_min_inline(spawn, config);
1729 /* Store device configuration on private structure. */
1730 priv->config = *config;
1731 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) {
1732 icfg[i].release_mem_en = !!config->reclaim_mode;
1733 if (config->reclaim_mode)
1734 icfg[i].per_core_cache = 0;
1735 priv->flows[i] = mlx5_ipool_create(&icfg[i]);
1736 if (!priv->flows[i])
1739 /* Create context for virtual machine VLAN workaround. */
1740 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
1741 if (config->dv_flow_en) {
1742 err = mlx5_alloc_shared_dr(priv);
1746 if (sh->devx && config->dv_flow_en && config->dest_tir) {
1747 priv->obj_ops = devx_obj_ops;
1748 priv->obj_ops.drop_action_create =
1749 ibv_obj_ops.drop_action_create;
1750 priv->obj_ops.drop_action_destroy =
1751 ibv_obj_ops.drop_action_destroy;
1752 #ifndef HAVE_MLX5DV_DEVX_UAR_OFFSET
1753 priv->obj_ops.txq_obj_modify = ibv_obj_ops.txq_obj_modify;
1755 if (config->dv_esw_en)
1756 priv->obj_ops.txq_obj_modify =
1757 ibv_obj_ops.txq_obj_modify;
1759 /* Use specific wrappers for Tx object. */
1760 priv->obj_ops.txq_obj_new = mlx5_os_txq_obj_new;
1761 priv->obj_ops.txq_obj_release = mlx5_os_txq_obj_release;
1762 mlx5_queue_counter_id_prepare(eth_dev);
1763 priv->obj_ops.lb_dummy_queue_create =
1764 mlx5_rxq_ibv_obj_dummy_lb_create;
1765 priv->obj_ops.lb_dummy_queue_release =
1766 mlx5_rxq_ibv_obj_dummy_lb_release;
1768 priv->obj_ops = ibv_obj_ops;
1770 if (config->tx_pp &&
1771 (priv->config.dv_esw_en ||
1772 priv->obj_ops.txq_obj_new != mlx5_os_txq_obj_new)) {
1774 * HAVE_MLX5DV_DEVX_UAR_OFFSET is required to support
1775 * packet pacing and already checked above.
1776 * Hence, we should only make sure the SQs will be created
1777 * with DevX, not with Verbs.
1778 * Verbs allocates the SQ UAR on its own and it can't be shared
1779 * with Clock Queue UAR as required for Tx scheduling.
1781 DRV_LOG(ERR, "Verbs SQs, UAR can't be shared as required for packet pacing");
1785 priv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev);
1786 if (!priv->drop_queue.hrxq)
1788 /* Supported Verbs flow priority number detection. */
1789 err = mlx5_flow_discover_priorities(eth_dev);
1794 priv->config.flow_prio = err;
1795 if (!priv->config.dv_esw_en &&
1796 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1797 DRV_LOG(WARNING, "metadata mode %u is not supported "
1798 "(no E-Switch)", priv->config.dv_xmeta_en);
1799 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
1801 mlx5_set_metadata_mask(eth_dev);
1802 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
1803 !priv->sh->dv_regc0_mask) {
1804 DRV_LOG(ERR, "metadata mode %u is not supported "
1805 "(no metadata reg_c[0] is available)",
1806 priv->config.dv_xmeta_en);
1810 priv->hrxqs = mlx5_list_create("hrxq", eth_dev, true,
1811 mlx5_hrxq_create_cb,
1813 mlx5_hrxq_remove_cb,
1815 mlx5_hrxq_clone_free_cb);
1818 rte_rwlock_init(&priv->ind_tbls_lock);
1819 /* Query availability of metadata reg_c's. */
1820 err = mlx5_flow_discover_mreg_c(eth_dev);
1825 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
1827 "port %u extensive metadata register is not supported",
1828 eth_dev->data->port_id);
1829 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1830 DRV_LOG(ERR, "metadata mode %u is not supported "
1831 "(no metadata registers available)",
1832 priv->config.dv_xmeta_en);
1837 if (priv->config.dv_flow_en &&
1838 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
1839 mlx5_flow_ext_mreg_supported(eth_dev) &&
1840 priv->sh->dv_regc0_mask) {
1841 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
1842 MLX5_FLOW_MREG_HTABLE_SZ,
1843 false, true, eth_dev,
1844 flow_dv_mreg_create_cb,
1845 flow_dv_mreg_match_cb,
1846 flow_dv_mreg_remove_cb,
1847 flow_dv_mreg_clone_cb,
1848 flow_dv_mreg_clone_free_cb);
1849 if (!priv->mreg_cp_tbl) {
1854 rte_spinlock_init(&priv->shared_act_sl);
1855 mlx5_flow_counter_mode_config(eth_dev);
1856 mlx5_flow_drop_action_config(eth_dev);
1857 if (priv->config.dv_flow_en)
1858 eth_dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE;
1862 if (priv->mreg_cp_tbl)
1863 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1865 mlx5_os_free_shared_dr(priv);
1866 if (priv->nl_socket_route >= 0)
1867 close(priv->nl_socket_route);
1868 if (priv->nl_socket_rdma >= 0)
1869 close(priv->nl_socket_rdma);
1870 if (priv->vmwa_context)
1871 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1872 if (eth_dev && priv->drop_queue.hrxq)
1873 mlx5_drop_action_destroy(eth_dev);
1874 if (priv->mtr_profile_tbl)
1875 mlx5_l3t_destroy(priv->mtr_profile_tbl);
1877 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1879 mlx5_list_destroy(priv->hrxqs);
1881 if (eth_dev != NULL)
1882 eth_dev->data->dev_private = NULL;
1884 if (eth_dev != NULL) {
1885 /* mac_addrs must not be freed alone because part of
1888 eth_dev->data->mac_addrs = NULL;
1889 rte_eth_dev_release_port(eth_dev);
1892 mlx5_free_shared_dev_ctx(sh);
1893 MLX5_ASSERT(err > 0);
1899 * Comparison callback to sort device data.
1901 * This is meant to be used with qsort().
1904 * Pointer to pointer to first data object.
1906 * Pointer to pointer to second data object.
1909 * 0 if both objects are equal, less than 0 if the first argument is less
1910 * than the second, greater than 0 otherwise.
1913 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1915 const struct mlx5_switch_info *si_a =
1916 &((const struct mlx5_dev_spawn_data *)a)->info;
1917 const struct mlx5_switch_info *si_b =
1918 &((const struct mlx5_dev_spawn_data *)b)->info;
1921 /* Master device first. */
1922 ret = si_b->master - si_a->master;
1925 /* Then representor devices. */
1926 ret = si_b->representor - si_a->representor;
1929 /* Unidentified devices come last in no specific order. */
1930 if (!si_a->representor)
1932 /* Order representors by name. */
1933 return si_a->port_name - si_b->port_name;
1937 * Match PCI information for possible slaves of bonding device.
1939 * @param[in] ibdev_name
1940 * Name of Infiniband device.
1941 * @param[in] pci_dev
1942 * Pointer to primary PCI address structure to match.
1943 * @param[in] nl_rdma
1944 * Netlink RDMA group socket handle.
1946 * Representor owner PF index.
1947 * @param[out] bond_info
1948 * Pointer to bonding information.
1951 * negative value if no bonding device found, otherwise
1952 * positive index of slave PF in bonding.
1955 mlx5_device_bond_pci_match(const char *ibdev_name,
1956 const struct rte_pci_addr *pci_dev,
1957 int nl_rdma, uint16_t owner,
1958 struct mlx5_bond_info *bond_info)
1960 char ifname[IF_NAMESIZE + 1];
1961 unsigned int ifindex;
1963 FILE *bond_file = NULL, *file;
1968 * Try to get master device name. If something goes wrong suppose
1969 * the lack of kernel support and no bonding devices.
1971 memset(bond_info, 0, sizeof(*bond_info));
1974 if (!strstr(ibdev_name, "bond"))
1976 np = mlx5_nl_portnum(nl_rdma, ibdev_name);
1980 * The master device might not be on the predefined port(not on port
1981 * index 1, it is not guaranteed), we have to scan all Infiniband
1982 * device ports and find master.
1984 for (i = 1; i <= np; ++i) {
1985 /* Check whether Infiniband port is populated. */
1986 ifindex = mlx5_nl_ifindex(nl_rdma, ibdev_name, i);
1989 if (!if_indextoname(ifindex, ifname))
1991 /* Try to read bonding slave names from sysfs. */
1993 "/sys/class/net/%s/master/bonding/slaves", ifname);
1994 bond_file = fopen(slaves, "r");
2000 /* Use safe format to check maximal buffer length. */
2001 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2002 while (fscanf(bond_file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2003 char tmp_str[IF_NAMESIZE + 32];
2004 struct rte_pci_addr pci_addr;
2005 struct mlx5_switch_info info;
2007 /* Process slave interface names in the loop. */
2008 snprintf(tmp_str, sizeof(tmp_str),
2009 "/sys/class/net/%s", ifname);
2010 if (mlx5_get_pci_addr(tmp_str, &pci_addr)) {
2012 "Cannot get PCI address for netdev \"%s\".",
2016 /* Slave interface PCI address match found. */
2017 snprintf(tmp_str, sizeof(tmp_str),
2018 "/sys/class/net/%s/phys_port_name", ifname);
2019 file = fopen(tmp_str, "rb");
2022 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2023 if (fscanf(file, "%32s", tmp_str) == 1)
2024 mlx5_translate_port_name(tmp_str, &info);
2026 /* Only process PF ports. */
2027 if (info.name_type != MLX5_PHYS_PORT_NAME_TYPE_LEGACY &&
2028 info.name_type != MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2030 /* Check max bonding member. */
2031 if (info.port_name >= MLX5_BOND_MAX_PORTS) {
2032 DRV_LOG(WARNING, "bonding index out of range, "
2033 "please increase MLX5_BOND_MAX_PORTS: %s",
2037 /* Match PCI address, allows BDF0+pfx or BDFx+pfx. */
2038 if (pci_dev->domain == pci_addr.domain &&
2039 pci_dev->bus == pci_addr.bus &&
2040 pci_dev->devid == pci_addr.devid &&
2041 ((pci_dev->function == 0 &&
2042 pci_dev->function + owner == pci_addr.function) ||
2043 (pci_dev->function == owner &&
2044 pci_addr.function == owner)))
2045 pf = info.port_name;
2047 snprintf(tmp_str, sizeof(tmp_str),
2048 "/sys/class/net/%s/ifindex", ifname);
2049 file = fopen(tmp_str, "rb");
2052 ret = fscanf(file, "%u", &ifindex);
2056 /* Save bonding info. */
2057 strncpy(bond_info->ports[info.port_name].ifname, ifname,
2058 sizeof(bond_info->ports[0].ifname));
2059 bond_info->ports[info.port_name].pci_addr = pci_addr;
2060 bond_info->ports[info.port_name].ifindex = ifindex;
2061 bond_info->n_port++;
2064 /* Get bond interface info */
2065 ret = mlx5_sysfs_bond_info(ifindex, &bond_info->ifindex,
2068 DRV_LOG(ERR, "unable to get bond info: %s",
2069 strerror(rte_errno));
2071 DRV_LOG(INFO, "PF device %u, bond device %u(%s)",
2072 ifindex, bond_info->ifindex, bond_info->ifname);
2078 mlx5_os_config_default(struct mlx5_dev_config *config)
2080 memset(config, 0, sizeof(*config));
2081 config->mps = MLX5_ARG_UNSET;
2082 config->rx_vec_en = 1;
2083 config->txq_inline_max = MLX5_ARG_UNSET;
2084 config->txq_inline_min = MLX5_ARG_UNSET;
2085 config->txq_inline_mpw = MLX5_ARG_UNSET;
2086 config->txqs_inline = MLX5_ARG_UNSET;
2087 config->vf_nl_en = 1;
2088 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN;
2089 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS;
2090 config->dv_esw_en = 1;
2091 config->dv_flow_en = 1;
2092 config->decap_en = 1;
2093 config->log_hp_size = MLX5_ARG_UNSET;
2094 config->allow_duplicate_pattern = 1;
2098 * Register a PCI device within bonding.
2100 * This function spawns Ethernet devices out of a given PCI device and
2101 * bonding owner PF index.
2104 * Pointer to common mlx5 device structure.
2105 * @param[in] req_eth_da
2106 * Requested ethdev device argument.
2107 * @param[in] owner_id
2108 * Requested owner PF port ID within bonding device, default to 0.
2111 * 0 on success, a negative errno value otherwise and rte_errno is set.
2114 mlx5_os_pci_probe_pf(struct mlx5_common_device *cdev,
2115 struct rte_eth_devargs *req_eth_da,
2118 struct ibv_device **ibv_list;
2120 * Number of found IB Devices matching with requested PCI BDF.
2121 * nd != 1 means there are multiple IB devices over the same
2122 * PCI device and we have representors and master.
2124 unsigned int nd = 0;
2126 * Number of found IB device Ports. nd = 1 and np = 1..n means
2127 * we have the single multiport IB device, and there may be
2128 * representors attached to some of found ports.
2130 unsigned int np = 0;
2132 * Number of DPDK ethernet devices to Spawn - either over
2133 * multiple IB devices or multiple ports of single IB device.
2134 * Actually this is the number of iterations to spawn.
2136 unsigned int ns = 0;
2139 * < 0 - no bonding device (single one)
2140 * >= 0 - bonding device (value is slave PF index)
2143 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
2144 struct mlx5_dev_spawn_data *list = NULL;
2145 struct mlx5_dev_config dev_config;
2146 unsigned int dev_config_vf;
2147 struct rte_eth_devargs eth_da = *req_eth_da;
2148 struct rte_pci_addr owner_pci = pci_dev->addr; /* Owner PF. */
2149 struct mlx5_bond_info bond_info;
2153 ibv_list = mlx5_glue->get_device_list(&ret);
2155 rte_errno = errno ? errno : ENOSYS;
2156 DRV_LOG(ERR, "Cannot list devices, is ib_uverbs loaded?");
2160 * First scan the list of all Infiniband devices to find
2161 * matching ones, gathering into the list.
2163 struct ibv_device *ibv_match[ret + 1];
2164 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
2165 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
2169 struct rte_pci_addr pci_addr;
2171 DRV_LOG(DEBUG, "Checking device \"%s\"", ibv_list[ret]->name);
2172 bd = mlx5_device_bond_pci_match(ibv_list[ret]->name, &owner_pci,
2173 nl_rdma, owner_id, &bond_info);
2176 * Bonding device detected. Only one match is allowed,
2177 * the bonding is supported over multi-port IB device,
2178 * there should be no matches on representor PCI
2179 * functions or non VF LAG bonding devices with
2180 * specified address.
2184 "multiple PCI match on bonding device"
2185 "\"%s\" found", ibv_list[ret]->name);
2190 /* Amend owner pci address if owner PF ID specified. */
2191 if (eth_da.nb_representor_ports)
2192 owner_pci.function += owner_id;
2194 "PCI information matches for slave %d bonding device \"%s\"",
2195 bd, ibv_list[ret]->name);
2196 ibv_match[nd++] = ibv_list[ret];
2199 /* Bonding device not found. */
2200 if (mlx5_get_pci_addr(ibv_list[ret]->ibdev_path,
2203 if (owner_pci.domain != pci_addr.domain ||
2204 owner_pci.bus != pci_addr.bus ||
2205 owner_pci.devid != pci_addr.devid ||
2206 owner_pci.function != pci_addr.function)
2208 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
2209 ibv_list[ret]->name);
2210 ibv_match[nd++] = ibv_list[ret];
2213 ibv_match[nd] = NULL;
2215 /* No device matches, just complain and bail out. */
2217 "No Verbs device matches PCI device " PCI_PRI_FMT ","
2218 " are kernel drivers loaded?",
2219 owner_pci.domain, owner_pci.bus,
2220 owner_pci.devid, owner_pci.function);
2227 * Found single matching device may have multiple ports.
2228 * Each port may be representor, we have to check the port
2229 * number and check the representors existence.
2232 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
2235 "Cannot get IB device \"%s\" ports number.",
2236 ibv_match[0]->name);
2237 if (bd >= 0 && !np) {
2238 DRV_LOG(ERR, "Cannot get ports for bonding device.");
2244 /* Now we can determine the maximal amount of devices to be spawned. */
2245 list = mlx5_malloc(MLX5_MEM_ZERO,
2246 sizeof(struct mlx5_dev_spawn_data) * (np ? np : nd),
2247 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
2249 DRV_LOG(ERR, "Spawn data array allocation failure.");
2254 if (bd >= 0 || np > 1) {
2256 * Single IB device with multiple ports found,
2257 * it may be E-Switch master device and representors.
2258 * We have to perform identification through the ports.
2260 MLX5_ASSERT(nl_rdma >= 0);
2261 MLX5_ASSERT(ns == 0);
2262 MLX5_ASSERT(nd == 1);
2264 for (i = 1; i <= np; ++i) {
2265 list[ns].bond_info = &bond_info;
2266 list[ns].max_port = np;
2267 list[ns].phys_port = i;
2268 list[ns].phys_dev_name = ibv_match[0]->name;
2269 list[ns].eth_dev = NULL;
2270 list[ns].pci_dev = pci_dev;
2271 list[ns].cdev = cdev;
2272 list[ns].pf_bond = bd;
2273 list[ns].ifindex = mlx5_nl_ifindex(nl_rdma,
2276 if (!list[ns].ifindex) {
2278 * No network interface index found for the
2279 * specified port, it means there is no
2280 * representor on this port. It's OK,
2281 * there can be disabled ports, for example
2282 * if sriov_numvfs < sriov_totalvfs.
2288 ret = mlx5_nl_switch_info(nl_route,
2291 if (ret || (!list[ns].info.representor &&
2292 !list[ns].info.master)) {
2294 * We failed to recognize representors with
2295 * Netlink, let's try to perform the task
2298 ret = mlx5_sysfs_switch_info(list[ns].ifindex,
2301 if (!ret && bd >= 0) {
2302 switch (list[ns].info.name_type) {
2303 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
2306 * Force standalone bonding
2307 * device for ROCE LAG
2310 list[ns].info.master = 0;
2311 list[ns].info.representor = 0;
2313 if (list[ns].info.port_name == bd)
2316 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF:
2318 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
2320 case MLX5_PHYS_PORT_NAME_TYPE_PFSF:
2321 if (list[ns].info.pf_num == bd)
2329 if (!ret && (list[ns].info.representor ^
2330 list[ns].info.master))
2335 "Unable to recognize master/representors on the IB device with multiple ports.");
2342 * The existence of several matching entries (nd > 1) means
2343 * port representors have been instantiated. No existing Verbs
2344 * call nor sysfs entries can tell them apart, this can only
2345 * be done through Netlink calls assuming kernel drivers are
2346 * recent enough to support them.
2348 * In the event of identification failure through Netlink,
2349 * try again through sysfs, then:
2351 * 1. A single IB device matches (nd == 1) with single
2352 * port (np=0/1) and is not a representor, assume
2353 * no switch support.
2355 * 2. Otherwise no safe assumptions can be made;
2356 * complain louder and bail out.
2358 for (i = 0; i != nd; ++i) {
2359 memset(&list[ns].info, 0, sizeof(list[ns].info));
2360 list[ns].bond_info = NULL;
2361 list[ns].max_port = 1;
2362 list[ns].phys_port = 1;
2363 list[ns].phys_dev_name = ibv_match[i]->name;
2364 list[ns].eth_dev = NULL;
2365 list[ns].pci_dev = pci_dev;
2366 list[ns].cdev = cdev;
2367 list[ns].pf_bond = -1;
2368 list[ns].ifindex = 0;
2370 list[ns].ifindex = mlx5_nl_ifindex
2374 if (!list[ns].ifindex) {
2375 char ifname[IF_NAMESIZE];
2378 * Netlink failed, it may happen with old
2379 * ib_core kernel driver (before 4.16).
2380 * We can assume there is old driver because
2381 * here we are processing single ports IB
2382 * devices. Let's try sysfs to retrieve
2383 * the ifindex. The method works for
2384 * master device only.
2388 * Multiple devices found, assume
2389 * representors, can not distinguish
2390 * master/representor and retrieve
2391 * ifindex via sysfs.
2395 ret = mlx5_get_ifname_sysfs
2396 (ibv_match[i]->ibdev_path, ifname);
2399 if_nametoindex(ifname);
2400 if (!list[ns].ifindex) {
2402 * No network interface index found
2403 * for the specified device, it means
2404 * there it is neither representor
2412 ret = mlx5_nl_switch_info(nl_route,
2415 if (ret || (!list[ns].info.representor &&
2416 !list[ns].info.master)) {
2418 * We failed to recognize representors with
2419 * Netlink, let's try to perform the task
2422 ret = mlx5_sysfs_switch_info(list[ns].ifindex,
2425 if (!ret && (list[ns].info.representor ^
2426 list[ns].info.master)) {
2428 } else if ((nd == 1) &&
2429 !list[ns].info.representor &&
2430 !list[ns].info.master) {
2432 * Single IB device with one physical port and
2433 * attached network device.
2434 * May be SRIOV is not enabled or there is no
2437 DRV_LOG(INFO, "No E-Switch support detected.");
2444 "Unable to recognize master/representors on the multiple IB devices.");
2450 * New kernels may add the switch_id attribute for the case
2451 * there is no E-Switch and we wrongly recognized the only
2452 * device as master. Override this if there is the single
2453 * device with single port and new device name format present.
2456 list[0].info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) {
2457 list[0].info.master = 0;
2458 list[0].info.representor = 0;
2463 * Sort list to probe devices in natural order for users convenience
2464 * (i.e. master first, then representors from lowest to highest ID).
2466 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
2467 /* Device specific configuration. */
2468 switch (pci_dev->id.device_id) {
2469 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2470 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2471 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2472 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2473 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
2474 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
2475 case PCI_DEVICE_ID_MELLANOX_CONNECTXVF:
2482 if (eth_da.type != RTE_ETH_REPRESENTOR_NONE) {
2483 /* Set devargs default values. */
2484 if (eth_da.nb_mh_controllers == 0) {
2485 eth_da.nb_mh_controllers = 1;
2486 eth_da.mh_controllers[0] = 0;
2488 if (eth_da.nb_ports == 0 && ns > 0) {
2489 if (list[0].pf_bond >= 0 && list[0].info.representor)
2490 DRV_LOG(WARNING, "Representor on Bonding device should use pf#vf# syntax: %s",
2491 pci_dev->device.devargs->args);
2492 eth_da.nb_ports = 1;
2493 eth_da.ports[0] = list[0].info.pf_num;
2495 if (eth_da.nb_representor_ports == 0) {
2496 eth_da.nb_representor_ports = 1;
2497 eth_da.representor_ports[0] = 0;
2500 for (i = 0; i != ns; ++i) {
2503 /* Default configuration. */
2504 mlx5_os_config_default(&dev_config);
2505 dev_config.vf = dev_config_vf;
2506 list[i].eth_dev = mlx5_dev_spawn(cdev->dev, &list[i],
2507 &dev_config, ð_da);
2508 if (!list[i].eth_dev) {
2509 if (rte_errno != EBUSY && rte_errno != EEXIST)
2511 /* Device is disabled or already spawned. Ignore it. */
2514 restore = list[i].eth_dev->data->dev_flags;
2515 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
2517 * Each representor has a dedicated interrupts vector.
2518 * rte_eth_copy_pci_info() assigns PF interrupts handle to
2519 * representor eth_dev object because representor and PF
2520 * share the same PCI address.
2521 * Override representor device with a dedicated
2522 * interrupts handle here.
2523 * Representor interrupts handle is released in mlx5_dev_stop().
2525 if (list[i].info.representor) {
2526 struct rte_intr_handle *intr_handle;
2527 intr_handle = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO,
2528 sizeof(*intr_handle), 0,
2532 "port %u failed to allocate memory for interrupt handler "
2533 "Rx interrupts will not be supported",
2539 list[i].eth_dev->intr_handle = intr_handle;
2541 /* Restore non-PCI flags cleared by the above call. */
2542 list[i].eth_dev->data->dev_flags |= restore;
2543 rte_eth_dev_probing_finish(list[i].eth_dev);
2547 "probe of PCI device " PCI_PRI_FMT " aborted after"
2548 " encountering an error: %s",
2549 owner_pci.domain, owner_pci.bus,
2550 owner_pci.devid, owner_pci.function,
2551 strerror(rte_errno));
2555 if (!list[i].eth_dev)
2557 mlx5_dev_close(list[i].eth_dev);
2558 /* mac_addrs must not be freed because in dev_private */
2559 list[i].eth_dev->data->mac_addrs = NULL;
2560 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
2562 /* Restore original error. */
2569 * Do the routine cleanup:
2570 * - close opened Netlink sockets
2571 * - free allocated spawn data array
2572 * - free the Infiniband device list
2580 MLX5_ASSERT(ibv_list);
2581 mlx5_glue->free_device_list(ibv_list);
2586 mlx5_os_parse_eth_devargs(struct rte_device *dev,
2587 struct rte_eth_devargs *eth_da)
2591 if (dev->devargs == NULL)
2593 memset(eth_da, 0, sizeof(*eth_da));
2594 /* Parse representor information first from class argument. */
2595 if (dev->devargs->cls_str)
2596 ret = rte_eth_devargs_parse(dev->devargs->cls_str, eth_da);
2598 DRV_LOG(ERR, "failed to parse device arguments: %s",
2599 dev->devargs->cls_str);
2602 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) {
2603 /* Parse legacy device argument */
2604 ret = rte_eth_devargs_parse(dev->devargs->args, eth_da);
2606 DRV_LOG(ERR, "failed to parse device arguments: %s",
2607 dev->devargs->args);
2615 * Callback to register a PCI device.
2617 * This function spawns Ethernet devices out of a given PCI device.
2620 * Pointer to common mlx5 device structure.
2623 * 0 on success, a negative errno value otherwise and rte_errno is set.
2626 mlx5_os_pci_probe(struct mlx5_common_device *cdev)
2628 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(cdev->dev);
2629 struct rte_eth_devargs eth_da = { .nb_ports = 0 };
2633 ret = mlx5_os_parse_eth_devargs(cdev->dev, ð_da);
2637 if (eth_da.nb_ports > 0) {
2638 /* Iterate all port if devargs pf is range: "pf[0-1]vf[...]". */
2639 for (p = 0; p < eth_da.nb_ports; p++) {
2640 ret = mlx5_os_pci_probe_pf(cdev, ð_da,
2646 DRV_LOG(ERR, "Probe of PCI device " PCI_PRI_FMT " "
2647 "aborted due to proding failure of PF %u",
2648 pci_dev->addr.domain, pci_dev->addr.bus,
2649 pci_dev->addr.devid, pci_dev->addr.function,
2651 mlx5_net_remove(cdev);
2654 ret = mlx5_os_pci_probe_pf(cdev, ð_da, 0);
2659 /* Probe a single SF device on auxiliary bus, no representor support. */
2661 mlx5_os_auxiliary_probe(struct mlx5_common_device *cdev)
2663 struct rte_eth_devargs eth_da = { .nb_ports = 0 };
2664 struct mlx5_dev_config config;
2665 struct mlx5_dev_spawn_data spawn = { .pf_bond = -1 };
2666 struct rte_device *dev = cdev->dev;
2667 struct rte_auxiliary_device *adev = RTE_DEV_TO_AUXILIARY(dev);
2668 struct rte_eth_dev *eth_dev;
2671 /* Parse ethdev devargs. */
2672 ret = mlx5_os_parse_eth_devargs(dev, ð_da);
2675 /* Set default config data. */
2676 mlx5_os_config_default(&config);
2678 /* Init spawn data. */
2680 spawn.phys_port = 1;
2681 spawn.phys_dev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
2682 ret = mlx5_auxiliary_get_ifindex(dev->name);
2684 DRV_LOG(ERR, "failed to get ethdev ifindex: %s", dev->name);
2687 spawn.ifindex = ret;
2690 eth_dev = mlx5_dev_spawn(dev, &spawn, &config, ð_da);
2691 if (eth_dev == NULL)
2694 eth_dev->intr_handle = &adev->intr_handle;
2695 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2696 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2697 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_RMV;
2698 eth_dev->data->numa_node = dev->numa_node;
2700 rte_eth_dev_probing_finish(eth_dev);
2705 * Net class driver callback to probe a device.
2707 * This function probe PCI bus device(s) or a single SF on auxiliary bus.
2710 * Pointer to the common mlx5 device.
2713 * 0 on success, a negative errno value otherwise and rte_errno is set.
2716 mlx5_os_net_probe(struct mlx5_common_device *cdev)
2720 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2721 mlx5_pmd_socket_init();
2722 ret = mlx5_init_once();
2724 DRV_LOG(ERR, "Unable to init PMD global data: %s",
2725 strerror(rte_errno));
2728 if (mlx5_dev_is_pci(cdev->dev))
2729 return mlx5_os_pci_probe(cdev);
2731 return mlx5_os_auxiliary_probe(cdev);
2735 * Extract pdn of PD object using DV API.
2738 * Pointer to the verbs PD object.
2740 * Pointer to the PD object number variable.
2743 * 0 on success, error value otherwise.
2746 mlx5_os_get_pdn(void *pd, uint32_t *pdn)
2748 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2749 struct mlx5dv_obj obj;
2750 struct mlx5dv_pd pd_info;
2754 obj.pd.out = &pd_info;
2755 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
2757 DRV_LOG(DEBUG, "Fail to get PD object info");
2766 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
2770 * Install shared asynchronous device events handler.
2771 * This function is implemented to support event sharing
2772 * between multiple ports of single IB device.
2775 * Pointer to mlx5_dev_ctx_shared object.
2778 mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh)
2782 struct ibv_context *ctx = sh->cdev->ctx;
2784 sh->intr_handle.fd = -1;
2785 flags = fcntl(ctx->async_fd, F_GETFL);
2786 ret = fcntl(ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
2788 DRV_LOG(INFO, "failed to change file descriptor async event"
2791 sh->intr_handle.fd = ctx->async_fd;
2792 sh->intr_handle.type = RTE_INTR_HANDLE_EXT;
2793 if (rte_intr_callback_register(&sh->intr_handle,
2794 mlx5_dev_interrupt_handler, sh)) {
2795 DRV_LOG(INFO, "Fail to install the shared interrupt.");
2796 sh->intr_handle.fd = -1;
2800 #ifdef HAVE_IBV_DEVX_ASYNC
2801 sh->intr_handle_devx.fd = -1;
2802 sh->devx_comp = (void *)mlx5_glue->devx_create_cmd_comp(ctx);
2803 struct mlx5dv_devx_cmd_comp *devx_comp = sh->devx_comp;
2805 DRV_LOG(INFO, "failed to allocate devx_comp.");
2808 flags = fcntl(devx_comp->fd, F_GETFL);
2809 ret = fcntl(devx_comp->fd, F_SETFL, flags | O_NONBLOCK);
2811 DRV_LOG(INFO, "failed to change file descriptor"
2815 sh->intr_handle_devx.fd = devx_comp->fd;
2816 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT;
2817 if (rte_intr_callback_register(&sh->intr_handle_devx,
2818 mlx5_dev_interrupt_handler_devx, sh)) {
2819 DRV_LOG(INFO, "Fail to install the devx shared"
2821 sh->intr_handle_devx.fd = -1;
2823 #endif /* HAVE_IBV_DEVX_ASYNC */
2828 * Uninstall shared asynchronous device events handler.
2829 * This function is implemented to support event sharing
2830 * between multiple ports of single IB device.
2833 * Pointer to mlx5_dev_ctx_shared object.
2836 mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh)
2838 if (sh->intr_handle.fd >= 0)
2839 mlx5_intr_callback_unregister(&sh->intr_handle,
2840 mlx5_dev_interrupt_handler, sh);
2841 #ifdef HAVE_IBV_DEVX_ASYNC
2842 if (sh->intr_handle_devx.fd >= 0)
2843 rte_intr_callback_unregister(&sh->intr_handle_devx,
2844 mlx5_dev_interrupt_handler_devx, sh);
2846 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp);
2851 * Read statistics by a named counter.
2854 * Pointer to the private device data structure.
2855 * @param[in] ctr_name
2856 * Pointer to the name of the statistic counter to read
2858 * Pointer to read statistic value.
2860 * 0 on success and stat is valud, 1 if failed to read the value
2865 mlx5_os_read_dev_stat(struct mlx5_priv *priv, const char *ctr_name,
2871 if (priv->q_counters != NULL &&
2872 strcmp(ctr_name, "out_of_buffer") == 0)
2873 return mlx5_devx_cmd_queue_counter_query
2874 (priv->q_counters, 0, (uint32_t *)stat);
2875 MKSTR(path, "%s/ports/%d/hw_counters/%s",
2876 priv->sh->ibdev_path,
2879 fd = open(path, O_RDONLY);
2881 * in switchdev the file location is not per port
2882 * but rather in <ibdev_path>/hw_counters/<file_name>.
2885 MKSTR(path1, "%s/hw_counters/%s",
2886 priv->sh->ibdev_path,
2888 fd = open(path1, O_RDONLY);
2891 char buf[21] = {'\0'};
2892 ssize_t n = read(fd, buf, sizeof(buf));
2896 *stat = strtoull(buf, NULL, 10);
2906 * Set the reg_mr and dereg_mr call backs
2908 * @param reg_mr_cb[out]
2909 * Pointer to reg_mr func
2910 * @param dereg_mr_cb[out]
2911 * Pointer to dereg_mr func
2915 mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb,
2916 mlx5_dereg_mr_t *dereg_mr_cb)
2918 *reg_mr_cb = mlx5_mr_verbs_ops.reg_mr;
2919 *dereg_mr_cb = mlx5_mr_verbs_ops.dereg_mr;
2923 * Remove a MAC address from device
2926 * Pointer to Ethernet device structure.
2928 * MAC address index.
2931 mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index)
2933 struct mlx5_priv *priv = dev->data->dev_private;
2934 const int vf = priv->config.vf;
2937 mlx5_nl_mac_addr_remove(priv->nl_socket_route,
2938 mlx5_ifindex(dev), priv->mac_own,
2939 &dev->data->mac_addrs[index], index);
2943 * Adds a MAC address to the device
2946 * Pointer to Ethernet device structure.
2948 * MAC address to register.
2950 * MAC address index.
2953 * 0 on success, a negative errno value otherwise
2956 mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
2959 struct mlx5_priv *priv = dev->data->dev_private;
2960 const int vf = priv->config.vf;
2964 ret = mlx5_nl_mac_addr_add(priv->nl_socket_route,
2965 mlx5_ifindex(dev), priv->mac_own,
2971 * Modify a VF MAC address
2974 * Pointer to device private data.
2976 * MAC address to modify into.
2978 * Net device interface index
2983 * 0 on success, a negative errno value otherwise
2986 mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv,
2987 unsigned int iface_idx,
2988 struct rte_ether_addr *mac_addr,
2991 return mlx5_nl_vf_mac_addr_modify
2992 (priv->nl_socket_route, iface_idx, mac_addr, vf_index);
2996 * Set device promiscuous mode
2999 * Pointer to Ethernet device structure.
3001 * 0 - promiscuous is disabled, otherwise - enabled
3004 * 0 on success, a negative error value otherwise
3007 mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable)
3009 struct mlx5_priv *priv = dev->data->dev_private;
3011 return mlx5_nl_promisc(priv->nl_socket_route,
3012 mlx5_ifindex(dev), !!enable);
3016 * Set device promiscuous mode
3019 * Pointer to Ethernet device structure.
3021 * 0 - all multicase is disabled, otherwise - enabled
3024 * 0 on success, a negative error value otherwise
3027 mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable)
3029 struct mlx5_priv *priv = dev->data->dev_private;
3031 return mlx5_nl_allmulti(priv->nl_socket_route,
3032 mlx5_ifindex(dev), !!enable);
3036 * Flush device MAC addresses
3039 * Pointer to Ethernet device structure.
3043 mlx5_os_mac_addr_flush(struct rte_eth_dev *dev)
3045 struct mlx5_priv *priv = dev->data->dev_private;
3047 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
3048 dev->data->mac_addrs,
3049 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);