drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 184
 185 /* Shared memory between primary and secondary processes. */
 186 struct mlx5_shared_data *mlx5_shared_data;
 187
 188 /* Spinlock for mlx5_shared_data allocation. */
 189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 190
 191 /* Process local data for secondary processes. */
 192 static struct mlx5_local_data mlx5_local_data;
 193
 194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 195                                                 LIST_HEAD_INITIALIZER();
 196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 197
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 0,
 206                 .release_mem_en = 1,
 207                 .malloc = rte_malloc_socket,
 208                 .free = rte_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 0,
 217                 .release_mem_en = 1,
 218                 .malloc = rte_malloc_socket,
 219                 .free = rte_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 0,
 228                 .release_mem_en = 1,
 229                 .malloc = rte_malloc_socket,
 230                 .free = rte_free,
 231                 .type = "mlx5_tag_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 0,
 239                 .release_mem_en = 1,
 240                 .malloc = rte_malloc_socket,
 241                 .free = rte_free,
 242                 .type = "mlx5_port_id_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 0,
 250                 .release_mem_en = 1,
 251                 .malloc = rte_malloc_socket,
 252                 .free = rte_free,
 253                 .type = "mlx5_jump_ipool",
 254         },
 255 #endif
 256         {
 257                 .size = sizeof(struct mlx5_flow_meter),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 0,
 262                 .release_mem_en = 1,
 263                 .malloc = rte_malloc_socket,
 264                 .free = rte_free,
 265                 .type = "mlx5_meter_ipool",
 266         },
 267         {
 268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 0,
 273                 .release_mem_en = 1,
 274                 .malloc = rte_malloc_socket,
 275                 .free = rte_free,
 276                 .type = "mlx5_mcp_ipool",
 277         },
 278         {
 279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_hrxq_ipool",
 288         },
 289         {
 290                 /*
 291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 292                  * It set in run time according to PCI function configuration.
 293                  */
 294                 .size = 0,
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 0,
 299                 .release_mem_en = 1,
 300                 .malloc = rte_malloc_socket,
 301                 .free = rte_free,
 302                 .type = "mlx5_flow_handle_ipool",
 303         },
 304         {
 305                 .size = sizeof(struct rte_flow),
 306                 .trunk_size = 4096,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = rte_malloc_socket,
 310                 .free = rte_free,
 311                 .type = "rte_flow_ipool",
 312         },
 313 };
 314
 315
 316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 318
 319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_dev_ctx_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 476                 sh->cmng.ccont[i].max_id = -1;
 477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 482         }
 483 }
 484
 485 /**
 486  * Destroy all the resources allocated for a counter memory management.
 487  *
 488  * @param[in] mng
 489  *   Pointer to the memory management structure.
 490  */
 491 static void
 492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 493 {
 494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 495
 496         LIST_REMOVE(mng, next);
 497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 499         rte_free(mem);
 500 }
 501
 502 /**
 503  * Close and release all the resources of the counters management.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_dev_ctx_shared object to free.
 507  */
 508 static void
 509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 510 {
 511         struct mlx5_counter_stats_mem_mng *mng;
 512         int i;
 513         int j;
 514         int retries = 1024;
 515
 516         rte_errno = 0;
 517         while (--retries) {
 518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 519                 if (rte_errno != EINPROGRESS)
 520                         break;
 521                 rte_pause();
 522         }
 523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 524                 struct mlx5_flow_counter_pool *pool;
 525                 uint32_t batch = !!(i > 1);
 526
 527                 if (!sh->cmng.ccont[i].pools)
 528                         continue;
 529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 530                 while (pool) {
 531                         if (batch && pool->min_dcs)
 532                                 claim_zero(mlx5_devx_cmd_destroy
 533                                                                (pool->min_dcs));
 534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 536                                         claim_zero
 537                                          (mlx5_glue->destroy_flow_action
 538                                           (MLX5_POOL_GET_CNT
 539                                           (pool, j)->action));
 540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 541                                     (pool, j)->dcs)
 542                                         claim_zero(mlx5_devx_cmd_destroy
 543                                                    (MLX5_GET_POOL_CNT_EXT
 544                                                     (pool, j)->dcs));
 545                         }
 546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 547                         rte_free(pool);
 548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 549                 }
 550                 rte_free(sh->cmng.ccont[i].pools);
 551         }
 552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 553         while (mng) {
 554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         }
 557         memset(&sh->cmng, 0, sizeof(sh->cmng));
 558 }
 559
 560 /**
 561  * Initialize the flow resources' indexed mempool.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object.
 565  * @param[in] sh
 566  *   Pointer to user dev config.
 567  */
 568 static void
 569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 570                        const struct mlx5_dev_config *config)
 571 {
 572         uint8_t i;
 573         struct mlx5_indexed_pool_config cfg;
 574
 575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 576                 cfg = mlx5_ipool_cfg[i];
 577                 switch (i) {
 578                 default:
 579                         break;
 580                 /*
 581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 582                  * according to PCI function flow configuration.
 583                  */
 584                 case MLX5_IPOOL_MLX5_FLOW:
 585                         cfg.size = config->dv_flow_en ?
 586                                 sizeof(struct mlx5_flow_handle) :
 587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 588                         break;
 589                 }
 590                 if (config->reclaim_mode)
 591                         cfg.release_mem_en = 1;
 592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 593         }
 594 }
 595
 596 /**
 597  * Release the flow resources' indexed mempool.
 598  *
 599  * @param[in] sh
 600  *   Pointer to mlx5_dev_ctx_shared object.
 601  */
 602 static void
 603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 604 {
 605         uint8_t i;
 606
 607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 608                 mlx5_ipool_destroy(sh->ipool[i]);
 609 }
 610
 611 /**
 612  * Allocate shared device context. If there is multiport device the
 613  * master and representors will share this context, if there is single
 614  * port dedicated device, the context will be used by only given
 615  * port due to unification.
 616  *
 617  * Routine first searches the context for the specified device name,
 618  * if found the shared context assumed and reference counter is incremented.
 619  * If no context found the new one is created and initialized with specified
 620  * device context and parameters.
 621  *
 622  * @param[in] spawn
 623  *   Pointer to the device attributes (name, port, etc).
 624  * @param[in] config
 625  *   Pointer to device configuration structure.
 626  *
 627  * @return
 628  *   Pointer to mlx5_dev_ctx_shared object on success,
 629  *   otherwise NULL and rte_errno is set.
 630  */
 631 struct mlx5_dev_ctx_shared *
 632 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 633                            const struct mlx5_dev_config *config)
 634 {
 635         struct mlx5_dev_ctx_shared *sh;
 636         int err = 0;
 637         uint32_t i;
 638         struct mlx5_devx_tis_attr tis_attr = { 0 };
 639
 640         MLX5_ASSERT(spawn);
 641         /* Secondary process should not create the shared context. */
 642         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 643         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 644         /* Search for IB context by device name. */
 645         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 646                 if (!strcmp(sh->ibdev_name,
 647                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 648                         sh->refcnt++;
 649                         goto exit;
 650                 }
 651         }
 652         /* No device found, we have to create new shared context. */
 653         MLX5_ASSERT(spawn->max_port);
 654         sh = rte_zmalloc("ethdev shared ib context",
 655                          sizeof(struct mlx5_dev_ctx_shared) +
 656                          spawn->max_port *
 657                          sizeof(struct mlx5_dev_shared_port),
 658                          RTE_CACHE_LINE_SIZE);
 659         if (!sh) {
 660                 DRV_LOG(ERR, "shared context allocation failure");
 661                 rte_errno  = ENOMEM;
 662                 goto exit;
 663         }
 664         err = mlx5_os_open_device(spawn, config, sh);
 665         if (!sh->ctx)
 666                 goto error;
 667         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 668         if (err) {
 669                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 670                 goto error;
 671         }
 672         sh->refcnt = 1;
 673         sh->max_port = spawn->max_port;
 674         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 675                 sizeof(sh->ibdev_name) - 1);
 676         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 677                 sizeof(sh->ibdev_path) - 1);
 678         /*
 679          * Setting port_id to max unallowed value means
 680          * there is no interrupt subhandler installed for
 681          * the given port index i.
 682          */
 683         for (i = 0; i < sh->max_port; i++) {
 684                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 685                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 686         }
 687         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 688         if (sh->pd == NULL) {
 689                 DRV_LOG(ERR, "PD allocation failure");
 690                 err = ENOMEM;
 691                 goto error;
 692         }
 693         if (sh->devx) {
 694                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 695                 if (err) {
 696                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 697                         goto error;
 698                 }
 699                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 700                 if (!sh->td) {
 701                         DRV_LOG(ERR, "TD allocation failure");
 702                         err = ENOMEM;
 703                         goto error;
 704                 }
 705                 tis_attr.transport_domain = sh->td->id;
 706                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 707                 if (!sh->tis) {
 708                         DRV_LOG(ERR, "TIS allocation failure");
 709                         err = ENOMEM;
 710                         goto error;
 711                 }
 712         }
 713         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 714                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 715         if (!sh->flow_id_pool) {
 716                 DRV_LOG(ERR, "can't create flow id pool");
 717                 err = ENOMEM;
 718                 goto error;
 719         }
 720 #ifndef RTE_ARCH_64
 721         /* Initialize UAR access locks for 32bit implementations. */
 722         rte_spinlock_init(&sh->uar_lock_cq);
 723         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 724                 rte_spinlock_init(&sh->uar_lock[i]);
 725 #endif
 726         /*
 727          * Once the device is added to the list of memory event
 728          * callback, its global MR cache table cannot be expanded
 729          * on the fly because of deadlock. If it overflows, lookup
 730          * should be done by searching MR list linearly, which is slow.
 731          *
 732          * At this point the device is not added to the memory
 733          * event list yet, context is just being created.
 734          */
 735         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 736                                  MLX5_MR_BTREE_CACHE_N * 2,
 737                                  spawn->pci_dev->device.numa_node);
 738         if (err) {
 739                 err = rte_errno;
 740                 goto error;
 741         }
 742         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 743                               &sh->share_cache.dereg_mr_cb);
 744         mlx5_os_dev_shared_handler_install(sh);
 745         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 746         if (!sh->cnt_id_tbl) {
 747                 err = rte_errno;
 748                 goto error;
 749         }
 750         mlx5_flow_aging_init(sh);
 751         mlx5_flow_counters_mng_init(sh);
 752         mlx5_flow_ipool_create(sh, config);
 753         /* Add device to memory callback list. */
 754         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 755         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 756                          sh, mem_event_cb);
 757         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 758         /* Add context to the global device list. */
 759         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 760 exit:
 761         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 762         return sh;
 763 error:
 764         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 765         MLX5_ASSERT(sh);
 766         if (sh->cnt_id_tbl) {
 767                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 768                 sh->cnt_id_tbl = NULL;
 769         }
 770         if (sh->tis)
 771                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 772         if (sh->td)
 773                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 774         if (sh->pd)
 775                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 776         if (sh->ctx)
 777                 claim_zero(mlx5_glue->close_device(sh->ctx));
 778         if (sh->flow_id_pool)
 779                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 780         rte_free(sh);
 781         MLX5_ASSERT(err > 0);
 782         rte_errno = err;
 783         return NULL;
 784 }
 785
 786 /**
 787  * Free shared IB device context. Decrement counter and if zero free
 788  * all allocated resources and close handles.
 789  *
 790  * @param[in] sh
 791  *   Pointer to mlx5_dev_ctx_shared object to free
 792  */
 793 void
 794 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 795 {
 796         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 797 #ifdef RTE_LIBRTE_MLX5_DEBUG
 798         /* Check the object presence in the list. */
 799         struct mlx5_dev_ctx_shared *lctx;
 800
 801         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 802                 if (lctx == sh)
 803                         break;
 804         MLX5_ASSERT(lctx);
 805         if (lctx != sh) {
 806                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 807                 goto exit;
 808         }
 809 #endif
 810         MLX5_ASSERT(sh);
 811         MLX5_ASSERT(sh->refcnt);
 812         /* Secondary process should not free the shared context. */
 813         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 814         if (--sh->refcnt)
 815                 goto exit;
 816         /* Remove from memory callback device list. */
 817         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 818         LIST_REMOVE(sh, mem_event_cb);
 819         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 820         /* Release created Memory Regions. */
 821         mlx5_mr_release_cache(&sh->share_cache);
 822         /* Remove context from the global device list. */
 823         LIST_REMOVE(sh, next);
 824         /*
 825          *  Ensure there is no async event handler installed.
 826          *  Only primary process handles async device events.
 827          **/
 828         mlx5_flow_counters_mng_close(sh);
 829         mlx5_flow_ipool_destroy(sh);
 830         mlx5_os_dev_shared_handler_uninstall(sh);
 831         if (sh->cnt_id_tbl) {
 832                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 833                 sh->cnt_id_tbl = NULL;
 834         }
 835         if (sh->pd)
 836                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 837         if (sh->tis)
 838                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 839         if (sh->td)
 840                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 841         if (sh->ctx)
 842                 claim_zero(mlx5_glue->close_device(sh->ctx));
 843         if (sh->flow_id_pool)
 844                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 845         rte_free(sh);
 846 exit:
 847         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 848 }
 849
 850 /**
 851  * Destroy table hash list and all the root entries per domain.
 852  *
 853  * @param[in] priv
 854  *   Pointer to the private device data structure.
 855  */
 856 void
 857 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 858 {
 859         struct mlx5_dev_ctx_shared *sh = priv->sh;
 860         struct mlx5_flow_tbl_data_entry *tbl_data;
 861         union mlx5_flow_tbl_key table_key = {
 862                 {
 863                         .table_id = 0,
 864                         .reserved = 0,
 865                         .domain = 0,
 866                         .direction = 0,
 867                 }
 868         };
 869         struct mlx5_hlist_entry *pos;
 870
 871         if (!sh->flow_tbls)
 872                 return;
 873         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 874         if (pos) {
 875                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 876                                         entry);
 877                 MLX5_ASSERT(tbl_data);
 878                 mlx5_hlist_remove(sh->flow_tbls, pos);
 879                 rte_free(tbl_data);
 880         }
 881         table_key.direction = 1;
 882         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 883         if (pos) {
 884                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 885                                         entry);
 886                 MLX5_ASSERT(tbl_data);
 887                 mlx5_hlist_remove(sh->flow_tbls, pos);
 888                 rte_free(tbl_data);
 889         }
 890         table_key.direction = 0;
 891         table_key.domain = 1;
 892         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 893         if (pos) {
 894                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 895                                         entry);
 896                 MLX5_ASSERT(tbl_data);
 897                 mlx5_hlist_remove(sh->flow_tbls, pos);
 898                 rte_free(tbl_data);
 899         }
 900         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 901 }
 902
 903 /**
 904  * Initialize flow table hash list and create the root tables entry
 905  * for each domain.
 906  *
 907  * @param[in] priv
 908  *   Pointer to the private device data structure.
 909  *
 910  * @return
 911  *   Zero on success, positive error code otherwise.
 912  */
 913 int
 914 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 915 {
 916         struct mlx5_dev_ctx_shared *sh = priv->sh;
 917         char s[MLX5_HLIST_NAMESIZE];
 918         int err = 0;
 919
 920         MLX5_ASSERT(sh);
 921         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 922         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 923         if (!sh->flow_tbls) {
 924                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 925                 err = ENOMEM;
 926                 return err;
 927         }
 928 #ifndef HAVE_MLX5DV_DR
 929         /*
 930          * In case we have not DR support, the zero tables should be created
 931          * because DV expect to see them even if they cannot be created by
 932          * RDMA-CORE.
 933          */
 934         union mlx5_flow_tbl_key table_key = {
 935                 {
 936                         .table_id = 0,
 937                         .reserved = 0,
 938                         .domain = 0,
 939                         .direction = 0,
 940                 }
 941         };
 942         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 943                                                           sizeof(*tbl_data), 0);
 944
 945         if (!tbl_data) {
 946                 err = ENOMEM;
 947                 goto error;
 948         }
 949         tbl_data->entry.key = table_key.v64;
 950         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 951         if (err)
 952                 goto error;
 953         rte_atomic32_init(&tbl_data->tbl.refcnt);
 954         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 955         table_key.direction = 1;
 956         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 957         if (!tbl_data) {
 958                 err = ENOMEM;
 959                 goto error;
 960         }
 961         tbl_data->entry.key = table_key.v64;
 962         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 963         if (err)
 964                 goto error;
 965         rte_atomic32_init(&tbl_data->tbl.refcnt);
 966         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 967         table_key.direction = 0;
 968         table_key.domain = 1;
 969         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 970         if (!tbl_data) {
 971                 err = ENOMEM;
 972                 goto error;
 973         }
 974         tbl_data->entry.key = table_key.v64;
 975         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 976         if (err)
 977                 goto error;
 978         rte_atomic32_init(&tbl_data->tbl.refcnt);
 979         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 980         return err;
 981 error:
 982         mlx5_free_table_hash_list(priv);
 983 #endif /* HAVE_MLX5DV_DR */
 984         return err;
 985 }
 986
 987 /**
 988  * Initialize shared data between primary and secondary process.
 989  *
 990  * A memzone is reserved by primary process and secondary processes attach to
 991  * the memzone.
 992  *
 993  * @return
 994  *   0 on success, a negative errno value otherwise and rte_errno is set.
 995  */
 996 static int
 997 mlx5_init_shared_data(void)
 998 {
 999         const struct rte_memzone *mz;
1000         int ret = 0;
1001
1002         rte_spinlock_lock(&mlx5_shared_data_lock);
1003         if (mlx5_shared_data == NULL) {
1004                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1005                         /* Allocate shared memory. */
1006                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1007                                                  sizeof(*mlx5_shared_data),
1008                                                  SOCKET_ID_ANY, 0);
1009                         if (mz == NULL) {
1010                                 DRV_LOG(ERR,
1011                                         "Cannot allocate mlx5 shared data");
1012                                 ret = -rte_errno;
1013                                 goto error;
1014                         }
1015                         mlx5_shared_data = mz->addr;
1016                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1017                         rte_spinlock_init(&mlx5_shared_data->lock);
1018                 } else {
1019                         /* Lookup allocated shared memory. */
1020                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1021                         if (mz == NULL) {
1022                                 DRV_LOG(ERR,
1023                                         "Cannot attach mlx5 shared data");
1024                                 ret = -rte_errno;
1025                                 goto error;
1026                         }
1027                         mlx5_shared_data = mz->addr;
1028                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1029                 }
1030         }
1031 error:
1032         rte_spinlock_unlock(&mlx5_shared_data_lock);
1033         return ret;
1034 }
1035
1036 /**
1037  * Retrieve integer value from environment variable.
1038  *
1039  * @param[in] name
1040  *   Environment variable name.
1041  *
1042  * @return
1043  *   Integer value, 0 if the variable is not set.
1044  */
1045 int
1046 mlx5_getenv_int(const char *name)
1047 {
1048         const char *val = getenv(name);
1049
1050         if (val == NULL)
1051                 return 0;
1052         return atoi(val);
1053 }
1054
1055 /**
1056  * DPDK callback to add udp tunnel port
1057  *
1058  * @param[in] dev
1059  *   A pointer to eth_dev
1060  * @param[in] udp_tunnel
1061  *   A pointer to udp tunnel
1062  *
1063  * @return
1064  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1065  */
1066 int
1067 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1068                          struct rte_eth_udp_tunnel *udp_tunnel)
1069 {
1070         MLX5_ASSERT(udp_tunnel != NULL);
1071         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1072             udp_tunnel->udp_port == 4789)
1073                 return 0;
1074         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1075             udp_tunnel->udp_port == 4790)
1076                 return 0;
1077         return -ENOTSUP;
1078 }
1079
1080 /**
1081  * Initialize process private data structure.
1082  *
1083  * @param dev
1084  *   Pointer to Ethernet device structure.
1085  *
1086  * @return
1087  *   0 on success, a negative errno value otherwise and rte_errno is set.
1088  */
1089 int
1090 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1091 {
1092         struct mlx5_priv *priv = dev->data->dev_private;
1093         struct mlx5_proc_priv *ppriv;
1094         size_t ppriv_size;
1095
1096         /*
1097          * UAR register table follows the process private structure. BlueFlame
1098          * registers for Tx queues are stored in the table.
1099          */
1100         ppriv_size =
1101                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1102         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1103                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1104         if (!ppriv) {
1105                 rte_errno = ENOMEM;
1106                 return -rte_errno;
1107         }
1108         ppriv->uar_table_sz = ppriv_size;
1109         dev->process_private = ppriv;
1110         return 0;
1111 }
1112
1113 /**
1114  * Un-initialize process private data structure.
1115  *
1116  * @param dev
1117  *   Pointer to Ethernet device structure.
1118  */
1119 static void
1120 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1121 {
1122         if (!dev->process_private)
1123                 return;
1124         rte_free(dev->process_private);
1125         dev->process_private = NULL;
1126 }
1127
1128 /**
1129  * DPDK callback to close the device.
1130  *
1131  * Destroy all queues and objects, free memory.
1132  *
1133  * @param dev
1134  *   Pointer to Ethernet device structure.
1135  */
1136 void
1137 mlx5_dev_close(struct rte_eth_dev *dev)
1138 {
1139         struct mlx5_priv *priv = dev->data->dev_private;
1140         unsigned int i;
1141         int ret;
1142
1143         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1144                 /* Check if process_private released. */
1145                 if (!dev->process_private)
1146                         return;
1147                 mlx5_tx_uar_uninit_secondary(dev);
1148                 mlx5_proc_priv_uninit(dev);
1149                 rte_eth_dev_release_port(dev);
1150                 return;
1151         }
1152         if (!priv->sh)
1153                 return;
1154         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1155                 dev->data->port_id,
1156                 ((priv->sh->ctx != NULL) ?
1157                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1158         /*
1159          * If default mreg copy action is removed at the stop stage,
1160          * the search will return none and nothing will be done anymore.
1161          */
1162         mlx5_flow_stop_default(dev);
1163         mlx5_traffic_disable(dev);
1164         /*
1165          * If all the flows are already flushed in the device stop stage,
1166          * then this will return directly without any action.
1167          */
1168         mlx5_flow_list_flush(dev, &priv->flows, true);
1169         mlx5_flow_meter_flush(dev, NULL);
1170         /* Free the intermediate buffers for flow creation. */
1171         mlx5_flow_free_intermediate(dev);
1172         /* Prevent crashes when queues are still in use. */
1173         dev->rx_pkt_burst = removed_rx_burst;
1174         dev->tx_pkt_burst = removed_tx_burst;
1175         rte_wmb();
1176         /* Disable datapath on secondary process. */
1177         mlx5_mp_req_stop_rxtx(dev);
1178         if (priv->rxqs != NULL) {
1179                 /* XXX race condition if mlx5_rx_burst() is still running. */
1180                 usleep(1000);
1181                 for (i = 0; (i != priv->rxqs_n); ++i)
1182                         mlx5_rxq_release(dev, i);
1183                 priv->rxqs_n = 0;
1184                 priv->rxqs = NULL;
1185         }
1186         if (priv->txqs != NULL) {
1187                 /* XXX race condition if mlx5_tx_burst() is still running. */
1188                 usleep(1000);
1189                 for (i = 0; (i != priv->txqs_n); ++i)
1190                         mlx5_txq_release(dev, i);
1191                 priv->txqs_n = 0;
1192                 priv->txqs = NULL;
1193         }
1194         mlx5_proc_priv_uninit(dev);
1195         if (priv->mreg_cp_tbl)
1196                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1197         mlx5_mprq_free_mp(dev);
1198         mlx5_os_free_shared_dr(priv);
1199         if (priv->rss_conf.rss_key != NULL)
1200                 rte_free(priv->rss_conf.rss_key);
1201         if (priv->reta_idx != NULL)
1202                 rte_free(priv->reta_idx);
1203         if (priv->config.vf)
1204                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1205                                        dev->data->mac_addrs,
1206                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1207         if (priv->nl_socket_route >= 0)
1208                 close(priv->nl_socket_route);
1209         if (priv->nl_socket_rdma >= 0)
1210                 close(priv->nl_socket_rdma);
1211         if (priv->vmwa_context)
1212                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1213         ret = mlx5_hrxq_verify(dev);
1214         if (ret)
1215                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1216                         dev->data->port_id);
1217         ret = mlx5_ind_table_obj_verify(dev);
1218         if (ret)
1219                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1220                         dev->data->port_id);
1221         ret = mlx5_rxq_obj_verify(dev);
1222         if (ret)
1223                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1224                         dev->data->port_id);
1225         ret = mlx5_rxq_verify(dev);
1226         if (ret)
1227                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1228                         dev->data->port_id);
1229         ret = mlx5_txq_obj_verify(dev);
1230         if (ret)
1231                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1232                         dev->data->port_id);
1233         ret = mlx5_txq_verify(dev);
1234         if (ret)
1235                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1236                         dev->data->port_id);
1237         ret = mlx5_flow_verify(dev);
1238         if (ret)
1239                 DRV_LOG(WARNING, "port %u some flows still remain",
1240                         dev->data->port_id);
1241         /*
1242          * Free the shared context in last turn, because the cleanup
1243          * routines above may use some shared fields, like
1244          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1245          * ifindex if Netlink fails.
1246          */
1247         mlx5_free_shared_dev_ctx(priv->sh);
1248         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1249                 unsigned int c = 0;
1250                 uint16_t port_id;
1251
1252                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1253                         struct mlx5_priv *opriv =
1254                                 rte_eth_devices[port_id].data->dev_private;
1255
1256                         if (!opriv ||
1257                             opriv->domain_id != priv->domain_id ||
1258                             &rte_eth_devices[port_id] == dev)
1259                                 continue;
1260                         ++c;
1261                         break;
1262                 }
1263                 if (!c)
1264                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1265         }
1266         memset(priv, 0, sizeof(*priv));
1267         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1268         /*
1269          * Reset mac_addrs to NULL such that it is not freed as part of
1270          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1271          * it is freed when dev_private is freed.
1272          */
1273         dev->data->mac_addrs = NULL;
1274 }
1275
1276 /**
1277  * Verify and store value for device argument.
1278  *
1279  * @param[in] key
1280  *   Key argument to verify.
1281  * @param[in] val
1282  *   Value associated with key.
1283  * @param opaque
1284  *   User data.
1285  *
1286  * @return
1287  *   0 on success, a negative errno value otherwise and rte_errno is set.
1288  */
1289 static int
1290 mlx5_args_check(const char *key, const char *val, void *opaque)
1291 {
1292         struct mlx5_dev_config *config = opaque;
1293         unsigned long mod;
1294         signed long tmp;
1295
1296         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1297         if (!strcmp(MLX5_REPRESENTOR, key))
1298                 return 0;
1299         errno = 0;
1300         tmp = strtol(val, NULL, 0);
1301         if (errno) {
1302                 rte_errno = errno;
1303                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1304                 return -rte_errno;
1305         }
1306         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1307                 /* Negative values are acceptable for some keys only. */
1308                 rte_errno = EINVAL;
1309                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1310                 return -rte_errno;
1311         }
1312         mod = tmp >= 0 ? tmp : -tmp;
1313         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1314                 config->cqe_comp = !!tmp;
1315         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1316                 config->cqe_pad = !!tmp;
1317         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1318                 config->hw_padding = !!tmp;
1319         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1320                 config->mprq.enabled = !!tmp;
1321         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1322                 config->mprq.stride_num_n = tmp;
1323         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1324                 config->mprq.stride_size_n = tmp;
1325         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1326                 config->mprq.max_memcpy_len = tmp;
1327         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1328                 config->mprq.min_rxqs_num = tmp;
1329         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1330                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1331                                  " converted to txq_inline_max", key);
1332                 config->txq_inline_max = tmp;
1333         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1334                 config->txq_inline_max = tmp;
1335         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1336                 config->txq_inline_min = tmp;
1337         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1338                 config->txq_inline_mpw = tmp;
1339         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1340                 config->txqs_inline = tmp;
1341         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1342                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1343         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1344                 config->mps = !!tmp;
1345         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1346                 if (tmp != MLX5_TXDB_CACHED &&
1347                     tmp != MLX5_TXDB_NCACHED &&
1348                     tmp != MLX5_TXDB_HEURISTIC) {
1349                         DRV_LOG(ERR, "invalid Tx doorbell "
1350                                      "mapping parameter");
1351                         rte_errno = EINVAL;
1352                         return -rte_errno;
1353                 }
1354                 config->dbnc = tmp;
1355         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1356                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1357         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1358                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1359                                  " converted to txq_inline_mpw", key);
1360                 config->txq_inline_mpw = tmp;
1361         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1362                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1363         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1364                 if (!mod) {
1365                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1366                         rte_errno = EINVAL;
1367                         return -rte_errno;
1368                 }
1369                 config->tx_pp = tmp;
1370         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1371                 config->tx_skew = tmp;
1372         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1373                 config->rx_vec_en = !!tmp;
1374         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1375                 config->l3_vxlan_en = !!tmp;
1376         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1377                 config->vf_nl_en = !!tmp;
1378         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1379                 config->dv_esw_en = !!tmp;
1380         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1381                 config->dv_flow_en = !!tmp;
1382         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1383                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1384                     tmp != MLX5_XMETA_MODE_META16 &&
1385                     tmp != MLX5_XMETA_MODE_META32) {
1386                         DRV_LOG(ERR, "invalid extensive "
1387                                      "metadata parameter");
1388                         rte_errno = EINVAL;
1389                         return -rte_errno;
1390                 }
1391                 config->dv_xmeta_en = tmp;
1392         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1393                 config->lacp_by_user = !!tmp;
1394         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1395                 config->mr_ext_memseg_en = !!tmp;
1396         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1397                 config->max_dump_files_num = tmp;
1398         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1399                 config->lro.timeout = tmp;
1400         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1401                 DRV_LOG(DEBUG, "class argument is %s.", val);
1402         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1403                 config->log_hp_size = tmp;
1404         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1405                 if (tmp != MLX5_RCM_NONE &&
1406                     tmp != MLX5_RCM_LIGHT &&
1407                     tmp != MLX5_RCM_AGGR) {
1408                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1409                         rte_errno = EINVAL;
1410                         return -rte_errno;
1411                 }
1412                 config->reclaim_mode = tmp;
1413         } else {
1414                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1415                 rte_errno = EINVAL;
1416                 return -rte_errno;
1417         }
1418         return 0;
1419 }
1420
1421 /**
1422  * Parse device parameters.
1423  *
1424  * @param config
1425  *   Pointer to device configuration structure.
1426  * @param devargs
1427  *   Device arguments structure.
1428  *
1429  * @return
1430  *   0 on success, a negative errno value otherwise and rte_errno is set.
1431  */
1432 int
1433 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1434 {
1435         const char **params = (const char *[]){
1436                 MLX5_RXQ_CQE_COMP_EN,
1437                 MLX5_RXQ_CQE_PAD_EN,
1438                 MLX5_RXQ_PKT_PAD_EN,
1439                 MLX5_RX_MPRQ_EN,
1440                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1441                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1442                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1443                 MLX5_RXQS_MIN_MPRQ,
1444                 MLX5_TXQ_INLINE,
1445                 MLX5_TXQ_INLINE_MIN,
1446                 MLX5_TXQ_INLINE_MAX,
1447                 MLX5_TXQ_INLINE_MPW,
1448                 MLX5_TXQS_MIN_INLINE,
1449                 MLX5_TXQS_MAX_VEC,
1450                 MLX5_TXQ_MPW_EN,
1451                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1452                 MLX5_TXQ_MAX_INLINE_LEN,
1453                 MLX5_TX_DB_NC,
1454                 MLX5_TX_PP,
1455                 MLX5_TX_SKEW,
1456                 MLX5_TX_VEC_EN,
1457                 MLX5_RX_VEC_EN,
1458                 MLX5_L3_VXLAN_EN,
1459                 MLX5_VF_NL_EN,
1460                 MLX5_DV_ESW_EN,
1461                 MLX5_DV_FLOW_EN,
1462                 MLX5_DV_XMETA_EN,
1463                 MLX5_LACP_BY_USER,
1464                 MLX5_MR_EXT_MEMSEG_EN,
1465                 MLX5_REPRESENTOR,
1466                 MLX5_MAX_DUMP_FILES_NUM,
1467                 MLX5_LRO_TIMEOUT_USEC,
1468                 MLX5_CLASS_ARG_NAME,
1469                 MLX5_HP_BUF_SIZE,
1470                 MLX5_RECLAIM_MEM,
1471                 NULL,
1472         };
1473         struct rte_kvargs *kvlist;
1474         int ret = 0;
1475         int i;
1476
1477         if (devargs == NULL)
1478                 return 0;
1479         /* Following UGLY cast is done to pass checkpatch. */
1480         kvlist = rte_kvargs_parse(devargs->args, params);
1481         if (kvlist == NULL) {
1482                 rte_errno = EINVAL;
1483                 return -rte_errno;
1484         }
1485         /* Process parameters. */
1486         for (i = 0; (params[i] != NULL); ++i) {
1487                 if (rte_kvargs_count(kvlist, params[i])) {
1488                         ret = rte_kvargs_process(kvlist, params[i],
1489                                                  mlx5_args_check, config);
1490                         if (ret) {
1491                                 rte_errno = EINVAL;
1492                                 rte_kvargs_free(kvlist);
1493                                 return -rte_errno;
1494                         }
1495                 }
1496         }
1497         rte_kvargs_free(kvlist);
1498         return 0;
1499 }
1500
1501 /**
1502  * PMD global initialization.
1503  *
1504  * Independent from individual device, this function initializes global
1505  * per-PMD data structures distinguishing primary and secondary processes.
1506  * Hence, each initialization is called once per a process.
1507  *
1508  * @return
1509  *   0 on success, a negative errno value otherwise and rte_errno is set.
1510  */
1511 int
1512 mlx5_init_once(void)
1513 {
1514         struct mlx5_shared_data *sd;
1515         struct mlx5_local_data *ld = &mlx5_local_data;
1516         int ret = 0;
1517
1518         if (mlx5_init_shared_data())
1519                 return -rte_errno;
1520         sd = mlx5_shared_data;
1521         MLX5_ASSERT(sd);
1522         rte_spinlock_lock(&sd->lock);
1523         switch (rte_eal_process_type()) {
1524         case RTE_PROC_PRIMARY:
1525                 if (sd->init_done)
1526                         break;
1527                 LIST_INIT(&sd->mem_event_cb_list);
1528                 rte_rwlock_init(&sd->mem_event_rwlock);
1529                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1530                                                 mlx5_mr_mem_event_cb, NULL);
1531                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1532                                            mlx5_mp_primary_handle);
1533                 if (ret)
1534                         goto out;
1535                 sd->init_done = true;
1536                 break;
1537         case RTE_PROC_SECONDARY:
1538                 if (ld->init_done)
1539                         break;
1540                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1541                                              mlx5_mp_secondary_handle);
1542                 if (ret)
1543                         goto out;
1544                 ++sd->secondary_cnt;
1545                 ld->init_done = true;
1546                 break;
1547         default:
1548                 break;
1549         }
1550 out:
1551         rte_spinlock_unlock(&sd->lock);
1552         return ret;
1553 }
1554
1555 /**
1556  * Configures the minimal amount of data to inline into WQE
1557  * while sending packets.
1558  *
1559  * - the txq_inline_min has the maximal priority, if this
1560  *   key is specified in devargs
1561  * - if DevX is enabled the inline mode is queried from the
1562  *   device (HCA attributes and NIC vport context if needed).
1563  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1564  *   and none (0 bytes) for other NICs
1565  *
1566  * @param spawn
1567  *   Verbs device parameters (name, port, switch_info) to spawn.
1568  * @param config
1569  *   Device configuration parameters.
1570  */
1571 void
1572 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1573                     struct mlx5_dev_config *config)
1574 {
1575         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1576                 /* Application defines size of inlined data explicitly. */
1577                 switch (spawn->pci_dev->id.device_id) {
1578                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1579                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1580                         if (config->txq_inline_min <
1581                                        (int)MLX5_INLINE_HSIZE_L2) {
1582                                 DRV_LOG(DEBUG,
1583                                         "txq_inline_mix aligned to minimal"
1584                                         " ConnectX-4 required value %d",
1585                                         (int)MLX5_INLINE_HSIZE_L2);
1586                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1587                         }
1588                         break;
1589                 }
1590                 goto exit;
1591         }
1592         if (config->hca_attr.eth_net_offloads) {
1593                 /* We have DevX enabled, inline mode queried successfully. */
1594                 switch (config->hca_attr.wqe_inline_mode) {
1595                 case MLX5_CAP_INLINE_MODE_L2:
1596                         /* outer L2 header must be inlined. */
1597                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1598                         goto exit;
1599                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1600                         /* No inline data are required by NIC. */
1601                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1602                         config->hw_vlan_insert =
1603                                 config->hca_attr.wqe_vlan_insert;
1604                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1605                         goto exit;
1606                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1607                         /* inline mode is defined by NIC vport context. */
1608                         if (!config->hca_attr.eth_virt)
1609                                 break;
1610                         switch (config->hca_attr.vport_inline_mode) {
1611                         case MLX5_INLINE_MODE_NONE:
1612                                 config->txq_inline_min =
1613                                         MLX5_INLINE_HSIZE_NONE;
1614                                 goto exit;
1615                         case MLX5_INLINE_MODE_L2:
1616                                 config->txq_inline_min =
1617                                         MLX5_INLINE_HSIZE_L2;
1618                                 goto exit;
1619                         case MLX5_INLINE_MODE_IP:
1620                                 config->txq_inline_min =
1621                                         MLX5_INLINE_HSIZE_L3;
1622                                 goto exit;
1623                         case MLX5_INLINE_MODE_TCP_UDP:
1624                                 config->txq_inline_min =
1625                                         MLX5_INLINE_HSIZE_L4;
1626                                 goto exit;
1627                         case MLX5_INLINE_MODE_INNER_L2:
1628                                 config->txq_inline_min =
1629                                         MLX5_INLINE_HSIZE_INNER_L2;
1630                                 goto exit;
1631                         case MLX5_INLINE_MODE_INNER_IP:
1632                                 config->txq_inline_min =
1633                                         MLX5_INLINE_HSIZE_INNER_L3;
1634                                 goto exit;
1635                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1636                                 config->txq_inline_min =
1637                                         MLX5_INLINE_HSIZE_INNER_L4;
1638                                 goto exit;
1639                         }
1640                 }
1641         }
1642         /*
1643          * We get here if we are unable to deduce
1644          * inline data size with DevX. Try PCI ID
1645          * to determine old NICs.
1646          */
1647         switch (spawn->pci_dev->id.device_id) {
1648         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1649         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1650         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1651         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1652                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1653                 config->hw_vlan_insert = 0;
1654                 break;
1655         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1656         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1657         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1658         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1659                 /*
1660                  * These NICs support VLAN insertion from WQE and
1661                  * report the wqe_vlan_insert flag. But there is the bug
1662                  * and PFC control may be broken, so disable feature.
1663                  */
1664                 config->hw_vlan_insert = 0;
1665                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1666                 break;
1667         default:
1668                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1669                 break;
1670         }
1671 exit:
1672         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1673 }
1674
1675 /**
1676  * Configures the metadata mask fields in the shared context.
1677  *
1678  * @param [in] dev
1679  *   Pointer to Ethernet device.
1680  */
1681 void
1682 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1683 {
1684         struct mlx5_priv *priv = dev->data->dev_private;
1685         struct mlx5_dev_ctx_shared *sh = priv->sh;
1686         uint32_t meta, mark, reg_c0;
1687
1688         reg_c0 = ~priv->vport_meta_mask;
1689         switch (priv->config.dv_xmeta_en) {
1690         case MLX5_XMETA_MODE_LEGACY:
1691                 meta = UINT32_MAX;
1692                 mark = MLX5_FLOW_MARK_MASK;
1693                 break;
1694         case MLX5_XMETA_MODE_META16:
1695                 meta = reg_c0 >> rte_bsf32(reg_c0);
1696                 mark = MLX5_FLOW_MARK_MASK;
1697                 break;
1698         case MLX5_XMETA_MODE_META32:
1699                 meta = UINT32_MAX;
1700                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1701                 break;
1702         default:
1703                 meta = 0;
1704                 mark = 0;
1705                 MLX5_ASSERT(false);
1706                 break;
1707         }
1708         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1709                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1710                                  sh->dv_mark_mask, mark);
1711         else
1712                 sh->dv_mark_mask = mark;
1713         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1714                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1715                                  sh->dv_meta_mask, meta);
1716         else
1717                 sh->dv_meta_mask = meta;
1718         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1719                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1720                                  sh->dv_meta_mask, reg_c0);
1721         else
1722                 sh->dv_regc0_mask = reg_c0;
1723         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1724         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1725         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1726         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1727 }
1728
1729 int
1730 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1731 {
1732         static const char *const dynf_names[] = {
1733                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1734                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1735                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1736         };
1737         unsigned int i;
1738
1739         if (n < RTE_DIM(dynf_names))
1740                 return -ENOMEM;
1741         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1742                 if (names[i] == NULL)
1743                         return -EINVAL;
1744                 strcpy(names[i], dynf_names[i]);
1745         }
1746         return RTE_DIM(dynf_names);
1747 }
1748
1749 /**
1750  * Comparison callback to sort device data.
1751  *
1752  * This is meant to be used with qsort().
1753  *
1754  * @param a[in]
1755  *   Pointer to pointer to first data object.
1756  * @param b[in]
1757  *   Pointer to pointer to second data object.
1758  *
1759  * @return
1760  *   0 if both objects are equal, less than 0 if the first argument is less
1761  *   than the second, greater than 0 otherwise.
1762  */
1763 int
1764 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1765                               struct mlx5_dev_config *config)
1766 {
1767         struct mlx5_dev_ctx_shared *sh = priv->sh;
1768         struct mlx5_dev_config *sh_conf = NULL;
1769         uint16_t port_id;
1770
1771         MLX5_ASSERT(sh);
1772         /* Nothing to compare for the single/first device. */
1773         if (sh->refcnt == 1)
1774                 return 0;
1775         /* Find the device with shared context. */
1776         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1777                 struct mlx5_priv *opriv =
1778                         rte_eth_devices[port_id].data->dev_private;
1779
1780                 if (opriv && opriv != priv && opriv->sh == sh) {
1781                         sh_conf = &opriv->config;
1782                         break;
1783                 }
1784         }
1785         if (!sh_conf)
1786                 return 0;
1787         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1788                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1789                              " for shared %s context", sh->ibdev_name);
1790                 rte_errno = EINVAL;
1791                 return rte_errno;
1792         }
1793         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1794                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1795                              " for shared %s context", sh->ibdev_name);
1796                 rte_errno = EINVAL;
1797                 return rte_errno;
1798         }
1799         return 0;
1800 }
1801
1802 /**
1803  * Look for the ethernet device belonging to mlx5 driver.
1804  *
1805  * @param[in] port_id
1806  *   port_id to start looking for device.
1807  * @param[in] pci_dev
1808  *   Pointer to the hint PCI device. When device is being probed
1809  *   the its siblings (master and preceding representors might
1810  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1811  *   is not completed yet, for this case match on hint PCI
1812  *   device may be used to detect sibling device.
1813  *
1814  * @return
1815  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1816  */
1817 uint16_t
1818 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1819 {
1820         while (port_id < RTE_MAX_ETHPORTS) {
1821                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1822
1823                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1824                     dev->device &&
1825                     (dev->device == &pci_dev->device ||
1826                      (dev->device->driver &&
1827                      dev->device->driver->name &&
1828                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1829                         break;
1830                 port_id++;
1831         }
1832         if (port_id >= RTE_MAX_ETHPORTS)
1833                 return RTE_MAX_ETHPORTS;
1834         return port_id;
1835 }
1836
1837 /**
1838  * DPDK callback to remove a PCI device.
1839  *
1840  * This function removes all Ethernet devices belong to a given PCI device.
1841  *
1842  * @param[in] pci_dev
1843  *   Pointer to the PCI device.
1844  *
1845  * @return
1846  *   0 on success, the function cannot fail.
1847  */
1848 static int
1849 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1850 {
1851         uint16_t port_id;
1852
1853         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1854                 /*
1855                  * mlx5_dev_close() is not registered to secondary process,
1856                  * call the close function explicitly for secondary process.
1857                  */
1858                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1859                         mlx5_dev_close(&rte_eth_devices[port_id]);
1860                 else
1861                         rte_eth_dev_close(port_id);
1862         }
1863         return 0;
1864 }
1865
1866 static const struct rte_pci_id mlx5_pci_id_map[] = {
1867         {
1868                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1869                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1870         },
1871         {
1872                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1873                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1874         },
1875         {
1876                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1877                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1878         },
1879         {
1880                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1881                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1882         },
1883         {
1884                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1885                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1886         },
1887         {
1888                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1889                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1890         },
1891         {
1892                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1893                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1894         },
1895         {
1896                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1897                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1898         },
1899         {
1900                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1901                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1902         },
1903         {
1904                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1905                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1906         },
1907         {
1908                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1909                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1910         },
1911         {
1912                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1913                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1914         },
1915         {
1916                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1917                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1918         },
1919         {
1920                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1921                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1922         },
1923         {
1924                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1926         },
1927         {
1928                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1930         },
1931         {
1932                 .vendor_id = 0
1933         }
1934 };
1935
1936 struct rte_pci_driver mlx5_driver = {
1937         .driver = {
1938                 .name = MLX5_DRIVER_NAME
1939         },
1940         .id_table = mlx5_pci_id_map,
1941         .probe = mlx5_os_pci_probe,
1942         .remove = mlx5_pci_remove,
1943         .dma_map = mlx5_dma_map,
1944         .dma_unmap = mlx5_dma_unmap,
1945         .drv_flags = PCI_DRV_FLAGS,
1946 };
1947
1948 /* Initialize driver log type. */
1949 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1950
1951 /**
1952  * Driver initialization routine.
1953  */
1954 RTE_INIT(rte_mlx5_pmd_init)
1955 {
1956         /* Build the static tables for Verbs conversion. */
1957         mlx5_set_ptype_table();
1958         mlx5_set_cksum_table();
1959         mlx5_set_swp_types_table();
1960         if (mlx5_glue)
1961                 rte_pci_register(&mlx5_driver);
1962 }
1963
1964 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1965 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1966 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");