1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_os.h>
42 #include <mlx5_common_mp.h>
44 #include "mlx5_defs.h"
46 #include "mlx5_utils.h"
47 #include "mlx5_rxtx.h"
48 #include "mlx5_autoconf.h"
50 #include "mlx5_flow.h"
51 #include "rte_pmd_mlx5.h"
53 /* Device parameter to enable RX completion queue compression. */
54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
56 /* Device parameter to enable RX completion entry padding to 128B. */
57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
59 /* Device parameter to enable padding Rx packet to cacheline size. */
60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
62 /* Device parameter to enable Multi-Packet Rx queue. */
63 #define MLX5_RX_MPRQ_EN "mprq_en"
65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
77 /* Device parameter to configure inline send. Deprecated, ignored.*/
78 #define MLX5_TXQ_INLINE "txq_inline"
80 /* Device parameter to limit packet size to inline with ordinary SEND. */
81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
83 /* Device parameter to configure minimal data size to inline. */
84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
90 * Device parameter to configure the number of TX queues threshold for
91 * enabling inline send.
93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
96 * Device parameter to configure the number of TX queues threshold for
97 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
101 /* Device parameter to enable multi-packet send WQEs. */
102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
105 * Device parameter to force doorbell register mapping
106 * to non-cahed region eliminating the extra write memory barrier.
108 #define MLX5_TX_DB_NC "tx_db_nc"
111 * Device parameter to include 2 dsegs in the title WQEBB.
112 * Deprecated, ignored.
114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
117 * Device parameter to limit the size of inlining packet.
118 * Deprecated, ignored.
120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
123 * Device parameter to enable Tx scheduling on timestamps
124 * and specify the packet pacing granularity in nanoseconds.
126 #define MLX5_TX_PP "tx_pp"
129 * Device parameter to specify skew in nanoseconds on Tx datapath,
130 * it represents the time between SQ start WQE processing and
131 * appearing actual packet data on the wire.
133 #define MLX5_TX_SKEW "tx_skew"
136 * Device parameter to enable hardware Tx vector.
137 * Deprecated, ignored (no vectorized Tx routines anymore).
139 #define MLX5_TX_VEC_EN "tx_vec_en"
141 /* Device parameter to enable hardware Rx vector. */
142 #define MLX5_RX_VEC_EN "rx_vec_en"
144 /* Allow L3 VXLAN flow creation. */
145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
147 /* Activate DV E-Switch flow steering. */
148 #define MLX5_DV_ESW_EN "dv_esw_en"
150 /* Activate DV flow steering. */
151 #define MLX5_DV_FLOW_EN "dv_flow_en"
153 /* Enable extensive flow metadata support. */
154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
156 /* Device parameter to let the user manage the lacp traffic of bonded device */
157 #define MLX5_LACP_BY_USER "lacp_by_user"
159 /* Activate Netlink support in VF mode. */
160 #define MLX5_VF_NL_EN "vf_nl_en"
162 /* Enable extending memsegs when creating a MR. */
163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
165 /* Select port representors to instantiate. */
166 #define MLX5_REPRESENTOR "representor"
168 /* Device parameter to configure the maximum number of dump files per queue. */
169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
171 /* Configure timeout of LRO session (in microseconds). */
172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
175 * Device parameter to configure the total data buffer size for a single
176 * hairpin queue (logarithm value).
178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
180 /* Flow memory reclaim mode. */
181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
185 /* Shared memory between primary and secondary processes. */
186 struct mlx5_shared_data *mlx5_shared_data;
188 /* Spinlock for mlx5_shared_data allocation. */
189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
191 /* Process local data for secondary processes. */
192 static struct mlx5_local_data mlx5_local_data;
194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
195 LIST_HEAD_INITIALIZER();
196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
201 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
207 .malloc = rte_malloc_socket,
209 .type = "mlx5_encap_decap_ipool",
212 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
218 .malloc = rte_malloc_socket,
220 .type = "mlx5_push_vlan_ipool",
223 .size = sizeof(struct mlx5_flow_dv_tag_resource),
229 .malloc = rte_malloc_socket,
231 .type = "mlx5_tag_ipool",
234 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
240 .malloc = rte_malloc_socket,
242 .type = "mlx5_port_id_ipool",
245 .size = sizeof(struct mlx5_flow_tbl_data_entry),
251 .malloc = rte_malloc_socket,
253 .type = "mlx5_jump_ipool",
257 .size = sizeof(struct mlx5_flow_meter),
263 .malloc = rte_malloc_socket,
265 .type = "mlx5_meter_ipool",
268 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
274 .malloc = rte_malloc_socket,
276 .type = "mlx5_mcp_ipool",
279 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
285 .malloc = rte_malloc_socket,
287 .type = "mlx5_hrxq_ipool",
291 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
292 * It set in run time according to PCI function configuration.
300 .malloc = rte_malloc_socket,
302 .type = "mlx5_flow_handle_ipool",
305 .size = sizeof(struct rte_flow),
309 .malloc = rte_malloc_socket,
311 .type = "rte_flow_ipool",
316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
322 * Allocate ID pool structure.
325 * The maximum id can be allocated from the pool.
328 * Pointer to pool object, NULL value otherwise.
330 struct mlx5_flow_id_pool *
331 mlx5_flow_id_pool_alloc(uint32_t max_id)
333 struct mlx5_flow_id_pool *pool;
336 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
337 RTE_CACHE_LINE_SIZE);
339 DRV_LOG(ERR, "can't allocate id pool");
343 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
344 RTE_CACHE_LINE_SIZE);
346 DRV_LOG(ERR, "can't allocate mem for id pool");
350 pool->free_arr = mem;
351 pool->curr = pool->free_arr;
352 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
353 pool->base_index = 0;
354 pool->max_id = max_id;
362 * Release ID pool structure.
365 * Pointer to flow id pool object to free.
368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
370 rte_free(pool->free_arr);
378 * Pointer to flow id pool.
383 * 0 on success, error value otherwise.
386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
388 if (pool->curr == pool->free_arr) {
389 if (pool->base_index == pool->max_id) {
391 DRV_LOG(ERR, "no free id");
394 *id = ++pool->base_index;
397 *id = *(--pool->curr);
405 * Pointer to flow id pool.
410 * 0 on success, error value otherwise.
413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
419 if (pool->curr == pool->last) {
420 size = pool->curr - pool->free_arr;
421 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
422 MLX5_ASSERT(size2 > size);
423 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
425 DRV_LOG(ERR, "can't allocate mem for id pool");
429 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
430 rte_free(pool->free_arr);
431 pool->free_arr = mem;
432 pool->curr = pool->free_arr + size;
433 pool->last = pool->free_arr + size2;
441 * Initialize the shared aging list information per port.
444 * Pointer to mlx5_dev_ctx_shared object.
447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
450 struct mlx5_age_info *age_info;
452 for (i = 0; i < sh->max_port; i++) {
453 age_info = &sh->port[i].age_info;
455 TAILQ_INIT(&age_info->aged_counters);
456 rte_spinlock_init(&age_info->aged_sl);
457 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
462 * Initialize the counters management structure.
465 * Pointer to mlx5_dev_ctx_shared object to free
468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
472 memset(&sh->cmng, 0, sizeof(sh->cmng));
473 TAILQ_INIT(&sh->cmng.flow_counters);
474 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
475 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
476 sh->cmng.ccont[i].max_id = -1;
477 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
478 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
479 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
480 TAILQ_INIT(&sh->cmng.ccont[i].counters);
481 rte_spinlock_init(&sh->cmng.ccont[i].csl);
486 * Destroy all the resources allocated for a counter memory management.
489 * Pointer to the memory management structure.
492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
494 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
496 LIST_REMOVE(mng, next);
497 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
498 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
503 * Close and release all the resources of the counters management.
506 * Pointer to mlx5_dev_ctx_shared object to free.
509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
511 struct mlx5_counter_stats_mem_mng *mng;
518 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
519 if (rte_errno != EINPROGRESS)
523 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
524 struct mlx5_flow_counter_pool *pool;
525 uint32_t batch = !!(i > 1);
527 if (!sh->cmng.ccont[i].pools)
529 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
531 if (batch && pool->min_dcs)
532 claim_zero(mlx5_devx_cmd_destroy
534 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
535 if (MLX5_POOL_GET_CNT(pool, j)->action)
537 (mlx5_glue->destroy_flow_action
540 if (!batch && MLX5_GET_POOL_CNT_EXT
542 claim_zero(mlx5_devx_cmd_destroy
543 (MLX5_GET_POOL_CNT_EXT
546 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
548 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
550 rte_free(sh->cmng.ccont[i].pools);
552 mng = LIST_FIRST(&sh->cmng.mem_mngs);
554 mlx5_flow_destroy_counter_stat_mem_mng(mng);
555 mng = LIST_FIRST(&sh->cmng.mem_mngs);
557 memset(&sh->cmng, 0, sizeof(sh->cmng));
561 * Initialize the flow resources' indexed mempool.
564 * Pointer to mlx5_dev_ctx_shared object.
566 * Pointer to user dev config.
569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
570 const struct mlx5_dev_config *config)
573 struct mlx5_indexed_pool_config cfg;
575 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
576 cfg = mlx5_ipool_cfg[i];
581 * Set MLX5_IPOOL_MLX5_FLOW ipool size
582 * according to PCI function flow configuration.
584 case MLX5_IPOOL_MLX5_FLOW:
585 cfg.size = config->dv_flow_en ?
586 sizeof(struct mlx5_flow_handle) :
587 MLX5_FLOW_HANDLE_VERBS_SIZE;
590 if (config->reclaim_mode)
591 cfg.release_mem_en = 1;
592 sh->ipool[i] = mlx5_ipool_create(&cfg);
597 * Release the flow resources' indexed mempool.
600 * Pointer to mlx5_dev_ctx_shared object.
603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
607 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
608 mlx5_ipool_destroy(sh->ipool[i]);
612 * Check if dynamic flex parser for eCPRI already exists.
615 * Pointer to Ethernet device structure.
618 * true on exists, false on not.
621 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
623 struct mlx5_priv *priv = dev->data->dev_private;
624 struct mlx5_flex_parser_profiles *prf =
625 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
631 * Allocation of a flex parser for eCPRI. Once created, this parser related
632 * resources will be held until the device is closed.
635 * Pointer to Ethernet device structure.
638 * 0 on success, a negative errno value otherwise and rte_errno is set.
641 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
643 struct mlx5_priv *priv = dev->data->dev_private;
644 struct mlx5_flex_parser_profiles *prf =
645 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
652 * Allocate shared device context. If there is multiport device the
653 * master and representors will share this context, if there is single
654 * port dedicated device, the context will be used by only given
655 * port due to unification.
657 * Routine first searches the context for the specified device name,
658 * if found the shared context assumed and reference counter is incremented.
659 * If no context found the new one is created and initialized with specified
660 * device context and parameters.
663 * Pointer to the device attributes (name, port, etc).
665 * Pointer to device configuration structure.
668 * Pointer to mlx5_dev_ctx_shared object on success,
669 * otherwise NULL and rte_errno is set.
671 struct mlx5_dev_ctx_shared *
672 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
673 const struct mlx5_dev_config *config)
675 struct mlx5_dev_ctx_shared *sh;
678 struct mlx5_devx_tis_attr tis_attr = { 0 };
681 /* Secondary process should not create the shared context. */
682 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
683 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
684 /* Search for IB context by device name. */
685 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
686 if (!strcmp(sh->ibdev_name,
687 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
692 /* No device found, we have to create new shared context. */
693 MLX5_ASSERT(spawn->max_port);
694 sh = rte_zmalloc("ethdev shared ib context",
695 sizeof(struct mlx5_dev_ctx_shared) +
697 sizeof(struct mlx5_dev_shared_port),
698 RTE_CACHE_LINE_SIZE);
700 DRV_LOG(ERR, "shared context allocation failure");
704 err = mlx5_os_open_device(spawn, config, sh);
707 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
709 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
713 sh->max_port = spawn->max_port;
714 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
715 sizeof(sh->ibdev_name) - 1);
716 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
717 sizeof(sh->ibdev_path) - 1);
719 * Setting port_id to max unallowed value means
720 * there is no interrupt subhandler installed for
721 * the given port index i.
723 for (i = 0; i < sh->max_port; i++) {
724 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
725 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
727 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
728 if (sh->pd == NULL) {
729 DRV_LOG(ERR, "PD allocation failure");
734 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
736 DRV_LOG(ERR, "Fail to extract pdn from PD");
739 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
741 DRV_LOG(ERR, "TD allocation failure");
745 tis_attr.transport_domain = sh->td->id;
746 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
748 DRV_LOG(ERR, "TIS allocation failure");
752 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
754 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
759 sh->flow_id_pool = mlx5_flow_id_pool_alloc
760 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
761 if (!sh->flow_id_pool) {
762 DRV_LOG(ERR, "can't create flow id pool");
767 /* Initialize UAR access locks for 32bit implementations. */
768 rte_spinlock_init(&sh->uar_lock_cq);
769 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
770 rte_spinlock_init(&sh->uar_lock[i]);
773 * Once the device is added to the list of memory event
774 * callback, its global MR cache table cannot be expanded
775 * on the fly because of deadlock. If it overflows, lookup
776 * should be done by searching MR list linearly, which is slow.
778 * At this point the device is not added to the memory
779 * event list yet, context is just being created.
781 err = mlx5_mr_btree_init(&sh->share_cache.cache,
782 MLX5_MR_BTREE_CACHE_N * 2,
783 spawn->pci_dev->device.numa_node);
788 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
789 &sh->share_cache.dereg_mr_cb);
790 mlx5_os_dev_shared_handler_install(sh);
791 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
792 if (!sh->cnt_id_tbl) {
796 mlx5_flow_aging_init(sh);
797 mlx5_flow_counters_mng_init(sh);
798 mlx5_flow_ipool_create(sh, config);
799 /* Add device to memory callback list. */
800 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
801 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
803 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
804 /* Add context to the global device list. */
805 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
807 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
810 pthread_mutex_destroy(&sh->txpp.mutex);
811 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
813 if (sh->cnt_id_tbl) {
814 mlx5_l3t_destroy(sh->cnt_id_tbl);
815 sh->cnt_id_tbl = NULL;
818 mlx5_glue->devx_free_uar(sh->tx_uar);
822 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
824 claim_zero(mlx5_devx_cmd_destroy(sh->td));
826 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
828 claim_zero(mlx5_glue->close_device(sh->ctx));
829 if (sh->flow_id_pool)
830 mlx5_flow_id_pool_release(sh->flow_id_pool);
832 MLX5_ASSERT(err > 0);
838 * Free shared IB device context. Decrement counter and if zero free
839 * all allocated resources and close handles.
842 * Pointer to mlx5_dev_ctx_shared object to free
845 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
847 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
848 #ifdef RTE_LIBRTE_MLX5_DEBUG
849 /* Check the object presence in the list. */
850 struct mlx5_dev_ctx_shared *lctx;
852 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
857 DRV_LOG(ERR, "Freeing non-existing shared IB context");
862 MLX5_ASSERT(sh->refcnt);
863 /* Secondary process should not free the shared context. */
864 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
867 /* Remove from memory callback device list. */
868 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
869 LIST_REMOVE(sh, mem_event_cb);
870 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
871 /* Release created Memory Regions. */
872 mlx5_mr_release_cache(&sh->share_cache);
873 /* Remove context from the global device list. */
874 LIST_REMOVE(sh, next);
876 * Ensure there is no async event handler installed.
877 * Only primary process handles async device events.
879 mlx5_flow_counters_mng_close(sh);
880 mlx5_flow_ipool_destroy(sh);
881 mlx5_os_dev_shared_handler_uninstall(sh);
882 if (sh->cnt_id_tbl) {
883 mlx5_l3t_destroy(sh->cnt_id_tbl);
884 sh->cnt_id_tbl = NULL;
887 mlx5_glue->devx_free_uar(sh->tx_uar);
891 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
893 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
895 claim_zero(mlx5_devx_cmd_destroy(sh->td));
897 claim_zero(mlx5_glue->close_device(sh->ctx));
898 if (sh->flow_id_pool)
899 mlx5_flow_id_pool_release(sh->flow_id_pool);
900 pthread_mutex_destroy(&sh->txpp.mutex);
903 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
907 * Destroy table hash list and all the root entries per domain.
910 * Pointer to the private device data structure.
913 mlx5_free_table_hash_list(struct mlx5_priv *priv)
915 struct mlx5_dev_ctx_shared *sh = priv->sh;
916 struct mlx5_flow_tbl_data_entry *tbl_data;
917 union mlx5_flow_tbl_key table_key = {
925 struct mlx5_hlist_entry *pos;
929 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
931 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
933 MLX5_ASSERT(tbl_data);
934 mlx5_hlist_remove(sh->flow_tbls, pos);
937 table_key.direction = 1;
938 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
940 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
942 MLX5_ASSERT(tbl_data);
943 mlx5_hlist_remove(sh->flow_tbls, pos);
946 table_key.direction = 0;
947 table_key.domain = 1;
948 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
950 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
952 MLX5_ASSERT(tbl_data);
953 mlx5_hlist_remove(sh->flow_tbls, pos);
956 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
960 * Initialize flow table hash list and create the root tables entry
964 * Pointer to the private device data structure.
967 * Zero on success, positive error code otherwise.
970 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
972 struct mlx5_dev_ctx_shared *sh = priv->sh;
973 char s[MLX5_HLIST_NAMESIZE];
977 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
978 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
979 if (!sh->flow_tbls) {
980 DRV_LOG(ERR, "flow tables with hash creation failed.");
984 #ifndef HAVE_MLX5DV_DR
986 * In case we have not DR support, the zero tables should be created
987 * because DV expect to see them even if they cannot be created by
990 union mlx5_flow_tbl_key table_key = {
998 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
999 sizeof(*tbl_data), 0);
1005 tbl_data->entry.key = table_key.v64;
1006 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1009 rte_atomic32_init(&tbl_data->tbl.refcnt);
1010 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1011 table_key.direction = 1;
1012 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1017 tbl_data->entry.key = table_key.v64;
1018 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1021 rte_atomic32_init(&tbl_data->tbl.refcnt);
1022 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1023 table_key.direction = 0;
1024 table_key.domain = 1;
1025 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1030 tbl_data->entry.key = table_key.v64;
1031 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1034 rte_atomic32_init(&tbl_data->tbl.refcnt);
1035 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1038 mlx5_free_table_hash_list(priv);
1039 #endif /* HAVE_MLX5DV_DR */
1044 * Initialize shared data between primary and secondary process.
1046 * A memzone is reserved by primary process and secondary processes attach to
1050 * 0 on success, a negative errno value otherwise and rte_errno is set.
1053 mlx5_init_shared_data(void)
1055 const struct rte_memzone *mz;
1058 rte_spinlock_lock(&mlx5_shared_data_lock);
1059 if (mlx5_shared_data == NULL) {
1060 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1061 /* Allocate shared memory. */
1062 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1063 sizeof(*mlx5_shared_data),
1067 "Cannot allocate mlx5 shared data");
1071 mlx5_shared_data = mz->addr;
1072 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1073 rte_spinlock_init(&mlx5_shared_data->lock);
1075 /* Lookup allocated shared memory. */
1076 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1079 "Cannot attach mlx5 shared data");
1083 mlx5_shared_data = mz->addr;
1084 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1088 rte_spinlock_unlock(&mlx5_shared_data_lock);
1093 * Retrieve integer value from environment variable.
1096 * Environment variable name.
1099 * Integer value, 0 if the variable is not set.
1102 mlx5_getenv_int(const char *name)
1104 const char *val = getenv(name);
1112 * DPDK callback to add udp tunnel port
1115 * A pointer to eth_dev
1116 * @param[in] udp_tunnel
1117 * A pointer to udp tunnel
1120 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1123 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1124 struct rte_eth_udp_tunnel *udp_tunnel)
1126 MLX5_ASSERT(udp_tunnel != NULL);
1127 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1128 udp_tunnel->udp_port == 4789)
1130 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1131 udp_tunnel->udp_port == 4790)
1137 * Initialize process private data structure.
1140 * Pointer to Ethernet device structure.
1143 * 0 on success, a negative errno value otherwise and rte_errno is set.
1146 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1148 struct mlx5_priv *priv = dev->data->dev_private;
1149 struct mlx5_proc_priv *ppriv;
1153 * UAR register table follows the process private structure. BlueFlame
1154 * registers for Tx queues are stored in the table.
1157 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1158 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1159 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1164 ppriv->uar_table_sz = ppriv_size;
1165 dev->process_private = ppriv;
1170 * Un-initialize process private data structure.
1173 * Pointer to Ethernet device structure.
1176 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1178 if (!dev->process_private)
1180 rte_free(dev->process_private);
1181 dev->process_private = NULL;
1185 * DPDK callback to close the device.
1187 * Destroy all queues and objects, free memory.
1190 * Pointer to Ethernet device structure.
1193 mlx5_dev_close(struct rte_eth_dev *dev)
1195 struct mlx5_priv *priv = dev->data->dev_private;
1199 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1200 /* Check if process_private released. */
1201 if (!dev->process_private)
1203 mlx5_tx_uar_uninit_secondary(dev);
1204 mlx5_proc_priv_uninit(dev);
1205 rte_eth_dev_release_port(dev);
1210 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1212 ((priv->sh->ctx != NULL) ?
1213 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1215 * If default mreg copy action is removed at the stop stage,
1216 * the search will return none and nothing will be done anymore.
1218 mlx5_flow_stop_default(dev);
1219 mlx5_traffic_disable(dev);
1221 * If all the flows are already flushed in the device stop stage,
1222 * then this will return directly without any action.
1224 mlx5_flow_list_flush(dev, &priv->flows, true);
1225 mlx5_flow_meter_flush(dev, NULL);
1226 /* Free the intermediate buffers for flow creation. */
1227 mlx5_flow_free_intermediate(dev);
1228 /* Prevent crashes when queues are still in use. */
1229 dev->rx_pkt_burst = removed_rx_burst;
1230 dev->tx_pkt_burst = removed_tx_burst;
1232 /* Disable datapath on secondary process. */
1233 mlx5_mp_req_stop_rxtx(dev);
1234 if (priv->rxqs != NULL) {
1235 /* XXX race condition if mlx5_rx_burst() is still running. */
1237 for (i = 0; (i != priv->rxqs_n); ++i)
1238 mlx5_rxq_release(dev, i);
1242 if (priv->txqs != NULL) {
1243 /* XXX race condition if mlx5_tx_burst() is still running. */
1245 for (i = 0; (i != priv->txqs_n); ++i)
1246 mlx5_txq_release(dev, i);
1250 mlx5_proc_priv_uninit(dev);
1251 if (priv->mreg_cp_tbl)
1252 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1253 mlx5_mprq_free_mp(dev);
1254 mlx5_os_free_shared_dr(priv);
1255 if (priv->rss_conf.rss_key != NULL)
1256 rte_free(priv->rss_conf.rss_key);
1257 if (priv->reta_idx != NULL)
1258 rte_free(priv->reta_idx);
1259 if (priv->config.vf)
1260 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1261 dev->data->mac_addrs,
1262 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1263 if (priv->nl_socket_route >= 0)
1264 close(priv->nl_socket_route);
1265 if (priv->nl_socket_rdma >= 0)
1266 close(priv->nl_socket_rdma);
1267 if (priv->vmwa_context)
1268 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1269 ret = mlx5_hrxq_verify(dev);
1271 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1272 dev->data->port_id);
1273 ret = mlx5_ind_table_obj_verify(dev);
1275 DRV_LOG(WARNING, "port %u some indirection table still remain",
1276 dev->data->port_id);
1277 ret = mlx5_rxq_obj_verify(dev);
1279 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1280 dev->data->port_id);
1281 ret = mlx5_rxq_verify(dev);
1283 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1284 dev->data->port_id);
1285 ret = mlx5_txq_obj_verify(dev);
1287 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1288 dev->data->port_id);
1289 ret = mlx5_txq_verify(dev);
1291 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1292 dev->data->port_id);
1293 ret = mlx5_flow_verify(dev);
1295 DRV_LOG(WARNING, "port %u some flows still remain",
1296 dev->data->port_id);
1298 * Free the shared context in last turn, because the cleanup
1299 * routines above may use some shared fields, like
1300 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1301 * ifindex if Netlink fails.
1303 mlx5_free_shared_dev_ctx(priv->sh);
1304 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1308 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1309 struct mlx5_priv *opriv =
1310 rte_eth_devices[port_id].data->dev_private;
1313 opriv->domain_id != priv->domain_id ||
1314 &rte_eth_devices[port_id] == dev)
1320 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1322 memset(priv, 0, sizeof(*priv));
1323 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1325 * Reset mac_addrs to NULL such that it is not freed as part of
1326 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1327 * it is freed when dev_private is freed.
1329 dev->data->mac_addrs = NULL;
1333 * Verify and store value for device argument.
1336 * Key argument to verify.
1338 * Value associated with key.
1343 * 0 on success, a negative errno value otherwise and rte_errno is set.
1346 mlx5_args_check(const char *key, const char *val, void *opaque)
1348 struct mlx5_dev_config *config = opaque;
1352 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1353 if (!strcmp(MLX5_REPRESENTOR, key))
1356 tmp = strtol(val, NULL, 0);
1359 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1362 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1363 /* Negative values are acceptable for some keys only. */
1365 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1368 mod = tmp >= 0 ? tmp : -tmp;
1369 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1370 config->cqe_comp = !!tmp;
1371 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1372 config->cqe_pad = !!tmp;
1373 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1374 config->hw_padding = !!tmp;
1375 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1376 config->mprq.enabled = !!tmp;
1377 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1378 config->mprq.stride_num_n = tmp;
1379 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1380 config->mprq.stride_size_n = tmp;
1381 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1382 config->mprq.max_memcpy_len = tmp;
1383 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1384 config->mprq.min_rxqs_num = tmp;
1385 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1386 DRV_LOG(WARNING, "%s: deprecated parameter,"
1387 " converted to txq_inline_max", key);
1388 config->txq_inline_max = tmp;
1389 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1390 config->txq_inline_max = tmp;
1391 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1392 config->txq_inline_min = tmp;
1393 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1394 config->txq_inline_mpw = tmp;
1395 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1396 config->txqs_inline = tmp;
1397 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1398 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1399 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1400 config->mps = !!tmp;
1401 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1402 if (tmp != MLX5_TXDB_CACHED &&
1403 tmp != MLX5_TXDB_NCACHED &&
1404 tmp != MLX5_TXDB_HEURISTIC) {
1405 DRV_LOG(ERR, "invalid Tx doorbell "
1406 "mapping parameter");
1411 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1412 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1413 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1414 DRV_LOG(WARNING, "%s: deprecated parameter,"
1415 " converted to txq_inline_mpw", key);
1416 config->txq_inline_mpw = tmp;
1417 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1418 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1419 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1421 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1425 config->tx_pp = tmp;
1426 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1427 config->tx_skew = tmp;
1428 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1429 config->rx_vec_en = !!tmp;
1430 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1431 config->l3_vxlan_en = !!tmp;
1432 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1433 config->vf_nl_en = !!tmp;
1434 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1435 config->dv_esw_en = !!tmp;
1436 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1437 config->dv_flow_en = !!tmp;
1438 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1439 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1440 tmp != MLX5_XMETA_MODE_META16 &&
1441 tmp != MLX5_XMETA_MODE_META32) {
1442 DRV_LOG(ERR, "invalid extensive "
1443 "metadata parameter");
1447 config->dv_xmeta_en = tmp;
1448 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1449 config->lacp_by_user = !!tmp;
1450 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1451 config->mr_ext_memseg_en = !!tmp;
1452 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1453 config->max_dump_files_num = tmp;
1454 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1455 config->lro.timeout = tmp;
1456 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1457 DRV_LOG(DEBUG, "class argument is %s.", val);
1458 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1459 config->log_hp_size = tmp;
1460 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1461 if (tmp != MLX5_RCM_NONE &&
1462 tmp != MLX5_RCM_LIGHT &&
1463 tmp != MLX5_RCM_AGGR) {
1464 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1468 config->reclaim_mode = tmp;
1470 DRV_LOG(WARNING, "%s: unknown parameter", key);
1478 * Parse device parameters.
1481 * Pointer to device configuration structure.
1483 * Device arguments structure.
1486 * 0 on success, a negative errno value otherwise and rte_errno is set.
1489 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1491 const char **params = (const char *[]){
1492 MLX5_RXQ_CQE_COMP_EN,
1493 MLX5_RXQ_CQE_PAD_EN,
1494 MLX5_RXQ_PKT_PAD_EN,
1496 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1497 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1498 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1501 MLX5_TXQ_INLINE_MIN,
1502 MLX5_TXQ_INLINE_MAX,
1503 MLX5_TXQ_INLINE_MPW,
1504 MLX5_TXQS_MIN_INLINE,
1507 MLX5_TXQ_MPW_HDR_DSEG_EN,
1508 MLX5_TXQ_MAX_INLINE_LEN,
1520 MLX5_MR_EXT_MEMSEG_EN,
1522 MLX5_MAX_DUMP_FILES_NUM,
1523 MLX5_LRO_TIMEOUT_USEC,
1524 MLX5_CLASS_ARG_NAME,
1529 struct rte_kvargs *kvlist;
1533 if (devargs == NULL)
1535 /* Following UGLY cast is done to pass checkpatch. */
1536 kvlist = rte_kvargs_parse(devargs->args, params);
1537 if (kvlist == NULL) {
1541 /* Process parameters. */
1542 for (i = 0; (params[i] != NULL); ++i) {
1543 if (rte_kvargs_count(kvlist, params[i])) {
1544 ret = rte_kvargs_process(kvlist, params[i],
1545 mlx5_args_check, config);
1548 rte_kvargs_free(kvlist);
1553 rte_kvargs_free(kvlist);
1558 * PMD global initialization.
1560 * Independent from individual device, this function initializes global
1561 * per-PMD data structures distinguishing primary and secondary processes.
1562 * Hence, each initialization is called once per a process.
1565 * 0 on success, a negative errno value otherwise and rte_errno is set.
1568 mlx5_init_once(void)
1570 struct mlx5_shared_data *sd;
1571 struct mlx5_local_data *ld = &mlx5_local_data;
1574 if (mlx5_init_shared_data())
1576 sd = mlx5_shared_data;
1578 rte_spinlock_lock(&sd->lock);
1579 switch (rte_eal_process_type()) {
1580 case RTE_PROC_PRIMARY:
1583 LIST_INIT(&sd->mem_event_cb_list);
1584 rte_rwlock_init(&sd->mem_event_rwlock);
1585 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1586 mlx5_mr_mem_event_cb, NULL);
1587 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1588 mlx5_mp_primary_handle);
1591 sd->init_done = true;
1593 case RTE_PROC_SECONDARY:
1596 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1597 mlx5_mp_secondary_handle);
1600 ++sd->secondary_cnt;
1601 ld->init_done = true;
1607 rte_spinlock_unlock(&sd->lock);
1612 * Configures the minimal amount of data to inline into WQE
1613 * while sending packets.
1615 * - the txq_inline_min has the maximal priority, if this
1616 * key is specified in devargs
1617 * - if DevX is enabled the inline mode is queried from the
1618 * device (HCA attributes and NIC vport context if needed).
1619 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1620 * and none (0 bytes) for other NICs
1623 * Verbs device parameters (name, port, switch_info) to spawn.
1625 * Device configuration parameters.
1628 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1629 struct mlx5_dev_config *config)
1631 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1632 /* Application defines size of inlined data explicitly. */
1633 switch (spawn->pci_dev->id.device_id) {
1634 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1635 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1636 if (config->txq_inline_min <
1637 (int)MLX5_INLINE_HSIZE_L2) {
1639 "txq_inline_mix aligned to minimal"
1640 " ConnectX-4 required value %d",
1641 (int)MLX5_INLINE_HSIZE_L2);
1642 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1648 if (config->hca_attr.eth_net_offloads) {
1649 /* We have DevX enabled, inline mode queried successfully. */
1650 switch (config->hca_attr.wqe_inline_mode) {
1651 case MLX5_CAP_INLINE_MODE_L2:
1652 /* outer L2 header must be inlined. */
1653 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1655 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1656 /* No inline data are required by NIC. */
1657 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1658 config->hw_vlan_insert =
1659 config->hca_attr.wqe_vlan_insert;
1660 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1662 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1663 /* inline mode is defined by NIC vport context. */
1664 if (!config->hca_attr.eth_virt)
1666 switch (config->hca_attr.vport_inline_mode) {
1667 case MLX5_INLINE_MODE_NONE:
1668 config->txq_inline_min =
1669 MLX5_INLINE_HSIZE_NONE;
1671 case MLX5_INLINE_MODE_L2:
1672 config->txq_inline_min =
1673 MLX5_INLINE_HSIZE_L2;
1675 case MLX5_INLINE_MODE_IP:
1676 config->txq_inline_min =
1677 MLX5_INLINE_HSIZE_L3;
1679 case MLX5_INLINE_MODE_TCP_UDP:
1680 config->txq_inline_min =
1681 MLX5_INLINE_HSIZE_L4;
1683 case MLX5_INLINE_MODE_INNER_L2:
1684 config->txq_inline_min =
1685 MLX5_INLINE_HSIZE_INNER_L2;
1687 case MLX5_INLINE_MODE_INNER_IP:
1688 config->txq_inline_min =
1689 MLX5_INLINE_HSIZE_INNER_L3;
1691 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1692 config->txq_inline_min =
1693 MLX5_INLINE_HSIZE_INNER_L4;
1699 * We get here if we are unable to deduce
1700 * inline data size with DevX. Try PCI ID
1701 * to determine old NICs.
1703 switch (spawn->pci_dev->id.device_id) {
1704 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1705 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1706 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1707 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1708 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1709 config->hw_vlan_insert = 0;
1711 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1712 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1713 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1714 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1716 * These NICs support VLAN insertion from WQE and
1717 * report the wqe_vlan_insert flag. But there is the bug
1718 * and PFC control may be broken, so disable feature.
1720 config->hw_vlan_insert = 0;
1721 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1724 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1728 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1732 * Configures the metadata mask fields in the shared context.
1735 * Pointer to Ethernet device.
1738 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1740 struct mlx5_priv *priv = dev->data->dev_private;
1741 struct mlx5_dev_ctx_shared *sh = priv->sh;
1742 uint32_t meta, mark, reg_c0;
1744 reg_c0 = ~priv->vport_meta_mask;
1745 switch (priv->config.dv_xmeta_en) {
1746 case MLX5_XMETA_MODE_LEGACY:
1748 mark = MLX5_FLOW_MARK_MASK;
1750 case MLX5_XMETA_MODE_META16:
1751 meta = reg_c0 >> rte_bsf32(reg_c0);
1752 mark = MLX5_FLOW_MARK_MASK;
1754 case MLX5_XMETA_MODE_META32:
1756 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1764 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1765 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1766 sh->dv_mark_mask, mark);
1768 sh->dv_mark_mask = mark;
1769 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1770 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1771 sh->dv_meta_mask, meta);
1773 sh->dv_meta_mask = meta;
1774 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1775 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1776 sh->dv_meta_mask, reg_c0);
1778 sh->dv_regc0_mask = reg_c0;
1779 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1780 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1781 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1782 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1786 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1788 static const char *const dynf_names[] = {
1789 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1790 RTE_MBUF_DYNFLAG_METADATA_NAME,
1791 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1795 if (n < RTE_DIM(dynf_names))
1797 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1798 if (names[i] == NULL)
1800 strcpy(names[i], dynf_names[i]);
1802 return RTE_DIM(dynf_names);
1806 * Comparison callback to sort device data.
1808 * This is meant to be used with qsort().
1811 * Pointer to pointer to first data object.
1813 * Pointer to pointer to second data object.
1816 * 0 if both objects are equal, less than 0 if the first argument is less
1817 * than the second, greater than 0 otherwise.
1820 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1821 struct mlx5_dev_config *config)
1823 struct mlx5_dev_ctx_shared *sh = priv->sh;
1824 struct mlx5_dev_config *sh_conf = NULL;
1828 /* Nothing to compare for the single/first device. */
1829 if (sh->refcnt == 1)
1831 /* Find the device with shared context. */
1832 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1833 struct mlx5_priv *opriv =
1834 rte_eth_devices[port_id].data->dev_private;
1836 if (opriv && opriv != priv && opriv->sh == sh) {
1837 sh_conf = &opriv->config;
1843 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1844 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1845 " for shared %s context", sh->ibdev_name);
1849 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1850 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1851 " for shared %s context", sh->ibdev_name);
1859 * Look for the ethernet device belonging to mlx5 driver.
1861 * @param[in] port_id
1862 * port_id to start looking for device.
1863 * @param[in] pci_dev
1864 * Pointer to the hint PCI device. When device is being probed
1865 * the its siblings (master and preceding representors might
1866 * not have assigned driver yet (because the mlx5_os_pci_probe()
1867 * is not completed yet, for this case match on hint PCI
1868 * device may be used to detect sibling device.
1871 * port_id of found device, RTE_MAX_ETHPORT if not found.
1874 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1876 while (port_id < RTE_MAX_ETHPORTS) {
1877 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1879 if (dev->state != RTE_ETH_DEV_UNUSED &&
1881 (dev->device == &pci_dev->device ||
1882 (dev->device->driver &&
1883 dev->device->driver->name &&
1884 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1888 if (port_id >= RTE_MAX_ETHPORTS)
1889 return RTE_MAX_ETHPORTS;
1894 * DPDK callback to remove a PCI device.
1896 * This function removes all Ethernet devices belong to a given PCI device.
1898 * @param[in] pci_dev
1899 * Pointer to the PCI device.
1902 * 0 on success, the function cannot fail.
1905 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1909 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1911 * mlx5_dev_close() is not registered to secondary process,
1912 * call the close function explicitly for secondary process.
1914 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1915 mlx5_dev_close(&rte_eth_devices[port_id]);
1917 rte_eth_dev_close(port_id);
1922 static const struct rte_pci_id mlx5_pci_id_map[] = {
1924 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1928 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1932 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1933 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1936 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1937 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1940 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1941 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1944 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1948 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1949 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1953 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1956 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1957 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1960 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1961 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1964 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1965 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1968 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1969 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1972 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1973 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1976 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1977 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1980 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1981 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1984 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1985 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1992 struct rte_pci_driver mlx5_driver = {
1994 .name = MLX5_DRIVER_NAME
1996 .id_table = mlx5_pci_id_map,
1997 .probe = mlx5_os_pci_probe,
1998 .remove = mlx5_pci_remove,
1999 .dma_map = mlx5_dma_map,
2000 .dma_unmap = mlx5_dma_unmap,
2001 .drv_flags = PCI_DRV_FLAGS,
2004 /* Initialize driver log type. */
2005 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2008 * Driver initialization routine.
2010 RTE_INIT(rte_mlx5_pmd_init)
2012 /* Build the static tables for Verbs conversion. */
2013 mlx5_set_ptype_table();
2014 mlx5_set_cksum_table();
2015 mlx5_set_swp_types_table();
2017 rte_pci_register(&mlx5_driver);
2020 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2021 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2022 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");