drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37
  38 #include "mlx5.h"
  39 #include "mlx5_utils.h"
  40 #include "mlx5_rxtx.h"
  41 #include "mlx5_autoconf.h"
  42 #include "mlx5_defs.h"
  43 #include "mlx5_glue.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to configure inline send. */
  49 #define MLX5_TXQ_INLINE "txq_inline"
  50
  51 /*
  52  * Device parameter to configure the number of TX queues threshold for
  53  * enabling inline send.
  54  */
  55 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  56
  57 /* Device parameter to enable multi-packet send WQEs. */
  58 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  59
  60 /* Device parameter to include 2 dsegs in the title WQEBB. */
  61 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  62
  63 /* Device parameter to limit the size of inlining packet. */
  64 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  65
  66 /* Device parameter to enable hardware Tx vector. */
  67 #define MLX5_TX_VEC_EN "tx_vec_en"
  68
  69 /* Device parameter to enable hardware Rx vector. */
  70 #define MLX5_RX_VEC_EN "rx_vec_en"
  71
  72 /* Activate Netlink support in VF mode. */
  73 #define MLX5_VF_NL_EN "vf_nl_en"
  74
  75 #ifndef HAVE_IBV_MLX5_MOD_MPW
  76 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  77 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  78 #endif
  79
  80 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  81 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
  82 #endif
  83
  84 /** Driver-specific log messages type. */
  85 int mlx5_logtype;
  86
  87 /**
  88  * Retrieve integer value from environment variable.
  89  *
  90  * @param[in] name
  91  *   Environment variable name.
  92  *
  93  * @return
  94  *   Integer value, 0 if the variable is not set.
  95  */
  96 int
  97 mlx5_getenv_int(const char *name)
  98 {
  99         const char *val = getenv(name);
 100
 101         if (val == NULL)
 102                 return 0;
 103         return atoi(val);
 104 }
 105
 106 /**
 107  * Verbs callback to allocate a memory. This function should allocate the space
 108  * according to the size provided residing inside a huge page.
 109  * Please note that all allocation must respect the alignment from libmlx5
 110  * (i.e. currently sysconf(_SC_PAGESIZE)).
 111  *
 112  * @param[in] size
 113  *   The size in bytes of the memory to allocate.
 114  * @param[in] data
 115  *   A pointer to the callback data.
 116  *
 117  * @return
 118  *   Allocated buffer, NULL otherwise and rte_errno is set.
 119  */
 120 static void *
 121 mlx5_alloc_verbs_buf(size_t size, void *data)
 122 {
 123         struct priv *priv = data;
 124         void *ret;
 125         size_t alignment = sysconf(_SC_PAGESIZE);
 126         unsigned int socket = SOCKET_ID_ANY;
 127
 128         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 129                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 130
 131                 socket = ctrl->socket;
 132         } else if (priv->verbs_alloc_ctx.type ==
 133                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 134                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 135
 136                 socket = ctrl->socket;
 137         }
 138         assert(data != NULL);
 139         ret = rte_malloc_socket(__func__, size, alignment, socket);
 140         if (!ret && size)
 141                 rte_errno = ENOMEM;
 142         return ret;
 143 }
 144
 145 /**
 146  * Verbs callback to free a memory.
 147  *
 148  * @param[in] ptr
 149  *   A pointer to the memory to free.
 150  * @param[in] data
 151  *   A pointer to the callback data.
 152  */
 153 static void
 154 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 155 {
 156         assert(data != NULL);
 157         rte_free(ptr);
 158 }
 159
 160 /**
 161  * DPDK callback to close the device.
 162  *
 163  * Destroy all queues and objects, free memory.
 164  *
 165  * @param dev
 166  *   Pointer to Ethernet device structure.
 167  */
 168 static void
 169 mlx5_dev_close(struct rte_eth_dev *dev)
 170 {
 171         struct priv *priv = dev->data->dev_private;
 172         unsigned int i;
 173         int ret;
 174
 175         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 176                 dev->data->port_id,
 177                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 178         /* In case mlx5_dev_stop() has not been called. */
 179         mlx5_dev_interrupt_handler_uninstall(dev);
 180         mlx5_traffic_disable(dev);
 181         /* Prevent crashes when queues are still in use. */
 182         dev->rx_pkt_burst = removed_rx_burst;
 183         dev->tx_pkt_burst = removed_tx_burst;
 184         if (priv->rxqs != NULL) {
 185                 /* XXX race condition if mlx5_rx_burst() is still running. */
 186                 usleep(1000);
 187                 for (i = 0; (i != priv->rxqs_n); ++i)
 188                         mlx5_rxq_release(dev, i);
 189                 priv->rxqs_n = 0;
 190                 priv->rxqs = NULL;
 191         }
 192         if (priv->txqs != NULL) {
 193                 /* XXX race condition if mlx5_tx_burst() is still running. */
 194                 usleep(1000);
 195                 for (i = 0; (i != priv->txqs_n); ++i)
 196                         mlx5_txq_release(dev, i);
 197                 priv->txqs_n = 0;
 198                 priv->txqs = NULL;
 199         }
 200         if (priv->pd != NULL) {
 201                 assert(priv->ctx != NULL);
 202                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 203                 claim_zero(mlx5_glue->close_device(priv->ctx));
 204         } else
 205                 assert(priv->ctx == NULL);
 206         if (priv->rss_conf.rss_key != NULL)
 207                 rte_free(priv->rss_conf.rss_key);
 208         if (priv->reta_idx != NULL)
 209                 rte_free(priv->reta_idx);
 210         if (priv->primary_socket)
 211                 mlx5_socket_uninit(dev);
 212         if (priv->config.vf)
 213                 mlx5_nl_mac_addr_flush(dev);
 214         if (priv->nl_socket >= 0)
 215                 close(priv->nl_socket);
 216         ret = mlx5_hrxq_ibv_verify(dev);
 217         if (ret)
 218                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 219                         dev->data->port_id);
 220         ret = mlx5_ind_table_ibv_verify(dev);
 221         if (ret)
 222                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 223                         dev->data->port_id);
 224         ret = mlx5_rxq_ibv_verify(dev);
 225         if (ret)
 226                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 227                         dev->data->port_id);
 228         ret = mlx5_rxq_verify(dev);
 229         if (ret)
 230                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 231                         dev->data->port_id);
 232         ret = mlx5_txq_ibv_verify(dev);
 233         if (ret)
 234                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 235                         dev->data->port_id);
 236         ret = mlx5_txq_verify(dev);
 237         if (ret)
 238                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 239                         dev->data->port_id);
 240         ret = mlx5_flow_verify(dev);
 241         if (ret)
 242                 DRV_LOG(WARNING, "port %u some flows still remain",
 243                         dev->data->port_id);
 244         ret = mlx5_mr_verify(dev);
 245         if (ret)
 246                 DRV_LOG(WARNING, "port %u some memory region still remain",
 247                         dev->data->port_id);
 248         memset(priv, 0, sizeof(*priv));
 249 }
 250
 251 const struct eth_dev_ops mlx5_dev_ops = {
 252         .dev_configure = mlx5_dev_configure,
 253         .dev_start = mlx5_dev_start,
 254         .dev_stop = mlx5_dev_stop,
 255         .dev_set_link_down = mlx5_set_link_down,
 256         .dev_set_link_up = mlx5_set_link_up,
 257         .dev_close = mlx5_dev_close,
 258         .promiscuous_enable = mlx5_promiscuous_enable,
 259         .promiscuous_disable = mlx5_promiscuous_disable,
 260         .allmulticast_enable = mlx5_allmulticast_enable,
 261         .allmulticast_disable = mlx5_allmulticast_disable,
 262         .link_update = mlx5_link_update,
 263         .stats_get = mlx5_stats_get,
 264         .stats_reset = mlx5_stats_reset,
 265         .xstats_get = mlx5_xstats_get,
 266         .xstats_reset = mlx5_xstats_reset,
 267         .xstats_get_names = mlx5_xstats_get_names,
 268         .dev_infos_get = mlx5_dev_infos_get,
 269         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 270         .vlan_filter_set = mlx5_vlan_filter_set,
 271         .rx_queue_setup = mlx5_rx_queue_setup,
 272         .tx_queue_setup = mlx5_tx_queue_setup,
 273         .rx_queue_release = mlx5_rx_queue_release,
 274         .tx_queue_release = mlx5_tx_queue_release,
 275         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 276         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 277         .mac_addr_remove = mlx5_mac_addr_remove,
 278         .mac_addr_add = mlx5_mac_addr_add,
 279         .mac_addr_set = mlx5_mac_addr_set,
 280         .mtu_set = mlx5_dev_set_mtu,
 281         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 282         .vlan_offload_set = mlx5_vlan_offload_set,
 283         .reta_update = mlx5_dev_rss_reta_update,
 284         .reta_query = mlx5_dev_rss_reta_query,
 285         .rss_hash_update = mlx5_rss_hash_update,
 286         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 287         .filter_ctrl = mlx5_dev_filter_ctrl,
 288         .rx_descriptor_status = mlx5_rx_descriptor_status,
 289         .tx_descriptor_status = mlx5_tx_descriptor_status,
 290         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 291         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 292         .is_removed = mlx5_is_removed,
 293 };
 294
 295 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 296         .stats_get = mlx5_stats_get,
 297         .stats_reset = mlx5_stats_reset,
 298         .xstats_get = mlx5_xstats_get,
 299         .xstats_reset = mlx5_xstats_reset,
 300         .xstats_get_names = mlx5_xstats_get_names,
 301         .dev_infos_get = mlx5_dev_infos_get,
 302         .rx_descriptor_status = mlx5_rx_descriptor_status,
 303         .tx_descriptor_status = mlx5_tx_descriptor_status,
 304 };
 305
 306 /* Available operators in flow isolated mode. */
 307 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 308         .dev_configure = mlx5_dev_configure,
 309         .dev_start = mlx5_dev_start,
 310         .dev_stop = mlx5_dev_stop,
 311         .dev_set_link_down = mlx5_set_link_down,
 312         .dev_set_link_up = mlx5_set_link_up,
 313         .dev_close = mlx5_dev_close,
 314         .link_update = mlx5_link_update,
 315         .stats_get = mlx5_stats_get,
 316         .stats_reset = mlx5_stats_reset,
 317         .xstats_get = mlx5_xstats_get,
 318         .xstats_reset = mlx5_xstats_reset,
 319         .xstats_get_names = mlx5_xstats_get_names,
 320         .dev_infos_get = mlx5_dev_infos_get,
 321         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 322         .vlan_filter_set = mlx5_vlan_filter_set,
 323         .rx_queue_setup = mlx5_rx_queue_setup,
 324         .tx_queue_setup = mlx5_tx_queue_setup,
 325         .rx_queue_release = mlx5_rx_queue_release,
 326         .tx_queue_release = mlx5_tx_queue_release,
 327         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 328         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 329         .mac_addr_remove = mlx5_mac_addr_remove,
 330         .mac_addr_add = mlx5_mac_addr_add,
 331         .mac_addr_set = mlx5_mac_addr_set,
 332         .mtu_set = mlx5_dev_set_mtu,
 333         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 334         .vlan_offload_set = mlx5_vlan_offload_set,
 335         .filter_ctrl = mlx5_dev_filter_ctrl,
 336         .rx_descriptor_status = mlx5_rx_descriptor_status,
 337         .tx_descriptor_status = mlx5_tx_descriptor_status,
 338         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 339         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 340         .is_removed = mlx5_is_removed,
 341 };
 342
 343 static struct {
 344         struct rte_pci_addr pci_addr; /* associated PCI address */
 345         uint32_t ports; /* physical ports bitfield. */
 346 } mlx5_dev[32];
 347
 348 /**
 349  * Get device index in mlx5_dev[] from PCI bus address.
 350  *
 351  * @param[in] pci_addr
 352  *   PCI bus address to look for.
 353  *
 354  * @return
 355  *   mlx5_dev[] index on success, -1 on failure.
 356  */
 357 static int
 358 mlx5_dev_idx(struct rte_pci_addr *pci_addr)
 359 {
 360         unsigned int i;
 361         int ret = -1;
 362
 363         assert(pci_addr != NULL);
 364         for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) {
 365                 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) &&
 366                     (mlx5_dev[i].pci_addr.bus == pci_addr->bus) &&
 367                     (mlx5_dev[i].pci_addr.devid == pci_addr->devid) &&
 368                     (mlx5_dev[i].pci_addr.function == pci_addr->function))
 369                         return i;
 370                 if ((mlx5_dev[i].ports == 0) && (ret == -1))
 371                         ret = i;
 372         }
 373         return ret;
 374 }
 375
 376 /**
 377  * Verify and store value for device argument.
 378  *
 379  * @param[in] key
 380  *   Key argument to verify.
 381  * @param[in] val
 382  *   Value associated with key.
 383  * @param opaque
 384  *   User data.
 385  *
 386  * @return
 387  *   0 on success, a negative errno value otherwise and rte_errno is set.
 388  */
 389 static int
 390 mlx5_args_check(const char *key, const char *val, void *opaque)
 391 {
 392         struct mlx5_dev_config *config = opaque;
 393         unsigned long tmp;
 394
 395         errno = 0;
 396         tmp = strtoul(val, NULL, 0);
 397         if (errno) {
 398                 rte_errno = errno;
 399                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 400                 return -rte_errno;
 401         }
 402         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 403                 config->cqe_comp = !!tmp;
 404         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 405                 config->txq_inline = tmp;
 406         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 407                 config->txqs_inline = tmp;
 408         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 409                 config->mps = !!tmp ? config->mps : 0;
 410         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 411                 config->mpw_hdr_dseg = !!tmp;
 412         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 413                 config->inline_max_packet_sz = tmp;
 414         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 415                 config->tx_vec_en = !!tmp;
 416         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 417                 config->rx_vec_en = !!tmp;
 418         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 419                 config->vf_nl_en = !!tmp;
 420         } else {
 421                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 422                 rte_errno = EINVAL;
 423                 return -rte_errno;
 424         }
 425         return 0;
 426 }
 427
 428 /**
 429  * Parse device parameters.
 430  *
 431  * @param config
 432  *   Pointer to device configuration structure.
 433  * @param devargs
 434  *   Device arguments structure.
 435  *
 436  * @return
 437  *   0 on success, a negative errno value otherwise and rte_errno is set.
 438  */
 439 static int
 440 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 441 {
 442         const char **params = (const char *[]){
 443                 MLX5_RXQ_CQE_COMP_EN,
 444                 MLX5_TXQ_INLINE,
 445                 MLX5_TXQS_MIN_INLINE,
 446                 MLX5_TXQ_MPW_EN,
 447                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 448                 MLX5_TXQ_MAX_INLINE_LEN,
 449                 MLX5_TX_VEC_EN,
 450                 MLX5_RX_VEC_EN,
 451                 MLX5_VF_NL_EN,
 452                 NULL,
 453         };
 454         struct rte_kvargs *kvlist;
 455         int ret = 0;
 456         int i;
 457
 458         if (devargs == NULL)
 459                 return 0;
 460         /* Following UGLY cast is done to pass checkpatch. */
 461         kvlist = rte_kvargs_parse(devargs->args, params);
 462         if (kvlist == NULL)
 463                 return 0;
 464         /* Process parameters. */
 465         for (i = 0; (params[i] != NULL); ++i) {
 466                 if (rte_kvargs_count(kvlist, params[i])) {
 467                         ret = rte_kvargs_process(kvlist, params[i],
 468                                                  mlx5_args_check, config);
 469                         if (ret) {
 470                                 rte_errno = EINVAL;
 471                                 rte_kvargs_free(kvlist);
 472                                 return -rte_errno;
 473                         }
 474                 }
 475         }
 476         rte_kvargs_free(kvlist);
 477         return 0;
 478 }
 479
 480 static struct rte_pci_driver mlx5_driver;
 481
 482 /*
 483  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 484  * local resource used by both primary and secondary to avoid duplicate
 485  * reservation.
 486  * The space has to be available on both primary and secondary process,
 487  * TXQ UAR maps to this area using fixed mmap w/o double check.
 488  */
 489 static void *uar_base;
 490
 491 static int
 492 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 493                 const struct rte_memseg *ms, void *arg)
 494 {
 495         void **addr = arg;
 496
 497         if (*addr == NULL)
 498                 *addr = ms->addr;
 499         else
 500                 *addr = RTE_MIN(*addr, ms->addr);
 501
 502         return 0;
 503 }
 504
 505 /**
 506  * Reserve UAR address space for primary process.
 507  *
 508  * @param[in] dev
 509  *   Pointer to Ethernet device.
 510  *
 511  * @return
 512  *   0 on success, a negative errno value otherwise and rte_errno is set.
 513  */
 514 static int
 515 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 516 {
 517         struct priv *priv = dev->data->dev_private;
 518         void *addr = (void *)0;
 519
 520         if (uar_base) { /* UAR address space mapped. */
 521                 priv->uar_base = uar_base;
 522                 return 0;
 523         }
 524         /* find out lower bound of hugepage segments */
 525         rte_memseg_walk(find_lower_va_bound, &addr);
 526
 527         /* keep distance to hugepages to minimize potential conflicts. */
 528         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 529         /* anonymous mmap, no real memory consumption. */
 530         addr = mmap(addr, MLX5_UAR_SIZE,
 531                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 532         if (addr == MAP_FAILED) {
 533                 DRV_LOG(ERR,
 534                         "port %u failed to reserve UAR address space, please"
 535                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 536                         dev->data->port_id);
 537                 rte_errno = ENOMEM;
 538                 return -rte_errno;
 539         }
 540         /* Accept either same addr or a new addr returned from mmap if target
 541          * range occupied.
 542          */
 543         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 544                 dev->data->port_id, addr);
 545         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 546         uar_base = addr; /* process local, don't reserve again. */
 547         return 0;
 548 }
 549
 550 /**
 551  * Reserve UAR address space for secondary process, align with
 552  * primary process.
 553  *
 554  * @param[in] dev
 555  *   Pointer to Ethernet device.
 556  *
 557  * @return
 558  *   0 on success, a negative errno value otherwise and rte_errno is set.
 559  */
 560 static int
 561 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 562 {
 563         struct priv *priv = dev->data->dev_private;
 564         void *addr;
 565
 566         assert(priv->uar_base);
 567         if (uar_base) { /* already reserved. */
 568                 assert(uar_base == priv->uar_base);
 569                 return 0;
 570         }
 571         /* anonymous mmap, no real memory consumption. */
 572         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 573                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 574         if (addr == MAP_FAILED) {
 575                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 576                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 577                 rte_errno = ENXIO;
 578                 return -rte_errno;
 579         }
 580         if (priv->uar_base != addr) {
 581                 DRV_LOG(ERR,
 582                         "port %u UAR address %p size %llu occupied, please"
 583                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 584                         " --base-virtaddr",
 585                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 586                 rte_errno = ENXIO;
 587                 return -rte_errno;
 588         }
 589         uar_base = addr; /* process local, don't reserve again */
 590         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 591                 dev->data->port_id, addr);
 592         return 0;
 593 }
 594
 595 /**
 596  * DPDK callback to register a PCI device.
 597  *
 598  * This function creates an Ethernet device for each port of a given
 599  * PCI device.
 600  *
 601  * @param[in] pci_drv
 602  *   PCI driver structure (mlx5_driver).
 603  * @param[in] pci_dev
 604  *   PCI device information.
 605  *
 606  * @return
 607  *   0 on success, a negative errno value otherwise and rte_errno is set.
 608  */
 609 static int
 610 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611                struct rte_pci_device *pci_dev)
 612 {
 613         struct ibv_device **list = NULL;
 614         struct ibv_device *ibv_dev;
 615         int err = 0;
 616         struct ibv_context *attr_ctx = NULL;
 617         struct ibv_device_attr_ex device_attr;
 618         unsigned int vf;
 619         unsigned int mps;
 620         unsigned int cqe_comp;
 621         unsigned int tunnel_en = 0;
 622         int idx;
 623         int i;
 624         struct mlx5dv_context attrs_out = {0};
 625 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 626         struct ibv_counter_set_description cs_desc;
 627 #endif
 628
 629         assert(pci_drv == &mlx5_driver);
 630         /* Get mlx5_dev[] index. */
 631         idx = mlx5_dev_idx(&pci_dev->addr);
 632         if (idx == -1) {
 633                 DRV_LOG(ERR, "this driver cannot support any more adapters");
 634                 err = ENOMEM;
 635                 goto error;
 636         }
 637         DRV_LOG(DEBUG, "using driver device index %d", idx);
 638         /* Save PCI address. */
 639         mlx5_dev[idx].pci_addr = pci_dev->addr;
 640         list = mlx5_glue->get_device_list(&i);
 641         if (list == NULL) {
 642                 assert(errno);
 643                 err = errno;
 644                 if (errno == ENOSYS)
 645                         DRV_LOG(ERR,
 646                                 "cannot list devices, is ib_uverbs loaded?");
 647                 goto error;
 648         }
 649         assert(i >= 0);
 650         /*
 651          * For each listed device, check related sysfs entry against
 652          * the provided PCI ID.
 653          */
 654         while (i != 0) {
 655                 struct rte_pci_addr pci_addr;
 656
 657                 --i;
 658                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 659                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 660                         continue;
 661                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 662                     (pci_dev->addr.bus != pci_addr.bus) ||
 663                     (pci_dev->addr.devid != pci_addr.devid) ||
 664                     (pci_dev->addr.function != pci_addr.function))
 665                         continue;
 666                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 667                         list[i]->name);
 668                 vf = ((pci_dev->id.device_id ==
 669                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 670                       (pci_dev->id.device_id ==
 671                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 672                       (pci_dev->id.device_id ==
 673                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 674                       (pci_dev->id.device_id ==
 675                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 676                 attr_ctx = mlx5_glue->open_device(list[i]);
 677                 rte_errno = errno;
 678                 err = rte_errno;
 679                 break;
 680         }
 681         if (attr_ctx == NULL) {
 682                 mlx5_glue->free_device_list(list);
 683                 switch (err) {
 684                 case 0:
 685                         DRV_LOG(ERR,
 686                                 "cannot access device, is mlx5_ib loaded?");
 687                         err = ENODEV;
 688                         goto error;
 689                 case EINVAL:
 690                         DRV_LOG(ERR,
 691                                 "cannot use device, are drivers up to date?");
 692                         goto error;
 693                 }
 694         }
 695         ibv_dev = list[i];
 696         DRV_LOG(DEBUG, "device opened");
 697         /*
 698          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 699          * as all ConnectX-5 devices.
 700          */
 701 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 702         attrs_out.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 703 #endif
 704         mlx5_glue->dv_query_device(attr_ctx, &attrs_out);
 705         if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 706                 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 707                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 708                         mps = MLX5_MPW_ENHANCED;
 709                 } else {
 710                         DRV_LOG(DEBUG, "MPW is supported");
 711                         mps = MLX5_MPW;
 712                 }
 713         } else {
 714                 DRV_LOG(DEBUG, "MPW isn't supported");
 715                 mps = MLX5_MPW_DISABLED;
 716         }
 717         if (RTE_CACHE_LINE_SIZE == 128 &&
 718             !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 719                 cqe_comp = 0;
 720         else
 721                 cqe_comp = 1;
 722 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 723         if (attrs_out.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 724                 tunnel_en = ((attrs_out.tunnel_offloads_caps &
 725                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 726                              (attrs_out.tunnel_offloads_caps &
 727                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 728         }
 729         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 730                 tunnel_en ? "" : "not ");
 731 #else
 732         DRV_LOG(WARNING,
 733                 "tunnel offloading disabled due to old OFED/rdma-core version");
 734 #endif
 735         if (mlx5_glue->query_device_ex(attr_ctx, NULL, &device_attr)) {
 736                 err = errno;
 737                 goto error;
 738         }
 739         DRV_LOG(INFO, "%u port(s) detected",
 740                 device_attr.orig_attr.phys_port_cnt);
 741         for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) {
 742                 char name[RTE_ETH_NAME_MAX_LEN];
 743                 int len;
 744                 uint32_t port = i + 1; /* ports are indexed from one */
 745                 uint32_t test = (1 << i);
 746                 struct ibv_context *ctx = NULL;
 747                 struct ibv_port_attr port_attr;
 748                 struct ibv_pd *pd = NULL;
 749                 struct priv *priv = NULL;
 750                 struct rte_eth_dev *eth_dev = NULL;
 751                 struct ibv_device_attr_ex device_attr_ex;
 752                 struct ether_addr mac;
 753                 struct mlx5_dev_config config = {
 754                         .cqe_comp = cqe_comp,
 755                         .mps = mps,
 756                         .tunnel_en = tunnel_en,
 757                         .tx_vec_en = 1,
 758                         .rx_vec_en = 1,
 759                         .mpw_hdr_dseg = 0,
 760                         .txq_inline = MLX5_ARG_UNSET,
 761                         .txqs_inline = MLX5_ARG_UNSET,
 762                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 763                         .vf_nl_en = 1,
 764                 };
 765
 766                 len = snprintf(name, sizeof(name), PCI_PRI_FMT,
 767                          pci_dev->addr.domain, pci_dev->addr.bus,
 768                          pci_dev->addr.devid, pci_dev->addr.function);
 769                 if (device_attr.orig_attr.phys_port_cnt > 1)
 770                         snprintf(name + len, sizeof(name), " port %u", i);
 771                 mlx5_dev[idx].ports |= test;
 772                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 773                         eth_dev = rte_eth_dev_attach_secondary(name);
 774                         if (eth_dev == NULL) {
 775                                 DRV_LOG(ERR, "can not attach rte ethdev");
 776                                 rte_errno = ENOMEM;
 777                                 err = rte_errno;
 778                                 goto error;
 779                         }
 780                         eth_dev->device = &pci_dev->device;
 781                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 782                         err = mlx5_uar_init_secondary(eth_dev);
 783                         if (err)
 784                                 goto error;
 785                         /* Receive command fd from primary process */
 786                         err = mlx5_socket_connect(eth_dev);
 787                         if (err)
 788                                 goto error;
 789                         /* Remap UAR for Tx queues. */
 790                         err = mlx5_tx_uar_remap(eth_dev, err);
 791                         if (err)
 792                                 goto error;
 793                         /*
 794                          * Ethdev pointer is still required as input since
 795                          * the primary device is not accessible from the
 796                          * secondary process.
 797                          */
 798                         eth_dev->rx_pkt_burst =
 799                                 mlx5_select_rx_function(eth_dev);
 800                         eth_dev->tx_pkt_burst =
 801                                 mlx5_select_tx_function(eth_dev);
 802                         continue;
 803                 }
 804                 DRV_LOG(DEBUG, "using port %u (%08" PRIx32 ")", port, test);
 805                 ctx = mlx5_glue->open_device(ibv_dev);
 806                 if (ctx == NULL) {
 807                         err = ENODEV;
 808                         goto port_error;
 809                 }
 810                 /* Check port status. */
 811                 err = mlx5_glue->query_port(ctx, port, &port_attr);
 812                 if (err) {
 813                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 814                         goto port_error;
 815                 }
 816                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 817                         DRV_LOG(ERR,
 818                                 "port %d is not configured in Ethernet mode",
 819                                 port);
 820                         err = EINVAL;
 821                         goto port_error;
 822                 }
 823                 if (port_attr.state != IBV_PORT_ACTIVE)
 824                         DRV_LOG(DEBUG, "port %d is not active: \"%s\" (%d)",
 825                                 port,
 826                                 mlx5_glue->port_state_str(port_attr.state),
 827                                 port_attr.state);
 828                 /* Allocate protection domain. */
 829                 pd = mlx5_glue->alloc_pd(ctx);
 830                 if (pd == NULL) {
 831                         DRV_LOG(ERR, "PD allocation failure");
 832                         err = ENOMEM;
 833                         goto port_error;
 834                 }
 835                 mlx5_dev[idx].ports |= test;
 836                 /* from rte_ethdev.c */
 837                 priv = rte_zmalloc("ethdev private structure",
 838                                    sizeof(*priv),
 839                                    RTE_CACHE_LINE_SIZE);
 840                 if (priv == NULL) {
 841                         DRV_LOG(ERR, "priv allocation failure");
 842                         err = ENOMEM;
 843                         goto port_error;
 844                 }
 845                 priv->ctx = ctx;
 846                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 847                         sizeof(priv->ibdev_path));
 848                 priv->device_attr = device_attr;
 849                 priv->port = port;
 850                 priv->pd = pd;
 851                 priv->mtu = ETHER_MTU;
 852                 err = mlx5_args(&config, pci_dev->device.devargs);
 853                 if (err) {
 854                         DRV_LOG(ERR, "failed to process device arguments: %s",
 855                                 strerror(err));
 856                         goto port_error;
 857                 }
 858                 if (mlx5_glue->query_device_ex(ctx, NULL, &device_attr_ex)) {
 859                         DRV_LOG(ERR, "ibv_query_device_ex() failed");
 860                         err = errno;
 861                         goto port_error;
 862                 }
 863                 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex &
 864                                     IBV_DEVICE_RAW_IP_CSUM);
 865                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 866                         (config.hw_csum ? "" : "not "));
 867 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 868                 config.flow_counter_en = !!(device_attr.max_counter_sets);
 869                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 870                 DRV_LOG(DEBUG,
 871                         "counter type = %d, num of cs = %ld, attributes = %d",
 872                         cs_desc.counter_type, cs_desc.num_of_cs,
 873                         cs_desc.attributes);
 874 #endif
 875                 config.ind_table_max_size =
 876                         device_attr_ex.rss_caps.max_rwq_indirection_table_size;
 877                 /* Remove this check once DPDK supports larger/variable
 878                  * indirection tables. */
 879                 if (config.ind_table_max_size >
 880                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 881                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 882                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 883                         config.ind_table_max_size);
 884                 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps &
 885                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 886                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 887                         (config.hw_vlan_strip ? "" : "not "));
 888
 889                 config.hw_fcs_strip = !!(device_attr_ex.raw_packet_caps &
 890                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 891                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 892                         (config.hw_fcs_strip ? "" : "not "));
 893
 894 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 895                 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align;
 896 #endif
 897                 DRV_LOG(DEBUG,
 898                         "hardware Rx end alignment padding is %ssupported",
 899                         (config.hw_padding ? "" : "not "));
 900                 config.vf = vf;
 901                 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) &&
 902                               (device_attr_ex.tso_caps.supported_qpts &
 903                               (1 << IBV_QPT_RAW_PACKET)));
 904                 if (config.tso)
 905                         config.tso_max_payload_sz =
 906                                         device_attr_ex.tso_caps.max_tso;
 907                 if (config.mps && !mps) {
 908                         DRV_LOG(ERR,
 909                                 "multi-packet send not supported on this device"
 910                                 " (" MLX5_TXQ_MPW_EN ")");
 911                         err = ENOTSUP;
 912                         goto port_error;
 913                 }
 914                 DRV_LOG(INFO, "%s MPS is %s",
 915                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 916                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 917                         "disabled");
 918                 if (config.cqe_comp && !cqe_comp) {
 919                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
 920                         config.cqe_comp = 0;
 921                 }
 922                 eth_dev = rte_eth_dev_allocate(name);
 923                 if (eth_dev == NULL) {
 924                         DRV_LOG(ERR, "can not allocate rte ethdev");
 925                         err = ENOMEM;
 926                         goto port_error;
 927                 }
 928                 eth_dev->data->dev_private = priv;
 929                 priv->dev = eth_dev;
 930                 eth_dev->data->mac_addrs = priv->mac;
 931                 eth_dev->device = &pci_dev->device;
 932                 rte_eth_copy_pci_info(eth_dev, pci_dev);
 933                 eth_dev->device->driver = &mlx5_driver.driver;
 934                 err = mlx5_uar_init_primary(eth_dev);
 935                 if (err)
 936                         goto port_error;
 937                 /* Configure the first MAC address by default. */
 938                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
 939                         DRV_LOG(ERR,
 940                                 "port %u cannot get MAC address, is mlx5_en"
 941                                 " loaded? (errno: %s)",
 942                                 eth_dev->data->port_id, strerror(errno));
 943                         err = ENODEV;
 944                         goto port_error;
 945                 }
 946                 DRV_LOG(INFO,
 947                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
 948                         eth_dev->data->port_id,
 949                         mac.addr_bytes[0], mac.addr_bytes[1],
 950                         mac.addr_bytes[2], mac.addr_bytes[3],
 951                         mac.addr_bytes[4], mac.addr_bytes[5]);
 952 #ifndef NDEBUG
 953                 {
 954                         char ifname[IF_NAMESIZE];
 955
 956                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
 957                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
 958                                         eth_dev->data->port_id, ifname);
 959                         else
 960                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
 961                                         eth_dev->data->port_id);
 962                 }
 963 #endif
 964                 /* Get actual MTU if possible. */
 965                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
 966                 if (err)
 967                         goto port_error;
 968                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
 969                         priv->mtu);
 970                 /*
 971                  * Initialize burst functions to prevent crashes before link-up.
 972                  */
 973                 eth_dev->rx_pkt_burst = removed_rx_burst;
 974                 eth_dev->tx_pkt_burst = removed_tx_burst;
 975                 eth_dev->dev_ops = &mlx5_dev_ops;
 976                 /* Register MAC address. */
 977                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
 978                 priv->nl_socket = -1;
 979                 priv->nl_sn = 0;
 980                 if (vf && config.vf_nl_en) {
 981                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
 982                         if (priv->nl_socket < 0)
 983                                 priv->nl_socket = -1;
 984                         mlx5_nl_mac_addr_sync(eth_dev);
 985                 }
 986                 TAILQ_INIT(&priv->flows);
 987                 TAILQ_INIT(&priv->ctrl_flows);
 988                 /* Hint libmlx5 to use PMD allocator for data plane resources */
 989                 struct mlx5dv_ctx_allocators alctr = {
 990                         .alloc = &mlx5_alloc_verbs_buf,
 991                         .free = &mlx5_free_verbs_buf,
 992                         .data = priv,
 993                 };
 994                 mlx5_glue->dv_set_context_attr(ctx,
 995                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
 996                                                (void *)((uintptr_t)&alctr));
 997                 /* Bring Ethernet device up. */
 998                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
 999                         eth_dev->data->port_id);
1000                 mlx5_set_link_up(eth_dev);
1001                 /* Store device configuration on private structure. */
1002                 priv->config = config;
1003                 continue;
1004 port_error:
1005                 if (priv)
1006                         rte_free(priv);
1007                 if (pd)
1008                         claim_zero(mlx5_glue->dealloc_pd(pd));
1009                 if (ctx)
1010                         claim_zero(mlx5_glue->close_device(ctx));
1011                 break;
1012         }
1013         /*
1014          * XXX if something went wrong in the loop above, there is a resource
1015          * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as
1016          * long as the dpdk does not provide a way to deallocate a ethdev and a
1017          * way to enumerate the registered ethdevs to free the previous ones.
1018          */
1019         /* no port found, complain */
1020         if (!mlx5_dev[idx].ports) {
1021                 rte_errno = ENODEV;
1022                 err = rte_errno;
1023         }
1024 error:
1025         if (attr_ctx)
1026                 claim_zero(mlx5_glue->close_device(attr_ctx));
1027         if (list)
1028                 mlx5_glue->free_device_list(list);
1029         if (err) {
1030                 rte_errno = err;
1031                 return -rte_errno;
1032         }
1033         return 0;
1034 }
1035
1036 static const struct rte_pci_id mlx5_pci_id_map[] = {
1037         {
1038                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1039                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1040         },
1041         {
1042                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1043                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1044         },
1045         {
1046                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1047                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1048         },
1049         {
1050                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1051                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1052         },
1053         {
1054                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1055                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1056         },
1057         {
1058                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1059                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1060         },
1061         {
1062                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1063                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1064         },
1065         {
1066                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1067                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1068         },
1069         {
1070                 .vendor_id = 0
1071         }
1072 };
1073
1074 static struct rte_pci_driver mlx5_driver = {
1075         .driver = {
1076                 .name = MLX5_DRIVER_NAME
1077         },
1078         .id_table = mlx5_pci_id_map,
1079         .probe = mlx5_pci_probe,
1080         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1081 };
1082
1083 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1084
1085 /**
1086  * Suffix RTE_EAL_PMD_PATH with "-glue".
1087  *
1088  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1089  * suffixing its last component.
1090  *
1091  * @param buf[out]
1092  *   Output buffer, should be large enough otherwise NULL is returned.
1093  * @param size
1094  *   Size of @p out.
1095  *
1096  * @return
1097  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1098  */
1099 static char *
1100 mlx5_glue_path(char *buf, size_t size)
1101 {
1102         static const char *const bad[] = { "/", ".", "..", NULL };
1103         const char *path = RTE_EAL_PMD_PATH;
1104         size_t len = strlen(path);
1105         size_t off;
1106         int i;
1107
1108         while (len && path[len - 1] == '/')
1109                 --len;
1110         for (off = len; off && path[off - 1] != '/'; --off)
1111                 ;
1112         for (i = 0; bad[i]; ++i)
1113                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1114                         goto error;
1115         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1116         if (i == -1 || (size_t)i >= size)
1117                 goto error;
1118         return buf;
1119 error:
1120         DRV_LOG(ERR,
1121                 "unable to append \"-glue\" to last component of"
1122                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1123                 " please re-configure DPDK");
1124         return NULL;
1125 }
1126
1127 /**
1128  * Initialization routine for run-time dependency on rdma-core.
1129  */
1130 static int
1131 mlx5_glue_init(void)
1132 {
1133         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1134         const char *path[] = {
1135                 /*
1136                  * A basic security check is necessary before trusting
1137                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1138                  */
1139                 (geteuid() == getuid() && getegid() == getgid() ?
1140                  getenv("MLX5_GLUE_PATH") : NULL),
1141                 /*
1142                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1143                  * variant, otherwise let dlopen() look up libraries on its
1144                  * own.
1145                  */
1146                 (*RTE_EAL_PMD_PATH ?
1147                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1148         };
1149         unsigned int i = 0;
1150         void *handle = NULL;
1151         void **sym;
1152         const char *dlmsg;
1153
1154         while (!handle && i != RTE_DIM(path)) {
1155                 const char *end;
1156                 size_t len;
1157                 int ret;
1158
1159                 if (!path[i]) {
1160                         ++i;
1161                         continue;
1162                 }
1163                 end = strpbrk(path[i], ":;");
1164                 if (!end)
1165                         end = path[i] + strlen(path[i]);
1166                 len = end - path[i];
1167                 ret = 0;
1168                 do {
1169                         char name[ret + 1];
1170
1171                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1172                                        (int)len, path[i],
1173                                        (!len || *(end - 1) == '/') ? "" : "/");
1174                         if (ret == -1)
1175                                 break;
1176                         if (sizeof(name) != (size_t)ret + 1)
1177                                 continue;
1178                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1179                                 name);
1180                         handle = dlopen(name, RTLD_LAZY);
1181                         break;
1182                 } while (1);
1183                 path[i] = end + 1;
1184                 if (!*end)
1185                         ++i;
1186         }
1187         if (!handle) {
1188                 rte_errno = EINVAL;
1189                 dlmsg = dlerror();
1190                 if (dlmsg)
1191                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1192                 goto glue_error;
1193         }
1194         sym = dlsym(handle, "mlx5_glue");
1195         if (!sym || !*sym) {
1196                 rte_errno = EINVAL;
1197                 dlmsg = dlerror();
1198                 if (dlmsg)
1199                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1200                 goto glue_error;
1201         }
1202         mlx5_glue = *sym;
1203         return 0;
1204 glue_error:
1205         if (handle)
1206                 dlclose(handle);
1207         DRV_LOG(WARNING,
1208                 "cannot initialize PMD due to missing run-time dependency on"
1209                 " rdma-core libraries (libibverbs, libmlx5)");
1210         return -rte_errno;
1211 }
1212
1213 #endif
1214
1215 /**
1216  * Driver initialization routine.
1217  */
1218 RTE_INIT(rte_mlx5_pmd_init);
1219 static void
1220 rte_mlx5_pmd_init(void)
1221 {
1222         /* Build the static table for ptype conversion. */
1223         mlx5_set_ptype_table();
1224         /*
1225          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1226          * huge pages. Calling ibv_fork_init() during init allows
1227          * applications to use fork() safely for purposes other than
1228          * using this PMD, which is not supported in forked processes.
1229          */
1230         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1231         /* Match the size of Rx completion entry to the size of a cacheline. */
1232         if (RTE_CACHE_LINE_SIZE == 128)
1233                 setenv("MLX5_CQE_SIZE", "128", 0);
1234 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1235         if (mlx5_glue_init())
1236                 return;
1237         assert(mlx5_glue);
1238 #endif
1239 #ifndef NDEBUG
1240         /* Glue structure must not contain any NULL pointers. */
1241         {
1242                 unsigned int i;
1243
1244                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1245                         assert(((const void *const *)mlx5_glue)[i]);
1246         }
1247 #endif
1248         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1249                 DRV_LOG(ERR,
1250                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1251                         mlx5_glue->version, MLX5_GLUE_VERSION);
1252                 return;
1253         }
1254         mlx5_glue->fork_init();
1255         rte_pci_register(&mlx5_driver);
1256 }
1257
1258 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1259 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1260 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
1261
1262 /** Initialize driver log type. */
1263 RTE_INIT(vdev_netvsc_init_log)
1264 {
1265         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1266         if (mlx5_logtype >= 0)
1267                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1268 }