1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
37 #include <rte_rwlock.h>
38 #include <rte_spinlock.h>
39 #include <rte_string_fns.h>
42 #include "mlx5_utils.h"
43 #include "mlx5_rxtx.h"
44 #include "mlx5_autoconf.h"
45 #include "mlx5_defs.h"
46 #include "mlx5_glue.h"
49 /* Device parameter to enable RX completion queue compression. */
50 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
59 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
61 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
62 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
64 /* Device parameter to configure inline send. */
65 #define MLX5_TXQ_INLINE "txq_inline"
68 * Device parameter to configure the number of TX queues threshold for
69 * enabling inline send.
71 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
73 /* Device parameter to enable multi-packet send WQEs. */
74 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
76 /* Device parameter to include 2 dsegs in the title WQEBB. */
77 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
79 /* Device parameter to limit the size of inlining packet. */
80 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
82 /* Device parameter to enable hardware Tx vector. */
83 #define MLX5_TX_VEC_EN "tx_vec_en"
85 /* Device parameter to enable hardware Rx vector. */
86 #define MLX5_RX_VEC_EN "rx_vec_en"
88 /* Allow L3 VXLAN flow creation. */
89 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
91 /* Activate Netlink support in VF mode. */
92 #define MLX5_VF_NL_EN "vf_nl_en"
94 #ifndef HAVE_IBV_MLX5_MOD_MPW
95 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
96 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
99 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
100 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
103 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
105 /* Shared memory between primary and secondary processes. */
106 struct mlx5_shared_data *mlx5_shared_data;
108 /* Spinlock for mlx5_shared_data allocation. */
109 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
111 /** Driver-specific log messages type. */
115 * Prepare shared data between primary and secondary process.
118 mlx5_prepare_shared_data(void)
120 const struct rte_memzone *mz;
122 rte_spinlock_lock(&mlx5_shared_data_lock);
123 if (mlx5_shared_data == NULL) {
124 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
125 /* Allocate shared memory. */
126 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
127 sizeof(*mlx5_shared_data),
130 /* Lookup allocated shared memory. */
131 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
134 rte_panic("Cannot allocate mlx5 shared data\n");
135 mlx5_shared_data = mz->addr;
136 /* Initialize shared data. */
137 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
138 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
139 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
141 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
142 mlx5_mr_mem_event_cb, NULL);
144 rte_spinlock_unlock(&mlx5_shared_data_lock);
148 * Retrieve integer value from environment variable.
151 * Environment variable name.
154 * Integer value, 0 if the variable is not set.
157 mlx5_getenv_int(const char *name)
159 const char *val = getenv(name);
167 * Verbs callback to allocate a memory. This function should allocate the space
168 * according to the size provided residing inside a huge page.
169 * Please note that all allocation must respect the alignment from libmlx5
170 * (i.e. currently sysconf(_SC_PAGESIZE)).
173 * The size in bytes of the memory to allocate.
175 * A pointer to the callback data.
178 * Allocated buffer, NULL otherwise and rte_errno is set.
181 mlx5_alloc_verbs_buf(size_t size, void *data)
183 struct priv *priv = data;
185 size_t alignment = sysconf(_SC_PAGESIZE);
186 unsigned int socket = SOCKET_ID_ANY;
188 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
189 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
191 socket = ctrl->socket;
192 } else if (priv->verbs_alloc_ctx.type ==
193 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
194 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
196 socket = ctrl->socket;
198 assert(data != NULL);
199 ret = rte_malloc_socket(__func__, size, alignment, socket);
206 * Verbs callback to free a memory.
209 * A pointer to the memory to free.
211 * A pointer to the callback data.
214 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
216 assert(data != NULL);
221 * DPDK callback to close the device.
223 * Destroy all queues and objects, free memory.
226 * Pointer to Ethernet device structure.
229 mlx5_dev_close(struct rte_eth_dev *dev)
231 struct priv *priv = dev->data->dev_private;
235 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
237 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
238 /* In case mlx5_dev_stop() has not been called. */
239 mlx5_dev_interrupt_handler_uninstall(dev);
240 mlx5_traffic_disable(dev);
241 /* Prevent crashes when queues are still in use. */
242 dev->rx_pkt_burst = removed_rx_burst;
243 dev->tx_pkt_burst = removed_tx_burst;
244 if (priv->rxqs != NULL) {
245 /* XXX race condition if mlx5_rx_burst() is still running. */
247 for (i = 0; (i != priv->rxqs_n); ++i)
248 mlx5_rxq_release(dev, i);
252 if (priv->txqs != NULL) {
253 /* XXX race condition if mlx5_tx_burst() is still running. */
255 for (i = 0; (i != priv->txqs_n); ++i)
256 mlx5_txq_release(dev, i);
260 mlx5_flow_delete_drop_queue(dev);
261 mlx5_mprq_free_mp(dev);
262 mlx5_mr_release(dev);
263 if (priv->pd != NULL) {
264 assert(priv->ctx != NULL);
265 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
266 claim_zero(mlx5_glue->close_device(priv->ctx));
268 assert(priv->ctx == NULL);
269 if (priv->rss_conf.rss_key != NULL)
270 rte_free(priv->rss_conf.rss_key);
271 if (priv->reta_idx != NULL)
272 rte_free(priv->reta_idx);
273 if (priv->primary_socket)
274 mlx5_socket_uninit(dev);
276 mlx5_nl_mac_addr_flush(dev);
277 if (priv->nl_socket >= 0)
278 close(priv->nl_socket);
279 ret = mlx5_hrxq_ibv_verify(dev);
281 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
283 ret = mlx5_ind_table_ibv_verify(dev);
285 DRV_LOG(WARNING, "port %u some indirection table still remain",
287 ret = mlx5_rxq_ibv_verify(dev);
289 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
291 ret = mlx5_rxq_verify(dev);
293 DRV_LOG(WARNING, "port %u some Rx queues still remain",
295 ret = mlx5_txq_ibv_verify(dev);
297 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
299 ret = mlx5_txq_verify(dev);
301 DRV_LOG(WARNING, "port %u some Tx queues still remain",
303 ret = mlx5_flow_verify(dev);
305 DRV_LOG(WARNING, "port %u some flows still remain",
307 memset(priv, 0, sizeof(*priv));
310 const struct eth_dev_ops mlx5_dev_ops = {
311 .dev_configure = mlx5_dev_configure,
312 .dev_start = mlx5_dev_start,
313 .dev_stop = mlx5_dev_stop,
314 .dev_set_link_down = mlx5_set_link_down,
315 .dev_set_link_up = mlx5_set_link_up,
316 .dev_close = mlx5_dev_close,
317 .promiscuous_enable = mlx5_promiscuous_enable,
318 .promiscuous_disable = mlx5_promiscuous_disable,
319 .allmulticast_enable = mlx5_allmulticast_enable,
320 .allmulticast_disable = mlx5_allmulticast_disable,
321 .link_update = mlx5_link_update,
322 .stats_get = mlx5_stats_get,
323 .stats_reset = mlx5_stats_reset,
324 .xstats_get = mlx5_xstats_get,
325 .xstats_reset = mlx5_xstats_reset,
326 .xstats_get_names = mlx5_xstats_get_names,
327 .dev_infos_get = mlx5_dev_infos_get,
328 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
329 .vlan_filter_set = mlx5_vlan_filter_set,
330 .rx_queue_setup = mlx5_rx_queue_setup,
331 .tx_queue_setup = mlx5_tx_queue_setup,
332 .rx_queue_release = mlx5_rx_queue_release,
333 .tx_queue_release = mlx5_tx_queue_release,
334 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
335 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
336 .mac_addr_remove = mlx5_mac_addr_remove,
337 .mac_addr_add = mlx5_mac_addr_add,
338 .mac_addr_set = mlx5_mac_addr_set,
339 .set_mc_addr_list = mlx5_set_mc_addr_list,
340 .mtu_set = mlx5_dev_set_mtu,
341 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
342 .vlan_offload_set = mlx5_vlan_offload_set,
343 .reta_update = mlx5_dev_rss_reta_update,
344 .reta_query = mlx5_dev_rss_reta_query,
345 .rss_hash_update = mlx5_rss_hash_update,
346 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
347 .filter_ctrl = mlx5_dev_filter_ctrl,
348 .rx_descriptor_status = mlx5_rx_descriptor_status,
349 .tx_descriptor_status = mlx5_tx_descriptor_status,
350 .rx_queue_intr_enable = mlx5_rx_intr_enable,
351 .rx_queue_intr_disable = mlx5_rx_intr_disable,
352 .is_removed = mlx5_is_removed,
355 static const struct eth_dev_ops mlx5_dev_sec_ops = {
356 .stats_get = mlx5_stats_get,
357 .stats_reset = mlx5_stats_reset,
358 .xstats_get = mlx5_xstats_get,
359 .xstats_reset = mlx5_xstats_reset,
360 .xstats_get_names = mlx5_xstats_get_names,
361 .dev_infos_get = mlx5_dev_infos_get,
362 .rx_descriptor_status = mlx5_rx_descriptor_status,
363 .tx_descriptor_status = mlx5_tx_descriptor_status,
366 /* Available operators in flow isolated mode. */
367 const struct eth_dev_ops mlx5_dev_ops_isolate = {
368 .dev_configure = mlx5_dev_configure,
369 .dev_start = mlx5_dev_start,
370 .dev_stop = mlx5_dev_stop,
371 .dev_set_link_down = mlx5_set_link_down,
372 .dev_set_link_up = mlx5_set_link_up,
373 .dev_close = mlx5_dev_close,
374 .link_update = mlx5_link_update,
375 .stats_get = mlx5_stats_get,
376 .stats_reset = mlx5_stats_reset,
377 .xstats_get = mlx5_xstats_get,
378 .xstats_reset = mlx5_xstats_reset,
379 .xstats_get_names = mlx5_xstats_get_names,
380 .dev_infos_get = mlx5_dev_infos_get,
381 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
382 .vlan_filter_set = mlx5_vlan_filter_set,
383 .rx_queue_setup = mlx5_rx_queue_setup,
384 .tx_queue_setup = mlx5_tx_queue_setup,
385 .rx_queue_release = mlx5_rx_queue_release,
386 .tx_queue_release = mlx5_tx_queue_release,
387 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
388 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
389 .mac_addr_remove = mlx5_mac_addr_remove,
390 .mac_addr_add = mlx5_mac_addr_add,
391 .mac_addr_set = mlx5_mac_addr_set,
392 .set_mc_addr_list = mlx5_set_mc_addr_list,
393 .mtu_set = mlx5_dev_set_mtu,
394 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
395 .vlan_offload_set = mlx5_vlan_offload_set,
396 .filter_ctrl = mlx5_dev_filter_ctrl,
397 .rx_descriptor_status = mlx5_rx_descriptor_status,
398 .tx_descriptor_status = mlx5_tx_descriptor_status,
399 .rx_queue_intr_enable = mlx5_rx_intr_enable,
400 .rx_queue_intr_disable = mlx5_rx_intr_disable,
401 .is_removed = mlx5_is_removed,
405 * Verify and store value for device argument.
408 * Key argument to verify.
410 * Value associated with key.
415 * 0 on success, a negative errno value otherwise and rte_errno is set.
418 mlx5_args_check(const char *key, const char *val, void *opaque)
420 struct mlx5_dev_config *config = opaque;
424 tmp = strtoul(val, NULL, 0);
427 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
430 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
431 config->cqe_comp = !!tmp;
432 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
433 config->mprq.enabled = !!tmp;
434 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
435 config->mprq.stride_num_n = tmp;
436 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
437 config->mprq.max_memcpy_len = tmp;
438 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
439 config->mprq.min_rxqs_num = tmp;
440 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
441 config->txq_inline = tmp;
442 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
443 config->txqs_inline = tmp;
444 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
445 config->mps = !!tmp ? config->mps : 0;
446 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
447 config->mpw_hdr_dseg = !!tmp;
448 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
449 config->inline_max_packet_sz = tmp;
450 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
451 config->tx_vec_en = !!tmp;
452 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
453 config->rx_vec_en = !!tmp;
454 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
455 config->l3_vxlan_en = !!tmp;
456 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
457 config->vf_nl_en = !!tmp;
459 DRV_LOG(WARNING, "%s: unknown parameter", key);
467 * Parse device parameters.
470 * Pointer to device configuration structure.
472 * Device arguments structure.
475 * 0 on success, a negative errno value otherwise and rte_errno is set.
478 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
480 const char **params = (const char *[]){
481 MLX5_RXQ_CQE_COMP_EN,
483 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
484 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
487 MLX5_TXQS_MIN_INLINE,
489 MLX5_TXQ_MPW_HDR_DSEG_EN,
490 MLX5_TXQ_MAX_INLINE_LEN,
497 struct rte_kvargs *kvlist;
503 /* Following UGLY cast is done to pass checkpatch. */
504 kvlist = rte_kvargs_parse(devargs->args, params);
507 /* Process parameters. */
508 for (i = 0; (params[i] != NULL); ++i) {
509 if (rte_kvargs_count(kvlist, params[i])) {
510 ret = rte_kvargs_process(kvlist, params[i],
511 mlx5_args_check, config);
514 rte_kvargs_free(kvlist);
519 rte_kvargs_free(kvlist);
523 static struct rte_pci_driver mlx5_driver;
526 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
527 * local resource used by both primary and secondary to avoid duplicate
529 * The space has to be available on both primary and secondary process,
530 * TXQ UAR maps to this area using fixed mmap w/o double check.
532 static void *uar_base;
535 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
536 const struct rte_memseg *ms, void *arg)
543 *addr = RTE_MIN(*addr, ms->addr);
549 * Reserve UAR address space for primary process.
552 * Pointer to Ethernet device.
555 * 0 on success, a negative errno value otherwise and rte_errno is set.
558 mlx5_uar_init_primary(struct rte_eth_dev *dev)
560 struct priv *priv = dev->data->dev_private;
561 void *addr = (void *)0;
563 if (uar_base) { /* UAR address space mapped. */
564 priv->uar_base = uar_base;
567 /* find out lower bound of hugepage segments */
568 rte_memseg_walk(find_lower_va_bound, &addr);
570 /* keep distance to hugepages to minimize potential conflicts. */
571 addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
572 /* anonymous mmap, no real memory consumption. */
573 addr = mmap(addr, MLX5_UAR_SIZE,
574 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
575 if (addr == MAP_FAILED) {
577 "port %u failed to reserve UAR address space, please"
578 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
583 /* Accept either same addr or a new addr returned from mmap if target
586 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
587 dev->data->port_id, addr);
588 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
589 uar_base = addr; /* process local, don't reserve again. */
594 * Reserve UAR address space for secondary process, align with
598 * Pointer to Ethernet device.
601 * 0 on success, a negative errno value otherwise and rte_errno is set.
604 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
606 struct priv *priv = dev->data->dev_private;
609 assert(priv->uar_base);
610 if (uar_base) { /* already reserved. */
611 assert(uar_base == priv->uar_base);
614 /* anonymous mmap, no real memory consumption. */
615 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
616 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
617 if (addr == MAP_FAILED) {
618 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
619 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
623 if (priv->uar_base != addr) {
625 "port %u UAR address %p size %llu occupied, please"
626 " adjust MLX5_UAR_OFFSET or try EAL parameter"
628 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
632 uar_base = addr; /* process local, don't reserve again */
633 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
634 dev->data->port_id, addr);
639 * Spawn an Ethernet device from Verbs information.
642 * Backing DPDK device.
646 * If nonzero, enable VF-specific features.
649 * A valid Ethernet device object on success, NULL otherwise and rte_errno
652 static struct rte_eth_dev *
653 mlx5_dev_spawn(struct rte_device *dpdk_dev,
654 struct ibv_device *ibv_dev,
657 struct ibv_context *ctx;
658 struct ibv_device_attr_ex attr;
659 struct ibv_port_attr port_attr;
660 struct ibv_pd *pd = NULL;
661 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
662 struct mlx5_dev_config config = {
667 .txq_inline = MLX5_ARG_UNSET,
668 .txqs_inline = MLX5_ARG_UNSET,
669 .inline_max_packet_sz = MLX5_ARG_UNSET,
673 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
674 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
675 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
678 struct rte_eth_dev *eth_dev = NULL;
679 struct priv *priv = NULL;
682 unsigned int cqe_comp;
683 unsigned int tunnel_en = 0;
684 unsigned int mpls_en = 0;
685 unsigned int swp = 0;
686 unsigned int verb_priorities = 0;
687 unsigned int mprq = 0;
688 unsigned int mprq_min_stride_size_n = 0;
689 unsigned int mprq_max_stride_size_n = 0;
690 unsigned int mprq_min_stride_num_n = 0;
691 unsigned int mprq_max_stride_num_n = 0;
692 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
693 struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
695 struct ether_addr mac;
696 char name[RTE_ETH_NAME_MAX_LEN];
698 /* Prepare shared data between primary and secondary process. */
699 mlx5_prepare_shared_data();
701 ctx = mlx5_glue->open_device(ibv_dev);
703 rte_errno = errno ? errno : ENODEV;
706 #ifdef HAVE_IBV_MLX5_MOD_SWP
707 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
710 * Multi-packet send is supported by ConnectX-4 Lx PF as well
711 * as all ConnectX-5 devices.
713 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
714 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
716 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
717 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
719 mlx5_glue->dv_query_device(ctx, &dv_attr);
720 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
721 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
722 DRV_LOG(DEBUG, "enhanced MPW is supported");
723 mps = MLX5_MPW_ENHANCED;
725 DRV_LOG(DEBUG, "MPW is supported");
729 DRV_LOG(DEBUG, "MPW isn't supported");
730 mps = MLX5_MPW_DISABLED;
733 #ifdef HAVE_IBV_MLX5_MOD_SWP
734 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
735 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
736 DRV_LOG(DEBUG, "SWP support: %u", swp);
739 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
740 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
741 struct mlx5dv_striding_rq_caps mprq_caps =
742 dv_attr.striding_rq_caps;
744 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
745 mprq_caps.min_single_stride_log_num_of_bytes);
746 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
747 mprq_caps.max_single_stride_log_num_of_bytes);
748 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
749 mprq_caps.min_single_wqe_log_num_of_strides);
750 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
751 mprq_caps.max_single_wqe_log_num_of_strides);
752 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
753 mprq_caps.supported_qpts);
754 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
756 mprq_min_stride_size_n =
757 mprq_caps.min_single_stride_log_num_of_bytes;
758 mprq_max_stride_size_n =
759 mprq_caps.max_single_stride_log_num_of_bytes;
760 mprq_min_stride_num_n =
761 mprq_caps.min_single_wqe_log_num_of_strides;
762 mprq_max_stride_num_n =
763 mprq_caps.max_single_wqe_log_num_of_strides;
764 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
765 mprq_min_stride_num_n);
768 if (RTE_CACHE_LINE_SIZE == 128 &&
769 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
773 config.cqe_comp = cqe_comp;
774 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
775 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
776 tunnel_en = ((dv_attr.tunnel_offloads_caps &
777 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
778 (dv_attr.tunnel_offloads_caps &
779 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
781 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
782 tunnel_en ? "" : "not ");
785 "tunnel offloading disabled due to old OFED/rdma-core version");
787 config.tunnel_en = tunnel_en;
788 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
789 mpls_en = ((dv_attr.tunnel_offloads_caps &
790 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
791 (dv_attr.tunnel_offloads_caps &
792 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
793 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
794 mpls_en ? "" : "not ");
796 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
797 " old OFED/rdma-core version or firmware configuration");
799 config.mpls_en = mpls_en;
800 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
802 DEBUG("ibv_query_device_ex() failed");
805 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
806 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
807 eth_dev = rte_eth_dev_attach_secondary(name);
808 if (eth_dev == NULL) {
809 DRV_LOG(ERR, "can not attach rte ethdev");
814 eth_dev->device = dpdk_dev;
815 eth_dev->dev_ops = &mlx5_dev_sec_ops;
816 err = mlx5_uar_init_secondary(eth_dev);
821 /* Receive command fd from primary process */
822 err = mlx5_socket_connect(eth_dev);
827 /* Remap UAR for Tx queues. */
828 err = mlx5_tx_uar_remap(eth_dev, err);
834 * Ethdev pointer is still required as input since
835 * the primary device is not accessible from the
838 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
839 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
840 claim_zero(mlx5_glue->close_device(ctx));
843 /* Check port status. */
844 err = mlx5_glue->query_port(ctx, 1, &port_attr);
846 DRV_LOG(ERR, "port query failed: %s", strerror(err));
849 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
850 DRV_LOG(ERR, "port is not configured in Ethernet mode");
854 if (port_attr.state != IBV_PORT_ACTIVE)
855 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
856 mlx5_glue->port_state_str(port_attr.state),
858 /* Allocate protection domain. */
859 pd = mlx5_glue->alloc_pd(ctx);
861 DRV_LOG(ERR, "PD allocation failure");
865 priv = rte_zmalloc("ethdev private structure",
867 RTE_CACHE_LINE_SIZE);
869 DRV_LOG(ERR, "priv allocation failure");
874 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
875 sizeof(priv->ibdev_path));
876 priv->device_attr = attr;
878 priv->mtu = ETHER_MTU;
879 err = mlx5_args(&config, dpdk_dev->devargs);
882 DRV_LOG(ERR, "failed to process device arguments: %s",
883 strerror(rte_errno));
886 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
887 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
888 (config.hw_csum ? "" : "not "));
889 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
890 config.flow_counter_en = !!attr.max_counter_sets;
891 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
892 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d",
893 cs_desc.counter_type, cs_desc.num_of_cs,
896 config.ind_table_max_size =
897 attr.rss_caps.max_rwq_indirection_table_size;
899 * Remove this check once DPDK supports larger/variable
900 * indirection tables.
902 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
903 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
904 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
905 config.ind_table_max_size);
906 config.hw_vlan_strip = !!(attr.raw_packet_caps &
907 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
908 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
909 (config.hw_vlan_strip ? "" : "not "));
910 config.hw_fcs_strip = !!(attr.raw_packet_caps &
911 IBV_RAW_PACKET_CAP_SCATTER_FCS);
912 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
913 (config.hw_fcs_strip ? "" : "not "));
914 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
915 config.hw_padding = !!attr.rx_pad_end_addr_align;
917 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
918 (config.hw_padding ? "" : "not "));
919 config.tso = (attr.tso_caps.max_tso > 0 &&
920 (attr.tso_caps.supported_qpts &
921 (1 << IBV_QPT_RAW_PACKET)));
923 config.tso_max_payload_sz = attr.tso_caps.max_tso;
924 if (config.mps && !mps) {
926 "multi-packet send not supported on this device"
927 " (" MLX5_TXQ_MPW_EN ")");
931 DRV_LOG(INFO, "%sMPS is %s",
932 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
933 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
934 if (config.cqe_comp && !cqe_comp) {
935 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
938 if (config.mprq.enabled && mprq) {
939 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
940 config.mprq.stride_num_n < mprq_min_stride_num_n) {
941 config.mprq.stride_num_n =
942 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
943 mprq_min_stride_num_n);
945 "the number of strides"
946 " for Multi-Packet RQ is out of range,"
947 " setting default value (%u)",
948 1 << config.mprq.stride_num_n);
950 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
951 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
952 } else if (config.mprq.enabled && !mprq) {
953 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
954 config.mprq.enabled = 0;
956 eth_dev = rte_eth_dev_allocate(name);
957 if (eth_dev == NULL) {
958 DRV_LOG(ERR, "can not allocate rte ethdev");
962 eth_dev->data->dev_private = priv;
963 priv->dev_data = eth_dev->data;
964 eth_dev->data->mac_addrs = priv->mac;
965 eth_dev->device = dpdk_dev;
966 eth_dev->device->driver = &mlx5_driver.driver;
967 err = mlx5_uar_init_primary(eth_dev);
972 /* Configure the first MAC address by default. */
973 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
975 "port %u cannot get MAC address, is mlx5_en"
976 " loaded? (errno: %s)",
977 eth_dev->data->port_id, strerror(rte_errno));
982 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
983 eth_dev->data->port_id,
984 mac.addr_bytes[0], mac.addr_bytes[1],
985 mac.addr_bytes[2], mac.addr_bytes[3],
986 mac.addr_bytes[4], mac.addr_bytes[5]);
989 char ifname[IF_NAMESIZE];
991 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
992 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
993 eth_dev->data->port_id, ifname);
995 DRV_LOG(DEBUG, "port %u ifname is unknown",
996 eth_dev->data->port_id);
999 /* Get actual MTU if possible. */
1000 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1005 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1007 /* Initialize burst functions to prevent crashes before link-up. */
1008 eth_dev->rx_pkt_burst = removed_rx_burst;
1009 eth_dev->tx_pkt_burst = removed_tx_burst;
1010 eth_dev->dev_ops = &mlx5_dev_ops;
1011 /* Register MAC address. */
1012 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1013 priv->nl_socket = -1;
1015 if (vf && config.vf_nl_en) {
1016 priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1017 if (priv->nl_socket < 0)
1018 priv->nl_socket = -1;
1019 mlx5_nl_mac_addr_sync(eth_dev);
1021 TAILQ_INIT(&priv->flows);
1022 TAILQ_INIT(&priv->ctrl_flows);
1023 /* Hint libmlx5 to use PMD allocator for data plane resources */
1024 struct mlx5dv_ctx_allocators alctr = {
1025 .alloc = &mlx5_alloc_verbs_buf,
1026 .free = &mlx5_free_verbs_buf,
1029 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1030 (void *)((uintptr_t)&alctr));
1031 /* Bring Ethernet device up. */
1032 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1033 eth_dev->data->port_id);
1034 mlx5_set_link_up(eth_dev);
1036 * Even though the interrupt handler is not installed yet,
1037 * interrupts will still trigger on the asyn_fd from
1038 * Verbs context returned by ibv_open_device().
1040 mlx5_link_update(eth_dev, 0);
1041 /* Store device configuration on private structure. */
1042 priv->config = config;
1043 /* Create drop queue. */
1044 err = mlx5_flow_create_drop_queue(eth_dev);
1046 DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1047 eth_dev->data->port_id, strerror(rte_errno));
1051 /* Supported Verbs flow priority number detection. */
1052 if (verb_priorities == 0)
1053 verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1054 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1055 DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1056 eth_dev->data->port_id, verb_priorities);
1060 priv->config.max_verbs_prio = verb_priorities;
1062 * Once the device is added to the list of memory event
1063 * callback, its global MR cache table cannot be expanded
1064 * on the fly because of deadlock. If it overflows, lookup
1065 * should be done by searching MR list linearly, which is slow.
1067 err = mlx5_mr_btree_init(&priv->mr.cache,
1068 MLX5_MR_BTREE_CACHE_N * 2,
1069 eth_dev->device->numa_node);
1074 /* Add device to memory callback list. */
1075 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1076 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1077 priv, mem_event_cb);
1078 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1084 claim_zero(mlx5_glue->dealloc_pd(pd));
1086 rte_eth_dev_release_port(eth_dev);
1088 claim_zero(mlx5_glue->close_device(ctx));
1095 * DPDK callback to register a PCI device.
1097 * This function spawns an Ethernet device out of a given PCI device.
1099 * @param[in] pci_drv
1100 * PCI driver structure (mlx5_driver).
1101 * @param[in] pci_dev
1102 * PCI device information.
1105 * 0 on success, a negative errno value otherwise and rte_errno is set.
1108 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1109 struct rte_pci_device *pci_dev)
1111 struct ibv_device **ibv_list;
1112 struct rte_eth_dev *eth_dev = NULL;
1116 assert(pci_drv == &mlx5_driver);
1118 ibv_list = mlx5_glue->get_device_list(&ret);
1120 rte_errno = errno ? errno : ENOSYS;
1121 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1125 struct rte_pci_addr pci_addr;
1127 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1128 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1130 if (pci_dev->addr.domain != pci_addr.domain ||
1131 pci_dev->addr.bus != pci_addr.bus ||
1132 pci_dev->addr.devid != pci_addr.devid ||
1133 pci_dev->addr.function != pci_addr.function)
1135 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
1136 ibv_list[ret]->name);
1139 switch (pci_dev->id.device_id) {
1140 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1141 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1142 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1143 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1150 eth_dev = mlx5_dev_spawn(&pci_dev->device, ibv_list[ret], vf);
1151 mlx5_glue->free_device_list(ibv_list);
1154 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1155 " are kernel drivers loaded?",
1156 pci_dev->addr.domain, pci_dev->addr.bus,
1157 pci_dev->addr.devid, pci_dev->addr.function);
1160 } else if (!eth_dev) {
1162 "probe of PCI device " PCI_PRI_FMT " aborted after"
1163 " encountering an error: %s",
1164 pci_dev->addr.domain, pci_dev->addr.bus,
1165 pci_dev->addr.devid, pci_dev->addr.function,
1166 strerror(rte_errno));
1169 rte_eth_copy_pci_info(eth_dev, pci_dev);
1170 rte_eth_dev_probing_finish(eth_dev);
1176 static const struct rte_pci_id mlx5_pci_id_map[] = {
1178 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1179 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1182 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1183 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1186 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1187 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1190 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1191 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1194 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1195 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1198 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1199 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1202 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1203 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1206 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1207 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1210 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1211 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1218 static struct rte_pci_driver mlx5_driver = {
1220 .name = MLX5_DRIVER_NAME
1222 .id_table = mlx5_pci_id_map,
1223 .probe = mlx5_pci_probe,
1224 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1227 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1230 * Suffix RTE_EAL_PMD_PATH with "-glue".
1232 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1233 * suffixing its last component.
1236 * Output buffer, should be large enough otherwise NULL is returned.
1241 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1244 mlx5_glue_path(char *buf, size_t size)
1246 static const char *const bad[] = { "/", ".", "..", NULL };
1247 const char *path = RTE_EAL_PMD_PATH;
1248 size_t len = strlen(path);
1252 while (len && path[len - 1] == '/')
1254 for (off = len; off && path[off - 1] != '/'; --off)
1256 for (i = 0; bad[i]; ++i)
1257 if (!strncmp(path + off, bad[i], (int)(len - off)))
1259 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1260 if (i == -1 || (size_t)i >= size)
1265 "unable to append \"-glue\" to last component of"
1266 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1267 " please re-configure DPDK");
1272 * Initialization routine for run-time dependency on rdma-core.
1275 mlx5_glue_init(void)
1277 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1278 const char *path[] = {
1280 * A basic security check is necessary before trusting
1281 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1283 (geteuid() == getuid() && getegid() == getgid() ?
1284 getenv("MLX5_GLUE_PATH") : NULL),
1286 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1287 * variant, otherwise let dlopen() look up libraries on its
1290 (*RTE_EAL_PMD_PATH ?
1291 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1294 void *handle = NULL;
1298 while (!handle && i != RTE_DIM(path)) {
1307 end = strpbrk(path[i], ":;");
1309 end = path[i] + strlen(path[i]);
1310 len = end - path[i];
1315 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1317 (!len || *(end - 1) == '/') ? "" : "/");
1320 if (sizeof(name) != (size_t)ret + 1)
1322 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1324 handle = dlopen(name, RTLD_LAZY);
1335 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1338 sym = dlsym(handle, "mlx5_glue");
1339 if (!sym || !*sym) {
1343 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1352 "cannot initialize PMD due to missing run-time dependency on"
1353 " rdma-core libraries (libibverbs, libmlx5)");
1360 * Driver initialization routine.
1362 RTE_INIT(rte_mlx5_pmd_init)
1364 /* Initialize driver log type. */
1365 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1366 if (mlx5_logtype >= 0)
1367 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1369 /* Build the static tables for Verbs conversion. */
1370 mlx5_set_ptype_table();
1371 mlx5_set_cksum_table();
1372 mlx5_set_swp_types_table();
1374 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1375 * huge pages. Calling ibv_fork_init() during init allows
1376 * applications to use fork() safely for purposes other than
1377 * using this PMD, which is not supported in forked processes.
1379 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1380 /* Match the size of Rx completion entry to the size of a cacheline. */
1381 if (RTE_CACHE_LINE_SIZE == 128)
1382 setenv("MLX5_CQE_SIZE", "128", 0);
1384 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1385 * cleanup all the Verbs resources even when the device was removed.
1387 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1388 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1389 if (mlx5_glue_init())
1394 /* Glue structure must not contain any NULL pointers. */
1398 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1399 assert(((const void *const *)mlx5_glue)[i]);
1402 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1404 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1405 mlx5_glue->version, MLX5_GLUE_VERSION);
1408 mlx5_glue->fork_init();
1409 rte_pci_register(&mlx5_driver);
1412 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1413 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1414 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");