drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_rwlock.h>
  38 #include <rte_spinlock.h>
  39 #include <rte_string_fns.h>
  40
  41 #include "mlx5.h"
  42 #include "mlx5_utils.h"
  43 #include "mlx5_rxtx.h"
  44 #include "mlx5_autoconf.h"
  45 #include "mlx5_defs.h"
  46 #include "mlx5_glue.h"
  47 #include "mlx5_mr.h"
  48 #include "mlx5_flow.h"
  49
  50 /* Device parameter to enable RX completion queue compression. */
  51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  52
  53 /* Device parameter to enable RX completion entry padding to 128B. */
  54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  55
  56 /* Device parameter to enable padding Rx packet to cacheline size. */
  57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  58
  59 /* Device parameter to enable Multi-Packet Rx queue. */
  60 #define MLX5_RX_MPRQ_EN "mprq_en"
  61
  62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  64
  65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  67
  68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  70
  71 /* Device parameter to configure inline send. */
  72 #define MLX5_TXQ_INLINE "txq_inline"
  73
  74 /*
  75  * Device parameter to configure the number of TX queues threshold for
  76  * enabling inline send.
  77  */
  78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  79
  80 /*
  81  * Device parameter to configure the number of TX queues threshold for
  82  * enabling vectorized Tx.
  83  */
  84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  85
  86 /* Device parameter to enable multi-packet send WQEs. */
  87 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  88
  89 /* Device parameter to include 2 dsegs in the title WQEBB. */
  90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  91
  92 /* Device parameter to limit the size of inlining packet. */
  93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  94
  95 /* Device parameter to enable hardware Tx vector. */
  96 #define MLX5_TX_VEC_EN "tx_vec_en"
  97
  98 /* Device parameter to enable hardware Rx vector. */
  99 #define MLX5_RX_VEC_EN "rx_vec_en"
 100
 101 /* Allow L3 VXLAN flow creation. */
 102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 103
 104 /* Activate DV flow steering. */
 105 #define MLX5_DV_FLOW_EN "dv_flow_en"
 106
 107 /* Activate Netlink support in VF mode. */
 108 #define MLX5_VF_NL_EN "vf_nl_en"
 109
 110 /* Enable extending memsegs when creating a MR. */
 111 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 112
 113 /* Select port representors to instantiate. */
 114 #define MLX5_REPRESENTOR "representor"
 115
 116 #ifndef HAVE_IBV_MLX5_MOD_MPW
 117 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 118 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 119 #endif
 120
 121 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 122 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 123 #endif
 124
 125 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 126
 127 /* Shared memory between primary and secondary processes. */
 128 struct mlx5_shared_data *mlx5_shared_data;
 129
 130 /* Spinlock for mlx5_shared_data allocation. */
 131 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 132
 133 /* Process local data for secondary processes. */
 134 static struct mlx5_local_data mlx5_local_data;
 135
 136 /** Driver-specific log messages type. */
 137 int mlx5_logtype;
 138
 139 /** Data associated with devices to spawn. */
 140 struct mlx5_dev_spawn_data {
 141         uint32_t ifindex; /**< Network interface index. */
 142         uint32_t max_port; /**< IB device maximal port index. */
 143         uint32_t ibv_port; /**< IB device physical port index. */
 144         struct mlx5_switch_info info; /**< Switch information. */
 145         struct ibv_device *ibv_dev; /**< Associated IB device. */
 146         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 147 };
 148
 149 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 150 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 151
 152 /**
 153  * Allocate shared IB device context. If there is multiport device the
 154  * master and representors will share this context, if there is single
 155  * port dedicated IB device, the context will be used by only given
 156  * port due to unification.
 157  *
 158  * Routine first searches the context for the spesified IB device name,
 159  * if found the shared context assumed and reference counter is incremented.
 160  * If no context found the new one is created and initialized with specified
 161  * IB device context and parameters.
 162  *
 163  * @param[in] spawn
 164  *   Pointer to the IB device attributes (name, port, etc).
 165  *
 166  * @return
 167  *   Pointer to mlx5_ibv_shared object on success,
 168  *   otherwise NULL and rte_errno is set.
 169  */
 170 static struct mlx5_ibv_shared *
 171 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn)
 172 {
 173         struct mlx5_ibv_shared *sh;
 174         int err = 0;
 175         uint32_t i;
 176
 177         assert(spawn);
 178         /* Secondary process should not create the shared context. */
 179         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 180         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 181         /* Search for IB context by device name. */
 182         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 183                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 184                         sh->refcnt++;
 185                         goto exit;
 186                 }
 187         }
 188         /* No device found, we have to create new sharted context. */
 189         assert(spawn->max_port);
 190         sh = rte_zmalloc("ethdev shared ib context",
 191                          sizeof(struct mlx5_ibv_shared) +
 192                          spawn->max_port *
 193                          sizeof(struct mlx5_ibv_shared_port),
 194                          RTE_CACHE_LINE_SIZE);
 195         if (!sh) {
 196                 DRV_LOG(ERR, "shared context allocation failure");
 197                 rte_errno  = ENOMEM;
 198                 goto exit;
 199         }
 200         /* Try to open IB device with DV first, then usual Verbs. */
 201         errno = 0;
 202         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 203         if (sh->ctx) {
 204                 sh->devx = 1;
 205                 DRV_LOG(DEBUG, "DevX is supported");
 206         } else {
 207                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 208                 if (!sh->ctx) {
 209                         err = errno ? errno : ENODEV;
 210                         goto error;
 211                 }
 212                 DRV_LOG(DEBUG, "DevX is NOT supported");
 213         }
 214         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 215         if (err) {
 216                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 217                 goto error;
 218         }
 219         sh->refcnt = 1;
 220         sh->max_port = spawn->max_port;
 221         strncpy(sh->ibdev_name, sh->ctx->device->name,
 222                 sizeof(sh->ibdev_name));
 223         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 224                 sizeof(sh->ibdev_path));
 225         pthread_mutex_init(&sh->intr_mutex, NULL);
 226         /*
 227          * Setting port_id to max unallowed value means
 228          * there is no interrupt subhandler installed for
 229          * the given port index i.
 230          */
 231         for (i = 0; i < sh->max_port; i++)
 232                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 233         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 234         if (sh->pd == NULL) {
 235                 DRV_LOG(ERR, "PD allocation failure");
 236                 err = ENOMEM;
 237                 goto error;
 238         }
 239         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 240 exit:
 241         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 242         return sh;
 243 error:
 244         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 245         assert(sh);
 246         if (sh->pd)
 247                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 248         if (sh->ctx)
 249                 claim_zero(mlx5_glue->close_device(sh->ctx));
 250         rte_free(sh);
 251         assert(err > 0);
 252         rte_errno = err;
 253         return NULL;
 254 }
 255
 256 /**
 257  * Free shared IB device context. Decrement counter and if zero free
 258  * all allocated resources and close handles.
 259  *
 260  * @param[in] sh
 261  *   Pointer to mlx5_ibv_shared object to free
 262  */
 263 static void
 264 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 265 {
 266         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 267 #ifndef NDEBUG
 268         /* Check the object presence in the list. */
 269         struct mlx5_ibv_shared *lctx;
 270
 271         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 272                 if (lctx == sh)
 273                         break;
 274         assert(lctx);
 275         if (lctx != sh) {
 276                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 277                 goto exit;
 278         }
 279 #endif
 280         assert(sh);
 281         assert(sh->refcnt);
 282         /* Secondary process should not free the shared context. */
 283         assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
 284         if (--sh->refcnt)
 285                 goto exit;
 286         LIST_REMOVE(sh, next);
 287         /*
 288          *  Ensure there is no async event handler installed.
 289          *  Only primary process handles async device events.
 290          **/
 291         assert(!sh->intr_cnt);
 292         if (sh->intr_cnt)
 293                 rte_intr_callback_unregister
 294                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 295         pthread_mutex_destroy(&sh->intr_mutex);
 296         if (sh->pd)
 297                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 298         if (sh->ctx)
 299                 claim_zero(mlx5_glue->close_device(sh->ctx));
 300         rte_free(sh);
 301 exit:
 302         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 303 }
 304
 305 /**
 306  * Initialize shared data between primary and secondary process.
 307  *
 308  * A memzone is reserved by primary process and secondary processes attach to
 309  * the memzone.
 310  *
 311  * @return
 312  *   0 on success, a negative errno value otherwise and rte_errno is set.
 313  */
 314 static int
 315 mlx5_init_shared_data(void)
 316 {
 317         const struct rte_memzone *mz;
 318         int ret = 0;
 319
 320         rte_spinlock_lock(&mlx5_shared_data_lock);
 321         if (mlx5_shared_data == NULL) {
 322                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 323                         /* Allocate shared memory. */
 324                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 325                                                  sizeof(*mlx5_shared_data),
 326                                                  SOCKET_ID_ANY, 0);
 327                         if (mz == NULL) {
 328                                 DRV_LOG(ERR,
 329                                         "Cannot allocate mlx5 shared data\n");
 330                                 ret = -rte_errno;
 331                                 goto error;
 332                         }
 333                         mlx5_shared_data = mz->addr;
 334                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 335                         rte_spinlock_init(&mlx5_shared_data->lock);
 336                 } else {
 337                         /* Lookup allocated shared memory. */
 338                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 339                         if (mz == NULL) {
 340                                 DRV_LOG(ERR,
 341                                         "Cannot attach mlx5 shared data\n");
 342                                 ret = -rte_errno;
 343                                 goto error;
 344                         }
 345                         mlx5_shared_data = mz->addr;
 346                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 347                 }
 348         }
 349 error:
 350         rte_spinlock_unlock(&mlx5_shared_data_lock);
 351         return ret;
 352 }
 353
 354 /**
 355  * Uninitialize shared data between primary and secondary process.
 356  *
 357  * The pointer of secondary process is dereferenced and primary process frees
 358  * the memzone.
 359  */
 360 static void
 361 mlx5_uninit_shared_data(void)
 362 {
 363         const struct rte_memzone *mz;
 364
 365         rte_spinlock_lock(&mlx5_shared_data_lock);
 366         if (mlx5_shared_data) {
 367                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 368                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 369                         rte_memzone_free(mz);
 370                 } else {
 371                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 372                 }
 373                 mlx5_shared_data = NULL;
 374         }
 375         rte_spinlock_unlock(&mlx5_shared_data_lock);
 376 }
 377
 378 /**
 379  * Retrieve integer value from environment variable.
 380  *
 381  * @param[in] name
 382  *   Environment variable name.
 383  *
 384  * @return
 385  *   Integer value, 0 if the variable is not set.
 386  */
 387 int
 388 mlx5_getenv_int(const char *name)
 389 {
 390         const char *val = getenv(name);
 391
 392         if (val == NULL)
 393                 return 0;
 394         return atoi(val);
 395 }
 396
 397 /**
 398  * Verbs callback to allocate a memory. This function should allocate the space
 399  * according to the size provided residing inside a huge page.
 400  * Please note that all allocation must respect the alignment from libmlx5
 401  * (i.e. currently sysconf(_SC_PAGESIZE)).
 402  *
 403  * @param[in] size
 404  *   The size in bytes of the memory to allocate.
 405  * @param[in] data
 406  *   A pointer to the callback data.
 407  *
 408  * @return
 409  *   Allocated buffer, NULL otherwise and rte_errno is set.
 410  */
 411 static void *
 412 mlx5_alloc_verbs_buf(size_t size, void *data)
 413 {
 414         struct mlx5_priv *priv = data;
 415         void *ret;
 416         size_t alignment = sysconf(_SC_PAGESIZE);
 417         unsigned int socket = SOCKET_ID_ANY;
 418
 419         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 420                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 421
 422                 socket = ctrl->socket;
 423         } else if (priv->verbs_alloc_ctx.type ==
 424                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 425                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 426
 427                 socket = ctrl->socket;
 428         }
 429         assert(data != NULL);
 430         ret = rte_malloc_socket(__func__, size, alignment, socket);
 431         if (!ret && size)
 432                 rte_errno = ENOMEM;
 433         return ret;
 434 }
 435
 436 /**
 437  * Verbs callback to free a memory.
 438  *
 439  * @param[in] ptr
 440  *   A pointer to the memory to free.
 441  * @param[in] data
 442  *   A pointer to the callback data.
 443  */
 444 static void
 445 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 446 {
 447         assert(data != NULL);
 448         rte_free(ptr);
 449 }
 450
 451 /**
 452  * DPDK callback to close the device.
 453  *
 454  * Destroy all queues and objects, free memory.
 455  *
 456  * @param dev
 457  *   Pointer to Ethernet device structure.
 458  */
 459 static void
 460 mlx5_dev_close(struct rte_eth_dev *dev)
 461 {
 462         struct mlx5_priv *priv = dev->data->dev_private;
 463         unsigned int i;
 464         int ret;
 465
 466         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 467                 dev->data->port_id,
 468                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
 469         /* In case mlx5_dev_stop() has not been called. */
 470         mlx5_dev_interrupt_handler_uninstall(dev);
 471         mlx5_traffic_disable(dev);
 472         mlx5_flow_flush(dev, NULL);
 473         /* Prevent crashes when queues are still in use. */
 474         dev->rx_pkt_burst = removed_rx_burst;
 475         dev->tx_pkt_burst = removed_tx_burst;
 476         rte_wmb();
 477         /* Disable datapath on secondary process. */
 478         mlx5_mp_req_stop_rxtx(dev);
 479         if (priv->rxqs != NULL) {
 480                 /* XXX race condition if mlx5_rx_burst() is still running. */
 481                 usleep(1000);
 482                 for (i = 0; (i != priv->rxqs_n); ++i)
 483                         mlx5_rxq_release(dev, i);
 484                 priv->rxqs_n = 0;
 485                 priv->rxqs = NULL;
 486         }
 487         if (priv->txqs != NULL) {
 488                 /* XXX race condition if mlx5_tx_burst() is still running. */
 489                 usleep(1000);
 490                 for (i = 0; (i != priv->txqs_n); ++i)
 491                         mlx5_txq_release(dev, i);
 492                 priv->txqs_n = 0;
 493                 priv->txqs = NULL;
 494         }
 495         mlx5_mprq_free_mp(dev);
 496         mlx5_mr_release(dev);
 497         assert(priv->sh);
 498         if (priv->sh)
 499                 mlx5_free_shared_ibctx(priv->sh);
 500         priv->sh = NULL;
 501         if (priv->rss_conf.rss_key != NULL)
 502                 rte_free(priv->rss_conf.rss_key);
 503         if (priv->reta_idx != NULL)
 504                 rte_free(priv->reta_idx);
 505         if (priv->config.vf)
 506                 mlx5_nl_mac_addr_flush(dev);
 507         if (priv->nl_socket_route >= 0)
 508                 close(priv->nl_socket_route);
 509         if (priv->nl_socket_rdma >= 0)
 510                 close(priv->nl_socket_rdma);
 511         if (priv->tcf_context)
 512                 mlx5_flow_tcf_context_destroy(priv->tcf_context);
 513         ret = mlx5_hrxq_ibv_verify(dev);
 514         if (ret)
 515                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 516                         dev->data->port_id);
 517         ret = mlx5_ind_table_ibv_verify(dev);
 518         if (ret)
 519                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 520                         dev->data->port_id);
 521         ret = mlx5_rxq_ibv_verify(dev);
 522         if (ret)
 523                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 524                         dev->data->port_id);
 525         ret = mlx5_rxq_verify(dev);
 526         if (ret)
 527                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 528                         dev->data->port_id);
 529         ret = mlx5_txq_ibv_verify(dev);
 530         if (ret)
 531                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 532                         dev->data->port_id);
 533         ret = mlx5_txq_verify(dev);
 534         if (ret)
 535                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 536                         dev->data->port_id);
 537         ret = mlx5_flow_verify(dev);
 538         if (ret)
 539                 DRV_LOG(WARNING, "port %u some flows still remain",
 540                         dev->data->port_id);
 541         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
 542                 unsigned int c = 0;
 543                 uint16_t port_id;
 544
 545                 RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) {
 546                         struct mlx5_priv *opriv =
 547                                 rte_eth_devices[port_id].data->dev_private;
 548
 549                         if (!opriv ||
 550                             opriv->domain_id != priv->domain_id ||
 551                             &rte_eth_devices[port_id] == dev)
 552                                 continue;
 553                         ++c;
 554                 }
 555                 if (!c)
 556                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
 557         }
 558         memset(priv, 0, sizeof(*priv));
 559         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
 560         /*
 561          * Reset mac_addrs to NULL such that it is not freed as part of
 562          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
 563          * it is freed when dev_private is freed.
 564          */
 565         dev->data->mac_addrs = NULL;
 566 }
 567
 568 const struct eth_dev_ops mlx5_dev_ops = {
 569         .dev_configure = mlx5_dev_configure,
 570         .dev_start = mlx5_dev_start,
 571         .dev_stop = mlx5_dev_stop,
 572         .dev_set_link_down = mlx5_set_link_down,
 573         .dev_set_link_up = mlx5_set_link_up,
 574         .dev_close = mlx5_dev_close,
 575         .promiscuous_enable = mlx5_promiscuous_enable,
 576         .promiscuous_disable = mlx5_promiscuous_disable,
 577         .allmulticast_enable = mlx5_allmulticast_enable,
 578         .allmulticast_disable = mlx5_allmulticast_disable,
 579         .link_update = mlx5_link_update,
 580         .stats_get = mlx5_stats_get,
 581         .stats_reset = mlx5_stats_reset,
 582         .xstats_get = mlx5_xstats_get,
 583         .xstats_reset = mlx5_xstats_reset,
 584         .xstats_get_names = mlx5_xstats_get_names,
 585         .fw_version_get = mlx5_fw_version_get,
 586         .dev_infos_get = mlx5_dev_infos_get,
 587         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 588         .vlan_filter_set = mlx5_vlan_filter_set,
 589         .rx_queue_setup = mlx5_rx_queue_setup,
 590         .tx_queue_setup = mlx5_tx_queue_setup,
 591         .rx_queue_release = mlx5_rx_queue_release,
 592         .tx_queue_release = mlx5_tx_queue_release,
 593         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 594         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 595         .mac_addr_remove = mlx5_mac_addr_remove,
 596         .mac_addr_add = mlx5_mac_addr_add,
 597         .mac_addr_set = mlx5_mac_addr_set,
 598         .set_mc_addr_list = mlx5_set_mc_addr_list,
 599         .mtu_set = mlx5_dev_set_mtu,
 600         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 601         .vlan_offload_set = mlx5_vlan_offload_set,
 602         .reta_update = mlx5_dev_rss_reta_update,
 603         .reta_query = mlx5_dev_rss_reta_query,
 604         .rss_hash_update = mlx5_rss_hash_update,
 605         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 606         .filter_ctrl = mlx5_dev_filter_ctrl,
 607         .rx_descriptor_status = mlx5_rx_descriptor_status,
 608         .tx_descriptor_status = mlx5_tx_descriptor_status,
 609         .rx_queue_count = mlx5_rx_queue_count,
 610         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 611         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 612         .is_removed = mlx5_is_removed,
 613 };
 614
 615 /* Available operations from secondary process. */
 616 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 617         .stats_get = mlx5_stats_get,
 618         .stats_reset = mlx5_stats_reset,
 619         .xstats_get = mlx5_xstats_get,
 620         .xstats_reset = mlx5_xstats_reset,
 621         .xstats_get_names = mlx5_xstats_get_names,
 622         .fw_version_get = mlx5_fw_version_get,
 623         .dev_infos_get = mlx5_dev_infos_get,
 624         .rx_descriptor_status = mlx5_rx_descriptor_status,
 625         .tx_descriptor_status = mlx5_tx_descriptor_status,
 626 };
 627
 628 /* Available operations in flow isolated mode. */
 629 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 630         .dev_configure = mlx5_dev_configure,
 631         .dev_start = mlx5_dev_start,
 632         .dev_stop = mlx5_dev_stop,
 633         .dev_set_link_down = mlx5_set_link_down,
 634         .dev_set_link_up = mlx5_set_link_up,
 635         .dev_close = mlx5_dev_close,
 636         .promiscuous_enable = mlx5_promiscuous_enable,
 637         .promiscuous_disable = mlx5_promiscuous_disable,
 638         .allmulticast_enable = mlx5_allmulticast_enable,
 639         .allmulticast_disable = mlx5_allmulticast_disable,
 640         .link_update = mlx5_link_update,
 641         .stats_get = mlx5_stats_get,
 642         .stats_reset = mlx5_stats_reset,
 643         .xstats_get = mlx5_xstats_get,
 644         .xstats_reset = mlx5_xstats_reset,
 645         .xstats_get_names = mlx5_xstats_get_names,
 646         .fw_version_get = mlx5_fw_version_get,
 647         .dev_infos_get = mlx5_dev_infos_get,
 648         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 649         .vlan_filter_set = mlx5_vlan_filter_set,
 650         .rx_queue_setup = mlx5_rx_queue_setup,
 651         .tx_queue_setup = mlx5_tx_queue_setup,
 652         .rx_queue_release = mlx5_rx_queue_release,
 653         .tx_queue_release = mlx5_tx_queue_release,
 654         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 655         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 656         .mac_addr_remove = mlx5_mac_addr_remove,
 657         .mac_addr_add = mlx5_mac_addr_add,
 658         .mac_addr_set = mlx5_mac_addr_set,
 659         .set_mc_addr_list = mlx5_set_mc_addr_list,
 660         .mtu_set = mlx5_dev_set_mtu,
 661         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 662         .vlan_offload_set = mlx5_vlan_offload_set,
 663         .filter_ctrl = mlx5_dev_filter_ctrl,
 664         .rx_descriptor_status = mlx5_rx_descriptor_status,
 665         .tx_descriptor_status = mlx5_tx_descriptor_status,
 666         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 667         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 668         .is_removed = mlx5_is_removed,
 669 };
 670
 671 /**
 672  * Verify and store value for device argument.
 673  *
 674  * @param[in] key
 675  *   Key argument to verify.
 676  * @param[in] val
 677  *   Value associated with key.
 678  * @param opaque
 679  *   User data.
 680  *
 681  * @return
 682  *   0 on success, a negative errno value otherwise and rte_errno is set.
 683  */
 684 static int
 685 mlx5_args_check(const char *key, const char *val, void *opaque)
 686 {
 687         struct mlx5_dev_config *config = opaque;
 688         unsigned long tmp;
 689
 690         /* No-op, port representors are processed in mlx5_dev_spawn(). */
 691         if (!strcmp(MLX5_REPRESENTOR, key))
 692                 return 0;
 693         errno = 0;
 694         tmp = strtoul(val, NULL, 0);
 695         if (errno) {
 696                 rte_errno = errno;
 697                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 698                 return -rte_errno;
 699         }
 700         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 701                 config->cqe_comp = !!tmp;
 702         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
 703                 config->cqe_pad = !!tmp;
 704         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
 705                 config->hw_padding = !!tmp;
 706         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 707                 config->mprq.enabled = !!tmp;
 708         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
 709                 config->mprq.stride_num_n = tmp;
 710         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
 711                 config->mprq.max_memcpy_len = tmp;
 712         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
 713                 config->mprq.min_rxqs_num = tmp;
 714         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 715                 config->txq_inline = tmp;
 716         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 717                 config->txqs_inline = tmp;
 718         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
 719                 config->txqs_vec = tmp;
 720         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 721                 config->mps = !!tmp;
 722         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 723                 config->mpw_hdr_dseg = !!tmp;
 724         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 725                 config->inline_max_packet_sz = tmp;
 726         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 727                 config->tx_vec_en = !!tmp;
 728         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 729                 config->rx_vec_en = !!tmp;
 730         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 731                 config->l3_vxlan_en = !!tmp;
 732         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 733                 config->vf_nl_en = !!tmp;
 734         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
 735                 config->dv_flow_en = !!tmp;
 736         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
 737                 config->mr_ext_memseg_en = !!tmp;
 738         } else {
 739                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 740                 rte_errno = EINVAL;
 741                 return -rte_errno;
 742         }
 743         return 0;
 744 }
 745
 746 /**
 747  * Parse device parameters.
 748  *
 749  * @param config
 750  *   Pointer to device configuration structure.
 751  * @param devargs
 752  *   Device arguments structure.
 753  *
 754  * @return
 755  *   0 on success, a negative errno value otherwise and rte_errno is set.
 756  */
 757 static int
 758 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 759 {
 760         const char **params = (const char *[]){
 761                 MLX5_RXQ_CQE_COMP_EN,
 762                 MLX5_RXQ_CQE_PAD_EN,
 763                 MLX5_RXQ_PKT_PAD_EN,
 764                 MLX5_RX_MPRQ_EN,
 765                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
 766                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
 767                 MLX5_RXQS_MIN_MPRQ,
 768                 MLX5_TXQ_INLINE,
 769                 MLX5_TXQS_MIN_INLINE,
 770                 MLX5_TXQS_MAX_VEC,
 771                 MLX5_TXQ_MPW_EN,
 772                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 773                 MLX5_TXQ_MAX_INLINE_LEN,
 774                 MLX5_TX_VEC_EN,
 775                 MLX5_RX_VEC_EN,
 776                 MLX5_L3_VXLAN_EN,
 777                 MLX5_VF_NL_EN,
 778                 MLX5_DV_FLOW_EN,
 779                 MLX5_MR_EXT_MEMSEG_EN,
 780                 MLX5_REPRESENTOR,
 781                 NULL,
 782         };
 783         struct rte_kvargs *kvlist;
 784         int ret = 0;
 785         int i;
 786
 787         if (devargs == NULL)
 788                 return 0;
 789         /* Following UGLY cast is done to pass checkpatch. */
 790         kvlist = rte_kvargs_parse(devargs->args, params);
 791         if (kvlist == NULL)
 792                 return 0;
 793         /* Process parameters. */
 794         for (i = 0; (params[i] != NULL); ++i) {
 795                 if (rte_kvargs_count(kvlist, params[i])) {
 796                         ret = rte_kvargs_process(kvlist, params[i],
 797                                                  mlx5_args_check, config);
 798                         if (ret) {
 799                                 rte_errno = EINVAL;
 800                                 rte_kvargs_free(kvlist);
 801                                 return -rte_errno;
 802                         }
 803                 }
 804         }
 805         rte_kvargs_free(kvlist);
 806         return 0;
 807 }
 808
 809 static struct rte_pci_driver mlx5_driver;
 810
 811 static int
 812 find_lower_va_bound(const struct rte_memseg_list *msl,
 813                 const struct rte_memseg *ms, void *arg)
 814 {
 815         void **addr = arg;
 816
 817         if (msl->external)
 818                 return 0;
 819         if (*addr == NULL)
 820                 *addr = ms->addr;
 821         else
 822                 *addr = RTE_MIN(*addr, ms->addr);
 823
 824         return 0;
 825 }
 826
 827 /**
 828  * Reserve UAR address space for primary process.
 829  *
 830  * Process local resource is used by both primary and secondary to avoid
 831  * duplicate reservation. The space has to be available on both primary and
 832  * secondary process, TXQ UAR maps to this area using fixed mmap w/o double
 833  * check.
 834  *
 835  * @return
 836  *   0 on success, a negative errno value otherwise and rte_errno is set.
 837  */
 838 static int
 839 mlx5_uar_init_primary(void)
 840 {
 841         struct mlx5_shared_data *sd = mlx5_shared_data;
 842         void *addr = (void *)0;
 843
 844         if (sd->uar_base)
 845                 return 0;
 846         /* find out lower bound of hugepage segments */
 847         rte_memseg_walk(find_lower_va_bound, &addr);
 848         /* keep distance to hugepages to minimize potential conflicts. */
 849         addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
 850         /* anonymous mmap, no real memory consumption. */
 851         addr = mmap(addr, MLX5_UAR_SIZE,
 852                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 853         if (addr == MAP_FAILED) {
 854                 DRV_LOG(ERR,
 855                         "Failed to reserve UAR address space, please"
 856                         " adjust MLX5_UAR_SIZE or try --base-virtaddr");
 857                 rte_errno = ENOMEM;
 858                 return -rte_errno;
 859         }
 860         /* Accept either same addr or a new addr returned from mmap if target
 861          * range occupied.
 862          */
 863         DRV_LOG(INFO, "Reserved UAR address space: %p", addr);
 864         sd->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 865         return 0;
 866 }
 867
 868 /**
 869  * Unmap UAR address space reserved for primary process.
 870  */
 871 static void
 872 mlx5_uar_uninit_primary(void)
 873 {
 874         struct mlx5_shared_data *sd = mlx5_shared_data;
 875
 876         if (!sd->uar_base)
 877                 return;
 878         munmap(sd->uar_base, MLX5_UAR_SIZE);
 879         sd->uar_base = NULL;
 880 }
 881
 882 /**
 883  * Reserve UAR address space for secondary process, align with primary process.
 884  *
 885  * @return
 886  *   0 on success, a negative errno value otherwise and rte_errno is set.
 887  */
 888 static int
 889 mlx5_uar_init_secondary(void)
 890 {
 891         struct mlx5_shared_data *sd = mlx5_shared_data;
 892         struct mlx5_local_data *ld = &mlx5_local_data;
 893         void *addr;
 894
 895         if (ld->uar_base) { /* Already reserved. */
 896                 assert(sd->uar_base == ld->uar_base);
 897                 return 0;
 898         }
 899         assert(sd->uar_base);
 900         /* anonymous mmap, no real memory consumption. */
 901         addr = mmap(sd->uar_base, MLX5_UAR_SIZE,
 902                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 903         if (addr == MAP_FAILED) {
 904                 DRV_LOG(ERR, "UAR mmap failed: %p size: %llu",
 905                         sd->uar_base, MLX5_UAR_SIZE);
 906                 rte_errno = ENXIO;
 907                 return -rte_errno;
 908         }
 909         if (sd->uar_base != addr) {
 910                 DRV_LOG(ERR,
 911                         "UAR address %p size %llu occupied, please"
 912                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 913                         " --base-virtaddr",
 914                         sd->uar_base, MLX5_UAR_SIZE);
 915                 rte_errno = ENXIO;
 916                 return -rte_errno;
 917         }
 918         ld->uar_base = addr;
 919         DRV_LOG(INFO, "Reserved UAR address space: %p", addr);
 920         return 0;
 921 }
 922
 923 /**
 924  * Unmap UAR address space reserved for secondary process.
 925  */
 926 static void
 927 mlx5_uar_uninit_secondary(void)
 928 {
 929         struct mlx5_local_data *ld = &mlx5_local_data;
 930
 931         if (!ld->uar_base)
 932                 return;
 933         munmap(ld->uar_base, MLX5_UAR_SIZE);
 934         ld->uar_base = NULL;
 935 }
 936
 937 /**
 938  * PMD global initialization.
 939  *
 940  * Independent from individual device, this function initializes global
 941  * per-PMD data structures distinguishing primary and secondary processes.
 942  * Hence, each initialization is called once per a process.
 943  *
 944  * @return
 945  *   0 on success, a negative errno value otherwise and rte_errno is set.
 946  */
 947 static int
 948 mlx5_init_once(void)
 949 {
 950         struct mlx5_shared_data *sd;
 951         struct mlx5_local_data *ld = &mlx5_local_data;
 952         int ret;
 953
 954         if (mlx5_init_shared_data())
 955                 return -rte_errno;
 956         sd = mlx5_shared_data;
 957         assert(sd);
 958         rte_spinlock_lock(&sd->lock);
 959         switch (rte_eal_process_type()) {
 960         case RTE_PROC_PRIMARY:
 961                 if (sd->init_done)
 962                         break;
 963                 LIST_INIT(&sd->mem_event_cb_list);
 964                 rte_rwlock_init(&sd->mem_event_rwlock);
 965                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 966                                                 mlx5_mr_mem_event_cb, NULL);
 967                 mlx5_mp_init_primary();
 968                 ret = mlx5_uar_init_primary();
 969                 if (ret)
 970                         goto error;
 971                 sd->init_done = true;
 972                 break;
 973         case RTE_PROC_SECONDARY:
 974                 if (ld->init_done)
 975                         break;
 976                 mlx5_mp_init_secondary();
 977                 ret = mlx5_uar_init_secondary();
 978                 if (ret)
 979                         goto error;
 980                 ++sd->secondary_cnt;
 981                 ld->init_done = true;
 982                 break;
 983         default:
 984                 break;
 985         }
 986         rte_spinlock_unlock(&sd->lock);
 987         return 0;
 988 error:
 989         switch (rte_eal_process_type()) {
 990         case RTE_PROC_PRIMARY:
 991                 mlx5_uar_uninit_primary();
 992                 mlx5_mp_uninit_primary();
 993                 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", NULL);
 994                 break;
 995         case RTE_PROC_SECONDARY:
 996                 mlx5_uar_uninit_secondary();
 997                 mlx5_mp_uninit_secondary();
 998                 break;
 999         default:
1000                 break;
1001         }
1002         rte_spinlock_unlock(&sd->lock);
1003         mlx5_uninit_shared_data();
1004         return -rte_errno;
1005 }
1006
1007 /**
1008  * Spawn an Ethernet device from Verbs information.
1009  *
1010  * @param dpdk_dev
1011  *   Backing DPDK device.
1012  * @param spawn
1013  *   Verbs device parameters (name, port, switch_info) to spawn.
1014  * @param config
1015  *   Device configuration parameters.
1016  *
1017  * @return
1018  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
1019  *   is set. The following errors are defined:
1020  *
1021  *   EBUSY: device is not supposed to be spawned.
1022  *   EEXIST: device is already spawned
1023  */
1024 static struct rte_eth_dev *
1025 mlx5_dev_spawn(struct rte_device *dpdk_dev,
1026                struct mlx5_dev_spawn_data *spawn,
1027                struct mlx5_dev_config config)
1028 {
1029         const struct mlx5_switch_info *switch_info = &spawn->info;
1030         struct mlx5_ibv_shared *sh = NULL;
1031         struct ibv_port_attr port_attr;
1032         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
1033         struct rte_eth_dev *eth_dev = NULL;
1034         struct mlx5_priv *priv = NULL;
1035         int err = 0;
1036         unsigned int hw_padding = 0;
1037         unsigned int mps;
1038         unsigned int cqe_comp;
1039         unsigned int cqe_pad = 0;
1040         unsigned int tunnel_en = 0;
1041         unsigned int mpls_en = 0;
1042         unsigned int swp = 0;
1043         unsigned int mprq = 0;
1044         unsigned int mprq_min_stride_size_n = 0;
1045         unsigned int mprq_max_stride_size_n = 0;
1046         unsigned int mprq_min_stride_num_n = 0;
1047         unsigned int mprq_max_stride_num_n = 0;
1048         struct ether_addr mac;
1049         char name[RTE_ETH_NAME_MAX_LEN];
1050         int own_domain_id = 0;
1051         uint16_t port_id;
1052         unsigned int i;
1053
1054         /* Determine if this port representor is supposed to be spawned. */
1055         if (switch_info->representor && dpdk_dev->devargs) {
1056                 struct rte_eth_devargs eth_da;
1057
1058                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
1059                 if (err) {
1060                         rte_errno = -err;
1061                         DRV_LOG(ERR, "failed to process device arguments: %s",
1062                                 strerror(rte_errno));
1063                         return NULL;
1064                 }
1065                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
1066                         if (eth_da.representor_ports[i] ==
1067                             (uint16_t)switch_info->port_name)
1068                                 break;
1069                 if (i == eth_da.nb_representor_ports) {
1070                         rte_errno = EBUSY;
1071                         return NULL;
1072                 }
1073         }
1074         /* Build device name. */
1075         if (!switch_info->representor)
1076                 strlcpy(name, dpdk_dev->name, sizeof(name));
1077         else
1078                 snprintf(name, sizeof(name), "%s_representor_%u",
1079                          dpdk_dev->name, switch_info->port_name);
1080         /* check if the device is already spawned */
1081         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
1082                 rte_errno = EEXIST;
1083                 return NULL;
1084         }
1085         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
1086         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1087                 eth_dev = rte_eth_dev_attach_secondary(name);
1088                 if (eth_dev == NULL) {
1089                         DRV_LOG(ERR, "can not attach rte ethdev");
1090                         rte_errno = ENOMEM;
1091                         return NULL;
1092                 }
1093                 eth_dev->device = dpdk_dev;
1094                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
1095                 /* Receive command fd from primary process */
1096                 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
1097                 if (err < 0)
1098                         return NULL;
1099                 /* Remap UAR for Tx queues. */
1100                 err = mlx5_tx_uar_remap(eth_dev, err);
1101                 if (err)
1102                         return NULL;
1103                 /*
1104                  * Ethdev pointer is still required as input since
1105                  * the primary device is not accessible from the
1106                  * secondary process.
1107                  */
1108                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
1109                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
1110                 return eth_dev;
1111         }
1112         sh = mlx5_alloc_shared_ibctx(spawn);
1113         if (!sh)
1114                 return NULL;
1115         config.devx = sh->devx;
1116 #ifdef HAVE_IBV_MLX5_MOD_SWP
1117         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
1118 #endif
1119         /*
1120          * Multi-packet send is supported by ConnectX-4 Lx PF as well
1121          * as all ConnectX-5 devices.
1122          */
1123 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1124         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1125 #endif
1126 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1127         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
1128 #endif
1129         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
1130         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
1131                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1132                         DRV_LOG(DEBUG, "enhanced MPW is supported");
1133                         mps = MLX5_MPW_ENHANCED;
1134                 } else {
1135                         DRV_LOG(DEBUG, "MPW is supported");
1136                         mps = MLX5_MPW;
1137                 }
1138         } else {
1139                 DRV_LOG(DEBUG, "MPW isn't supported");
1140                 mps = MLX5_MPW_DISABLED;
1141         }
1142 #ifdef HAVE_IBV_MLX5_MOD_SWP
1143         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
1144                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
1145         DRV_LOG(DEBUG, "SWP support: %u", swp);
1146 #endif
1147         config.swp = !!swp;
1148 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
1149         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
1150                 struct mlx5dv_striding_rq_caps mprq_caps =
1151                         dv_attr.striding_rq_caps;
1152
1153                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
1154                         mprq_caps.min_single_stride_log_num_of_bytes);
1155                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
1156                         mprq_caps.max_single_stride_log_num_of_bytes);
1157                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
1158                         mprq_caps.min_single_wqe_log_num_of_strides);
1159                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
1160                         mprq_caps.max_single_wqe_log_num_of_strides);
1161                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
1162                         mprq_caps.supported_qpts);
1163                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
1164                 mprq = 1;
1165                 mprq_min_stride_size_n =
1166                         mprq_caps.min_single_stride_log_num_of_bytes;
1167                 mprq_max_stride_size_n =
1168                         mprq_caps.max_single_stride_log_num_of_bytes;
1169                 mprq_min_stride_num_n =
1170                         mprq_caps.min_single_wqe_log_num_of_strides;
1171                 mprq_max_stride_num_n =
1172                         mprq_caps.max_single_wqe_log_num_of_strides;
1173                 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1174                                                    mprq_min_stride_num_n);
1175         }
1176 #endif
1177         if (RTE_CACHE_LINE_SIZE == 128 &&
1178             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
1179                 cqe_comp = 0;
1180         else
1181                 cqe_comp = 1;
1182         config.cqe_comp = cqe_comp;
1183 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1184         /* Whether device supports 128B Rx CQE padding. */
1185         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
1186                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
1187 #endif
1188 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
1189         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
1190                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
1191                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
1192                              (dv_attr.tunnel_offloads_caps &
1193                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
1194         }
1195         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
1196                 tunnel_en ? "" : "not ");
1197 #else
1198         DRV_LOG(WARNING,
1199                 "tunnel offloading disabled due to old OFED/rdma-core version");
1200 #endif
1201         config.tunnel_en = tunnel_en;
1202 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
1203         mpls_en = ((dv_attr.tunnel_offloads_caps &
1204                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
1205                    (dv_attr.tunnel_offloads_caps &
1206                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
1207         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
1208                 mpls_en ? "" : "not ");
1209 #else
1210         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
1211                 " old OFED/rdma-core version or firmware configuration");
1212 #endif
1213         config.mpls_en = mpls_en;
1214         /* Check port status. */
1215         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
1216         if (err) {
1217                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
1218                 goto error;
1219         }
1220         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
1221                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
1222                 err = EINVAL;
1223                 goto error;
1224         }
1225         if (port_attr.state != IBV_PORT_ACTIVE)
1226                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
1227                         mlx5_glue->port_state_str(port_attr.state),
1228                         port_attr.state);
1229         /* Allocate private eth device data. */
1230         priv = rte_zmalloc("ethdev private structure",
1231                            sizeof(*priv),
1232                            RTE_CACHE_LINE_SIZE);
1233         if (priv == NULL) {
1234                 DRV_LOG(ERR, "priv allocation failure");
1235                 err = ENOMEM;
1236                 goto error;
1237         }
1238         priv->sh = sh;
1239         priv->ibv_port = spawn->ibv_port;
1240         priv->mtu = ETHER_MTU;
1241 #ifndef RTE_ARCH_64
1242         /* Initialize UAR access locks for 32bit implementations. */
1243         rte_spinlock_init(&priv->uar_lock_cq);
1244         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1245                 rte_spinlock_init(&priv->uar_lock[i]);
1246 #endif
1247         /* Some internal functions rely on Netlink sockets, open them now. */
1248         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
1249         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
1250         priv->nl_sn = 0;
1251         priv->representor = !!switch_info->representor;
1252         priv->master = !!switch_info->master;
1253         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1254         /*
1255          * Currently we support single E-Switch per PF configurations
1256          * only and vport_id field contains the vport index for
1257          * associated VF, which is deduced from representor port name.
1258          * For exapmple, let's have the IB device port 10, it has
1259          * attached network device eth0, which has port name attribute
1260          * pf0vf2, we can deduce the VF number as 2, and set vport index
1261          * as 3 (2+1). This assigning schema should be changed if the
1262          * multiple E-Switch instances per PF configurations or/and PCI
1263          * subfunctions are added.
1264          */
1265         priv->vport_id = switch_info->representor ?
1266                          switch_info->port_name + 1 : -1;
1267         /* representor_id field keeps the unmodified port/VF index. */
1268         priv->representor_id = switch_info->representor ?
1269                                switch_info->port_name : -1;
1270         /*
1271          * Look for sibling devices in order to reuse their switch domain
1272          * if any, otherwise allocate one.
1273          */
1274         RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) {
1275                 const struct mlx5_priv *opriv =
1276                         rte_eth_devices[port_id].data->dev_private;
1277
1278                 if (!opriv ||
1279                         opriv->domain_id ==
1280                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1281                         continue;
1282                 priv->domain_id = opriv->domain_id;
1283                 break;
1284         }
1285         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1286                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1287                 if (err) {
1288                         err = rte_errno;
1289                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
1290                                 strerror(rte_errno));
1291                         goto error;
1292                 }
1293                 own_domain_id = 1;
1294         }
1295         err = mlx5_args(&config, dpdk_dev->devargs);
1296         if (err) {
1297                 err = rte_errno;
1298                 DRV_LOG(ERR, "failed to process device arguments: %s",
1299                         strerror(rte_errno));
1300                 goto error;
1301         }
1302         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
1303                             IBV_DEVICE_RAW_IP_CSUM);
1304         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1305                 (config.hw_csum ? "" : "not "));
1306 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1307         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1308         DRV_LOG(DEBUG, "counters are not supported");
1309 #endif
1310 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1311         if (config.dv_flow_en) {
1312                 DRV_LOG(WARNING, "DV flow is not supported");
1313                 config.dv_flow_en = 0;
1314         }
1315 #endif
1316         config.ind_table_max_size =
1317                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
1318         /*
1319          * Remove this check once DPDK supports larger/variable
1320          * indirection tables.
1321          */
1322         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1323                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1324         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1325                 config.ind_table_max_size);
1326         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
1327                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1328         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1329                 (config.hw_vlan_strip ? "" : "not "));
1330         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1331                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
1332         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1333                 (config.hw_fcs_strip ? "" : "not "));
1334 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1335         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
1336 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1337         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
1338                         IBV_DEVICE_PCI_WRITE_END_PADDING);
1339 #endif
1340         if (config.hw_padding && !hw_padding) {
1341                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1342                 config.hw_padding = 0;
1343         } else if (config.hw_padding) {
1344                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1345         }
1346         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
1347                       (sh->device_attr.tso_caps.supported_qpts &
1348                        (1 << IBV_QPT_RAW_PACKET)));
1349         if (config.tso)
1350                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
1351         /*
1352          * MPW is disabled by default, while the Enhanced MPW is enabled
1353          * by default.
1354          */
1355         if (config.mps == MLX5_ARG_UNSET)
1356                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1357                                                           MLX5_MPW_DISABLED;
1358         else
1359                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1360         DRV_LOG(INFO, "%sMPS is %s",
1361                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1362                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1363         if (config.cqe_comp && !cqe_comp) {
1364                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1365                 config.cqe_comp = 0;
1366         }
1367         if (config.cqe_pad && !cqe_pad) {
1368                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1369                 config.cqe_pad = 0;
1370         } else if (config.cqe_pad) {
1371                 DRV_LOG(INFO, "Rx CQE padding is enabled");
1372         }
1373         if (config.mprq.enabled && mprq) {
1374                 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1375                     config.mprq.stride_num_n < mprq_min_stride_num_n) {
1376                         config.mprq.stride_num_n =
1377                                 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1378                                         mprq_min_stride_num_n);
1379                         DRV_LOG(WARNING,
1380                                 "the number of strides"
1381                                 " for Multi-Packet RQ is out of range,"
1382                                 " setting default value (%u)",
1383                                 1 << config.mprq.stride_num_n);
1384                 }
1385                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1386                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1387         } else if (config.mprq.enabled && !mprq) {
1388                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1389                 config.mprq.enabled = 0;
1390         }
1391         eth_dev = rte_eth_dev_allocate(name);
1392         if (eth_dev == NULL) {
1393                 DRV_LOG(ERR, "can not allocate rte ethdev");
1394                 err = ENOMEM;
1395                 goto error;
1396         }
1397         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1398         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1399         if (priv->representor) {
1400                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1401                 eth_dev->data->representor_id = priv->representor_id;
1402         }
1403         eth_dev->data->dev_private = priv;
1404         priv->dev_data = eth_dev->data;
1405         eth_dev->data->mac_addrs = priv->mac;
1406         eth_dev->device = dpdk_dev;
1407         /* Configure the first MAC address by default. */
1408         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1409                 DRV_LOG(ERR,
1410                         "port %u cannot get MAC address, is mlx5_en"
1411                         " loaded? (errno: %s)",
1412                         eth_dev->data->port_id, strerror(rte_errno));
1413                 err = ENODEV;
1414                 goto error;
1415         }
1416         DRV_LOG(INFO,
1417                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1418                 eth_dev->data->port_id,
1419                 mac.addr_bytes[0], mac.addr_bytes[1],
1420                 mac.addr_bytes[2], mac.addr_bytes[3],
1421                 mac.addr_bytes[4], mac.addr_bytes[5]);
1422 #ifndef NDEBUG
1423         {
1424                 char ifname[IF_NAMESIZE];
1425
1426                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1427                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1428                                 eth_dev->data->port_id, ifname);
1429                 else
1430                         DRV_LOG(DEBUG, "port %u ifname is unknown",
1431                                 eth_dev->data->port_id);
1432         }
1433 #endif
1434         /* Get actual MTU if possible. */
1435         err = mlx5_get_mtu(eth_dev, &priv->mtu);
1436         if (err) {
1437                 err = rte_errno;
1438                 goto error;
1439         }
1440         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1441                 priv->mtu);
1442         /* Initialize burst functions to prevent crashes before link-up. */
1443         eth_dev->rx_pkt_burst = removed_rx_burst;
1444         eth_dev->tx_pkt_burst = removed_tx_burst;
1445         eth_dev->dev_ops = &mlx5_dev_ops;
1446         /* Register MAC address. */
1447         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1448         if (config.vf && config.vf_nl_en)
1449                 mlx5_nl_mac_addr_sync(eth_dev);
1450         priv->tcf_context = mlx5_flow_tcf_context_create();
1451         if (!priv->tcf_context) {
1452                 err = -rte_errno;
1453                 DRV_LOG(WARNING,
1454                         "flow rules relying on switch offloads will not be"
1455                         " supported: cannot open libmnl socket: %s",
1456                         strerror(rte_errno));
1457         } else {
1458                 struct rte_flow_error error;
1459                 unsigned int ifindex = mlx5_ifindex(eth_dev);
1460
1461                 if (!ifindex) {
1462                         err = -rte_errno;
1463                         error.message =
1464                                 "cannot retrieve network interface index";
1465                 } else {
1466                         err = mlx5_flow_tcf_init(priv->tcf_context,
1467                                                  ifindex, &error);
1468                 }
1469                 if (err) {
1470                         DRV_LOG(WARNING,
1471                                 "flow rules relying on switch offloads will"
1472                                 " not be supported: %s: %s",
1473                                 error.message, strerror(rte_errno));
1474                         mlx5_flow_tcf_context_destroy(priv->tcf_context);
1475                         priv->tcf_context = NULL;
1476                 }
1477         }
1478         TAILQ_INIT(&priv->flows);
1479         TAILQ_INIT(&priv->ctrl_flows);
1480         /* Hint libmlx5 to use PMD allocator for data plane resources */
1481         struct mlx5dv_ctx_allocators alctr = {
1482                 .alloc = &mlx5_alloc_verbs_buf,
1483                 .free = &mlx5_free_verbs_buf,
1484                 .data = priv,
1485         };
1486         mlx5_glue->dv_set_context_attr(sh->ctx,
1487                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1488                                        (void *)((uintptr_t)&alctr));
1489         /* Bring Ethernet device up. */
1490         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1491                 eth_dev->data->port_id);
1492         mlx5_set_link_up(eth_dev);
1493         /*
1494          * Even though the interrupt handler is not installed yet,
1495          * interrupts will still trigger on the asyn_fd from
1496          * Verbs context returned by ibv_open_device().
1497          */
1498         mlx5_link_update(eth_dev, 0);
1499         /* Store device configuration on private structure. */
1500         priv->config = config;
1501         /* Supported Verbs flow priority number detection. */
1502         err = mlx5_flow_discover_priorities(eth_dev);
1503         if (err < 0) {
1504                 err = -err;
1505                 goto error;
1506         }
1507         priv->config.flow_prio = err;
1508         /*
1509          * Once the device is added to the list of memory event
1510          * callback, its global MR cache table cannot be expanded
1511          * on the fly because of deadlock. If it overflows, lookup
1512          * should be done by searching MR list linearly, which is slow.
1513          */
1514         err = mlx5_mr_btree_init(&priv->mr.cache,
1515                                  MLX5_MR_BTREE_CACHE_N * 2,
1516                                  eth_dev->device->numa_node);
1517         if (err) {
1518                 err = rte_errno;
1519                 goto error;
1520         }
1521         /* Add device to memory callback list. */
1522         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1523         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1524                          priv, mem_event_cb);
1525         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1526         return eth_dev;
1527 error:
1528         if (priv) {
1529                 if (priv->nl_socket_route >= 0)
1530                         close(priv->nl_socket_route);
1531                 if (priv->nl_socket_rdma >= 0)
1532                         close(priv->nl_socket_rdma);
1533                 if (priv->tcf_context)
1534                         mlx5_flow_tcf_context_destroy(priv->tcf_context);
1535                 if (own_domain_id)
1536                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1537                 rte_free(priv);
1538                 if (eth_dev != NULL)
1539                         eth_dev->data->dev_private = NULL;
1540         }
1541         if (eth_dev != NULL) {
1542                 /* mac_addrs must not be freed alone because part of dev_private */
1543                 eth_dev->data->mac_addrs = NULL;
1544                 rte_eth_dev_release_port(eth_dev);
1545         }
1546         if (sh)
1547                 mlx5_free_shared_ibctx(sh);
1548         assert(err > 0);
1549         rte_errno = err;
1550         return NULL;
1551 }
1552
1553 /**
1554  * Comparison callback to sort device data.
1555  *
1556  * This is meant to be used with qsort().
1557  *
1558  * @param a[in]
1559  *   Pointer to pointer to first data object.
1560  * @param b[in]
1561  *   Pointer to pointer to second data object.
1562  *
1563  * @return
1564  *   0 if both objects are equal, less than 0 if the first argument is less
1565  *   than the second, greater than 0 otherwise.
1566  */
1567 static int
1568 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1569 {
1570         const struct mlx5_switch_info *si_a =
1571                 &((const struct mlx5_dev_spawn_data *)a)->info;
1572         const struct mlx5_switch_info *si_b =
1573                 &((const struct mlx5_dev_spawn_data *)b)->info;
1574         int ret;
1575
1576         /* Master device first. */
1577         ret = si_b->master - si_a->master;
1578         if (ret)
1579                 return ret;
1580         /* Then representor devices. */
1581         ret = si_b->representor - si_a->representor;
1582         if (ret)
1583                 return ret;
1584         /* Unidentified devices come last in no specific order. */
1585         if (!si_a->representor)
1586                 return 0;
1587         /* Order representors by name. */
1588         return si_a->port_name - si_b->port_name;
1589 }
1590
1591 /**
1592  * DPDK callback to register a PCI device.
1593  *
1594  * This function spawns Ethernet devices out of a given PCI device.
1595  *
1596  * @param[in] pci_drv
1597  *   PCI driver structure (mlx5_driver).
1598  * @param[in] pci_dev
1599  *   PCI device information.
1600  *
1601  * @return
1602  *   0 on success, a negative errno value otherwise and rte_errno is set.
1603  */
1604 static int
1605 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1606                struct rte_pci_device *pci_dev)
1607 {
1608         struct ibv_device **ibv_list;
1609         /*
1610          * Number of found IB Devices matching with requested PCI BDF.
1611          * nd != 1 means there are multiple IB devices over the same
1612          * PCI device and we have representors and master.
1613          */
1614         unsigned int nd = 0;
1615         /*
1616          * Number of found IB device Ports. nd = 1 and np = 1..n means
1617          * we have the single multiport IB device, and there may be
1618          * representors attached to some of found ports.
1619          */
1620         unsigned int np = 0;
1621         /*
1622          * Number of DPDK ethernet devices to Spawn - either over
1623          * multiple IB devices or multiple ports of single IB device.
1624          * Actually this is the number of iterations to spawn.
1625          */
1626         unsigned int ns = 0;
1627         struct mlx5_dev_config dev_config;
1628         int ret;
1629
1630         ret = mlx5_init_once();
1631         if (ret) {
1632                 DRV_LOG(ERR, "unable to init PMD global data: %s",
1633                         strerror(rte_errno));
1634                 return -rte_errno;
1635         }
1636         assert(pci_drv == &mlx5_driver);
1637         errno = 0;
1638         ibv_list = mlx5_glue->get_device_list(&ret);
1639         if (!ibv_list) {
1640                 rte_errno = errno ? errno : ENOSYS;
1641                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1642                 return -rte_errno;
1643         }
1644         /*
1645          * First scan the list of all Infiniband devices to find
1646          * matching ones, gathering into the list.
1647          */
1648         struct ibv_device *ibv_match[ret + 1];
1649         int nl_route = -1;
1650         int nl_rdma = -1;
1651         unsigned int i;
1652
1653         while (ret-- > 0) {
1654                 struct rte_pci_addr pci_addr;
1655
1656                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1657                 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1658                         continue;
1659                 if (pci_dev->addr.domain != pci_addr.domain ||
1660                     pci_dev->addr.bus != pci_addr.bus ||
1661                     pci_dev->addr.devid != pci_addr.devid ||
1662                     pci_dev->addr.function != pci_addr.function)
1663                         continue;
1664                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1665                         ibv_list[ret]->name);
1666                 ibv_match[nd++] = ibv_list[ret];
1667         }
1668         ibv_match[nd] = NULL;
1669         if (!nd) {
1670                 /* No device macthes, just complain and bail out. */
1671                 mlx5_glue->free_device_list(ibv_list);
1672                 DRV_LOG(WARNING,
1673                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
1674                         " are kernel drivers loaded?",
1675                         pci_dev->addr.domain, pci_dev->addr.bus,
1676                         pci_dev->addr.devid, pci_dev->addr.function);
1677                 rte_errno = ENOENT;
1678                 ret = -rte_errno;
1679                 return ret;
1680         }
1681         nl_route = mlx5_nl_init(NETLINK_ROUTE);
1682         nl_rdma = mlx5_nl_init(NETLINK_RDMA);
1683         if (nd == 1) {
1684                 /*
1685                  * Found single matching device may have multiple ports.
1686                  * Each port may be representor, we have to check the port
1687                  * number and check the representors existence.
1688                  */
1689                 if (nl_rdma >= 0)
1690                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
1691                 if (!np)
1692                         DRV_LOG(WARNING, "can not get IB device \"%s\""
1693                                          " ports number", ibv_match[0]->name);
1694         }
1695         /*
1696          * Now we can determine the maximal
1697          * amount of devices to be spawned.
1698          */
1699         struct mlx5_dev_spawn_data list[np ? np : nd];
1700
1701         if (np > 1) {
1702                 /*
1703                  * Signle IB device with multiple ports found,
1704                  * it may be E-Switch master device and representors.
1705                  * We have to perform identification trough the ports.
1706                  */
1707                 assert(nl_rdma >= 0);
1708                 assert(ns == 0);
1709                 assert(nd == 1);
1710                 for (i = 1; i <= np; ++i) {
1711                         list[ns].max_port = np;
1712                         list[ns].ibv_port = i;
1713                         list[ns].ibv_dev = ibv_match[0];
1714                         list[ns].eth_dev = NULL;
1715                         list[ns].ifindex = mlx5_nl_ifindex
1716                                         (nl_rdma, list[ns].ibv_dev->name, i);
1717                         if (!list[ns].ifindex) {
1718                                 /*
1719                                  * No network interface index found for the
1720                                  * specified port, it means there is no
1721                                  * representor on this port. It's OK,
1722                                  * there can be disabled ports, for example
1723                                  * if sriov_numvfs < sriov_totalvfs.
1724                                  */
1725                                 continue;
1726                         }
1727                         ret = -1;
1728                         if (nl_route >= 0)
1729                                 ret = mlx5_nl_switch_info
1730                                                (nl_route,
1731                                                 list[ns].ifindex,
1732                                                 &list[ns].info);
1733                         if (ret || (!list[ns].info.representor &&
1734                                     !list[ns].info.master)) {
1735                                 /*
1736                                  * We failed to recognize representors with
1737                                  * Netlink, let's try to perform the task
1738                                  * with sysfs.
1739                                  */
1740                                 ret =  mlx5_sysfs_switch_info
1741                                                 (list[ns].ifindex,
1742                                                  &list[ns].info);
1743                         }
1744                         if (!ret && (list[ns].info.representor ^
1745                                      list[ns].info.master))
1746                                 ns++;
1747                 }
1748                 if (!ns) {
1749                         DRV_LOG(ERR,
1750                                 "unable to recognize master/representors"
1751                                 " on the IB device with multiple ports");
1752                         rte_errno = ENOENT;
1753                         ret = -rte_errno;
1754                         goto exit;
1755                 }
1756         } else {
1757                 /*
1758                  * The existence of several matching entries (nd > 1) means
1759                  * port representors have been instantiated. No existing Verbs
1760                  * call nor sysfs entries can tell them apart, this can only
1761                  * be done through Netlink calls assuming kernel drivers are
1762                  * recent enough to support them.
1763                  *
1764                  * In the event of identification failure through Netlink,
1765                  * try again through sysfs, then:
1766                  *
1767                  * 1. A single IB device matches (nd == 1) with single
1768                  *    port (np=0/1) and is not a representor, assume
1769                  *    no switch support.
1770                  *
1771                  * 2. Otherwise no safe assumptions can be made;
1772                  *    complain louder and bail out.
1773                  */
1774                 np = 1;
1775                 for (i = 0; i != nd; ++i) {
1776                         memset(&list[ns].info, 0, sizeof(list[ns].info));
1777                         list[ns].max_port = 1;
1778                         list[ns].ibv_port = 1;
1779                         list[ns].ibv_dev = ibv_match[i];
1780                         list[ns].eth_dev = NULL;
1781                         list[ns].ifindex = 0;
1782                         if (nl_rdma >= 0)
1783                                 list[ns].ifindex = mlx5_nl_ifindex
1784                                         (nl_rdma, list[ns].ibv_dev->name, 1);
1785                         if (!list[ns].ifindex) {
1786                                 /*
1787                                  * No network interface index found for the
1788                                  * specified device, it means there it is not
1789                                  * a representor/master.
1790                                  */
1791                                 continue;
1792                         }
1793                         ret = -1;
1794                         if (nl_route >= 0)
1795                                 ret = mlx5_nl_switch_info
1796                                                (nl_route,
1797                                                 list[ns].ifindex,
1798                                                 &list[ns].info);
1799                         if (ret || (!list[ns].info.representor &&
1800                                     !list[ns].info.master)) {
1801                                 /*
1802                                  * We failed to recognize representors with
1803                                  * Netlink, let's try to perform the task
1804                                  * with sysfs.
1805                                  */
1806                                 ret =  mlx5_sysfs_switch_info
1807                                                 (list[ns].ifindex,
1808                                                  &list[ns].info);
1809                         }
1810                         if (!ret && (list[ns].info.representor ^
1811                                      list[ns].info.master)) {
1812                                 ns++;
1813                         } else if ((nd == 1) &&
1814                                    !list[ns].info.representor &&
1815                                    !list[ns].info.master) {
1816                                 /*
1817                                  * Single IB device with
1818                                  * one physical port and
1819                                  * attached network device.
1820                                  * May be SRIOV is not enabled
1821                                  * or there is no representors.
1822                                  */
1823                                 DRV_LOG(INFO, "no E-Switch support detected");
1824                                 ns++;
1825                                 break;
1826                         }
1827                 }
1828                 if (!ns) {
1829                         DRV_LOG(ERR,
1830                                 "unable to recognize master/representors"
1831                                 " on the multiple IB devices");
1832                         rte_errno = ENOENT;
1833                         ret = -rte_errno;
1834                         goto exit;
1835                 }
1836         }
1837         assert(ns);
1838         /*
1839          * Sort list to probe devices in natural order for users convenience
1840          * (i.e. master first, then representors from lowest to highest ID).
1841          */
1842         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
1843         /* Default configuration. */
1844         dev_config = (struct mlx5_dev_config){
1845                 .hw_padding = 0,
1846                 .mps = MLX5_ARG_UNSET,
1847                 .tx_vec_en = 1,
1848                 .rx_vec_en = 1,
1849                 .txq_inline = MLX5_ARG_UNSET,
1850                 .txqs_inline = MLX5_ARG_UNSET,
1851                 .txqs_vec = MLX5_ARG_UNSET,
1852                 .inline_max_packet_sz = MLX5_ARG_UNSET,
1853                 .vf_nl_en = 1,
1854                 .mr_ext_memseg_en = 1,
1855                 .mprq = {
1856                         .enabled = 0, /* Disabled by default. */
1857                         .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1858                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1859                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1860                 },
1861         };
1862         /* Device specific configuration. */
1863         switch (pci_dev->id.device_id) {
1864         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1865                 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1866                 break;
1867         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1868         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1869         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1870         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1871                 dev_config.vf = 1;
1872                 break;
1873         default:
1874                 break;
1875         }
1876         /* Set architecture-dependent default value if unset. */
1877         if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1878                 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1879         for (i = 0; i != ns; ++i) {
1880                 uint32_t restore;
1881
1882                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1883                                                  &list[i],
1884                                                  dev_config);
1885                 if (!list[i].eth_dev) {
1886                         if (rte_errno != EBUSY && rte_errno != EEXIST)
1887                                 break;
1888                         /* Device is disabled or already spawned. Ignore it. */
1889                         continue;
1890                 }
1891                 restore = list[i].eth_dev->data->dev_flags;
1892                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1893                 /* Restore non-PCI flags cleared by the above call. */
1894                 list[i].eth_dev->data->dev_flags |= restore;
1895                 rte_eth_dev_probing_finish(list[i].eth_dev);
1896         }
1897         if (i != ns) {
1898                 DRV_LOG(ERR,
1899                         "probe of PCI device " PCI_PRI_FMT " aborted after"
1900                         " encountering an error: %s",
1901                         pci_dev->addr.domain, pci_dev->addr.bus,
1902                         pci_dev->addr.devid, pci_dev->addr.function,
1903                         strerror(rte_errno));
1904                 ret = -rte_errno;
1905                 /* Roll back. */
1906                 while (i--) {
1907                         if (!list[i].eth_dev)
1908                                 continue;
1909                         mlx5_dev_close(list[i].eth_dev);
1910                         /* mac_addrs must not be freed because in dev_private */
1911                         list[i].eth_dev->data->mac_addrs = NULL;
1912                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1913                 }
1914                 /* Restore original error. */
1915                 rte_errno = -ret;
1916         } else {
1917                 ret = 0;
1918         }
1919 exit:
1920         /*
1921          * Do the routine cleanup:
1922          * - close opened Netlink sockets
1923          * - free the Infiniband device list
1924          */
1925         if (nl_rdma >= 0)
1926                 close(nl_rdma);
1927         if (nl_route >= 0)
1928                 close(nl_route);
1929         assert(ibv_list);
1930         mlx5_glue->free_device_list(ibv_list);
1931         return ret;
1932 }
1933
1934 /**
1935  * DPDK callback to remove a PCI device.
1936  *
1937  * This function removes all Ethernet devices belong to a given PCI device.
1938  *
1939  * @param[in] pci_dev
1940  *   Pointer to the PCI device.
1941  *
1942  * @return
1943  *   0 on success, the function cannot fail.
1944  */
1945 static int
1946 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1947 {
1948         uint16_t port_id;
1949         struct rte_eth_dev *port;
1950
1951         for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1952                 port = &rte_eth_devices[port_id];
1953                 if (port->state != RTE_ETH_DEV_UNUSED &&
1954                                 port->device == &pci_dev->device)
1955                         rte_eth_dev_close(port_id);
1956         }
1957         return 0;
1958 }
1959
1960 static const struct rte_pci_id mlx5_pci_id_map[] = {
1961         {
1962                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1963                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1964         },
1965         {
1966                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1967                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1968         },
1969         {
1970                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1971                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1972         },
1973         {
1974                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1975                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1976         },
1977         {
1978                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1979                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1980         },
1981         {
1982                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1983                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1984         },
1985         {
1986                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1987                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1988         },
1989         {
1990                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1991                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1992         },
1993         {
1994                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1995                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1996         },
1997         {
1998                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1999                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2000         },
2001         {
2002                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2003                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2004         },
2005         {
2006                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2007                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2008         },
2009         {
2010                 .vendor_id = 0
2011         }
2012 };
2013
2014 static struct rte_pci_driver mlx5_driver = {
2015         .driver = {
2016                 .name = MLX5_DRIVER_NAME
2017         },
2018         .id_table = mlx5_pci_id_map,
2019         .probe = mlx5_pci_probe,
2020         .remove = mlx5_pci_remove,
2021         .dma_map = mlx5_dma_map,
2022         .dma_unmap = mlx5_dma_unmap,
2023         .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
2024                       RTE_PCI_DRV_PROBE_AGAIN),
2025 };
2026
2027 #ifdef RTE_IBVERBS_LINK_DLOPEN
2028
2029 /**
2030  * Suffix RTE_EAL_PMD_PATH with "-glue".
2031  *
2032  * This function performs a sanity check on RTE_EAL_PMD_PATH before
2033  * suffixing its last component.
2034  *
2035  * @param buf[out]
2036  *   Output buffer, should be large enough otherwise NULL is returned.
2037  * @param size
2038  *   Size of @p out.
2039  *
2040  * @return
2041  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
2042  */
2043 static char *
2044 mlx5_glue_path(char *buf, size_t size)
2045 {
2046         static const char *const bad[] = { "/", ".", "..", NULL };
2047         const char *path = RTE_EAL_PMD_PATH;
2048         size_t len = strlen(path);
2049         size_t off;
2050         int i;
2051
2052         while (len && path[len - 1] == '/')
2053                 --len;
2054         for (off = len; off && path[off - 1] != '/'; --off)
2055                 ;
2056         for (i = 0; bad[i]; ++i)
2057                 if (!strncmp(path + off, bad[i], (int)(len - off)))
2058                         goto error;
2059         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
2060         if (i == -1 || (size_t)i >= size)
2061                 goto error;
2062         return buf;
2063 error:
2064         DRV_LOG(ERR,
2065                 "unable to append \"-glue\" to last component of"
2066                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
2067                 " please re-configure DPDK");
2068         return NULL;
2069 }
2070
2071 /**
2072  * Initialization routine for run-time dependency on rdma-core.
2073  */
2074 static int
2075 mlx5_glue_init(void)
2076 {
2077         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
2078         const char *path[] = {
2079                 /*
2080                  * A basic security check is necessary before trusting
2081                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
2082                  */
2083                 (geteuid() == getuid() && getegid() == getgid() ?
2084                  getenv("MLX5_GLUE_PATH") : NULL),
2085                 /*
2086                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
2087                  * variant, otherwise let dlopen() look up libraries on its
2088                  * own.
2089                  */
2090                 (*RTE_EAL_PMD_PATH ?
2091                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
2092         };
2093         unsigned int i = 0;
2094         void *handle = NULL;
2095         void **sym;
2096         const char *dlmsg;
2097
2098         while (!handle && i != RTE_DIM(path)) {
2099                 const char *end;
2100                 size_t len;
2101                 int ret;
2102
2103                 if (!path[i]) {
2104                         ++i;
2105                         continue;
2106                 }
2107                 end = strpbrk(path[i], ":;");
2108                 if (!end)
2109                         end = path[i] + strlen(path[i]);
2110                 len = end - path[i];
2111                 ret = 0;
2112                 do {
2113                         char name[ret + 1];
2114
2115                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
2116                                        (int)len, path[i],
2117                                        (!len || *(end - 1) == '/') ? "" : "/");
2118                         if (ret == -1)
2119                                 break;
2120                         if (sizeof(name) != (size_t)ret + 1)
2121                                 continue;
2122                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
2123                                 name);
2124                         handle = dlopen(name, RTLD_LAZY);
2125                         break;
2126                 } while (1);
2127                 path[i] = end + 1;
2128                 if (!*end)
2129                         ++i;
2130         }
2131         if (!handle) {
2132                 rte_errno = EINVAL;
2133                 dlmsg = dlerror();
2134                 if (dlmsg)
2135                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
2136                 goto glue_error;
2137         }
2138         sym = dlsym(handle, "mlx5_glue");
2139         if (!sym || !*sym) {
2140                 rte_errno = EINVAL;
2141                 dlmsg = dlerror();
2142                 if (dlmsg)
2143                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
2144                 goto glue_error;
2145         }
2146         mlx5_glue = *sym;
2147         return 0;
2148 glue_error:
2149         if (handle)
2150                 dlclose(handle);
2151         DRV_LOG(WARNING,
2152                 "cannot initialize PMD due to missing run-time dependency on"
2153                 " rdma-core libraries (libibverbs, libmlx5)");
2154         return -rte_errno;
2155 }
2156
2157 #endif
2158
2159 /**
2160  * Driver initialization routine.
2161  */
2162 RTE_INIT(rte_mlx5_pmd_init)
2163 {
2164         /* Initialize driver log type. */
2165         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2166         if (mlx5_logtype >= 0)
2167                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2168
2169         /* Build the static tables for Verbs conversion. */
2170         mlx5_set_ptype_table();
2171         mlx5_set_cksum_table();
2172         mlx5_set_swp_types_table();
2173         /*
2174          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
2175          * huge pages. Calling ibv_fork_init() during init allows
2176          * applications to use fork() safely for purposes other than
2177          * using this PMD, which is not supported in forked processes.
2178          */
2179         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
2180         /* Match the size of Rx completion entry to the size of a cacheline. */
2181         if (RTE_CACHE_LINE_SIZE == 128)
2182                 setenv("MLX5_CQE_SIZE", "128", 0);
2183         /*
2184          * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
2185          * cleanup all the Verbs resources even when the device was removed.
2186          */
2187         setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
2188 #ifdef RTE_IBVERBS_LINK_DLOPEN
2189         if (mlx5_glue_init())
2190                 return;
2191         assert(mlx5_glue);
2192 #endif
2193 #ifndef NDEBUG
2194         /* Glue structure must not contain any NULL pointers. */
2195         {
2196                 unsigned int i;
2197
2198                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
2199                         assert(((const void *const *)mlx5_glue)[i]);
2200         }
2201 #endif
2202         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
2203                 DRV_LOG(ERR,
2204                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
2205                         mlx5_glue->version, MLX5_GLUE_VERSION);
2206                 return;
2207         }
2208         mlx5_glue->fork_init();
2209         rte_pci_register(&mlx5_driver);
2210 }
2211
2212 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2213 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2214 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");