1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable Multi-Packet Rx queue. */
58 #define MLX5_RX_MPRQ_EN "mprq_en"
60 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
61 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
78 /* Device parameter to enable multi-packet send WQEs. */
79 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
81 /* Device parameter to include 2 dsegs in the title WQEBB. */
82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
84 /* Device parameter to limit the size of inlining packet. */
85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
87 /* Device parameter to enable hardware Tx vector. */
88 #define MLX5_TX_VEC_EN "tx_vec_en"
90 /* Device parameter to enable hardware Rx vector. */
91 #define MLX5_RX_VEC_EN "rx_vec_en"
93 /* Allow L3 VXLAN flow creation. */
94 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
96 /* Activate DV flow steering. */
97 #define MLX5_DV_FLOW_EN "dv_flow_en"
99 /* Activate Netlink support in VF mode. */
100 #define MLX5_VF_NL_EN "vf_nl_en"
102 /* Select port representors to instantiate. */
103 #define MLX5_REPRESENTOR "representor"
105 #ifndef HAVE_IBV_MLX5_MOD_MPW
106 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
107 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
110 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
111 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
114 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
116 /* Shared memory between primary and secondary processes. */
117 struct mlx5_shared_data *mlx5_shared_data;
119 /* Spinlock for mlx5_shared_data allocation. */
120 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
122 /** Driver-specific log messages type. */
126 * Prepare shared data between primary and secondary process.
129 mlx5_prepare_shared_data(void)
131 const struct rte_memzone *mz;
133 rte_spinlock_lock(&mlx5_shared_data_lock);
134 if (mlx5_shared_data == NULL) {
135 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
136 /* Allocate shared memory. */
137 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
138 sizeof(*mlx5_shared_data),
141 /* Lookup allocated shared memory. */
142 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
145 rte_panic("Cannot allocate mlx5 shared data\n");
146 mlx5_shared_data = mz->addr;
147 /* Initialize shared data. */
148 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
149 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
150 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
152 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
153 mlx5_mr_mem_event_cb, NULL);
155 rte_spinlock_unlock(&mlx5_shared_data_lock);
159 * Retrieve integer value from environment variable.
162 * Environment variable name.
165 * Integer value, 0 if the variable is not set.
168 mlx5_getenv_int(const char *name)
170 const char *val = getenv(name);
178 * Verbs callback to allocate a memory. This function should allocate the space
179 * according to the size provided residing inside a huge page.
180 * Please note that all allocation must respect the alignment from libmlx5
181 * (i.e. currently sysconf(_SC_PAGESIZE)).
184 * The size in bytes of the memory to allocate.
186 * A pointer to the callback data.
189 * Allocated buffer, NULL otherwise and rte_errno is set.
192 mlx5_alloc_verbs_buf(size_t size, void *data)
194 struct priv *priv = data;
196 size_t alignment = sysconf(_SC_PAGESIZE);
197 unsigned int socket = SOCKET_ID_ANY;
199 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
200 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
202 socket = ctrl->socket;
203 } else if (priv->verbs_alloc_ctx.type ==
204 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
205 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
207 socket = ctrl->socket;
209 assert(data != NULL);
210 ret = rte_malloc_socket(__func__, size, alignment, socket);
217 * Verbs callback to free a memory.
220 * A pointer to the memory to free.
222 * A pointer to the callback data.
225 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
227 assert(data != NULL);
232 * DPDK callback to close the device.
234 * Destroy all queues and objects, free memory.
237 * Pointer to Ethernet device structure.
240 mlx5_dev_close(struct rte_eth_dev *dev)
242 struct priv *priv = dev->data->dev_private;
246 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
248 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
249 /* In case mlx5_dev_stop() has not been called. */
250 mlx5_dev_interrupt_handler_uninstall(dev);
251 mlx5_traffic_disable(dev);
252 mlx5_flow_flush(dev, NULL);
253 /* Prevent crashes when queues are still in use. */
254 dev->rx_pkt_burst = removed_rx_burst;
255 dev->tx_pkt_burst = removed_tx_burst;
256 if (priv->rxqs != NULL) {
257 /* XXX race condition if mlx5_rx_burst() is still running. */
259 for (i = 0; (i != priv->rxqs_n); ++i)
260 mlx5_rxq_release(dev, i);
264 if (priv->txqs != NULL) {
265 /* XXX race condition if mlx5_tx_burst() is still running. */
267 for (i = 0; (i != priv->txqs_n); ++i)
268 mlx5_txq_release(dev, i);
272 mlx5_mprq_free_mp(dev);
273 mlx5_mr_release(dev);
274 if (priv->pd != NULL) {
275 assert(priv->ctx != NULL);
276 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
277 claim_zero(mlx5_glue->close_device(priv->ctx));
279 assert(priv->ctx == NULL);
280 if (priv->rss_conf.rss_key != NULL)
281 rte_free(priv->rss_conf.rss_key);
282 if (priv->reta_idx != NULL)
283 rte_free(priv->reta_idx);
284 if (priv->primary_socket)
285 mlx5_socket_uninit(dev);
287 mlx5_nl_mac_addr_flush(dev);
288 if (priv->nl_socket_route >= 0)
289 close(priv->nl_socket_route);
290 if (priv->nl_socket_rdma >= 0)
291 close(priv->nl_socket_rdma);
292 if (priv->tcf_context)
293 mlx5_flow_tcf_context_destroy(priv->tcf_context);
294 ret = mlx5_hrxq_ibv_verify(dev);
296 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
298 ret = mlx5_ind_table_ibv_verify(dev);
300 DRV_LOG(WARNING, "port %u some indirection table still remain",
302 ret = mlx5_rxq_ibv_verify(dev);
304 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
306 ret = mlx5_rxq_verify(dev);
308 DRV_LOG(WARNING, "port %u some Rx queues still remain",
310 ret = mlx5_txq_ibv_verify(dev);
312 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
314 ret = mlx5_txq_verify(dev);
316 DRV_LOG(WARNING, "port %u some Tx queues still remain",
318 ret = mlx5_flow_verify(dev);
320 DRV_LOG(WARNING, "port %u some flows still remain",
322 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
324 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
327 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
330 rte_eth_devices[port_id[i]].data->dev_private;
333 opriv->domain_id != priv->domain_id ||
334 &rte_eth_devices[port_id[i]] == dev)
339 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
341 memset(priv, 0, sizeof(*priv));
342 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
344 * flag to rte_eth_dev_close() that it should release the port resources
345 * (calling rte_eth_dev_release_port()) in addition to closing it.
347 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
349 * Reset mac_addrs to NULL such that it is not freed as part of
350 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
351 * it is freed when dev_private is freed.
353 dev->data->mac_addrs = NULL;
356 const struct eth_dev_ops mlx5_dev_ops = {
357 .dev_configure = mlx5_dev_configure,
358 .dev_start = mlx5_dev_start,
359 .dev_stop = mlx5_dev_stop,
360 .dev_set_link_down = mlx5_set_link_down,
361 .dev_set_link_up = mlx5_set_link_up,
362 .dev_close = mlx5_dev_close,
363 .promiscuous_enable = mlx5_promiscuous_enable,
364 .promiscuous_disable = mlx5_promiscuous_disable,
365 .allmulticast_enable = mlx5_allmulticast_enable,
366 .allmulticast_disable = mlx5_allmulticast_disable,
367 .link_update = mlx5_link_update,
368 .stats_get = mlx5_stats_get,
369 .stats_reset = mlx5_stats_reset,
370 .xstats_get = mlx5_xstats_get,
371 .xstats_reset = mlx5_xstats_reset,
372 .xstats_get_names = mlx5_xstats_get_names,
373 .dev_infos_get = mlx5_dev_infos_get,
374 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
375 .vlan_filter_set = mlx5_vlan_filter_set,
376 .rx_queue_setup = mlx5_rx_queue_setup,
377 .tx_queue_setup = mlx5_tx_queue_setup,
378 .rx_queue_release = mlx5_rx_queue_release,
379 .tx_queue_release = mlx5_tx_queue_release,
380 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
381 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
382 .mac_addr_remove = mlx5_mac_addr_remove,
383 .mac_addr_add = mlx5_mac_addr_add,
384 .mac_addr_set = mlx5_mac_addr_set,
385 .set_mc_addr_list = mlx5_set_mc_addr_list,
386 .mtu_set = mlx5_dev_set_mtu,
387 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
388 .vlan_offload_set = mlx5_vlan_offload_set,
389 .reta_update = mlx5_dev_rss_reta_update,
390 .reta_query = mlx5_dev_rss_reta_query,
391 .rss_hash_update = mlx5_rss_hash_update,
392 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
393 .filter_ctrl = mlx5_dev_filter_ctrl,
394 .rx_descriptor_status = mlx5_rx_descriptor_status,
395 .tx_descriptor_status = mlx5_tx_descriptor_status,
396 .rx_queue_intr_enable = mlx5_rx_intr_enable,
397 .rx_queue_intr_disable = mlx5_rx_intr_disable,
398 .is_removed = mlx5_is_removed,
401 static const struct eth_dev_ops mlx5_dev_sec_ops = {
402 .stats_get = mlx5_stats_get,
403 .stats_reset = mlx5_stats_reset,
404 .xstats_get = mlx5_xstats_get,
405 .xstats_reset = mlx5_xstats_reset,
406 .xstats_get_names = mlx5_xstats_get_names,
407 .dev_infos_get = mlx5_dev_infos_get,
408 .rx_descriptor_status = mlx5_rx_descriptor_status,
409 .tx_descriptor_status = mlx5_tx_descriptor_status,
412 /* Available operators in flow isolated mode. */
413 const struct eth_dev_ops mlx5_dev_ops_isolate = {
414 .dev_configure = mlx5_dev_configure,
415 .dev_start = mlx5_dev_start,
416 .dev_stop = mlx5_dev_stop,
417 .dev_set_link_down = mlx5_set_link_down,
418 .dev_set_link_up = mlx5_set_link_up,
419 .dev_close = mlx5_dev_close,
420 .promiscuous_enable = mlx5_promiscuous_enable,
421 .promiscuous_disable = mlx5_promiscuous_disable,
422 .allmulticast_enable = mlx5_allmulticast_enable,
423 .allmulticast_disable = mlx5_allmulticast_disable,
424 .link_update = mlx5_link_update,
425 .stats_get = mlx5_stats_get,
426 .stats_reset = mlx5_stats_reset,
427 .xstats_get = mlx5_xstats_get,
428 .xstats_reset = mlx5_xstats_reset,
429 .xstats_get_names = mlx5_xstats_get_names,
430 .dev_infos_get = mlx5_dev_infos_get,
431 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
432 .vlan_filter_set = mlx5_vlan_filter_set,
433 .rx_queue_setup = mlx5_rx_queue_setup,
434 .tx_queue_setup = mlx5_tx_queue_setup,
435 .rx_queue_release = mlx5_rx_queue_release,
436 .tx_queue_release = mlx5_tx_queue_release,
437 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
438 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
439 .mac_addr_remove = mlx5_mac_addr_remove,
440 .mac_addr_add = mlx5_mac_addr_add,
441 .mac_addr_set = mlx5_mac_addr_set,
442 .set_mc_addr_list = mlx5_set_mc_addr_list,
443 .mtu_set = mlx5_dev_set_mtu,
444 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
445 .vlan_offload_set = mlx5_vlan_offload_set,
446 .filter_ctrl = mlx5_dev_filter_ctrl,
447 .rx_descriptor_status = mlx5_rx_descriptor_status,
448 .tx_descriptor_status = mlx5_tx_descriptor_status,
449 .rx_queue_intr_enable = mlx5_rx_intr_enable,
450 .rx_queue_intr_disable = mlx5_rx_intr_disable,
451 .is_removed = mlx5_is_removed,
455 * Verify and store value for device argument.
458 * Key argument to verify.
460 * Value associated with key.
465 * 0 on success, a negative errno value otherwise and rte_errno is set.
468 mlx5_args_check(const char *key, const char *val, void *opaque)
470 struct mlx5_dev_config *config = opaque;
473 /* No-op, port representors are processed in mlx5_dev_spawn(). */
474 if (!strcmp(MLX5_REPRESENTOR, key))
477 tmp = strtoul(val, NULL, 0);
480 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
483 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
484 config->cqe_comp = !!tmp;
485 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
486 config->cqe_pad = !!tmp;
487 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
488 config->mprq.enabled = !!tmp;
489 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
490 config->mprq.stride_num_n = tmp;
491 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
492 config->mprq.max_memcpy_len = tmp;
493 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
494 config->mprq.min_rxqs_num = tmp;
495 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
496 config->txq_inline = tmp;
497 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
498 config->txqs_inline = tmp;
499 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
501 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
502 config->mpw_hdr_dseg = !!tmp;
503 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
504 config->inline_max_packet_sz = tmp;
505 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
506 config->tx_vec_en = !!tmp;
507 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
508 config->rx_vec_en = !!tmp;
509 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
510 config->l3_vxlan_en = !!tmp;
511 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
512 config->vf_nl_en = !!tmp;
513 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
514 config->dv_flow_en = !!tmp;
516 DRV_LOG(WARNING, "%s: unknown parameter", key);
524 * Parse device parameters.
527 * Pointer to device configuration structure.
529 * Device arguments structure.
532 * 0 on success, a negative errno value otherwise and rte_errno is set.
535 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
537 const char **params = (const char *[]){
538 MLX5_RXQ_CQE_COMP_EN,
541 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
542 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
545 MLX5_TXQS_MIN_INLINE,
547 MLX5_TXQ_MPW_HDR_DSEG_EN,
548 MLX5_TXQ_MAX_INLINE_LEN,
557 struct rte_kvargs *kvlist;
563 /* Following UGLY cast is done to pass checkpatch. */
564 kvlist = rte_kvargs_parse(devargs->args, params);
567 /* Process parameters. */
568 for (i = 0; (params[i] != NULL); ++i) {
569 if (rte_kvargs_count(kvlist, params[i])) {
570 ret = rte_kvargs_process(kvlist, params[i],
571 mlx5_args_check, config);
574 rte_kvargs_free(kvlist);
579 rte_kvargs_free(kvlist);
583 static struct rte_pci_driver mlx5_driver;
586 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
587 * local resource used by both primary and secondary to avoid duplicate
589 * The space has to be available on both primary and secondary process,
590 * TXQ UAR maps to this area using fixed mmap w/o double check.
592 static void *uar_base;
595 find_lower_va_bound(const struct rte_memseg_list *msl,
596 const struct rte_memseg *ms, void *arg)
605 *addr = RTE_MIN(*addr, ms->addr);
611 * Reserve UAR address space for primary process.
614 * Pointer to Ethernet device.
617 * 0 on success, a negative errno value otherwise and rte_errno is set.
620 mlx5_uar_init_primary(struct rte_eth_dev *dev)
622 struct priv *priv = dev->data->dev_private;
623 void *addr = (void *)0;
625 if (uar_base) { /* UAR address space mapped. */
626 priv->uar_base = uar_base;
629 /* find out lower bound of hugepage segments */
630 rte_memseg_walk(find_lower_va_bound, &addr);
632 /* keep distance to hugepages to minimize potential conflicts. */
633 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
634 /* anonymous mmap, no real memory consumption. */
635 addr = mmap(addr, MLX5_UAR_SIZE,
636 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
637 if (addr == MAP_FAILED) {
639 "port %u failed to reserve UAR address space, please"
640 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
645 /* Accept either same addr or a new addr returned from mmap if target
648 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
649 dev->data->port_id, addr);
650 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
651 uar_base = addr; /* process local, don't reserve again. */
656 * Reserve UAR address space for secondary process, align with
660 * Pointer to Ethernet device.
663 * 0 on success, a negative errno value otherwise and rte_errno is set.
666 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
668 struct priv *priv = dev->data->dev_private;
671 assert(priv->uar_base);
672 if (uar_base) { /* already reserved. */
673 assert(uar_base == priv->uar_base);
676 /* anonymous mmap, no real memory consumption. */
677 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
678 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
679 if (addr == MAP_FAILED) {
680 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
681 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
685 if (priv->uar_base != addr) {
687 "port %u UAR address %p size %llu occupied, please"
688 " adjust MLX5_UAR_OFFSET or try EAL parameter"
690 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
694 uar_base = addr; /* process local, don't reserve again */
695 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
696 dev->data->port_id, addr);
701 * Spawn an Ethernet device from Verbs information.
704 * Backing DPDK device.
708 * Device configuration parameters.
709 * @param[in] switch_info
710 * Switch properties of Ethernet device.
713 * A valid Ethernet device object on success, NULL otherwise and rte_errno
714 * is set. The following errors are defined:
716 * EBUSY: device is not supposed to be spawned.
717 * EEXIST: device is already spawned
719 static struct rte_eth_dev *
720 mlx5_dev_spawn(struct rte_device *dpdk_dev,
721 struct ibv_device *ibv_dev,
722 struct mlx5_dev_config config,
723 const struct mlx5_switch_info *switch_info)
725 struct ibv_context *ctx;
726 struct ibv_device_attr_ex attr;
727 struct ibv_port_attr port_attr;
728 struct ibv_pd *pd = NULL;
729 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
730 struct rte_eth_dev *eth_dev = NULL;
731 struct priv *priv = NULL;
734 unsigned int cqe_comp;
735 unsigned int cqe_pad = 0;
736 unsigned int tunnel_en = 0;
737 unsigned int mpls_en = 0;
738 unsigned int swp = 0;
739 unsigned int mprq = 0;
740 unsigned int mprq_min_stride_size_n = 0;
741 unsigned int mprq_max_stride_size_n = 0;
742 unsigned int mprq_min_stride_num_n = 0;
743 unsigned int mprq_max_stride_num_n = 0;
744 struct ether_addr mac;
745 char name[RTE_ETH_NAME_MAX_LEN];
746 int own_domain_id = 0;
750 /* Determine if this port representor is supposed to be spawned. */
751 if (switch_info->representor && dpdk_dev->devargs) {
752 struct rte_eth_devargs eth_da;
754 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
757 DRV_LOG(ERR, "failed to process device arguments: %s",
758 strerror(rte_errno));
761 for (i = 0; i < eth_da.nb_representor_ports; ++i)
762 if (eth_da.representor_ports[i] ==
763 (uint16_t)switch_info->port_name)
765 if (i == eth_da.nb_representor_ports) {
770 /* Build device name. */
771 if (!switch_info->representor)
772 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
774 snprintf(name, sizeof(name), "%s_representor_%u",
775 dpdk_dev->name, switch_info->port_name);
776 /* check if the device is already spawned */
777 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
781 /* Prepare shared data between primary and secondary process. */
782 mlx5_prepare_shared_data();
784 ctx = mlx5_glue->open_device(ibv_dev);
786 rte_errno = errno ? errno : ENODEV;
789 #ifdef HAVE_IBV_MLX5_MOD_SWP
790 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
793 * Multi-packet send is supported by ConnectX-4 Lx PF as well
794 * as all ConnectX-5 devices.
796 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
797 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
799 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
800 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
802 mlx5_glue->dv_query_device(ctx, &dv_attr);
803 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
804 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
805 DRV_LOG(DEBUG, "enhanced MPW is supported");
806 mps = MLX5_MPW_ENHANCED;
808 DRV_LOG(DEBUG, "MPW is supported");
812 DRV_LOG(DEBUG, "MPW isn't supported");
813 mps = MLX5_MPW_DISABLED;
815 #ifdef HAVE_IBV_MLX5_MOD_SWP
816 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
817 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
818 DRV_LOG(DEBUG, "SWP support: %u", swp);
821 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
822 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
823 struct mlx5dv_striding_rq_caps mprq_caps =
824 dv_attr.striding_rq_caps;
826 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
827 mprq_caps.min_single_stride_log_num_of_bytes);
828 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
829 mprq_caps.max_single_stride_log_num_of_bytes);
830 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
831 mprq_caps.min_single_wqe_log_num_of_strides);
832 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
833 mprq_caps.max_single_wqe_log_num_of_strides);
834 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
835 mprq_caps.supported_qpts);
836 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
838 mprq_min_stride_size_n =
839 mprq_caps.min_single_stride_log_num_of_bytes;
840 mprq_max_stride_size_n =
841 mprq_caps.max_single_stride_log_num_of_bytes;
842 mprq_min_stride_num_n =
843 mprq_caps.min_single_wqe_log_num_of_strides;
844 mprq_max_stride_num_n =
845 mprq_caps.max_single_wqe_log_num_of_strides;
846 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
847 mprq_min_stride_num_n);
850 if (RTE_CACHE_LINE_SIZE == 128 &&
851 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
855 config.cqe_comp = cqe_comp;
856 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
857 /* Whether device supports 128B Rx CQE padding. */
858 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
859 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
861 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
862 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
863 tunnel_en = ((dv_attr.tunnel_offloads_caps &
864 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
865 (dv_attr.tunnel_offloads_caps &
866 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
868 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
869 tunnel_en ? "" : "not ");
872 "tunnel offloading disabled due to old OFED/rdma-core version");
874 config.tunnel_en = tunnel_en;
875 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
876 mpls_en = ((dv_attr.tunnel_offloads_caps &
877 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
878 (dv_attr.tunnel_offloads_caps &
879 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
880 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
881 mpls_en ? "" : "not ");
883 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
884 " old OFED/rdma-core version or firmware configuration");
886 config.mpls_en = mpls_en;
887 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
889 DEBUG("ibv_query_device_ex() failed");
892 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
893 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
894 eth_dev = rte_eth_dev_attach_secondary(name);
895 if (eth_dev == NULL) {
896 DRV_LOG(ERR, "can not attach rte ethdev");
901 eth_dev->device = dpdk_dev;
902 eth_dev->dev_ops = &mlx5_dev_sec_ops;
903 err = mlx5_uar_init_secondary(eth_dev);
908 /* Receive command fd from primary process */
909 err = mlx5_socket_connect(eth_dev);
914 /* Remap UAR for Tx queues. */
915 err = mlx5_tx_uar_remap(eth_dev, err);
921 * Ethdev pointer is still required as input since
922 * the primary device is not accessible from the
925 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
926 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
927 claim_zero(mlx5_glue->close_device(ctx));
930 /* Check port status. */
931 err = mlx5_glue->query_port(ctx, 1, &port_attr);
933 DRV_LOG(ERR, "port query failed: %s", strerror(err));
936 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
937 DRV_LOG(ERR, "port is not configured in Ethernet mode");
941 if (port_attr.state != IBV_PORT_ACTIVE)
942 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
943 mlx5_glue->port_state_str(port_attr.state),
945 /* Allocate protection domain. */
946 pd = mlx5_glue->alloc_pd(ctx);
948 DRV_LOG(ERR, "PD allocation failure");
952 priv = rte_zmalloc("ethdev private structure",
954 RTE_CACHE_LINE_SIZE);
956 DRV_LOG(ERR, "priv allocation failure");
961 strncpy(priv->ibdev_name, priv->ctx->device->name,
962 sizeof(priv->ibdev_name));
963 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
964 sizeof(priv->ibdev_path));
965 priv->device_attr = attr;
967 priv->mtu = ETHER_MTU;
969 /* Initialize UAR access locks for 32bit implementations. */
970 rte_spinlock_init(&priv->uar_lock_cq);
971 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
972 rte_spinlock_init(&priv->uar_lock[i]);
974 /* Some internal functions rely on Netlink sockets, open them now. */
975 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
976 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
978 priv->representor = !!switch_info->representor;
979 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
980 priv->representor_id =
981 switch_info->representor ? switch_info->port_name : -1;
983 * Look for sibling devices in order to reuse their switch domain
984 * if any, otherwise allocate one.
986 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
990 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
992 const struct priv *opriv =
993 rte_eth_devices[port_id[i]].data->dev_private;
997 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
999 priv->domain_id = opriv->domain_id;
1003 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1004 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1007 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1008 strerror(rte_errno));
1013 err = mlx5_args(&config, dpdk_dev->devargs);
1016 DRV_LOG(ERR, "failed to process device arguments: %s",
1017 strerror(rte_errno));
1020 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1021 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1022 (config.hw_csum ? "" : "not "));
1023 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1024 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1025 DRV_LOG(DEBUG, "counters are not supported");
1027 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1028 if (config.dv_flow_en) {
1029 DRV_LOG(WARNING, "DV flow is not supported");
1030 config.dv_flow_en = 0;
1033 config.ind_table_max_size =
1034 attr.rss_caps.max_rwq_indirection_table_size;
1036 * Remove this check once DPDK supports larger/variable
1037 * indirection tables.
1039 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1040 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1041 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1042 config.ind_table_max_size);
1043 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1044 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1045 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1046 (config.hw_vlan_strip ? "" : "not "));
1047 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1048 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1049 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1050 (config.hw_fcs_strip ? "" : "not "));
1051 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1052 config.hw_padding = !!attr.rx_pad_end_addr_align;
1054 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1055 (config.hw_padding ? "" : "not "));
1056 config.tso = (attr.tso_caps.max_tso > 0 &&
1057 (attr.tso_caps.supported_qpts &
1058 (1 << IBV_QPT_RAW_PACKET)));
1060 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1062 * MPW is disabled by default, while the Enhanced MPW is enabled
1065 if (config.mps == MLX5_ARG_UNSET)
1066 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1069 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1070 DRV_LOG(INFO, "%sMPS is %s",
1071 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1072 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1073 if (config.cqe_comp && !cqe_comp) {
1074 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1075 config.cqe_comp = 0;
1077 if (config.cqe_pad && !cqe_pad) {
1078 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1080 } else if (config.cqe_pad) {
1081 DRV_LOG(INFO, "Rx CQE padding is enabled");
1083 if (config.mprq.enabled && mprq) {
1084 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1085 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1086 config.mprq.stride_num_n =
1087 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1088 mprq_min_stride_num_n);
1090 "the number of strides"
1091 " for Multi-Packet RQ is out of range,"
1092 " setting default value (%u)",
1093 1 << config.mprq.stride_num_n);
1095 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1096 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1097 } else if (config.mprq.enabled && !mprq) {
1098 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1099 config.mprq.enabled = 0;
1101 eth_dev = rte_eth_dev_allocate(name);
1102 if (eth_dev == NULL) {
1103 DRV_LOG(ERR, "can not allocate rte ethdev");
1107 if (priv->representor) {
1108 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1109 eth_dev->data->representor_id = priv->representor_id;
1111 eth_dev->data->dev_private = priv;
1112 priv->dev_data = eth_dev->data;
1113 eth_dev->data->mac_addrs = priv->mac;
1114 eth_dev->device = dpdk_dev;
1115 err = mlx5_uar_init_primary(eth_dev);
1120 /* Configure the first MAC address by default. */
1121 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1123 "port %u cannot get MAC address, is mlx5_en"
1124 " loaded? (errno: %s)",
1125 eth_dev->data->port_id, strerror(rte_errno));
1130 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1131 eth_dev->data->port_id,
1132 mac.addr_bytes[0], mac.addr_bytes[1],
1133 mac.addr_bytes[2], mac.addr_bytes[3],
1134 mac.addr_bytes[4], mac.addr_bytes[5]);
1137 char ifname[IF_NAMESIZE];
1139 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1140 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1141 eth_dev->data->port_id, ifname);
1143 DRV_LOG(DEBUG, "port %u ifname is unknown",
1144 eth_dev->data->port_id);
1147 /* Get actual MTU if possible. */
1148 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1153 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1155 /* Initialize burst functions to prevent crashes before link-up. */
1156 eth_dev->rx_pkt_burst = removed_rx_burst;
1157 eth_dev->tx_pkt_burst = removed_tx_burst;
1158 eth_dev->dev_ops = &mlx5_dev_ops;
1159 /* Register MAC address. */
1160 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1161 if (config.vf && config.vf_nl_en)
1162 mlx5_nl_mac_addr_sync(eth_dev);
1163 priv->tcf_context = mlx5_flow_tcf_context_create();
1164 if (!priv->tcf_context) {
1167 "flow rules relying on switch offloads will not be"
1168 " supported: cannot open libmnl socket: %s",
1169 strerror(rte_errno));
1171 struct rte_flow_error error;
1172 unsigned int ifindex = mlx5_ifindex(eth_dev);
1177 "cannot retrieve network interface index";
1179 err = mlx5_flow_tcf_init(priv->tcf_context,
1184 "flow rules relying on switch offloads will"
1185 " not be supported: %s: %s",
1186 error.message, strerror(rte_errno));
1187 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1188 priv->tcf_context = NULL;
1191 TAILQ_INIT(&priv->flows);
1192 TAILQ_INIT(&priv->ctrl_flows);
1193 /* Hint libmlx5 to use PMD allocator for data plane resources */
1194 struct mlx5dv_ctx_allocators alctr = {
1195 .alloc = &mlx5_alloc_verbs_buf,
1196 .free = &mlx5_free_verbs_buf,
1199 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1200 (void *)((uintptr_t)&alctr));
1201 /* Bring Ethernet device up. */
1202 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1203 eth_dev->data->port_id);
1204 mlx5_set_link_up(eth_dev);
1206 * Even though the interrupt handler is not installed yet,
1207 * interrupts will still trigger on the asyn_fd from
1208 * Verbs context returned by ibv_open_device().
1210 mlx5_link_update(eth_dev, 0);
1211 /* Store device configuration on private structure. */
1212 priv->config = config;
1213 /* Supported Verbs flow priority number detection. */
1214 err = mlx5_flow_discover_priorities(eth_dev);
1217 priv->config.flow_prio = err;
1219 * Once the device is added to the list of memory event
1220 * callback, its global MR cache table cannot be expanded
1221 * on the fly because of deadlock. If it overflows, lookup
1222 * should be done by searching MR list linearly, which is slow.
1224 err = mlx5_mr_btree_init(&priv->mr.cache,
1225 MLX5_MR_BTREE_CACHE_N * 2,
1226 eth_dev->device->numa_node);
1231 /* Add device to memory callback list. */
1232 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1233 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1234 priv, mem_event_cb);
1235 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1239 if (priv->nl_socket_route >= 0)
1240 close(priv->nl_socket_route);
1241 if (priv->nl_socket_rdma >= 0)
1242 close(priv->nl_socket_rdma);
1243 if (priv->tcf_context)
1244 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1246 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1248 if (eth_dev != NULL)
1249 eth_dev->data->dev_private = NULL;
1252 claim_zero(mlx5_glue->dealloc_pd(pd));
1253 if (eth_dev != NULL) {
1254 /* mac_addrs must not be freed alone because part of dev_private */
1255 eth_dev->data->mac_addrs = NULL;
1256 rte_eth_dev_release_port(eth_dev);
1259 claim_zero(mlx5_glue->close_device(ctx));
1265 /** Data associated with devices to spawn. */
1266 struct mlx5_dev_spawn_data {
1267 unsigned int ifindex; /**< Network interface index. */
1268 struct mlx5_switch_info info; /**< Switch information. */
1269 struct ibv_device *ibv_dev; /**< Associated IB device. */
1270 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1274 * Comparison callback to sort device data.
1276 * This is meant to be used with qsort().
1279 * Pointer to pointer to first data object.
1281 * Pointer to pointer to second data object.
1284 * 0 if both objects are equal, less than 0 if the first argument is less
1285 * than the second, greater than 0 otherwise.
1288 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1290 const struct mlx5_switch_info *si_a =
1291 &((const struct mlx5_dev_spawn_data *)a)->info;
1292 const struct mlx5_switch_info *si_b =
1293 &((const struct mlx5_dev_spawn_data *)b)->info;
1296 /* Master device first. */
1297 ret = si_b->master - si_a->master;
1300 /* Then representor devices. */
1301 ret = si_b->representor - si_a->representor;
1304 /* Unidentified devices come last in no specific order. */
1305 if (!si_a->representor)
1307 /* Order representors by name. */
1308 return si_a->port_name - si_b->port_name;
1312 * DPDK callback to register a PCI device.
1314 * This function spawns Ethernet devices out of a given PCI device.
1316 * @param[in] pci_drv
1317 * PCI driver structure (mlx5_driver).
1318 * @param[in] pci_dev
1319 * PCI device information.
1322 * 0 on success, a negative errno value otherwise and rte_errno is set.
1325 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1326 struct rte_pci_device *pci_dev)
1328 struct ibv_device **ibv_list;
1330 struct mlx5_dev_config dev_config;
1333 assert(pci_drv == &mlx5_driver);
1335 ibv_list = mlx5_glue->get_device_list(&ret);
1337 rte_errno = errno ? errno : ENOSYS;
1338 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1342 struct ibv_device *ibv_match[ret + 1];
1345 struct rte_pci_addr pci_addr;
1347 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1348 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1350 if (pci_dev->addr.domain != pci_addr.domain ||
1351 pci_dev->addr.bus != pci_addr.bus ||
1352 pci_dev->addr.devid != pci_addr.devid ||
1353 pci_dev->addr.function != pci_addr.function)
1355 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1356 ibv_list[ret]->name);
1357 ibv_match[n++] = ibv_list[ret];
1359 ibv_match[n] = NULL;
1361 struct mlx5_dev_spawn_data list[n];
1362 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1363 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1368 * The existence of several matching entries (n > 1) means port
1369 * representors have been instantiated. No existing Verbs call nor
1370 * /sys entries can tell them apart, this can only be done through
1371 * Netlink calls assuming kernel drivers are recent enough to
1374 * In the event of identification failure through Netlink, try again
1375 * through sysfs, then either:
1377 * 1. No device matches (n == 0), complain and bail out.
1378 * 2. A single IB device matches (n == 1) and is not a representor,
1379 * assume no switch support.
1380 * 3. Otherwise no safe assumptions can be made; complain louder and
1383 for (i = 0; i != n; ++i) {
1384 list[i].ibv_dev = ibv_match[i];
1385 list[i].eth_dev = NULL;
1387 list[i].ifindex = 0;
1389 list[i].ifindex = mlx5_nl_ifindex
1390 (nl_rdma, list[i].ibv_dev->name);
1393 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1395 ((!list[i].info.representor && !list[i].info.master) &&
1396 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1397 list[i].ifindex = 0;
1398 memset(&list[i].info, 0, sizeof(list[i].info));
1406 /* Count unidentified devices. */
1407 for (u = 0, i = 0; i != n; ++i)
1408 if (!list[i].info.master && !list[i].info.representor)
1411 if (n == 1 && u == 1) {
1413 DRV_LOG(INFO, "no switch support detected");
1417 "unable to tell which of the matching devices"
1418 " is the master (lack of kernel support?)");
1423 * Sort list to probe devices in natural order for users convenience
1424 * (i.e. master first, then representors from lowest to highest ID).
1427 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1428 /* Default configuration. */
1429 dev_config = (struct mlx5_dev_config){
1430 .mps = MLX5_ARG_UNSET,
1433 .txq_inline = MLX5_ARG_UNSET,
1434 .txqs_inline = MLX5_ARG_UNSET,
1435 .inline_max_packet_sz = MLX5_ARG_UNSET,
1438 .enabled = 0, /* Disabled by default. */
1439 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1440 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1441 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1444 /* Device speicific configuration. */
1445 switch (pci_dev->id.device_id) {
1446 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1447 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1448 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1449 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1455 for (i = 0; i != n; ++i) {
1458 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1459 list[i].ibv_dev, dev_config,
1461 if (!list[i].eth_dev) {
1462 if (rte_errno != EBUSY && rte_errno != EEXIST)
1464 /* Device is disabled or already spawned. Ignore it. */
1467 restore = list[i].eth_dev->data->dev_flags;
1468 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1469 /* Restore non-PCI flags cleared by the above call. */
1470 list[i].eth_dev->data->dev_flags |= restore;
1471 rte_eth_dev_probing_finish(list[i].eth_dev);
1473 mlx5_glue->free_device_list(ibv_list);
1476 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1477 " are kernel drivers loaded?",
1478 pci_dev->addr.domain, pci_dev->addr.bus,
1479 pci_dev->addr.devid, pci_dev->addr.function);
1482 } else if (i != n) {
1484 "probe of PCI device " PCI_PRI_FMT " aborted after"
1485 " encountering an error: %s",
1486 pci_dev->addr.domain, pci_dev->addr.bus,
1487 pci_dev->addr.devid, pci_dev->addr.function,
1488 strerror(rte_errno));
1492 if (!list[i].eth_dev)
1494 mlx5_dev_close(list[i].eth_dev);
1495 /* mac_addrs must not be freed because in dev_private */
1496 list[i].eth_dev->data->mac_addrs = NULL;
1497 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1499 /* Restore original error. */
1508 * DPDK callback to remove a PCI device.
1510 * This function removes all Ethernet devices belong to a given PCI device.
1512 * @param[in] pci_dev
1513 * Pointer to the PCI device.
1516 * 0 on success, the function cannot fail.
1519 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1522 struct rte_eth_dev *port;
1524 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1525 port = &rte_eth_devices[port_id];
1526 if (port->state != RTE_ETH_DEV_UNUSED &&
1527 port->device == &pci_dev->device)
1528 rte_eth_dev_close(port_id);
1533 static const struct rte_pci_id mlx5_pci_id_map[] = {
1535 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1536 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1539 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1540 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1543 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1544 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1547 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1548 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1551 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1552 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1555 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1556 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1559 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1560 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1563 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1564 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1567 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1568 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1571 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1572 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1579 static struct rte_pci_driver mlx5_driver = {
1581 .name = MLX5_DRIVER_NAME
1583 .id_table = mlx5_pci_id_map,
1584 .probe = mlx5_pci_probe,
1585 .remove = mlx5_pci_remove,
1586 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1587 RTE_PCI_DRV_PROBE_AGAIN),
1590 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1593 * Suffix RTE_EAL_PMD_PATH with "-glue".
1595 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1596 * suffixing its last component.
1599 * Output buffer, should be large enough otherwise NULL is returned.
1604 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1607 mlx5_glue_path(char *buf, size_t size)
1609 static const char *const bad[] = { "/", ".", "..", NULL };
1610 const char *path = RTE_EAL_PMD_PATH;
1611 size_t len = strlen(path);
1615 while (len && path[len - 1] == '/')
1617 for (off = len; off && path[off - 1] != '/'; --off)
1619 for (i = 0; bad[i]; ++i)
1620 if (!strncmp(path + off, bad[i], (int)(len - off)))
1622 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1623 if (i == -1 || (size_t)i >= size)
1628 "unable to append \"-glue\" to last component of"
1629 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1630 " please re-configure DPDK");
1635 * Initialization routine for run-time dependency on rdma-core.
1638 mlx5_glue_init(void)
1640 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1641 const char *path[] = {
1643 * A basic security check is necessary before trusting
1644 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1646 (geteuid() == getuid() && getegid() == getgid() ?
1647 getenv("MLX5_GLUE_PATH") : NULL),
1649 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1650 * variant, otherwise let dlopen() look up libraries on its
1653 (*RTE_EAL_PMD_PATH ?
1654 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1657 void *handle = NULL;
1661 while (!handle && i != RTE_DIM(path)) {
1670 end = strpbrk(path[i], ":;");
1672 end = path[i] + strlen(path[i]);
1673 len = end - path[i];
1678 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1680 (!len || *(end - 1) == '/') ? "" : "/");
1683 if (sizeof(name) != (size_t)ret + 1)
1685 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1687 handle = dlopen(name, RTLD_LAZY);
1698 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1701 sym = dlsym(handle, "mlx5_glue");
1702 if (!sym || !*sym) {
1706 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1715 "cannot initialize PMD due to missing run-time dependency on"
1716 " rdma-core libraries (libibverbs, libmlx5)");
1723 * Driver initialization routine.
1725 RTE_INIT(rte_mlx5_pmd_init)
1727 /* Initialize driver log type. */
1728 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1729 if (mlx5_logtype >= 0)
1730 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1732 /* Build the static tables for Verbs conversion. */
1733 mlx5_set_ptype_table();
1734 mlx5_set_cksum_table();
1735 mlx5_set_swp_types_table();
1737 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1738 * huge pages. Calling ibv_fork_init() during init allows
1739 * applications to use fork() safely for purposes other than
1740 * using this PMD, which is not supported in forked processes.
1742 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1743 /* Match the size of Rx completion entry to the size of a cacheline. */
1744 if (RTE_CACHE_LINE_SIZE == 128)
1745 setenv("MLX5_CQE_SIZE", "128", 0);
1747 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1748 * cleanup all the Verbs resources even when the device was removed.
1750 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1751 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1752 if (mlx5_glue_init())
1757 /* Glue structure must not contain any NULL pointers. */
1761 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1762 assert(((const void *const *)mlx5_glue)[i]);
1765 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1767 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1768 mlx5_glue->version, MLX5_GLUE_VERSION);
1771 mlx5_glue->fork_init();
1772 rte_pci_register(&mlx5_driver);
1775 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1776 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1777 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");