1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/rtnetlink.h>
19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
21 #pragma GCC diagnostic ignored "-Wpedantic"
23 #include <infiniband/verbs.h>
25 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_malloc.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_ethdev_pci.h>
32 #include <rte_bus_pci.h>
33 #include <rte_common.h>
34 #include <rte_config.h>
35 #include <rte_eal_memconfig.h>
36 #include <rte_kvargs.h>
37 #include <rte_rwlock.h>
38 #include <rte_spinlock.h>
39 #include <rte_string_fns.h>
42 #include "mlx5_utils.h"
43 #include "mlx5_rxtx.h"
44 #include "mlx5_autoconf.h"
45 #include "mlx5_defs.h"
46 #include "mlx5_glue.h"
48 #include "mlx5_flow.h"
50 /* Device parameter to enable RX completion queue compression. */
51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
53 /* Device parameter to enable RX completion entry padding to 128B. */
54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
56 /* Device parameter to enable padding Rx packet to cacheline size. */
57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
59 /* Device parameter to enable Multi-Packet Rx queue. */
60 #define MLX5_RX_MPRQ_EN "mprq_en"
62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
71 /* Device parameter to configure inline send. */
72 #define MLX5_TXQ_INLINE "txq_inline"
75 * Device parameter to configure the number of TX queues threshold for
76 * enabling inline send.
78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
81 * Device parameter to configure the number of TX queues threshold for
82 * enabling vectorized Tx.
84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
86 /* Device parameter to enable multi-packet send WQEs. */
87 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
89 /* Device parameter to include 2 dsegs in the title WQEBB. */
90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
92 /* Device parameter to limit the size of inlining packet. */
93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
95 /* Device parameter to enable hardware Tx vector. */
96 #define MLX5_TX_VEC_EN "tx_vec_en"
98 /* Device parameter to enable hardware Rx vector. */
99 #define MLX5_RX_VEC_EN "rx_vec_en"
101 /* Allow L3 VXLAN flow creation. */
102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
104 /* Activate DV flow steering. */
105 #define MLX5_DV_FLOW_EN "dv_flow_en"
107 /* Activate Netlink support in VF mode. */
108 #define MLX5_VF_NL_EN "vf_nl_en"
110 /* Select port representors to instantiate. */
111 #define MLX5_REPRESENTOR "representor"
113 #ifndef HAVE_IBV_MLX5_MOD_MPW
114 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
115 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
118 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
119 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
122 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
124 /* Shared memory between primary and secondary processes. */
125 struct mlx5_shared_data *mlx5_shared_data;
127 /* Spinlock for mlx5_shared_data allocation. */
128 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
130 /** Driver-specific log messages type. */
134 * Prepare shared data between primary and secondary process.
137 mlx5_prepare_shared_data(void)
139 const struct rte_memzone *mz;
141 rte_spinlock_lock(&mlx5_shared_data_lock);
142 if (mlx5_shared_data == NULL) {
143 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
144 /* Allocate shared memory. */
145 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
146 sizeof(*mlx5_shared_data),
149 /* Lookup allocated shared memory. */
150 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
153 rte_panic("Cannot allocate mlx5 shared data\n");
154 mlx5_shared_data = mz->addr;
155 /* Initialize shared data. */
156 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
157 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
158 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
160 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
161 mlx5_mr_mem_event_cb, NULL);
163 rte_spinlock_unlock(&mlx5_shared_data_lock);
167 * Retrieve integer value from environment variable.
170 * Environment variable name.
173 * Integer value, 0 if the variable is not set.
176 mlx5_getenv_int(const char *name)
178 const char *val = getenv(name);
186 * Verbs callback to allocate a memory. This function should allocate the space
187 * according to the size provided residing inside a huge page.
188 * Please note that all allocation must respect the alignment from libmlx5
189 * (i.e. currently sysconf(_SC_PAGESIZE)).
192 * The size in bytes of the memory to allocate.
194 * A pointer to the callback data.
197 * Allocated buffer, NULL otherwise and rte_errno is set.
200 mlx5_alloc_verbs_buf(size_t size, void *data)
202 struct mlx5_priv *priv = data;
204 size_t alignment = sysconf(_SC_PAGESIZE);
205 unsigned int socket = SOCKET_ID_ANY;
207 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
208 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
210 socket = ctrl->socket;
211 } else if (priv->verbs_alloc_ctx.type ==
212 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
213 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
215 socket = ctrl->socket;
217 assert(data != NULL);
218 ret = rte_malloc_socket(__func__, size, alignment, socket);
225 * Verbs callback to free a memory.
228 * A pointer to the memory to free.
230 * A pointer to the callback data.
233 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
235 assert(data != NULL);
240 * DPDK callback to close the device.
242 * Destroy all queues and objects, free memory.
245 * Pointer to Ethernet device structure.
248 mlx5_dev_close(struct rte_eth_dev *dev)
250 struct mlx5_priv *priv = dev->data->dev_private;
254 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
256 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
257 /* In case mlx5_dev_stop() has not been called. */
258 mlx5_dev_interrupt_handler_uninstall(dev);
259 mlx5_traffic_disable(dev);
260 mlx5_flow_flush(dev, NULL);
261 /* Prevent crashes when queues are still in use. */
262 dev->rx_pkt_burst = removed_rx_burst;
263 dev->tx_pkt_burst = removed_tx_burst;
264 if (priv->rxqs != NULL) {
265 /* XXX race condition if mlx5_rx_burst() is still running. */
267 for (i = 0; (i != priv->rxqs_n); ++i)
268 mlx5_rxq_release(dev, i);
272 if (priv->txqs != NULL) {
273 /* XXX race condition if mlx5_tx_burst() is still running. */
275 for (i = 0; (i != priv->txqs_n); ++i)
276 mlx5_txq_release(dev, i);
280 mlx5_mprq_free_mp(dev);
281 mlx5_mr_release(dev);
282 if (priv->pd != NULL) {
283 assert(priv->ctx != NULL);
284 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
285 claim_zero(mlx5_glue->close_device(priv->ctx));
287 assert(priv->ctx == NULL);
288 if (priv->rss_conf.rss_key != NULL)
289 rte_free(priv->rss_conf.rss_key);
290 if (priv->reta_idx != NULL)
291 rte_free(priv->reta_idx);
292 if (priv->primary_socket)
293 mlx5_socket_uninit(dev);
295 mlx5_nl_mac_addr_flush(dev);
296 if (priv->nl_socket_route >= 0)
297 close(priv->nl_socket_route);
298 if (priv->nl_socket_rdma >= 0)
299 close(priv->nl_socket_rdma);
300 if (priv->tcf_context)
301 mlx5_flow_tcf_context_destroy(priv->tcf_context);
302 ret = mlx5_hrxq_ibv_verify(dev);
304 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
306 ret = mlx5_ind_table_ibv_verify(dev);
308 DRV_LOG(WARNING, "port %u some indirection table still remain",
310 ret = mlx5_rxq_ibv_verify(dev);
312 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
314 ret = mlx5_rxq_verify(dev);
316 DRV_LOG(WARNING, "port %u some Rx queues still remain",
318 ret = mlx5_txq_ibv_verify(dev);
320 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
322 ret = mlx5_txq_verify(dev);
324 DRV_LOG(WARNING, "port %u some Tx queues still remain",
326 ret = mlx5_flow_verify(dev);
328 DRV_LOG(WARNING, "port %u some flows still remain",
330 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
332 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
335 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
337 struct mlx5_priv *opriv =
338 rte_eth_devices[port_id[i]].data->dev_private;
341 opriv->domain_id != priv->domain_id ||
342 &rte_eth_devices[port_id[i]] == dev)
347 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
349 memset(priv, 0, sizeof(*priv));
350 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
352 * Reset mac_addrs to NULL such that it is not freed as part of
353 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
354 * it is freed when dev_private is freed.
356 dev->data->mac_addrs = NULL;
359 const struct eth_dev_ops mlx5_dev_ops = {
360 .dev_configure = mlx5_dev_configure,
361 .dev_start = mlx5_dev_start,
362 .dev_stop = mlx5_dev_stop,
363 .dev_set_link_down = mlx5_set_link_down,
364 .dev_set_link_up = mlx5_set_link_up,
365 .dev_close = mlx5_dev_close,
366 .promiscuous_enable = mlx5_promiscuous_enable,
367 .promiscuous_disable = mlx5_promiscuous_disable,
368 .allmulticast_enable = mlx5_allmulticast_enable,
369 .allmulticast_disable = mlx5_allmulticast_disable,
370 .link_update = mlx5_link_update,
371 .stats_get = mlx5_stats_get,
372 .stats_reset = mlx5_stats_reset,
373 .xstats_get = mlx5_xstats_get,
374 .xstats_reset = mlx5_xstats_reset,
375 .xstats_get_names = mlx5_xstats_get_names,
376 .fw_version_get = mlx5_fw_version_get,
377 .dev_infos_get = mlx5_dev_infos_get,
378 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
379 .vlan_filter_set = mlx5_vlan_filter_set,
380 .rx_queue_setup = mlx5_rx_queue_setup,
381 .tx_queue_setup = mlx5_tx_queue_setup,
382 .rx_queue_release = mlx5_rx_queue_release,
383 .tx_queue_release = mlx5_tx_queue_release,
384 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
385 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
386 .mac_addr_remove = mlx5_mac_addr_remove,
387 .mac_addr_add = mlx5_mac_addr_add,
388 .mac_addr_set = mlx5_mac_addr_set,
389 .set_mc_addr_list = mlx5_set_mc_addr_list,
390 .mtu_set = mlx5_dev_set_mtu,
391 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
392 .vlan_offload_set = mlx5_vlan_offload_set,
393 .reta_update = mlx5_dev_rss_reta_update,
394 .reta_query = mlx5_dev_rss_reta_query,
395 .rss_hash_update = mlx5_rss_hash_update,
396 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
397 .filter_ctrl = mlx5_dev_filter_ctrl,
398 .rx_descriptor_status = mlx5_rx_descriptor_status,
399 .tx_descriptor_status = mlx5_tx_descriptor_status,
400 .rx_queue_count = mlx5_rx_queue_count,
401 .rx_queue_intr_enable = mlx5_rx_intr_enable,
402 .rx_queue_intr_disable = mlx5_rx_intr_disable,
403 .is_removed = mlx5_is_removed,
406 /* Available operations from secondary process. */
407 static const struct eth_dev_ops mlx5_dev_sec_ops = {
408 .stats_get = mlx5_stats_get,
409 .stats_reset = mlx5_stats_reset,
410 .xstats_get = mlx5_xstats_get,
411 .xstats_reset = mlx5_xstats_reset,
412 .xstats_get_names = mlx5_xstats_get_names,
413 .fw_version_get = mlx5_fw_version_get,
414 .dev_infos_get = mlx5_dev_infos_get,
415 .rx_descriptor_status = mlx5_rx_descriptor_status,
416 .tx_descriptor_status = mlx5_tx_descriptor_status,
419 /* Available operations in flow isolated mode. */
420 const struct eth_dev_ops mlx5_dev_ops_isolate = {
421 .dev_configure = mlx5_dev_configure,
422 .dev_start = mlx5_dev_start,
423 .dev_stop = mlx5_dev_stop,
424 .dev_set_link_down = mlx5_set_link_down,
425 .dev_set_link_up = mlx5_set_link_up,
426 .dev_close = mlx5_dev_close,
427 .promiscuous_enable = mlx5_promiscuous_enable,
428 .promiscuous_disable = mlx5_promiscuous_disable,
429 .allmulticast_enable = mlx5_allmulticast_enable,
430 .allmulticast_disable = mlx5_allmulticast_disable,
431 .link_update = mlx5_link_update,
432 .stats_get = mlx5_stats_get,
433 .stats_reset = mlx5_stats_reset,
434 .xstats_get = mlx5_xstats_get,
435 .xstats_reset = mlx5_xstats_reset,
436 .xstats_get_names = mlx5_xstats_get_names,
437 .fw_version_get = mlx5_fw_version_get,
438 .dev_infos_get = mlx5_dev_infos_get,
439 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
440 .vlan_filter_set = mlx5_vlan_filter_set,
441 .rx_queue_setup = mlx5_rx_queue_setup,
442 .tx_queue_setup = mlx5_tx_queue_setup,
443 .rx_queue_release = mlx5_rx_queue_release,
444 .tx_queue_release = mlx5_tx_queue_release,
445 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
446 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
447 .mac_addr_remove = mlx5_mac_addr_remove,
448 .mac_addr_add = mlx5_mac_addr_add,
449 .mac_addr_set = mlx5_mac_addr_set,
450 .set_mc_addr_list = mlx5_set_mc_addr_list,
451 .mtu_set = mlx5_dev_set_mtu,
452 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
453 .vlan_offload_set = mlx5_vlan_offload_set,
454 .filter_ctrl = mlx5_dev_filter_ctrl,
455 .rx_descriptor_status = mlx5_rx_descriptor_status,
456 .tx_descriptor_status = mlx5_tx_descriptor_status,
457 .rx_queue_intr_enable = mlx5_rx_intr_enable,
458 .rx_queue_intr_disable = mlx5_rx_intr_disable,
459 .is_removed = mlx5_is_removed,
463 * Verify and store value for device argument.
466 * Key argument to verify.
468 * Value associated with key.
473 * 0 on success, a negative errno value otherwise and rte_errno is set.
476 mlx5_args_check(const char *key, const char *val, void *opaque)
478 struct mlx5_dev_config *config = opaque;
481 /* No-op, port representors are processed in mlx5_dev_spawn(). */
482 if (!strcmp(MLX5_REPRESENTOR, key))
485 tmp = strtoul(val, NULL, 0);
488 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
491 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
492 config->cqe_comp = !!tmp;
493 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
494 config->cqe_pad = !!tmp;
495 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
496 config->hw_padding = !!tmp;
497 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
498 config->mprq.enabled = !!tmp;
499 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
500 config->mprq.stride_num_n = tmp;
501 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
502 config->mprq.max_memcpy_len = tmp;
503 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
504 config->mprq.min_rxqs_num = tmp;
505 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
506 config->txq_inline = tmp;
507 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
508 config->txqs_inline = tmp;
509 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
510 config->txqs_vec = tmp;
511 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
513 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
514 config->mpw_hdr_dseg = !!tmp;
515 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
516 config->inline_max_packet_sz = tmp;
517 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
518 config->tx_vec_en = !!tmp;
519 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
520 config->rx_vec_en = !!tmp;
521 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
522 config->l3_vxlan_en = !!tmp;
523 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
524 config->vf_nl_en = !!tmp;
525 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
526 config->dv_flow_en = !!tmp;
528 DRV_LOG(WARNING, "%s: unknown parameter", key);
536 * Parse device parameters.
539 * Pointer to device configuration structure.
541 * Device arguments structure.
544 * 0 on success, a negative errno value otherwise and rte_errno is set.
547 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
549 const char **params = (const char *[]){
550 MLX5_RXQ_CQE_COMP_EN,
554 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
555 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
558 MLX5_TXQS_MIN_INLINE,
561 MLX5_TXQ_MPW_HDR_DSEG_EN,
562 MLX5_TXQ_MAX_INLINE_LEN,
571 struct rte_kvargs *kvlist;
577 /* Following UGLY cast is done to pass checkpatch. */
578 kvlist = rte_kvargs_parse(devargs->args, params);
581 /* Process parameters. */
582 for (i = 0; (params[i] != NULL); ++i) {
583 if (rte_kvargs_count(kvlist, params[i])) {
584 ret = rte_kvargs_process(kvlist, params[i],
585 mlx5_args_check, config);
588 rte_kvargs_free(kvlist);
593 rte_kvargs_free(kvlist);
597 static struct rte_pci_driver mlx5_driver;
600 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
601 * local resource used by both primary and secondary to avoid duplicate
603 * The space has to be available on both primary and secondary process,
604 * TXQ UAR maps to this area using fixed mmap w/o double check.
606 static void *uar_base;
609 find_lower_va_bound(const struct rte_memseg_list *msl,
610 const struct rte_memseg *ms, void *arg)
619 *addr = RTE_MIN(*addr, ms->addr);
625 * Reserve UAR address space for primary process.
628 * Pointer to Ethernet device.
631 * 0 on success, a negative errno value otherwise and rte_errno is set.
634 mlx5_uar_init_primary(struct rte_eth_dev *dev)
636 struct mlx5_priv *priv = dev->data->dev_private;
637 void *addr = (void *)0;
639 if (uar_base) { /* UAR address space mapped. */
640 priv->uar_base = uar_base;
643 /* find out lower bound of hugepage segments */
644 rte_memseg_walk(find_lower_va_bound, &addr);
646 /* keep distance to hugepages to minimize potential conflicts. */
647 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
648 /* anonymous mmap, no real memory consumption. */
649 addr = mmap(addr, MLX5_UAR_SIZE,
650 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
651 if (addr == MAP_FAILED) {
653 "port %u failed to reserve UAR address space, please"
654 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
659 /* Accept either same addr or a new addr returned from mmap if target
662 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
663 dev->data->port_id, addr);
664 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
665 uar_base = addr; /* process local, don't reserve again. */
670 * Reserve UAR address space for secondary process, align with
674 * Pointer to Ethernet device.
677 * 0 on success, a negative errno value otherwise and rte_errno is set.
680 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
682 struct mlx5_priv *priv = dev->data->dev_private;
685 assert(priv->uar_base);
686 if (uar_base) { /* already reserved. */
687 assert(uar_base == priv->uar_base);
690 /* anonymous mmap, no real memory consumption. */
691 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
692 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
693 if (addr == MAP_FAILED) {
694 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
695 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
699 if (priv->uar_base != addr) {
701 "port %u UAR address %p size %llu occupied, please"
702 " adjust MLX5_UAR_OFFSET or try EAL parameter"
704 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
708 uar_base = addr; /* process local, don't reserve again */
709 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
710 dev->data->port_id, addr);
715 * Spawn an Ethernet device from Verbs information.
718 * Backing DPDK device.
722 * Device configuration parameters.
723 * @param[in] switch_info
724 * Switch properties of Ethernet device.
727 * A valid Ethernet device object on success, NULL otherwise and rte_errno
728 * is set. The following errors are defined:
730 * EBUSY: device is not supposed to be spawned.
731 * EEXIST: device is already spawned
733 static struct rte_eth_dev *
734 mlx5_dev_spawn(struct rte_device *dpdk_dev,
735 struct ibv_device *ibv_dev,
736 struct mlx5_dev_config config,
737 const struct mlx5_switch_info *switch_info)
739 struct ibv_context *ctx = NULL;
740 struct ibv_device_attr_ex attr;
741 struct ibv_port_attr port_attr;
742 struct ibv_pd *pd = NULL;
743 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
744 struct rte_eth_dev *eth_dev = NULL;
745 struct mlx5_priv *priv = NULL;
747 unsigned int hw_padding = 0;
749 unsigned int cqe_comp;
750 unsigned int cqe_pad = 0;
751 unsigned int tunnel_en = 0;
752 unsigned int mpls_en = 0;
753 unsigned int swp = 0;
754 unsigned int mprq = 0;
755 unsigned int mprq_min_stride_size_n = 0;
756 unsigned int mprq_max_stride_size_n = 0;
757 unsigned int mprq_min_stride_num_n = 0;
758 unsigned int mprq_max_stride_num_n = 0;
759 struct ether_addr mac;
760 char name[RTE_ETH_NAME_MAX_LEN];
761 int own_domain_id = 0;
765 /* Determine if this port representor is supposed to be spawned. */
766 if (switch_info->representor && dpdk_dev->devargs) {
767 struct rte_eth_devargs eth_da;
769 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
772 DRV_LOG(ERR, "failed to process device arguments: %s",
773 strerror(rte_errno));
776 for (i = 0; i < eth_da.nb_representor_ports; ++i)
777 if (eth_da.representor_ports[i] ==
778 (uint16_t)switch_info->port_name)
780 if (i == eth_da.nb_representor_ports) {
785 /* Build device name. */
786 if (!switch_info->representor)
787 strlcpy(name, dpdk_dev->name, sizeof(name));
789 snprintf(name, sizeof(name), "%s_representor_%u",
790 dpdk_dev->name, switch_info->port_name);
791 /* check if the device is already spawned */
792 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
796 /* Prepare shared data between primary and secondary process. */
797 mlx5_prepare_shared_data();
799 ctx = mlx5_glue->dv_open_device(ibv_dev);
802 DRV_LOG(DEBUG, "DEVX is supported");
804 ctx = mlx5_glue->open_device(ibv_dev);
806 rte_errno = errno ? errno : ENODEV;
810 #ifdef HAVE_IBV_MLX5_MOD_SWP
811 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
814 * Multi-packet send is supported by ConnectX-4 Lx PF as well
815 * as all ConnectX-5 devices.
817 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
818 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
820 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
821 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
823 mlx5_glue->dv_query_device(ctx, &dv_attr);
824 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
825 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
826 DRV_LOG(DEBUG, "enhanced MPW is supported");
827 mps = MLX5_MPW_ENHANCED;
829 DRV_LOG(DEBUG, "MPW is supported");
833 DRV_LOG(DEBUG, "MPW isn't supported");
834 mps = MLX5_MPW_DISABLED;
836 #ifdef HAVE_IBV_MLX5_MOD_SWP
837 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
838 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
839 DRV_LOG(DEBUG, "SWP support: %u", swp);
842 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
843 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
844 struct mlx5dv_striding_rq_caps mprq_caps =
845 dv_attr.striding_rq_caps;
847 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
848 mprq_caps.min_single_stride_log_num_of_bytes);
849 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
850 mprq_caps.max_single_stride_log_num_of_bytes);
851 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
852 mprq_caps.min_single_wqe_log_num_of_strides);
853 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
854 mprq_caps.max_single_wqe_log_num_of_strides);
855 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
856 mprq_caps.supported_qpts);
857 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
859 mprq_min_stride_size_n =
860 mprq_caps.min_single_stride_log_num_of_bytes;
861 mprq_max_stride_size_n =
862 mprq_caps.max_single_stride_log_num_of_bytes;
863 mprq_min_stride_num_n =
864 mprq_caps.min_single_wqe_log_num_of_strides;
865 mprq_max_stride_num_n =
866 mprq_caps.max_single_wqe_log_num_of_strides;
867 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
868 mprq_min_stride_num_n);
871 if (RTE_CACHE_LINE_SIZE == 128 &&
872 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
876 config.cqe_comp = cqe_comp;
877 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
878 /* Whether device supports 128B Rx CQE padding. */
879 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
880 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
882 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
883 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
884 tunnel_en = ((dv_attr.tunnel_offloads_caps &
885 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
886 (dv_attr.tunnel_offloads_caps &
887 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
889 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
890 tunnel_en ? "" : "not ");
893 "tunnel offloading disabled due to old OFED/rdma-core version");
895 config.tunnel_en = tunnel_en;
896 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
897 mpls_en = ((dv_attr.tunnel_offloads_caps &
898 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
899 (dv_attr.tunnel_offloads_caps &
900 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
901 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
902 mpls_en ? "" : "not ");
904 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
905 " old OFED/rdma-core version or firmware configuration");
907 config.mpls_en = mpls_en;
908 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
910 DEBUG("ibv_query_device_ex() failed");
913 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
914 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
915 eth_dev = rte_eth_dev_attach_secondary(name);
916 if (eth_dev == NULL) {
917 DRV_LOG(ERR, "can not attach rte ethdev");
922 eth_dev->device = dpdk_dev;
923 eth_dev->dev_ops = &mlx5_dev_sec_ops;
924 err = mlx5_uar_init_secondary(eth_dev);
929 /* Receive command fd from primary process */
930 err = mlx5_socket_connect(eth_dev);
935 /* Remap UAR for Tx queues. */
936 err = mlx5_tx_uar_remap(eth_dev, err);
942 * Ethdev pointer is still required as input since
943 * the primary device is not accessible from the
946 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
947 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
948 claim_zero(mlx5_glue->close_device(ctx));
951 /* Check port status. */
952 err = mlx5_glue->query_port(ctx, 1, &port_attr);
954 DRV_LOG(ERR, "port query failed: %s", strerror(err));
957 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
958 DRV_LOG(ERR, "port is not configured in Ethernet mode");
962 if (port_attr.state != IBV_PORT_ACTIVE)
963 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
964 mlx5_glue->port_state_str(port_attr.state),
966 /* Allocate protection domain. */
967 pd = mlx5_glue->alloc_pd(ctx);
969 DRV_LOG(ERR, "PD allocation failure");
973 priv = rte_zmalloc("ethdev private structure",
975 RTE_CACHE_LINE_SIZE);
977 DRV_LOG(ERR, "priv allocation failure");
982 strncpy(priv->ibdev_name, priv->ctx->device->name,
983 sizeof(priv->ibdev_name));
984 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
985 sizeof(priv->ibdev_path));
986 priv->device_attr = attr;
988 priv->mtu = ETHER_MTU;
990 /* Initialize UAR access locks for 32bit implementations. */
991 rte_spinlock_init(&priv->uar_lock_cq);
992 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
993 rte_spinlock_init(&priv->uar_lock[i]);
995 /* Some internal functions rely on Netlink sockets, open them now. */
996 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
997 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
999 priv->representor = !!switch_info->representor;
1000 priv->master = !!switch_info->master;
1001 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1003 * Currently we support single E-Switch per PF configurations
1004 * only and vport_id field contains the vport index for
1005 * associated VF, which is deduced from representor port name.
1006 * For exapmple, let's have the IB device port 10, it has
1007 * attached network device eth0, which has port name attribute
1008 * pf0vf2, we can deduce the VF number as 2, and set vport index
1009 * as 3 (2+1). This assigning schema should be changed if the
1010 * multiple E-Switch instances per PF configurations or/and PCI
1011 * subfunctions are added.
1013 priv->vport_id = switch_info->representor ?
1014 switch_info->port_name + 1 : -1;
1015 /* representor_id field keeps the unmodified port/VF index. */
1016 priv->representor_id = switch_info->representor ?
1017 switch_info->port_name : -1;
1019 * Look for sibling devices in order to reuse their switch domain
1020 * if any, otherwise allocate one.
1022 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
1024 uint16_t port_id[i];
1026 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1028 const struct mlx5_priv *opriv =
1029 rte_eth_devices[port_id[i]].data->dev_private;
1033 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1035 priv->domain_id = opriv->domain_id;
1039 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1040 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1043 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1044 strerror(rte_errno));
1049 err = mlx5_args(&config, dpdk_dev->devargs);
1052 DRV_LOG(ERR, "failed to process device arguments: %s",
1053 strerror(rte_errno));
1056 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1057 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1058 (config.hw_csum ? "" : "not "));
1059 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1060 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1061 DRV_LOG(DEBUG, "counters are not supported");
1063 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1064 if (config.dv_flow_en) {
1065 DRV_LOG(WARNING, "DV flow is not supported");
1066 config.dv_flow_en = 0;
1069 config.ind_table_max_size =
1070 attr.rss_caps.max_rwq_indirection_table_size;
1072 * Remove this check once DPDK supports larger/variable
1073 * indirection tables.
1075 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1076 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1077 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1078 config.ind_table_max_size);
1079 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1080 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1081 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1082 (config.hw_vlan_strip ? "" : "not "));
1083 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1084 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1085 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1086 (config.hw_fcs_strip ? "" : "not "));
1087 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
1088 hw_padding = !!attr.rx_pad_end_addr_align;
1089 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
1090 hw_padding = !!(attr.device_cap_flags_ex &
1091 IBV_DEVICE_PCI_WRITE_END_PADDING);
1093 if (config.hw_padding && !hw_padding) {
1094 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1095 config.hw_padding = 0;
1096 } else if (config.hw_padding) {
1097 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1099 config.tso = (attr.tso_caps.max_tso > 0 &&
1100 (attr.tso_caps.supported_qpts &
1101 (1 << IBV_QPT_RAW_PACKET)));
1103 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1105 * MPW is disabled by default, while the Enhanced MPW is enabled
1108 if (config.mps == MLX5_ARG_UNSET)
1109 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1112 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1113 DRV_LOG(INFO, "%sMPS is %s",
1114 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1115 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1116 if (config.cqe_comp && !cqe_comp) {
1117 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1118 config.cqe_comp = 0;
1120 if (config.cqe_pad && !cqe_pad) {
1121 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1123 } else if (config.cqe_pad) {
1124 DRV_LOG(INFO, "Rx CQE padding is enabled");
1126 if (config.mprq.enabled && mprq) {
1127 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1128 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1129 config.mprq.stride_num_n =
1130 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1131 mprq_min_stride_num_n);
1133 "the number of strides"
1134 " for Multi-Packet RQ is out of range,"
1135 " setting default value (%u)",
1136 1 << config.mprq.stride_num_n);
1138 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1139 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1140 } else if (config.mprq.enabled && !mprq) {
1141 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1142 config.mprq.enabled = 0;
1144 eth_dev = rte_eth_dev_allocate(name);
1145 if (eth_dev == NULL) {
1146 DRV_LOG(ERR, "can not allocate rte ethdev");
1150 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1151 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1152 if (priv->representor) {
1153 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1154 eth_dev->data->representor_id = priv->representor_id;
1156 eth_dev->data->dev_private = priv;
1157 priv->dev_data = eth_dev->data;
1158 eth_dev->data->mac_addrs = priv->mac;
1159 eth_dev->device = dpdk_dev;
1160 err = mlx5_uar_init_primary(eth_dev);
1165 /* Configure the first MAC address by default. */
1166 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1168 "port %u cannot get MAC address, is mlx5_en"
1169 " loaded? (errno: %s)",
1170 eth_dev->data->port_id, strerror(rte_errno));
1175 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1176 eth_dev->data->port_id,
1177 mac.addr_bytes[0], mac.addr_bytes[1],
1178 mac.addr_bytes[2], mac.addr_bytes[3],
1179 mac.addr_bytes[4], mac.addr_bytes[5]);
1182 char ifname[IF_NAMESIZE];
1184 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1185 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1186 eth_dev->data->port_id, ifname);
1188 DRV_LOG(DEBUG, "port %u ifname is unknown",
1189 eth_dev->data->port_id);
1192 /* Get actual MTU if possible. */
1193 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1198 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1200 /* Initialize burst functions to prevent crashes before link-up. */
1201 eth_dev->rx_pkt_burst = removed_rx_burst;
1202 eth_dev->tx_pkt_burst = removed_tx_burst;
1203 eth_dev->dev_ops = &mlx5_dev_ops;
1204 /* Register MAC address. */
1205 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1206 if (config.vf && config.vf_nl_en)
1207 mlx5_nl_mac_addr_sync(eth_dev);
1208 priv->tcf_context = mlx5_flow_tcf_context_create();
1209 if (!priv->tcf_context) {
1212 "flow rules relying on switch offloads will not be"
1213 " supported: cannot open libmnl socket: %s",
1214 strerror(rte_errno));
1216 struct rte_flow_error error;
1217 unsigned int ifindex = mlx5_ifindex(eth_dev);
1222 "cannot retrieve network interface index";
1224 err = mlx5_flow_tcf_init(priv->tcf_context,
1229 "flow rules relying on switch offloads will"
1230 " not be supported: %s: %s",
1231 error.message, strerror(rte_errno));
1232 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1233 priv->tcf_context = NULL;
1236 TAILQ_INIT(&priv->flows);
1237 TAILQ_INIT(&priv->ctrl_flows);
1238 /* Hint libmlx5 to use PMD allocator for data plane resources */
1239 struct mlx5dv_ctx_allocators alctr = {
1240 .alloc = &mlx5_alloc_verbs_buf,
1241 .free = &mlx5_free_verbs_buf,
1244 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1245 (void *)((uintptr_t)&alctr));
1246 /* Bring Ethernet device up. */
1247 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1248 eth_dev->data->port_id);
1249 mlx5_set_link_up(eth_dev);
1251 * Even though the interrupt handler is not installed yet,
1252 * interrupts will still trigger on the asyn_fd from
1253 * Verbs context returned by ibv_open_device().
1255 mlx5_link_update(eth_dev, 0);
1256 /* Store device configuration on private structure. */
1257 priv->config = config;
1258 /* Supported Verbs flow priority number detection. */
1259 err = mlx5_flow_discover_priorities(eth_dev);
1264 priv->config.flow_prio = err;
1266 * Once the device is added to the list of memory event
1267 * callback, its global MR cache table cannot be expanded
1268 * on the fly because of deadlock. If it overflows, lookup
1269 * should be done by searching MR list linearly, which is slow.
1271 err = mlx5_mr_btree_init(&priv->mr.cache,
1272 MLX5_MR_BTREE_CACHE_N * 2,
1273 eth_dev->device->numa_node);
1278 /* Add device to memory callback list. */
1279 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1280 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1281 priv, mem_event_cb);
1282 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1286 if (priv->nl_socket_route >= 0)
1287 close(priv->nl_socket_route);
1288 if (priv->nl_socket_rdma >= 0)
1289 close(priv->nl_socket_rdma);
1290 if (priv->tcf_context)
1291 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1293 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1295 if (eth_dev != NULL)
1296 eth_dev->data->dev_private = NULL;
1299 claim_zero(mlx5_glue->dealloc_pd(pd));
1300 if (eth_dev != NULL) {
1301 /* mac_addrs must not be freed alone because part of dev_private */
1302 eth_dev->data->mac_addrs = NULL;
1303 rte_eth_dev_release_port(eth_dev);
1306 claim_zero(mlx5_glue->close_device(ctx));
1312 /** Data associated with devices to spawn. */
1313 struct mlx5_dev_spawn_data {
1314 unsigned int ifindex; /**< Network interface index. */
1315 struct mlx5_switch_info info; /**< Switch information. */
1316 struct ibv_device *ibv_dev; /**< Associated IB device. */
1317 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1321 * Comparison callback to sort device data.
1323 * This is meant to be used with qsort().
1326 * Pointer to pointer to first data object.
1328 * Pointer to pointer to second data object.
1331 * 0 if both objects are equal, less than 0 if the first argument is less
1332 * than the second, greater than 0 otherwise.
1335 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1337 const struct mlx5_switch_info *si_a =
1338 &((const struct mlx5_dev_spawn_data *)a)->info;
1339 const struct mlx5_switch_info *si_b =
1340 &((const struct mlx5_dev_spawn_data *)b)->info;
1343 /* Master device first. */
1344 ret = si_b->master - si_a->master;
1347 /* Then representor devices. */
1348 ret = si_b->representor - si_a->representor;
1351 /* Unidentified devices come last in no specific order. */
1352 if (!si_a->representor)
1354 /* Order representors by name. */
1355 return si_a->port_name - si_b->port_name;
1359 * DPDK callback to register a PCI device.
1361 * This function spawns Ethernet devices out of a given PCI device.
1363 * @param[in] pci_drv
1364 * PCI driver structure (mlx5_driver).
1365 * @param[in] pci_dev
1366 * PCI device information.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1373 struct rte_pci_device *pci_dev)
1375 struct ibv_device **ibv_list;
1377 struct mlx5_dev_config dev_config;
1380 assert(pci_drv == &mlx5_driver);
1382 ibv_list = mlx5_glue->get_device_list(&ret);
1384 rte_errno = errno ? errno : ENOSYS;
1385 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1389 struct ibv_device *ibv_match[ret + 1];
1392 struct rte_pci_addr pci_addr;
1394 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1395 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1397 if (pci_dev->addr.domain != pci_addr.domain ||
1398 pci_dev->addr.bus != pci_addr.bus ||
1399 pci_dev->addr.devid != pci_addr.devid ||
1400 pci_dev->addr.function != pci_addr.function)
1402 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1403 ibv_list[ret]->name);
1404 ibv_match[n++] = ibv_list[ret];
1406 ibv_match[n] = NULL;
1408 struct mlx5_dev_spawn_data list[n];
1409 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1410 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1415 * The existence of several matching entries (n > 1) means port
1416 * representors have been instantiated. No existing Verbs call nor
1417 * /sys entries can tell them apart, this can only be done through
1418 * Netlink calls assuming kernel drivers are recent enough to
1421 * In the event of identification failure through Netlink, try again
1422 * through sysfs, then either:
1424 * 1. No device matches (n == 0), complain and bail out.
1425 * 2. A single IB device matches (n == 1) and is not a representor,
1426 * assume no switch support.
1427 * 3. Otherwise no safe assumptions can be made; complain louder and
1430 for (i = 0; i != n; ++i) {
1431 list[i].ibv_dev = ibv_match[i];
1432 list[i].eth_dev = NULL;
1434 list[i].ifindex = 0;
1436 list[i].ifindex = mlx5_nl_ifindex
1437 (nl_rdma, list[i].ibv_dev->name);
1440 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1442 ((!list[i].info.representor && !list[i].info.master) &&
1443 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1444 list[i].ifindex = 0;
1445 memset(&list[i].info, 0, sizeof(list[i].info));
1453 /* Count unidentified devices. */
1454 for (u = 0, i = 0; i != n; ++i)
1455 if (!list[i].info.master && !list[i].info.representor)
1458 if (n == 1 && u == 1) {
1460 DRV_LOG(INFO, "no switch support detected");
1464 "unable to tell which of the matching devices"
1465 " is the master (lack of kernel support?)");
1470 * Sort list to probe devices in natural order for users convenience
1471 * (i.e. master first, then representors from lowest to highest ID).
1474 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1475 /* Default configuration. */
1476 dev_config = (struct mlx5_dev_config){
1478 .mps = MLX5_ARG_UNSET,
1481 .txq_inline = MLX5_ARG_UNSET,
1482 .txqs_inline = MLX5_ARG_UNSET,
1483 .txqs_vec = MLX5_ARG_UNSET,
1484 .inline_max_packet_sz = MLX5_ARG_UNSET,
1487 .enabled = 0, /* Disabled by default. */
1488 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1489 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1490 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1493 /* Device speicific configuration. */
1494 switch (pci_dev->id.device_id) {
1495 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1496 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1498 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1499 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1500 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1501 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1507 /* Set architecture-dependent default value if unset. */
1508 if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1509 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1510 for (i = 0; i != n; ++i) {
1513 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1514 list[i].ibv_dev, dev_config,
1516 if (!list[i].eth_dev) {
1517 if (rte_errno != EBUSY && rte_errno != EEXIST)
1519 /* Device is disabled or already spawned. Ignore it. */
1522 restore = list[i].eth_dev->data->dev_flags;
1523 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1524 /* Restore non-PCI flags cleared by the above call. */
1525 list[i].eth_dev->data->dev_flags |= restore;
1526 rte_eth_dev_probing_finish(list[i].eth_dev);
1528 mlx5_glue->free_device_list(ibv_list);
1531 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1532 " are kernel drivers loaded?",
1533 pci_dev->addr.domain, pci_dev->addr.bus,
1534 pci_dev->addr.devid, pci_dev->addr.function);
1537 } else if (i != n) {
1539 "probe of PCI device " PCI_PRI_FMT " aborted after"
1540 " encountering an error: %s",
1541 pci_dev->addr.domain, pci_dev->addr.bus,
1542 pci_dev->addr.devid, pci_dev->addr.function,
1543 strerror(rte_errno));
1547 if (!list[i].eth_dev)
1549 mlx5_dev_close(list[i].eth_dev);
1550 /* mac_addrs must not be freed because in dev_private */
1551 list[i].eth_dev->data->mac_addrs = NULL;
1552 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1554 /* Restore original error. */
1563 * DPDK callback to remove a PCI device.
1565 * This function removes all Ethernet devices belong to a given PCI device.
1567 * @param[in] pci_dev
1568 * Pointer to the PCI device.
1571 * 0 on success, the function cannot fail.
1574 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1577 struct rte_eth_dev *port;
1579 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1580 port = &rte_eth_devices[port_id];
1581 if (port->state != RTE_ETH_DEV_UNUSED &&
1582 port->device == &pci_dev->device)
1583 rte_eth_dev_close(port_id);
1588 static const struct rte_pci_id mlx5_pci_id_map[] = {
1590 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1591 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1594 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1595 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1598 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1599 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1602 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1603 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1606 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1607 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1610 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1611 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1614 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1615 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1618 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1619 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1622 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1623 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1626 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1627 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1630 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1631 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1634 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1635 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1642 static struct rte_pci_driver mlx5_driver = {
1644 .name = MLX5_DRIVER_NAME
1646 .id_table = mlx5_pci_id_map,
1647 .probe = mlx5_pci_probe,
1648 .remove = mlx5_pci_remove,
1649 .dma_map = mlx5_dma_map,
1650 .dma_unmap = mlx5_dma_unmap,
1651 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1652 RTE_PCI_DRV_PROBE_AGAIN),
1655 #ifdef RTE_IBVERBS_LINK_DLOPEN
1658 * Suffix RTE_EAL_PMD_PATH with "-glue".
1660 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1661 * suffixing its last component.
1664 * Output buffer, should be large enough otherwise NULL is returned.
1669 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1672 mlx5_glue_path(char *buf, size_t size)
1674 static const char *const bad[] = { "/", ".", "..", NULL };
1675 const char *path = RTE_EAL_PMD_PATH;
1676 size_t len = strlen(path);
1680 while (len && path[len - 1] == '/')
1682 for (off = len; off && path[off - 1] != '/'; --off)
1684 for (i = 0; bad[i]; ++i)
1685 if (!strncmp(path + off, bad[i], (int)(len - off)))
1687 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1688 if (i == -1 || (size_t)i >= size)
1693 "unable to append \"-glue\" to last component of"
1694 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1695 " please re-configure DPDK");
1700 * Initialization routine for run-time dependency on rdma-core.
1703 mlx5_glue_init(void)
1705 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1706 const char *path[] = {
1708 * A basic security check is necessary before trusting
1709 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1711 (geteuid() == getuid() && getegid() == getgid() ?
1712 getenv("MLX5_GLUE_PATH") : NULL),
1714 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1715 * variant, otherwise let dlopen() look up libraries on its
1718 (*RTE_EAL_PMD_PATH ?
1719 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1722 void *handle = NULL;
1726 while (!handle && i != RTE_DIM(path)) {
1735 end = strpbrk(path[i], ":;");
1737 end = path[i] + strlen(path[i]);
1738 len = end - path[i];
1743 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1745 (!len || *(end - 1) == '/') ? "" : "/");
1748 if (sizeof(name) != (size_t)ret + 1)
1750 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1752 handle = dlopen(name, RTLD_LAZY);
1763 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1766 sym = dlsym(handle, "mlx5_glue");
1767 if (!sym || !*sym) {
1771 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1780 "cannot initialize PMD due to missing run-time dependency on"
1781 " rdma-core libraries (libibverbs, libmlx5)");
1788 * Driver initialization routine.
1790 RTE_INIT(rte_mlx5_pmd_init)
1792 /* Initialize driver log type. */
1793 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1794 if (mlx5_logtype >= 0)
1795 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1797 /* Build the static tables for Verbs conversion. */
1798 mlx5_set_ptype_table();
1799 mlx5_set_cksum_table();
1800 mlx5_set_swp_types_table();
1802 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1803 * huge pages. Calling ibv_fork_init() during init allows
1804 * applications to use fork() safely for purposes other than
1805 * using this PMD, which is not supported in forked processes.
1807 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1808 /* Match the size of Rx completion entry to the size of a cacheline. */
1809 if (RTE_CACHE_LINE_SIZE == 128)
1810 setenv("MLX5_CQE_SIZE", "128", 0);
1812 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1813 * cleanup all the Verbs resources even when the device was removed.
1815 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1816 #ifdef RTE_IBVERBS_LINK_DLOPEN
1817 if (mlx5_glue_init())
1822 /* Glue structure must not contain any NULL pointers. */
1826 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1827 assert(((const void *const *)mlx5_glue)[i]);
1830 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1832 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1833 mlx5_glue->version, MLX5_GLUE_VERSION);
1836 mlx5_glue->fork_init();
1837 rte_pci_register(&mlx5_driver);
1840 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1841 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1842 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");