drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202         {
 203                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 204                 .trunk_size = 64,
 205                 .grow_trunk = 3,
 206                 .grow_shift = 2,
 207                 .need_lock = 0,
 208                 .release_mem_en = 1,
 209                 .malloc = rte_malloc_socket,
 210                 .free = rte_free,
 211                 .type = "mlx5_encap_decap_ipool",
 212         },
 213         {
 214                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 215                 .trunk_size = 64,
 216                 .grow_trunk = 3,
 217                 .grow_shift = 2,
 218                 .need_lock = 0,
 219                 .release_mem_en = 1,
 220                 .malloc = rte_malloc_socket,
 221                 .free = rte_free,
 222                 .type = "mlx5_push_vlan_ipool",
 223         },
 224 };
 225
 226
 227 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 228 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 229
 230 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 231 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 232
 233 /**
 234  * Allocate ID pool structure.
 235  *
 236  * @param[in] max_id
 237  *   The maximum id can be allocated from the pool.
 238  *
 239  * @return
 240  *   Pointer to pool object, NULL value otherwise.
 241  */
 242 struct mlx5_flow_id_pool *
 243 mlx5_flow_id_pool_alloc(uint32_t max_id)
 244 {
 245         struct mlx5_flow_id_pool *pool;
 246         void *mem;
 247
 248         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 249                            RTE_CACHE_LINE_SIZE);
 250         if (!pool) {
 251                 DRV_LOG(ERR, "can't allocate id pool");
 252                 rte_errno  = ENOMEM;
 253                 return NULL;
 254         }
 255         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 256                           RTE_CACHE_LINE_SIZE);
 257         if (!mem) {
 258                 DRV_LOG(ERR, "can't allocate mem for id pool");
 259                 rte_errno  = ENOMEM;
 260                 goto error;
 261         }
 262         pool->free_arr = mem;
 263         pool->curr = pool->free_arr;
 264         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 265         pool->base_index = 0;
 266         pool->max_id = max_id;
 267         return pool;
 268 error:
 269         rte_free(pool);
 270         return NULL;
 271 }
 272
 273 /**
 274  * Release ID pool structure.
 275  *
 276  * @param[in] pool
 277  *   Pointer to flow id pool object to free.
 278  */
 279 void
 280 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 281 {
 282         rte_free(pool->free_arr);
 283         rte_free(pool);
 284 }
 285
 286 /**
 287  * Generate ID.
 288  *
 289  * @param[in] pool
 290  *   Pointer to flow id pool.
 291  * @param[out] id
 292  *   The generated ID.
 293  *
 294  * @return
 295  *   0 on success, error value otherwise.
 296  */
 297 uint32_t
 298 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 299 {
 300         if (pool->curr == pool->free_arr) {
 301                 if (pool->base_index == pool->max_id) {
 302                         rte_errno  = ENOMEM;
 303                         DRV_LOG(ERR, "no free id");
 304                         return -rte_errno;
 305                 }
 306                 *id = ++pool->base_index;
 307                 return 0;
 308         }
 309         *id = *(--pool->curr);
 310         return 0;
 311 }
 312
 313 /**
 314  * Release ID.
 315  *
 316  * @param[in] pool
 317  *   Pointer to flow id pool.
 318  * @param[out] id
 319  *   The generated ID.
 320  *
 321  * @return
 322  *   0 on success, error value otherwise.
 323  */
 324 uint32_t
 325 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 326 {
 327         uint32_t size;
 328         uint32_t size2;
 329         void *mem;
 330
 331         if (pool->curr == pool->last) {
 332                 size = pool->curr - pool->free_arr;
 333                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 334                 MLX5_ASSERT(size2 > size);
 335                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 336                 if (!mem) {
 337                         DRV_LOG(ERR, "can't allocate mem for id pool");
 338                         rte_errno  = ENOMEM;
 339                         return -rte_errno;
 340                 }
 341                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 342                 rte_free(pool->free_arr);
 343                 pool->free_arr = mem;
 344                 pool->curr = pool->free_arr + size;
 345                 pool->last = pool->free_arr + size2;
 346         }
 347         *pool->curr = id;
 348         pool->curr++;
 349         return 0;
 350 }
 351
 352 /**
 353  * Initialize the counters management structure.
 354  *
 355  * @param[in] sh
 356  *   Pointer to mlx5_ibv_shared object to free
 357  */
 358 static void
 359 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 360 {
 361         uint8_t i;
 362
 363         TAILQ_INIT(&sh->cmng.flow_counters);
 364         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 365                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 366 }
 367
 368 /**
 369  * Destroy all the resources allocated for a counter memory management.
 370  *
 371  * @param[in] mng
 372  *   Pointer to the memory management structure.
 373  */
 374 static void
 375 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 376 {
 377         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 378
 379         LIST_REMOVE(mng, next);
 380         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 381         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 382         rte_free(mem);
 383 }
 384
 385 /**
 386  * Close and release all the resources of the counters management.
 387  *
 388  * @param[in] sh
 389  *   Pointer to mlx5_ibv_shared object to free.
 390  */
 391 static void
 392 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 393 {
 394         struct mlx5_counter_stats_mem_mng *mng;
 395         uint8_t i;
 396         int j;
 397         int retries = 1024;
 398
 399         rte_errno = 0;
 400         while (--retries) {
 401                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 402                 if (rte_errno != EINPROGRESS)
 403                         break;
 404                 rte_pause();
 405         }
 406         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 407                 struct mlx5_flow_counter_pool *pool;
 408                 uint32_t batch = !!(i % 2);
 409
 410                 if (!sh->cmng.ccont[i].pools)
 411                         continue;
 412                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 413                 while (pool) {
 414                         if (batch) {
 415                                 if (pool->min_dcs)
 416                                         claim_zero
 417                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 418                         }
 419                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 420                                 if (pool->counters_raw[j].action)
 421                                         claim_zero
 422                                         (mlx5_glue->destroy_flow_action
 423                                                (pool->counters_raw[j].action));
 424                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 425                                     (pool, j)->dcs)
 426                                         claim_zero(mlx5_devx_cmd_destroy
 427                                                   (MLX5_GET_POOL_CNT_EXT
 428                                                   (pool, j)->dcs));
 429                         }
 430                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 431                                      next);
 432                         rte_free(pool);
 433                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 434                 }
 435                 rte_free(sh->cmng.ccont[i].pools);
 436         }
 437         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 438         while (mng) {
 439                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 440                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 441         }
 442         memset(&sh->cmng, 0, sizeof(sh->cmng));
 443 }
 444
 445 /**
 446  * Initialize the flow resources' indexed mempool.
 447  *
 448  * @param[in] sh
 449  *   Pointer to mlx5_ibv_shared object.
 450  */
 451 static void
 452 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh)
 453 {
 454         uint8_t i;
 455
 456         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 457                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 458 }
 459
 460 /**
 461  * Release the flow resources' indexed mempool.
 462  *
 463  * @param[in] sh
 464  *   Pointer to mlx5_ibv_shared object.
 465  */
 466 static void
 467 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 468 {
 469         uint8_t i;
 470
 471         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 472                 mlx5_ipool_destroy(sh->ipool[i]);
 473 }
 474
 475 /**
 476  * Extract pdn of PD object using DV API.
 477  *
 478  * @param[in] pd
 479  *   Pointer to the verbs PD object.
 480  * @param[out] pdn
 481  *   Pointer to the PD object number variable.
 482  *
 483  * @return
 484  *   0 on success, error value otherwise.
 485  */
 486 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 487 static int
 488 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 489 {
 490         struct mlx5dv_obj obj;
 491         struct mlx5dv_pd pd_info;
 492         int ret = 0;
 493
 494         obj.pd.in = pd;
 495         obj.pd.out = &pd_info;
 496         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 497         if (ret) {
 498                 DRV_LOG(DEBUG, "Fail to get PD object info");
 499                 return ret;
 500         }
 501         *pdn = pd_info.pdn;
 502         return 0;
 503 }
 504 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 505
 506 static int
 507 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 508 {
 509         char *env;
 510         int value;
 511
 512         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 513         /* Get environment variable to store. */
 514         env = getenv(MLX5_SHUT_UP_BF);
 515         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 516         if (config->dbnc == MLX5_ARG_UNSET)
 517                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 518         else
 519                 setenv(MLX5_SHUT_UP_BF,
 520                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 521         return value;
 522 }
 523
 524 static void
 525 mlx5_restore_doorbell_mapping_env(int value)
 526 {
 527         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 528         /* Restore the original environment variable state. */
 529         if (value == MLX5_ARG_UNSET)
 530                 unsetenv(MLX5_SHUT_UP_BF);
 531         else
 532                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 533 }
 534
 535 /**
 536  * Allocate shared IB device context. If there is multiport device the
 537  * master and representors will share this context, if there is single
 538  * port dedicated IB device, the context will be used by only given
 539  * port due to unification.
 540  *
 541  * Routine first searches the context for the specified IB device name,
 542  * if found the shared context assumed and reference counter is incremented.
 543  * If no context found the new one is created and initialized with specified
 544  * IB device context and parameters.
 545  *
 546  * @param[in] spawn
 547  *   Pointer to the IB device attributes (name, port, etc).
 548  * @param[in] config
 549  *   Pointer to device configuration structure.
 550  *
 551  * @return
 552  *   Pointer to mlx5_ibv_shared object on success,
 553  *   otherwise NULL and rte_errno is set.
 554  */
 555 static struct mlx5_ibv_shared *
 556 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 557                         const struct mlx5_dev_config *config)
 558 {
 559         struct mlx5_ibv_shared *sh;
 560         int dbmap_env;
 561         int err = 0;
 562         uint32_t i;
 563 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 564         struct mlx5_devx_tis_attr tis_attr = { 0 };
 565 #endif
 566
 567         MLX5_ASSERT(spawn);
 568         /* Secondary process should not create the shared context. */
 569         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 570         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 571         /* Search for IB context by device name. */
 572         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 573                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 574                         sh->refcnt++;
 575                         goto exit;
 576                 }
 577         }
 578         /* No device found, we have to create new shared context. */
 579         MLX5_ASSERT(spawn->max_port);
 580         sh = rte_zmalloc("ethdev shared ib context",
 581                          sizeof(struct mlx5_ibv_shared) +
 582                          spawn->max_port *
 583                          sizeof(struct mlx5_ibv_shared_port),
 584                          RTE_CACHE_LINE_SIZE);
 585         if (!sh) {
 586                 DRV_LOG(ERR, "shared context allocation failure");
 587                 rte_errno  = ENOMEM;
 588                 goto exit;
 589         }
 590         /*
 591          * Configure environment variable "MLX5_BF_SHUT_UP"
 592          * before the device creation. The rdma_core library
 593          * checks the variable at device creation and
 594          * stores the result internally.
 595          */
 596         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 597         /* Try to open IB device with DV first, then usual Verbs. */
 598         errno = 0;
 599         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 600         if (sh->ctx) {
 601                 sh->devx = 1;
 602                 DRV_LOG(DEBUG, "DevX is supported");
 603                 /* The device is created, no need for environment. */
 604                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 605         } else {
 606                 /* The environment variable is still configured. */
 607                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 608                 err = errno ? errno : ENODEV;
 609                 /*
 610                  * The environment variable is not needed anymore,
 611                  * all device creation attempts are completed.
 612                  */
 613                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 614                 if (!sh->ctx)
 615                         goto error;
 616                 DRV_LOG(DEBUG, "DevX is NOT supported");
 617         }
 618         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 619         if (err) {
 620                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 621                 goto error;
 622         }
 623         sh->refcnt = 1;
 624         sh->max_port = spawn->max_port;
 625         strncpy(sh->ibdev_name, sh->ctx->device->name,
 626                 sizeof(sh->ibdev_name));
 627         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 628                 sizeof(sh->ibdev_path));
 629         pthread_mutex_init(&sh->intr_mutex, NULL);
 630         /*
 631          * Setting port_id to max unallowed value means
 632          * there is no interrupt subhandler installed for
 633          * the given port index i.
 634          */
 635         for (i = 0; i < sh->max_port; i++) {
 636                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 637                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 638         }
 639         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 640         if (sh->pd == NULL) {
 641                 DRV_LOG(ERR, "PD allocation failure");
 642                 err = ENOMEM;
 643                 goto error;
 644         }
 645 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 646         if (sh->devx) {
 647                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 648                 if (err) {
 649                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 650                         goto error;
 651                 }
 652                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 653                 if (!sh->td) {
 654                         DRV_LOG(ERR, "TD allocation failure");
 655                         err = ENOMEM;
 656                         goto error;
 657                 }
 658                 tis_attr.transport_domain = sh->td->id;
 659                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 660                 if (!sh->tis) {
 661                         DRV_LOG(ERR, "TIS allocation failure");
 662                         err = ENOMEM;
 663                         goto error;
 664                 }
 665         }
 666         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 667         if (!sh->flow_id_pool) {
 668                 DRV_LOG(ERR, "can't create flow id pool");
 669                 err = ENOMEM;
 670                 goto error;
 671         }
 672 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 673         /*
 674          * Once the device is added to the list of memory event
 675          * callback, its global MR cache table cannot be expanded
 676          * on the fly because of deadlock. If it overflows, lookup
 677          * should be done by searching MR list linearly, which is slow.
 678          *
 679          * At this point the device is not added to the memory
 680          * event list yet, context is just being created.
 681          */
 682         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 683                                  MLX5_MR_BTREE_CACHE_N * 2,
 684                                  spawn->pci_dev->device.numa_node);
 685         if (err) {
 686                 err = rte_errno;
 687                 goto error;
 688         }
 689         mlx5_flow_counters_mng_init(sh);
 690         mlx5_flow_ipool_create(sh);
 691         /* Add device to memory callback list. */
 692         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 693         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 694                          sh, mem_event_cb);
 695         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 696         /* Add context to the global device list. */
 697         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 698 exit:
 699         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 700         return sh;
 701 error:
 702         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 703         MLX5_ASSERT(sh);
 704         if (sh->tis)
 705                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 706         if (sh->td)
 707                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 708         if (sh->pd)
 709                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 710         if (sh->ctx)
 711                 claim_zero(mlx5_glue->close_device(sh->ctx));
 712         if (sh->flow_id_pool)
 713                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 714         rte_free(sh);
 715         MLX5_ASSERT(err > 0);
 716         rte_errno = err;
 717         return NULL;
 718 }
 719
 720 /**
 721  * Free shared IB device context. Decrement counter and if zero free
 722  * all allocated resources and close handles.
 723  *
 724  * @param[in] sh
 725  *   Pointer to mlx5_ibv_shared object to free
 726  */
 727 static void
 728 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 729 {
 730         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 731 #ifdef RTE_LIBRTE_MLX5_DEBUG
 732         /* Check the object presence in the list. */
 733         struct mlx5_ibv_shared *lctx;
 734
 735         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 736                 if (lctx == sh)
 737                         break;
 738         MLX5_ASSERT(lctx);
 739         if (lctx != sh) {
 740                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 741                 goto exit;
 742         }
 743 #endif
 744         MLX5_ASSERT(sh);
 745         MLX5_ASSERT(sh->refcnt);
 746         /* Secondary process should not free the shared context. */
 747         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 748         if (--sh->refcnt)
 749                 goto exit;
 750         /* Remove from memory callback device list. */
 751         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 752         LIST_REMOVE(sh, mem_event_cb);
 753         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 754         /* Release created Memory Regions. */
 755         mlx5_mr_release_cache(&sh->share_cache);
 756         /* Remove context from the global device list. */
 757         LIST_REMOVE(sh, next);
 758         /*
 759          *  Ensure there is no async event handler installed.
 760          *  Only primary process handles async device events.
 761          **/
 762         mlx5_flow_counters_mng_close(sh);
 763         mlx5_flow_ipool_destroy(sh);
 764         MLX5_ASSERT(!sh->intr_cnt);
 765         if (sh->intr_cnt)
 766                 mlx5_intr_callback_unregister
 767                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 768 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 769         if (sh->devx_intr_cnt) {
 770                 if (sh->intr_handle_devx.fd)
 771                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 772                                           mlx5_dev_interrupt_handler_devx, sh);
 773                 if (sh->devx_comp)
 774                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 775         }
 776 #endif
 777         pthread_mutex_destroy(&sh->intr_mutex);
 778         if (sh->pd)
 779                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 780         if (sh->tis)
 781                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 782         if (sh->td)
 783                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 784         if (sh->ctx)
 785                 claim_zero(mlx5_glue->close_device(sh->ctx));
 786         if (sh->flow_id_pool)
 787                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 788         rte_free(sh);
 789 exit:
 790         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 791 }
 792
 793 /**
 794  * Destroy table hash list and all the root entries per domain.
 795  *
 796  * @param[in] priv
 797  *   Pointer to the private device data structure.
 798  */
 799 static void
 800 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 801 {
 802         struct mlx5_ibv_shared *sh = priv->sh;
 803         struct mlx5_flow_tbl_data_entry *tbl_data;
 804         union mlx5_flow_tbl_key table_key = {
 805                 {
 806                         .table_id = 0,
 807                         .reserved = 0,
 808                         .domain = 0,
 809                         .direction = 0,
 810                 }
 811         };
 812         struct mlx5_hlist_entry *pos;
 813
 814         if (!sh->flow_tbls)
 815                 return;
 816         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 817         if (pos) {
 818                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 819                                         entry);
 820                 MLX5_ASSERT(tbl_data);
 821                 mlx5_hlist_remove(sh->flow_tbls, pos);
 822                 rte_free(tbl_data);
 823         }
 824         table_key.direction = 1;
 825         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 826         if (pos) {
 827                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 828                                         entry);
 829                 MLX5_ASSERT(tbl_data);
 830                 mlx5_hlist_remove(sh->flow_tbls, pos);
 831                 rte_free(tbl_data);
 832         }
 833         table_key.direction = 0;
 834         table_key.domain = 1;
 835         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 836         if (pos) {
 837                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 838                                         entry);
 839                 MLX5_ASSERT(tbl_data);
 840                 mlx5_hlist_remove(sh->flow_tbls, pos);
 841                 rte_free(tbl_data);
 842         }
 843         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 844 }
 845
 846 /**
 847  * Initialize flow table hash list and create the root tables entry
 848  * for each domain.
 849  *
 850  * @param[in] priv
 851  *   Pointer to the private device data structure.
 852  *
 853  * @return
 854  *   Zero on success, positive error code otherwise.
 855  */
 856 static int
 857 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 858 {
 859         struct mlx5_ibv_shared *sh = priv->sh;
 860         char s[MLX5_HLIST_NAMESIZE];
 861         int err = 0;
 862
 863         MLX5_ASSERT(sh);
 864         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 865         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 866         if (!sh->flow_tbls) {
 867                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 868                 err = ENOMEM;
 869                 return err;
 870         }
 871 #ifndef HAVE_MLX5DV_DR
 872         /*
 873          * In case we have not DR support, the zero tables should be created
 874          * because DV expect to see them even if they cannot be created by
 875          * RDMA-CORE.
 876          */
 877         union mlx5_flow_tbl_key table_key = {
 878                 {
 879                         .table_id = 0,
 880                         .reserved = 0,
 881                         .domain = 0,
 882                         .direction = 0,
 883                 }
 884         };
 885         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 886                                                           sizeof(*tbl_data), 0);
 887
 888         if (!tbl_data) {
 889                 err = ENOMEM;
 890                 goto error;
 891         }
 892         tbl_data->entry.key = table_key.v64;
 893         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 894         if (err)
 895                 goto error;
 896         rte_atomic32_init(&tbl_data->tbl.refcnt);
 897         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 898         table_key.direction = 1;
 899         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 900         if (!tbl_data) {
 901                 err = ENOMEM;
 902                 goto error;
 903         }
 904         tbl_data->entry.key = table_key.v64;
 905         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 906         if (err)
 907                 goto error;
 908         rte_atomic32_init(&tbl_data->tbl.refcnt);
 909         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 910         table_key.direction = 0;
 911         table_key.domain = 1;
 912         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 913         if (!tbl_data) {
 914                 err = ENOMEM;
 915                 goto error;
 916         }
 917         tbl_data->entry.key = table_key.v64;
 918         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 919         if (err)
 920                 goto error;
 921         rte_atomic32_init(&tbl_data->tbl.refcnt);
 922         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 923         return err;
 924 error:
 925         mlx5_free_table_hash_list(priv);
 926 #endif /* HAVE_MLX5DV_DR */
 927         return err;
 928 }
 929
 930 /**
 931  * Initialize DR related data within private structure.
 932  * Routine checks the reference counter and does actual
 933  * resources creation/initialization only if counter is zero.
 934  *
 935  * @param[in] priv
 936  *   Pointer to the private device data structure.
 937  *
 938  * @return
 939  *   Zero on success, positive error code otherwise.
 940  */
 941 static int
 942 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
 943 {
 944         struct mlx5_ibv_shared *sh = priv->sh;
 945         char s[MLX5_HLIST_NAMESIZE];
 946         int err = 0;
 947
 948         if (!sh->flow_tbls)
 949                 err = mlx5_alloc_table_hash_list(priv);
 950         else
 951                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
 952                         (void *)sh->flow_tbls);
 953         if (err)
 954                 return err;
 955         /* Create tags hash list table. */
 956         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
 957         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
 958         if (!sh->tag_table) {
 959                 DRV_LOG(ERR, "tags with hash creation failed.\n");
 960                 err = ENOMEM;
 961                 goto error;
 962         }
 963 #ifdef HAVE_MLX5DV_DR
 964         void *domain;
 965
 966         if (sh->dv_refcnt) {
 967                 /* Shared DV/DR structures is already initialized. */
 968                 sh->dv_refcnt++;
 969                 priv->dr_shared = 1;
 970                 return 0;
 971         }
 972         /* Reference counter is zero, we should initialize structures. */
 973         domain = mlx5_glue->dr_create_domain(sh->ctx,
 974                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
 975         if (!domain) {
 976                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
 977                 err = errno;
 978                 goto error;
 979         }
 980         sh->rx_domain = domain;
 981         domain = mlx5_glue->dr_create_domain(sh->ctx,
 982                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
 983         if (!domain) {
 984                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
 985                 err = errno;
 986                 goto error;
 987         }
 988         pthread_mutex_init(&sh->dv_mutex, NULL);
 989         sh->tx_domain = domain;
 990 #ifdef HAVE_MLX5DV_DR_ESWITCH
 991         if (priv->config.dv_esw_en) {
 992                 domain  = mlx5_glue->dr_create_domain
 993                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
 994                 if (!domain) {
 995                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
 996                         err = errno;
 997                         goto error;
 998                 }
 999                 sh->fdb_domain = domain;
1000                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1001         }
1002 #endif
1003         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1004 #endif /* HAVE_MLX5DV_DR */
1005         sh->dv_refcnt++;
1006         priv->dr_shared = 1;
1007         return 0;
1008 error:
1009         /* Rollback the created objects. */
1010         if (sh->rx_domain) {
1011                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1012                 sh->rx_domain = NULL;
1013         }
1014         if (sh->tx_domain) {
1015                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1016                 sh->tx_domain = NULL;
1017         }
1018         if (sh->fdb_domain) {
1019                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1020                 sh->fdb_domain = NULL;
1021         }
1022         if (sh->esw_drop_action) {
1023                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1024                 sh->esw_drop_action = NULL;
1025         }
1026         if (sh->pop_vlan_action) {
1027                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1028                 sh->pop_vlan_action = NULL;
1029         }
1030         if (sh->tag_table) {
1031                 /* tags should be destroyed with flow before. */
1032                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1033                 sh->tag_table = NULL;
1034         }
1035         mlx5_free_table_hash_list(priv);
1036         return err;
1037 }
1038
1039 /**
1040  * Destroy DR related data within private structure.
1041  *
1042  * @param[in] priv
1043  *   Pointer to the private device data structure.
1044  */
1045 static void
1046 mlx5_free_shared_dr(struct mlx5_priv *priv)
1047 {
1048         struct mlx5_ibv_shared *sh;
1049
1050         if (!priv->dr_shared)
1051                 return;
1052         priv->dr_shared = 0;
1053         sh = priv->sh;
1054         MLX5_ASSERT(sh);
1055 #ifdef HAVE_MLX5DV_DR
1056         MLX5_ASSERT(sh->dv_refcnt);
1057         if (sh->dv_refcnt && --sh->dv_refcnt)
1058                 return;
1059         if (sh->rx_domain) {
1060                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1061                 sh->rx_domain = NULL;
1062         }
1063         if (sh->tx_domain) {
1064                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1065                 sh->tx_domain = NULL;
1066         }
1067 #ifdef HAVE_MLX5DV_DR_ESWITCH
1068         if (sh->fdb_domain) {
1069                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1070                 sh->fdb_domain = NULL;
1071         }
1072         if (sh->esw_drop_action) {
1073                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1074                 sh->esw_drop_action = NULL;
1075         }
1076 #endif
1077         if (sh->pop_vlan_action) {
1078                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1079                 sh->pop_vlan_action = NULL;
1080         }
1081         pthread_mutex_destroy(&sh->dv_mutex);
1082 #endif /* HAVE_MLX5DV_DR */
1083         if (sh->tag_table) {
1084                 /* tags should be destroyed with flow before. */
1085                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1086                 sh->tag_table = NULL;
1087         }
1088         mlx5_free_table_hash_list(priv);
1089 }
1090
1091 /**
1092  * Initialize shared data between primary and secondary process.
1093  *
1094  * A memzone is reserved by primary process and secondary processes attach to
1095  * the memzone.
1096  *
1097  * @return
1098  *   0 on success, a negative errno value otherwise and rte_errno is set.
1099  */
1100 static int
1101 mlx5_init_shared_data(void)
1102 {
1103         const struct rte_memzone *mz;
1104         int ret = 0;
1105
1106         rte_spinlock_lock(&mlx5_shared_data_lock);
1107         if (mlx5_shared_data == NULL) {
1108                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1109                         /* Allocate shared memory. */
1110                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1111                                                  sizeof(*mlx5_shared_data),
1112                                                  SOCKET_ID_ANY, 0);
1113                         if (mz == NULL) {
1114                                 DRV_LOG(ERR,
1115                                         "Cannot allocate mlx5 shared data");
1116                                 ret = -rte_errno;
1117                                 goto error;
1118                         }
1119                         mlx5_shared_data = mz->addr;
1120                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1121                         rte_spinlock_init(&mlx5_shared_data->lock);
1122                 } else {
1123                         /* Lookup allocated shared memory. */
1124                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1125                         if (mz == NULL) {
1126                                 DRV_LOG(ERR,
1127                                         "Cannot attach mlx5 shared data");
1128                                 ret = -rte_errno;
1129                                 goto error;
1130                         }
1131                         mlx5_shared_data = mz->addr;
1132                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1133                 }
1134         }
1135 error:
1136         rte_spinlock_unlock(&mlx5_shared_data_lock);
1137         return ret;
1138 }
1139
1140 /**
1141  * Retrieve integer value from environment variable.
1142  *
1143  * @param[in] name
1144  *   Environment variable name.
1145  *
1146  * @return
1147  *   Integer value, 0 if the variable is not set.
1148  */
1149 int
1150 mlx5_getenv_int(const char *name)
1151 {
1152         const char *val = getenv(name);
1153
1154         if (val == NULL)
1155                 return 0;
1156         return atoi(val);
1157 }
1158
1159 /**
1160  * Verbs callback to allocate a memory. This function should allocate the space
1161  * according to the size provided residing inside a huge page.
1162  * Please note that all allocation must respect the alignment from libmlx5
1163  * (i.e. currently sysconf(_SC_PAGESIZE)).
1164  *
1165  * @param[in] size
1166  *   The size in bytes of the memory to allocate.
1167  * @param[in] data
1168  *   A pointer to the callback data.
1169  *
1170  * @return
1171  *   Allocated buffer, NULL otherwise and rte_errno is set.
1172  */
1173 static void *
1174 mlx5_alloc_verbs_buf(size_t size, void *data)
1175 {
1176         struct mlx5_priv *priv = data;
1177         void *ret;
1178         size_t alignment = sysconf(_SC_PAGESIZE);
1179         unsigned int socket = SOCKET_ID_ANY;
1180
1181         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1182                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1183
1184                 socket = ctrl->socket;
1185         } else if (priv->verbs_alloc_ctx.type ==
1186                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1187                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1188
1189                 socket = ctrl->socket;
1190         }
1191         MLX5_ASSERT(data != NULL);
1192         ret = rte_malloc_socket(__func__, size, alignment, socket);
1193         if (!ret && size)
1194                 rte_errno = ENOMEM;
1195         return ret;
1196 }
1197
1198 /**
1199  * Verbs callback to free a memory.
1200  *
1201  * @param[in] ptr
1202  *   A pointer to the memory to free.
1203  * @param[in] data
1204  *   A pointer to the callback data.
1205  */
1206 static void
1207 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1208 {
1209         MLX5_ASSERT(data != NULL);
1210         rte_free(ptr);
1211 }
1212
1213 /**
1214  * DPDK callback to add udp tunnel port
1215  *
1216  * @param[in] dev
1217  *   A pointer to eth_dev
1218  * @param[in] udp_tunnel
1219  *   A pointer to udp tunnel
1220  *
1221  * @return
1222  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1223  */
1224 int
1225 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1226                          struct rte_eth_udp_tunnel *udp_tunnel)
1227 {
1228         MLX5_ASSERT(udp_tunnel != NULL);
1229         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1230             udp_tunnel->udp_port == 4789)
1231                 return 0;
1232         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1233             udp_tunnel->udp_port == 4790)
1234                 return 0;
1235         return -ENOTSUP;
1236 }
1237
1238 /**
1239  * Initialize process private data structure.
1240  *
1241  * @param dev
1242  *   Pointer to Ethernet device structure.
1243  *
1244  * @return
1245  *   0 on success, a negative errno value otherwise and rte_errno is set.
1246  */
1247 int
1248 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1249 {
1250         struct mlx5_priv *priv = dev->data->dev_private;
1251         struct mlx5_proc_priv *ppriv;
1252         size_t ppriv_size;
1253
1254         /*
1255          * UAR register table follows the process private structure. BlueFlame
1256          * registers for Tx queues are stored in the table.
1257          */
1258         ppriv_size =
1259                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1260         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1261                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1262         if (!ppriv) {
1263                 rte_errno = ENOMEM;
1264                 return -rte_errno;
1265         }
1266         ppriv->uar_table_sz = ppriv_size;
1267         dev->process_private = ppriv;
1268         return 0;
1269 }
1270
1271 /**
1272  * Un-initialize process private data structure.
1273  *
1274  * @param dev
1275  *   Pointer to Ethernet device structure.
1276  */
1277 static void
1278 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1279 {
1280         if (!dev->process_private)
1281                 return;
1282         rte_free(dev->process_private);
1283         dev->process_private = NULL;
1284 }
1285
1286 /**
1287  * DPDK callback to close the device.
1288  *
1289  * Destroy all queues and objects, free memory.
1290  *
1291  * @param dev
1292  *   Pointer to Ethernet device structure.
1293  */
1294 static void
1295 mlx5_dev_close(struct rte_eth_dev *dev)
1296 {
1297         struct mlx5_priv *priv = dev->data->dev_private;
1298         unsigned int i;
1299         int ret;
1300
1301         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1302                 dev->data->port_id,
1303                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1304         /* In case mlx5_dev_stop() has not been called. */
1305         mlx5_dev_interrupt_handler_uninstall(dev);
1306         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1307         /*
1308          * If default mreg copy action is removed at the stop stage,
1309          * the search will return none and nothing will be done anymore.
1310          */
1311         mlx5_flow_stop_default(dev);
1312         mlx5_traffic_disable(dev);
1313         /*
1314          * If all the flows are already flushed in the device stop stage,
1315          * then this will return directly without any action.
1316          */
1317         mlx5_flow_list_flush(dev, &priv->flows, true);
1318         mlx5_flow_meter_flush(dev, NULL);
1319         /* Free the intermediate buffers for flow creation. */
1320         mlx5_flow_free_intermediate(dev);
1321         /* Prevent crashes when queues are still in use. */
1322         dev->rx_pkt_burst = removed_rx_burst;
1323         dev->tx_pkt_burst = removed_tx_burst;
1324         rte_wmb();
1325         /* Disable datapath on secondary process. */
1326         mlx5_mp_req_stop_rxtx(dev);
1327         if (priv->rxqs != NULL) {
1328                 /* XXX race condition if mlx5_rx_burst() is still running. */
1329                 usleep(1000);
1330                 for (i = 0; (i != priv->rxqs_n); ++i)
1331                         mlx5_rxq_release(dev, i);
1332                 priv->rxqs_n = 0;
1333                 priv->rxqs = NULL;
1334         }
1335         if (priv->txqs != NULL) {
1336                 /* XXX race condition if mlx5_tx_burst() is still running. */
1337                 usleep(1000);
1338                 for (i = 0; (i != priv->txqs_n); ++i)
1339                         mlx5_txq_release(dev, i);
1340                 priv->txqs_n = 0;
1341                 priv->txqs = NULL;
1342         }
1343         mlx5_proc_priv_uninit(dev);
1344         if (priv->mreg_cp_tbl)
1345                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1346         mlx5_mprq_free_mp(dev);
1347         mlx5_free_shared_dr(priv);
1348         if (priv->rss_conf.rss_key != NULL)
1349                 rte_free(priv->rss_conf.rss_key);
1350         if (priv->reta_idx != NULL)
1351                 rte_free(priv->reta_idx);
1352         if (priv->config.vf)
1353                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1354                                        dev->data->mac_addrs,
1355                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1356         if (priv->nl_socket_route >= 0)
1357                 close(priv->nl_socket_route);
1358         if (priv->nl_socket_rdma >= 0)
1359                 close(priv->nl_socket_rdma);
1360         if (priv->vmwa_context)
1361                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1362         if (priv->sh) {
1363                 /*
1364                  * Free the shared context in last turn, because the cleanup
1365                  * routines above may use some shared fields, like
1366                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1367                  * ifindex if Netlink fails.
1368                  */
1369                 mlx5_free_shared_ibctx(priv->sh);
1370                 priv->sh = NULL;
1371         }
1372         ret = mlx5_hrxq_verify(dev);
1373         if (ret)
1374                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1375                         dev->data->port_id);
1376         ret = mlx5_ind_table_obj_verify(dev);
1377         if (ret)
1378                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1379                         dev->data->port_id);
1380         ret = mlx5_rxq_obj_verify(dev);
1381         if (ret)
1382                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1383                         dev->data->port_id);
1384         ret = mlx5_rxq_verify(dev);
1385         if (ret)
1386                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1387                         dev->data->port_id);
1388         ret = mlx5_txq_obj_verify(dev);
1389         if (ret)
1390                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1391                         dev->data->port_id);
1392         ret = mlx5_txq_verify(dev);
1393         if (ret)
1394                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1395                         dev->data->port_id);
1396         ret = mlx5_flow_verify(dev);
1397         if (ret)
1398                 DRV_LOG(WARNING, "port %u some flows still remain",
1399                         dev->data->port_id);
1400         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1401                 unsigned int c = 0;
1402                 uint16_t port_id;
1403
1404                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1405                         struct mlx5_priv *opriv =
1406                                 rte_eth_devices[port_id].data->dev_private;
1407
1408                         if (!opriv ||
1409                             opriv->domain_id != priv->domain_id ||
1410                             &rte_eth_devices[port_id] == dev)
1411                                 continue;
1412                         ++c;
1413                         break;
1414                 }
1415                 if (!c)
1416                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1417         }
1418         memset(priv, 0, sizeof(*priv));
1419         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1420         /*
1421          * Reset mac_addrs to NULL such that it is not freed as part of
1422          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1423          * it is freed when dev_private is freed.
1424          */
1425         dev->data->mac_addrs = NULL;
1426 }
1427
1428 const struct eth_dev_ops mlx5_dev_ops = {
1429         .dev_configure = mlx5_dev_configure,
1430         .dev_start = mlx5_dev_start,
1431         .dev_stop = mlx5_dev_stop,
1432         .dev_set_link_down = mlx5_set_link_down,
1433         .dev_set_link_up = mlx5_set_link_up,
1434         .dev_close = mlx5_dev_close,
1435         .promiscuous_enable = mlx5_promiscuous_enable,
1436         .promiscuous_disable = mlx5_promiscuous_disable,
1437         .allmulticast_enable = mlx5_allmulticast_enable,
1438         .allmulticast_disable = mlx5_allmulticast_disable,
1439         .link_update = mlx5_link_update,
1440         .stats_get = mlx5_stats_get,
1441         .stats_reset = mlx5_stats_reset,
1442         .xstats_get = mlx5_xstats_get,
1443         .xstats_reset = mlx5_xstats_reset,
1444         .xstats_get_names = mlx5_xstats_get_names,
1445         .fw_version_get = mlx5_fw_version_get,
1446         .dev_infos_get = mlx5_dev_infos_get,
1447         .read_clock = mlx5_read_clock,
1448         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1449         .vlan_filter_set = mlx5_vlan_filter_set,
1450         .rx_queue_setup = mlx5_rx_queue_setup,
1451         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1452         .tx_queue_setup = mlx5_tx_queue_setup,
1453         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1454         .rx_queue_release = mlx5_rx_queue_release,
1455         .tx_queue_release = mlx5_tx_queue_release,
1456         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1457         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1458         .mac_addr_remove = mlx5_mac_addr_remove,
1459         .mac_addr_add = mlx5_mac_addr_add,
1460         .mac_addr_set = mlx5_mac_addr_set,
1461         .set_mc_addr_list = mlx5_set_mc_addr_list,
1462         .mtu_set = mlx5_dev_set_mtu,
1463         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1464         .vlan_offload_set = mlx5_vlan_offload_set,
1465         .reta_update = mlx5_dev_rss_reta_update,
1466         .reta_query = mlx5_dev_rss_reta_query,
1467         .rss_hash_update = mlx5_rss_hash_update,
1468         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1469         .filter_ctrl = mlx5_dev_filter_ctrl,
1470         .rx_descriptor_status = mlx5_rx_descriptor_status,
1471         .tx_descriptor_status = mlx5_tx_descriptor_status,
1472         .rxq_info_get = mlx5_rxq_info_get,
1473         .txq_info_get = mlx5_txq_info_get,
1474         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1475         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1476         .rx_queue_count = mlx5_rx_queue_count,
1477         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1478         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1479         .is_removed = mlx5_is_removed,
1480         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1481         .get_module_info = mlx5_get_module_info,
1482         .get_module_eeprom = mlx5_get_module_eeprom,
1483         .hairpin_cap_get = mlx5_hairpin_cap_get,
1484         .mtr_ops_get = mlx5_flow_meter_ops_get,
1485 };
1486
1487 /* Available operations from secondary process. */
1488 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1489         .stats_get = mlx5_stats_get,
1490         .stats_reset = mlx5_stats_reset,
1491         .xstats_get = mlx5_xstats_get,
1492         .xstats_reset = mlx5_xstats_reset,
1493         .xstats_get_names = mlx5_xstats_get_names,
1494         .fw_version_get = mlx5_fw_version_get,
1495         .dev_infos_get = mlx5_dev_infos_get,
1496         .rx_descriptor_status = mlx5_rx_descriptor_status,
1497         .tx_descriptor_status = mlx5_tx_descriptor_status,
1498         .rxq_info_get = mlx5_rxq_info_get,
1499         .txq_info_get = mlx5_txq_info_get,
1500         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1501         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1502         .get_module_info = mlx5_get_module_info,
1503         .get_module_eeprom = mlx5_get_module_eeprom,
1504 };
1505
1506 /* Available operations in flow isolated mode. */
1507 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1508         .dev_configure = mlx5_dev_configure,
1509         .dev_start = mlx5_dev_start,
1510         .dev_stop = mlx5_dev_stop,
1511         .dev_set_link_down = mlx5_set_link_down,
1512         .dev_set_link_up = mlx5_set_link_up,
1513         .dev_close = mlx5_dev_close,
1514         .promiscuous_enable = mlx5_promiscuous_enable,
1515         .promiscuous_disable = mlx5_promiscuous_disable,
1516         .allmulticast_enable = mlx5_allmulticast_enable,
1517         .allmulticast_disable = mlx5_allmulticast_disable,
1518         .link_update = mlx5_link_update,
1519         .stats_get = mlx5_stats_get,
1520         .stats_reset = mlx5_stats_reset,
1521         .xstats_get = mlx5_xstats_get,
1522         .xstats_reset = mlx5_xstats_reset,
1523         .xstats_get_names = mlx5_xstats_get_names,
1524         .fw_version_get = mlx5_fw_version_get,
1525         .dev_infos_get = mlx5_dev_infos_get,
1526         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1527         .vlan_filter_set = mlx5_vlan_filter_set,
1528         .rx_queue_setup = mlx5_rx_queue_setup,
1529         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1530         .tx_queue_setup = mlx5_tx_queue_setup,
1531         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1532         .rx_queue_release = mlx5_rx_queue_release,
1533         .tx_queue_release = mlx5_tx_queue_release,
1534         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1535         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1536         .mac_addr_remove = mlx5_mac_addr_remove,
1537         .mac_addr_add = mlx5_mac_addr_add,
1538         .mac_addr_set = mlx5_mac_addr_set,
1539         .set_mc_addr_list = mlx5_set_mc_addr_list,
1540         .mtu_set = mlx5_dev_set_mtu,
1541         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1542         .vlan_offload_set = mlx5_vlan_offload_set,
1543         .filter_ctrl = mlx5_dev_filter_ctrl,
1544         .rx_descriptor_status = mlx5_rx_descriptor_status,
1545         .tx_descriptor_status = mlx5_tx_descriptor_status,
1546         .rxq_info_get = mlx5_rxq_info_get,
1547         .txq_info_get = mlx5_txq_info_get,
1548         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1549         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1550         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1551         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1552         .is_removed = mlx5_is_removed,
1553         .get_module_info = mlx5_get_module_info,
1554         .get_module_eeprom = mlx5_get_module_eeprom,
1555         .hairpin_cap_get = mlx5_hairpin_cap_get,
1556         .mtr_ops_get = mlx5_flow_meter_ops_get,
1557 };
1558
1559 /**
1560  * Verify and store value for device argument.
1561  *
1562  * @param[in] key
1563  *   Key argument to verify.
1564  * @param[in] val
1565  *   Value associated with key.
1566  * @param opaque
1567  *   User data.
1568  *
1569  * @return
1570  *   0 on success, a negative errno value otherwise and rte_errno is set.
1571  */
1572 static int
1573 mlx5_args_check(const char *key, const char *val, void *opaque)
1574 {
1575         struct mlx5_dev_config *config = opaque;
1576         unsigned long tmp;
1577
1578         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1579         if (!strcmp(MLX5_REPRESENTOR, key))
1580                 return 0;
1581         errno = 0;
1582         tmp = strtoul(val, NULL, 0);
1583         if (errno) {
1584                 rte_errno = errno;
1585                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1586                 return -rte_errno;
1587         }
1588         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1589                 config->cqe_comp = !!tmp;
1590         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1591                 config->cqe_pad = !!tmp;
1592         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1593                 config->hw_padding = !!tmp;
1594         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1595                 config->mprq.enabled = !!tmp;
1596         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1597                 config->mprq.stride_num_n = tmp;
1598         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1599                 config->mprq.stride_size_n = tmp;
1600         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1601                 config->mprq.max_memcpy_len = tmp;
1602         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1603                 config->mprq.min_rxqs_num = tmp;
1604         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1605                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1606                                  " converted to txq_inline_max", key);
1607                 config->txq_inline_max = tmp;
1608         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1609                 config->txq_inline_max = tmp;
1610         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1611                 config->txq_inline_min = tmp;
1612         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1613                 config->txq_inline_mpw = tmp;
1614         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1615                 config->txqs_inline = tmp;
1616         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1617                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1618         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1619                 config->mps = !!tmp;
1620         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1621                 if (tmp != MLX5_TXDB_CACHED &&
1622                     tmp != MLX5_TXDB_NCACHED &&
1623                     tmp != MLX5_TXDB_HEURISTIC) {
1624                         DRV_LOG(ERR, "invalid Tx doorbell "
1625                                      "mapping parameter");
1626                         rte_errno = EINVAL;
1627                         return -rte_errno;
1628                 }
1629                 config->dbnc = tmp;
1630         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1631                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1632         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1633                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1634                                  " converted to txq_inline_mpw", key);
1635                 config->txq_inline_mpw = tmp;
1636         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1637                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1638         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1639                 config->rx_vec_en = !!tmp;
1640         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1641                 config->l3_vxlan_en = !!tmp;
1642         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1643                 config->vf_nl_en = !!tmp;
1644         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1645                 config->dv_esw_en = !!tmp;
1646         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1647                 config->dv_flow_en = !!tmp;
1648         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1649                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1650                     tmp != MLX5_XMETA_MODE_META16 &&
1651                     tmp != MLX5_XMETA_MODE_META32) {
1652                         DRV_LOG(ERR, "invalid extensive "
1653                                      "metadata parameter");
1654                         rte_errno = EINVAL;
1655                         return -rte_errno;
1656                 }
1657                 config->dv_xmeta_en = tmp;
1658         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1659                 config->mr_ext_memseg_en = !!tmp;
1660         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1661                 config->max_dump_files_num = tmp;
1662         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1663                 config->lro.timeout = tmp;
1664         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1665                 DRV_LOG(DEBUG, "class argument is %s.", val);
1666         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1667                 config->log_hp_size = tmp;
1668         } else {
1669                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1670                 rte_errno = EINVAL;
1671                 return -rte_errno;
1672         }
1673         return 0;
1674 }
1675
1676 /**
1677  * Parse device parameters.
1678  *
1679  * @param config
1680  *   Pointer to device configuration structure.
1681  * @param devargs
1682  *   Device arguments structure.
1683  *
1684  * @return
1685  *   0 on success, a negative errno value otherwise and rte_errno is set.
1686  */
1687 static int
1688 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1689 {
1690         const char **params = (const char *[]){
1691                 MLX5_RXQ_CQE_COMP_EN,
1692                 MLX5_RXQ_CQE_PAD_EN,
1693                 MLX5_RXQ_PKT_PAD_EN,
1694                 MLX5_RX_MPRQ_EN,
1695                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1696                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1697                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1698                 MLX5_RXQS_MIN_MPRQ,
1699                 MLX5_TXQ_INLINE,
1700                 MLX5_TXQ_INLINE_MIN,
1701                 MLX5_TXQ_INLINE_MAX,
1702                 MLX5_TXQ_INLINE_MPW,
1703                 MLX5_TXQS_MIN_INLINE,
1704                 MLX5_TXQS_MAX_VEC,
1705                 MLX5_TXQ_MPW_EN,
1706                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1707                 MLX5_TXQ_MAX_INLINE_LEN,
1708                 MLX5_TX_DB_NC,
1709                 MLX5_TX_VEC_EN,
1710                 MLX5_RX_VEC_EN,
1711                 MLX5_L3_VXLAN_EN,
1712                 MLX5_VF_NL_EN,
1713                 MLX5_DV_ESW_EN,
1714                 MLX5_DV_FLOW_EN,
1715                 MLX5_DV_XMETA_EN,
1716                 MLX5_MR_EXT_MEMSEG_EN,
1717                 MLX5_REPRESENTOR,
1718                 MLX5_MAX_DUMP_FILES_NUM,
1719                 MLX5_LRO_TIMEOUT_USEC,
1720                 MLX5_CLASS_ARG_NAME,
1721                 MLX5_HP_BUF_SIZE,
1722                 NULL,
1723         };
1724         struct rte_kvargs *kvlist;
1725         int ret = 0;
1726         int i;
1727
1728         if (devargs == NULL)
1729                 return 0;
1730         /* Following UGLY cast is done to pass checkpatch. */
1731         kvlist = rte_kvargs_parse(devargs->args, params);
1732         if (kvlist == NULL) {
1733                 rte_errno = EINVAL;
1734                 return -rte_errno;
1735         }
1736         /* Process parameters. */
1737         for (i = 0; (params[i] != NULL); ++i) {
1738                 if (rte_kvargs_count(kvlist, params[i])) {
1739                         ret = rte_kvargs_process(kvlist, params[i],
1740                                                  mlx5_args_check, config);
1741                         if (ret) {
1742                                 rte_errno = EINVAL;
1743                                 rte_kvargs_free(kvlist);
1744                                 return -rte_errno;
1745                         }
1746                 }
1747         }
1748         rte_kvargs_free(kvlist);
1749         return 0;
1750 }
1751
1752 static struct rte_pci_driver mlx5_driver;
1753
1754 /**
1755  * PMD global initialization.
1756  *
1757  * Independent from individual device, this function initializes global
1758  * per-PMD data structures distinguishing primary and secondary processes.
1759  * Hence, each initialization is called once per a process.
1760  *
1761  * @return
1762  *   0 on success, a negative errno value otherwise and rte_errno is set.
1763  */
1764 static int
1765 mlx5_init_once(void)
1766 {
1767         struct mlx5_shared_data *sd;
1768         struct mlx5_local_data *ld = &mlx5_local_data;
1769         int ret = 0;
1770
1771         if (mlx5_init_shared_data())
1772                 return -rte_errno;
1773         sd = mlx5_shared_data;
1774         MLX5_ASSERT(sd);
1775         rte_spinlock_lock(&sd->lock);
1776         switch (rte_eal_process_type()) {
1777         case RTE_PROC_PRIMARY:
1778                 if (sd->init_done)
1779                         break;
1780                 LIST_INIT(&sd->mem_event_cb_list);
1781                 rte_rwlock_init(&sd->mem_event_rwlock);
1782                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1783                                                 mlx5_mr_mem_event_cb, NULL);
1784                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1785                                            mlx5_mp_primary_handle);
1786                 if (ret)
1787                         goto out;
1788                 sd->init_done = true;
1789                 break;
1790         case RTE_PROC_SECONDARY:
1791                 if (ld->init_done)
1792                         break;
1793                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1794                                              mlx5_mp_secondary_handle);
1795                 if (ret)
1796                         goto out;
1797                 ++sd->secondary_cnt;
1798                 ld->init_done = true;
1799                 break;
1800         default:
1801                 break;
1802         }
1803 out:
1804         rte_spinlock_unlock(&sd->lock);
1805         return ret;
1806 }
1807
1808 /**
1809  * Configures the minimal amount of data to inline into WQE
1810  * while sending packets.
1811  *
1812  * - the txq_inline_min has the maximal priority, if this
1813  *   key is specified in devargs
1814  * - if DevX is enabled the inline mode is queried from the
1815  *   device (HCA attributes and NIC vport context if needed).
1816  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1817  *   and none (0 bytes) for other NICs
1818  *
1819  * @param spawn
1820  *   Verbs device parameters (name, port, switch_info) to spawn.
1821  * @param config
1822  *   Device configuration parameters.
1823  */
1824 static void
1825 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1826                     struct mlx5_dev_config *config)
1827 {
1828         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1829                 /* Application defines size of inlined data explicitly. */
1830                 switch (spawn->pci_dev->id.device_id) {
1831                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1832                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1833                         if (config->txq_inline_min <
1834                                        (int)MLX5_INLINE_HSIZE_L2) {
1835                                 DRV_LOG(DEBUG,
1836                                         "txq_inline_mix aligned to minimal"
1837                                         " ConnectX-4 required value %d",
1838                                         (int)MLX5_INLINE_HSIZE_L2);
1839                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1840                         }
1841                         break;
1842                 }
1843                 goto exit;
1844         }
1845         if (config->hca_attr.eth_net_offloads) {
1846                 /* We have DevX enabled, inline mode queried successfully. */
1847                 switch (config->hca_attr.wqe_inline_mode) {
1848                 case MLX5_CAP_INLINE_MODE_L2:
1849                         /* outer L2 header must be inlined. */
1850                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1851                         goto exit;
1852                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1853                         /* No inline data are required by NIC. */
1854                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1855                         config->hw_vlan_insert =
1856                                 config->hca_attr.wqe_vlan_insert;
1857                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1858                         goto exit;
1859                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1860                         /* inline mode is defined by NIC vport context. */
1861                         if (!config->hca_attr.eth_virt)
1862                                 break;
1863                         switch (config->hca_attr.vport_inline_mode) {
1864                         case MLX5_INLINE_MODE_NONE:
1865                                 config->txq_inline_min =
1866                                         MLX5_INLINE_HSIZE_NONE;
1867                                 goto exit;
1868                         case MLX5_INLINE_MODE_L2:
1869                                 config->txq_inline_min =
1870                                         MLX5_INLINE_HSIZE_L2;
1871                                 goto exit;
1872                         case MLX5_INLINE_MODE_IP:
1873                                 config->txq_inline_min =
1874                                         MLX5_INLINE_HSIZE_L3;
1875                                 goto exit;
1876                         case MLX5_INLINE_MODE_TCP_UDP:
1877                                 config->txq_inline_min =
1878                                         MLX5_INLINE_HSIZE_L4;
1879                                 goto exit;
1880                         case MLX5_INLINE_MODE_INNER_L2:
1881                                 config->txq_inline_min =
1882                                         MLX5_INLINE_HSIZE_INNER_L2;
1883                                 goto exit;
1884                         case MLX5_INLINE_MODE_INNER_IP:
1885                                 config->txq_inline_min =
1886                                         MLX5_INLINE_HSIZE_INNER_L3;
1887                                 goto exit;
1888                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1889                                 config->txq_inline_min =
1890                                         MLX5_INLINE_HSIZE_INNER_L4;
1891                                 goto exit;
1892                         }
1893                 }
1894         }
1895         /*
1896          * We get here if we are unable to deduce
1897          * inline data size with DevX. Try PCI ID
1898          * to determine old NICs.
1899          */
1900         switch (spawn->pci_dev->id.device_id) {
1901         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1902         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1903         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1904         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1905                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1906                 config->hw_vlan_insert = 0;
1907                 break;
1908         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1909         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1910         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1911         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1912                 /*
1913                  * These NICs support VLAN insertion from WQE and
1914                  * report the wqe_vlan_insert flag. But there is the bug
1915                  * and PFC control may be broken, so disable feature.
1916                  */
1917                 config->hw_vlan_insert = 0;
1918                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1919                 break;
1920         default:
1921                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1922                 break;
1923         }
1924 exit:
1925         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1926 }
1927
1928 /**
1929  * Configures the metadata mask fields in the shared context.
1930  *
1931  * @param [in] dev
1932  *   Pointer to Ethernet device.
1933  */
1934 static void
1935 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1936 {
1937         struct mlx5_priv *priv = dev->data->dev_private;
1938         struct mlx5_ibv_shared *sh = priv->sh;
1939         uint32_t meta, mark, reg_c0;
1940
1941         reg_c0 = ~priv->vport_meta_mask;
1942         switch (priv->config.dv_xmeta_en) {
1943         case MLX5_XMETA_MODE_LEGACY:
1944                 meta = UINT32_MAX;
1945                 mark = MLX5_FLOW_MARK_MASK;
1946                 break;
1947         case MLX5_XMETA_MODE_META16:
1948                 meta = reg_c0 >> rte_bsf32(reg_c0);
1949                 mark = MLX5_FLOW_MARK_MASK;
1950                 break;
1951         case MLX5_XMETA_MODE_META32:
1952                 meta = UINT32_MAX;
1953                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1954                 break;
1955         default:
1956                 meta = 0;
1957                 mark = 0;
1958                 MLX5_ASSERT(false);
1959                 break;
1960         }
1961         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1962                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1963                                  sh->dv_mark_mask, mark);
1964         else
1965                 sh->dv_mark_mask = mark;
1966         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1967                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1968                                  sh->dv_meta_mask, meta);
1969         else
1970                 sh->dv_meta_mask = meta;
1971         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1972                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1973                                  sh->dv_meta_mask, reg_c0);
1974         else
1975                 sh->dv_regc0_mask = reg_c0;
1976         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1977         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1978         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1979         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1980 }
1981
1982 /**
1983  * Allocate page of door-bells and register it using DevX API.
1984  *
1985  * @param [in] dev
1986  *   Pointer to Ethernet device.
1987  *
1988  * @return
1989  *   Pointer to new page on success, NULL otherwise.
1990  */
1991 static struct mlx5_devx_dbr_page *
1992 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1993 {
1994         struct mlx5_priv *priv = dev->data->dev_private;
1995         struct mlx5_devx_dbr_page *page;
1996
1997         /* Allocate space for door-bell page and management data. */
1998         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1999                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2000         if (!page) {
2001                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2002                         dev->data->port_id);
2003                 return NULL;
2004         }
2005         /* Register allocated memory. */
2006         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2007                                               MLX5_DBR_PAGE_SIZE, 0);
2008         if (!page->umem) {
2009                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2010                         dev->data->port_id);
2011                 rte_free(page);
2012                 return NULL;
2013         }
2014         return page;
2015 }
2016
2017 /**
2018  * Find the next available door-bell, allocate new page if needed.
2019  *
2020  * @param [in] dev
2021  *   Pointer to Ethernet device.
2022  * @param [out] dbr_page
2023  *   Door-bell page containing the page data.
2024  *
2025  * @return
2026  *   Door-bell address offset on success, a negative error value otherwise.
2027  */
2028 int64_t
2029 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2030 {
2031         struct mlx5_priv *priv = dev->data->dev_private;
2032         struct mlx5_devx_dbr_page *page = NULL;
2033         uint32_t i, j;
2034
2035         LIST_FOREACH(page, &priv->dbrpgs, next)
2036                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2037                         break;
2038         if (!page) { /* No page with free door-bell exists. */
2039                 page = mlx5_alloc_dbr_page(dev);
2040                 if (!page) /* Failed to allocate new page. */
2041                         return (-1);
2042                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2043         }
2044         /* Loop to find bitmap part with clear bit. */
2045         for (i = 0;
2046              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2047              i++)
2048                 ; /* Empty. */
2049         /* Find the first clear bit. */
2050         j = rte_bsf64(~page->dbr_bitmap[i]);
2051         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2052         page->dbr_bitmap[i] |= (1 << j);
2053         page->dbr_count++;
2054         *dbr_page = page;
2055         return (((i * 64) + j) * sizeof(uint64_t));
2056 }
2057
2058 /**
2059  * Release a door-bell record.
2060  *
2061  * @param [in] dev
2062  *   Pointer to Ethernet device.
2063  * @param [in] umem_id
2064  *   UMEM ID of page containing the door-bell record to release.
2065  * @param [in] offset
2066  *   Offset of door-bell record in page.
2067  *
2068  * @return
2069  *   0 on success, a negative error value otherwise.
2070  */
2071 int32_t
2072 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2073 {
2074         struct mlx5_priv *priv = dev->data->dev_private;
2075         struct mlx5_devx_dbr_page *page = NULL;
2076         int ret = 0;
2077
2078         LIST_FOREACH(page, &priv->dbrpgs, next)
2079                 /* Find the page this address belongs to. */
2080                 if (page->umem->umem_id == umem_id)
2081                         break;
2082         if (!page)
2083                 return -EINVAL;
2084         page->dbr_count--;
2085         if (!page->dbr_count) {
2086                 /* Page not used, free it and remove from list. */
2087                 LIST_REMOVE(page, next);
2088                 if (page->umem)
2089                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2090                 rte_free(page);
2091         } else {
2092                 /* Mark in bitmap that this door-bell is not in use. */
2093                 offset /= MLX5_DBR_SIZE;
2094                 int i = offset / 64;
2095                 int j = offset % 64;
2096
2097                 page->dbr_bitmap[i] &= ~(1 << j);
2098         }
2099         return ret;
2100 }
2101
2102 int
2103 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2104 {
2105         static const char *const dynf_names[] = {
2106                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2107                 RTE_MBUF_DYNFLAG_METADATA_NAME
2108         };
2109         unsigned int i;
2110
2111         if (n < RTE_DIM(dynf_names))
2112                 return -ENOMEM;
2113         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2114                 if (names[i] == NULL)
2115                         return -EINVAL;
2116                 strcpy(names[i], dynf_names[i]);
2117         }
2118         return RTE_DIM(dynf_names);
2119 }
2120
2121 /**
2122  * Check sibling device configurations.
2123  *
2124  * Sibling devices sharing the Infiniband device context
2125  * should have compatible configurations. This regards
2126  * representors and bonding slaves.
2127  *
2128  * @param priv
2129  *   Private device descriptor.
2130  * @param config
2131  *   Configuration of the device is going to be created.
2132  *
2133  * @return
2134  *   0 on success, EINVAL otherwise
2135  */
2136 static int
2137 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2138                               struct mlx5_dev_config *config)
2139 {
2140         struct mlx5_ibv_shared *sh = priv->sh;
2141         struct mlx5_dev_config *sh_conf = NULL;
2142         uint16_t port_id;
2143
2144         MLX5_ASSERT(sh);
2145         /* Nothing to compare for the single/first device. */
2146         if (sh->refcnt == 1)
2147                 return 0;
2148         /* Find the device with shared context. */
2149         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2150                 struct mlx5_priv *opriv =
2151                         rte_eth_devices[port_id].data->dev_private;
2152
2153                 if (opriv && opriv != priv && opriv->sh == sh) {
2154                         sh_conf = &opriv->config;
2155                         break;
2156                 }
2157         }
2158         if (!sh_conf)
2159                 return 0;
2160         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2161                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2162                              " for shared %s context", sh->ibdev_name);
2163                 rte_errno = EINVAL;
2164                 return rte_errno;
2165         }
2166         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2167                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2168                              " for shared %s context", sh->ibdev_name);
2169                 rte_errno = EINVAL;
2170                 return rte_errno;
2171         }
2172         return 0;
2173 }
2174 /**
2175  * Spawn an Ethernet device from Verbs information.
2176  *
2177  * @param dpdk_dev
2178  *   Backing DPDK device.
2179  * @param spawn
2180  *   Verbs device parameters (name, port, switch_info) to spawn.
2181  * @param config
2182  *   Device configuration parameters.
2183  *
2184  * @return
2185  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2186  *   is set. The following errors are defined:
2187  *
2188  *   EBUSY: device is not supposed to be spawned.
2189  *   EEXIST: device is already spawned
2190  */
2191 static struct rte_eth_dev *
2192 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2193                struct mlx5_dev_spawn_data *spawn,
2194                struct mlx5_dev_config config)
2195 {
2196         const struct mlx5_switch_info *switch_info = &spawn->info;
2197         struct mlx5_ibv_shared *sh = NULL;
2198         struct ibv_port_attr port_attr;
2199         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2200         struct rte_eth_dev *eth_dev = NULL;
2201         struct mlx5_priv *priv = NULL;
2202         int err = 0;
2203         unsigned int hw_padding = 0;
2204         unsigned int mps;
2205         unsigned int cqe_comp;
2206         unsigned int cqe_pad = 0;
2207         unsigned int tunnel_en = 0;
2208         unsigned int mpls_en = 0;
2209         unsigned int swp = 0;
2210         unsigned int mprq = 0;
2211         unsigned int mprq_min_stride_size_n = 0;
2212         unsigned int mprq_max_stride_size_n = 0;
2213         unsigned int mprq_min_stride_num_n = 0;
2214         unsigned int mprq_max_stride_num_n = 0;
2215         struct rte_ether_addr mac;
2216         char name[RTE_ETH_NAME_MAX_LEN];
2217         int own_domain_id = 0;
2218         uint16_t port_id;
2219         unsigned int i;
2220 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2221         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2222 #endif
2223
2224         /* Determine if this port representor is supposed to be spawned. */
2225         if (switch_info->representor && dpdk_dev->devargs) {
2226                 struct rte_eth_devargs eth_da;
2227
2228                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2229                 if (err) {
2230                         rte_errno = -err;
2231                         DRV_LOG(ERR, "failed to process device arguments: %s",
2232                                 strerror(rte_errno));
2233                         return NULL;
2234                 }
2235                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2236                         if (eth_da.representor_ports[i] ==
2237                             (uint16_t)switch_info->port_name)
2238                                 break;
2239                 if (i == eth_da.nb_representor_ports) {
2240                         rte_errno = EBUSY;
2241                         return NULL;
2242                 }
2243         }
2244         /* Build device name. */
2245         if (spawn->pf_bond <  0) {
2246                 /* Single device. */
2247                 if (!switch_info->representor)
2248                         strlcpy(name, dpdk_dev->name, sizeof(name));
2249                 else
2250                         snprintf(name, sizeof(name), "%s_representor_%u",
2251                                  dpdk_dev->name, switch_info->port_name);
2252         } else {
2253                 /* Bonding device. */
2254                 if (!switch_info->representor)
2255                         snprintf(name, sizeof(name), "%s_%s",
2256                                  dpdk_dev->name, spawn->ibv_dev->name);
2257                 else
2258                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2259                                  dpdk_dev->name, spawn->ibv_dev->name,
2260                                  switch_info->port_name);
2261         }
2262         /* check if the device is already spawned */
2263         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2264                 rte_errno = EEXIST;
2265                 return NULL;
2266         }
2267         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2268         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2269                 struct mlx5_mp_id mp_id;
2270
2271                 eth_dev = rte_eth_dev_attach_secondary(name);
2272                 if (eth_dev == NULL) {
2273                         DRV_LOG(ERR, "can not attach rte ethdev");
2274                         rte_errno = ENOMEM;
2275                         return NULL;
2276                 }
2277                 eth_dev->device = dpdk_dev;
2278                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2279                 err = mlx5_proc_priv_init(eth_dev);
2280                 if (err)
2281                         return NULL;
2282                 mp_id.port_id = eth_dev->data->port_id;
2283                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2284                 /* Receive command fd from primary process */
2285                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2286                 if (err < 0)
2287                         return NULL;
2288                 /* Remap UAR for Tx queues. */
2289                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2290                 if (err)
2291                         return NULL;
2292                 /*
2293                  * Ethdev pointer is still required as input since
2294                  * the primary device is not accessible from the
2295                  * secondary process.
2296                  */
2297                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2298                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2299                 return eth_dev;
2300         }
2301         /*
2302          * Some parameters ("tx_db_nc" in particularly) are needed in
2303          * advance to create dv/verbs device context. We proceed the
2304          * devargs here to get ones, and later proceed devargs again
2305          * to override some hardware settings.
2306          */
2307         err = mlx5_args(&config, dpdk_dev->devargs);
2308         if (err) {
2309                 err = rte_errno;
2310                 DRV_LOG(ERR, "failed to process device arguments: %s",
2311                         strerror(rte_errno));
2312                 goto error;
2313         }
2314         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2315         if (!sh)
2316                 return NULL;
2317         config.devx = sh->devx;
2318 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2319         config.dest_tir = 1;
2320 #endif
2321 #ifdef HAVE_IBV_MLX5_MOD_SWP
2322         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2323 #endif
2324         /*
2325          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2326          * as all ConnectX-5 devices.
2327          */
2328 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2329         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2330 #endif
2331 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2332         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2333 #endif
2334         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2335         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2336                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2337                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2338                         mps = MLX5_MPW_ENHANCED;
2339                 } else {
2340                         DRV_LOG(DEBUG, "MPW is supported");
2341                         mps = MLX5_MPW;
2342                 }
2343         } else {
2344                 DRV_LOG(DEBUG, "MPW isn't supported");
2345                 mps = MLX5_MPW_DISABLED;
2346         }
2347 #ifdef HAVE_IBV_MLX5_MOD_SWP
2348         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2349                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2350         DRV_LOG(DEBUG, "SWP support: %u", swp);
2351 #endif
2352         config.swp = !!swp;
2353 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2354         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2355                 struct mlx5dv_striding_rq_caps mprq_caps =
2356                         dv_attr.striding_rq_caps;
2357
2358                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2359                         mprq_caps.min_single_stride_log_num_of_bytes);
2360                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2361                         mprq_caps.max_single_stride_log_num_of_bytes);
2362                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2363                         mprq_caps.min_single_wqe_log_num_of_strides);
2364                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2365                         mprq_caps.max_single_wqe_log_num_of_strides);
2366                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2367                         mprq_caps.supported_qpts);
2368                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2369                 mprq = 1;
2370                 mprq_min_stride_size_n =
2371                         mprq_caps.min_single_stride_log_num_of_bytes;
2372                 mprq_max_stride_size_n =
2373                         mprq_caps.max_single_stride_log_num_of_bytes;
2374                 mprq_min_stride_num_n =
2375                         mprq_caps.min_single_wqe_log_num_of_strides;
2376                 mprq_max_stride_num_n =
2377                         mprq_caps.max_single_wqe_log_num_of_strides;
2378         }
2379 #endif
2380         if (RTE_CACHE_LINE_SIZE == 128 &&
2381             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2382                 cqe_comp = 0;
2383         else
2384                 cqe_comp = 1;
2385         config.cqe_comp = cqe_comp;
2386 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2387         /* Whether device supports 128B Rx CQE padding. */
2388         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2389                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2390 #endif
2391 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2392         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2393                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2394                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2395                              (dv_attr.tunnel_offloads_caps &
2396                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2397                              (dv_attr.tunnel_offloads_caps &
2398                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2399         }
2400         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2401                 tunnel_en ? "" : "not ");
2402 #else
2403         DRV_LOG(WARNING,
2404                 "tunnel offloading disabled due to old OFED/rdma-core version");
2405 #endif
2406         config.tunnel_en = tunnel_en;
2407 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2408         mpls_en = ((dv_attr.tunnel_offloads_caps &
2409                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2410                    (dv_attr.tunnel_offloads_caps &
2411                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2412         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2413                 mpls_en ? "" : "not ");
2414 #else
2415         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2416                 " old OFED/rdma-core version or firmware configuration");
2417 #endif
2418         config.mpls_en = mpls_en;
2419         /* Check port status. */
2420         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2421         if (err) {
2422                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2423                 goto error;
2424         }
2425         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2426                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2427                 err = EINVAL;
2428                 goto error;
2429         }
2430         if (port_attr.state != IBV_PORT_ACTIVE)
2431                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2432                         mlx5_glue->port_state_str(port_attr.state),
2433                         port_attr.state);
2434         /* Allocate private eth device data. */
2435         priv = rte_zmalloc("ethdev private structure",
2436                            sizeof(*priv),
2437                            RTE_CACHE_LINE_SIZE);
2438         if (priv == NULL) {
2439                 DRV_LOG(ERR, "priv allocation failure");
2440                 err = ENOMEM;
2441                 goto error;
2442         }
2443         priv->sh = sh;
2444         priv->ibv_port = spawn->ibv_port;
2445         priv->pci_dev = spawn->pci_dev;
2446         priv->mtu = RTE_ETHER_MTU;
2447         priv->mp_id.port_id = port_id;
2448         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2449 #ifndef RTE_ARCH_64
2450         /* Initialize UAR access locks for 32bit implementations. */
2451         rte_spinlock_init(&priv->uar_lock_cq);
2452         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2453                 rte_spinlock_init(&priv->uar_lock[i]);
2454 #endif
2455         /* Some internal functions rely on Netlink sockets, open them now. */
2456         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2457         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2458         priv->representor = !!switch_info->representor;
2459         priv->master = !!switch_info->master;
2460         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2461         priv->vport_meta_tag = 0;
2462         priv->vport_meta_mask = 0;
2463         priv->pf_bond = spawn->pf_bond;
2464 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2465         /*
2466          * The DevX port query API is implemented. E-Switch may use
2467          * either vport or reg_c[0] metadata register to match on
2468          * vport index. The engaged part of metadata register is
2469          * defined by mask.
2470          */
2471         if (switch_info->representor || switch_info->master) {
2472                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2473                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2474                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2475                                                  &devx_port);
2476                 if (err) {
2477                         DRV_LOG(WARNING,
2478                                 "can't query devx port %d on device %s",
2479                                 spawn->ibv_port, spawn->ibv_dev->name);
2480                         devx_port.comp_mask = 0;
2481                 }
2482         }
2483         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2484                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2485                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2486                 if (!priv->vport_meta_mask) {
2487                         DRV_LOG(ERR, "vport zero mask for port %d"
2488                                      " on bonding device %s",
2489                                      spawn->ibv_port, spawn->ibv_dev->name);
2490                         err = ENOTSUP;
2491                         goto error;
2492                 }
2493                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2494                         DRV_LOG(ERR, "invalid vport tag for port %d"
2495                                      " on bonding device %s",
2496                                      spawn->ibv_port, spawn->ibv_dev->name);
2497                         err = ENOTSUP;
2498                         goto error;
2499                 }
2500         }
2501         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2502                 priv->vport_id = devx_port.vport_num;
2503         } else if (spawn->pf_bond >= 0) {
2504                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2505                              " on bonding device %s",
2506                              spawn->ibv_port, spawn->ibv_dev->name);
2507                 err = ENOTSUP;
2508                 goto error;
2509         } else {
2510                 /* Suppose vport index in compatible way. */
2511                 priv->vport_id = switch_info->representor ?
2512                                  switch_info->port_name + 1 : -1;
2513         }
2514 #else
2515         /*
2516          * Kernel/rdma_core support single E-Switch per PF configurations
2517          * only and vport_id field contains the vport index for
2518          * associated VF, which is deduced from representor port name.
2519          * For example, let's have the IB device port 10, it has
2520          * attached network device eth0, which has port name attribute
2521          * pf0vf2, we can deduce the VF number as 2, and set vport index
2522          * as 3 (2+1). This assigning schema should be changed if the
2523          * multiple E-Switch instances per PF configurations or/and PCI
2524          * subfunctions are added.
2525          */
2526         priv->vport_id = switch_info->representor ?
2527                          switch_info->port_name + 1 : -1;
2528 #endif
2529         /* representor_id field keeps the unmodified VF index. */
2530         priv->representor_id = switch_info->representor ?
2531                                switch_info->port_name : -1;
2532         /*
2533          * Look for sibling devices in order to reuse their switch domain
2534          * if any, otherwise allocate one.
2535          */
2536         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2537                 const struct mlx5_priv *opriv =
2538                         rte_eth_devices[port_id].data->dev_private;
2539
2540                 if (!opriv ||
2541                     opriv->sh != priv->sh ||
2542                         opriv->domain_id ==
2543                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2544                         continue;
2545                 priv->domain_id = opriv->domain_id;
2546                 break;
2547         }
2548         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2549                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2550                 if (err) {
2551                         err = rte_errno;
2552                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2553                                 strerror(rte_errno));
2554                         goto error;
2555                 }
2556                 own_domain_id = 1;
2557         }
2558         /* Override some values set by hardware configuration. */
2559         mlx5_args(&config, dpdk_dev->devargs);
2560         err = mlx5_dev_check_sibling_config(priv, &config);
2561         if (err)
2562                 goto error;
2563         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2564                             IBV_DEVICE_RAW_IP_CSUM);
2565         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2566                 (config.hw_csum ? "" : "not "));
2567 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2568         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2569         DRV_LOG(DEBUG, "counters are not supported");
2570 #endif
2571 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2572         if (config.dv_flow_en) {
2573                 DRV_LOG(WARNING, "DV flow is not supported");
2574                 config.dv_flow_en = 0;
2575         }
2576 #endif
2577         config.ind_table_max_size =
2578                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2579         /*
2580          * Remove this check once DPDK supports larger/variable
2581          * indirection tables.
2582          */
2583         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2584                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2585         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2586                 config.ind_table_max_size);
2587         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2588                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2589         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2590                 (config.hw_vlan_strip ? "" : "not "));
2591         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2592                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2593         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2594                 (config.hw_fcs_strip ? "" : "not "));
2595 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2596         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2597 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2598         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2599                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2600 #endif
2601         if (config.hw_padding && !hw_padding) {
2602                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2603                 config.hw_padding = 0;
2604         } else if (config.hw_padding) {
2605                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2606         }
2607         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2608                       (sh->device_attr.tso_caps.supported_qpts &
2609                        (1 << IBV_QPT_RAW_PACKET)));
2610         if (config.tso)
2611                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2612         /*
2613          * MPW is disabled by default, while the Enhanced MPW is enabled
2614          * by default.
2615          */
2616         if (config.mps == MLX5_ARG_UNSET)
2617                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2618                                                           MLX5_MPW_DISABLED;
2619         else
2620                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2621         DRV_LOG(INFO, "%sMPS is %s",
2622                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2623                 config.mps == MLX5_MPW ? "legacy " : "",
2624                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2625         if (config.cqe_comp && !cqe_comp) {
2626                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2627                 config.cqe_comp = 0;
2628         }
2629         if (config.cqe_pad && !cqe_pad) {
2630                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2631                 config.cqe_pad = 0;
2632         } else if (config.cqe_pad) {
2633                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2634         }
2635         if (config.devx) {
2636                 priv->counter_fallback = 0;
2637                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2638                 if (err) {
2639                         err = -err;
2640                         goto error;
2641                 }
2642                 if (!config.hca_attr.flow_counters_dump)
2643                         priv->counter_fallback = 1;
2644 #ifndef HAVE_IBV_DEVX_ASYNC
2645                 priv->counter_fallback = 1;
2646 #endif
2647                 if (priv->counter_fallback)
2648                         DRV_LOG(INFO, "Use fall-back DV counter management");
2649                 /* Check for LRO support. */
2650                 if (config.dest_tir && config.hca_attr.lro_cap &&
2651                     config.dv_flow_en) {
2652                         /* TBD check tunnel lro caps. */
2653                         config.lro.supported = config.hca_attr.lro_cap;
2654                         DRV_LOG(DEBUG, "Device supports LRO");
2655                         /*
2656                          * If LRO timeout is not configured by application,
2657                          * use the minimal supported value.
2658                          */
2659                         if (!config.lro.timeout)
2660                                 config.lro.timeout =
2661                                 config.hca_attr.lro_timer_supported_periods[0];
2662                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2663                                 config.lro.timeout);
2664                 }
2665 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2666                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2667                     config.dv_flow_en) {
2668                         uint8_t reg_c_mask =
2669                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2670                         /*
2671                          * Meter needs two REG_C's for color match and pre-sfx
2672                          * flow match. Here get the REG_C for color match.
2673                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2674                          */
2675                         reg_c_mask &= 0xfc;
2676                         if (__builtin_popcount(reg_c_mask) < 1) {
2677                                 priv->mtr_en = 0;
2678                                 DRV_LOG(WARNING, "No available register for"
2679                                         " meter.");
2680                         } else {
2681                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2682                                                       REG_C_0;
2683                                 priv->mtr_en = 1;
2684                                 priv->mtr_reg_share =
2685                                       config.hca_attr.qos.flow_meter_reg_share;
2686                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2687                                         priv->mtr_color_reg);
2688                         }
2689                 }
2690 #endif
2691         }
2692         if (config.mprq.enabled && mprq) {
2693                 if (config.mprq.stride_num_n &&
2694                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2695                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2696                         config.mprq.stride_num_n =
2697                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2698                                                 mprq_min_stride_num_n),
2699                                         mprq_max_stride_num_n);
2700                         DRV_LOG(WARNING,
2701                                 "the number of strides"
2702                                 " for Multi-Packet RQ is out of range,"
2703                                 " setting default value (%u)",
2704                                 1 << config.mprq.stride_num_n);
2705                 }
2706                 if (config.mprq.stride_size_n &&
2707                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2708                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2709                         config.mprq.stride_size_n =
2710                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2711                                                 mprq_min_stride_size_n),
2712                                         mprq_max_stride_size_n);
2713                         DRV_LOG(WARNING,
2714                                 "the size of a stride"
2715                                 " for Multi-Packet RQ is out of range,"
2716                                 " setting default value (%u)",
2717                                 1 << config.mprq.stride_size_n);
2718                 }
2719                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2720                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2721         } else if (config.mprq.enabled && !mprq) {
2722                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2723                 config.mprq.enabled = 0;
2724         }
2725         if (config.max_dump_files_num == 0)
2726                 config.max_dump_files_num = 128;
2727         eth_dev = rte_eth_dev_allocate(name);
2728         if (eth_dev == NULL) {
2729                 DRV_LOG(ERR, "can not allocate rte ethdev");
2730                 err = ENOMEM;
2731                 goto error;
2732         }
2733         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2734         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2735         if (priv->representor) {
2736                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2737                 eth_dev->data->representor_id = priv->representor_id;
2738         }
2739         /*
2740          * Store associated network device interface index. This index
2741          * is permanent throughout the lifetime of device. So, we may store
2742          * the ifindex here and use the cached value further.
2743          */
2744         MLX5_ASSERT(spawn->ifindex);
2745         priv->if_index = spawn->ifindex;
2746         eth_dev->data->dev_private = priv;
2747         priv->dev_data = eth_dev->data;
2748         eth_dev->data->mac_addrs = priv->mac;
2749         eth_dev->device = dpdk_dev;
2750         /* Configure the first MAC address by default. */
2751         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2752                 DRV_LOG(ERR,
2753                         "port %u cannot get MAC address, is mlx5_en"
2754                         " loaded? (errno: %s)",
2755                         eth_dev->data->port_id, strerror(rte_errno));
2756                 err = ENODEV;
2757                 goto error;
2758         }
2759         DRV_LOG(INFO,
2760                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2761                 eth_dev->data->port_id,
2762                 mac.addr_bytes[0], mac.addr_bytes[1],
2763                 mac.addr_bytes[2], mac.addr_bytes[3],
2764                 mac.addr_bytes[4], mac.addr_bytes[5]);
2765 #ifdef RTE_LIBRTE_MLX5_DEBUG
2766         {
2767                 char ifname[IF_NAMESIZE];
2768
2769                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2770                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2771                                 eth_dev->data->port_id, ifname);
2772                 else
2773                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2774                                 eth_dev->data->port_id);
2775         }
2776 #endif
2777         /* Get actual MTU if possible. */
2778         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2779         if (err) {
2780                 err = rte_errno;
2781                 goto error;
2782         }
2783         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2784                 priv->mtu);
2785         /* Initialize burst functions to prevent crashes before link-up. */
2786         eth_dev->rx_pkt_burst = removed_rx_burst;
2787         eth_dev->tx_pkt_burst = removed_tx_burst;
2788         eth_dev->dev_ops = &mlx5_dev_ops;
2789         /* Register MAC address. */
2790         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2791         if (config.vf && config.vf_nl_en)
2792                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2793                                       mlx5_ifindex(eth_dev),
2794                                       eth_dev->data->mac_addrs,
2795                                       MLX5_MAX_MAC_ADDRESSES);
2796         TAILQ_INIT(&priv->flows);
2797         TAILQ_INIT(&priv->ctrl_flows);
2798         TAILQ_INIT(&priv->flow_meters);
2799         TAILQ_INIT(&priv->flow_meter_profiles);
2800         /* Hint libmlx5 to use PMD allocator for data plane resources */
2801         struct mlx5dv_ctx_allocators alctr = {
2802                 .alloc = &mlx5_alloc_verbs_buf,
2803                 .free = &mlx5_free_verbs_buf,
2804                 .data = priv,
2805         };
2806         mlx5_glue->dv_set_context_attr(sh->ctx,
2807                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2808                                        (void *)((uintptr_t)&alctr));
2809         /* Bring Ethernet device up. */
2810         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2811                 eth_dev->data->port_id);
2812         mlx5_set_link_up(eth_dev);
2813         /*
2814          * Even though the interrupt handler is not installed yet,
2815          * interrupts will still trigger on the async_fd from
2816          * Verbs context returned by ibv_open_device().
2817          */
2818         mlx5_link_update(eth_dev, 0);
2819 #ifdef HAVE_MLX5DV_DR_ESWITCH
2820         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2821               (switch_info->representor || switch_info->master)))
2822                 config.dv_esw_en = 0;
2823 #else
2824         config.dv_esw_en = 0;
2825 #endif
2826         /* Detect minimal data bytes to inline. */
2827         mlx5_set_min_inline(spawn, &config);
2828         /* Store device configuration on private structure. */
2829         priv->config = config;
2830         /* Create context for virtual machine VLAN workaround. */
2831         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2832         if (config.dv_flow_en) {
2833                 err = mlx5_alloc_shared_dr(priv);
2834                 if (err)
2835                         goto error;
2836                 /*
2837                  * RSS id is shared with meter flow id. Meter flow id can only
2838                  * use the 24 MSB of the register.
2839                  */
2840                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2841                                      MLX5_MTR_COLOR_BITS);
2842                 if (!priv->qrss_id_pool) {
2843                         DRV_LOG(ERR, "can't create flow id pool");
2844                         err = ENOMEM;
2845                         goto error;
2846                 }
2847         }
2848         /* Supported Verbs flow priority number detection. */
2849         err = mlx5_flow_discover_priorities(eth_dev);
2850         if (err < 0) {
2851                 err = -err;
2852                 goto error;
2853         }
2854         priv->config.flow_prio = err;
2855         if (!priv->config.dv_esw_en &&
2856             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2857                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2858                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2859                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2860         }
2861         mlx5_set_metadata_mask(eth_dev);
2862         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2863             !priv->sh->dv_regc0_mask) {
2864                 DRV_LOG(ERR, "metadata mode %u is not supported "
2865                              "(no metadata reg_c[0] is available)",
2866                              priv->config.dv_xmeta_en);
2867                         err = ENOTSUP;
2868                         goto error;
2869         }
2870         /*
2871          * Allocate the buffer for flow creating, just once.
2872          * The allocation must be done before any flow creating.
2873          */
2874         mlx5_flow_alloc_intermediate(eth_dev);
2875         /* Query availibility of metadata reg_c's. */
2876         err = mlx5_flow_discover_mreg_c(eth_dev);
2877         if (err < 0) {
2878                 err = -err;
2879                 goto error;
2880         }
2881         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2882                 DRV_LOG(DEBUG,
2883                         "port %u extensive metadata register is not supported",
2884                         eth_dev->data->port_id);
2885                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2886                         DRV_LOG(ERR, "metadata mode %u is not supported "
2887                                      "(no metadata registers available)",
2888                                      priv->config.dv_xmeta_en);
2889                         err = ENOTSUP;
2890                         goto error;
2891                 }
2892         }
2893         if (priv->config.dv_flow_en &&
2894             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2895             mlx5_flow_ext_mreg_supported(eth_dev) &&
2896             priv->sh->dv_regc0_mask) {
2897                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2898                                                       MLX5_FLOW_MREG_HTABLE_SZ);
2899                 if (!priv->mreg_cp_tbl) {
2900                         err = ENOMEM;
2901                         goto error;
2902                 }
2903         }
2904         return eth_dev;
2905 error:
2906         if (priv) {
2907                 if (priv->mreg_cp_tbl)
2908                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2909                 if (priv->sh)
2910                         mlx5_free_shared_dr(priv);
2911                 if (priv->nl_socket_route >= 0)
2912                         close(priv->nl_socket_route);
2913                 if (priv->nl_socket_rdma >= 0)
2914                         close(priv->nl_socket_rdma);
2915                 if (priv->vmwa_context)
2916                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
2917                 if (priv->qrss_id_pool)
2918                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
2919                 if (own_domain_id)
2920                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2921                 rte_free(priv);
2922                 if (eth_dev != NULL)
2923                         eth_dev->data->dev_private = NULL;
2924         }
2925         if (eth_dev != NULL) {
2926                 /* mac_addrs must not be freed alone because part of dev_private */
2927                 eth_dev->data->mac_addrs = NULL;
2928                 rte_eth_dev_release_port(eth_dev);
2929         }
2930         if (sh)
2931                 mlx5_free_shared_ibctx(sh);
2932         MLX5_ASSERT(err > 0);
2933         rte_errno = err;
2934         return NULL;
2935 }
2936
2937 /**
2938  * Comparison callback to sort device data.
2939  *
2940  * This is meant to be used with qsort().
2941  *
2942  * @param a[in]
2943  *   Pointer to pointer to first data object.
2944  * @param b[in]
2945  *   Pointer to pointer to second data object.
2946  *
2947  * @return
2948  *   0 if both objects are equal, less than 0 if the first argument is less
2949  *   than the second, greater than 0 otherwise.
2950  */
2951 static int
2952 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2953 {
2954         const struct mlx5_switch_info *si_a =
2955                 &((const struct mlx5_dev_spawn_data *)a)->info;
2956         const struct mlx5_switch_info *si_b =
2957                 &((const struct mlx5_dev_spawn_data *)b)->info;
2958         int ret;
2959
2960         /* Master device first. */
2961         ret = si_b->master - si_a->master;
2962         if (ret)
2963                 return ret;
2964         /* Then representor devices. */
2965         ret = si_b->representor - si_a->representor;
2966         if (ret)
2967                 return ret;
2968         /* Unidentified devices come last in no specific order. */
2969         if (!si_a->representor)
2970                 return 0;
2971         /* Order representors by name. */
2972         return si_a->port_name - si_b->port_name;
2973 }
2974
2975 /**
2976  * Match PCI information for possible slaves of bonding device.
2977  *
2978  * @param[in] ibv_dev
2979  *   Pointer to Infiniband device structure.
2980  * @param[in] pci_dev
2981  *   Pointer to PCI device structure to match PCI address.
2982  * @param[in] nl_rdma
2983  *   Netlink RDMA group socket handle.
2984  *
2985  * @return
2986  *   negative value if no bonding device found, otherwise
2987  *   positive index of slave PF in bonding.
2988  */
2989 static int
2990 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2991                            const struct rte_pci_device *pci_dev,
2992                            int nl_rdma)
2993 {
2994         char ifname[IF_NAMESIZE + 1];
2995         unsigned int ifindex;
2996         unsigned int np, i;
2997         FILE *file = NULL;
2998         int pf = -1;
2999
3000         /*
3001          * Try to get master device name. If something goes
3002          * wrong suppose the lack of kernel support and no
3003          * bonding devices.
3004          */
3005         if (nl_rdma < 0)
3006                 return -1;
3007         if (!strstr(ibv_dev->name, "bond"))
3008                 return -1;
3009         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3010         if (!np)
3011                 return -1;
3012         /*
3013          * The Master device might not be on the predefined
3014          * port (not on port index 1, it is not garanted),
3015          * we have to scan all Infiniband device port and
3016          * find master.
3017          */
3018         for (i = 1; i <= np; ++i) {
3019                 /* Check whether Infiniband port is populated. */
3020                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3021                 if (!ifindex)
3022                         continue;
3023                 if (!if_indextoname(ifindex, ifname))
3024                         continue;
3025                 /* Try to read bonding slave names from sysfs. */
3026                 MKSTR(slaves,
3027                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3028                 file = fopen(slaves, "r");
3029                 if (file)
3030                         break;
3031         }
3032         if (!file)
3033                 return -1;
3034         /* Use safe format to check maximal buffer length. */
3035         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3036         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3037                 char tmp_str[IF_NAMESIZE + 32];
3038                 struct rte_pci_addr pci_addr;
3039                 struct mlx5_switch_info info;
3040
3041                 /* Process slave interface names in the loop. */
3042                 snprintf(tmp_str, sizeof(tmp_str),
3043                          "/sys/class/net/%s", ifname);
3044                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3045                         DRV_LOG(WARNING, "can not get PCI address"
3046                                          " for netdev \"%s\"", ifname);
3047                         continue;
3048                 }
3049                 if (pci_dev->addr.domain != pci_addr.domain ||
3050                     pci_dev->addr.bus != pci_addr.bus ||
3051                     pci_dev->addr.devid != pci_addr.devid ||
3052                     pci_dev->addr.function != pci_addr.function)
3053                         continue;
3054                 /* Slave interface PCI address match found. */
3055                 fclose(file);
3056                 snprintf(tmp_str, sizeof(tmp_str),
3057                          "/sys/class/net/%s/phys_port_name", ifname);
3058                 file = fopen(tmp_str, "rb");
3059                 if (!file)
3060                         break;
3061                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3062                 if (fscanf(file, "%32s", tmp_str) == 1)
3063                         mlx5_translate_port_name(tmp_str, &info);
3064                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3065                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3066                         pf = info.port_name;
3067                 break;
3068         }
3069         if (file)
3070                 fclose(file);
3071         return pf;
3072 }
3073
3074 /**
3075  * DPDK callback to register a PCI device.
3076  *
3077  * This function spawns Ethernet devices out of a given PCI device.
3078  *
3079  * @param[in] pci_drv
3080  *   PCI driver structure (mlx5_driver).
3081  * @param[in] pci_dev
3082  *   PCI device information.
3083  *
3084  * @return
3085  *   0 on success, a negative errno value otherwise and rte_errno is set.
3086  */
3087 static int
3088 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3089                struct rte_pci_device *pci_dev)
3090 {
3091         struct ibv_device **ibv_list;
3092         /*
3093          * Number of found IB Devices matching with requested PCI BDF.
3094          * nd != 1 means there are multiple IB devices over the same
3095          * PCI device and we have representors and master.
3096          */
3097         unsigned int nd = 0;
3098         /*
3099          * Number of found IB device Ports. nd = 1 and np = 1..n means
3100          * we have the single multiport IB device, and there may be
3101          * representors attached to some of found ports.
3102          */
3103         unsigned int np = 0;
3104         /*
3105          * Number of DPDK ethernet devices to Spawn - either over
3106          * multiple IB devices or multiple ports of single IB device.
3107          * Actually this is the number of iterations to spawn.
3108          */
3109         unsigned int ns = 0;
3110         /*
3111          * Bonding device
3112          *   < 0 - no bonding device (single one)
3113          *  >= 0 - bonding device (value is slave PF index)
3114          */
3115         int bd = -1;
3116         struct mlx5_dev_spawn_data *list = NULL;
3117         struct mlx5_dev_config dev_config;
3118         int ret;
3119
3120         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3121                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3122                         " driver.");
3123                 return 1;
3124         }
3125         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3126                 mlx5_pmd_socket_init();
3127         ret = mlx5_init_once();
3128         if (ret) {
3129                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3130                         strerror(rte_errno));
3131                 return -rte_errno;
3132         }
3133         MLX5_ASSERT(pci_drv == &mlx5_driver);
3134         errno = 0;
3135         ibv_list = mlx5_glue->get_device_list(&ret);
3136         if (!ibv_list) {
3137                 rte_errno = errno ? errno : ENOSYS;
3138                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3139                 return -rte_errno;
3140         }
3141         /*
3142          * First scan the list of all Infiniband devices to find
3143          * matching ones, gathering into the list.
3144          */
3145         struct ibv_device *ibv_match[ret + 1];
3146         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3147         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3148         unsigned int i;
3149
3150         while (ret-- > 0) {
3151                 struct rte_pci_addr pci_addr;
3152
3153                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3154                 bd = mlx5_device_bond_pci_match
3155                                 (ibv_list[ret], pci_dev, nl_rdma);
3156                 if (bd >= 0) {
3157                         /*
3158                          * Bonding device detected. Only one match is allowed,
3159                          * the bonding is supported over multi-port IB device,
3160                          * there should be no matches on representor PCI
3161                          * functions or non VF LAG bonding devices with
3162                          * specified address.
3163                          */
3164                         if (nd) {
3165                                 DRV_LOG(ERR,
3166                                         "multiple PCI match on bonding device"
3167                                         "\"%s\" found", ibv_list[ret]->name);
3168                                 rte_errno = ENOENT;
3169                                 ret = -rte_errno;
3170                                 goto exit;
3171                         }
3172                         DRV_LOG(INFO, "PCI information matches for"
3173                                       " slave %d bonding device \"%s\"",
3174                                       bd, ibv_list[ret]->name);
3175                         ibv_match[nd++] = ibv_list[ret];
3176                         break;
3177                 }
3178                 if (mlx5_dev_to_pci_addr
3179                         (ibv_list[ret]->ibdev_path, &pci_addr))
3180                         continue;
3181                 if (pci_dev->addr.domain != pci_addr.domain ||
3182                     pci_dev->addr.bus != pci_addr.bus ||
3183                     pci_dev->addr.devid != pci_addr.devid ||
3184                     pci_dev->addr.function != pci_addr.function)
3185                         continue;
3186                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3187                         ibv_list[ret]->name);
3188                 ibv_match[nd++] = ibv_list[ret];
3189         }
3190         ibv_match[nd] = NULL;
3191         if (!nd) {
3192                 /* No device matches, just complain and bail out. */
3193                 DRV_LOG(WARNING,
3194                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3195                         " are kernel drivers loaded?",
3196                         pci_dev->addr.domain, pci_dev->addr.bus,
3197                         pci_dev->addr.devid, pci_dev->addr.function);
3198                 rte_errno = ENOENT;
3199                 ret = -rte_errno;
3200                 goto exit;
3201         }
3202         if (nd == 1) {
3203                 /*
3204                  * Found single matching device may have multiple ports.
3205                  * Each port may be representor, we have to check the port
3206                  * number and check the representors existence.
3207                  */
3208                 if (nl_rdma >= 0)
3209                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3210                 if (!np)
3211                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3212                                          " ports number", ibv_match[0]->name);
3213                 if (bd >= 0 && !np) {
3214                         DRV_LOG(ERR, "can not get ports"
3215                                      " for bonding device");
3216                         rte_errno = ENOENT;
3217                         ret = -rte_errno;
3218                         goto exit;
3219                 }
3220         }
3221 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3222         if (bd >= 0) {
3223                 /*
3224                  * This may happen if there is VF LAG kernel support and
3225                  * application is compiled with older rdma_core library.
3226                  */
3227                 DRV_LOG(ERR,
3228                         "No kernel/verbs support for VF LAG bonding found.");
3229                 rte_errno = ENOTSUP;
3230                 ret = -rte_errno;
3231                 goto exit;
3232         }
3233 #endif
3234         /*
3235          * Now we can determine the maximal
3236          * amount of devices to be spawned.
3237          */
3238         list = rte_zmalloc("device spawn data",
3239                          sizeof(struct mlx5_dev_spawn_data) *
3240                          (np ? np : nd),
3241                          RTE_CACHE_LINE_SIZE);
3242         if (!list) {
3243                 DRV_LOG(ERR, "spawn data array allocation failure");
3244                 rte_errno = ENOMEM;
3245                 ret = -rte_errno;
3246                 goto exit;
3247         }
3248         if (bd >= 0 || np > 1) {
3249                 /*
3250                  * Single IB device with multiple ports found,
3251                  * it may be E-Switch master device and representors.
3252                  * We have to perform identification trough the ports.
3253                  */
3254                 MLX5_ASSERT(nl_rdma >= 0);
3255                 MLX5_ASSERT(ns == 0);
3256                 MLX5_ASSERT(nd == 1);
3257                 MLX5_ASSERT(np);
3258                 for (i = 1; i <= np; ++i) {
3259                         list[ns].max_port = np;
3260                         list[ns].ibv_port = i;
3261                         list[ns].ibv_dev = ibv_match[0];
3262                         list[ns].eth_dev = NULL;
3263                         list[ns].pci_dev = pci_dev;
3264                         list[ns].pf_bond = bd;
3265                         list[ns].ifindex = mlx5_nl_ifindex
3266                                         (nl_rdma, list[ns].ibv_dev->name, i);
3267                         if (!list[ns].ifindex) {
3268                                 /*
3269                                  * No network interface index found for the
3270                                  * specified port, it means there is no
3271                                  * representor on this port. It's OK,
3272                                  * there can be disabled ports, for example
3273                                  * if sriov_numvfs < sriov_totalvfs.
3274                                  */
3275                                 continue;
3276                         }
3277                         ret = -1;
3278                         if (nl_route >= 0)
3279                                 ret = mlx5_nl_switch_info
3280                                                (nl_route,
3281                                                 list[ns].ifindex,
3282                                                 &list[ns].info);
3283                         if (ret || (!list[ns].info.representor &&
3284                                     !list[ns].info.master)) {
3285                                 /*
3286                                  * We failed to recognize representors with
3287                                  * Netlink, let's try to perform the task
3288                                  * with sysfs.
3289                                  */
3290                                 ret =  mlx5_sysfs_switch_info
3291                                                 (list[ns].ifindex,
3292                                                  &list[ns].info);
3293                         }
3294                         if (!ret && bd >= 0) {
3295                                 switch (list[ns].info.name_type) {
3296                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3297                                         if (list[ns].info.port_name == bd)
3298                                                 ns++;
3299                                         break;
3300                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3301                                         if (list[ns].info.pf_num == bd)
3302                                                 ns++;
3303                                         break;
3304                                 default:
3305                                         break;
3306                                 }
3307                                 continue;
3308                         }
3309                         if (!ret && (list[ns].info.representor ^
3310                                      list[ns].info.master))
3311                                 ns++;
3312                 }
3313                 if (!ns) {
3314                         DRV_LOG(ERR,
3315                                 "unable to recognize master/representors"
3316                                 " on the IB device with multiple ports");
3317                         rte_errno = ENOENT;
3318                         ret = -rte_errno;
3319                         goto exit;
3320                 }
3321         } else {
3322                 /*
3323                  * The existence of several matching entries (nd > 1) means
3324                  * port representors have been instantiated. No existing Verbs
3325                  * call nor sysfs entries can tell them apart, this can only
3326                  * be done through Netlink calls assuming kernel drivers are
3327                  * recent enough to support them.
3328                  *
3329                  * In the event of identification failure through Netlink,
3330                  * try again through sysfs, then:
3331                  *
3332                  * 1. A single IB device matches (nd == 1) with single
3333                  *    port (np=0/1) and is not a representor, assume
3334                  *    no switch support.
3335                  *
3336                  * 2. Otherwise no safe assumptions can be made;
3337                  *    complain louder and bail out.
3338                  */
3339                 np = 1;
3340                 for (i = 0; i != nd; ++i) {
3341                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3342                         list[ns].max_port = 1;
3343                         list[ns].ibv_port = 1;
3344                         list[ns].ibv_dev = ibv_match[i];
3345                         list[ns].eth_dev = NULL;
3346                         list[ns].pci_dev = pci_dev;
3347                         list[ns].pf_bond = -1;
3348                         list[ns].ifindex = 0;
3349                         if (nl_rdma >= 0)
3350                                 list[ns].ifindex = mlx5_nl_ifindex
3351                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3352                         if (!list[ns].ifindex) {
3353                                 char ifname[IF_NAMESIZE];
3354
3355                                 /*
3356                                  * Netlink failed, it may happen with old
3357                                  * ib_core kernel driver (before 4.16).
3358                                  * We can assume there is old driver because
3359                                  * here we are processing single ports IB
3360                                  * devices. Let's try sysfs to retrieve
3361                                  * the ifindex. The method works for
3362                                  * master device only.
3363                                  */
3364                                 if (nd > 1) {
3365                                         /*
3366                                          * Multiple devices found, assume
3367                                          * representors, can not distinguish
3368                                          * master/representor and retrieve
3369                                          * ifindex via sysfs.
3370                                          */
3371                                         continue;
3372                                 }
3373                                 ret = mlx5_get_master_ifname
3374                                         (ibv_match[i]->ibdev_path, &ifname);
3375                                 if (!ret)
3376                                         list[ns].ifindex =
3377                                                 if_nametoindex(ifname);
3378                                 if (!list[ns].ifindex) {
3379                                         /*
3380                                          * No network interface index found
3381                                          * for the specified device, it means
3382                                          * there it is neither representor
3383                                          * nor master.
3384                                          */
3385                                         continue;
3386                                 }
3387                         }
3388                         ret = -1;
3389                         if (nl_route >= 0)
3390                                 ret = mlx5_nl_switch_info
3391                                                (nl_route,
3392                                                 list[ns].ifindex,
3393                                                 &list[ns].info);
3394                         if (ret || (!list[ns].info.representor &&
3395                                     !list[ns].info.master)) {
3396                                 /*
3397                                  * We failed to recognize representors with
3398                                  * Netlink, let's try to perform the task
3399                                  * with sysfs.
3400                                  */
3401                                 ret =  mlx5_sysfs_switch_info
3402                                                 (list[ns].ifindex,
3403                                                  &list[ns].info);
3404                         }
3405                         if (!ret && (list[ns].info.representor ^
3406                                      list[ns].info.master)) {
3407                                 ns++;
3408                         } else if ((nd == 1) &&
3409                                    !list[ns].info.representor &&
3410                                    !list[ns].info.master) {
3411                                 /*
3412                                  * Single IB device with
3413                                  * one physical port and
3414                                  * attached network device.
3415                                  * May be SRIOV is not enabled
3416                                  * or there is no representors.
3417                                  */
3418                                 DRV_LOG(INFO, "no E-Switch support detected");
3419                                 ns++;
3420                                 break;
3421                         }
3422                 }
3423                 if (!ns) {
3424                         DRV_LOG(ERR,
3425                                 "unable to recognize master/representors"
3426                                 " on the multiple IB devices");
3427                         rte_errno = ENOENT;
3428                         ret = -rte_errno;
3429                         goto exit;
3430                 }
3431         }
3432         MLX5_ASSERT(ns);
3433         /*
3434          * Sort list to probe devices in natural order for users convenience
3435          * (i.e. master first, then representors from lowest to highest ID).
3436          */
3437         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3438         /* Default configuration. */
3439         dev_config = (struct mlx5_dev_config){
3440                 .hw_padding = 0,
3441                 .mps = MLX5_ARG_UNSET,
3442                 .dbnc = MLX5_ARG_UNSET,
3443                 .rx_vec_en = 1,
3444                 .txq_inline_max = MLX5_ARG_UNSET,
3445                 .txq_inline_min = MLX5_ARG_UNSET,
3446                 .txq_inline_mpw = MLX5_ARG_UNSET,
3447                 .txqs_inline = MLX5_ARG_UNSET,
3448                 .vf_nl_en = 1,
3449                 .mr_ext_memseg_en = 1,
3450                 .mprq = {
3451                         .enabled = 0, /* Disabled by default. */
3452                         .stride_num_n = 0,
3453                         .stride_size_n = 0,
3454                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3455                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3456                 },
3457                 .dv_esw_en = 1,
3458                 .dv_flow_en = 1,
3459                 .log_hp_size = MLX5_ARG_UNSET,
3460         };
3461         /* Device specific configuration. */
3462         switch (pci_dev->id.device_id) {
3463         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3464         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3465         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3466         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3467         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3468         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3469         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3470                 dev_config.vf = 1;
3471                 break;
3472         default:
3473                 break;
3474         }
3475         for (i = 0; i != ns; ++i) {
3476                 uint32_t restore;
3477
3478                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3479                                                  &list[i],
3480                                                  dev_config);
3481                 if (!list[i].eth_dev) {
3482                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3483                                 break;
3484                         /* Device is disabled or already spawned. Ignore it. */
3485                         continue;
3486                 }
3487                 restore = list[i].eth_dev->data->dev_flags;
3488                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3489                 /* Restore non-PCI flags cleared by the above call. */
3490                 list[i].eth_dev->data->dev_flags |= restore;
3491                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3492                 rte_eth_dev_probing_finish(list[i].eth_dev);
3493         }
3494         if (i != ns) {
3495                 DRV_LOG(ERR,
3496                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3497                         " encountering an error: %s",
3498                         pci_dev->addr.domain, pci_dev->addr.bus,
3499                         pci_dev->addr.devid, pci_dev->addr.function,
3500                         strerror(rte_errno));
3501                 ret = -rte_errno;
3502                 /* Roll back. */
3503                 while (i--) {
3504                         if (!list[i].eth_dev)
3505                                 continue;
3506                         mlx5_dev_close(list[i].eth_dev);
3507                         /* mac_addrs must not be freed because in dev_private */
3508                         list[i].eth_dev->data->mac_addrs = NULL;
3509                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3510                 }
3511                 /* Restore original error. */
3512                 rte_errno = -ret;
3513         } else {
3514                 ret = 0;
3515         }
3516 exit:
3517         /*
3518          * Do the routine cleanup:
3519          * - close opened Netlink sockets
3520          * - free allocated spawn data array
3521          * - free the Infiniband device list
3522          */
3523         if (nl_rdma >= 0)
3524                 close(nl_rdma);
3525         if (nl_route >= 0)
3526                 close(nl_route);
3527         if (list)
3528                 rte_free(list);
3529         MLX5_ASSERT(ibv_list);
3530         mlx5_glue->free_device_list(ibv_list);
3531         return ret;
3532 }
3533
3534 /**
3535  * Look for the ethernet device belonging to mlx5 driver.
3536  *
3537  * @param[in] port_id
3538  *   port_id to start looking for device.
3539  * @param[in] pci_dev
3540  *   Pointer to the hint PCI device. When device is being probed
3541  *   the its siblings (master and preceding representors might
3542  *   not have assigned driver yet (because the mlx5_pci_probe()
3543  *   is not completed yet, for this case match on hint PCI
3544  *   device may be used to detect sibling device.
3545  *
3546  * @return
3547  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3548  */
3549 uint16_t
3550 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3551 {
3552         while (port_id < RTE_MAX_ETHPORTS) {
3553                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3554
3555                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3556                     dev->device &&
3557                     (dev->device == &pci_dev->device ||
3558                      (dev->device->driver &&
3559                      dev->device->driver->name &&
3560                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3561                         break;
3562                 port_id++;
3563         }
3564         if (port_id >= RTE_MAX_ETHPORTS)
3565                 return RTE_MAX_ETHPORTS;
3566         return port_id;
3567 }
3568
3569 /**
3570  * DPDK callback to remove a PCI device.
3571  *
3572  * This function removes all Ethernet devices belong to a given PCI device.
3573  *
3574  * @param[in] pci_dev
3575  *   Pointer to the PCI device.
3576  *
3577  * @return
3578  *   0 on success, the function cannot fail.
3579  */
3580 static int
3581 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3582 {
3583         uint16_t port_id;
3584
3585         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3586                 rte_eth_dev_close(port_id);
3587         return 0;
3588 }
3589
3590 static const struct rte_pci_id mlx5_pci_id_map[] = {
3591         {
3592                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3593                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3594         },
3595         {
3596                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3597                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3598         },
3599         {
3600                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3601                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3602         },
3603         {
3604                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3605                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3606         },
3607         {
3608                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3609                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3610         },
3611         {
3612                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3613                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3614         },
3615         {
3616                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3617                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3618         },
3619         {
3620                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3621                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3622         },
3623         {
3624                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3625                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3626         },
3627         {
3628                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3629                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3630         },
3631         {
3632                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3633                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3634         },
3635         {
3636                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3637                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3638         },
3639         {
3640                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3641                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3642         },
3643         {
3644                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3645                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3646         },
3647         {
3648                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3649                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3650         },
3651         {
3652                 .vendor_id = 0
3653         }
3654 };
3655
3656 static struct rte_pci_driver mlx5_driver = {
3657         .driver = {
3658                 .name = MLX5_DRIVER_NAME
3659         },
3660         .id_table = mlx5_pci_id_map,
3661         .probe = mlx5_pci_probe,
3662         .remove = mlx5_pci_remove,
3663         .dma_map = mlx5_dma_map,
3664         .dma_unmap = mlx5_dma_unmap,
3665         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3666                      RTE_PCI_DRV_PROBE_AGAIN,
3667 };
3668
3669 /**
3670  * Driver initialization routine.
3671  */
3672 RTE_INIT(rte_mlx5_pmd_init)
3673 {
3674         /* Initialize driver log type. */
3675         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3676         if (mlx5_logtype >= 0)
3677                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3678
3679         /* Build the static tables for Verbs conversion. */
3680         mlx5_set_ptype_table();
3681         mlx5_set_cksum_table();
3682         mlx5_set_swp_types_table();
3683         if (mlx5_glue)
3684                 rte_pci_register(&mlx5_driver);
3685 }
3686
3687 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3688 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3689 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");