drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_autoconf.h"
  40 #include "mlx5_mr.h"
  41 #include "mlx5_flow.h"
  42 #include "mlx5_flow_os.h"
  43 #include "rte_pmd_mlx5.h"
  44
  45 /* Device parameter to enable RX completion queue compression. */
  46 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  47
  48 /* Device parameter to enable padding Rx packet to cacheline size. */
  49 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  50
  51 /* Device parameter to enable Multi-Packet Rx queue. */
  52 #define MLX5_RX_MPRQ_EN "mprq_en"
  53
  54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  56
  57 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  58 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  59
  60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  62
  63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  65
  66 /* Device parameter to configure inline send. Deprecated, ignored.*/
  67 #define MLX5_TXQ_INLINE "txq_inline"
  68
  69 /* Device parameter to limit packet size to inline with ordinary SEND. */
  70 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  71
  72 /* Device parameter to configure minimal data size to inline. */
  73 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  74
  75 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  76 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  77
  78 /*
  79  * Device parameter to configure the number of TX queues threshold for
  80  * enabling inline send.
  81  */
  82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  83
  84 /*
  85  * Device parameter to configure the number of TX queues threshold for
  86  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  87  */
  88 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  89
  90 /* Device parameter to enable multi-packet send WQEs. */
  91 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  92
  93 /*
  94  * Device parameter to force doorbell register mapping
  95  * to non-cahed region eliminating the extra write memory barrier.
  96  */
  97 #define MLX5_TX_DB_NC "tx_db_nc"
  98
  99 /*
 100  * Device parameter to include 2 dsegs in the title WQEBB.
 101  * Deprecated, ignored.
 102  */
 103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 104
 105 /*
 106  * Device parameter to limit the size of inlining packet.
 107  * Deprecated, ignored.
 108  */
 109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 110
 111 /*
 112  * Device parameter to enable Tx scheduling on timestamps
 113  * and specify the packet pacing granularity in nanoseconds.
 114  */
 115 #define MLX5_TX_PP "tx_pp"
 116
 117 /*
 118  * Device parameter to specify skew in nanoseconds on Tx datapath,
 119  * it represents the time between SQ start WQE processing and
 120  * appearing actual packet data on the wire.
 121  */
 122 #define MLX5_TX_SKEW "tx_skew"
 123
 124 /*
 125  * Device parameter to enable hardware Tx vector.
 126  * Deprecated, ignored (no vectorized Tx routines anymore).
 127  */
 128 #define MLX5_TX_VEC_EN "tx_vec_en"
 129
 130 /* Device parameter to enable hardware Rx vector. */
 131 #define MLX5_RX_VEC_EN "rx_vec_en"
 132
 133 /* Allow L3 VXLAN flow creation. */
 134 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 135
 136 /* Activate DV E-Switch flow steering. */
 137 #define MLX5_DV_ESW_EN "dv_esw_en"
 138
 139 /* Activate DV flow steering. */
 140 #define MLX5_DV_FLOW_EN "dv_flow_en"
 141
 142 /* Enable extensive flow metadata support. */
 143 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 144
 145 /* Device parameter to let the user manage the lacp traffic of bonded device */
 146 #define MLX5_LACP_BY_USER "lacp_by_user"
 147
 148 /* Activate Netlink support in VF mode. */
 149 #define MLX5_VF_NL_EN "vf_nl_en"
 150
 151 /* Enable extending memsegs when creating a MR. */
 152 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 153
 154 /* Select port representors to instantiate. */
 155 #define MLX5_REPRESENTOR "representor"
 156
 157 /* Device parameter to configure the maximum number of dump files per queue. */
 158 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 159
 160 /* Configure timeout of LRO session (in microseconds). */
 161 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 162
 163 /*
 164  * Device parameter to configure the total data buffer size for a single
 165  * hairpin queue (logarithm value).
 166  */
 167 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 168
 169 /* Flow memory reclaim mode. */
 170 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 171
 172 /* The default memory allocator used in PMD. */
 173 #define MLX5_SYS_MEM_EN "sys_mem_en"
 174 /* Decap will be used or not. */
 175 #define MLX5_DECAP_EN "decap_en"
 176
 177 /* Shared memory between primary and secondary processes. */
 178 struct mlx5_shared_data *mlx5_shared_data;
 179
 180 /** Driver-specific log messages type. */
 181 int mlx5_logtype;
 182
 183 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 184                                                 LIST_HEAD_INITIALIZER();
 185 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 186 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 187 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 188         [MLX5_IPOOL_DECAP_ENCAP] = {
 189                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 190                 .trunk_size = 64,
 191                 .grow_trunk = 3,
 192                 .grow_shift = 2,
 193                 .need_lock = 1,
 194                 .release_mem_en = 1,
 195                 .malloc = mlx5_malloc,
 196                 .free = mlx5_free,
 197                 .type = "mlx5_encap_decap_ipool",
 198         },
 199         [MLX5_IPOOL_PUSH_VLAN] = {
 200                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 201                 .trunk_size = 64,
 202                 .grow_trunk = 3,
 203                 .grow_shift = 2,
 204                 .need_lock = 1,
 205                 .release_mem_en = 1,
 206                 .malloc = mlx5_malloc,
 207                 .free = mlx5_free,
 208                 .type = "mlx5_push_vlan_ipool",
 209         },
 210         [MLX5_IPOOL_TAG] = {
 211                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 212                 .trunk_size = 64,
 213                 .grow_trunk = 3,
 214                 .grow_shift = 2,
 215                 .need_lock = 1,
 216                 .release_mem_en = 1,
 217                 .malloc = mlx5_malloc,
 218                 .free = mlx5_free,
 219                 .type = "mlx5_tag_ipool",
 220         },
 221         [MLX5_IPOOL_PORT_ID] = {
 222                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 223                 .trunk_size = 64,
 224                 .grow_trunk = 3,
 225                 .grow_shift = 2,
 226                 .need_lock = 1,
 227                 .release_mem_en = 1,
 228                 .malloc = mlx5_malloc,
 229                 .free = mlx5_free,
 230                 .type = "mlx5_port_id_ipool",
 231         },
 232         [MLX5_IPOOL_JUMP] = {
 233                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 234                 .trunk_size = 64,
 235                 .grow_trunk = 3,
 236                 .grow_shift = 2,
 237                 .need_lock = 1,
 238                 .release_mem_en = 1,
 239                 .malloc = mlx5_malloc,
 240                 .free = mlx5_free,
 241                 .type = "mlx5_jump_ipool",
 242         },
 243         [MLX5_IPOOL_SAMPLE] = {
 244                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 245                 .trunk_size = 64,
 246                 .grow_trunk = 3,
 247                 .grow_shift = 2,
 248                 .need_lock = 1,
 249                 .release_mem_en = 1,
 250                 .malloc = mlx5_malloc,
 251                 .free = mlx5_free,
 252                 .type = "mlx5_sample_ipool",
 253         },
 254         [MLX5_IPOOL_DEST_ARRAY] = {
 255                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 256                 .trunk_size = 64,
 257                 .grow_trunk = 3,
 258                 .grow_shift = 2,
 259                 .need_lock = 1,
 260                 .release_mem_en = 1,
 261                 .malloc = mlx5_malloc,
 262                 .free = mlx5_free,
 263                 .type = "mlx5_dest_array_ipool",
 264         },
 265         [MLX5_IPOOL_TUNNEL_ID] = {
 266                 .size = sizeof(struct mlx5_flow_tunnel),
 267                 .trunk_size = MLX5_MAX_TUNNELS,
 268                 .need_lock = 1,
 269                 .release_mem_en = 1,
 270                 .type = "mlx5_tunnel_offload",
 271         },
 272         [MLX5_IPOOL_TNL_TBL_ID] = {
 273                 .size = 0,
 274                 .need_lock = 1,
 275                 .type = "mlx5_flow_tnl_tbl_ipool",
 276         },
 277 #endif
 278         [MLX5_IPOOL_MTR] = {
 279                 .size = sizeof(struct mlx5_flow_meter),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 1,
 284                 .release_mem_en = 1,
 285                 .malloc = mlx5_malloc,
 286                 .free = mlx5_free,
 287                 .type = "mlx5_meter_ipool",
 288         },
 289         [MLX5_IPOOL_MCP] = {
 290                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 291                 .trunk_size = 64,
 292                 .grow_trunk = 3,
 293                 .grow_shift = 2,
 294                 .need_lock = 1,
 295                 .release_mem_en = 1,
 296                 .malloc = mlx5_malloc,
 297                 .free = mlx5_free,
 298                 .type = "mlx5_mcp_ipool",
 299         },
 300         [MLX5_IPOOL_HRXQ] = {
 301                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 302                 .trunk_size = 64,
 303                 .grow_trunk = 3,
 304                 .grow_shift = 2,
 305                 .need_lock = 1,
 306                 .release_mem_en = 1,
 307                 .malloc = mlx5_malloc,
 308                 .free = mlx5_free,
 309                 .type = "mlx5_hrxq_ipool",
 310         },
 311         [MLX5_IPOOL_MLX5_FLOW] = {
 312                 /*
 313                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 314                  * It set in run time according to PCI function configuration.
 315                  */
 316                 .size = 0,
 317                 .trunk_size = 64,
 318                 .grow_trunk = 3,
 319                 .grow_shift = 2,
 320                 .need_lock = 1,
 321                 .release_mem_en = 1,
 322                 .malloc = mlx5_malloc,
 323                 .free = mlx5_free,
 324                 .type = "mlx5_flow_handle_ipool",
 325         },
 326         [MLX5_IPOOL_RTE_FLOW] = {
 327                 .size = sizeof(struct rte_flow),
 328                 .trunk_size = 4096,
 329                 .need_lock = 1,
 330                 .release_mem_en = 1,
 331                 .malloc = mlx5_malloc,
 332                 .free = mlx5_free,
 333                 .type = "rte_flow_ipool",
 334         },
 335         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 336                 .size = 0,
 337                 .need_lock = 1,
 338                 .type = "mlx5_flow_rss_id_ipool",
 339         },
 340         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 341                 .size = sizeof(struct mlx5_shared_action_rss),
 342                 .trunk_size = 64,
 343                 .grow_trunk = 3,
 344                 .grow_shift = 2,
 345                 .need_lock = 1,
 346                 .release_mem_en = 1,
 347                 .malloc = mlx5_malloc,
 348                 .free = mlx5_free,
 349                 .type = "mlx5_shared_action_rss",
 350         },
 351 };
 352
 353
 354 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 355 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 356
 357 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 358
 359 /**
 360  * Decide whether representor ID is a HPF(host PF) port on BF2.
 361  *
 362  * @param dev
 363  *   Pointer to Ethernet device structure.
 364  *
 365  * @return
 366  *   Non-zero if HPF, otherwise 0.
 367  */
 368 bool
 369 mlx5_is_hpf(struct rte_eth_dev *dev)
 370 {
 371         struct mlx5_priv *priv = dev->data->dev_private;
 372         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 373         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 374
 375         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 376                MLX5_REPRESENTOR_REPR(-1) == repr;
 377 }
 378
 379 /**
 380  * Initialize the ASO aging management structure.
 381  *
 382  * @param[in] sh
 383  *   Pointer to mlx5_dev_ctx_shared object to free
 384  *
 385  * @return
 386  *   0 on success, a negative errno value otherwise and rte_errno is set.
 387  */
 388 int
 389 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 390 {
 391         int err;
 392
 393         if (sh->aso_age_mng)
 394                 return 0;
 395         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 396                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 397         if (!sh->aso_age_mng) {
 398                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 399                 rte_errno = ENOMEM;
 400                 return -ENOMEM;
 401         }
 402         err = mlx5_aso_queue_init(sh);
 403         if (err) {
 404                 mlx5_free(sh->aso_age_mng);
 405                 return -1;
 406         }
 407         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 408         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 409         LIST_INIT(&sh->aso_age_mng->free);
 410         return 0;
 411 }
 412
 413 /**
 414  * Close and release all the resources of the ASO aging management structure.
 415  *
 416  * @param[in] sh
 417  *   Pointer to mlx5_dev_ctx_shared object to free.
 418  */
 419 static void
 420 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 421 {
 422         int i, j;
 423
 424         mlx5_aso_queue_stop(sh);
 425         mlx5_aso_queue_uninit(sh);
 426         if (sh->aso_age_mng->pools) {
 427                 struct mlx5_aso_age_pool *pool;
 428
 429                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 430                         pool = sh->aso_age_mng->pools[i];
 431                         claim_zero(mlx5_devx_cmd_destroy
 432                                                 (pool->flow_hit_aso_obj));
 433                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 434                                 if (pool->actions[j].dr_action)
 435                                         claim_zero
 436                                             (mlx5_flow_os_destroy_flow_action
 437                                               (pool->actions[j].dr_action));
 438                         mlx5_free(pool);
 439                 }
 440                 mlx5_free(sh->aso_age_mng->pools);
 441         }
 442         mlx5_free(sh->aso_age_mng);
 443 }
 444
 445 /**
 446  * Initialize the shared aging list information per port.
 447  *
 448  * @param[in] sh
 449  *   Pointer to mlx5_dev_ctx_shared object.
 450  */
 451 static void
 452 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 453 {
 454         uint32_t i;
 455         struct mlx5_age_info *age_info;
 456
 457         for (i = 0; i < sh->max_port; i++) {
 458                 age_info = &sh->port[i].age_info;
 459                 age_info->flags = 0;
 460                 TAILQ_INIT(&age_info->aged_counters);
 461                 LIST_INIT(&age_info->aged_aso);
 462                 rte_spinlock_init(&age_info->aged_sl);
 463                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 464         }
 465 }
 466
 467 /**
 468  * Initialize the counters management structure.
 469  *
 470  * @param[in] sh
 471  *   Pointer to mlx5_dev_ctx_shared object to free
 472  */
 473 static void
 474 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 475 {
 476         int i;
 477
 478         memset(&sh->cmng, 0, sizeof(sh->cmng));
 479         TAILQ_INIT(&sh->cmng.flow_counters);
 480         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 481         sh->cmng.max_id = -1;
 482         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 483         rte_spinlock_init(&sh->cmng.pool_update_sl);
 484         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 485                 TAILQ_INIT(&sh->cmng.counters[i]);
 486                 rte_spinlock_init(&sh->cmng.csl[i]);
 487         }
 488 }
 489
 490 /**
 491  * Destroy all the resources allocated for a counter memory management.
 492  *
 493  * @param[in] mng
 494  *   Pointer to the memory management structure.
 495  */
 496 static void
 497 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 498 {
 499         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 500
 501         LIST_REMOVE(mng, next);
 502         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 503         claim_zero(mlx5_os_umem_dereg(mng->umem));
 504         mlx5_free(mem);
 505 }
 506
 507 /**
 508  * Close and release all the resources of the counters management.
 509  *
 510  * @param[in] sh
 511  *   Pointer to mlx5_dev_ctx_shared object to free.
 512  */
 513 static void
 514 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 515 {
 516         struct mlx5_counter_stats_mem_mng *mng;
 517         int i, j;
 518         int retries = 1024;
 519
 520         rte_errno = 0;
 521         while (--retries) {
 522                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 523                 if (rte_errno != EINPROGRESS)
 524                         break;
 525                 rte_pause();
 526         }
 527
 528         if (sh->cmng.pools) {
 529                 struct mlx5_flow_counter_pool *pool;
 530                 uint16_t n_valid = sh->cmng.n_valid;
 531                 bool fallback = sh->cmng.counter_fallback;
 532
 533                 for (i = 0; i < n_valid; ++i) {
 534                         pool = sh->cmng.pools[i];
 535                         if (!fallback && pool->min_dcs)
 536                                 claim_zero(mlx5_devx_cmd_destroy
 537                                                                (pool->min_dcs));
 538                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 539                                 struct mlx5_flow_counter *cnt =
 540                                                 MLX5_POOL_GET_CNT(pool, j);
 541
 542                                 if (cnt->action)
 543                                         claim_zero
 544                                          (mlx5_flow_os_destroy_flow_action
 545                                           (cnt->action));
 546                                 if (fallback && MLX5_POOL_GET_CNT
 547                                     (pool, j)->dcs_when_free)
 548                                         claim_zero(mlx5_devx_cmd_destroy
 549                                                    (cnt->dcs_when_free));
 550                         }
 551                         mlx5_free(pool);
 552                 }
 553                 mlx5_free(sh->cmng.pools);
 554         }
 555         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         while (mng) {
 557                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 558                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 559         }
 560         memset(&sh->cmng, 0, sizeof(sh->cmng));
 561 }
 562
 563 /* Send FLOW_AGED event if needed. */
 564 void
 565 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 566 {
 567         struct mlx5_age_info *age_info;
 568         uint32_t i;
 569
 570         for (i = 0; i < sh->max_port; i++) {
 571                 age_info = &sh->port[i].age_info;
 572                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 573                         continue;
 574                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 575                         rte_eth_dev_callback_process
 576                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 577                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 578                 age_info->flags = 0;
 579         }
 580 }
 581
 582 /**
 583  * Initialize the flow resources' indexed mempool.
 584  *
 585  * @param[in] sh
 586  *   Pointer to mlx5_dev_ctx_shared object.
 587  * @param[in] sh
 588  *   Pointer to user dev config.
 589  */
 590 static void
 591 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 592                        const struct mlx5_dev_config *config)
 593 {
 594         uint8_t i;
 595         struct mlx5_indexed_pool_config cfg;
 596
 597         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 598                 cfg = mlx5_ipool_cfg[i];
 599                 switch (i) {
 600                 default:
 601                         break;
 602                 /*
 603                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 604                  * according to PCI function flow configuration.
 605                  */
 606                 case MLX5_IPOOL_MLX5_FLOW:
 607                         cfg.size = config->dv_flow_en ?
 608                                 sizeof(struct mlx5_flow_handle) :
 609                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 610                         break;
 611                 }
 612                 if (config->reclaim_mode)
 613                         cfg.release_mem_en = 1;
 614                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 615         }
 616 }
 617
 618 /**
 619  * Release the flow resources' indexed mempool.
 620  *
 621  * @param[in] sh
 622  *   Pointer to mlx5_dev_ctx_shared object.
 623  */
 624 static void
 625 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 626 {
 627         uint8_t i;
 628
 629         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 630                 mlx5_ipool_destroy(sh->ipool[i]);
 631 }
 632
 633 /*
 634  * Check if dynamic flex parser for eCPRI already exists.
 635  *
 636  * @param dev
 637  *   Pointer to Ethernet device structure.
 638  *
 639  * @return
 640  *   true on exists, false on not.
 641  */
 642 bool
 643 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 644 {
 645         struct mlx5_priv *priv = dev->data->dev_private;
 646         struct mlx5_flex_parser_profiles *prf =
 647                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 648
 649         return !!prf->obj;
 650 }
 651
 652 /*
 653  * Allocation of a flex parser for eCPRI. Once created, this parser related
 654  * resources will be held until the device is closed.
 655  *
 656  * @param dev
 657  *   Pointer to Ethernet device structure.
 658  *
 659  * @return
 660  *   0 on success, a negative errno value otherwise and rte_errno is set.
 661  */
 662 int
 663 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 664 {
 665         struct mlx5_priv *priv = dev->data->dev_private;
 666         struct mlx5_flex_parser_profiles *prf =
 667                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 668         struct mlx5_devx_graph_node_attr node = {
 669                 .modify_field_select = 0,
 670         };
 671         uint32_t ids[8];
 672         int ret;
 673
 674         if (!priv->config.hca_attr.parse_graph_flex_node) {
 675                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 676                         "for device %s.", priv->dev_data->name);
 677                 return -ENOTSUP;
 678         }
 679         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 680         /* 8 bytes now: 4B common header + 4B message body header. */
 681         node.header_length_base_value = 0x8;
 682         /* After MAC layer: Ether / VLAN. */
 683         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 684         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 685         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 686         /* Sample #0: type in common header. */
 687         node.sample[0].flow_match_sample_en = 1;
 688         /* Fixed offset. */
 689         node.sample[0].flow_match_sample_offset_mode = 0x0;
 690         /* Only the 2nd byte will be used. */
 691         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 692         /* Sample #1: message payload. */
 693         node.sample[1].flow_match_sample_en = 1;
 694         /* Fixed offset. */
 695         node.sample[1].flow_match_sample_offset_mode = 0x0;
 696         /*
 697          * Only the first two bytes will be used right now, and its offset will
 698          * start after the common header that with the length of a DW(u32).
 699          */
 700         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 701         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 702         if (!prf->obj) {
 703                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 704                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 705         }
 706         prf->num = 2;
 707         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 708         if (ret) {
 709                 DRV_LOG(ERR, "Failed to query sample IDs.");
 710                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 711         }
 712         prf->offset[0] = 0x0;
 713         prf->offset[1] = sizeof(uint32_t);
 714         prf->ids[0] = ids[0];
 715         prf->ids[1] = ids[1];
 716         return 0;
 717 }
 718
 719 /*
 720  * Destroy the flex parser node, including the parser itself, input / output
 721  * arcs and DW samples. Resources could be reused then.
 722  *
 723  * @param dev
 724  *   Pointer to Ethernet device structure.
 725  */
 726 static void
 727 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 728 {
 729         struct mlx5_priv *priv = dev->data->dev_private;
 730         struct mlx5_flex_parser_profiles *prf =
 731                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 732
 733         if (prf->obj)
 734                 mlx5_devx_cmd_destroy(prf->obj);
 735         prf->obj = NULL;
 736 }
 737
 738 /*
 739  * Allocate Rx and Tx UARs in robust fashion.
 740  * This routine handles the following UAR allocation issues:
 741  *
 742  *  - tries to allocate the UAR with the most appropriate memory
 743  *    mapping type from the ones supported by the host
 744  *
 745  *  - tries to allocate the UAR with non-NULL base address
 746  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 747  *    UAR base address if UAR was not the first object in the UAR page.
 748  *    It caused the PMD failure and we should try to get another UAR
 749  *    till we get the first one with non-NULL base address returned.
 750  */
 751 static int
 752 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 753                      const struct mlx5_dev_config *config)
 754 {
 755         uint32_t uar_mapping, retry;
 756         int err = 0;
 757         void *base_addr;
 758
 759         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 760 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 761                 /* Control the mapping type according to the settings. */
 762                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 763                               MLX5DV_UAR_ALLOC_TYPE_NC :
 764                               MLX5DV_UAR_ALLOC_TYPE_BF;
 765 #else
 766                 RTE_SET_USED(config);
 767                 /*
 768                  * It seems we have no way to control the memory mapping type
 769                  * for the UAR, the default "Write-Combining" type is supposed.
 770                  * The UAR initialization on queue creation queries the
 771                  * actual mapping type done by Verbs/kernel and setups the
 772                  * PMD datapath accordingly.
 773                  */
 774                 uar_mapping = 0;
 775 #endif
 776                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 777 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 778                 if (!sh->tx_uar &&
 779                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 780                         if (config->dbnc == MLX5_TXDB_CACHED ||
 781                             config->dbnc == MLX5_TXDB_HEURISTIC)
 782                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 783                                                  "is not supported by DevX");
 784                         /*
 785                          * In some environments like virtual machine
 786                          * the Write Combining mapped might be not supported
 787                          * and UAR allocation fails. We try "Non-Cached"
 788                          * mapping for the case. The tx_burst routines take
 789                          * the UAR mapping type into account on UAR setup
 790                          * on queue creation.
 791                          */
 792                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 793                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 794                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 795                                                         (sh->ctx, uar_mapping);
 796                 } else if (!sh->tx_uar &&
 797                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 798                         if (config->dbnc == MLX5_TXDB_NCACHED)
 799                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 800                                                  "is not supported by DevX");
 801                         /*
 802                          * If Verbs/kernel does not support "Non-Cached"
 803                          * try the "Write-Combining".
 804                          */
 805                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 806                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 807                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 808                                                         (sh->ctx, uar_mapping);
 809                 }
 810 #endif
 811                 if (!sh->tx_uar) {
 812                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 813                         err = ENOMEM;
 814                         goto exit;
 815                 }
 816                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 817                 if (base_addr)
 818                         break;
 819                 /*
 820                  * The UARs are allocated by rdma_core within the
 821                  * IB device context, on context closure all UARs
 822                  * will be freed, should be no memory/object leakage.
 823                  */
 824                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 825                 sh->tx_uar = NULL;
 826         }
 827         /* Check whether we finally succeeded with valid UAR allocation. */
 828         if (!sh->tx_uar) {
 829                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 830                 err = ENOMEM;
 831                 goto exit;
 832         }
 833         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 834                 uar_mapping = 0;
 835                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 836                                                         (sh->ctx, uar_mapping);
 837 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 838                 if (!sh->devx_rx_uar &&
 839                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 840                         /*
 841                          * Rx UAR is used to control interrupts only,
 842                          * should be no datapath noticeable impact,
 843                          * can try "Non-Cached" mapping safely.
 844                          */
 845                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 846                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 847                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 848                                                         (sh->ctx, uar_mapping);
 849                 }
 850 #endif
 851                 if (!sh->devx_rx_uar) {
 852                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 853                         err = ENOMEM;
 854                         goto exit;
 855                 }
 856                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 857                 if (base_addr)
 858                         break;
 859                 /*
 860                  * The UARs are allocated by rdma_core within the
 861                  * IB device context, on context closure all UARs
 862                  * will be freed, should be no memory/object leakage.
 863                  */
 864                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 865                 sh->devx_rx_uar = NULL;
 866         }
 867         /* Check whether we finally succeeded with valid UAR allocation. */
 868         if (!sh->devx_rx_uar) {
 869                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 870                 err = ENOMEM;
 871         }
 872 exit:
 873         return err;
 874 }
 875
 876 /**
 877  * Allocate shared device context. If there is multiport device the
 878  * master and representors will share this context, if there is single
 879  * port dedicated device, the context will be used by only given
 880  * port due to unification.
 881  *
 882  * Routine first searches the context for the specified device name,
 883  * if found the shared context assumed and reference counter is incremented.
 884  * If no context found the new one is created and initialized with specified
 885  * device context and parameters.
 886  *
 887  * @param[in] spawn
 888  *   Pointer to the device attributes (name, port, etc).
 889  * @param[in] config
 890  *   Pointer to device configuration structure.
 891  *
 892  * @return
 893  *   Pointer to mlx5_dev_ctx_shared object on success,
 894  *   otherwise NULL and rte_errno is set.
 895  */
 896 struct mlx5_dev_ctx_shared *
 897 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 898                            const struct mlx5_dev_config *config)
 899 {
 900         struct mlx5_dev_ctx_shared *sh;
 901         int err = 0;
 902         uint32_t i;
 903         struct mlx5_devx_tis_attr tis_attr = { 0 };
 904
 905         MLX5_ASSERT(spawn);
 906         /* Secondary process should not create the shared context. */
 907         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 908         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 909         /* Search for IB context by device name. */
 910         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 911                 if (!strcmp(sh->ibdev_name,
 912                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 913                         sh->refcnt++;
 914                         goto exit;
 915                 }
 916         }
 917         /* No device found, we have to create new shared context. */
 918         MLX5_ASSERT(spawn->max_port);
 919         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 920                          sizeof(struct mlx5_dev_ctx_shared) +
 921                          spawn->max_port *
 922                          sizeof(struct mlx5_dev_shared_port),
 923                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 924         if (!sh) {
 925                 DRV_LOG(ERR, "shared context allocation failure");
 926                 rte_errno  = ENOMEM;
 927                 goto exit;
 928         }
 929         if (spawn->bond_info)
 930                 sh->bond = *spawn->bond_info;
 931         err = mlx5_os_open_device(spawn, config, sh);
 932         if (!sh->ctx)
 933                 goto error;
 934         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 935         if (err) {
 936                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 937                 goto error;
 938         }
 939         sh->refcnt = 1;
 940         sh->max_port = spawn->max_port;
 941         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 942                 sizeof(sh->ibdev_name) - 1);
 943         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 944                 sizeof(sh->ibdev_path) - 1);
 945         /*
 946          * Setting port_id to max unallowed value means
 947          * there is no interrupt subhandler installed for
 948          * the given port index i.
 949          */
 950         for (i = 0; i < sh->max_port; i++) {
 951                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 952                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 953         }
 954         sh->pd = mlx5_os_alloc_pd(sh->ctx);
 955         if (sh->pd == NULL) {
 956                 DRV_LOG(ERR, "PD allocation failure");
 957                 err = ENOMEM;
 958                 goto error;
 959         }
 960         if (sh->devx) {
 961                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 962                 if (err) {
 963                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 964                         goto error;
 965                 }
 966                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 967                 if (!sh->td) {
 968                         DRV_LOG(ERR, "TD allocation failure");
 969                         err = ENOMEM;
 970                         goto error;
 971                 }
 972                 tis_attr.transport_domain = sh->td->id;
 973                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 974                 if (!sh->tis) {
 975                         DRV_LOG(ERR, "TIS allocation failure");
 976                         err = ENOMEM;
 977                         goto error;
 978                 }
 979                 err = mlx5_alloc_rxtx_uars(sh, config);
 980                 if (err)
 981                         goto error;
 982                 MLX5_ASSERT(sh->tx_uar);
 983                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 984
 985                 MLX5_ASSERT(sh->devx_rx_uar);
 986                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 987         }
 988 #ifndef RTE_ARCH_64
 989         /* Initialize UAR access locks for 32bit implementations. */
 990         rte_spinlock_init(&sh->uar_lock_cq);
 991         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 992                 rte_spinlock_init(&sh->uar_lock[i]);
 993 #endif
 994         /*
 995          * Once the device is added to the list of memory event
 996          * callback, its global MR cache table cannot be expanded
 997          * on the fly because of deadlock. If it overflows, lookup
 998          * should be done by searching MR list linearly, which is slow.
 999          *
1000          * At this point the device is not added to the memory
1001          * event list yet, context is just being created.
1002          */
1003         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1004                                  MLX5_MR_BTREE_CACHE_N * 2,
1005                                  spawn->pci_dev->device.numa_node);
1006         if (err) {
1007                 err = rte_errno;
1008                 goto error;
1009         }
1010         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1011                               &sh->share_cache.dereg_mr_cb);
1012         mlx5_os_dev_shared_handler_install(sh);
1013         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1014         if (!sh->cnt_id_tbl) {
1015                 err = rte_errno;
1016                 goto error;
1017         }
1018         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1019                 err = mlx5_flow_os_init_workspace_once();
1020                 if (err)
1021                         goto error;
1022         }
1023         mlx5_flow_aging_init(sh);
1024         mlx5_flow_counters_mng_init(sh);
1025         mlx5_flow_ipool_create(sh, config);
1026         /* Add device to memory callback list. */
1027         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1028         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1029                          sh, mem_event_cb);
1030         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1031         /* Add context to the global device list. */
1032         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1033         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1034 exit:
1035         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1036         return sh;
1037 error:
1038         pthread_mutex_destroy(&sh->txpp.mutex);
1039         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1040         MLX5_ASSERT(sh);
1041         if (sh->cnt_id_tbl)
1042                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1043         if (sh->tis)
1044                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1045         if (sh->td)
1046                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1047         if (sh->devx_rx_uar)
1048                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1049         if (sh->tx_uar)
1050                 mlx5_glue->devx_free_uar(sh->tx_uar);
1051         if (sh->pd)
1052                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1053         if (sh->ctx)
1054                 claim_zero(mlx5_glue->close_device(sh->ctx));
1055         mlx5_free(sh);
1056         MLX5_ASSERT(err > 0);
1057         rte_errno = err;
1058         return NULL;
1059 }
1060
1061 /**
1062  * Free shared IB device context. Decrement counter and if zero free
1063  * all allocated resources and close handles.
1064  *
1065  * @param[in] sh
1066  *   Pointer to mlx5_dev_ctx_shared object to free
1067  */
1068 void
1069 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1070 {
1071         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1072 #ifdef RTE_LIBRTE_MLX5_DEBUG
1073         /* Check the object presence in the list. */
1074         struct mlx5_dev_ctx_shared *lctx;
1075
1076         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1077                 if (lctx == sh)
1078                         break;
1079         MLX5_ASSERT(lctx);
1080         if (lctx != sh) {
1081                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1082                 goto exit;
1083         }
1084 #endif
1085         MLX5_ASSERT(sh);
1086         MLX5_ASSERT(sh->refcnt);
1087         /* Secondary process should not free the shared context. */
1088         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1089         if (--sh->refcnt)
1090                 goto exit;
1091         /* Remove from memory callback device list. */
1092         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1093         LIST_REMOVE(sh, mem_event_cb);
1094         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1095         /* Release created Memory Regions. */
1096         mlx5_mr_release_cache(&sh->share_cache);
1097         /* Remove context from the global device list. */
1098         LIST_REMOVE(sh, next);
1099         /* Release flow workspaces objects on the last device. */
1100         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1101                 mlx5_flow_os_release_workspace();
1102         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1103         /*
1104          *  Ensure there is no async event handler installed.
1105          *  Only primary process handles async device events.
1106          **/
1107         mlx5_flow_counters_mng_close(sh);
1108         if (sh->aso_age_mng) {
1109                 mlx5_flow_aso_age_mng_close(sh);
1110                 sh->aso_age_mng = NULL;
1111         }
1112         mlx5_flow_ipool_destroy(sh);
1113         mlx5_os_dev_shared_handler_uninstall(sh);
1114         if (sh->cnt_id_tbl) {
1115                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1116                 sh->cnt_id_tbl = NULL;
1117         }
1118         if (sh->tx_uar) {
1119                 mlx5_glue->devx_free_uar(sh->tx_uar);
1120                 sh->tx_uar = NULL;
1121         }
1122         if (sh->pd)
1123                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1124         if (sh->tis)
1125                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1126         if (sh->td)
1127                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1128         if (sh->devx_rx_uar)
1129                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1130         if (sh->ctx)
1131                 claim_zero(mlx5_glue->close_device(sh->ctx));
1132         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1133         pthread_mutex_destroy(&sh->txpp.mutex);
1134         mlx5_free(sh);
1135         return;
1136 exit:
1137         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1138 }
1139
1140 /**
1141  * Destroy table hash list.
1142  *
1143  * @param[in] priv
1144  *   Pointer to the private device data structure.
1145  */
1146 void
1147 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1148 {
1149         struct mlx5_dev_ctx_shared *sh = priv->sh;
1150
1151         if (!sh->flow_tbls)
1152                 return;
1153         mlx5_hlist_destroy(sh->flow_tbls);
1154 }
1155
1156 /**
1157  * Initialize flow table hash list and create the root tables entry
1158  * for each domain.
1159  *
1160  * @param[in] priv
1161  *   Pointer to the private device data structure.
1162  *
1163  * @return
1164  *   Zero on success, positive error code otherwise.
1165  */
1166 int
1167 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1168 {
1169         int err = 0;
1170         /* Tables are only used in DV and DR modes. */
1171 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1172         struct mlx5_dev_ctx_shared *sh = priv->sh;
1173         char s[MLX5_HLIST_NAMESIZE];
1174
1175         MLX5_ASSERT(sh);
1176         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1177         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1178                                           0, 0, flow_dv_tbl_create_cb,
1179                                           flow_dv_tbl_match_cb,
1180                                           flow_dv_tbl_remove_cb);
1181         if (!sh->flow_tbls) {
1182                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1183                 err = ENOMEM;
1184                 return err;
1185         }
1186         sh->flow_tbls->ctx = sh;
1187 #ifndef HAVE_MLX5DV_DR
1188         struct rte_flow_error error;
1189         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1190
1191         /*
1192          * In case we have not DR support, the zero tables should be created
1193          * because DV expect to see them even if they cannot be created by
1194          * RDMA-CORE.
1195          */
1196         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1197             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1198             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1199                 err = ENOMEM;
1200                 goto error;
1201         }
1202         return err;
1203 error:
1204         mlx5_free_table_hash_list(priv);
1205 #endif /* HAVE_MLX5DV_DR */
1206 #endif
1207         return err;
1208 }
1209
1210 /**
1211  * Retrieve integer value from environment variable.
1212  *
1213  * @param[in] name
1214  *   Environment variable name.
1215  *
1216  * @return
1217  *   Integer value, 0 if the variable is not set.
1218  */
1219 int
1220 mlx5_getenv_int(const char *name)
1221 {
1222         const char *val = getenv(name);
1223
1224         if (val == NULL)
1225                 return 0;
1226         return atoi(val);
1227 }
1228
1229 /**
1230  * DPDK callback to add udp tunnel port
1231  *
1232  * @param[in] dev
1233  *   A pointer to eth_dev
1234  * @param[in] udp_tunnel
1235  *   A pointer to udp tunnel
1236  *
1237  * @return
1238  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1239  */
1240 int
1241 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1242                          struct rte_eth_udp_tunnel *udp_tunnel)
1243 {
1244         MLX5_ASSERT(udp_tunnel != NULL);
1245         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1246             udp_tunnel->udp_port == 4789)
1247                 return 0;
1248         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1249             udp_tunnel->udp_port == 4790)
1250                 return 0;
1251         return -ENOTSUP;
1252 }
1253
1254 /**
1255  * Initialize process private data structure.
1256  *
1257  * @param dev
1258  *   Pointer to Ethernet device structure.
1259  *
1260  * @return
1261  *   0 on success, a negative errno value otherwise and rte_errno is set.
1262  */
1263 int
1264 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1265 {
1266         struct mlx5_priv *priv = dev->data->dev_private;
1267         struct mlx5_proc_priv *ppriv;
1268         size_t ppriv_size;
1269
1270         /*
1271          * UAR register table follows the process private structure. BlueFlame
1272          * registers for Tx queues are stored in the table.
1273          */
1274         ppriv_size =
1275                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1276         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1277                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1278         if (!ppriv) {
1279                 rte_errno = ENOMEM;
1280                 return -rte_errno;
1281         }
1282         ppriv->uar_table_sz = priv->txqs_n;
1283         dev->process_private = ppriv;
1284         return 0;
1285 }
1286
1287 /**
1288  * Un-initialize process private data structure.
1289  *
1290  * @param dev
1291  *   Pointer to Ethernet device structure.
1292  */
1293 void
1294 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1295 {
1296         if (!dev->process_private)
1297                 return;
1298         mlx5_free(dev->process_private);
1299         dev->process_private = NULL;
1300 }
1301
1302 /**
1303  * DPDK callback to close the device.
1304  *
1305  * Destroy all queues and objects, free memory.
1306  *
1307  * @param dev
1308  *   Pointer to Ethernet device structure.
1309  */
1310 int
1311 mlx5_dev_close(struct rte_eth_dev *dev)
1312 {
1313         struct mlx5_priv *priv = dev->data->dev_private;
1314         unsigned int i;
1315         int ret;
1316
1317         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1318                 /* Check if process_private released. */
1319                 if (!dev->process_private)
1320                         return 0;
1321                 mlx5_tx_uar_uninit_secondary(dev);
1322                 mlx5_proc_priv_uninit(dev);
1323                 rte_eth_dev_release_port(dev);
1324                 return 0;
1325         }
1326         if (!priv->sh)
1327                 return 0;
1328         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1329                 dev->data->port_id,
1330                 ((priv->sh->ctx != NULL) ?
1331                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1332         /*
1333          * If default mreg copy action is removed at the stop stage,
1334          * the search will return none and nothing will be done anymore.
1335          */
1336         mlx5_flow_stop_default(dev);
1337         mlx5_traffic_disable(dev);
1338         /*
1339          * If all the flows are already flushed in the device stop stage,
1340          * then this will return directly without any action.
1341          */
1342         mlx5_flow_list_flush(dev, &priv->flows, true);
1343         mlx5_shared_action_flush(dev);
1344         mlx5_flow_meter_flush(dev, NULL);
1345         /* Prevent crashes when queues are still in use. */
1346         dev->rx_pkt_burst = removed_rx_burst;
1347         dev->tx_pkt_burst = removed_tx_burst;
1348         rte_wmb();
1349         /* Disable datapath on secondary process. */
1350         mlx5_mp_os_req_stop_rxtx(dev);
1351         /* Free the eCPRI flex parser resource. */
1352         mlx5_flex_parser_ecpri_release(dev);
1353         if (priv->rxqs != NULL) {
1354                 /* XXX race condition if mlx5_rx_burst() is still running. */
1355                 rte_delay_us_sleep(1000);
1356                 for (i = 0; (i != priv->rxqs_n); ++i)
1357                         mlx5_rxq_release(dev, i);
1358                 priv->rxqs_n = 0;
1359                 priv->rxqs = NULL;
1360         }
1361         if (priv->txqs != NULL) {
1362                 /* XXX race condition if mlx5_tx_burst() is still running. */
1363                 rte_delay_us_sleep(1000);
1364                 for (i = 0; (i != priv->txqs_n); ++i)
1365                         mlx5_txq_release(dev, i);
1366                 priv->txqs_n = 0;
1367                 priv->txqs = NULL;
1368         }
1369         mlx5_proc_priv_uninit(dev);
1370         if (priv->q_counters) {
1371                 mlx5_devx_cmd_destroy(priv->q_counters);
1372                 priv->q_counters = NULL;
1373         }
1374         if (priv->drop_queue.hrxq)
1375                 mlx5_drop_action_destroy(dev);
1376         if (priv->mreg_cp_tbl)
1377                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1378         mlx5_mprq_free_mp(dev);
1379         mlx5_os_free_shared_dr(priv);
1380         if (priv->rss_conf.rss_key != NULL)
1381                 mlx5_free(priv->rss_conf.rss_key);
1382         if (priv->reta_idx != NULL)
1383                 mlx5_free(priv->reta_idx);
1384         if (priv->config.vf)
1385                 mlx5_os_mac_addr_flush(dev);
1386         if (priv->nl_socket_route >= 0)
1387                 close(priv->nl_socket_route);
1388         if (priv->nl_socket_rdma >= 0)
1389                 close(priv->nl_socket_rdma);
1390         if (priv->vmwa_context)
1391                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1392         ret = mlx5_hrxq_verify(dev);
1393         if (ret)
1394                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1395                         dev->data->port_id);
1396         ret = mlx5_ind_table_obj_verify(dev);
1397         if (ret)
1398                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1399                         dev->data->port_id);
1400         ret = mlx5_rxq_obj_verify(dev);
1401         if (ret)
1402                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1403                         dev->data->port_id);
1404         ret = mlx5_rxq_verify(dev);
1405         if (ret)
1406                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1407                         dev->data->port_id);
1408         ret = mlx5_txq_obj_verify(dev);
1409         if (ret)
1410                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1411                         dev->data->port_id);
1412         ret = mlx5_txq_verify(dev);
1413         if (ret)
1414                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1415                         dev->data->port_id);
1416         ret = mlx5_flow_verify(dev);
1417         if (ret)
1418                 DRV_LOG(WARNING, "port %u some flows still remain",
1419                         dev->data->port_id);
1420         mlx5_cache_list_destroy(&priv->hrxqs);
1421         /*
1422          * Free the shared context in last turn, because the cleanup
1423          * routines above may use some shared fields, like
1424          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1425          * ifindex if Netlink fails.
1426          */
1427         mlx5_free_shared_dev_ctx(priv->sh);
1428         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1429                 unsigned int c = 0;
1430                 uint16_t port_id;
1431
1432                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1433                         struct mlx5_priv *opriv =
1434                                 rte_eth_devices[port_id].data->dev_private;
1435
1436                         if (!opriv ||
1437                             opriv->domain_id != priv->domain_id ||
1438                             &rte_eth_devices[port_id] == dev)
1439                                 continue;
1440                         ++c;
1441                         break;
1442                 }
1443                 if (!c)
1444                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1445         }
1446         memset(priv, 0, sizeof(*priv));
1447         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1448         /*
1449          * Reset mac_addrs to NULL such that it is not freed as part of
1450          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1451          * it is freed when dev_private is freed.
1452          */
1453         dev->data->mac_addrs = NULL;
1454         return 0;
1455 }
1456
1457 const struct eth_dev_ops mlx5_dev_ops = {
1458         .dev_configure = mlx5_dev_configure,
1459         .dev_start = mlx5_dev_start,
1460         .dev_stop = mlx5_dev_stop,
1461         .dev_set_link_down = mlx5_set_link_down,
1462         .dev_set_link_up = mlx5_set_link_up,
1463         .dev_close = mlx5_dev_close,
1464         .promiscuous_enable = mlx5_promiscuous_enable,
1465         .promiscuous_disable = mlx5_promiscuous_disable,
1466         .allmulticast_enable = mlx5_allmulticast_enable,
1467         .allmulticast_disable = mlx5_allmulticast_disable,
1468         .link_update = mlx5_link_update,
1469         .stats_get = mlx5_stats_get,
1470         .stats_reset = mlx5_stats_reset,
1471         .xstats_get = mlx5_xstats_get,
1472         .xstats_reset = mlx5_xstats_reset,
1473         .xstats_get_names = mlx5_xstats_get_names,
1474         .fw_version_get = mlx5_fw_version_get,
1475         .dev_infos_get = mlx5_dev_infos_get,
1476         .representor_info_get = mlx5_representor_info_get,
1477         .read_clock = mlx5_txpp_read_clock,
1478         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1479         .vlan_filter_set = mlx5_vlan_filter_set,
1480         .rx_queue_setup = mlx5_rx_queue_setup,
1481         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1482         .tx_queue_setup = mlx5_tx_queue_setup,
1483         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1484         .rx_queue_release = mlx5_rx_queue_release,
1485         .tx_queue_release = mlx5_tx_queue_release,
1486         .rx_queue_start = mlx5_rx_queue_start,
1487         .rx_queue_stop = mlx5_rx_queue_stop,
1488         .tx_queue_start = mlx5_tx_queue_start,
1489         .tx_queue_stop = mlx5_tx_queue_stop,
1490         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1491         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1492         .mac_addr_remove = mlx5_mac_addr_remove,
1493         .mac_addr_add = mlx5_mac_addr_add,
1494         .mac_addr_set = mlx5_mac_addr_set,
1495         .set_mc_addr_list = mlx5_set_mc_addr_list,
1496         .mtu_set = mlx5_dev_set_mtu,
1497         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1498         .vlan_offload_set = mlx5_vlan_offload_set,
1499         .reta_update = mlx5_dev_rss_reta_update,
1500         .reta_query = mlx5_dev_rss_reta_query,
1501         .rss_hash_update = mlx5_rss_hash_update,
1502         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1503         .flow_ops_get = mlx5_flow_ops_get,
1504         .rxq_info_get = mlx5_rxq_info_get,
1505         .txq_info_get = mlx5_txq_info_get,
1506         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1507         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1508         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1509         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1510         .is_removed = mlx5_is_removed,
1511         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1512         .get_module_info = mlx5_get_module_info,
1513         .get_module_eeprom = mlx5_get_module_eeprom,
1514         .hairpin_cap_get = mlx5_hairpin_cap_get,
1515         .mtr_ops_get = mlx5_flow_meter_ops_get,
1516         .hairpin_bind = mlx5_hairpin_bind,
1517         .hairpin_unbind = mlx5_hairpin_unbind,
1518         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1519         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1520         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1521         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1522 };
1523
1524 /* Available operations from secondary process. */
1525 const struct eth_dev_ops mlx5_dev_sec_ops = {
1526         .stats_get = mlx5_stats_get,
1527         .stats_reset = mlx5_stats_reset,
1528         .xstats_get = mlx5_xstats_get,
1529         .xstats_reset = mlx5_xstats_reset,
1530         .xstats_get_names = mlx5_xstats_get_names,
1531         .fw_version_get = mlx5_fw_version_get,
1532         .dev_infos_get = mlx5_dev_infos_get,
1533         .read_clock = mlx5_txpp_read_clock,
1534         .rx_queue_start = mlx5_rx_queue_start,
1535         .rx_queue_stop = mlx5_rx_queue_stop,
1536         .tx_queue_start = mlx5_tx_queue_start,
1537         .tx_queue_stop = mlx5_tx_queue_stop,
1538         .rxq_info_get = mlx5_rxq_info_get,
1539         .txq_info_get = mlx5_txq_info_get,
1540         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1541         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1542         .get_module_info = mlx5_get_module_info,
1543         .get_module_eeprom = mlx5_get_module_eeprom,
1544 };
1545
1546 /* Available operations in flow isolated mode. */
1547 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1548         .dev_configure = mlx5_dev_configure,
1549         .dev_start = mlx5_dev_start,
1550         .dev_stop = mlx5_dev_stop,
1551         .dev_set_link_down = mlx5_set_link_down,
1552         .dev_set_link_up = mlx5_set_link_up,
1553         .dev_close = mlx5_dev_close,
1554         .promiscuous_enable = mlx5_promiscuous_enable,
1555         .promiscuous_disable = mlx5_promiscuous_disable,
1556         .allmulticast_enable = mlx5_allmulticast_enable,
1557         .allmulticast_disable = mlx5_allmulticast_disable,
1558         .link_update = mlx5_link_update,
1559         .stats_get = mlx5_stats_get,
1560         .stats_reset = mlx5_stats_reset,
1561         .xstats_get = mlx5_xstats_get,
1562         .xstats_reset = mlx5_xstats_reset,
1563         .xstats_get_names = mlx5_xstats_get_names,
1564         .fw_version_get = mlx5_fw_version_get,
1565         .dev_infos_get = mlx5_dev_infos_get,
1566         .read_clock = mlx5_txpp_read_clock,
1567         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1568         .vlan_filter_set = mlx5_vlan_filter_set,
1569         .rx_queue_setup = mlx5_rx_queue_setup,
1570         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1571         .tx_queue_setup = mlx5_tx_queue_setup,
1572         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1573         .rx_queue_release = mlx5_rx_queue_release,
1574         .tx_queue_release = mlx5_tx_queue_release,
1575         .rx_queue_start = mlx5_rx_queue_start,
1576         .rx_queue_stop = mlx5_rx_queue_stop,
1577         .tx_queue_start = mlx5_tx_queue_start,
1578         .tx_queue_stop = mlx5_tx_queue_stop,
1579         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1580         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1581         .mac_addr_remove = mlx5_mac_addr_remove,
1582         .mac_addr_add = mlx5_mac_addr_add,
1583         .mac_addr_set = mlx5_mac_addr_set,
1584         .set_mc_addr_list = mlx5_set_mc_addr_list,
1585         .mtu_set = mlx5_dev_set_mtu,
1586         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1587         .vlan_offload_set = mlx5_vlan_offload_set,
1588         .flow_ops_get = mlx5_flow_ops_get,
1589         .rxq_info_get = mlx5_rxq_info_get,
1590         .txq_info_get = mlx5_txq_info_get,
1591         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1592         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1593         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1594         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1595         .is_removed = mlx5_is_removed,
1596         .get_module_info = mlx5_get_module_info,
1597         .get_module_eeprom = mlx5_get_module_eeprom,
1598         .hairpin_cap_get = mlx5_hairpin_cap_get,
1599         .mtr_ops_get = mlx5_flow_meter_ops_get,
1600         .hairpin_bind = mlx5_hairpin_bind,
1601         .hairpin_unbind = mlx5_hairpin_unbind,
1602         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1603         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1604         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1605         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1606 };
1607
1608 /**
1609  * Verify and store value for device argument.
1610  *
1611  * @param[in] key
1612  *   Key argument to verify.
1613  * @param[in] val
1614  *   Value associated with key.
1615  * @param opaque
1616  *   User data.
1617  *
1618  * @return
1619  *   0 on success, a negative errno value otherwise and rte_errno is set.
1620  */
1621 static int
1622 mlx5_args_check(const char *key, const char *val, void *opaque)
1623 {
1624         struct mlx5_dev_config *config = opaque;
1625         unsigned long mod;
1626         signed long tmp;
1627
1628         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1629         if (!strcmp(MLX5_REPRESENTOR, key))
1630                 return 0;
1631         errno = 0;
1632         tmp = strtol(val, NULL, 0);
1633         if (errno) {
1634                 rte_errno = errno;
1635                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1636                 return -rte_errno;
1637         }
1638         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1639                 /* Negative values are acceptable for some keys only. */
1640                 rte_errno = EINVAL;
1641                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1642                 return -rte_errno;
1643         }
1644         mod = tmp >= 0 ? tmp : -tmp;
1645         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1646                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1647                         DRV_LOG(ERR, "invalid CQE compression "
1648                                      "format parameter");
1649                         rte_errno = EINVAL;
1650                         return -rte_errno;
1651                 }
1652                 config->cqe_comp = !!tmp;
1653                 config->cqe_comp_fmt = tmp;
1654         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1655                 config->hw_padding = !!tmp;
1656         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1657                 config->mprq.enabled = !!tmp;
1658         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1659                 config->mprq.stride_num_n = tmp;
1660         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1661                 config->mprq.stride_size_n = tmp;
1662         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1663                 config->mprq.max_memcpy_len = tmp;
1664         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1665                 config->mprq.min_rxqs_num = tmp;
1666         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1667                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1668                                  " converted to txq_inline_max", key);
1669                 config->txq_inline_max = tmp;
1670         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1671                 config->txq_inline_max = tmp;
1672         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1673                 config->txq_inline_min = tmp;
1674         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1675                 config->txq_inline_mpw = tmp;
1676         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1677                 config->txqs_inline = tmp;
1678         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1679                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1680         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1681                 config->mps = !!tmp;
1682         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1683                 if (tmp != MLX5_TXDB_CACHED &&
1684                     tmp != MLX5_TXDB_NCACHED &&
1685                     tmp != MLX5_TXDB_HEURISTIC) {
1686                         DRV_LOG(ERR, "invalid Tx doorbell "
1687                                      "mapping parameter");
1688                         rte_errno = EINVAL;
1689                         return -rte_errno;
1690                 }
1691                 config->dbnc = tmp;
1692         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1693                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1694         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1695                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1696                                  " converted to txq_inline_mpw", key);
1697                 config->txq_inline_mpw = tmp;
1698         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1699                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1700         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1701                 if (!mod) {
1702                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1703                         rte_errno = EINVAL;
1704                         return -rte_errno;
1705                 }
1706                 config->tx_pp = tmp;
1707         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1708                 config->tx_skew = tmp;
1709         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1710                 config->rx_vec_en = !!tmp;
1711         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1712                 config->l3_vxlan_en = !!tmp;
1713         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1714                 config->vf_nl_en = !!tmp;
1715         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1716                 config->dv_esw_en = !!tmp;
1717         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1718                 config->dv_flow_en = !!tmp;
1719         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1720                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1721                     tmp != MLX5_XMETA_MODE_META16 &&
1722                     tmp != MLX5_XMETA_MODE_META32 &&
1723                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1724                         DRV_LOG(ERR, "invalid extensive "
1725                                      "metadata parameter");
1726                         rte_errno = EINVAL;
1727                         return -rte_errno;
1728                 }
1729                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1730                         config->dv_xmeta_en = tmp;
1731                 else
1732                         config->dv_miss_info = 1;
1733         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1734                 config->lacp_by_user = !!tmp;
1735         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1736                 config->mr_ext_memseg_en = !!tmp;
1737         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1738                 config->max_dump_files_num = tmp;
1739         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1740                 config->lro.timeout = tmp;
1741         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1742                 DRV_LOG(DEBUG, "class argument is %s.", val);
1743         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1744                 config->log_hp_size = tmp;
1745         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1746                 if (tmp != MLX5_RCM_NONE &&
1747                     tmp != MLX5_RCM_LIGHT &&
1748                     tmp != MLX5_RCM_AGGR) {
1749                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1750                         rte_errno = EINVAL;
1751                         return -rte_errno;
1752                 }
1753                 config->reclaim_mode = tmp;
1754         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1755                 config->sys_mem_en = !!tmp;
1756         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1757                 config->decap_en = !!tmp;
1758         } else {
1759                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1760                 rte_errno = EINVAL;
1761                 return -rte_errno;
1762         }
1763         return 0;
1764 }
1765
1766 /**
1767  * Parse device parameters.
1768  *
1769  * @param config
1770  *   Pointer to device configuration structure.
1771  * @param devargs
1772  *   Device arguments structure.
1773  *
1774  * @return
1775  *   0 on success, a negative errno value otherwise and rte_errno is set.
1776  */
1777 int
1778 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1779 {
1780         const char **params = (const char *[]){
1781                 MLX5_RXQ_CQE_COMP_EN,
1782                 MLX5_RXQ_PKT_PAD_EN,
1783                 MLX5_RX_MPRQ_EN,
1784                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1785                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1786                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1787                 MLX5_RXQS_MIN_MPRQ,
1788                 MLX5_TXQ_INLINE,
1789                 MLX5_TXQ_INLINE_MIN,
1790                 MLX5_TXQ_INLINE_MAX,
1791                 MLX5_TXQ_INLINE_MPW,
1792                 MLX5_TXQS_MIN_INLINE,
1793                 MLX5_TXQS_MAX_VEC,
1794                 MLX5_TXQ_MPW_EN,
1795                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1796                 MLX5_TXQ_MAX_INLINE_LEN,
1797                 MLX5_TX_DB_NC,
1798                 MLX5_TX_PP,
1799                 MLX5_TX_SKEW,
1800                 MLX5_TX_VEC_EN,
1801                 MLX5_RX_VEC_EN,
1802                 MLX5_L3_VXLAN_EN,
1803                 MLX5_VF_NL_EN,
1804                 MLX5_DV_ESW_EN,
1805                 MLX5_DV_FLOW_EN,
1806                 MLX5_DV_XMETA_EN,
1807                 MLX5_LACP_BY_USER,
1808                 MLX5_MR_EXT_MEMSEG_EN,
1809                 MLX5_REPRESENTOR,
1810                 MLX5_MAX_DUMP_FILES_NUM,
1811                 MLX5_LRO_TIMEOUT_USEC,
1812                 MLX5_CLASS_ARG_NAME,
1813                 MLX5_HP_BUF_SIZE,
1814                 MLX5_RECLAIM_MEM,
1815                 MLX5_SYS_MEM_EN,
1816                 MLX5_DECAP_EN,
1817                 NULL,
1818         };
1819         struct rte_kvargs *kvlist;
1820         int ret = 0;
1821         int i;
1822
1823         if (devargs == NULL)
1824                 return 0;
1825         /* Following UGLY cast is done to pass checkpatch. */
1826         kvlist = rte_kvargs_parse(devargs->args, params);
1827         if (kvlist == NULL) {
1828                 rte_errno = EINVAL;
1829                 return -rte_errno;
1830         }
1831         /* Process parameters. */
1832         for (i = 0; (params[i] != NULL); ++i) {
1833                 if (rte_kvargs_count(kvlist, params[i])) {
1834                         ret = rte_kvargs_process(kvlist, params[i],
1835                                                  mlx5_args_check, config);
1836                         if (ret) {
1837                                 rte_errno = EINVAL;
1838                                 rte_kvargs_free(kvlist);
1839                                 return -rte_errno;
1840                         }
1841                 }
1842         }
1843         rte_kvargs_free(kvlist);
1844         return 0;
1845 }
1846
1847 /**
1848  * Configures the minimal amount of data to inline into WQE
1849  * while sending packets.
1850  *
1851  * - the txq_inline_min has the maximal priority, if this
1852  *   key is specified in devargs
1853  * - if DevX is enabled the inline mode is queried from the
1854  *   device (HCA attributes and NIC vport context if needed).
1855  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1856  *   and none (0 bytes) for other NICs
1857  *
1858  * @param spawn
1859  *   Verbs device parameters (name, port, switch_info) to spawn.
1860  * @param config
1861  *   Device configuration parameters.
1862  */
1863 void
1864 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1865                     struct mlx5_dev_config *config)
1866 {
1867         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1868                 /* Application defines size of inlined data explicitly. */
1869                 switch (spawn->pci_dev->id.device_id) {
1870                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1871                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1872                         if (config->txq_inline_min <
1873                                        (int)MLX5_INLINE_HSIZE_L2) {
1874                                 DRV_LOG(DEBUG,
1875                                         "txq_inline_mix aligned to minimal"
1876                                         " ConnectX-4 required value %d",
1877                                         (int)MLX5_INLINE_HSIZE_L2);
1878                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1879                         }
1880                         break;
1881                 }
1882                 goto exit;
1883         }
1884         if (config->hca_attr.eth_net_offloads) {
1885                 /* We have DevX enabled, inline mode queried successfully. */
1886                 switch (config->hca_attr.wqe_inline_mode) {
1887                 case MLX5_CAP_INLINE_MODE_L2:
1888                         /* outer L2 header must be inlined. */
1889                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1890                         goto exit;
1891                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1892                         /* No inline data are required by NIC. */
1893                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1894                         config->hw_vlan_insert =
1895                                 config->hca_attr.wqe_vlan_insert;
1896                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1897                         goto exit;
1898                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1899                         /* inline mode is defined by NIC vport context. */
1900                         if (!config->hca_attr.eth_virt)
1901                                 break;
1902                         switch (config->hca_attr.vport_inline_mode) {
1903                         case MLX5_INLINE_MODE_NONE:
1904                                 config->txq_inline_min =
1905                                         MLX5_INLINE_HSIZE_NONE;
1906                                 goto exit;
1907                         case MLX5_INLINE_MODE_L2:
1908                                 config->txq_inline_min =
1909                                         MLX5_INLINE_HSIZE_L2;
1910                                 goto exit;
1911                         case MLX5_INLINE_MODE_IP:
1912                                 config->txq_inline_min =
1913                                         MLX5_INLINE_HSIZE_L3;
1914                                 goto exit;
1915                         case MLX5_INLINE_MODE_TCP_UDP:
1916                                 config->txq_inline_min =
1917                                         MLX5_INLINE_HSIZE_L4;
1918                                 goto exit;
1919                         case MLX5_INLINE_MODE_INNER_L2:
1920                                 config->txq_inline_min =
1921                                         MLX5_INLINE_HSIZE_INNER_L2;
1922                                 goto exit;
1923                         case MLX5_INLINE_MODE_INNER_IP:
1924                                 config->txq_inline_min =
1925                                         MLX5_INLINE_HSIZE_INNER_L3;
1926                                 goto exit;
1927                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1928                                 config->txq_inline_min =
1929                                         MLX5_INLINE_HSIZE_INNER_L4;
1930                                 goto exit;
1931                         }
1932                 }
1933         }
1934         /*
1935          * We get here if we are unable to deduce
1936          * inline data size with DevX. Try PCI ID
1937          * to determine old NICs.
1938          */
1939         switch (spawn->pci_dev->id.device_id) {
1940         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1941         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1942         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1943         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1944                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1945                 config->hw_vlan_insert = 0;
1946                 break;
1947         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1948         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1949         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1950         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1951                 /*
1952                  * These NICs support VLAN insertion from WQE and
1953                  * report the wqe_vlan_insert flag. But there is the bug
1954                  * and PFC control may be broken, so disable feature.
1955                  */
1956                 config->hw_vlan_insert = 0;
1957                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1958                 break;
1959         default:
1960                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1961                 break;
1962         }
1963 exit:
1964         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1965 }
1966
1967 /**
1968  * Configures the metadata mask fields in the shared context.
1969  *
1970  * @param [in] dev
1971  *   Pointer to Ethernet device.
1972  */
1973 void
1974 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1975 {
1976         struct mlx5_priv *priv = dev->data->dev_private;
1977         struct mlx5_dev_ctx_shared *sh = priv->sh;
1978         uint32_t meta, mark, reg_c0;
1979
1980         reg_c0 = ~priv->vport_meta_mask;
1981         switch (priv->config.dv_xmeta_en) {
1982         case MLX5_XMETA_MODE_LEGACY:
1983                 meta = UINT32_MAX;
1984                 mark = MLX5_FLOW_MARK_MASK;
1985                 break;
1986         case MLX5_XMETA_MODE_META16:
1987                 meta = reg_c0 >> rte_bsf32(reg_c0);
1988                 mark = MLX5_FLOW_MARK_MASK;
1989                 break;
1990         case MLX5_XMETA_MODE_META32:
1991                 meta = UINT32_MAX;
1992                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1993                 break;
1994         default:
1995                 meta = 0;
1996                 mark = 0;
1997                 MLX5_ASSERT(false);
1998                 break;
1999         }
2000         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2001                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2002                                  sh->dv_mark_mask, mark);
2003         else
2004                 sh->dv_mark_mask = mark;
2005         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2006                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2007                                  sh->dv_meta_mask, meta);
2008         else
2009                 sh->dv_meta_mask = meta;
2010         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2011                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2012                                  sh->dv_meta_mask, reg_c0);
2013         else
2014                 sh->dv_regc0_mask = reg_c0;
2015         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2016         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2017         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2018         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2019 }
2020
2021 int
2022 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2023 {
2024         static const char *const dynf_names[] = {
2025                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2026                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2027                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2028         };
2029         unsigned int i;
2030
2031         if (n < RTE_DIM(dynf_names))
2032                 return -ENOMEM;
2033         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2034                 if (names[i] == NULL)
2035                         return -EINVAL;
2036                 strcpy(names[i], dynf_names[i]);
2037         }
2038         return RTE_DIM(dynf_names);
2039 }
2040
2041 /**
2042  * Comparison callback to sort device data.
2043  *
2044  * This is meant to be used with qsort().
2045  *
2046  * @param a[in]
2047  *   Pointer to pointer to first data object.
2048  * @param b[in]
2049  *   Pointer to pointer to second data object.
2050  *
2051  * @return
2052  *   0 if both objects are equal, less than 0 if the first argument is less
2053  *   than the second, greater than 0 otherwise.
2054  */
2055 int
2056 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2057                               struct mlx5_dev_config *config)
2058 {
2059         struct mlx5_dev_ctx_shared *sh = priv->sh;
2060         struct mlx5_dev_config *sh_conf = NULL;
2061         uint16_t port_id;
2062
2063         MLX5_ASSERT(sh);
2064         /* Nothing to compare for the single/first device. */
2065         if (sh->refcnt == 1)
2066                 return 0;
2067         /* Find the device with shared context. */
2068         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2069                 struct mlx5_priv *opriv =
2070                         rte_eth_devices[port_id].data->dev_private;
2071
2072                 if (opriv && opriv != priv && opriv->sh == sh) {
2073                         sh_conf = &opriv->config;
2074                         break;
2075                 }
2076         }
2077         if (!sh_conf)
2078                 return 0;
2079         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2080                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2081                              " for shared %s context", sh->ibdev_name);
2082                 rte_errno = EINVAL;
2083                 return rte_errno;
2084         }
2085         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2086                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2087                              " for shared %s context", sh->ibdev_name);
2088                 rte_errno = EINVAL;
2089                 return rte_errno;
2090         }
2091         return 0;
2092 }
2093
2094 /**
2095  * Look for the ethernet device belonging to mlx5 driver.
2096  *
2097  * @param[in] port_id
2098  *   port_id to start looking for device.
2099  * @param[in] pci_dev
2100  *   Pointer to the hint PCI device. When device is being probed
2101  *   the its siblings (master and preceding representors might
2102  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2103  *   is not completed yet, for this case match on hint PCI
2104  *   device may be used to detect sibling device.
2105  *
2106  * @return
2107  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2108  */
2109 uint16_t
2110 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2111 {
2112         while (port_id < RTE_MAX_ETHPORTS) {
2113                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2114
2115                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2116                     dev->device &&
2117                     (dev->device == &pci_dev->device ||
2118                      (dev->device->driver &&
2119                      dev->device->driver->name &&
2120                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2121                         break;
2122                 port_id++;
2123         }
2124         if (port_id >= RTE_MAX_ETHPORTS)
2125                 return RTE_MAX_ETHPORTS;
2126         return port_id;
2127 }
2128
2129 /**
2130  * DPDK callback to remove a PCI device.
2131  *
2132  * This function removes all Ethernet devices belong to a given PCI device.
2133  *
2134  * @param[in] pci_dev
2135  *   Pointer to the PCI device.
2136  *
2137  * @return
2138  *   0 on success, the function cannot fail.
2139  */
2140 static int
2141 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2142 {
2143         uint16_t port_id;
2144         int ret = 0;
2145
2146         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2147                 /*
2148                  * mlx5_dev_close() is not registered to secondary process,
2149                  * call the close function explicitly for secondary process.
2150                  */
2151                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2152                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2153                 else
2154                         ret |= rte_eth_dev_close(port_id);
2155         }
2156         return ret == 0 ? 0 : -EIO;
2157 }
2158
2159 static const struct rte_pci_id mlx5_pci_id_map[] = {
2160         {
2161                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2162                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2163         },
2164         {
2165                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2166                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2167         },
2168         {
2169                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2170                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2171         },
2172         {
2173                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2174                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2175         },
2176         {
2177                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2178                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2179         },
2180         {
2181                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2182                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2183         },
2184         {
2185                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2186                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2187         },
2188         {
2189                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2190                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2191         },
2192         {
2193                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2194                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2195         },
2196         {
2197                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2198                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2199         },
2200         {
2201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2202                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2203         },
2204         {
2205                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2206                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2207         },
2208         {
2209                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2210                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2211         },
2212         {
2213                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2214                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2215         },
2216         {
2217                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2218                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2219         },
2220         {
2221                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2222                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2223         },
2224         {
2225                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2226                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2227         },
2228         {
2229                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2230                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2231         },
2232         {
2233                 .vendor_id = 0
2234         }
2235 };
2236
2237 static struct mlx5_pci_driver mlx5_driver = {
2238         .driver_class = MLX5_CLASS_NET,
2239         .pci_driver = {
2240                 .driver = {
2241                         .name = MLX5_PCI_DRIVER_NAME,
2242                 },
2243                 .id_table = mlx5_pci_id_map,
2244                 .probe = mlx5_os_pci_probe,
2245                 .remove = mlx5_pci_remove,
2246                 .dma_map = mlx5_dma_map,
2247                 .dma_unmap = mlx5_dma_unmap,
2248                 .drv_flags = PCI_DRV_FLAGS,
2249         },
2250 };
2251
2252 /* Initialize driver log type. */
2253 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2254
2255 /**
2256  * Driver initialization routine.
2257  */
2258 RTE_INIT(rte_mlx5_pmd_init)
2259 {
2260         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2261         mlx5_common_init();
2262         /* Build the static tables for Verbs conversion. */
2263         mlx5_set_ptype_table();
2264         mlx5_set_cksum_table();
2265         mlx5_set_swp_types_table();
2266         if (mlx5_glue)
2267                 mlx5_pci_driver_register(&mlx5_driver);
2268 }
2269
2270 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2271 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2272 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");