1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable padding Rx packet to cacheline size. */
58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
60 /* Device parameter to enable Multi-Packet Rx queue. */
61 #define MLX5_RX_MPRQ_EN "mprq_en"
63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
72 /* Device parameter to configure inline send. */
73 #define MLX5_TXQ_INLINE "txq_inline"
76 * Device parameter to configure the number of TX queues threshold for
77 * enabling inline send.
79 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
82 * Device parameter to configure the number of TX queues threshold for
83 * enabling vectorized Tx.
85 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
87 /* Device parameter to enable multi-packet send WQEs. */
88 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
90 /* Device parameter to include 2 dsegs in the title WQEBB. */
91 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
93 /* Device parameter to limit the size of inlining packet. */
94 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
96 /* Device parameter to enable hardware Tx vector. */
97 #define MLX5_TX_VEC_EN "tx_vec_en"
99 /* Device parameter to enable hardware Rx vector. */
100 #define MLX5_RX_VEC_EN "rx_vec_en"
102 /* Allow L3 VXLAN flow creation. */
103 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
105 /* Activate DV flow steering. */
106 #define MLX5_DV_FLOW_EN "dv_flow_en"
108 /* Activate Netlink support in VF mode. */
109 #define MLX5_VF_NL_EN "vf_nl_en"
111 /* Select port representors to instantiate. */
112 #define MLX5_REPRESENTOR "representor"
114 #ifndef HAVE_IBV_MLX5_MOD_MPW
115 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
116 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
119 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
120 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
123 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
125 /* Shared memory between primary and secondary processes. */
126 struct mlx5_shared_data *mlx5_shared_data;
128 /* Spinlock for mlx5_shared_data allocation. */
129 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
131 /** Driver-specific log messages type. */
135 * Prepare shared data between primary and secondary process.
138 mlx5_prepare_shared_data(void)
140 const struct rte_memzone *mz;
142 rte_spinlock_lock(&mlx5_shared_data_lock);
143 if (mlx5_shared_data == NULL) {
144 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
145 /* Allocate shared memory. */
146 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
147 sizeof(*mlx5_shared_data),
150 /* Lookup allocated shared memory. */
151 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
154 rte_panic("Cannot allocate mlx5 shared data\n");
155 mlx5_shared_data = mz->addr;
156 /* Initialize shared data. */
157 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
158 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
159 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
161 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
162 mlx5_mr_mem_event_cb, NULL);
164 rte_spinlock_unlock(&mlx5_shared_data_lock);
168 * Retrieve integer value from environment variable.
171 * Environment variable name.
174 * Integer value, 0 if the variable is not set.
177 mlx5_getenv_int(const char *name)
179 const char *val = getenv(name);
187 * Verbs callback to allocate a memory. This function should allocate the space
188 * according to the size provided residing inside a huge page.
189 * Please note that all allocation must respect the alignment from libmlx5
190 * (i.e. currently sysconf(_SC_PAGESIZE)).
193 * The size in bytes of the memory to allocate.
195 * A pointer to the callback data.
198 * Allocated buffer, NULL otherwise and rte_errno is set.
201 mlx5_alloc_verbs_buf(size_t size, void *data)
203 struct priv *priv = data;
205 size_t alignment = sysconf(_SC_PAGESIZE);
206 unsigned int socket = SOCKET_ID_ANY;
208 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
209 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
211 socket = ctrl->socket;
212 } else if (priv->verbs_alloc_ctx.type ==
213 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
214 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
216 socket = ctrl->socket;
218 assert(data != NULL);
219 ret = rte_malloc_socket(__func__, size, alignment, socket);
226 * Verbs callback to free a memory.
229 * A pointer to the memory to free.
231 * A pointer to the callback data.
234 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
236 assert(data != NULL);
241 * DPDK callback to close the device.
243 * Destroy all queues and objects, free memory.
246 * Pointer to Ethernet device structure.
249 mlx5_dev_close(struct rte_eth_dev *dev)
251 struct priv *priv = dev->data->dev_private;
255 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
257 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
258 /* In case mlx5_dev_stop() has not been called. */
259 mlx5_dev_interrupt_handler_uninstall(dev);
260 mlx5_traffic_disable(dev);
261 mlx5_flow_flush(dev, NULL);
262 /* Prevent crashes when queues are still in use. */
263 dev->rx_pkt_burst = removed_rx_burst;
264 dev->tx_pkt_burst = removed_tx_burst;
265 if (priv->rxqs != NULL) {
266 /* XXX race condition if mlx5_rx_burst() is still running. */
268 for (i = 0; (i != priv->rxqs_n); ++i)
269 mlx5_rxq_release(dev, i);
273 if (priv->txqs != NULL) {
274 /* XXX race condition if mlx5_tx_burst() is still running. */
276 for (i = 0; (i != priv->txqs_n); ++i)
277 mlx5_txq_release(dev, i);
281 mlx5_mprq_free_mp(dev);
282 mlx5_mr_release(dev);
283 if (priv->pd != NULL) {
284 assert(priv->ctx != NULL);
285 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
286 claim_zero(mlx5_glue->close_device(priv->ctx));
288 assert(priv->ctx == NULL);
289 if (priv->rss_conf.rss_key != NULL)
290 rte_free(priv->rss_conf.rss_key);
291 if (priv->reta_idx != NULL)
292 rte_free(priv->reta_idx);
293 if (priv->primary_socket)
294 mlx5_socket_uninit(dev);
296 mlx5_nl_mac_addr_flush(dev);
297 if (priv->nl_socket_route >= 0)
298 close(priv->nl_socket_route);
299 if (priv->nl_socket_rdma >= 0)
300 close(priv->nl_socket_rdma);
301 if (priv->tcf_context)
302 mlx5_flow_tcf_context_destroy(priv->tcf_context);
303 ret = mlx5_hrxq_ibv_verify(dev);
305 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
307 ret = mlx5_ind_table_ibv_verify(dev);
309 DRV_LOG(WARNING, "port %u some indirection table still remain",
311 ret = mlx5_rxq_ibv_verify(dev);
313 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
315 ret = mlx5_rxq_verify(dev);
317 DRV_LOG(WARNING, "port %u some Rx queues still remain",
319 ret = mlx5_txq_ibv_verify(dev);
321 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
323 ret = mlx5_txq_verify(dev);
325 DRV_LOG(WARNING, "port %u some Tx queues still remain",
327 ret = mlx5_flow_verify(dev);
329 DRV_LOG(WARNING, "port %u some flows still remain",
331 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
333 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
336 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
339 rte_eth_devices[port_id[i]].data->dev_private;
342 opriv->domain_id != priv->domain_id ||
343 &rte_eth_devices[port_id[i]] == dev)
348 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
350 memset(priv, 0, sizeof(*priv));
351 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
353 * Reset mac_addrs to NULL such that it is not freed as part of
354 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
355 * it is freed when dev_private is freed.
357 dev->data->mac_addrs = NULL;
360 const struct eth_dev_ops mlx5_dev_ops = {
361 .dev_configure = mlx5_dev_configure,
362 .dev_start = mlx5_dev_start,
363 .dev_stop = mlx5_dev_stop,
364 .dev_set_link_down = mlx5_set_link_down,
365 .dev_set_link_up = mlx5_set_link_up,
366 .dev_close = mlx5_dev_close,
367 .promiscuous_enable = mlx5_promiscuous_enable,
368 .promiscuous_disable = mlx5_promiscuous_disable,
369 .allmulticast_enable = mlx5_allmulticast_enable,
370 .allmulticast_disable = mlx5_allmulticast_disable,
371 .link_update = mlx5_link_update,
372 .stats_get = mlx5_stats_get,
373 .stats_reset = mlx5_stats_reset,
374 .xstats_get = mlx5_xstats_get,
375 .xstats_reset = mlx5_xstats_reset,
376 .xstats_get_names = mlx5_xstats_get_names,
377 .dev_infos_get = mlx5_dev_infos_get,
378 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
379 .vlan_filter_set = mlx5_vlan_filter_set,
380 .rx_queue_setup = mlx5_rx_queue_setup,
381 .tx_queue_setup = mlx5_tx_queue_setup,
382 .rx_queue_release = mlx5_rx_queue_release,
383 .tx_queue_release = mlx5_tx_queue_release,
384 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
385 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
386 .mac_addr_remove = mlx5_mac_addr_remove,
387 .mac_addr_add = mlx5_mac_addr_add,
388 .mac_addr_set = mlx5_mac_addr_set,
389 .set_mc_addr_list = mlx5_set_mc_addr_list,
390 .mtu_set = mlx5_dev_set_mtu,
391 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
392 .vlan_offload_set = mlx5_vlan_offload_set,
393 .reta_update = mlx5_dev_rss_reta_update,
394 .reta_query = mlx5_dev_rss_reta_query,
395 .rss_hash_update = mlx5_rss_hash_update,
396 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
397 .filter_ctrl = mlx5_dev_filter_ctrl,
398 .rx_descriptor_status = mlx5_rx_descriptor_status,
399 .tx_descriptor_status = mlx5_tx_descriptor_status,
400 .rx_queue_count = mlx5_rx_queue_count,
401 .rx_queue_intr_enable = mlx5_rx_intr_enable,
402 .rx_queue_intr_disable = mlx5_rx_intr_disable,
403 .is_removed = mlx5_is_removed,
406 static const struct eth_dev_ops mlx5_dev_sec_ops = {
407 .stats_get = mlx5_stats_get,
408 .stats_reset = mlx5_stats_reset,
409 .xstats_get = mlx5_xstats_get,
410 .xstats_reset = mlx5_xstats_reset,
411 .xstats_get_names = mlx5_xstats_get_names,
412 .dev_infos_get = mlx5_dev_infos_get,
413 .rx_descriptor_status = mlx5_rx_descriptor_status,
414 .tx_descriptor_status = mlx5_tx_descriptor_status,
417 /* Available operators in flow isolated mode. */
418 const struct eth_dev_ops mlx5_dev_ops_isolate = {
419 .dev_configure = mlx5_dev_configure,
420 .dev_start = mlx5_dev_start,
421 .dev_stop = mlx5_dev_stop,
422 .dev_set_link_down = mlx5_set_link_down,
423 .dev_set_link_up = mlx5_set_link_up,
424 .dev_close = mlx5_dev_close,
425 .promiscuous_enable = mlx5_promiscuous_enable,
426 .promiscuous_disable = mlx5_promiscuous_disable,
427 .allmulticast_enable = mlx5_allmulticast_enable,
428 .allmulticast_disable = mlx5_allmulticast_disable,
429 .link_update = mlx5_link_update,
430 .stats_get = mlx5_stats_get,
431 .stats_reset = mlx5_stats_reset,
432 .xstats_get = mlx5_xstats_get,
433 .xstats_reset = mlx5_xstats_reset,
434 .xstats_get_names = mlx5_xstats_get_names,
435 .dev_infos_get = mlx5_dev_infos_get,
436 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
437 .vlan_filter_set = mlx5_vlan_filter_set,
438 .rx_queue_setup = mlx5_rx_queue_setup,
439 .tx_queue_setup = mlx5_tx_queue_setup,
440 .rx_queue_release = mlx5_rx_queue_release,
441 .tx_queue_release = mlx5_tx_queue_release,
442 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
443 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
444 .mac_addr_remove = mlx5_mac_addr_remove,
445 .mac_addr_add = mlx5_mac_addr_add,
446 .mac_addr_set = mlx5_mac_addr_set,
447 .set_mc_addr_list = mlx5_set_mc_addr_list,
448 .mtu_set = mlx5_dev_set_mtu,
449 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
450 .vlan_offload_set = mlx5_vlan_offload_set,
451 .filter_ctrl = mlx5_dev_filter_ctrl,
452 .rx_descriptor_status = mlx5_rx_descriptor_status,
453 .tx_descriptor_status = mlx5_tx_descriptor_status,
454 .rx_queue_intr_enable = mlx5_rx_intr_enable,
455 .rx_queue_intr_disable = mlx5_rx_intr_disable,
456 .is_removed = mlx5_is_removed,
460 * Verify and store value for device argument.
463 * Key argument to verify.
465 * Value associated with key.
470 * 0 on success, a negative errno value otherwise and rte_errno is set.
473 mlx5_args_check(const char *key, const char *val, void *opaque)
475 struct mlx5_dev_config *config = opaque;
478 /* No-op, port representors are processed in mlx5_dev_spawn(). */
479 if (!strcmp(MLX5_REPRESENTOR, key))
482 tmp = strtoul(val, NULL, 0);
485 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
488 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
489 config->cqe_comp = !!tmp;
490 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
491 config->cqe_pad = !!tmp;
492 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
493 config->hw_padding = !!tmp;
494 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
495 config->mprq.enabled = !!tmp;
496 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
497 config->mprq.stride_num_n = tmp;
498 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
499 config->mprq.max_memcpy_len = tmp;
500 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
501 config->mprq.min_rxqs_num = tmp;
502 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
503 config->txq_inline = tmp;
504 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
505 config->txqs_inline = tmp;
506 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
507 config->txqs_vec = tmp;
508 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
510 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
511 config->mpw_hdr_dseg = !!tmp;
512 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
513 config->inline_max_packet_sz = tmp;
514 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
515 config->tx_vec_en = !!tmp;
516 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
517 config->rx_vec_en = !!tmp;
518 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
519 config->l3_vxlan_en = !!tmp;
520 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
521 config->vf_nl_en = !!tmp;
522 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
523 config->dv_flow_en = !!tmp;
525 DRV_LOG(WARNING, "%s: unknown parameter", key);
533 * Parse device parameters.
536 * Pointer to device configuration structure.
538 * Device arguments structure.
541 * 0 on success, a negative errno value otherwise and rte_errno is set.
544 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
546 const char **params = (const char *[]){
547 MLX5_RXQ_CQE_COMP_EN,
551 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
552 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
555 MLX5_TXQS_MIN_INLINE,
558 MLX5_TXQ_MPW_HDR_DSEG_EN,
559 MLX5_TXQ_MAX_INLINE_LEN,
568 struct rte_kvargs *kvlist;
574 /* Following UGLY cast is done to pass checkpatch. */
575 kvlist = rte_kvargs_parse(devargs->args, params);
578 /* Process parameters. */
579 for (i = 0; (params[i] != NULL); ++i) {
580 if (rte_kvargs_count(kvlist, params[i])) {
581 ret = rte_kvargs_process(kvlist, params[i],
582 mlx5_args_check, config);
585 rte_kvargs_free(kvlist);
590 rte_kvargs_free(kvlist);
594 static struct rte_pci_driver mlx5_driver;
597 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
598 * local resource used by both primary and secondary to avoid duplicate
600 * The space has to be available on both primary and secondary process,
601 * TXQ UAR maps to this area using fixed mmap w/o double check.
603 static void *uar_base;
606 find_lower_va_bound(const struct rte_memseg_list *msl,
607 const struct rte_memseg *ms, void *arg)
616 *addr = RTE_MIN(*addr, ms->addr);
622 * Reserve UAR address space for primary process.
625 * Pointer to Ethernet device.
628 * 0 on success, a negative errno value otherwise and rte_errno is set.
631 mlx5_uar_init_primary(struct rte_eth_dev *dev)
633 struct priv *priv = dev->data->dev_private;
634 void *addr = (void *)0;
636 if (uar_base) { /* UAR address space mapped. */
637 priv->uar_base = uar_base;
640 /* find out lower bound of hugepage segments */
641 rte_memseg_walk(find_lower_va_bound, &addr);
643 /* keep distance to hugepages to minimize potential conflicts. */
644 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
645 /* anonymous mmap, no real memory consumption. */
646 addr = mmap(addr, MLX5_UAR_SIZE,
647 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
648 if (addr == MAP_FAILED) {
650 "port %u failed to reserve UAR address space, please"
651 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
656 /* Accept either same addr or a new addr returned from mmap if target
659 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
660 dev->data->port_id, addr);
661 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
662 uar_base = addr; /* process local, don't reserve again. */
667 * Reserve UAR address space for secondary process, align with
671 * Pointer to Ethernet device.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
679 struct priv *priv = dev->data->dev_private;
682 assert(priv->uar_base);
683 if (uar_base) { /* already reserved. */
684 assert(uar_base == priv->uar_base);
687 /* anonymous mmap, no real memory consumption. */
688 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
689 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
690 if (addr == MAP_FAILED) {
691 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
692 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
696 if (priv->uar_base != addr) {
698 "port %u UAR address %p size %llu occupied, please"
699 " adjust MLX5_UAR_OFFSET or try EAL parameter"
701 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
705 uar_base = addr; /* process local, don't reserve again */
706 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
707 dev->data->port_id, addr);
712 * Spawn an Ethernet device from Verbs information.
715 * Backing DPDK device.
719 * Device configuration parameters.
720 * @param[in] switch_info
721 * Switch properties of Ethernet device.
724 * A valid Ethernet device object on success, NULL otherwise and rte_errno
725 * is set. The following errors are defined:
727 * EBUSY: device is not supposed to be spawned.
728 * EEXIST: device is already spawned
730 static struct rte_eth_dev *
731 mlx5_dev_spawn(struct rte_device *dpdk_dev,
732 struct ibv_device *ibv_dev,
733 struct mlx5_dev_config config,
734 const struct mlx5_switch_info *switch_info)
736 struct ibv_context *ctx = NULL;
737 struct ibv_device_attr_ex attr;
738 struct ibv_port_attr port_attr;
739 struct ibv_pd *pd = NULL;
740 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
741 struct rte_eth_dev *eth_dev = NULL;
742 struct priv *priv = NULL;
744 unsigned int hw_padding = 0;
746 unsigned int cqe_comp;
747 unsigned int cqe_pad = 0;
748 unsigned int tunnel_en = 0;
749 unsigned int mpls_en = 0;
750 unsigned int swp = 0;
751 unsigned int mprq = 0;
752 unsigned int mprq_min_stride_size_n = 0;
753 unsigned int mprq_max_stride_size_n = 0;
754 unsigned int mprq_min_stride_num_n = 0;
755 unsigned int mprq_max_stride_num_n = 0;
756 struct ether_addr mac;
757 char name[RTE_ETH_NAME_MAX_LEN];
758 int own_domain_id = 0;
762 /* Determine if this port representor is supposed to be spawned. */
763 if (switch_info->representor && dpdk_dev->devargs) {
764 struct rte_eth_devargs eth_da;
766 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
769 DRV_LOG(ERR, "failed to process device arguments: %s",
770 strerror(rte_errno));
773 for (i = 0; i < eth_da.nb_representor_ports; ++i)
774 if (eth_da.representor_ports[i] ==
775 (uint16_t)switch_info->port_name)
777 if (i == eth_da.nb_representor_ports) {
782 /* Build device name. */
783 if (!switch_info->representor)
784 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
786 snprintf(name, sizeof(name), "%s_representor_%u",
787 dpdk_dev->name, switch_info->port_name);
788 /* check if the device is already spawned */
789 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
793 /* Prepare shared data between primary and secondary process. */
794 mlx5_prepare_shared_data();
796 ctx = mlx5_glue->dv_open_device(ibv_dev);
799 DRV_LOG(DEBUG, "DEVX is supported");
801 ctx = mlx5_glue->open_device(ibv_dev);
803 rte_errno = errno ? errno : ENODEV;
807 #ifdef HAVE_IBV_MLX5_MOD_SWP
808 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
811 * Multi-packet send is supported by ConnectX-4 Lx PF as well
812 * as all ConnectX-5 devices.
814 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
815 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
817 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
818 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
820 mlx5_glue->dv_query_device(ctx, &dv_attr);
821 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
822 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
823 DRV_LOG(DEBUG, "enhanced MPW is supported");
824 mps = MLX5_MPW_ENHANCED;
826 DRV_LOG(DEBUG, "MPW is supported");
830 DRV_LOG(DEBUG, "MPW isn't supported");
831 mps = MLX5_MPW_DISABLED;
833 #ifdef HAVE_IBV_MLX5_MOD_SWP
834 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
835 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
836 DRV_LOG(DEBUG, "SWP support: %u", swp);
839 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
840 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
841 struct mlx5dv_striding_rq_caps mprq_caps =
842 dv_attr.striding_rq_caps;
844 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
845 mprq_caps.min_single_stride_log_num_of_bytes);
846 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
847 mprq_caps.max_single_stride_log_num_of_bytes);
848 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
849 mprq_caps.min_single_wqe_log_num_of_strides);
850 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
851 mprq_caps.max_single_wqe_log_num_of_strides);
852 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
853 mprq_caps.supported_qpts);
854 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
856 mprq_min_stride_size_n =
857 mprq_caps.min_single_stride_log_num_of_bytes;
858 mprq_max_stride_size_n =
859 mprq_caps.max_single_stride_log_num_of_bytes;
860 mprq_min_stride_num_n =
861 mprq_caps.min_single_wqe_log_num_of_strides;
862 mprq_max_stride_num_n =
863 mprq_caps.max_single_wqe_log_num_of_strides;
864 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
865 mprq_min_stride_num_n);
868 if (RTE_CACHE_LINE_SIZE == 128 &&
869 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
873 config.cqe_comp = cqe_comp;
874 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
875 /* Whether device supports 128B Rx CQE padding. */
876 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
877 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
879 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
880 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
881 tunnel_en = ((dv_attr.tunnel_offloads_caps &
882 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
883 (dv_attr.tunnel_offloads_caps &
884 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
886 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
887 tunnel_en ? "" : "not ");
890 "tunnel offloading disabled due to old OFED/rdma-core version");
892 config.tunnel_en = tunnel_en;
893 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
894 mpls_en = ((dv_attr.tunnel_offloads_caps &
895 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
896 (dv_attr.tunnel_offloads_caps &
897 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
898 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
899 mpls_en ? "" : "not ");
901 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
902 " old OFED/rdma-core version or firmware configuration");
904 config.mpls_en = mpls_en;
905 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
907 DEBUG("ibv_query_device_ex() failed");
910 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
911 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
912 eth_dev = rte_eth_dev_attach_secondary(name);
913 if (eth_dev == NULL) {
914 DRV_LOG(ERR, "can not attach rte ethdev");
919 eth_dev->device = dpdk_dev;
920 eth_dev->dev_ops = &mlx5_dev_sec_ops;
921 err = mlx5_uar_init_secondary(eth_dev);
926 /* Receive command fd from primary process */
927 err = mlx5_socket_connect(eth_dev);
932 /* Remap UAR for Tx queues. */
933 err = mlx5_tx_uar_remap(eth_dev, err);
939 * Ethdev pointer is still required as input since
940 * the primary device is not accessible from the
943 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
944 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
945 claim_zero(mlx5_glue->close_device(ctx));
948 /* Check port status. */
949 err = mlx5_glue->query_port(ctx, 1, &port_attr);
951 DRV_LOG(ERR, "port query failed: %s", strerror(err));
954 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
955 DRV_LOG(ERR, "port is not configured in Ethernet mode");
959 if (port_attr.state != IBV_PORT_ACTIVE)
960 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
961 mlx5_glue->port_state_str(port_attr.state),
963 /* Allocate protection domain. */
964 pd = mlx5_glue->alloc_pd(ctx);
966 DRV_LOG(ERR, "PD allocation failure");
970 priv = rte_zmalloc("ethdev private structure",
972 RTE_CACHE_LINE_SIZE);
974 DRV_LOG(ERR, "priv allocation failure");
979 strncpy(priv->ibdev_name, priv->ctx->device->name,
980 sizeof(priv->ibdev_name));
981 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
982 sizeof(priv->ibdev_path));
983 priv->device_attr = attr;
985 priv->mtu = ETHER_MTU;
987 /* Initialize UAR access locks for 32bit implementations. */
988 rte_spinlock_init(&priv->uar_lock_cq);
989 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
990 rte_spinlock_init(&priv->uar_lock[i]);
992 /* Some internal functions rely on Netlink sockets, open them now. */
993 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
994 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
996 priv->representor = !!switch_info->representor;
997 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
998 priv->representor_id =
999 switch_info->representor ? switch_info->port_name : -1;
1001 * Look for sibling devices in order to reuse their switch domain
1002 * if any, otherwise allocate one.
1004 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
1006 uint16_t port_id[i];
1008 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1010 const struct priv *opriv =
1011 rte_eth_devices[port_id[i]].data->dev_private;
1015 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1017 priv->domain_id = opriv->domain_id;
1021 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1022 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1025 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1026 strerror(rte_errno));
1031 err = mlx5_args(&config, dpdk_dev->devargs);
1034 DRV_LOG(ERR, "failed to process device arguments: %s",
1035 strerror(rte_errno));
1038 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1039 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1040 (config.hw_csum ? "" : "not "));
1041 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1042 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1043 DRV_LOG(DEBUG, "counters are not supported");
1045 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1046 if (config.dv_flow_en) {
1047 DRV_LOG(WARNING, "DV flow is not supported");
1048 config.dv_flow_en = 0;
1051 config.ind_table_max_size =
1052 attr.rss_caps.max_rwq_indirection_table_size;
1054 * Remove this check once DPDK supports larger/variable
1055 * indirection tables.
1057 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1058 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1059 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1060 config.ind_table_max_size);
1061 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1062 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1063 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1064 (config.hw_vlan_strip ? "" : "not "));
1065 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1066 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1067 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1068 (config.hw_fcs_strip ? "" : "not "));
1069 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1070 hw_padding = !!attr.rx_pad_end_addr_align;
1072 if (config.hw_padding && !hw_padding) {
1073 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
1074 config.hw_padding = 0;
1075 } else if (config.hw_padding) {
1076 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
1078 config.tso = (attr.tso_caps.max_tso > 0 &&
1079 (attr.tso_caps.supported_qpts &
1080 (1 << IBV_QPT_RAW_PACKET)));
1082 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1084 * MPW is disabled by default, while the Enhanced MPW is enabled
1087 if (config.mps == MLX5_ARG_UNSET)
1088 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1091 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1092 DRV_LOG(INFO, "%sMPS is %s",
1093 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1094 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1095 if (config.cqe_comp && !cqe_comp) {
1096 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1097 config.cqe_comp = 0;
1099 if (config.cqe_pad && !cqe_pad) {
1100 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1102 } else if (config.cqe_pad) {
1103 DRV_LOG(INFO, "Rx CQE padding is enabled");
1105 if (config.mprq.enabled && mprq) {
1106 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1107 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1108 config.mprq.stride_num_n =
1109 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1110 mprq_min_stride_num_n);
1112 "the number of strides"
1113 " for Multi-Packet RQ is out of range,"
1114 " setting default value (%u)",
1115 1 << config.mprq.stride_num_n);
1117 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1118 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1119 } else if (config.mprq.enabled && !mprq) {
1120 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1121 config.mprq.enabled = 0;
1123 eth_dev = rte_eth_dev_allocate(name);
1124 if (eth_dev == NULL) {
1125 DRV_LOG(ERR, "can not allocate rte ethdev");
1129 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1130 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1131 if (priv->representor) {
1132 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1133 eth_dev->data->representor_id = priv->representor_id;
1135 eth_dev->data->dev_private = priv;
1136 priv->dev_data = eth_dev->data;
1137 eth_dev->data->mac_addrs = priv->mac;
1138 eth_dev->device = dpdk_dev;
1139 err = mlx5_uar_init_primary(eth_dev);
1144 /* Configure the first MAC address by default. */
1145 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1147 "port %u cannot get MAC address, is mlx5_en"
1148 " loaded? (errno: %s)",
1149 eth_dev->data->port_id, strerror(rte_errno));
1154 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1155 eth_dev->data->port_id,
1156 mac.addr_bytes[0], mac.addr_bytes[1],
1157 mac.addr_bytes[2], mac.addr_bytes[3],
1158 mac.addr_bytes[4], mac.addr_bytes[5]);
1161 char ifname[IF_NAMESIZE];
1163 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1164 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1165 eth_dev->data->port_id, ifname);
1167 DRV_LOG(DEBUG, "port %u ifname is unknown",
1168 eth_dev->data->port_id);
1171 /* Get actual MTU if possible. */
1172 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1177 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1179 /* Initialize burst functions to prevent crashes before link-up. */
1180 eth_dev->rx_pkt_burst = removed_rx_burst;
1181 eth_dev->tx_pkt_burst = removed_tx_burst;
1182 eth_dev->dev_ops = &mlx5_dev_ops;
1183 /* Register MAC address. */
1184 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1185 if (config.vf && config.vf_nl_en)
1186 mlx5_nl_mac_addr_sync(eth_dev);
1187 priv->tcf_context = mlx5_flow_tcf_context_create();
1188 if (!priv->tcf_context) {
1191 "flow rules relying on switch offloads will not be"
1192 " supported: cannot open libmnl socket: %s",
1193 strerror(rte_errno));
1195 struct rte_flow_error error;
1196 unsigned int ifindex = mlx5_ifindex(eth_dev);
1201 "cannot retrieve network interface index";
1203 err = mlx5_flow_tcf_init(priv->tcf_context,
1208 "flow rules relying on switch offloads will"
1209 " not be supported: %s: %s",
1210 error.message, strerror(rte_errno));
1211 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1212 priv->tcf_context = NULL;
1215 TAILQ_INIT(&priv->flows);
1216 TAILQ_INIT(&priv->ctrl_flows);
1217 /* Hint libmlx5 to use PMD allocator for data plane resources */
1218 struct mlx5dv_ctx_allocators alctr = {
1219 .alloc = &mlx5_alloc_verbs_buf,
1220 .free = &mlx5_free_verbs_buf,
1223 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1224 (void *)((uintptr_t)&alctr));
1225 /* Bring Ethernet device up. */
1226 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1227 eth_dev->data->port_id);
1228 mlx5_set_link_up(eth_dev);
1230 * Even though the interrupt handler is not installed yet,
1231 * interrupts will still trigger on the asyn_fd from
1232 * Verbs context returned by ibv_open_device().
1234 mlx5_link_update(eth_dev, 0);
1235 /* Store device configuration on private structure. */
1236 priv->config = config;
1237 /* Supported Verbs flow priority number detection. */
1238 err = mlx5_flow_discover_priorities(eth_dev);
1241 priv->config.flow_prio = err;
1243 * Once the device is added to the list of memory event
1244 * callback, its global MR cache table cannot be expanded
1245 * on the fly because of deadlock. If it overflows, lookup
1246 * should be done by searching MR list linearly, which is slow.
1248 err = mlx5_mr_btree_init(&priv->mr.cache,
1249 MLX5_MR_BTREE_CACHE_N * 2,
1250 eth_dev->device->numa_node);
1255 /* Add device to memory callback list. */
1256 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1257 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1258 priv, mem_event_cb);
1259 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1263 if (priv->nl_socket_route >= 0)
1264 close(priv->nl_socket_route);
1265 if (priv->nl_socket_rdma >= 0)
1266 close(priv->nl_socket_rdma);
1267 if (priv->tcf_context)
1268 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1270 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1272 if (eth_dev != NULL)
1273 eth_dev->data->dev_private = NULL;
1276 claim_zero(mlx5_glue->dealloc_pd(pd));
1277 if (eth_dev != NULL) {
1278 /* mac_addrs must not be freed alone because part of dev_private */
1279 eth_dev->data->mac_addrs = NULL;
1280 rte_eth_dev_release_port(eth_dev);
1283 claim_zero(mlx5_glue->close_device(ctx));
1289 /** Data associated with devices to spawn. */
1290 struct mlx5_dev_spawn_data {
1291 unsigned int ifindex; /**< Network interface index. */
1292 struct mlx5_switch_info info; /**< Switch information. */
1293 struct ibv_device *ibv_dev; /**< Associated IB device. */
1294 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1298 * Comparison callback to sort device data.
1300 * This is meant to be used with qsort().
1303 * Pointer to pointer to first data object.
1305 * Pointer to pointer to second data object.
1308 * 0 if both objects are equal, less than 0 if the first argument is less
1309 * than the second, greater than 0 otherwise.
1312 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1314 const struct mlx5_switch_info *si_a =
1315 &((const struct mlx5_dev_spawn_data *)a)->info;
1316 const struct mlx5_switch_info *si_b =
1317 &((const struct mlx5_dev_spawn_data *)b)->info;
1320 /* Master device first. */
1321 ret = si_b->master - si_a->master;
1324 /* Then representor devices. */
1325 ret = si_b->representor - si_a->representor;
1328 /* Unidentified devices come last in no specific order. */
1329 if (!si_a->representor)
1331 /* Order representors by name. */
1332 return si_a->port_name - si_b->port_name;
1336 * DPDK callback to register a PCI device.
1338 * This function spawns Ethernet devices out of a given PCI device.
1340 * @param[in] pci_drv
1341 * PCI driver structure (mlx5_driver).
1342 * @param[in] pci_dev
1343 * PCI device information.
1346 * 0 on success, a negative errno value otherwise and rte_errno is set.
1349 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1350 struct rte_pci_device *pci_dev)
1352 struct ibv_device **ibv_list;
1354 struct mlx5_dev_config dev_config;
1357 assert(pci_drv == &mlx5_driver);
1359 ibv_list = mlx5_glue->get_device_list(&ret);
1361 rte_errno = errno ? errno : ENOSYS;
1362 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1366 struct ibv_device *ibv_match[ret + 1];
1369 struct rte_pci_addr pci_addr;
1371 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1372 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1374 if (pci_dev->addr.domain != pci_addr.domain ||
1375 pci_dev->addr.bus != pci_addr.bus ||
1376 pci_dev->addr.devid != pci_addr.devid ||
1377 pci_dev->addr.function != pci_addr.function)
1379 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1380 ibv_list[ret]->name);
1381 ibv_match[n++] = ibv_list[ret];
1383 ibv_match[n] = NULL;
1385 struct mlx5_dev_spawn_data list[n];
1386 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1387 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1392 * The existence of several matching entries (n > 1) means port
1393 * representors have been instantiated. No existing Verbs call nor
1394 * /sys entries can tell them apart, this can only be done through
1395 * Netlink calls assuming kernel drivers are recent enough to
1398 * In the event of identification failure through Netlink, try again
1399 * through sysfs, then either:
1401 * 1. No device matches (n == 0), complain and bail out.
1402 * 2. A single IB device matches (n == 1) and is not a representor,
1403 * assume no switch support.
1404 * 3. Otherwise no safe assumptions can be made; complain louder and
1407 for (i = 0; i != n; ++i) {
1408 list[i].ibv_dev = ibv_match[i];
1409 list[i].eth_dev = NULL;
1411 list[i].ifindex = 0;
1413 list[i].ifindex = mlx5_nl_ifindex
1414 (nl_rdma, list[i].ibv_dev->name);
1417 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1419 ((!list[i].info.representor && !list[i].info.master) &&
1420 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1421 list[i].ifindex = 0;
1422 memset(&list[i].info, 0, sizeof(list[i].info));
1430 /* Count unidentified devices. */
1431 for (u = 0, i = 0; i != n; ++i)
1432 if (!list[i].info.master && !list[i].info.representor)
1435 if (n == 1 && u == 1) {
1437 DRV_LOG(INFO, "no switch support detected");
1441 "unable to tell which of the matching devices"
1442 " is the master (lack of kernel support?)");
1447 * Sort list to probe devices in natural order for users convenience
1448 * (i.e. master first, then representors from lowest to highest ID).
1451 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1452 /* Default configuration. */
1453 dev_config = (struct mlx5_dev_config){
1455 .mps = MLX5_ARG_UNSET,
1458 .txq_inline = MLX5_ARG_UNSET,
1459 .txqs_inline = MLX5_ARG_UNSET,
1460 .txqs_vec = MLX5_ARG_UNSET,
1461 .inline_max_packet_sz = MLX5_ARG_UNSET,
1464 .enabled = 0, /* Disabled by default. */
1465 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1466 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1467 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1470 /* Device speicific configuration. */
1471 switch (pci_dev->id.device_id) {
1472 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1473 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1475 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1476 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1477 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1478 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1484 /* Set architecture-dependent default value if unset. */
1485 if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1486 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1487 for (i = 0; i != n; ++i) {
1490 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1491 list[i].ibv_dev, dev_config,
1493 if (!list[i].eth_dev) {
1494 if (rte_errno != EBUSY && rte_errno != EEXIST)
1496 /* Device is disabled or already spawned. Ignore it. */
1499 restore = list[i].eth_dev->data->dev_flags;
1500 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1501 /* Restore non-PCI flags cleared by the above call. */
1502 list[i].eth_dev->data->dev_flags |= restore;
1503 rte_eth_dev_probing_finish(list[i].eth_dev);
1505 mlx5_glue->free_device_list(ibv_list);
1508 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1509 " are kernel drivers loaded?",
1510 pci_dev->addr.domain, pci_dev->addr.bus,
1511 pci_dev->addr.devid, pci_dev->addr.function);
1514 } else if (i != n) {
1516 "probe of PCI device " PCI_PRI_FMT " aborted after"
1517 " encountering an error: %s",
1518 pci_dev->addr.domain, pci_dev->addr.bus,
1519 pci_dev->addr.devid, pci_dev->addr.function,
1520 strerror(rte_errno));
1524 if (!list[i].eth_dev)
1526 mlx5_dev_close(list[i].eth_dev);
1527 /* mac_addrs must not be freed because in dev_private */
1528 list[i].eth_dev->data->mac_addrs = NULL;
1529 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1531 /* Restore original error. */
1540 * DPDK callback to remove a PCI device.
1542 * This function removes all Ethernet devices belong to a given PCI device.
1544 * @param[in] pci_dev
1545 * Pointer to the PCI device.
1548 * 0 on success, the function cannot fail.
1551 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1554 struct rte_eth_dev *port;
1556 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1557 port = &rte_eth_devices[port_id];
1558 if (port->state != RTE_ETH_DEV_UNUSED &&
1559 port->device == &pci_dev->device)
1560 rte_eth_dev_close(port_id);
1565 static const struct rte_pci_id mlx5_pci_id_map[] = {
1567 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1568 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1571 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1572 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1575 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1576 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1579 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1580 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1583 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1584 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1587 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1588 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1591 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1592 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1595 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1596 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1599 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1600 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1603 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1604 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1607 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1608 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1611 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1612 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1619 static struct rte_pci_driver mlx5_driver = {
1621 .name = MLX5_DRIVER_NAME
1623 .id_table = mlx5_pci_id_map,
1624 .probe = mlx5_pci_probe,
1625 .remove = mlx5_pci_remove,
1626 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1627 RTE_PCI_DRV_PROBE_AGAIN),
1630 #ifdef RTE_IBVERBS_LINK_DLOPEN
1633 * Suffix RTE_EAL_PMD_PATH with "-glue".
1635 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1636 * suffixing its last component.
1639 * Output buffer, should be large enough otherwise NULL is returned.
1644 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1647 mlx5_glue_path(char *buf, size_t size)
1649 static const char *const bad[] = { "/", ".", "..", NULL };
1650 const char *path = RTE_EAL_PMD_PATH;
1651 size_t len = strlen(path);
1655 while (len && path[len - 1] == '/')
1657 for (off = len; off && path[off - 1] != '/'; --off)
1659 for (i = 0; bad[i]; ++i)
1660 if (!strncmp(path + off, bad[i], (int)(len - off)))
1662 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1663 if (i == -1 || (size_t)i >= size)
1668 "unable to append \"-glue\" to last component of"
1669 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1670 " please re-configure DPDK");
1675 * Initialization routine for run-time dependency on rdma-core.
1678 mlx5_glue_init(void)
1680 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1681 const char *path[] = {
1683 * A basic security check is necessary before trusting
1684 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1686 (geteuid() == getuid() && getegid() == getgid() ?
1687 getenv("MLX5_GLUE_PATH") : NULL),
1689 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1690 * variant, otherwise let dlopen() look up libraries on its
1693 (*RTE_EAL_PMD_PATH ?
1694 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1697 void *handle = NULL;
1701 while (!handle && i != RTE_DIM(path)) {
1710 end = strpbrk(path[i], ":;");
1712 end = path[i] + strlen(path[i]);
1713 len = end - path[i];
1718 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1720 (!len || *(end - 1) == '/') ? "" : "/");
1723 if (sizeof(name) != (size_t)ret + 1)
1725 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1727 handle = dlopen(name, RTLD_LAZY);
1738 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1741 sym = dlsym(handle, "mlx5_glue");
1742 if (!sym || !*sym) {
1746 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1755 "cannot initialize PMD due to missing run-time dependency on"
1756 " rdma-core libraries (libibverbs, libmlx5)");
1763 * Driver initialization routine.
1765 RTE_INIT(rte_mlx5_pmd_init)
1767 /* Initialize driver log type. */
1768 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1769 if (mlx5_logtype >= 0)
1770 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1772 /* Build the static tables for Verbs conversion. */
1773 mlx5_set_ptype_table();
1774 mlx5_set_cksum_table();
1775 mlx5_set_swp_types_table();
1777 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1778 * huge pages. Calling ibv_fork_init() during init allows
1779 * applications to use fork() safely for purposes other than
1780 * using this PMD, which is not supported in forked processes.
1782 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1783 /* Match the size of Rx completion entry to the size of a cacheline. */
1784 if (RTE_CACHE_LINE_SIZE == 128)
1785 setenv("MLX5_CQE_SIZE", "128", 0);
1787 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1788 * cleanup all the Verbs resources even when the device was removed.
1790 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1791 #ifdef RTE_IBVERBS_LINK_DLOPEN
1792 if (mlx5_glue_init())
1797 /* Glue structure must not contain any NULL pointers. */
1801 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1802 assert(((const void *const *)mlx5_glue)[i]);
1805 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1807 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1808 mlx5_glue->version, MLX5_GLUE_VERSION);
1811 mlx5_glue->fork_init();
1812 rte_pci_register(&mlx5_driver);
1815 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1816 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1817 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");