drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_legacy_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355         [MLX5_IPOOL_MTR_POLICY] = {
 356                 /**
 357                  * The ipool index should grow continually from small to big,
 358                  * for policy idx, so not set grow_trunk to avoid policy index
 359                  * not jump continually.
 360                  */
 361                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 362                 .trunk_size = 64,
 363                 .need_lock = 1,
 364                 .release_mem_en = 1,
 365                 .malloc = mlx5_malloc,
 366                 .free = mlx5_free,
 367                 .type = "mlx5_meter_policy_ipool",
 368         },
 369 };
 370
 371
 372 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 373 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 374
 375 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 376
 377 /**
 378  * Decide whether representor ID is a HPF(host PF) port on BF2.
 379  *
 380  * @param dev
 381  *   Pointer to Ethernet device structure.
 382  *
 383  * @return
 384  *   Non-zero if HPF, otherwise 0.
 385  */
 386 bool
 387 mlx5_is_hpf(struct rte_eth_dev *dev)
 388 {
 389         struct mlx5_priv *priv = dev->data->dev_private;
 390         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 391         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 392
 393         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 394                MLX5_REPRESENTOR_REPR(-1) == repr;
 395 }
 396
 397 /**
 398  * Initialize the ASO aging management structure.
 399  *
 400  * @param[in] sh
 401  *   Pointer to mlx5_dev_ctx_shared object to free
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 int
 407 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 408 {
 409         int err;
 410
 411         if (sh->aso_age_mng)
 412                 return 0;
 413         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 414                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 415         if (!sh->aso_age_mng) {
 416                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 417                 rte_errno = ENOMEM;
 418                 return -ENOMEM;
 419         }
 420         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 421         if (err) {
 422                 mlx5_free(sh->aso_age_mng);
 423                 return -1;
 424         }
 425         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 426         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 427         LIST_INIT(&sh->aso_age_mng->free);
 428         return 0;
 429 }
 430
 431 /**
 432  * Close and release all the resources of the ASO aging management structure.
 433  *
 434  * @param[in] sh
 435  *   Pointer to mlx5_dev_ctx_shared object to free.
 436  */
 437 static void
 438 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 439 {
 440         int i, j;
 441
 442         mlx5_aso_flow_hit_queue_poll_stop(sh);
 443         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 444         if (sh->aso_age_mng->pools) {
 445                 struct mlx5_aso_age_pool *pool;
 446
 447                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 448                         pool = sh->aso_age_mng->pools[i];
 449                         claim_zero(mlx5_devx_cmd_destroy
 450                                                 (pool->flow_hit_aso_obj));
 451                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 452                                 if (pool->actions[j].dr_action)
 453                                         claim_zero
 454                                             (mlx5_flow_os_destroy_flow_action
 455                                               (pool->actions[j].dr_action));
 456                         mlx5_free(pool);
 457                 }
 458                 mlx5_free(sh->aso_age_mng->pools);
 459         }
 460         mlx5_free(sh->aso_age_mng);
 461 }
 462
 463 /**
 464  * Initialize the shared aging list information per port.
 465  *
 466  * @param[in] sh
 467  *   Pointer to mlx5_dev_ctx_shared object.
 468  */
 469 static void
 470 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 471 {
 472         uint32_t i;
 473         struct mlx5_age_info *age_info;
 474
 475         for (i = 0; i < sh->max_port; i++) {
 476                 age_info = &sh->port[i].age_info;
 477                 age_info->flags = 0;
 478                 TAILQ_INIT(&age_info->aged_counters);
 479                 LIST_INIT(&age_info->aged_aso);
 480                 rte_spinlock_init(&age_info->aged_sl);
 481                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 482         }
 483 }
 484
 485 /**
 486  * Initialize the counters management structure.
 487  *
 488  * @param[in] sh
 489  *   Pointer to mlx5_dev_ctx_shared object to free
 490  */
 491 static void
 492 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 493 {
 494         int i;
 495
 496         memset(&sh->cmng, 0, sizeof(sh->cmng));
 497         TAILQ_INIT(&sh->cmng.flow_counters);
 498         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 499         sh->cmng.max_id = -1;
 500         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 501         rte_spinlock_init(&sh->cmng.pool_update_sl);
 502         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 503                 TAILQ_INIT(&sh->cmng.counters[i]);
 504                 rte_spinlock_init(&sh->cmng.csl[i]);
 505         }
 506 }
 507
 508 /**
 509  * Destroy all the resources allocated for a counter memory management.
 510  *
 511  * @param[in] mng
 512  *   Pointer to the memory management structure.
 513  */
 514 static void
 515 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 516 {
 517         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 518
 519         LIST_REMOVE(mng, next);
 520         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 521         claim_zero(mlx5_os_umem_dereg(mng->umem));
 522         mlx5_free(mem);
 523 }
 524
 525 /**
 526  * Close and release all the resources of the counters management.
 527  *
 528  * @param[in] sh
 529  *   Pointer to mlx5_dev_ctx_shared object to free.
 530  */
 531 static void
 532 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 533 {
 534         struct mlx5_counter_stats_mem_mng *mng;
 535         int i, j;
 536         int retries = 1024;
 537
 538         rte_errno = 0;
 539         while (--retries) {
 540                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 541                 if (rte_errno != EINPROGRESS)
 542                         break;
 543                 rte_pause();
 544         }
 545
 546         if (sh->cmng.pools) {
 547                 struct mlx5_flow_counter_pool *pool;
 548                 uint16_t n_valid = sh->cmng.n_valid;
 549                 bool fallback = sh->cmng.counter_fallback;
 550
 551                 for (i = 0; i < n_valid; ++i) {
 552                         pool = sh->cmng.pools[i];
 553                         if (!fallback && pool->min_dcs)
 554                                 claim_zero(mlx5_devx_cmd_destroy
 555                                                                (pool->min_dcs));
 556                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 557                                 struct mlx5_flow_counter *cnt =
 558                                                 MLX5_POOL_GET_CNT(pool, j);
 559
 560                                 if (cnt->action)
 561                                         claim_zero
 562                                          (mlx5_flow_os_destroy_flow_action
 563                                           (cnt->action));
 564                                 if (fallback && MLX5_POOL_GET_CNT
 565                                     (pool, j)->dcs_when_free)
 566                                         claim_zero(mlx5_devx_cmd_destroy
 567                                                    (cnt->dcs_when_free));
 568                         }
 569                         mlx5_free(pool);
 570                 }
 571                 mlx5_free(sh->cmng.pools);
 572         }
 573         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 574         while (mng) {
 575                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 576                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 577         }
 578         memset(&sh->cmng, 0, sizeof(sh->cmng));
 579 }
 580
 581 /**
 582  * Initialize the aso flow meters management structure.
 583  *
 584  * @param[in] sh
 585  *   Pointer to mlx5_dev_ctx_shared object to free
 586  */
 587 int
 588 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 589 {
 590         if (!sh->mtrmng) {
 591                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 592                         sizeof(*sh->mtrmng),
 593                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 594                 if (!sh->mtrmng) {
 595                         DRV_LOG(ERR,
 596                         "meter management allocation was failed.");
 597                         rte_errno = ENOMEM;
 598                         return -ENOMEM;
 599                 }
 600                 if (sh->meter_aso_en) {
 601                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 602                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 603                         sh->mtrmng->policy_idx_tbl =
 604                                 mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 605                 }
 606                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 607         }
 608         return 0;
 609 }
 610
 611 /**
 612  * Close and release all the resources of
 613  * the ASO flow meter management structure.
 614  *
 615  * @param[in] sh
 616  *   Pointer to mlx5_dev_ctx_shared object to free.
 617  */
 618 static void
 619 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 620 {
 621         struct mlx5_aso_mtr_pool *mtr_pool;
 622         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 623         uint32_t idx;
 624 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 625         struct mlx5_aso_mtr *aso_mtr;
 626         int i;
 627 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 628
 629         if (sh->meter_aso_en) {
 630                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 631                 idx = mtrmng->pools_mng.n_valid;
 632                 while (idx--) {
 633                         mtr_pool = mtrmng->pools_mng.pools[idx];
 634 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 635                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 636                                 aso_mtr = &mtr_pool->mtrs[i];
 637                                 if (aso_mtr->fm.meter_action)
 638                                         claim_zero
 639                                         (mlx5_glue->destroy_flow_action
 640                                         (aso_mtr->fm.meter_action));
 641                         }
 642 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 643                         claim_zero(mlx5_devx_cmd_destroy
 644                                                 (mtr_pool->devx_obj));
 645                         mtrmng->pools_mng.n_valid--;
 646                         mlx5_free(mtr_pool);
 647                 }
 648                 mlx5_free(sh->mtrmng->pools_mng.pools);
 649         }
 650         mlx5_free(sh->mtrmng);
 651         sh->mtrmng = NULL;
 652 }
 653
 654 /* Send FLOW_AGED event if needed. */
 655 void
 656 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 657 {
 658         struct mlx5_age_info *age_info;
 659         uint32_t i;
 660
 661         for (i = 0; i < sh->max_port; i++) {
 662                 age_info = &sh->port[i].age_info;
 663                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 664                         continue;
 665                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 666                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 667                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 668                         rte_eth_dev_callback_process
 669                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 670                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 671                 }
 672         }
 673 }
 674
 675 /*
 676  * Initialize the ASO connection tracking structure.
 677  *
 678  * @param[in] sh
 679  *   Pointer to mlx5_dev_ctx_shared object.
 680  *
 681  * @return
 682  *   0 on success, a negative errno value otherwise and rte_errno is set.
 683  */
 684 int
 685 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 686 {
 687         int err;
 688
 689         if (sh->ct_mng)
 690                 return 0;
 691         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 692                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 693         if (!sh->ct_mng) {
 694                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 695                 rte_errno = ENOMEM;
 696                 return -rte_errno;
 697         }
 698         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 699         if (err) {
 700                 mlx5_free(sh->ct_mng);
 701                 /* rte_errno should be extracted from the failure. */
 702                 rte_errno = EINVAL;
 703                 return -rte_errno;
 704         }
 705         rte_spinlock_init(&sh->ct_mng->ct_sl);
 706         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 707         LIST_INIT(&sh->ct_mng->free_cts);
 708         return 0;
 709 }
 710
 711 /**
 712  * Initialize the flow resources' indexed mempool.
 713  *
 714  * @param[in] sh
 715  *   Pointer to mlx5_dev_ctx_shared object.
 716  * @param[in] config
 717  *   Pointer to user dev config.
 718  */
 719 static void
 720 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 721                        const struct mlx5_dev_config *config)
 722 {
 723         uint8_t i;
 724         struct mlx5_indexed_pool_config cfg;
 725
 726         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 727                 cfg = mlx5_ipool_cfg[i];
 728                 switch (i) {
 729                 default:
 730                         break;
 731                 /*
 732                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 733                  * according to PCI function flow configuration.
 734                  */
 735                 case MLX5_IPOOL_MLX5_FLOW:
 736                         cfg.size = config->dv_flow_en ?
 737                                 sizeof(struct mlx5_flow_handle) :
 738                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 739                         break;
 740                 }
 741                 if (config->reclaim_mode)
 742                         cfg.release_mem_en = 1;
 743                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 744         }
 745 }
 746
 747 /**
 748  * Release the flow resources' indexed mempool.
 749  *
 750  * @param[in] sh
 751  *   Pointer to mlx5_dev_ctx_shared object.
 752  */
 753 static void
 754 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 755 {
 756         uint8_t i;
 757
 758         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 759                 mlx5_ipool_destroy(sh->ipool[i]);
 760 }
 761
 762 /*
 763  * Check if dynamic flex parser for eCPRI already exists.
 764  *
 765  * @param dev
 766  *   Pointer to Ethernet device structure.
 767  *
 768  * @return
 769  *   true on exists, false on not.
 770  */
 771 bool
 772 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 773 {
 774         struct mlx5_priv *priv = dev->data->dev_private;
 775         struct mlx5_flex_parser_profiles *prf =
 776                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 777
 778         return !!prf->obj;
 779 }
 780
 781 /*
 782  * Allocation of a flex parser for eCPRI. Once created, this parser related
 783  * resources will be held until the device is closed.
 784  *
 785  * @param dev
 786  *   Pointer to Ethernet device structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 int
 792 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 793 {
 794         struct mlx5_priv *priv = dev->data->dev_private;
 795         struct mlx5_flex_parser_profiles *prf =
 796                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 797         struct mlx5_devx_graph_node_attr node = {
 798                 .modify_field_select = 0,
 799         };
 800         uint32_t ids[8];
 801         int ret;
 802
 803         if (!priv->config.hca_attr.parse_graph_flex_node) {
 804                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 805                         "for device %s.", priv->dev_data->name);
 806                 return -ENOTSUP;
 807         }
 808         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 809         /* 8 bytes now: 4B common header + 4B message body header. */
 810         node.header_length_base_value = 0x8;
 811         /* After MAC layer: Ether / VLAN. */
 812         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 813         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 814         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 815         /* Sample #0: type in common header. */
 816         node.sample[0].flow_match_sample_en = 1;
 817         /* Fixed offset. */
 818         node.sample[0].flow_match_sample_offset_mode = 0x0;
 819         /* Only the 2nd byte will be used. */
 820         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 821         /* Sample #1: message payload. */
 822         node.sample[1].flow_match_sample_en = 1;
 823         /* Fixed offset. */
 824         node.sample[1].flow_match_sample_offset_mode = 0x0;
 825         /*
 826          * Only the first two bytes will be used right now, and its offset will
 827          * start after the common header that with the length of a DW(u32).
 828          */
 829         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 830         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 831         if (!prf->obj) {
 832                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 833                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 834         }
 835         prf->num = 2;
 836         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 837         if (ret) {
 838                 DRV_LOG(ERR, "Failed to query sample IDs.");
 839                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 840         }
 841         prf->offset[0] = 0x0;
 842         prf->offset[1] = sizeof(uint32_t);
 843         prf->ids[0] = ids[0];
 844         prf->ids[1] = ids[1];
 845         return 0;
 846 }
 847
 848 /*
 849  * Destroy the flex parser node, including the parser itself, input / output
 850  * arcs and DW samples. Resources could be reused then.
 851  *
 852  * @param dev
 853  *   Pointer to Ethernet device structure.
 854  */
 855 static void
 856 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 857 {
 858         struct mlx5_priv *priv = dev->data->dev_private;
 859         struct mlx5_flex_parser_profiles *prf =
 860                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 861
 862         if (prf->obj)
 863                 mlx5_devx_cmd_destroy(prf->obj);
 864         prf->obj = NULL;
 865 }
 866
 867 /*
 868  * Allocate Rx and Tx UARs in robust fashion.
 869  * This routine handles the following UAR allocation issues:
 870  *
 871  *  - tries to allocate the UAR with the most appropriate memory
 872  *    mapping type from the ones supported by the host
 873  *
 874  *  - tries to allocate the UAR with non-NULL base address
 875  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 876  *    UAR base address if UAR was not the first object in the UAR page.
 877  *    It caused the PMD failure and we should try to get another UAR
 878  *    till we get the first one with non-NULL base address returned.
 879  */
 880 static int
 881 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 882                      const struct mlx5_dev_config *config)
 883 {
 884         uint32_t uar_mapping, retry;
 885         int err = 0;
 886         void *base_addr;
 887
 888         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 889 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 890                 /* Control the mapping type according to the settings. */
 891                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 892                               MLX5DV_UAR_ALLOC_TYPE_NC :
 893                               MLX5DV_UAR_ALLOC_TYPE_BF;
 894 #else
 895                 RTE_SET_USED(config);
 896                 /*
 897                  * It seems we have no way to control the memory mapping type
 898                  * for the UAR, the default "Write-Combining" type is supposed.
 899                  * The UAR initialization on queue creation queries the
 900                  * actual mapping type done by Verbs/kernel and setups the
 901                  * PMD datapath accordingly.
 902                  */
 903                 uar_mapping = 0;
 904 #endif
 905                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 906 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 907                 if (!sh->tx_uar &&
 908                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 909                         if (config->dbnc == MLX5_TXDB_CACHED ||
 910                             config->dbnc == MLX5_TXDB_HEURISTIC)
 911                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 912                                                  "is not supported by DevX");
 913                         /*
 914                          * In some environments like virtual machine
 915                          * the Write Combining mapped might be not supported
 916                          * and UAR allocation fails. We try "Non-Cached"
 917                          * mapping for the case. The tx_burst routines take
 918                          * the UAR mapping type into account on UAR setup
 919                          * on queue creation.
 920                          */
 921                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 922                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 923                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 924                                                         (sh->ctx, uar_mapping);
 925                 } else if (!sh->tx_uar &&
 926                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 927                         if (config->dbnc == MLX5_TXDB_NCACHED)
 928                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 929                                                  "is not supported by DevX");
 930                         /*
 931                          * If Verbs/kernel does not support "Non-Cached"
 932                          * try the "Write-Combining".
 933                          */
 934                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 935                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 936                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 937                                                         (sh->ctx, uar_mapping);
 938                 }
 939 #endif
 940                 if (!sh->tx_uar) {
 941                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 942                         err = ENOMEM;
 943                         goto exit;
 944                 }
 945                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 946                 if (base_addr)
 947                         break;
 948                 /*
 949                  * The UARs are allocated by rdma_core within the
 950                  * IB device context, on context closure all UARs
 951                  * will be freed, should be no memory/object leakage.
 952                  */
 953                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 954                 sh->tx_uar = NULL;
 955         }
 956         /* Check whether we finally succeeded with valid UAR allocation. */
 957         if (!sh->tx_uar) {
 958                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 959                 err = ENOMEM;
 960                 goto exit;
 961         }
 962         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 963                 uar_mapping = 0;
 964                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 965                                                         (sh->ctx, uar_mapping);
 966 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 967                 if (!sh->devx_rx_uar &&
 968                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 969                         /*
 970                          * Rx UAR is used to control interrupts only,
 971                          * should be no datapath noticeable impact,
 972                          * can try "Non-Cached" mapping safely.
 973                          */
 974                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 975                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 976                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 977                                                         (sh->ctx, uar_mapping);
 978                 }
 979 #endif
 980                 if (!sh->devx_rx_uar) {
 981                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 982                         err = ENOMEM;
 983                         goto exit;
 984                 }
 985                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 986                 if (base_addr)
 987                         break;
 988                 /*
 989                  * The UARs are allocated by rdma_core within the
 990                  * IB device context, on context closure all UARs
 991                  * will be freed, should be no memory/object leakage.
 992                  */
 993                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 994                 sh->devx_rx_uar = NULL;
 995         }
 996         /* Check whether we finally succeeded with valid UAR allocation. */
 997         if (!sh->devx_rx_uar) {
 998                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 999                 err = ENOMEM;
1000         }
1001 exit:
1002         return err;
1003 }
1004
1005 /**
1006  * Allocate shared device context. If there is multiport device the
1007  * master and representors will share this context, if there is single
1008  * port dedicated device, the context will be used by only given
1009  * port due to unification.
1010  *
1011  * Routine first searches the context for the specified device name,
1012  * if found the shared context assumed and reference counter is incremented.
1013  * If no context found the new one is created and initialized with specified
1014  * device context and parameters.
1015  *
1016  * @param[in] spawn
1017  *   Pointer to the device attributes (name, port, etc).
1018  * @param[in] config
1019  *   Pointer to device configuration structure.
1020  *
1021  * @return
1022  *   Pointer to mlx5_dev_ctx_shared object on success,
1023  *   otherwise NULL and rte_errno is set.
1024  */
1025 struct mlx5_dev_ctx_shared *
1026 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1027                            const struct mlx5_dev_config *config)
1028 {
1029         struct mlx5_dev_ctx_shared *sh;
1030         int err = 0;
1031         uint32_t i;
1032         struct mlx5_devx_tis_attr tis_attr = { 0 };
1033
1034         MLX5_ASSERT(spawn);
1035         /* Secondary process should not create the shared context. */
1036         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1037         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1038         /* Search for IB context by device name. */
1039         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1040                 if (!strcmp(sh->ibdev_name,
1041                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1042                         sh->refcnt++;
1043                         goto exit;
1044                 }
1045         }
1046         /* No device found, we have to create new shared context. */
1047         MLX5_ASSERT(spawn->max_port);
1048         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1049                          sizeof(struct mlx5_dev_ctx_shared) +
1050                          spawn->max_port *
1051                          sizeof(struct mlx5_dev_shared_port),
1052                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1053         if (!sh) {
1054                 DRV_LOG(ERR, "shared context allocation failure");
1055                 rte_errno  = ENOMEM;
1056                 goto exit;
1057         }
1058         if (spawn->bond_info)
1059                 sh->bond = *spawn->bond_info;
1060         err = mlx5_os_open_device(spawn, config, sh);
1061         if (!sh->ctx)
1062                 goto error;
1063         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1064         if (err) {
1065                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1066                 goto error;
1067         }
1068         sh->refcnt = 1;
1069         sh->max_port = spawn->max_port;
1070         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1071                 sizeof(sh->ibdev_name) - 1);
1072         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1073                 sizeof(sh->ibdev_path) - 1);
1074         /*
1075          * Setting port_id to max unallowed value means
1076          * there is no interrupt subhandler installed for
1077          * the given port index i.
1078          */
1079         for (i = 0; i < sh->max_port; i++) {
1080                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1081                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1082         }
1083         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1084         if (sh->pd == NULL) {
1085                 DRV_LOG(ERR, "PD allocation failure");
1086                 err = ENOMEM;
1087                 goto error;
1088         }
1089         if (sh->devx) {
1090                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1091                 if (err) {
1092                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1093                         goto error;
1094                 }
1095                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1096                 if (!sh->td) {
1097                         DRV_LOG(ERR, "TD allocation failure");
1098                         err = ENOMEM;
1099                         goto error;
1100                 }
1101                 tis_attr.transport_domain = sh->td->id;
1102                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1103                 if (!sh->tis) {
1104                         DRV_LOG(ERR, "TIS allocation failure");
1105                         err = ENOMEM;
1106                         goto error;
1107                 }
1108                 err = mlx5_alloc_rxtx_uars(sh, config);
1109                 if (err)
1110                         goto error;
1111                 MLX5_ASSERT(sh->tx_uar);
1112                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1113
1114                 MLX5_ASSERT(sh->devx_rx_uar);
1115                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1116         }
1117 #ifndef RTE_ARCH_64
1118         /* Initialize UAR access locks for 32bit implementations. */
1119         rte_spinlock_init(&sh->uar_lock_cq);
1120         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1121                 rte_spinlock_init(&sh->uar_lock[i]);
1122 #endif
1123         /*
1124          * Once the device is added to the list of memory event
1125          * callback, its global MR cache table cannot be expanded
1126          * on the fly because of deadlock. If it overflows, lookup
1127          * should be done by searching MR list linearly, which is slow.
1128          *
1129          * At this point the device is not added to the memory
1130          * event list yet, context is just being created.
1131          */
1132         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1133                                  MLX5_MR_BTREE_CACHE_N * 2,
1134                                  spawn->pci_dev->device.numa_node);
1135         if (err) {
1136                 err = rte_errno;
1137                 goto error;
1138         }
1139         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1140                               &sh->share_cache.dereg_mr_cb);
1141         mlx5_os_dev_shared_handler_install(sh);
1142         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1143         if (!sh->cnt_id_tbl) {
1144                 err = rte_errno;
1145                 goto error;
1146         }
1147         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1148                 err = mlx5_flow_os_init_workspace_once();
1149                 if (err)
1150                         goto error;
1151         }
1152         mlx5_flow_aging_init(sh);
1153         mlx5_flow_counters_mng_init(sh);
1154         mlx5_flow_ipool_create(sh, config);
1155         /* Add device to memory callback list. */
1156         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1157         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1158                          sh, mem_event_cb);
1159         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1160         /* Add context to the global device list. */
1161         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1162         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1163 exit:
1164         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1165         return sh;
1166 error:
1167         pthread_mutex_destroy(&sh->txpp.mutex);
1168         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1169         MLX5_ASSERT(sh);
1170         if (sh->cnt_id_tbl)
1171                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1172         if (sh->tis)
1173                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1174         if (sh->td)
1175                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1176         if (sh->devx_rx_uar)
1177                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1178         if (sh->tx_uar)
1179                 mlx5_glue->devx_free_uar(sh->tx_uar);
1180         if (sh->pd)
1181                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1182         if (sh->ctx)
1183                 claim_zero(mlx5_glue->close_device(sh->ctx));
1184         mlx5_free(sh);
1185         MLX5_ASSERT(err > 0);
1186         rte_errno = err;
1187         return NULL;
1188 }
1189
1190 /**
1191  * Free shared IB device context. Decrement counter and if zero free
1192  * all allocated resources and close handles.
1193  *
1194  * @param[in] sh
1195  *   Pointer to mlx5_dev_ctx_shared object to free
1196  */
1197 void
1198 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1199 {
1200         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1201 #ifdef RTE_LIBRTE_MLX5_DEBUG
1202         /* Check the object presence in the list. */
1203         struct mlx5_dev_ctx_shared *lctx;
1204
1205         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1206                 if (lctx == sh)
1207                         break;
1208         MLX5_ASSERT(lctx);
1209         if (lctx != sh) {
1210                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1211                 goto exit;
1212         }
1213 #endif
1214         MLX5_ASSERT(sh);
1215         MLX5_ASSERT(sh->refcnt);
1216         /* Secondary process should not free the shared context. */
1217         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1218         if (--sh->refcnt)
1219                 goto exit;
1220         /* Remove from memory callback device list. */
1221         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1222         LIST_REMOVE(sh, mem_event_cb);
1223         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1224         /* Release created Memory Regions. */
1225         mlx5_mr_release_cache(&sh->share_cache);
1226         /* Remove context from the global device list. */
1227         LIST_REMOVE(sh, next);
1228         /* Release flow workspaces objects on the last device. */
1229         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1230                 mlx5_flow_os_release_workspace();
1231         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1232         /*
1233          *  Ensure there is no async event handler installed.
1234          *  Only primary process handles async device events.
1235          **/
1236         mlx5_flow_counters_mng_close(sh);
1237         if (sh->aso_age_mng) {
1238                 mlx5_flow_aso_age_mng_close(sh);
1239                 sh->aso_age_mng = NULL;
1240         }
1241         if (sh->mtrmng)
1242                 mlx5_aso_flow_mtrs_mng_close(sh);
1243         mlx5_flow_ipool_destroy(sh);
1244         mlx5_os_dev_shared_handler_uninstall(sh);
1245         if (sh->cnt_id_tbl) {
1246                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1247                 sh->cnt_id_tbl = NULL;
1248         }
1249         if (sh->tx_uar) {
1250                 mlx5_glue->devx_free_uar(sh->tx_uar);
1251                 sh->tx_uar = NULL;
1252         }
1253         if (sh->pd)
1254                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1255         if (sh->tis)
1256                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1257         if (sh->td)
1258                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1259         if (sh->devx_rx_uar)
1260                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1261         if (sh->ctx)
1262                 claim_zero(mlx5_glue->close_device(sh->ctx));
1263         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1264         pthread_mutex_destroy(&sh->txpp.mutex);
1265         mlx5_free(sh);
1266         return;
1267 exit:
1268         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1269 }
1270
1271 /**
1272  * Destroy table hash list.
1273  *
1274  * @param[in] priv
1275  *   Pointer to the private device data structure.
1276  */
1277 void
1278 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1279 {
1280         struct mlx5_dev_ctx_shared *sh = priv->sh;
1281
1282         if (!sh->flow_tbls)
1283                 return;
1284         mlx5_hlist_destroy(sh->flow_tbls);
1285 }
1286
1287 /**
1288  * Initialize flow table hash list and create the root tables entry
1289  * for each domain.
1290  *
1291  * @param[in] priv
1292  *   Pointer to the private device data structure.
1293  *
1294  * @return
1295  *   Zero on success, positive error code otherwise.
1296  */
1297 int
1298 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1299 {
1300         int err = 0;
1301         /* Tables are only used in DV and DR modes. */
1302 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1303         struct mlx5_dev_ctx_shared *sh = priv->sh;
1304         char s[MLX5_HLIST_NAMESIZE];
1305
1306         MLX5_ASSERT(sh);
1307         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1308         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1309                                           0, 0, flow_dv_tbl_create_cb,
1310                                           flow_dv_tbl_match_cb,
1311                                           flow_dv_tbl_remove_cb);
1312         if (!sh->flow_tbls) {
1313                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1314                 err = ENOMEM;
1315                 return err;
1316         }
1317         sh->flow_tbls->ctx = sh;
1318 #ifndef HAVE_MLX5DV_DR
1319         struct rte_flow_error error;
1320         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1321
1322         /*
1323          * In case we have not DR support, the zero tables should be created
1324          * because DV expect to see them even if they cannot be created by
1325          * RDMA-CORE.
1326          */
1327         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1328                 NULL, 0, 1, 0, &error) ||
1329             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1330                 NULL, 0, 1, 0, &error) ||
1331             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1332                 NULL, 0, 1, 0, &error)) {
1333                 err = ENOMEM;
1334                 goto error;
1335         }
1336         return err;
1337 error:
1338         mlx5_free_table_hash_list(priv);
1339 #endif /* HAVE_MLX5DV_DR */
1340 #endif
1341         return err;
1342 }
1343
1344 /**
1345  * Retrieve integer value from environment variable.
1346  *
1347  * @param[in] name
1348  *   Environment variable name.
1349  *
1350  * @return
1351  *   Integer value, 0 if the variable is not set.
1352  */
1353 int
1354 mlx5_getenv_int(const char *name)
1355 {
1356         const char *val = getenv(name);
1357
1358         if (val == NULL)
1359                 return 0;
1360         return atoi(val);
1361 }
1362
1363 /**
1364  * DPDK callback to add udp tunnel port
1365  *
1366  * @param[in] dev
1367  *   A pointer to eth_dev
1368  * @param[in] udp_tunnel
1369  *   A pointer to udp tunnel
1370  *
1371  * @return
1372  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1373  */
1374 int
1375 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1376                          struct rte_eth_udp_tunnel *udp_tunnel)
1377 {
1378         MLX5_ASSERT(udp_tunnel != NULL);
1379         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1380             udp_tunnel->udp_port == 4789)
1381                 return 0;
1382         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1383             udp_tunnel->udp_port == 4790)
1384                 return 0;
1385         return -ENOTSUP;
1386 }
1387
1388 /**
1389  * Initialize process private data structure.
1390  *
1391  * @param dev
1392  *   Pointer to Ethernet device structure.
1393  *
1394  * @return
1395  *   0 on success, a negative errno value otherwise and rte_errno is set.
1396  */
1397 int
1398 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1399 {
1400         struct mlx5_priv *priv = dev->data->dev_private;
1401         struct mlx5_proc_priv *ppriv;
1402         size_t ppriv_size;
1403
1404         /*
1405          * UAR register table follows the process private structure. BlueFlame
1406          * registers for Tx queues are stored in the table.
1407          */
1408         ppriv_size =
1409                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1410         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1411                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1412         if (!ppriv) {
1413                 rte_errno = ENOMEM;
1414                 return -rte_errno;
1415         }
1416         ppriv->uar_table_sz = priv->txqs_n;
1417         dev->process_private = ppriv;
1418         return 0;
1419 }
1420
1421 /**
1422  * Un-initialize process private data structure.
1423  *
1424  * @param dev
1425  *   Pointer to Ethernet device structure.
1426  */
1427 void
1428 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1429 {
1430         if (!dev->process_private)
1431                 return;
1432         mlx5_free(dev->process_private);
1433         dev->process_private = NULL;
1434 }
1435
1436 /**
1437  * DPDK callback to close the device.
1438  *
1439  * Destroy all queues and objects, free memory.
1440  *
1441  * @param dev
1442  *   Pointer to Ethernet device structure.
1443  */
1444 int
1445 mlx5_dev_close(struct rte_eth_dev *dev)
1446 {
1447         struct mlx5_priv *priv = dev->data->dev_private;
1448         unsigned int i;
1449         int ret;
1450
1451         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1452                 /* Check if process_private released. */
1453                 if (!dev->process_private)
1454                         return 0;
1455                 mlx5_tx_uar_uninit_secondary(dev);
1456                 mlx5_proc_priv_uninit(dev);
1457                 rte_eth_dev_release_port(dev);
1458                 return 0;
1459         }
1460         if (!priv->sh)
1461                 return 0;
1462         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1463                 dev->data->port_id,
1464                 ((priv->sh->ctx != NULL) ?
1465                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1466         /*
1467          * If default mreg copy action is removed at the stop stage,
1468          * the search will return none and nothing will be done anymore.
1469          */
1470         mlx5_flow_stop_default(dev);
1471         mlx5_traffic_disable(dev);
1472         /*
1473          * If all the flows are already flushed in the device stop stage,
1474          * then this will return directly without any action.
1475          */
1476         mlx5_flow_list_flush(dev, &priv->flows, true);
1477         mlx5_action_handle_flush(dev);
1478         mlx5_flow_meter_flush(dev, NULL);
1479         /* Prevent crashes when queues are still in use. */
1480         dev->rx_pkt_burst = removed_rx_burst;
1481         dev->tx_pkt_burst = removed_tx_burst;
1482         rte_wmb();
1483         /* Disable datapath on secondary process. */
1484         mlx5_mp_os_req_stop_rxtx(dev);
1485         /* Free the eCPRI flex parser resource. */
1486         mlx5_flex_parser_ecpri_release(dev);
1487         if (priv->rxqs != NULL) {
1488                 /* XXX race condition if mlx5_rx_burst() is still running. */
1489                 rte_delay_us_sleep(1000);
1490                 for (i = 0; (i != priv->rxqs_n); ++i)
1491                         mlx5_rxq_release(dev, i);
1492                 priv->rxqs_n = 0;
1493                 priv->rxqs = NULL;
1494         }
1495         if (priv->txqs != NULL) {
1496                 /* XXX race condition if mlx5_tx_burst() is still running. */
1497                 rte_delay_us_sleep(1000);
1498                 for (i = 0; (i != priv->txqs_n); ++i)
1499                         mlx5_txq_release(dev, i);
1500                 priv->txqs_n = 0;
1501                 priv->txqs = NULL;
1502         }
1503         mlx5_proc_priv_uninit(dev);
1504         if (priv->q_counters) {
1505                 mlx5_devx_cmd_destroy(priv->q_counters);
1506                 priv->q_counters = NULL;
1507         }
1508         if (priv->drop_queue.hrxq)
1509                 mlx5_drop_action_destroy(dev);
1510         if (priv->mreg_cp_tbl)
1511                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1512         mlx5_mprq_free_mp(dev);
1513         mlx5_os_free_shared_dr(priv);
1514         if (priv->rss_conf.rss_key != NULL)
1515                 mlx5_free(priv->rss_conf.rss_key);
1516         if (priv->reta_idx != NULL)
1517                 mlx5_free(priv->reta_idx);
1518         if (priv->config.vf)
1519                 mlx5_os_mac_addr_flush(dev);
1520         if (priv->nl_socket_route >= 0)
1521                 close(priv->nl_socket_route);
1522         if (priv->nl_socket_rdma >= 0)
1523                 close(priv->nl_socket_rdma);
1524         if (priv->vmwa_context)
1525                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1526         ret = mlx5_hrxq_verify(dev);
1527         if (ret)
1528                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1529                         dev->data->port_id);
1530         ret = mlx5_ind_table_obj_verify(dev);
1531         if (ret)
1532                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1533                         dev->data->port_id);
1534         ret = mlx5_rxq_obj_verify(dev);
1535         if (ret)
1536                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1537                         dev->data->port_id);
1538         ret = mlx5_rxq_verify(dev);
1539         if (ret)
1540                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1541                         dev->data->port_id);
1542         ret = mlx5_txq_obj_verify(dev);
1543         if (ret)
1544                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1545                         dev->data->port_id);
1546         ret = mlx5_txq_verify(dev);
1547         if (ret)
1548                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1549                         dev->data->port_id);
1550         ret = mlx5_flow_verify(dev);
1551         if (ret)
1552                 DRV_LOG(WARNING, "port %u some flows still remain",
1553                         dev->data->port_id);
1554         mlx5_cache_list_destroy(&priv->hrxqs);
1555         /*
1556          * Free the shared context in last turn, because the cleanup
1557          * routines above may use some shared fields, like
1558          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1559          * ifindex if Netlink fails.
1560          */
1561         mlx5_free_shared_dev_ctx(priv->sh);
1562         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1563                 unsigned int c = 0;
1564                 uint16_t port_id;
1565
1566                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1567                         struct mlx5_priv *opriv =
1568                                 rte_eth_devices[port_id].data->dev_private;
1569
1570                         if (!opriv ||
1571                             opriv->domain_id != priv->domain_id ||
1572                             &rte_eth_devices[port_id] == dev)
1573                                 continue;
1574                         ++c;
1575                         break;
1576                 }
1577                 if (!c)
1578                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1579         }
1580         memset(priv, 0, sizeof(*priv));
1581         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1582         /*
1583          * Reset mac_addrs to NULL such that it is not freed as part of
1584          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1585          * it is freed when dev_private is freed.
1586          */
1587         dev->data->mac_addrs = NULL;
1588         return 0;
1589 }
1590
1591 const struct eth_dev_ops mlx5_dev_ops = {
1592         .dev_configure = mlx5_dev_configure,
1593         .dev_start = mlx5_dev_start,
1594         .dev_stop = mlx5_dev_stop,
1595         .dev_set_link_down = mlx5_set_link_down,
1596         .dev_set_link_up = mlx5_set_link_up,
1597         .dev_close = mlx5_dev_close,
1598         .promiscuous_enable = mlx5_promiscuous_enable,
1599         .promiscuous_disable = mlx5_promiscuous_disable,
1600         .allmulticast_enable = mlx5_allmulticast_enable,
1601         .allmulticast_disable = mlx5_allmulticast_disable,
1602         .link_update = mlx5_link_update,
1603         .stats_get = mlx5_stats_get,
1604         .stats_reset = mlx5_stats_reset,
1605         .xstats_get = mlx5_xstats_get,
1606         .xstats_reset = mlx5_xstats_reset,
1607         .xstats_get_names = mlx5_xstats_get_names,
1608         .fw_version_get = mlx5_fw_version_get,
1609         .dev_infos_get = mlx5_dev_infos_get,
1610         .representor_info_get = mlx5_representor_info_get,
1611         .read_clock = mlx5_txpp_read_clock,
1612         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1613         .vlan_filter_set = mlx5_vlan_filter_set,
1614         .rx_queue_setup = mlx5_rx_queue_setup,
1615         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1616         .tx_queue_setup = mlx5_tx_queue_setup,
1617         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1618         .rx_queue_release = mlx5_rx_queue_release,
1619         .tx_queue_release = mlx5_tx_queue_release,
1620         .rx_queue_start = mlx5_rx_queue_start,
1621         .rx_queue_stop = mlx5_rx_queue_stop,
1622         .tx_queue_start = mlx5_tx_queue_start,
1623         .tx_queue_stop = mlx5_tx_queue_stop,
1624         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1625         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1626         .mac_addr_remove = mlx5_mac_addr_remove,
1627         .mac_addr_add = mlx5_mac_addr_add,
1628         .mac_addr_set = mlx5_mac_addr_set,
1629         .set_mc_addr_list = mlx5_set_mc_addr_list,
1630         .mtu_set = mlx5_dev_set_mtu,
1631         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1632         .vlan_offload_set = mlx5_vlan_offload_set,
1633         .reta_update = mlx5_dev_rss_reta_update,
1634         .reta_query = mlx5_dev_rss_reta_query,
1635         .rss_hash_update = mlx5_rss_hash_update,
1636         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1637         .flow_ops_get = mlx5_flow_ops_get,
1638         .rxq_info_get = mlx5_rxq_info_get,
1639         .txq_info_get = mlx5_txq_info_get,
1640         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1641         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1642         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1643         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1644         .is_removed = mlx5_is_removed,
1645         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1646         .get_module_info = mlx5_get_module_info,
1647         .get_module_eeprom = mlx5_get_module_eeprom,
1648         .hairpin_cap_get = mlx5_hairpin_cap_get,
1649         .mtr_ops_get = mlx5_flow_meter_ops_get,
1650         .hairpin_bind = mlx5_hairpin_bind,
1651         .hairpin_unbind = mlx5_hairpin_unbind,
1652         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1653         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1654         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1655         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1656         .get_monitor_addr = mlx5_get_monitor_addr,
1657 };
1658
1659 /* Available operations from secondary process. */
1660 const struct eth_dev_ops mlx5_dev_sec_ops = {
1661         .stats_get = mlx5_stats_get,
1662         .stats_reset = mlx5_stats_reset,
1663         .xstats_get = mlx5_xstats_get,
1664         .xstats_reset = mlx5_xstats_reset,
1665         .xstats_get_names = mlx5_xstats_get_names,
1666         .fw_version_get = mlx5_fw_version_get,
1667         .dev_infos_get = mlx5_dev_infos_get,
1668         .read_clock = mlx5_txpp_read_clock,
1669         .rx_queue_start = mlx5_rx_queue_start,
1670         .rx_queue_stop = mlx5_rx_queue_stop,
1671         .tx_queue_start = mlx5_tx_queue_start,
1672         .tx_queue_stop = mlx5_tx_queue_stop,
1673         .rxq_info_get = mlx5_rxq_info_get,
1674         .txq_info_get = mlx5_txq_info_get,
1675         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1676         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1677         .get_module_info = mlx5_get_module_info,
1678         .get_module_eeprom = mlx5_get_module_eeprom,
1679 };
1680
1681 /* Available operations in flow isolated mode. */
1682 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1683         .dev_configure = mlx5_dev_configure,
1684         .dev_start = mlx5_dev_start,
1685         .dev_stop = mlx5_dev_stop,
1686         .dev_set_link_down = mlx5_set_link_down,
1687         .dev_set_link_up = mlx5_set_link_up,
1688         .dev_close = mlx5_dev_close,
1689         .promiscuous_enable = mlx5_promiscuous_enable,
1690         .promiscuous_disable = mlx5_promiscuous_disable,
1691         .allmulticast_enable = mlx5_allmulticast_enable,
1692         .allmulticast_disable = mlx5_allmulticast_disable,
1693         .link_update = mlx5_link_update,
1694         .stats_get = mlx5_stats_get,
1695         .stats_reset = mlx5_stats_reset,
1696         .xstats_get = mlx5_xstats_get,
1697         .xstats_reset = mlx5_xstats_reset,
1698         .xstats_get_names = mlx5_xstats_get_names,
1699         .fw_version_get = mlx5_fw_version_get,
1700         .dev_infos_get = mlx5_dev_infos_get,
1701         .read_clock = mlx5_txpp_read_clock,
1702         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1703         .vlan_filter_set = mlx5_vlan_filter_set,
1704         .rx_queue_setup = mlx5_rx_queue_setup,
1705         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1706         .tx_queue_setup = mlx5_tx_queue_setup,
1707         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1708         .rx_queue_release = mlx5_rx_queue_release,
1709         .tx_queue_release = mlx5_tx_queue_release,
1710         .rx_queue_start = mlx5_rx_queue_start,
1711         .rx_queue_stop = mlx5_rx_queue_stop,
1712         .tx_queue_start = mlx5_tx_queue_start,
1713         .tx_queue_stop = mlx5_tx_queue_stop,
1714         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1715         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1716         .mac_addr_remove = mlx5_mac_addr_remove,
1717         .mac_addr_add = mlx5_mac_addr_add,
1718         .mac_addr_set = mlx5_mac_addr_set,
1719         .set_mc_addr_list = mlx5_set_mc_addr_list,
1720         .mtu_set = mlx5_dev_set_mtu,
1721         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1722         .vlan_offload_set = mlx5_vlan_offload_set,
1723         .flow_ops_get = mlx5_flow_ops_get,
1724         .rxq_info_get = mlx5_rxq_info_get,
1725         .txq_info_get = mlx5_txq_info_get,
1726         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1727         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1728         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1729         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1730         .is_removed = mlx5_is_removed,
1731         .get_module_info = mlx5_get_module_info,
1732         .get_module_eeprom = mlx5_get_module_eeprom,
1733         .hairpin_cap_get = mlx5_hairpin_cap_get,
1734         .mtr_ops_get = mlx5_flow_meter_ops_get,
1735         .hairpin_bind = mlx5_hairpin_bind,
1736         .hairpin_unbind = mlx5_hairpin_unbind,
1737         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1738         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1739         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1740         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1741         .get_monitor_addr = mlx5_get_monitor_addr,
1742 };
1743
1744 /**
1745  * Verify and store value for device argument.
1746  *
1747  * @param[in] key
1748  *   Key argument to verify.
1749  * @param[in] val
1750  *   Value associated with key.
1751  * @param opaque
1752  *   User data.
1753  *
1754  * @return
1755  *   0 on success, a negative errno value otherwise and rte_errno is set.
1756  */
1757 static int
1758 mlx5_args_check(const char *key, const char *val, void *opaque)
1759 {
1760         struct mlx5_dev_config *config = opaque;
1761         unsigned long mod;
1762         signed long tmp;
1763
1764         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1765         if (!strcmp(MLX5_REPRESENTOR, key))
1766                 return 0;
1767         errno = 0;
1768         tmp = strtol(val, NULL, 0);
1769         if (errno) {
1770                 rte_errno = errno;
1771                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1772                 return -rte_errno;
1773         }
1774         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1775                 /* Negative values are acceptable for some keys only. */
1776                 rte_errno = EINVAL;
1777                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1778                 return -rte_errno;
1779         }
1780         mod = tmp >= 0 ? tmp : -tmp;
1781         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1782                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1783                         DRV_LOG(ERR, "invalid CQE compression "
1784                                      "format parameter");
1785                         rte_errno = EINVAL;
1786                         return -rte_errno;
1787                 }
1788                 config->cqe_comp = !!tmp;
1789                 config->cqe_comp_fmt = tmp;
1790         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1791                 config->hw_padding = !!tmp;
1792         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1793                 config->mprq.enabled = !!tmp;
1794         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1795                 config->mprq.stride_num_n = tmp;
1796         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1797                 config->mprq.stride_size_n = tmp;
1798         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1799                 config->mprq.max_memcpy_len = tmp;
1800         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1801                 config->mprq.min_rxqs_num = tmp;
1802         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1803                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1804                                  " converted to txq_inline_max", key);
1805                 config->txq_inline_max = tmp;
1806         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1807                 config->txq_inline_max = tmp;
1808         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1809                 config->txq_inline_min = tmp;
1810         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1811                 config->txq_inline_mpw = tmp;
1812         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1813                 config->txqs_inline = tmp;
1814         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1815                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1816         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1817                 config->mps = !!tmp;
1818         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1819                 if (tmp != MLX5_TXDB_CACHED &&
1820                     tmp != MLX5_TXDB_NCACHED &&
1821                     tmp != MLX5_TXDB_HEURISTIC) {
1822                         DRV_LOG(ERR, "invalid Tx doorbell "
1823                                      "mapping parameter");
1824                         rte_errno = EINVAL;
1825                         return -rte_errno;
1826                 }
1827                 config->dbnc = tmp;
1828         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1829                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1830         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1831                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1832                                  " converted to txq_inline_mpw", key);
1833                 config->txq_inline_mpw = tmp;
1834         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1835                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1836         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1837                 if (!mod) {
1838                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1839                         rte_errno = EINVAL;
1840                         return -rte_errno;
1841                 }
1842                 config->tx_pp = tmp;
1843         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1844                 config->tx_skew = tmp;
1845         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1846                 config->rx_vec_en = !!tmp;
1847         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1848                 config->l3_vxlan_en = !!tmp;
1849         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1850                 config->vf_nl_en = !!tmp;
1851         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1852                 config->dv_esw_en = !!tmp;
1853         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1854                 config->dv_flow_en = !!tmp;
1855         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1856                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1857                     tmp != MLX5_XMETA_MODE_META16 &&
1858                     tmp != MLX5_XMETA_MODE_META32 &&
1859                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1860                         DRV_LOG(ERR, "invalid extensive "
1861                                      "metadata parameter");
1862                         rte_errno = EINVAL;
1863                         return -rte_errno;
1864                 }
1865                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1866                         config->dv_xmeta_en = tmp;
1867                 else
1868                         config->dv_miss_info = 1;
1869         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1870                 config->lacp_by_user = !!tmp;
1871         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1872                 config->mr_ext_memseg_en = !!tmp;
1873         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1874                 config->max_dump_files_num = tmp;
1875         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1876                 config->lro.timeout = tmp;
1877         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1878                 DRV_LOG(DEBUG, "class argument is %s.", val);
1879         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1880                 config->log_hp_size = tmp;
1881         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1882                 if (tmp != MLX5_RCM_NONE &&
1883                     tmp != MLX5_RCM_LIGHT &&
1884                     tmp != MLX5_RCM_AGGR) {
1885                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1886                         rte_errno = EINVAL;
1887                         return -rte_errno;
1888                 }
1889                 config->reclaim_mode = tmp;
1890         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1891                 config->sys_mem_en = !!tmp;
1892         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1893                 config->decap_en = !!tmp;
1894         } else {
1895                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1896                 rte_errno = EINVAL;
1897                 return -rte_errno;
1898         }
1899         return 0;
1900 }
1901
1902 /**
1903  * Parse device parameters.
1904  *
1905  * @param config
1906  *   Pointer to device configuration structure.
1907  * @param devargs
1908  *   Device arguments structure.
1909  *
1910  * @return
1911  *   0 on success, a negative errno value otherwise and rte_errno is set.
1912  */
1913 int
1914 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1915 {
1916         const char **params = (const char *[]){
1917                 MLX5_RXQ_CQE_COMP_EN,
1918                 MLX5_RXQ_PKT_PAD_EN,
1919                 MLX5_RX_MPRQ_EN,
1920                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1921                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1922                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1923                 MLX5_RXQS_MIN_MPRQ,
1924                 MLX5_TXQ_INLINE,
1925                 MLX5_TXQ_INLINE_MIN,
1926                 MLX5_TXQ_INLINE_MAX,
1927                 MLX5_TXQ_INLINE_MPW,
1928                 MLX5_TXQS_MIN_INLINE,
1929                 MLX5_TXQS_MAX_VEC,
1930                 MLX5_TXQ_MPW_EN,
1931                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1932                 MLX5_TXQ_MAX_INLINE_LEN,
1933                 MLX5_TX_DB_NC,
1934                 MLX5_TX_PP,
1935                 MLX5_TX_SKEW,
1936                 MLX5_TX_VEC_EN,
1937                 MLX5_RX_VEC_EN,
1938                 MLX5_L3_VXLAN_EN,
1939                 MLX5_VF_NL_EN,
1940                 MLX5_DV_ESW_EN,
1941                 MLX5_DV_FLOW_EN,
1942                 MLX5_DV_XMETA_EN,
1943                 MLX5_LACP_BY_USER,
1944                 MLX5_MR_EXT_MEMSEG_EN,
1945                 MLX5_REPRESENTOR,
1946                 MLX5_MAX_DUMP_FILES_NUM,
1947                 MLX5_LRO_TIMEOUT_USEC,
1948                 MLX5_CLASS_ARG_NAME,
1949                 MLX5_HP_BUF_SIZE,
1950                 MLX5_RECLAIM_MEM,
1951                 MLX5_SYS_MEM_EN,
1952                 MLX5_DECAP_EN,
1953                 NULL,
1954         };
1955         struct rte_kvargs *kvlist;
1956         int ret = 0;
1957         int i;
1958
1959         if (devargs == NULL)
1960                 return 0;
1961         /* Following UGLY cast is done to pass checkpatch. */
1962         kvlist = rte_kvargs_parse(devargs->args, params);
1963         if (kvlist == NULL) {
1964                 rte_errno = EINVAL;
1965                 return -rte_errno;
1966         }
1967         /* Process parameters. */
1968         for (i = 0; (params[i] != NULL); ++i) {
1969                 if (rte_kvargs_count(kvlist, params[i])) {
1970                         ret = rte_kvargs_process(kvlist, params[i],
1971                                                  mlx5_args_check, config);
1972                         if (ret) {
1973                                 rte_errno = EINVAL;
1974                                 rte_kvargs_free(kvlist);
1975                                 return -rte_errno;
1976                         }
1977                 }
1978         }
1979         rte_kvargs_free(kvlist);
1980         return 0;
1981 }
1982
1983 /**
1984  * Configures the minimal amount of data to inline into WQE
1985  * while sending packets.
1986  *
1987  * - the txq_inline_min has the maximal priority, if this
1988  *   key is specified in devargs
1989  * - if DevX is enabled the inline mode is queried from the
1990  *   device (HCA attributes and NIC vport context if needed).
1991  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1992  *   and none (0 bytes) for other NICs
1993  *
1994  * @param spawn
1995  *   Verbs device parameters (name, port, switch_info) to spawn.
1996  * @param config
1997  *   Device configuration parameters.
1998  */
1999 void
2000 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2001                     struct mlx5_dev_config *config)
2002 {
2003         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2004                 /* Application defines size of inlined data explicitly. */
2005                 switch (spawn->pci_dev->id.device_id) {
2006                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2007                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2008                         if (config->txq_inline_min <
2009                                        (int)MLX5_INLINE_HSIZE_L2) {
2010                                 DRV_LOG(DEBUG,
2011                                         "txq_inline_mix aligned to minimal"
2012                                         " ConnectX-4 required value %d",
2013                                         (int)MLX5_INLINE_HSIZE_L2);
2014                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2015                         }
2016                         break;
2017                 }
2018                 goto exit;
2019         }
2020         if (config->hca_attr.eth_net_offloads) {
2021                 /* We have DevX enabled, inline mode queried successfully. */
2022                 switch (config->hca_attr.wqe_inline_mode) {
2023                 case MLX5_CAP_INLINE_MODE_L2:
2024                         /* outer L2 header must be inlined. */
2025                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2026                         goto exit;
2027                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2028                         /* No inline data are required by NIC. */
2029                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2030                         config->hw_vlan_insert =
2031                                 config->hca_attr.wqe_vlan_insert;
2032                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2033                         goto exit;
2034                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2035                         /* inline mode is defined by NIC vport context. */
2036                         if (!config->hca_attr.eth_virt)
2037                                 break;
2038                         switch (config->hca_attr.vport_inline_mode) {
2039                         case MLX5_INLINE_MODE_NONE:
2040                                 config->txq_inline_min =
2041                                         MLX5_INLINE_HSIZE_NONE;
2042                                 goto exit;
2043                         case MLX5_INLINE_MODE_L2:
2044                                 config->txq_inline_min =
2045                                         MLX5_INLINE_HSIZE_L2;
2046                                 goto exit;
2047                         case MLX5_INLINE_MODE_IP:
2048                                 config->txq_inline_min =
2049                                         MLX5_INLINE_HSIZE_L3;
2050                                 goto exit;
2051                         case MLX5_INLINE_MODE_TCP_UDP:
2052                                 config->txq_inline_min =
2053                                         MLX5_INLINE_HSIZE_L4;
2054                                 goto exit;
2055                         case MLX5_INLINE_MODE_INNER_L2:
2056                                 config->txq_inline_min =
2057                                         MLX5_INLINE_HSIZE_INNER_L2;
2058                                 goto exit;
2059                         case MLX5_INLINE_MODE_INNER_IP:
2060                                 config->txq_inline_min =
2061                                         MLX5_INLINE_HSIZE_INNER_L3;
2062                                 goto exit;
2063                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2064                                 config->txq_inline_min =
2065                                         MLX5_INLINE_HSIZE_INNER_L4;
2066                                 goto exit;
2067                         }
2068                 }
2069         }
2070         /*
2071          * We get here if we are unable to deduce
2072          * inline data size with DevX. Try PCI ID
2073          * to determine old NICs.
2074          */
2075         switch (spawn->pci_dev->id.device_id) {
2076         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2077         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2078         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2079         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2080                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2081                 config->hw_vlan_insert = 0;
2082                 break;
2083         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2084         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2085         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2086         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2087                 /*
2088                  * These NICs support VLAN insertion from WQE and
2089                  * report the wqe_vlan_insert flag. But there is the bug
2090                  * and PFC control may be broken, so disable feature.
2091                  */
2092                 config->hw_vlan_insert = 0;
2093                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2094                 break;
2095         default:
2096                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2097                 break;
2098         }
2099 exit:
2100         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2101 }
2102
2103 /**
2104  * Configures the metadata mask fields in the shared context.
2105  *
2106  * @param [in] dev
2107  *   Pointer to Ethernet device.
2108  */
2109 void
2110 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2111 {
2112         struct mlx5_priv *priv = dev->data->dev_private;
2113         struct mlx5_dev_ctx_shared *sh = priv->sh;
2114         uint32_t meta, mark, reg_c0;
2115
2116         reg_c0 = ~priv->vport_meta_mask;
2117         switch (priv->config.dv_xmeta_en) {
2118         case MLX5_XMETA_MODE_LEGACY:
2119                 meta = UINT32_MAX;
2120                 mark = MLX5_FLOW_MARK_MASK;
2121                 break;
2122         case MLX5_XMETA_MODE_META16:
2123                 meta = reg_c0 >> rte_bsf32(reg_c0);
2124                 mark = MLX5_FLOW_MARK_MASK;
2125                 break;
2126         case MLX5_XMETA_MODE_META32:
2127                 meta = UINT32_MAX;
2128                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2129                 break;
2130         default:
2131                 meta = 0;
2132                 mark = 0;
2133                 MLX5_ASSERT(false);
2134                 break;
2135         }
2136         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2137                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2138                                  sh->dv_mark_mask, mark);
2139         else
2140                 sh->dv_mark_mask = mark;
2141         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2142                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2143                                  sh->dv_meta_mask, meta);
2144         else
2145                 sh->dv_meta_mask = meta;
2146         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2147                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2148                                  sh->dv_meta_mask, reg_c0);
2149         else
2150                 sh->dv_regc0_mask = reg_c0;
2151         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2152         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2153         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2154         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2155 }
2156
2157 int
2158 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2159 {
2160         static const char *const dynf_names[] = {
2161                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2162                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2163                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2164         };
2165         unsigned int i;
2166
2167         if (n < RTE_DIM(dynf_names))
2168                 return -ENOMEM;
2169         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2170                 if (names[i] == NULL)
2171                         return -EINVAL;
2172                 strcpy(names[i], dynf_names[i]);
2173         }
2174         return RTE_DIM(dynf_names);
2175 }
2176
2177 /**
2178  * Comparison callback to sort device data.
2179  *
2180  * This is meant to be used with qsort().
2181  *
2182  * @param a[in]
2183  *   Pointer to pointer to first data object.
2184  * @param b[in]
2185  *   Pointer to pointer to second data object.
2186  *
2187  * @return
2188  *   0 if both objects are equal, less than 0 if the first argument is less
2189  *   than the second, greater than 0 otherwise.
2190  */
2191 int
2192 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2193                               struct mlx5_dev_config *config)
2194 {
2195         struct mlx5_dev_ctx_shared *sh = priv->sh;
2196         struct mlx5_dev_config *sh_conf = NULL;
2197         uint16_t port_id;
2198
2199         MLX5_ASSERT(sh);
2200         /* Nothing to compare for the single/first device. */
2201         if (sh->refcnt == 1)
2202                 return 0;
2203         /* Find the device with shared context. */
2204         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2205                 struct mlx5_priv *opriv =
2206                         rte_eth_devices[port_id].data->dev_private;
2207
2208                 if (opriv && opriv != priv && opriv->sh == sh) {
2209                         sh_conf = &opriv->config;
2210                         break;
2211                 }
2212         }
2213         if (!sh_conf)
2214                 return 0;
2215         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2216                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2217                              " for shared %s context", sh->ibdev_name);
2218                 rte_errno = EINVAL;
2219                 return rte_errno;
2220         }
2221         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2222                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2223                              " for shared %s context", sh->ibdev_name);
2224                 rte_errno = EINVAL;
2225                 return rte_errno;
2226         }
2227         return 0;
2228 }
2229
2230 /**
2231  * Look for the ethernet device belonging to mlx5 driver.
2232  *
2233  * @param[in] port_id
2234  *   port_id to start looking for device.
2235  * @param[in] pci_dev
2236  *   Pointer to the hint PCI device. When device is being probed
2237  *   the its siblings (master and preceding representors might
2238  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2239  *   is not completed yet, for this case match on hint PCI
2240  *   device may be used to detect sibling device.
2241  *
2242  * @return
2243  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2244  */
2245 uint16_t
2246 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2247 {
2248         while (port_id < RTE_MAX_ETHPORTS) {
2249                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2250
2251                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2252                     dev->device &&
2253                     (dev->device == &pci_dev->device ||
2254                      (dev->device->driver &&
2255                      dev->device->driver->name &&
2256                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2257                         break;
2258                 port_id++;
2259         }
2260         if (port_id >= RTE_MAX_ETHPORTS)
2261                 return RTE_MAX_ETHPORTS;
2262         return port_id;
2263 }
2264
2265 /**
2266  * DPDK callback to remove a PCI device.
2267  *
2268  * This function removes all Ethernet devices belong to a given PCI device.
2269  *
2270  * @param[in] pci_dev
2271  *   Pointer to the PCI device.
2272  *
2273  * @return
2274  *   0 on success, the function cannot fail.
2275  */
2276 static int
2277 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2278 {
2279         uint16_t port_id;
2280         int ret = 0;
2281
2282         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2283                 /*
2284                  * mlx5_dev_close() is not registered to secondary process,
2285                  * call the close function explicitly for secondary process.
2286                  */
2287                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2288                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2289                 else
2290                         ret |= rte_eth_dev_close(port_id);
2291         }
2292         return ret == 0 ? 0 : -EIO;
2293 }
2294
2295 static const struct rte_pci_id mlx5_pci_id_map[] = {
2296         {
2297                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2298                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2299         },
2300         {
2301                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2302                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2303         },
2304         {
2305                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2306                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2307         },
2308         {
2309                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2310                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2311         },
2312         {
2313                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2314                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2315         },
2316         {
2317                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2318                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2319         },
2320         {
2321                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2322                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2323         },
2324         {
2325                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2326                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2327         },
2328         {
2329                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2330                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2331         },
2332         {
2333                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2334                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2335         },
2336         {
2337                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2338                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2339         },
2340         {
2341                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2342                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2343         },
2344         {
2345                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2346                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2347         },
2348         {
2349                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2350                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2351         },
2352         {
2353                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2354                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2355         },
2356         {
2357                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2358                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2359         },
2360         {
2361                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2362                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2363         },
2364         {
2365                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2366                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2367         },
2368         {
2369                 .vendor_id = 0
2370         }
2371 };
2372
2373 static struct mlx5_pci_driver mlx5_driver = {
2374         .driver_class = MLX5_CLASS_NET,
2375         .pci_driver = {
2376                 .driver = {
2377                         .name = MLX5_PCI_DRIVER_NAME,
2378                 },
2379                 .id_table = mlx5_pci_id_map,
2380                 .probe = mlx5_os_pci_probe,
2381                 .remove = mlx5_pci_remove,
2382                 .dma_map = mlx5_dma_map,
2383                 .dma_unmap = mlx5_dma_unmap,
2384                 .drv_flags = PCI_DRV_FLAGS,
2385         },
2386 };
2387
2388 /* Initialize driver log type. */
2389 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2390
2391 /**
2392  * Driver initialization routine.
2393  */
2394 RTE_INIT(rte_mlx5_pmd_init)
2395 {
2396         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2397         mlx5_common_init();
2398         /* Build the static tables for Verbs conversion. */
2399         mlx5_set_ptype_table();
2400         mlx5_set_cksum_table();
2401         mlx5_set_swp_types_table();
2402         if (mlx5_glue)
2403                 mlx5_pci_driver_register(&mlx5_driver);
2404 }
2405
2406 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2407 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2408 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");