drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 180                                                 LIST_HEAD_INITIALIZER();
 181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 182
 183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 185         {
 186                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 187                 .trunk_size = 64,
 188                 .grow_trunk = 3,
 189                 .grow_shift = 2,
 190                 .need_lock = 0,
 191                 .release_mem_en = 1,
 192                 .malloc = rte_malloc_socket,
 193                 .free = rte_free,
 194                 .type = "mlx5_encap_decap_ipool",
 195         },
 196         {
 197                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 198                 .trunk_size = 64,
 199                 .grow_trunk = 3,
 200                 .grow_shift = 2,
 201                 .need_lock = 0,
 202                 .release_mem_en = 1,
 203                 .malloc = rte_malloc_socket,
 204                 .free = rte_free,
 205                 .type = "mlx5_push_vlan_ipool",
 206         },
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_tag_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_port_id_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_jump_ipool",
 239         },
 240 #endif
 241         {
 242                 .size = sizeof(struct mlx5_flow_meter),
 243                 .trunk_size = 64,
 244                 .grow_trunk = 3,
 245                 .grow_shift = 2,
 246                 .need_lock = 0,
 247                 .release_mem_en = 1,
 248                 .malloc = rte_malloc_socket,
 249                 .free = rte_free,
 250                 .type = "mlx5_meter_ipool",
 251         },
 252         {
 253                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 254                 .trunk_size = 64,
 255                 .grow_trunk = 3,
 256                 .grow_shift = 2,
 257                 .need_lock = 0,
 258                 .release_mem_en = 1,
 259                 .malloc = rte_malloc_socket,
 260                 .free = rte_free,
 261                 .type = "mlx5_mcp_ipool",
 262         },
 263         {
 264                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_hrxq_ipool",
 273         },
 274         {
 275                 /*
 276                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 277                  * It set in run time according to PCI function configuration.
 278                  */
 279                 .size = 0,
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_flow_handle_ipool",
 288         },
 289         {
 290                 .size = sizeof(struct rte_flow),
 291                 .trunk_size = 4096,
 292                 .need_lock = 1,
 293                 .release_mem_en = 1,
 294                 .malloc = rte_malloc_socket,
 295                 .free = rte_free,
 296                 .type = "rte_flow_ipool",
 297         },
 298 };
 299
 300
 301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 303
 304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 305
 306 /**
 307  * Allocate ID pool structure.
 308  *
 309  * @param[in] max_id
 310  *   The maximum id can be allocated from the pool.
 311  *
 312  * @return
 313  *   Pointer to pool object, NULL value otherwise.
 314  */
 315 struct mlx5_flow_id_pool *
 316 mlx5_flow_id_pool_alloc(uint32_t max_id)
 317 {
 318         struct mlx5_flow_id_pool *pool;
 319         void *mem;
 320
 321         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 322                            RTE_CACHE_LINE_SIZE);
 323         if (!pool) {
 324                 DRV_LOG(ERR, "can't allocate id pool");
 325                 rte_errno  = ENOMEM;
 326                 return NULL;
 327         }
 328         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 329                           RTE_CACHE_LINE_SIZE);
 330         if (!mem) {
 331                 DRV_LOG(ERR, "can't allocate mem for id pool");
 332                 rte_errno  = ENOMEM;
 333                 goto error;
 334         }
 335         pool->free_arr = mem;
 336         pool->curr = pool->free_arr;
 337         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 338         pool->base_index = 0;
 339         pool->max_id = max_id;
 340         return pool;
 341 error:
 342         rte_free(pool);
 343         return NULL;
 344 }
 345
 346 /**
 347  * Release ID pool structure.
 348  *
 349  * @param[in] pool
 350  *   Pointer to flow id pool object to free.
 351  */
 352 void
 353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 354 {
 355         rte_free(pool->free_arr);
 356         rte_free(pool);
 357 }
 358
 359 /**
 360  * Generate ID.
 361  *
 362  * @param[in] pool
 363  *   Pointer to flow id pool.
 364  * @param[out] id
 365  *   The generated ID.
 366  *
 367  * @return
 368  *   0 on success, error value otherwise.
 369  */
 370 uint32_t
 371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 372 {
 373         if (pool->curr == pool->free_arr) {
 374                 if (pool->base_index == pool->max_id) {
 375                         rte_errno  = ENOMEM;
 376                         DRV_LOG(ERR, "no free id");
 377                         return -rte_errno;
 378                 }
 379                 *id = ++pool->base_index;
 380                 return 0;
 381         }
 382         *id = *(--pool->curr);
 383         return 0;
 384 }
 385
 386 /**
 387  * Release ID.
 388  *
 389  * @param[in] pool
 390  *   Pointer to flow id pool.
 391  * @param[out] id
 392  *   The generated ID.
 393  *
 394  * @return
 395  *   0 on success, error value otherwise.
 396  */
 397 uint32_t
 398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 399 {
 400         uint32_t size;
 401         uint32_t size2;
 402         void *mem;
 403
 404         if (pool->curr == pool->last) {
 405                 size = pool->curr - pool->free_arr;
 406                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 407                 MLX5_ASSERT(size2 > size);
 408                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 409                 if (!mem) {
 410                         DRV_LOG(ERR, "can't allocate mem for id pool");
 411                         rte_errno  = ENOMEM;
 412                         return -rte_errno;
 413                 }
 414                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 415                 rte_free(pool->free_arr);
 416                 pool->free_arr = mem;
 417                 pool->curr = pool->free_arr + size;
 418                 pool->last = pool->free_arr + size2;
 419         }
 420         *pool->curr = id;
 421         pool->curr++;
 422         return 0;
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 460                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 461                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 462         }
 463 }
 464
 465 /**
 466  * Destroy all the resources allocated for a counter memory management.
 467  *
 468  * @param[in] mng
 469  *   Pointer to the memory management structure.
 470  */
 471 static void
 472 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 473 {
 474         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 475
 476         LIST_REMOVE(mng, next);
 477         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 478         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 479         rte_free(mem);
 480 }
 481
 482 /**
 483  * Close and release all the resources of the counters management.
 484  *
 485  * @param[in] sh
 486  *   Pointer to mlx5_dev_ctx_shared object to free.
 487  */
 488 static void
 489 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 490 {
 491         struct mlx5_counter_stats_mem_mng *mng;
 492         int i;
 493         int j;
 494         int retries = 1024;
 495
 496         rte_errno = 0;
 497         while (--retries) {
 498                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 499                 if (rte_errno != EINPROGRESS)
 500                         break;
 501                 rte_pause();
 502         }
 503         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 504                 struct mlx5_flow_counter_pool *pool;
 505                 uint32_t batch = !!(i > 1);
 506
 507                 if (!sh->cmng.ccont[i].pools)
 508                         continue;
 509                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 510                 while (pool) {
 511                         if (batch && pool->min_dcs)
 512                                 claim_zero(mlx5_devx_cmd_destroy
 513                                                                (pool->min_dcs));
 514                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 515                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 516                                         claim_zero
 517                                          (mlx5_glue->destroy_flow_action
 518                                           (MLX5_POOL_GET_CNT
 519                                           (pool, j)->action));
 520                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 521                                     (pool, j)->dcs)
 522                                         claim_zero(mlx5_devx_cmd_destroy
 523                                                    (MLX5_GET_POOL_CNT_EXT
 524                                                     (pool, j)->dcs));
 525                         }
 526                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 527                         rte_free(pool);
 528                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 529                 }
 530                 rte_free(sh->cmng.ccont[i].pools);
 531         }
 532         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 533         while (mng) {
 534                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 535                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 536         }
 537         memset(&sh->cmng, 0, sizeof(sh->cmng));
 538 }
 539
 540 /**
 541  * Initialize the flow resources' indexed mempool.
 542  *
 543  * @param[in] sh
 544  *   Pointer to mlx5_dev_ctx_shared object.
 545  * @param[in] sh
 546  *   Pointer to user dev config.
 547  */
 548 static void
 549 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 550                        const struct mlx5_dev_config *config)
 551 {
 552         uint8_t i;
 553         struct mlx5_indexed_pool_config cfg;
 554
 555         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 556                 cfg = mlx5_ipool_cfg[i];
 557                 switch (i) {
 558                 default:
 559                         break;
 560                 /*
 561                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 562                  * according to PCI function flow configuration.
 563                  */
 564                 case MLX5_IPOOL_MLX5_FLOW:
 565                         cfg.size = config->dv_flow_en ?
 566                                 sizeof(struct mlx5_flow_handle) :
 567                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 568                         break;
 569                 }
 570                 if (config->reclaim_mode)
 571                         cfg.release_mem_en = 1;
 572                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 573         }
 574 }
 575
 576 /**
 577  * Release the flow resources' indexed mempool.
 578  *
 579  * @param[in] sh
 580  *   Pointer to mlx5_dev_ctx_shared object.
 581  */
 582 static void
 583 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 584 {
 585         uint8_t i;
 586
 587         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 588                 mlx5_ipool_destroy(sh->ipool[i]);
 589 }
 590
 591 /**
 592  * Allocate shared device context. If there is multiport device the
 593  * master and representors will share this context, if there is single
 594  * port dedicated device, the context will be used by only given
 595  * port due to unification.
 596  *
 597  * Routine first searches the context for the specified device name,
 598  * if found the shared context assumed and reference counter is incremented.
 599  * If no context found the new one is created and initialized with specified
 600  * device context and parameters.
 601  *
 602  * @param[in] spawn
 603  *   Pointer to the device attributes (name, port, etc).
 604  * @param[in] config
 605  *   Pointer to device configuration structure.
 606  *
 607  * @return
 608  *   Pointer to mlx5_dev_ctx_shared object on success,
 609  *   otherwise NULL and rte_errno is set.
 610  */
 611 struct mlx5_dev_ctx_shared *
 612 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 613                            const struct mlx5_dev_config *config)
 614 {
 615         struct mlx5_dev_ctx_shared *sh;
 616         int err = 0;
 617         uint32_t i;
 618         struct mlx5_devx_tis_attr tis_attr = { 0 };
 619
 620         MLX5_ASSERT(spawn);
 621         /* Secondary process should not create the shared context. */
 622         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 623         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 624         /* Search for IB context by device name. */
 625         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 626                 if (!strcmp(sh->ibdev_name,
 627                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 628                         sh->refcnt++;
 629                         goto exit;
 630                 }
 631         }
 632         /* No device found, we have to create new shared context. */
 633         MLX5_ASSERT(spawn->max_port);
 634         sh = rte_zmalloc("ethdev shared ib context",
 635                          sizeof(struct mlx5_dev_ctx_shared) +
 636                          spawn->max_port *
 637                          sizeof(struct mlx5_dev_shared_port),
 638                          RTE_CACHE_LINE_SIZE);
 639         if (!sh) {
 640                 DRV_LOG(ERR, "shared context allocation failure");
 641                 rte_errno  = ENOMEM;
 642                 goto exit;
 643         }
 644         err = mlx5_os_open_device(spawn, config, sh);
 645         if (!sh->ctx)
 646                 goto error;
 647         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 648         if (err) {
 649                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 650                 goto error;
 651         }
 652         sh->refcnt = 1;
 653         sh->max_port = spawn->max_port;
 654         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 655                 sizeof(sh->ibdev_name) - 1);
 656         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 657                 sizeof(sh->ibdev_path) - 1);
 658         /*
 659          * Setting port_id to max unallowed value means
 660          * there is no interrupt subhandler installed for
 661          * the given port index i.
 662          */
 663         for (i = 0; i < sh->max_port; i++) {
 664                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 665                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 666         }
 667         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 668         if (sh->pd == NULL) {
 669                 DRV_LOG(ERR, "PD allocation failure");
 670                 err = ENOMEM;
 671                 goto error;
 672         }
 673         if (sh->devx) {
 674                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 675                 if (err) {
 676                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 677                         goto error;
 678                 }
 679                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 680                 if (!sh->td) {
 681                         DRV_LOG(ERR, "TD allocation failure");
 682                         err = ENOMEM;
 683                         goto error;
 684                 }
 685                 tis_attr.transport_domain = sh->td->id;
 686                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 687                 if (!sh->tis) {
 688                         DRV_LOG(ERR, "TIS allocation failure");
 689                         err = ENOMEM;
 690                         goto error;
 691                 }
 692         }
 693         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 694                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 695         if (!sh->flow_id_pool) {
 696                 DRV_LOG(ERR, "can't create flow id pool");
 697                 err = ENOMEM;
 698                 goto error;
 699         }
 700         /*
 701          * Once the device is added to the list of memory event
 702          * callback, its global MR cache table cannot be expanded
 703          * on the fly because of deadlock. If it overflows, lookup
 704          * should be done by searching MR list linearly, which is slow.
 705          *
 706          * At this point the device is not added to the memory
 707          * event list yet, context is just being created.
 708          */
 709         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 710                                  MLX5_MR_BTREE_CACHE_N * 2,
 711                                  spawn->pci_dev->device.numa_node);
 712         if (err) {
 713                 err = rte_errno;
 714                 goto error;
 715         }
 716         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 717                               &sh->share_cache.dereg_mr_cb);
 718         mlx5_os_dev_shared_handler_install(sh);
 719         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 720         if (!sh->cnt_id_tbl) {
 721                 err = rte_errno;
 722                 goto error;
 723         }
 724         mlx5_flow_aging_init(sh);
 725         mlx5_flow_counters_mng_init(sh);
 726         mlx5_flow_ipool_create(sh, config);
 727         /* Add device to memory callback list. */
 728         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 729         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 730                          sh, mem_event_cb);
 731         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 732         /* Add context to the global device list. */
 733         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 734 exit:
 735         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 736         return sh;
 737 error:
 738         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 739         MLX5_ASSERT(sh);
 740         if (sh->cnt_id_tbl) {
 741                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 742                 sh->cnt_id_tbl = NULL;
 743         }
 744         if (sh->tis)
 745                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 746         if (sh->td)
 747                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 748         if (sh->pd)
 749                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 750         if (sh->ctx)
 751                 claim_zero(mlx5_glue->close_device(sh->ctx));
 752         if (sh->flow_id_pool)
 753                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 754         rte_free(sh);
 755         MLX5_ASSERT(err > 0);
 756         rte_errno = err;
 757         return NULL;
 758 }
 759
 760 /**
 761  * Free shared IB device context. Decrement counter and if zero free
 762  * all allocated resources and close handles.
 763  *
 764  * @param[in] sh
 765  *   Pointer to mlx5_dev_ctx_shared object to free
 766  */
 767 void
 768 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 769 {
 770         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 771 #ifdef RTE_LIBRTE_MLX5_DEBUG
 772         /* Check the object presence in the list. */
 773         struct mlx5_dev_ctx_shared *lctx;
 774
 775         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 776                 if (lctx == sh)
 777                         break;
 778         MLX5_ASSERT(lctx);
 779         if (lctx != sh) {
 780                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 781                 goto exit;
 782         }
 783 #endif
 784         MLX5_ASSERT(sh);
 785         MLX5_ASSERT(sh->refcnt);
 786         /* Secondary process should not free the shared context. */
 787         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 788         if (--sh->refcnt)
 789                 goto exit;
 790         /* Remove from memory callback device list. */
 791         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 792         LIST_REMOVE(sh, mem_event_cb);
 793         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 794         /* Release created Memory Regions. */
 795         mlx5_mr_release_cache(&sh->share_cache);
 796         /* Remove context from the global device list. */
 797         LIST_REMOVE(sh, next);
 798         /*
 799          *  Ensure there is no async event handler installed.
 800          *  Only primary process handles async device events.
 801          **/
 802         mlx5_flow_counters_mng_close(sh);
 803         mlx5_flow_ipool_destroy(sh);
 804         mlx5_os_dev_shared_handler_uninstall(sh);
 805         if (sh->cnt_id_tbl) {
 806                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 807                 sh->cnt_id_tbl = NULL;
 808         }
 809         if (sh->pd)
 810                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 811         if (sh->tis)
 812                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 813         if (sh->td)
 814                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 815         if (sh->ctx)
 816                 claim_zero(mlx5_glue->close_device(sh->ctx));
 817         if (sh->flow_id_pool)
 818                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 819         rte_free(sh);
 820 exit:
 821         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 822 }
 823
 824 /**
 825  * Destroy table hash list and all the root entries per domain.
 826  *
 827  * @param[in] priv
 828  *   Pointer to the private device data structure.
 829  */
 830 void
 831 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 832 {
 833         struct mlx5_dev_ctx_shared *sh = priv->sh;
 834         struct mlx5_flow_tbl_data_entry *tbl_data;
 835         union mlx5_flow_tbl_key table_key = {
 836                 {
 837                         .table_id = 0,
 838                         .reserved = 0,
 839                         .domain = 0,
 840                         .direction = 0,
 841                 }
 842         };
 843         struct mlx5_hlist_entry *pos;
 844
 845         if (!sh->flow_tbls)
 846                 return;
 847         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 848         if (pos) {
 849                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 850                                         entry);
 851                 MLX5_ASSERT(tbl_data);
 852                 mlx5_hlist_remove(sh->flow_tbls, pos);
 853                 rte_free(tbl_data);
 854         }
 855         table_key.direction = 1;
 856         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 857         if (pos) {
 858                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 859                                         entry);
 860                 MLX5_ASSERT(tbl_data);
 861                 mlx5_hlist_remove(sh->flow_tbls, pos);
 862                 rte_free(tbl_data);
 863         }
 864         table_key.direction = 0;
 865         table_key.domain = 1;
 866         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 867         if (pos) {
 868                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 869                                         entry);
 870                 MLX5_ASSERT(tbl_data);
 871                 mlx5_hlist_remove(sh->flow_tbls, pos);
 872                 rte_free(tbl_data);
 873         }
 874         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 875 }
 876
 877 /**
 878  * Initialize flow table hash list and create the root tables entry
 879  * for each domain.
 880  *
 881  * @param[in] priv
 882  *   Pointer to the private device data structure.
 883  *
 884  * @return
 885  *   Zero on success, positive error code otherwise.
 886  */
 887 int
 888 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 889 {
 890         struct mlx5_dev_ctx_shared *sh = priv->sh;
 891         char s[MLX5_HLIST_NAMESIZE];
 892         int err = 0;
 893
 894         MLX5_ASSERT(sh);
 895         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 896         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 897         if (!sh->flow_tbls) {
 898                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 899                 err = ENOMEM;
 900                 return err;
 901         }
 902 #ifndef HAVE_MLX5DV_DR
 903         /*
 904          * In case we have not DR support, the zero tables should be created
 905          * because DV expect to see them even if they cannot be created by
 906          * RDMA-CORE.
 907          */
 908         union mlx5_flow_tbl_key table_key = {
 909                 {
 910                         .table_id = 0,
 911                         .reserved = 0,
 912                         .domain = 0,
 913                         .direction = 0,
 914                 }
 915         };
 916         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 917                                                           sizeof(*tbl_data), 0);
 918
 919         if (!tbl_data) {
 920                 err = ENOMEM;
 921                 goto error;
 922         }
 923         tbl_data->entry.key = table_key.v64;
 924         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 925         if (err)
 926                 goto error;
 927         rte_atomic32_init(&tbl_data->tbl.refcnt);
 928         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 929         table_key.direction = 1;
 930         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 931         if (!tbl_data) {
 932                 err = ENOMEM;
 933                 goto error;
 934         }
 935         tbl_data->entry.key = table_key.v64;
 936         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 937         if (err)
 938                 goto error;
 939         rte_atomic32_init(&tbl_data->tbl.refcnt);
 940         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 941         table_key.direction = 0;
 942         table_key.domain = 1;
 943         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 944         if (!tbl_data) {
 945                 err = ENOMEM;
 946                 goto error;
 947         }
 948         tbl_data->entry.key = table_key.v64;
 949         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 950         if (err)
 951                 goto error;
 952         rte_atomic32_init(&tbl_data->tbl.refcnt);
 953         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 954         return err;
 955 error:
 956         mlx5_free_table_hash_list(priv);
 957 #endif /* HAVE_MLX5DV_DR */
 958         return err;
 959 }
 960
 961 /**
 962  * Initialize shared data between primary and secondary process.
 963  *
 964  * A memzone is reserved by primary process and secondary processes attach to
 965  * the memzone.
 966  *
 967  * @return
 968  *   0 on success, a negative errno value otherwise and rte_errno is set.
 969  */
 970 static int
 971 mlx5_init_shared_data(void)
 972 {
 973         const struct rte_memzone *mz;
 974         int ret = 0;
 975
 976         rte_spinlock_lock(&mlx5_shared_data_lock);
 977         if (mlx5_shared_data == NULL) {
 978                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 979                         /* Allocate shared memory. */
 980                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 981                                                  sizeof(*mlx5_shared_data),
 982                                                  SOCKET_ID_ANY, 0);
 983                         if (mz == NULL) {
 984                                 DRV_LOG(ERR,
 985                                         "Cannot allocate mlx5 shared data");
 986                                 ret = -rte_errno;
 987                                 goto error;
 988                         }
 989                         mlx5_shared_data = mz->addr;
 990                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 991                         rte_spinlock_init(&mlx5_shared_data->lock);
 992                 } else {
 993                         /* Lookup allocated shared memory. */
 994                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 995                         if (mz == NULL) {
 996                                 DRV_LOG(ERR,
 997                                         "Cannot attach mlx5 shared data");
 998                                 ret = -rte_errno;
 999                                 goto error;
1000                         }
1001                         mlx5_shared_data = mz->addr;
1002                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1003                 }
1004         }
1005 error:
1006         rte_spinlock_unlock(&mlx5_shared_data_lock);
1007         return ret;
1008 }
1009
1010 /**
1011  * Retrieve integer value from environment variable.
1012  *
1013  * @param[in] name
1014  *   Environment variable name.
1015  *
1016  * @return
1017  *   Integer value, 0 if the variable is not set.
1018  */
1019 int
1020 mlx5_getenv_int(const char *name)
1021 {
1022         const char *val = getenv(name);
1023
1024         if (val == NULL)
1025                 return 0;
1026         return atoi(val);
1027 }
1028
1029 /**
1030  * DPDK callback to add udp tunnel port
1031  *
1032  * @param[in] dev
1033  *   A pointer to eth_dev
1034  * @param[in] udp_tunnel
1035  *   A pointer to udp tunnel
1036  *
1037  * @return
1038  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1039  */
1040 int
1041 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1042                          struct rte_eth_udp_tunnel *udp_tunnel)
1043 {
1044         MLX5_ASSERT(udp_tunnel != NULL);
1045         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1046             udp_tunnel->udp_port == 4789)
1047                 return 0;
1048         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1049             udp_tunnel->udp_port == 4790)
1050                 return 0;
1051         return -ENOTSUP;
1052 }
1053
1054 /**
1055  * Initialize process private data structure.
1056  *
1057  * @param dev
1058  *   Pointer to Ethernet device structure.
1059  *
1060  * @return
1061  *   0 on success, a negative errno value otherwise and rte_errno is set.
1062  */
1063 int
1064 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1065 {
1066         struct mlx5_priv *priv = dev->data->dev_private;
1067         struct mlx5_proc_priv *ppriv;
1068         size_t ppriv_size;
1069
1070         /*
1071          * UAR register table follows the process private structure. BlueFlame
1072          * registers for Tx queues are stored in the table.
1073          */
1074         ppriv_size =
1075                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1076         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1077                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1078         if (!ppriv) {
1079                 rte_errno = ENOMEM;
1080                 return -rte_errno;
1081         }
1082         ppriv->uar_table_sz = ppriv_size;
1083         dev->process_private = ppriv;
1084         return 0;
1085 }
1086
1087 /**
1088  * Un-initialize process private data structure.
1089  *
1090  * @param dev
1091  *   Pointer to Ethernet device structure.
1092  */
1093 static void
1094 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1095 {
1096         if (!dev->process_private)
1097                 return;
1098         rte_free(dev->process_private);
1099         dev->process_private = NULL;
1100 }
1101
1102 /**
1103  * DPDK callback to close the device.
1104  *
1105  * Destroy all queues and objects, free memory.
1106  *
1107  * @param dev
1108  *   Pointer to Ethernet device structure.
1109  */
1110 void
1111 mlx5_dev_close(struct rte_eth_dev *dev)
1112 {
1113         struct mlx5_priv *priv = dev->data->dev_private;
1114         unsigned int i;
1115         int ret;
1116
1117         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1118                 /* Check if process_private released. */
1119                 if (!dev->process_private)
1120                         return;
1121                 mlx5_tx_uar_uninit_secondary(dev);
1122                 mlx5_proc_priv_uninit(dev);
1123                 rte_eth_dev_release_port(dev);
1124                 return;
1125         }
1126         if (!priv->sh)
1127                 return;
1128         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1129                 dev->data->port_id,
1130                 ((priv->sh->ctx != NULL) ?
1131                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1132         /*
1133          * If default mreg copy action is removed at the stop stage,
1134          * the search will return none and nothing will be done anymore.
1135          */
1136         mlx5_flow_stop_default(dev);
1137         mlx5_traffic_disable(dev);
1138         /*
1139          * If all the flows are already flushed in the device stop stage,
1140          * then this will return directly without any action.
1141          */
1142         mlx5_flow_list_flush(dev, &priv->flows, true);
1143         mlx5_flow_meter_flush(dev, NULL);
1144         /* Free the intermediate buffers for flow creation. */
1145         mlx5_flow_free_intermediate(dev);
1146         /* Prevent crashes when queues are still in use. */
1147         dev->rx_pkt_burst = removed_rx_burst;
1148         dev->tx_pkt_burst = removed_tx_burst;
1149         rte_wmb();
1150         /* Disable datapath on secondary process. */
1151         mlx5_mp_req_stop_rxtx(dev);
1152         if (priv->rxqs != NULL) {
1153                 /* XXX race condition if mlx5_rx_burst() is still running. */
1154                 usleep(1000);
1155                 for (i = 0; (i != priv->rxqs_n); ++i)
1156                         mlx5_rxq_release(dev, i);
1157                 priv->rxqs_n = 0;
1158                 priv->rxqs = NULL;
1159         }
1160         if (priv->txqs != NULL) {
1161                 /* XXX race condition if mlx5_tx_burst() is still running. */
1162                 usleep(1000);
1163                 for (i = 0; (i != priv->txqs_n); ++i)
1164                         mlx5_txq_release(dev, i);
1165                 priv->txqs_n = 0;
1166                 priv->txqs = NULL;
1167         }
1168         mlx5_proc_priv_uninit(dev);
1169         if (priv->mreg_cp_tbl)
1170                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1171         mlx5_mprq_free_mp(dev);
1172         mlx5_os_free_shared_dr(priv);
1173         if (priv->rss_conf.rss_key != NULL)
1174                 rte_free(priv->rss_conf.rss_key);
1175         if (priv->reta_idx != NULL)
1176                 rte_free(priv->reta_idx);
1177         if (priv->config.vf)
1178                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1179                                        dev->data->mac_addrs,
1180                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1181         if (priv->nl_socket_route >= 0)
1182                 close(priv->nl_socket_route);
1183         if (priv->nl_socket_rdma >= 0)
1184                 close(priv->nl_socket_rdma);
1185         if (priv->vmwa_context)
1186                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1187         ret = mlx5_hrxq_verify(dev);
1188         if (ret)
1189                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1190                         dev->data->port_id);
1191         ret = mlx5_ind_table_obj_verify(dev);
1192         if (ret)
1193                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1194                         dev->data->port_id);
1195         ret = mlx5_rxq_obj_verify(dev);
1196         if (ret)
1197                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1198                         dev->data->port_id);
1199         ret = mlx5_rxq_verify(dev);
1200         if (ret)
1201                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1202                         dev->data->port_id);
1203         ret = mlx5_txq_obj_verify(dev);
1204         if (ret)
1205                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1206                         dev->data->port_id);
1207         ret = mlx5_txq_verify(dev);
1208         if (ret)
1209                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1210                         dev->data->port_id);
1211         ret = mlx5_flow_verify(dev);
1212         if (ret)
1213                 DRV_LOG(WARNING, "port %u some flows still remain",
1214                         dev->data->port_id);
1215         /*
1216          * Free the shared context in last turn, because the cleanup
1217          * routines above may use some shared fields, like
1218          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1219          * ifindex if Netlink fails.
1220          */
1221         mlx5_free_shared_dev_ctx(priv->sh);
1222         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1223                 unsigned int c = 0;
1224                 uint16_t port_id;
1225
1226                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1227                         struct mlx5_priv *opriv =
1228                                 rte_eth_devices[port_id].data->dev_private;
1229
1230                         if (!opriv ||
1231                             opriv->domain_id != priv->domain_id ||
1232                             &rte_eth_devices[port_id] == dev)
1233                                 continue;
1234                         ++c;
1235                         break;
1236                 }
1237                 if (!c)
1238                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1239         }
1240         memset(priv, 0, sizeof(*priv));
1241         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1242         /*
1243          * Reset mac_addrs to NULL such that it is not freed as part of
1244          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1245          * it is freed when dev_private is freed.
1246          */
1247         dev->data->mac_addrs = NULL;
1248 }
1249
1250 /**
1251  * Verify and store value for device argument.
1252  *
1253  * @param[in] key
1254  *   Key argument to verify.
1255  * @param[in] val
1256  *   Value associated with key.
1257  * @param opaque
1258  *   User data.
1259  *
1260  * @return
1261  *   0 on success, a negative errno value otherwise and rte_errno is set.
1262  */
1263 static int
1264 mlx5_args_check(const char *key, const char *val, void *opaque)
1265 {
1266         struct mlx5_dev_config *config = opaque;
1267         unsigned long tmp;
1268
1269         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1270         if (!strcmp(MLX5_REPRESENTOR, key))
1271                 return 0;
1272         errno = 0;
1273         tmp = strtoul(val, NULL, 0);
1274         if (errno) {
1275                 rte_errno = errno;
1276                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1277                 return -rte_errno;
1278         }
1279         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1280                 config->cqe_comp = !!tmp;
1281         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1282                 config->cqe_pad = !!tmp;
1283         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1284                 config->hw_padding = !!tmp;
1285         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1286                 config->mprq.enabled = !!tmp;
1287         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1288                 config->mprq.stride_num_n = tmp;
1289         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1290                 config->mprq.stride_size_n = tmp;
1291         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1292                 config->mprq.max_memcpy_len = tmp;
1293         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1294                 config->mprq.min_rxqs_num = tmp;
1295         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1296                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1297                                  " converted to txq_inline_max", key);
1298                 config->txq_inline_max = tmp;
1299         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1300                 config->txq_inline_max = tmp;
1301         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1302                 config->txq_inline_min = tmp;
1303         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1304                 config->txq_inline_mpw = tmp;
1305         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1306                 config->txqs_inline = tmp;
1307         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1308                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1309         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1310                 config->mps = !!tmp;
1311         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1312                 if (tmp != MLX5_TXDB_CACHED &&
1313                     tmp != MLX5_TXDB_NCACHED &&
1314                     tmp != MLX5_TXDB_HEURISTIC) {
1315                         DRV_LOG(ERR, "invalid Tx doorbell "
1316                                      "mapping parameter");
1317                         rte_errno = EINVAL;
1318                         return -rte_errno;
1319                 }
1320                 config->dbnc = tmp;
1321         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1322                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1323         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1324                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1325                                  " converted to txq_inline_mpw", key);
1326                 config->txq_inline_mpw = tmp;
1327         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1328                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1329         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1330                 config->rx_vec_en = !!tmp;
1331         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1332                 config->l3_vxlan_en = !!tmp;
1333         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1334                 config->vf_nl_en = !!tmp;
1335         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1336                 config->dv_esw_en = !!tmp;
1337         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1338                 config->dv_flow_en = !!tmp;
1339         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1340                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1341                     tmp != MLX5_XMETA_MODE_META16 &&
1342                     tmp != MLX5_XMETA_MODE_META32) {
1343                         DRV_LOG(ERR, "invalid extensive "
1344                                      "metadata parameter");
1345                         rte_errno = EINVAL;
1346                         return -rte_errno;
1347                 }
1348                 config->dv_xmeta_en = tmp;
1349         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1350                 config->mr_ext_memseg_en = !!tmp;
1351         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1352                 config->max_dump_files_num = tmp;
1353         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1354                 config->lro.timeout = tmp;
1355         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1356                 DRV_LOG(DEBUG, "class argument is %s.", val);
1357         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1358                 config->log_hp_size = tmp;
1359         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1360                 if (tmp != MLX5_RCM_NONE &&
1361                     tmp != MLX5_RCM_LIGHT &&
1362                     tmp != MLX5_RCM_AGGR) {
1363                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1364                         rte_errno = EINVAL;
1365                         return -rte_errno;
1366                 }
1367                 config->reclaim_mode = tmp;
1368         } else {
1369                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1370                 rte_errno = EINVAL;
1371                 return -rte_errno;
1372         }
1373         return 0;
1374 }
1375
1376 /**
1377  * Parse device parameters.
1378  *
1379  * @param config
1380  *   Pointer to device configuration structure.
1381  * @param devargs
1382  *   Device arguments structure.
1383  *
1384  * @return
1385  *   0 on success, a negative errno value otherwise and rte_errno is set.
1386  */
1387 int
1388 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1389 {
1390         const char **params = (const char *[]){
1391                 MLX5_RXQ_CQE_COMP_EN,
1392                 MLX5_RXQ_CQE_PAD_EN,
1393                 MLX5_RXQ_PKT_PAD_EN,
1394                 MLX5_RX_MPRQ_EN,
1395                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1396                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1397                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1398                 MLX5_RXQS_MIN_MPRQ,
1399                 MLX5_TXQ_INLINE,
1400                 MLX5_TXQ_INLINE_MIN,
1401                 MLX5_TXQ_INLINE_MAX,
1402                 MLX5_TXQ_INLINE_MPW,
1403                 MLX5_TXQS_MIN_INLINE,
1404                 MLX5_TXQS_MAX_VEC,
1405                 MLX5_TXQ_MPW_EN,
1406                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1407                 MLX5_TXQ_MAX_INLINE_LEN,
1408                 MLX5_TX_DB_NC,
1409                 MLX5_TX_VEC_EN,
1410                 MLX5_RX_VEC_EN,
1411                 MLX5_L3_VXLAN_EN,
1412                 MLX5_VF_NL_EN,
1413                 MLX5_DV_ESW_EN,
1414                 MLX5_DV_FLOW_EN,
1415                 MLX5_DV_XMETA_EN,
1416                 MLX5_MR_EXT_MEMSEG_EN,
1417                 MLX5_REPRESENTOR,
1418                 MLX5_MAX_DUMP_FILES_NUM,
1419                 MLX5_LRO_TIMEOUT_USEC,
1420                 MLX5_CLASS_ARG_NAME,
1421                 MLX5_HP_BUF_SIZE,
1422                 MLX5_RECLAIM_MEM,
1423                 NULL,
1424         };
1425         struct rte_kvargs *kvlist;
1426         int ret = 0;
1427         int i;
1428
1429         if (devargs == NULL)
1430                 return 0;
1431         /* Following UGLY cast is done to pass checkpatch. */
1432         kvlist = rte_kvargs_parse(devargs->args, params);
1433         if (kvlist == NULL) {
1434                 rte_errno = EINVAL;
1435                 return -rte_errno;
1436         }
1437         /* Process parameters. */
1438         for (i = 0; (params[i] != NULL); ++i) {
1439                 if (rte_kvargs_count(kvlist, params[i])) {
1440                         ret = rte_kvargs_process(kvlist, params[i],
1441                                                  mlx5_args_check, config);
1442                         if (ret) {
1443                                 rte_errno = EINVAL;
1444                                 rte_kvargs_free(kvlist);
1445                                 return -rte_errno;
1446                         }
1447                 }
1448         }
1449         rte_kvargs_free(kvlist);
1450         return 0;
1451 }
1452
1453 /**
1454  * PMD global initialization.
1455  *
1456  * Independent from individual device, this function initializes global
1457  * per-PMD data structures distinguishing primary and secondary processes.
1458  * Hence, each initialization is called once per a process.
1459  *
1460  * @return
1461  *   0 on success, a negative errno value otherwise and rte_errno is set.
1462  */
1463 int
1464 mlx5_init_once(void)
1465 {
1466         struct mlx5_shared_data *sd;
1467         struct mlx5_local_data *ld = &mlx5_local_data;
1468         int ret = 0;
1469
1470         if (mlx5_init_shared_data())
1471                 return -rte_errno;
1472         sd = mlx5_shared_data;
1473         MLX5_ASSERT(sd);
1474         rte_spinlock_lock(&sd->lock);
1475         switch (rte_eal_process_type()) {
1476         case RTE_PROC_PRIMARY:
1477                 if (sd->init_done)
1478                         break;
1479                 LIST_INIT(&sd->mem_event_cb_list);
1480                 rte_rwlock_init(&sd->mem_event_rwlock);
1481                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1482                                                 mlx5_mr_mem_event_cb, NULL);
1483                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1484                                            mlx5_mp_primary_handle);
1485                 if (ret)
1486                         goto out;
1487                 sd->init_done = true;
1488                 break;
1489         case RTE_PROC_SECONDARY:
1490                 if (ld->init_done)
1491                         break;
1492                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1493                                              mlx5_mp_secondary_handle);
1494                 if (ret)
1495                         goto out;
1496                 ++sd->secondary_cnt;
1497                 ld->init_done = true;
1498                 break;
1499         default:
1500                 break;
1501         }
1502 out:
1503         rte_spinlock_unlock(&sd->lock);
1504         return ret;
1505 }
1506
1507 /**
1508  * Configures the minimal amount of data to inline into WQE
1509  * while sending packets.
1510  *
1511  * - the txq_inline_min has the maximal priority, if this
1512  *   key is specified in devargs
1513  * - if DevX is enabled the inline mode is queried from the
1514  *   device (HCA attributes and NIC vport context if needed).
1515  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1516  *   and none (0 bytes) for other NICs
1517  *
1518  * @param spawn
1519  *   Verbs device parameters (name, port, switch_info) to spawn.
1520  * @param config
1521  *   Device configuration parameters.
1522  */
1523 void
1524 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1525                     struct mlx5_dev_config *config)
1526 {
1527         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1528                 /* Application defines size of inlined data explicitly. */
1529                 switch (spawn->pci_dev->id.device_id) {
1530                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1531                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1532                         if (config->txq_inline_min <
1533                                        (int)MLX5_INLINE_HSIZE_L2) {
1534                                 DRV_LOG(DEBUG,
1535                                         "txq_inline_mix aligned to minimal"
1536                                         " ConnectX-4 required value %d",
1537                                         (int)MLX5_INLINE_HSIZE_L2);
1538                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1539                         }
1540                         break;
1541                 }
1542                 goto exit;
1543         }
1544         if (config->hca_attr.eth_net_offloads) {
1545                 /* We have DevX enabled, inline mode queried successfully. */
1546                 switch (config->hca_attr.wqe_inline_mode) {
1547                 case MLX5_CAP_INLINE_MODE_L2:
1548                         /* outer L2 header must be inlined. */
1549                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1550                         goto exit;
1551                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1552                         /* No inline data are required by NIC. */
1553                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1554                         config->hw_vlan_insert =
1555                                 config->hca_attr.wqe_vlan_insert;
1556                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1557                         goto exit;
1558                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1559                         /* inline mode is defined by NIC vport context. */
1560                         if (!config->hca_attr.eth_virt)
1561                                 break;
1562                         switch (config->hca_attr.vport_inline_mode) {
1563                         case MLX5_INLINE_MODE_NONE:
1564                                 config->txq_inline_min =
1565                                         MLX5_INLINE_HSIZE_NONE;
1566                                 goto exit;
1567                         case MLX5_INLINE_MODE_L2:
1568                                 config->txq_inline_min =
1569                                         MLX5_INLINE_HSIZE_L2;
1570                                 goto exit;
1571                         case MLX5_INLINE_MODE_IP:
1572                                 config->txq_inline_min =
1573                                         MLX5_INLINE_HSIZE_L3;
1574                                 goto exit;
1575                         case MLX5_INLINE_MODE_TCP_UDP:
1576                                 config->txq_inline_min =
1577                                         MLX5_INLINE_HSIZE_L4;
1578                                 goto exit;
1579                         case MLX5_INLINE_MODE_INNER_L2:
1580                                 config->txq_inline_min =
1581                                         MLX5_INLINE_HSIZE_INNER_L2;
1582                                 goto exit;
1583                         case MLX5_INLINE_MODE_INNER_IP:
1584                                 config->txq_inline_min =
1585                                         MLX5_INLINE_HSIZE_INNER_L3;
1586                                 goto exit;
1587                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1588                                 config->txq_inline_min =
1589                                         MLX5_INLINE_HSIZE_INNER_L4;
1590                                 goto exit;
1591                         }
1592                 }
1593         }
1594         /*
1595          * We get here if we are unable to deduce
1596          * inline data size with DevX. Try PCI ID
1597          * to determine old NICs.
1598          */
1599         switch (spawn->pci_dev->id.device_id) {
1600         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1601         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1602         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1603         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1604                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1605                 config->hw_vlan_insert = 0;
1606                 break;
1607         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1608         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1609         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1610         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1611                 /*
1612                  * These NICs support VLAN insertion from WQE and
1613                  * report the wqe_vlan_insert flag. But there is the bug
1614                  * and PFC control may be broken, so disable feature.
1615                  */
1616                 config->hw_vlan_insert = 0;
1617                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1618                 break;
1619         default:
1620                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1621                 break;
1622         }
1623 exit:
1624         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1625 }
1626
1627 /**
1628  * Configures the metadata mask fields in the shared context.
1629  *
1630  * @param [in] dev
1631  *   Pointer to Ethernet device.
1632  */
1633 void
1634 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1635 {
1636         struct mlx5_priv *priv = dev->data->dev_private;
1637         struct mlx5_dev_ctx_shared *sh = priv->sh;
1638         uint32_t meta, mark, reg_c0;
1639
1640         reg_c0 = ~priv->vport_meta_mask;
1641         switch (priv->config.dv_xmeta_en) {
1642         case MLX5_XMETA_MODE_LEGACY:
1643                 meta = UINT32_MAX;
1644                 mark = MLX5_FLOW_MARK_MASK;
1645                 break;
1646         case MLX5_XMETA_MODE_META16:
1647                 meta = reg_c0 >> rte_bsf32(reg_c0);
1648                 mark = MLX5_FLOW_MARK_MASK;
1649                 break;
1650         case MLX5_XMETA_MODE_META32:
1651                 meta = UINT32_MAX;
1652                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1653                 break;
1654         default:
1655                 meta = 0;
1656                 mark = 0;
1657                 MLX5_ASSERT(false);
1658                 break;
1659         }
1660         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1661                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1662                                  sh->dv_mark_mask, mark);
1663         else
1664                 sh->dv_mark_mask = mark;
1665         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1666                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1667                                  sh->dv_meta_mask, meta);
1668         else
1669                 sh->dv_meta_mask = meta;
1670         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1671                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1672                                  sh->dv_meta_mask, reg_c0);
1673         else
1674                 sh->dv_regc0_mask = reg_c0;
1675         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1676         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1677         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1678         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1679 }
1680
1681 /**
1682  * Allocate page of door-bells and register it using DevX API.
1683  *
1684  * @param [in] dev
1685  *   Pointer to Ethernet device.
1686  *
1687  * @return
1688  *   Pointer to new page on success, NULL otherwise.
1689  */
1690 static struct mlx5_devx_dbr_page *
1691 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1692 {
1693         struct mlx5_priv *priv = dev->data->dev_private;
1694         struct mlx5_devx_dbr_page *page;
1695
1696         /* Allocate space for door-bell page and management data. */
1697         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1698                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1699         if (!page) {
1700                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1701                         dev->data->port_id);
1702                 return NULL;
1703         }
1704         /* Register allocated memory. */
1705         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1706                                               MLX5_DBR_PAGE_SIZE, 0);
1707         if (!page->umem) {
1708                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1709                         dev->data->port_id);
1710                 rte_free(page);
1711                 return NULL;
1712         }
1713         return page;
1714 }
1715
1716 /**
1717  * Find the next available door-bell, allocate new page if needed.
1718  *
1719  * @param [in] dev
1720  *   Pointer to Ethernet device.
1721  * @param [out] dbr_page
1722  *   Door-bell page containing the page data.
1723  *
1724  * @return
1725  *   Door-bell address offset on success, a negative error value otherwise.
1726  */
1727 int64_t
1728 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1729 {
1730         struct mlx5_priv *priv = dev->data->dev_private;
1731         struct mlx5_devx_dbr_page *page = NULL;
1732         uint32_t i, j;
1733
1734         LIST_FOREACH(page, &priv->dbrpgs, next)
1735                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1736                         break;
1737         if (!page) { /* No page with free door-bell exists. */
1738                 page = mlx5_alloc_dbr_page(dev);
1739                 if (!page) /* Failed to allocate new page. */
1740                         return (-1);
1741                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1742         }
1743         /* Loop to find bitmap part with clear bit. */
1744         for (i = 0;
1745              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1746              i++)
1747                 ; /* Empty. */
1748         /* Find the first clear bit. */
1749         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1750         j = rte_bsf64(~page->dbr_bitmap[i]);
1751         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1752         page->dbr_count++;
1753         *dbr_page = page;
1754         return (((i * 64) + j) * sizeof(uint64_t));
1755 }
1756
1757 /**
1758  * Release a door-bell record.
1759  *
1760  * @param [in] dev
1761  *   Pointer to Ethernet device.
1762  * @param [in] umem_id
1763  *   UMEM ID of page containing the door-bell record to release.
1764  * @param [in] offset
1765  *   Offset of door-bell record in page.
1766  *
1767  * @return
1768  *   0 on success, a negative error value otherwise.
1769  */
1770 int32_t
1771 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1772 {
1773         struct mlx5_priv *priv = dev->data->dev_private;
1774         struct mlx5_devx_dbr_page *page = NULL;
1775         int ret = 0;
1776
1777         LIST_FOREACH(page, &priv->dbrpgs, next)
1778                 /* Find the page this address belongs to. */
1779                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1780                         break;
1781         if (!page)
1782                 return -EINVAL;
1783         page->dbr_count--;
1784         if (!page->dbr_count) {
1785                 /* Page not used, free it and remove from list. */
1786                 LIST_REMOVE(page, next);
1787                 if (page->umem)
1788                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1789                 rte_free(page);
1790         } else {
1791                 /* Mark in bitmap that this door-bell is not in use. */
1792                 offset /= MLX5_DBR_SIZE;
1793                 int i = offset / 64;
1794                 int j = offset % 64;
1795
1796                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1797         }
1798         return ret;
1799 }
1800
1801 int
1802 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1803 {
1804         static const char *const dynf_names[] = {
1805                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1806                 RTE_MBUF_DYNFLAG_METADATA_NAME
1807         };
1808         unsigned int i;
1809
1810         if (n < RTE_DIM(dynf_names))
1811                 return -ENOMEM;
1812         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1813                 if (names[i] == NULL)
1814                         return -EINVAL;
1815                 strcpy(names[i], dynf_names[i]);
1816         }
1817         return RTE_DIM(dynf_names);
1818 }
1819
1820 /**
1821  * Comparison callback to sort device data.
1822  *
1823  * This is meant to be used with qsort().
1824  *
1825  * @param a[in]
1826  *   Pointer to pointer to first data object.
1827  * @param b[in]
1828  *   Pointer to pointer to second data object.
1829  *
1830  * @return
1831  *   0 if both objects are equal, less than 0 if the first argument is less
1832  *   than the second, greater than 0 otherwise.
1833  */
1834 int
1835 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1836                               struct mlx5_dev_config *config)
1837 {
1838         struct mlx5_dev_ctx_shared *sh = priv->sh;
1839         struct mlx5_dev_config *sh_conf = NULL;
1840         uint16_t port_id;
1841
1842         MLX5_ASSERT(sh);
1843         /* Nothing to compare for the single/first device. */
1844         if (sh->refcnt == 1)
1845                 return 0;
1846         /* Find the device with shared context. */
1847         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1848                 struct mlx5_priv *opriv =
1849                         rte_eth_devices[port_id].data->dev_private;
1850
1851                 if (opriv && opriv != priv && opriv->sh == sh) {
1852                         sh_conf = &opriv->config;
1853                         break;
1854                 }
1855         }
1856         if (!sh_conf)
1857                 return 0;
1858         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1859                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1860                              " for shared %s context", sh->ibdev_name);
1861                 rte_errno = EINVAL;
1862                 return rte_errno;
1863         }
1864         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1865                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1866                              " for shared %s context", sh->ibdev_name);
1867                 rte_errno = EINVAL;
1868                 return rte_errno;
1869         }
1870         return 0;
1871 }
1872
1873 /**
1874  * Look for the ethernet device belonging to mlx5 driver.
1875  *
1876  * @param[in] port_id
1877  *   port_id to start looking for device.
1878  * @param[in] pci_dev
1879  *   Pointer to the hint PCI device. When device is being probed
1880  *   the its siblings (master and preceding representors might
1881  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1882  *   is not completed yet, for this case match on hint PCI
1883  *   device may be used to detect sibling device.
1884  *
1885  * @return
1886  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1887  */
1888 uint16_t
1889 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1890 {
1891         while (port_id < RTE_MAX_ETHPORTS) {
1892                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1893
1894                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1895                     dev->device &&
1896                     (dev->device == &pci_dev->device ||
1897                      (dev->device->driver &&
1898                      dev->device->driver->name &&
1899                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1900                         break;
1901                 port_id++;
1902         }
1903         if (port_id >= RTE_MAX_ETHPORTS)
1904                 return RTE_MAX_ETHPORTS;
1905         return port_id;
1906 }
1907
1908 /**
1909  * DPDK callback to remove a PCI device.
1910  *
1911  * This function removes all Ethernet devices belong to a given PCI device.
1912  *
1913  * @param[in] pci_dev
1914  *   Pointer to the PCI device.
1915  *
1916  * @return
1917  *   0 on success, the function cannot fail.
1918  */
1919 static int
1920 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1921 {
1922         uint16_t port_id;
1923
1924         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1925                 /*
1926                  * mlx5_dev_close() is not registered to secondary process,
1927                  * call the close function explicitly for secondary process.
1928                  */
1929                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1930                         mlx5_dev_close(&rte_eth_devices[port_id]);
1931                 else
1932                         rte_eth_dev_close(port_id);
1933         }
1934         return 0;
1935 }
1936
1937 static const struct rte_pci_id mlx5_pci_id_map[] = {
1938         {
1939                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1940                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1941         },
1942         {
1943                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1944                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1945         },
1946         {
1947                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1948                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1949         },
1950         {
1951                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1952                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1953         },
1954         {
1955                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1956                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1957         },
1958         {
1959                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1960                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1961         },
1962         {
1963                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1964                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1965         },
1966         {
1967                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1968                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1969         },
1970         {
1971                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1972                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1973         },
1974         {
1975                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1976                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1977         },
1978         {
1979                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1980                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1981         },
1982         {
1983                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1984                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1985         },
1986         {
1987                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1988                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1989         },
1990         {
1991                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1993         },
1994         {
1995                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1997         },
1998         {
1999                 .vendor_id = 0
2000         }
2001 };
2002
2003 struct rte_pci_driver mlx5_driver = {
2004         .driver = {
2005                 .name = MLX5_DRIVER_NAME
2006         },
2007         .id_table = mlx5_pci_id_map,
2008         .probe = mlx5_os_pci_probe,
2009         .remove = mlx5_pci_remove,
2010         .dma_map = mlx5_dma_map,
2011         .dma_unmap = mlx5_dma_unmap,
2012         .drv_flags = PCI_DRV_FLAGS,
2013 };
2014
2015 /**
2016  * Driver initialization routine.
2017  */
2018 RTE_INIT(rte_mlx5_pmd_init)
2019 {
2020         /* Initialize driver log type. */
2021         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2022         if (mlx5_logtype >= 0)
2023                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2024
2025         /* Build the static tables for Verbs conversion. */
2026         mlx5_set_ptype_table();
2027         mlx5_set_cksum_table();
2028         mlx5_set_swp_types_table();
2029         if (mlx5_glue)
2030                 rte_pci_register(&mlx5_driver);
2031 }
2032
2033 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2034 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2035 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");