1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
16 #include <linux/netlink.h>
17 #include <linux/rtnetlink.h>
20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
22 #pragma GCC diagnostic ignored "-Wpedantic"
24 #include <infiniband/verbs.h>
26 #pragma GCC diagnostic error "-Wpedantic"
29 #include <rte_malloc.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
33 #include <rte_bus_pci.h>
34 #include <rte_common.h>
35 #include <rte_config.h>
36 #include <rte_eal_memconfig.h>
37 #include <rte_kvargs.h>
38 #include <rte_rwlock.h>
39 #include <rte_spinlock.h>
40 #include <rte_string_fns.h>
43 #include "mlx5_utils.h"
44 #include "mlx5_rxtx.h"
45 #include "mlx5_autoconf.h"
46 #include "mlx5_defs.h"
47 #include "mlx5_glue.h"
49 #include "mlx5_flow.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable Multi-Packet Rx queue. */
58 #define MLX5_RX_MPRQ_EN "mprq_en"
60 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
61 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
69 /* Device parameter to configure inline send. */
70 #define MLX5_TXQ_INLINE "txq_inline"
73 * Device parameter to configure the number of TX queues threshold for
74 * enabling inline send.
76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
79 * Device parameter to configure the number of TX queues threshold for
80 * enabling vectorized Tx.
82 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
84 /* Device parameter to enable multi-packet send WQEs. */
85 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
87 /* Device parameter to include 2 dsegs in the title WQEBB. */
88 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
90 /* Device parameter to limit the size of inlining packet. */
91 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
93 /* Device parameter to enable hardware Tx vector. */
94 #define MLX5_TX_VEC_EN "tx_vec_en"
96 /* Device parameter to enable hardware Rx vector. */
97 #define MLX5_RX_VEC_EN "rx_vec_en"
99 /* Allow L3 VXLAN flow creation. */
100 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
102 /* Activate DV flow steering. */
103 #define MLX5_DV_FLOW_EN "dv_flow_en"
105 /* Activate Netlink support in VF mode. */
106 #define MLX5_VF_NL_EN "vf_nl_en"
108 /* Select port representors to instantiate. */
109 #define MLX5_REPRESENTOR "representor"
111 #ifndef HAVE_IBV_MLX5_MOD_MPW
112 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
113 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
116 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
117 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
120 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
122 /* Shared memory between primary and secondary processes. */
123 struct mlx5_shared_data *mlx5_shared_data;
125 /* Spinlock for mlx5_shared_data allocation. */
126 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
128 /** Driver-specific log messages type. */
132 * Prepare shared data between primary and secondary process.
135 mlx5_prepare_shared_data(void)
137 const struct rte_memzone *mz;
139 rte_spinlock_lock(&mlx5_shared_data_lock);
140 if (mlx5_shared_data == NULL) {
141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
142 /* Allocate shared memory. */
143 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
144 sizeof(*mlx5_shared_data),
147 /* Lookup allocated shared memory. */
148 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
151 rte_panic("Cannot allocate mlx5 shared data\n");
152 mlx5_shared_data = mz->addr;
153 /* Initialize shared data. */
154 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
155 LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
156 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
158 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
159 mlx5_mr_mem_event_cb, NULL);
161 rte_spinlock_unlock(&mlx5_shared_data_lock);
165 * Retrieve integer value from environment variable.
168 * Environment variable name.
171 * Integer value, 0 if the variable is not set.
174 mlx5_getenv_int(const char *name)
176 const char *val = getenv(name);
184 * Verbs callback to allocate a memory. This function should allocate the space
185 * according to the size provided residing inside a huge page.
186 * Please note that all allocation must respect the alignment from libmlx5
187 * (i.e. currently sysconf(_SC_PAGESIZE)).
190 * The size in bytes of the memory to allocate.
192 * A pointer to the callback data.
195 * Allocated buffer, NULL otherwise and rte_errno is set.
198 mlx5_alloc_verbs_buf(size_t size, void *data)
200 struct priv *priv = data;
202 size_t alignment = sysconf(_SC_PAGESIZE);
203 unsigned int socket = SOCKET_ID_ANY;
205 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
206 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
208 socket = ctrl->socket;
209 } else if (priv->verbs_alloc_ctx.type ==
210 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
211 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
213 socket = ctrl->socket;
215 assert(data != NULL);
216 ret = rte_malloc_socket(__func__, size, alignment, socket);
223 * Verbs callback to free a memory.
226 * A pointer to the memory to free.
228 * A pointer to the callback data.
231 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
233 assert(data != NULL);
238 * DPDK callback to close the device.
240 * Destroy all queues and objects, free memory.
243 * Pointer to Ethernet device structure.
246 mlx5_dev_close(struct rte_eth_dev *dev)
248 struct priv *priv = dev->data->dev_private;
252 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
254 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
255 /* In case mlx5_dev_stop() has not been called. */
256 mlx5_dev_interrupt_handler_uninstall(dev);
257 mlx5_traffic_disable(dev);
258 mlx5_flow_flush(dev, NULL);
259 /* Prevent crashes when queues are still in use. */
260 dev->rx_pkt_burst = removed_rx_burst;
261 dev->tx_pkt_burst = removed_tx_burst;
262 if (priv->rxqs != NULL) {
263 /* XXX race condition if mlx5_rx_burst() is still running. */
265 for (i = 0; (i != priv->rxqs_n); ++i)
266 mlx5_rxq_release(dev, i);
270 if (priv->txqs != NULL) {
271 /* XXX race condition if mlx5_tx_burst() is still running. */
273 for (i = 0; (i != priv->txqs_n); ++i)
274 mlx5_txq_release(dev, i);
278 mlx5_mprq_free_mp(dev);
279 mlx5_mr_release(dev);
280 if (priv->pd != NULL) {
281 assert(priv->ctx != NULL);
282 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
283 claim_zero(mlx5_glue->close_device(priv->ctx));
285 assert(priv->ctx == NULL);
286 if (priv->rss_conf.rss_key != NULL)
287 rte_free(priv->rss_conf.rss_key);
288 if (priv->reta_idx != NULL)
289 rte_free(priv->reta_idx);
290 if (priv->primary_socket)
291 mlx5_socket_uninit(dev);
293 mlx5_nl_mac_addr_flush(dev);
294 if (priv->nl_socket_route >= 0)
295 close(priv->nl_socket_route);
296 if (priv->nl_socket_rdma >= 0)
297 close(priv->nl_socket_rdma);
298 if (priv->tcf_context)
299 mlx5_flow_tcf_context_destroy(priv->tcf_context);
300 ret = mlx5_hrxq_ibv_verify(dev);
302 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
304 ret = mlx5_ind_table_ibv_verify(dev);
306 DRV_LOG(WARNING, "port %u some indirection table still remain",
308 ret = mlx5_rxq_ibv_verify(dev);
310 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
312 ret = mlx5_rxq_verify(dev);
314 DRV_LOG(WARNING, "port %u some Rx queues still remain",
316 ret = mlx5_txq_ibv_verify(dev);
318 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
320 ret = mlx5_txq_verify(dev);
322 DRV_LOG(WARNING, "port %u some Tx queues still remain",
324 ret = mlx5_flow_verify(dev);
326 DRV_LOG(WARNING, "port %u some flows still remain",
328 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
330 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0);
333 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i);
336 rte_eth_devices[port_id[i]].data->dev_private;
339 opriv->domain_id != priv->domain_id ||
340 &rte_eth_devices[port_id[i]] == dev)
345 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
347 memset(priv, 0, sizeof(*priv));
348 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
350 * Reset mac_addrs to NULL such that it is not freed as part of
351 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
352 * it is freed when dev_private is freed.
354 dev->data->mac_addrs = NULL;
357 const struct eth_dev_ops mlx5_dev_ops = {
358 .dev_configure = mlx5_dev_configure,
359 .dev_start = mlx5_dev_start,
360 .dev_stop = mlx5_dev_stop,
361 .dev_set_link_down = mlx5_set_link_down,
362 .dev_set_link_up = mlx5_set_link_up,
363 .dev_close = mlx5_dev_close,
364 .promiscuous_enable = mlx5_promiscuous_enable,
365 .promiscuous_disable = mlx5_promiscuous_disable,
366 .allmulticast_enable = mlx5_allmulticast_enable,
367 .allmulticast_disable = mlx5_allmulticast_disable,
368 .link_update = mlx5_link_update,
369 .stats_get = mlx5_stats_get,
370 .stats_reset = mlx5_stats_reset,
371 .xstats_get = mlx5_xstats_get,
372 .xstats_reset = mlx5_xstats_reset,
373 .xstats_get_names = mlx5_xstats_get_names,
374 .dev_infos_get = mlx5_dev_infos_get,
375 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
376 .vlan_filter_set = mlx5_vlan_filter_set,
377 .rx_queue_setup = mlx5_rx_queue_setup,
378 .tx_queue_setup = mlx5_tx_queue_setup,
379 .rx_queue_release = mlx5_rx_queue_release,
380 .tx_queue_release = mlx5_tx_queue_release,
381 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
382 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
383 .mac_addr_remove = mlx5_mac_addr_remove,
384 .mac_addr_add = mlx5_mac_addr_add,
385 .mac_addr_set = mlx5_mac_addr_set,
386 .set_mc_addr_list = mlx5_set_mc_addr_list,
387 .mtu_set = mlx5_dev_set_mtu,
388 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
389 .vlan_offload_set = mlx5_vlan_offload_set,
390 .reta_update = mlx5_dev_rss_reta_update,
391 .reta_query = mlx5_dev_rss_reta_query,
392 .rss_hash_update = mlx5_rss_hash_update,
393 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
394 .filter_ctrl = mlx5_dev_filter_ctrl,
395 .rx_descriptor_status = mlx5_rx_descriptor_status,
396 .tx_descriptor_status = mlx5_tx_descriptor_status,
397 .rx_queue_count = mlx5_rx_queue_count,
398 .rx_queue_intr_enable = mlx5_rx_intr_enable,
399 .rx_queue_intr_disable = mlx5_rx_intr_disable,
400 .is_removed = mlx5_is_removed,
403 static const struct eth_dev_ops mlx5_dev_sec_ops = {
404 .stats_get = mlx5_stats_get,
405 .stats_reset = mlx5_stats_reset,
406 .xstats_get = mlx5_xstats_get,
407 .xstats_reset = mlx5_xstats_reset,
408 .xstats_get_names = mlx5_xstats_get_names,
409 .dev_infos_get = mlx5_dev_infos_get,
410 .rx_descriptor_status = mlx5_rx_descriptor_status,
411 .tx_descriptor_status = mlx5_tx_descriptor_status,
414 /* Available operators in flow isolated mode. */
415 const struct eth_dev_ops mlx5_dev_ops_isolate = {
416 .dev_configure = mlx5_dev_configure,
417 .dev_start = mlx5_dev_start,
418 .dev_stop = mlx5_dev_stop,
419 .dev_set_link_down = mlx5_set_link_down,
420 .dev_set_link_up = mlx5_set_link_up,
421 .dev_close = mlx5_dev_close,
422 .promiscuous_enable = mlx5_promiscuous_enable,
423 .promiscuous_disable = mlx5_promiscuous_disable,
424 .allmulticast_enable = mlx5_allmulticast_enable,
425 .allmulticast_disable = mlx5_allmulticast_disable,
426 .link_update = mlx5_link_update,
427 .stats_get = mlx5_stats_get,
428 .stats_reset = mlx5_stats_reset,
429 .xstats_get = mlx5_xstats_get,
430 .xstats_reset = mlx5_xstats_reset,
431 .xstats_get_names = mlx5_xstats_get_names,
432 .dev_infos_get = mlx5_dev_infos_get,
433 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
434 .vlan_filter_set = mlx5_vlan_filter_set,
435 .rx_queue_setup = mlx5_rx_queue_setup,
436 .tx_queue_setup = mlx5_tx_queue_setup,
437 .rx_queue_release = mlx5_rx_queue_release,
438 .tx_queue_release = mlx5_tx_queue_release,
439 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
440 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
441 .mac_addr_remove = mlx5_mac_addr_remove,
442 .mac_addr_add = mlx5_mac_addr_add,
443 .mac_addr_set = mlx5_mac_addr_set,
444 .set_mc_addr_list = mlx5_set_mc_addr_list,
445 .mtu_set = mlx5_dev_set_mtu,
446 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
447 .vlan_offload_set = mlx5_vlan_offload_set,
448 .filter_ctrl = mlx5_dev_filter_ctrl,
449 .rx_descriptor_status = mlx5_rx_descriptor_status,
450 .tx_descriptor_status = mlx5_tx_descriptor_status,
451 .rx_queue_intr_enable = mlx5_rx_intr_enable,
452 .rx_queue_intr_disable = mlx5_rx_intr_disable,
453 .is_removed = mlx5_is_removed,
457 * Verify and store value for device argument.
460 * Key argument to verify.
462 * Value associated with key.
467 * 0 on success, a negative errno value otherwise and rte_errno is set.
470 mlx5_args_check(const char *key, const char *val, void *opaque)
472 struct mlx5_dev_config *config = opaque;
475 /* No-op, port representors are processed in mlx5_dev_spawn(). */
476 if (!strcmp(MLX5_REPRESENTOR, key))
479 tmp = strtoul(val, NULL, 0);
482 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
485 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
486 config->cqe_comp = !!tmp;
487 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
488 config->cqe_pad = !!tmp;
489 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
490 config->mprq.enabled = !!tmp;
491 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
492 config->mprq.stride_num_n = tmp;
493 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
494 config->mprq.max_memcpy_len = tmp;
495 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
496 config->mprq.min_rxqs_num = tmp;
497 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
498 config->txq_inline = tmp;
499 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
500 config->txqs_inline = tmp;
501 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
502 config->txqs_vec = tmp;
503 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
505 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
506 config->mpw_hdr_dseg = !!tmp;
507 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
508 config->inline_max_packet_sz = tmp;
509 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
510 config->tx_vec_en = !!tmp;
511 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
512 config->rx_vec_en = !!tmp;
513 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
514 config->l3_vxlan_en = !!tmp;
515 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
516 config->vf_nl_en = !!tmp;
517 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
518 config->dv_flow_en = !!tmp;
520 DRV_LOG(WARNING, "%s: unknown parameter", key);
528 * Parse device parameters.
531 * Pointer to device configuration structure.
533 * Device arguments structure.
536 * 0 on success, a negative errno value otherwise and rte_errno is set.
539 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
541 const char **params = (const char *[]){
542 MLX5_RXQ_CQE_COMP_EN,
545 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
546 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
549 MLX5_TXQS_MIN_INLINE,
552 MLX5_TXQ_MPW_HDR_DSEG_EN,
553 MLX5_TXQ_MAX_INLINE_LEN,
562 struct rte_kvargs *kvlist;
568 /* Following UGLY cast is done to pass checkpatch. */
569 kvlist = rte_kvargs_parse(devargs->args, params);
572 /* Process parameters. */
573 for (i = 0; (params[i] != NULL); ++i) {
574 if (rte_kvargs_count(kvlist, params[i])) {
575 ret = rte_kvargs_process(kvlist, params[i],
576 mlx5_args_check, config);
579 rte_kvargs_free(kvlist);
584 rte_kvargs_free(kvlist);
588 static struct rte_pci_driver mlx5_driver;
591 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
592 * local resource used by both primary and secondary to avoid duplicate
594 * The space has to be available on both primary and secondary process,
595 * TXQ UAR maps to this area using fixed mmap w/o double check.
597 static void *uar_base;
600 find_lower_va_bound(const struct rte_memseg_list *msl,
601 const struct rte_memseg *ms, void *arg)
610 *addr = RTE_MIN(*addr, ms->addr);
616 * Reserve UAR address space for primary process.
619 * Pointer to Ethernet device.
622 * 0 on success, a negative errno value otherwise and rte_errno is set.
625 mlx5_uar_init_primary(struct rte_eth_dev *dev)
627 struct priv *priv = dev->data->dev_private;
628 void *addr = (void *)0;
630 if (uar_base) { /* UAR address space mapped. */
631 priv->uar_base = uar_base;
634 /* find out lower bound of hugepage segments */
635 rte_memseg_walk(find_lower_va_bound, &addr);
637 /* keep distance to hugepages to minimize potential conflicts. */
638 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE));
639 /* anonymous mmap, no real memory consumption. */
640 addr = mmap(addr, MLX5_UAR_SIZE,
641 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
642 if (addr == MAP_FAILED) {
644 "port %u failed to reserve UAR address space, please"
645 " adjust MLX5_UAR_SIZE or try --base-virtaddr",
650 /* Accept either same addr or a new addr returned from mmap if target
653 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
654 dev->data->port_id, addr);
655 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
656 uar_base = addr; /* process local, don't reserve again. */
661 * Reserve UAR address space for secondary process, align with
665 * Pointer to Ethernet device.
668 * 0 on success, a negative errno value otherwise and rte_errno is set.
671 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
673 struct priv *priv = dev->data->dev_private;
676 assert(priv->uar_base);
677 if (uar_base) { /* already reserved. */
678 assert(uar_base == priv->uar_base);
681 /* anonymous mmap, no real memory consumption. */
682 addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
683 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
684 if (addr == MAP_FAILED) {
685 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
686 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
690 if (priv->uar_base != addr) {
692 "port %u UAR address %p size %llu occupied, please"
693 " adjust MLX5_UAR_OFFSET or try EAL parameter"
695 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
699 uar_base = addr; /* process local, don't reserve again */
700 DRV_LOG(INFO, "port %u reserved UAR address space: %p",
701 dev->data->port_id, addr);
706 * Spawn an Ethernet device from Verbs information.
709 * Backing DPDK device.
713 * Device configuration parameters.
714 * @param[in] switch_info
715 * Switch properties of Ethernet device.
718 * A valid Ethernet device object on success, NULL otherwise and rte_errno
719 * is set. The following errors are defined:
721 * EBUSY: device is not supposed to be spawned.
722 * EEXIST: device is already spawned
724 static struct rte_eth_dev *
725 mlx5_dev_spawn(struct rte_device *dpdk_dev,
726 struct ibv_device *ibv_dev,
727 struct mlx5_dev_config config,
728 const struct mlx5_switch_info *switch_info)
730 struct ibv_context *ctx = NULL;
731 struct ibv_device_attr_ex attr;
732 struct ibv_port_attr port_attr;
733 struct ibv_pd *pd = NULL;
734 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
735 struct rte_eth_dev *eth_dev = NULL;
736 struct priv *priv = NULL;
739 unsigned int cqe_comp;
740 unsigned int cqe_pad = 0;
741 unsigned int tunnel_en = 0;
742 unsigned int mpls_en = 0;
743 unsigned int swp = 0;
744 unsigned int mprq = 0;
745 unsigned int mprq_min_stride_size_n = 0;
746 unsigned int mprq_max_stride_size_n = 0;
747 unsigned int mprq_min_stride_num_n = 0;
748 unsigned int mprq_max_stride_num_n = 0;
749 struct ether_addr mac;
750 char name[RTE_ETH_NAME_MAX_LEN];
751 int own_domain_id = 0;
755 /* Determine if this port representor is supposed to be spawned. */
756 if (switch_info->representor && dpdk_dev->devargs) {
757 struct rte_eth_devargs eth_da;
759 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
762 DRV_LOG(ERR, "failed to process device arguments: %s",
763 strerror(rte_errno));
766 for (i = 0; i < eth_da.nb_representor_ports; ++i)
767 if (eth_da.representor_ports[i] ==
768 (uint16_t)switch_info->port_name)
770 if (i == eth_da.nb_representor_ports) {
775 /* Build device name. */
776 if (!switch_info->representor)
777 rte_strlcpy(name, dpdk_dev->name, sizeof(name));
779 snprintf(name, sizeof(name), "%s_representor_%u",
780 dpdk_dev->name, switch_info->port_name);
781 /* check if the device is already spawned */
782 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
786 /* Prepare shared data between primary and secondary process. */
787 mlx5_prepare_shared_data();
789 ctx = mlx5_glue->dv_open_device(ibv_dev);
792 DRV_LOG(DEBUG, "DEVX is supported");
794 ctx = mlx5_glue->open_device(ibv_dev);
796 rte_errno = errno ? errno : ENODEV;
800 #ifdef HAVE_IBV_MLX5_MOD_SWP
801 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
804 * Multi-packet send is supported by ConnectX-4 Lx PF as well
805 * as all ConnectX-5 devices.
807 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
808 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
810 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
811 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
813 mlx5_glue->dv_query_device(ctx, &dv_attr);
814 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
815 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
816 DRV_LOG(DEBUG, "enhanced MPW is supported");
817 mps = MLX5_MPW_ENHANCED;
819 DRV_LOG(DEBUG, "MPW is supported");
823 DRV_LOG(DEBUG, "MPW isn't supported");
824 mps = MLX5_MPW_DISABLED;
826 #ifdef HAVE_IBV_MLX5_MOD_SWP
827 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
828 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
829 DRV_LOG(DEBUG, "SWP support: %u", swp);
832 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
833 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
834 struct mlx5dv_striding_rq_caps mprq_caps =
835 dv_attr.striding_rq_caps;
837 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
838 mprq_caps.min_single_stride_log_num_of_bytes);
839 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
840 mprq_caps.max_single_stride_log_num_of_bytes);
841 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
842 mprq_caps.min_single_wqe_log_num_of_strides);
843 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
844 mprq_caps.max_single_wqe_log_num_of_strides);
845 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
846 mprq_caps.supported_qpts);
847 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
849 mprq_min_stride_size_n =
850 mprq_caps.min_single_stride_log_num_of_bytes;
851 mprq_max_stride_size_n =
852 mprq_caps.max_single_stride_log_num_of_bytes;
853 mprq_min_stride_num_n =
854 mprq_caps.min_single_wqe_log_num_of_strides;
855 mprq_max_stride_num_n =
856 mprq_caps.max_single_wqe_log_num_of_strides;
857 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
858 mprq_min_stride_num_n);
861 if (RTE_CACHE_LINE_SIZE == 128 &&
862 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
866 config.cqe_comp = cqe_comp;
867 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
868 /* Whether device supports 128B Rx CQE padding. */
869 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
870 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
872 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
873 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
874 tunnel_en = ((dv_attr.tunnel_offloads_caps &
875 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
876 (dv_attr.tunnel_offloads_caps &
877 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
879 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
880 tunnel_en ? "" : "not ");
883 "tunnel offloading disabled due to old OFED/rdma-core version");
885 config.tunnel_en = tunnel_en;
886 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
887 mpls_en = ((dv_attr.tunnel_offloads_caps &
888 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
889 (dv_attr.tunnel_offloads_caps &
890 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
891 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
892 mpls_en ? "" : "not ");
894 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
895 " old OFED/rdma-core version or firmware configuration");
897 config.mpls_en = mpls_en;
898 err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
900 DEBUG("ibv_query_device_ex() failed");
903 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
904 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
905 eth_dev = rte_eth_dev_attach_secondary(name);
906 if (eth_dev == NULL) {
907 DRV_LOG(ERR, "can not attach rte ethdev");
912 eth_dev->device = dpdk_dev;
913 eth_dev->dev_ops = &mlx5_dev_sec_ops;
914 err = mlx5_uar_init_secondary(eth_dev);
919 /* Receive command fd from primary process */
920 err = mlx5_socket_connect(eth_dev);
925 /* Remap UAR for Tx queues. */
926 err = mlx5_tx_uar_remap(eth_dev, err);
932 * Ethdev pointer is still required as input since
933 * the primary device is not accessible from the
936 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
937 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
938 claim_zero(mlx5_glue->close_device(ctx));
941 /* Check port status. */
942 err = mlx5_glue->query_port(ctx, 1, &port_attr);
944 DRV_LOG(ERR, "port query failed: %s", strerror(err));
947 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
948 DRV_LOG(ERR, "port is not configured in Ethernet mode");
952 if (port_attr.state != IBV_PORT_ACTIVE)
953 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
954 mlx5_glue->port_state_str(port_attr.state),
956 /* Allocate protection domain. */
957 pd = mlx5_glue->alloc_pd(ctx);
959 DRV_LOG(ERR, "PD allocation failure");
963 priv = rte_zmalloc("ethdev private structure",
965 RTE_CACHE_LINE_SIZE);
967 DRV_LOG(ERR, "priv allocation failure");
972 strncpy(priv->ibdev_name, priv->ctx->device->name,
973 sizeof(priv->ibdev_name));
974 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
975 sizeof(priv->ibdev_path));
976 priv->device_attr = attr;
978 priv->mtu = ETHER_MTU;
980 /* Initialize UAR access locks for 32bit implementations. */
981 rte_spinlock_init(&priv->uar_lock_cq);
982 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
983 rte_spinlock_init(&priv->uar_lock[i]);
985 /* Some internal functions rely on Netlink sockets, open them now. */
986 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
987 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
989 priv->representor = !!switch_info->representor;
990 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
991 priv->representor_id =
992 switch_info->representor ? switch_info->port_name : -1;
994 * Look for sibling devices in order to reuse their switch domain
995 * if any, otherwise allocate one.
997 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0);
1001 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i);
1003 const struct priv *opriv =
1004 rte_eth_devices[port_id[i]].data->dev_private;
1008 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
1010 priv->domain_id = opriv->domain_id;
1014 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1015 err = rte_eth_switch_domain_alloc(&priv->domain_id);
1018 DRV_LOG(ERR, "unable to allocate switch domain: %s",
1019 strerror(rte_errno));
1024 err = mlx5_args(&config, dpdk_dev->devargs);
1027 DRV_LOG(ERR, "failed to process device arguments: %s",
1028 strerror(rte_errno));
1031 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM);
1032 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
1033 (config.hw_csum ? "" : "not "));
1034 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
1035 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
1036 DRV_LOG(DEBUG, "counters are not supported");
1038 #ifndef HAVE_IBV_FLOW_DV_SUPPORT
1039 if (config.dv_flow_en) {
1040 DRV_LOG(WARNING, "DV flow is not supported");
1041 config.dv_flow_en = 0;
1044 config.ind_table_max_size =
1045 attr.rss_caps.max_rwq_indirection_table_size;
1047 * Remove this check once DPDK supports larger/variable
1048 * indirection tables.
1050 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
1051 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1052 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
1053 config.ind_table_max_size);
1054 config.hw_vlan_strip = !!(attr.raw_packet_caps &
1055 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1056 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
1057 (config.hw_vlan_strip ? "" : "not "));
1058 config.hw_fcs_strip = !!(attr.raw_packet_caps &
1059 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1060 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
1061 (config.hw_fcs_strip ? "" : "not "));
1062 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
1063 config.hw_padding = !!attr.rx_pad_end_addr_align;
1065 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported",
1066 (config.hw_padding ? "" : "not "));
1067 config.tso = (attr.tso_caps.max_tso > 0 &&
1068 (attr.tso_caps.supported_qpts &
1069 (1 << IBV_QPT_RAW_PACKET)));
1071 config.tso_max_payload_sz = attr.tso_caps.max_tso;
1073 * MPW is disabled by default, while the Enhanced MPW is enabled
1076 if (config.mps == MLX5_ARG_UNSET)
1077 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1080 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1081 DRV_LOG(INFO, "%sMPS is %s",
1082 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
1083 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
1084 if (config.cqe_comp && !cqe_comp) {
1085 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1086 config.cqe_comp = 0;
1088 if (config.cqe_pad && !cqe_pad) {
1089 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1091 } else if (config.cqe_pad) {
1092 DRV_LOG(INFO, "Rx CQE padding is enabled");
1094 if (config.mprq.enabled && mprq) {
1095 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1096 config.mprq.stride_num_n < mprq_min_stride_num_n) {
1097 config.mprq.stride_num_n =
1098 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1099 mprq_min_stride_num_n);
1101 "the number of strides"
1102 " for Multi-Packet RQ is out of range,"
1103 " setting default value (%u)",
1104 1 << config.mprq.stride_num_n);
1106 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1107 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1108 } else if (config.mprq.enabled && !mprq) {
1109 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1110 config.mprq.enabled = 0;
1112 eth_dev = rte_eth_dev_allocate(name);
1113 if (eth_dev == NULL) {
1114 DRV_LOG(ERR, "can not allocate rte ethdev");
1118 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
1119 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1120 if (priv->representor) {
1121 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1122 eth_dev->data->representor_id = priv->representor_id;
1124 eth_dev->data->dev_private = priv;
1125 priv->dev_data = eth_dev->data;
1126 eth_dev->data->mac_addrs = priv->mac;
1127 eth_dev->device = dpdk_dev;
1128 err = mlx5_uar_init_primary(eth_dev);
1133 /* Configure the first MAC address by default. */
1134 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1136 "port %u cannot get MAC address, is mlx5_en"
1137 " loaded? (errno: %s)",
1138 eth_dev->data->port_id, strerror(rte_errno));
1143 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1144 eth_dev->data->port_id,
1145 mac.addr_bytes[0], mac.addr_bytes[1],
1146 mac.addr_bytes[2], mac.addr_bytes[3],
1147 mac.addr_bytes[4], mac.addr_bytes[5]);
1150 char ifname[IF_NAMESIZE];
1152 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1153 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1154 eth_dev->data->port_id, ifname);
1156 DRV_LOG(DEBUG, "port %u ifname is unknown",
1157 eth_dev->data->port_id);
1160 /* Get actual MTU if possible. */
1161 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1166 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1168 /* Initialize burst functions to prevent crashes before link-up. */
1169 eth_dev->rx_pkt_burst = removed_rx_burst;
1170 eth_dev->tx_pkt_burst = removed_tx_burst;
1171 eth_dev->dev_ops = &mlx5_dev_ops;
1172 /* Register MAC address. */
1173 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1174 if (config.vf && config.vf_nl_en)
1175 mlx5_nl_mac_addr_sync(eth_dev);
1176 priv->tcf_context = mlx5_flow_tcf_context_create();
1177 if (!priv->tcf_context) {
1180 "flow rules relying on switch offloads will not be"
1181 " supported: cannot open libmnl socket: %s",
1182 strerror(rte_errno));
1184 struct rte_flow_error error;
1185 unsigned int ifindex = mlx5_ifindex(eth_dev);
1190 "cannot retrieve network interface index";
1192 err = mlx5_flow_tcf_init(priv->tcf_context,
1197 "flow rules relying on switch offloads will"
1198 " not be supported: %s: %s",
1199 error.message, strerror(rte_errno));
1200 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1201 priv->tcf_context = NULL;
1204 TAILQ_INIT(&priv->flows);
1205 TAILQ_INIT(&priv->ctrl_flows);
1206 /* Hint libmlx5 to use PMD allocator for data plane resources */
1207 struct mlx5dv_ctx_allocators alctr = {
1208 .alloc = &mlx5_alloc_verbs_buf,
1209 .free = &mlx5_free_verbs_buf,
1212 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1213 (void *)((uintptr_t)&alctr));
1214 /* Bring Ethernet device up. */
1215 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1216 eth_dev->data->port_id);
1217 mlx5_set_link_up(eth_dev);
1219 * Even though the interrupt handler is not installed yet,
1220 * interrupts will still trigger on the asyn_fd from
1221 * Verbs context returned by ibv_open_device().
1223 mlx5_link_update(eth_dev, 0);
1224 /* Store device configuration on private structure. */
1225 priv->config = config;
1226 /* Supported Verbs flow priority number detection. */
1227 err = mlx5_flow_discover_priorities(eth_dev);
1230 priv->config.flow_prio = err;
1232 * Once the device is added to the list of memory event
1233 * callback, its global MR cache table cannot be expanded
1234 * on the fly because of deadlock. If it overflows, lookup
1235 * should be done by searching MR list linearly, which is slow.
1237 err = mlx5_mr_btree_init(&priv->mr.cache,
1238 MLX5_MR_BTREE_CACHE_N * 2,
1239 eth_dev->device->numa_node);
1244 /* Add device to memory callback list. */
1245 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1246 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1247 priv, mem_event_cb);
1248 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1252 if (priv->nl_socket_route >= 0)
1253 close(priv->nl_socket_route);
1254 if (priv->nl_socket_rdma >= 0)
1255 close(priv->nl_socket_rdma);
1256 if (priv->tcf_context)
1257 mlx5_flow_tcf_context_destroy(priv->tcf_context);
1259 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1261 if (eth_dev != NULL)
1262 eth_dev->data->dev_private = NULL;
1265 claim_zero(mlx5_glue->dealloc_pd(pd));
1266 if (eth_dev != NULL) {
1267 /* mac_addrs must not be freed alone because part of dev_private */
1268 eth_dev->data->mac_addrs = NULL;
1269 rte_eth_dev_release_port(eth_dev);
1272 claim_zero(mlx5_glue->close_device(ctx));
1278 /** Data associated with devices to spawn. */
1279 struct mlx5_dev_spawn_data {
1280 unsigned int ifindex; /**< Network interface index. */
1281 struct mlx5_switch_info info; /**< Switch information. */
1282 struct ibv_device *ibv_dev; /**< Associated IB device. */
1283 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
1287 * Comparison callback to sort device data.
1289 * This is meant to be used with qsort().
1292 * Pointer to pointer to first data object.
1294 * Pointer to pointer to second data object.
1297 * 0 if both objects are equal, less than 0 if the first argument is less
1298 * than the second, greater than 0 otherwise.
1301 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1303 const struct mlx5_switch_info *si_a =
1304 &((const struct mlx5_dev_spawn_data *)a)->info;
1305 const struct mlx5_switch_info *si_b =
1306 &((const struct mlx5_dev_spawn_data *)b)->info;
1309 /* Master device first. */
1310 ret = si_b->master - si_a->master;
1313 /* Then representor devices. */
1314 ret = si_b->representor - si_a->representor;
1317 /* Unidentified devices come last in no specific order. */
1318 if (!si_a->representor)
1320 /* Order representors by name. */
1321 return si_a->port_name - si_b->port_name;
1325 * DPDK callback to register a PCI device.
1327 * This function spawns Ethernet devices out of a given PCI device.
1329 * @param[in] pci_drv
1330 * PCI driver structure (mlx5_driver).
1331 * @param[in] pci_dev
1332 * PCI device information.
1335 * 0 on success, a negative errno value otherwise and rte_errno is set.
1338 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1339 struct rte_pci_device *pci_dev)
1341 struct ibv_device **ibv_list;
1343 struct mlx5_dev_config dev_config;
1346 assert(pci_drv == &mlx5_driver);
1348 ibv_list = mlx5_glue->get_device_list(&ret);
1350 rte_errno = errno ? errno : ENOSYS;
1351 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1355 struct ibv_device *ibv_match[ret + 1];
1358 struct rte_pci_addr pci_addr;
1360 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1361 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1363 if (pci_dev->addr.domain != pci_addr.domain ||
1364 pci_dev->addr.bus != pci_addr.bus ||
1365 pci_dev->addr.devid != pci_addr.devid ||
1366 pci_dev->addr.function != pci_addr.function)
1368 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1369 ibv_list[ret]->name);
1370 ibv_match[n++] = ibv_list[ret];
1372 ibv_match[n] = NULL;
1374 struct mlx5_dev_spawn_data list[n];
1375 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1;
1376 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1;
1381 * The existence of several matching entries (n > 1) means port
1382 * representors have been instantiated. No existing Verbs call nor
1383 * /sys entries can tell them apart, this can only be done through
1384 * Netlink calls assuming kernel drivers are recent enough to
1387 * In the event of identification failure through Netlink, try again
1388 * through sysfs, then either:
1390 * 1. No device matches (n == 0), complain and bail out.
1391 * 2. A single IB device matches (n == 1) and is not a representor,
1392 * assume no switch support.
1393 * 3. Otherwise no safe assumptions can be made; complain louder and
1396 for (i = 0; i != n; ++i) {
1397 list[i].ibv_dev = ibv_match[i];
1398 list[i].eth_dev = NULL;
1400 list[i].ifindex = 0;
1402 list[i].ifindex = mlx5_nl_ifindex
1403 (nl_rdma, list[i].ibv_dev->name);
1406 mlx5_nl_switch_info(nl_route, list[i].ifindex,
1408 ((!list[i].info.representor && !list[i].info.master) &&
1409 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) {
1410 list[i].ifindex = 0;
1411 memset(&list[i].info, 0, sizeof(list[i].info));
1419 /* Count unidentified devices. */
1420 for (u = 0, i = 0; i != n; ++i)
1421 if (!list[i].info.master && !list[i].info.representor)
1424 if (n == 1 && u == 1) {
1426 DRV_LOG(INFO, "no switch support detected");
1430 "unable to tell which of the matching devices"
1431 " is the master (lack of kernel support?)");
1436 * Sort list to probe devices in natural order for users convenience
1437 * (i.e. master first, then representors from lowest to highest ID).
1440 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp);
1441 /* Default configuration. */
1442 dev_config = (struct mlx5_dev_config){
1443 .mps = MLX5_ARG_UNSET,
1446 .txq_inline = MLX5_ARG_UNSET,
1447 .txqs_inline = MLX5_ARG_UNSET,
1448 .txqs_vec = MLX5_ARG_UNSET,
1449 .inline_max_packet_sz = MLX5_ARG_UNSET,
1452 .enabled = 0, /* Disabled by default. */
1453 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1454 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1455 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1458 /* Device speicific configuration. */
1459 switch (pci_dev->id.device_id) {
1460 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
1461 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
1463 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1464 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1465 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1466 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1472 /* Set architecture-dependent default value if unset. */
1473 if (dev_config.txqs_vec == MLX5_ARG_UNSET)
1474 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1475 for (i = 0; i != n; ++i) {
1478 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1479 list[i].ibv_dev, dev_config,
1481 if (!list[i].eth_dev) {
1482 if (rte_errno != EBUSY && rte_errno != EEXIST)
1484 /* Device is disabled or already spawned. Ignore it. */
1487 restore = list[i].eth_dev->data->dev_flags;
1488 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
1489 /* Restore non-PCI flags cleared by the above call. */
1490 list[i].eth_dev->data->dev_flags |= restore;
1491 rte_eth_dev_probing_finish(list[i].eth_dev);
1493 mlx5_glue->free_device_list(ibv_list);
1496 "no Verbs device matches PCI device " PCI_PRI_FMT ","
1497 " are kernel drivers loaded?",
1498 pci_dev->addr.domain, pci_dev->addr.bus,
1499 pci_dev->addr.devid, pci_dev->addr.function);
1502 } else if (i != n) {
1504 "probe of PCI device " PCI_PRI_FMT " aborted after"
1505 " encountering an error: %s",
1506 pci_dev->addr.domain, pci_dev->addr.bus,
1507 pci_dev->addr.devid, pci_dev->addr.function,
1508 strerror(rte_errno));
1512 if (!list[i].eth_dev)
1514 mlx5_dev_close(list[i].eth_dev);
1515 /* mac_addrs must not be freed because in dev_private */
1516 list[i].eth_dev->data->mac_addrs = NULL;
1517 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
1519 /* Restore original error. */
1528 * DPDK callback to remove a PCI device.
1530 * This function removes all Ethernet devices belong to a given PCI device.
1532 * @param[in] pci_dev
1533 * Pointer to the PCI device.
1536 * 0 on success, the function cannot fail.
1539 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1542 struct rte_eth_dev *port;
1544 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) {
1545 port = &rte_eth_devices[port_id];
1546 if (port->state != RTE_ETH_DEV_UNUSED &&
1547 port->device == &pci_dev->device)
1548 rte_eth_dev_close(port_id);
1553 static const struct rte_pci_id mlx5_pci_id_map[] = {
1555 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1556 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1559 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1560 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1563 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1564 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1567 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1568 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1571 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1572 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1575 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1576 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1579 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1580 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1583 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1584 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1587 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1588 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1591 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1592 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1595 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1596 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1599 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1600 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1607 static struct rte_pci_driver mlx5_driver = {
1609 .name = MLX5_DRIVER_NAME
1611 .id_table = mlx5_pci_id_map,
1612 .probe = mlx5_pci_probe,
1613 .remove = mlx5_pci_remove,
1614 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
1615 RTE_PCI_DRV_PROBE_AGAIN),
1618 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1621 * Suffix RTE_EAL_PMD_PATH with "-glue".
1623 * This function performs a sanity check on RTE_EAL_PMD_PATH before
1624 * suffixing its last component.
1627 * Output buffer, should be large enough otherwise NULL is returned.
1632 * Pointer to @p buf or @p NULL in case suffix cannot be appended.
1635 mlx5_glue_path(char *buf, size_t size)
1637 static const char *const bad[] = { "/", ".", "..", NULL };
1638 const char *path = RTE_EAL_PMD_PATH;
1639 size_t len = strlen(path);
1643 while (len && path[len - 1] == '/')
1645 for (off = len; off && path[off - 1] != '/'; --off)
1647 for (i = 0; bad[i]; ++i)
1648 if (!strncmp(path + off, bad[i], (int)(len - off)))
1650 i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1651 if (i == -1 || (size_t)i >= size)
1656 "unable to append \"-glue\" to last component of"
1657 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1658 " please re-configure DPDK");
1663 * Initialization routine for run-time dependency on rdma-core.
1666 mlx5_glue_init(void)
1668 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1669 const char *path[] = {
1671 * A basic security check is necessary before trusting
1672 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1674 (geteuid() == getuid() && getegid() == getgid() ?
1675 getenv("MLX5_GLUE_PATH") : NULL),
1677 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1678 * variant, otherwise let dlopen() look up libraries on its
1681 (*RTE_EAL_PMD_PATH ?
1682 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1685 void *handle = NULL;
1689 while (!handle && i != RTE_DIM(path)) {
1698 end = strpbrk(path[i], ":;");
1700 end = path[i] + strlen(path[i]);
1701 len = end - path[i];
1706 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1708 (!len || *(end - 1) == '/') ? "" : "/");
1711 if (sizeof(name) != (size_t)ret + 1)
1713 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1715 handle = dlopen(name, RTLD_LAZY);
1726 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1729 sym = dlsym(handle, "mlx5_glue");
1730 if (!sym || !*sym) {
1734 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1743 "cannot initialize PMD due to missing run-time dependency on"
1744 " rdma-core libraries (libibverbs, libmlx5)");
1751 * Driver initialization routine.
1753 RTE_INIT(rte_mlx5_pmd_init)
1755 /* Initialize driver log type. */
1756 mlx5_logtype = rte_log_register("pmd.net.mlx5");
1757 if (mlx5_logtype >= 0)
1758 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1760 /* Build the static tables for Verbs conversion. */
1761 mlx5_set_ptype_table();
1762 mlx5_set_cksum_table();
1763 mlx5_set_swp_types_table();
1765 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1766 * huge pages. Calling ibv_fork_init() during init allows
1767 * applications to use fork() safely for purposes other than
1768 * using this PMD, which is not supported in forked processes.
1770 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1771 /* Match the size of Rx completion entry to the size of a cacheline. */
1772 if (RTE_CACHE_LINE_SIZE == 128)
1773 setenv("MLX5_CQE_SIZE", "128", 0);
1775 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1776 * cleanup all the Verbs resources even when the device was removed.
1778 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1779 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1780 if (mlx5_glue_init())
1785 /* Glue structure must not contain any NULL pointers. */
1789 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1790 assert(((const void *const *)mlx5_glue)[i]);
1793 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1795 "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1796 mlx5_glue->version, MLX5_GLUE_VERSION);
1799 mlx5_glue->fork_init();
1800 rte_pci_register(&mlx5_driver);
1803 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1804 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1805 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");