drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <assert.h>
  10 #include <dlfcn.h>
  11 #include <stdint.h>
  12 #include <stdlib.h>
  13 #include <errno.h>
  14 #include <net/if.h>
  15 #include <sys/mman.h>
  16 #include <linux/rtnetlink.h>
  17
  18 /* Verbs header. */
  19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  20 #ifdef PEDANTIC
  21 #pragma GCC diagnostic ignored "-Wpedantic"
  22 #endif
  23 #include <infiniband/verbs.h>
  24 #ifdef PEDANTIC
  25 #pragma GCC diagnostic error "-Wpedantic"
  26 #endif
  27
  28 #include <rte_malloc.h>
  29 #include <rte_ethdev_driver.h>
  30 #include <rte_ethdev_pci.h>
  31 #include <rte_pci.h>
  32 #include <rte_bus_pci.h>
  33 #include <rte_common.h>
  34 #include <rte_config.h>
  35 #include <rte_eal_memconfig.h>
  36 #include <rte_kvargs.h>
  37 #include <rte_rwlock.h>
  38 #include <rte_spinlock.h>
  39
  40 #include "mlx5.h"
  41 #include "mlx5_utils.h"
  42 #include "mlx5_rxtx.h"
  43 #include "mlx5_autoconf.h"
  44 #include "mlx5_defs.h"
  45 #include "mlx5_glue.h"
  46 #include "mlx5_mr.h"
  47
  48 /* Device parameter to enable RX completion queue compression. */
  49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  50
  51 /* Device parameter to enable Multi-Packet Rx queue. */
  52 #define MLX5_RX_MPRQ_EN "mprq_en"
  53
  54 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  55 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  56
  57 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  58 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  59
  60 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  61 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  62
  63 /* Device parameter to configure inline send. */
  64 #define MLX5_TXQ_INLINE "txq_inline"
  65
  66 /*
  67  * Device parameter to configure the number of TX queues threshold for
  68  * enabling inline send.
  69  */
  70 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  71
  72 /* Device parameter to enable multi-packet send WQEs. */
  73 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  74
  75 /* Device parameter to include 2 dsegs in the title WQEBB. */
  76 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
  77
  78 /* Device parameter to limit the size of inlining packet. */
  79 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
  80
  81 /* Device parameter to enable hardware Tx vector. */
  82 #define MLX5_TX_VEC_EN "tx_vec_en"
  83
  84 /* Device parameter to enable hardware Rx vector. */
  85 #define MLX5_RX_VEC_EN "rx_vec_en"
  86
  87 /* Allow L3 VXLAN flow creation. */
  88 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
  89
  90 /* Activate Netlink support in VF mode. */
  91 #define MLX5_VF_NL_EN "vf_nl_en"
  92
  93 #ifndef HAVE_IBV_MLX5_MOD_MPW
  94 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
  95 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
  96 #endif
  97
  98 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
  99 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 100 #endif
 101
 102 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 103
 104 /* Shared memory between primary and secondary processes. */
 105 struct mlx5_shared_data *mlx5_shared_data;
 106
 107 /* Spinlock for mlx5_shared_data allocation. */
 108 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 109
 110 /** Driver-specific log messages type. */
 111 int mlx5_logtype;
 112
 113 /**
 114  * Prepare shared data between primary and secondary process.
 115  */
 116 static void
 117 mlx5_prepare_shared_data(void)
 118 {
 119         const struct rte_memzone *mz;
 120
 121         rte_spinlock_lock(&mlx5_shared_data_lock);
 122         if (mlx5_shared_data == NULL) {
 123                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 124                         /* Allocate shared memory. */
 125                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 126                                                  sizeof(*mlx5_shared_data),
 127                                                  SOCKET_ID_ANY, 0);
 128                 } else {
 129                         /* Lookup allocated shared memory. */
 130                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 131                 }
 132                 if (mz == NULL)
 133                         rte_panic("Cannot allocate mlx5 shared data\n");
 134                 mlx5_shared_data = mz->addr;
 135                 /* Initialize shared data. */
 136                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 137                         LIST_INIT(&mlx5_shared_data->mem_event_cb_list);
 138                         rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock);
 139                 }
 140                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 141                                                 mlx5_mr_mem_event_cb, NULL);
 142         }
 143         rte_spinlock_unlock(&mlx5_shared_data_lock);
 144 }
 145
 146 /**
 147  * Retrieve integer value from environment variable.
 148  *
 149  * @param[in] name
 150  *   Environment variable name.
 151  *
 152  * @return
 153  *   Integer value, 0 if the variable is not set.
 154  */
 155 int
 156 mlx5_getenv_int(const char *name)
 157 {
 158         const char *val = getenv(name);
 159
 160         if (val == NULL)
 161                 return 0;
 162         return atoi(val);
 163 }
 164
 165 /**
 166  * Verbs callback to allocate a memory. This function should allocate the space
 167  * according to the size provided residing inside a huge page.
 168  * Please note that all allocation must respect the alignment from libmlx5
 169  * (i.e. currently sysconf(_SC_PAGESIZE)).
 170  *
 171  * @param[in] size
 172  *   The size in bytes of the memory to allocate.
 173  * @param[in] data
 174  *   A pointer to the callback data.
 175  *
 176  * @return
 177  *   Allocated buffer, NULL otherwise and rte_errno is set.
 178  */
 179 static void *
 180 mlx5_alloc_verbs_buf(size_t size, void *data)
 181 {
 182         struct priv *priv = data;
 183         void *ret;
 184         size_t alignment = sysconf(_SC_PAGESIZE);
 185         unsigned int socket = SOCKET_ID_ANY;
 186
 187         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
 188                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 189
 190                 socket = ctrl->socket;
 191         } else if (priv->verbs_alloc_ctx.type ==
 192                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
 193                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
 194
 195                 socket = ctrl->socket;
 196         }
 197         assert(data != NULL);
 198         ret = rte_malloc_socket(__func__, size, alignment, socket);
 199         if (!ret && size)
 200                 rte_errno = ENOMEM;
 201         return ret;
 202 }
 203
 204 /**
 205  * Verbs callback to free a memory.
 206  *
 207  * @param[in] ptr
 208  *   A pointer to the memory to free.
 209  * @param[in] data
 210  *   A pointer to the callback data.
 211  */
 212 static void
 213 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
 214 {
 215         assert(data != NULL);
 216         rte_free(ptr);
 217 }
 218
 219 /**
 220  * DPDK callback to close the device.
 221  *
 222  * Destroy all queues and objects, free memory.
 223  *
 224  * @param dev
 225  *   Pointer to Ethernet device structure.
 226  */
 227 static void
 228 mlx5_dev_close(struct rte_eth_dev *dev)
 229 {
 230         struct priv *priv = dev->data->dev_private;
 231         unsigned int i;
 232         int ret;
 233
 234         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
 235                 dev->data->port_id,
 236                 ((priv->ctx != NULL) ? priv->ctx->device->name : ""));
 237         /* In case mlx5_dev_stop() has not been called. */
 238         mlx5_dev_interrupt_handler_uninstall(dev);
 239         mlx5_traffic_disable(dev);
 240         /* Prevent crashes when queues are still in use. */
 241         dev->rx_pkt_burst = removed_rx_burst;
 242         dev->tx_pkt_burst = removed_tx_burst;
 243         if (priv->rxqs != NULL) {
 244                 /* XXX race condition if mlx5_rx_burst() is still running. */
 245                 usleep(1000);
 246                 for (i = 0; (i != priv->rxqs_n); ++i)
 247                         mlx5_rxq_release(dev, i);
 248                 priv->rxqs_n = 0;
 249                 priv->rxqs = NULL;
 250         }
 251         if (priv->txqs != NULL) {
 252                 /* XXX race condition if mlx5_tx_burst() is still running. */
 253                 usleep(1000);
 254                 for (i = 0; (i != priv->txqs_n); ++i)
 255                         mlx5_txq_release(dev, i);
 256                 priv->txqs_n = 0;
 257                 priv->txqs = NULL;
 258         }
 259         mlx5_flow_delete_drop_queue(dev);
 260         mlx5_mprq_free_mp(dev);
 261         mlx5_mr_release(dev);
 262         if (priv->pd != NULL) {
 263                 assert(priv->ctx != NULL);
 264                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 265                 claim_zero(mlx5_glue->close_device(priv->ctx));
 266         } else
 267                 assert(priv->ctx == NULL);
 268         if (priv->rss_conf.rss_key != NULL)
 269                 rte_free(priv->rss_conf.rss_key);
 270         if (priv->reta_idx != NULL)
 271                 rte_free(priv->reta_idx);
 272         if (priv->primary_socket)
 273                 mlx5_socket_uninit(dev);
 274         if (priv->config.vf)
 275                 mlx5_nl_mac_addr_flush(dev);
 276         if (priv->nl_socket >= 0)
 277                 close(priv->nl_socket);
 278         ret = mlx5_hrxq_ibv_verify(dev);
 279         if (ret)
 280                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
 281                         dev->data->port_id);
 282         ret = mlx5_ind_table_ibv_verify(dev);
 283         if (ret)
 284                 DRV_LOG(WARNING, "port %u some indirection table still remain",
 285                         dev->data->port_id);
 286         ret = mlx5_rxq_ibv_verify(dev);
 287         if (ret)
 288                 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
 289                         dev->data->port_id);
 290         ret = mlx5_rxq_verify(dev);
 291         if (ret)
 292                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
 293                         dev->data->port_id);
 294         ret = mlx5_txq_ibv_verify(dev);
 295         if (ret)
 296                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
 297                         dev->data->port_id);
 298         ret = mlx5_txq_verify(dev);
 299         if (ret)
 300                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
 301                         dev->data->port_id);
 302         ret = mlx5_flow_verify(dev);
 303         if (ret)
 304                 DRV_LOG(WARNING, "port %u some flows still remain",
 305                         dev->data->port_id);
 306         memset(priv, 0, sizeof(*priv));
 307 }
 308
 309 const struct eth_dev_ops mlx5_dev_ops = {
 310         .dev_configure = mlx5_dev_configure,
 311         .dev_start = mlx5_dev_start,
 312         .dev_stop = mlx5_dev_stop,
 313         .dev_set_link_down = mlx5_set_link_down,
 314         .dev_set_link_up = mlx5_set_link_up,
 315         .dev_close = mlx5_dev_close,
 316         .promiscuous_enable = mlx5_promiscuous_enable,
 317         .promiscuous_disable = mlx5_promiscuous_disable,
 318         .allmulticast_enable = mlx5_allmulticast_enable,
 319         .allmulticast_disable = mlx5_allmulticast_disable,
 320         .link_update = mlx5_link_update,
 321         .stats_get = mlx5_stats_get,
 322         .stats_reset = mlx5_stats_reset,
 323         .xstats_get = mlx5_xstats_get,
 324         .xstats_reset = mlx5_xstats_reset,
 325         .xstats_get_names = mlx5_xstats_get_names,
 326         .dev_infos_get = mlx5_dev_infos_get,
 327         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 328         .vlan_filter_set = mlx5_vlan_filter_set,
 329         .rx_queue_setup = mlx5_rx_queue_setup,
 330         .tx_queue_setup = mlx5_tx_queue_setup,
 331         .rx_queue_release = mlx5_rx_queue_release,
 332         .tx_queue_release = mlx5_tx_queue_release,
 333         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 334         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 335         .mac_addr_remove = mlx5_mac_addr_remove,
 336         .mac_addr_add = mlx5_mac_addr_add,
 337         .mac_addr_set = mlx5_mac_addr_set,
 338         .set_mc_addr_list = mlx5_set_mc_addr_list,
 339         .mtu_set = mlx5_dev_set_mtu,
 340         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 341         .vlan_offload_set = mlx5_vlan_offload_set,
 342         .reta_update = mlx5_dev_rss_reta_update,
 343         .reta_query = mlx5_dev_rss_reta_query,
 344         .rss_hash_update = mlx5_rss_hash_update,
 345         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
 346         .filter_ctrl = mlx5_dev_filter_ctrl,
 347         .rx_descriptor_status = mlx5_rx_descriptor_status,
 348         .tx_descriptor_status = mlx5_tx_descriptor_status,
 349         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 350         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 351         .is_removed = mlx5_is_removed,
 352 };
 353
 354 static const struct eth_dev_ops mlx5_dev_sec_ops = {
 355         .stats_get = mlx5_stats_get,
 356         .stats_reset = mlx5_stats_reset,
 357         .xstats_get = mlx5_xstats_get,
 358         .xstats_reset = mlx5_xstats_reset,
 359         .xstats_get_names = mlx5_xstats_get_names,
 360         .dev_infos_get = mlx5_dev_infos_get,
 361         .rx_descriptor_status = mlx5_rx_descriptor_status,
 362         .tx_descriptor_status = mlx5_tx_descriptor_status,
 363 };
 364
 365 /* Available operators in flow isolated mode. */
 366 const struct eth_dev_ops mlx5_dev_ops_isolate = {
 367         .dev_configure = mlx5_dev_configure,
 368         .dev_start = mlx5_dev_start,
 369         .dev_stop = mlx5_dev_stop,
 370         .dev_set_link_down = mlx5_set_link_down,
 371         .dev_set_link_up = mlx5_set_link_up,
 372         .dev_close = mlx5_dev_close,
 373         .link_update = mlx5_link_update,
 374         .stats_get = mlx5_stats_get,
 375         .stats_reset = mlx5_stats_reset,
 376         .xstats_get = mlx5_xstats_get,
 377         .xstats_reset = mlx5_xstats_reset,
 378         .xstats_get_names = mlx5_xstats_get_names,
 379         .dev_infos_get = mlx5_dev_infos_get,
 380         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
 381         .vlan_filter_set = mlx5_vlan_filter_set,
 382         .rx_queue_setup = mlx5_rx_queue_setup,
 383         .tx_queue_setup = mlx5_tx_queue_setup,
 384         .rx_queue_release = mlx5_rx_queue_release,
 385         .tx_queue_release = mlx5_tx_queue_release,
 386         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
 387         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
 388         .mac_addr_remove = mlx5_mac_addr_remove,
 389         .mac_addr_add = mlx5_mac_addr_add,
 390         .mac_addr_set = mlx5_mac_addr_set,
 391         .set_mc_addr_list = mlx5_set_mc_addr_list,
 392         .mtu_set = mlx5_dev_set_mtu,
 393         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
 394         .vlan_offload_set = mlx5_vlan_offload_set,
 395         .filter_ctrl = mlx5_dev_filter_ctrl,
 396         .rx_descriptor_status = mlx5_rx_descriptor_status,
 397         .tx_descriptor_status = mlx5_tx_descriptor_status,
 398         .rx_queue_intr_enable = mlx5_rx_intr_enable,
 399         .rx_queue_intr_disable = mlx5_rx_intr_disable,
 400         .is_removed = mlx5_is_removed,
 401 };
 402
 403 /**
 404  * Verify and store value for device argument.
 405  *
 406  * @param[in] key
 407  *   Key argument to verify.
 408  * @param[in] val
 409  *   Value associated with key.
 410  * @param opaque
 411  *   User data.
 412  *
 413  * @return
 414  *   0 on success, a negative errno value otherwise and rte_errno is set.
 415  */
 416 static int
 417 mlx5_args_check(const char *key, const char *val, void *opaque)
 418 {
 419         struct mlx5_dev_config *config = opaque;
 420         unsigned long tmp;
 421
 422         errno = 0;
 423         tmp = strtoul(val, NULL, 0);
 424         if (errno) {
 425                 rte_errno = errno;
 426                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
 427                 return -rte_errno;
 428         }
 429         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
 430                 config->cqe_comp = !!tmp;
 431         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
 432                 config->mprq.enabled = !!tmp;
 433         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
 434                 config->mprq.stride_num_n = tmp;
 435         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
 436                 config->mprq.max_memcpy_len = tmp;
 437         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
 438                 config->mprq.min_rxqs_num = tmp;
 439         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
 440                 config->txq_inline = tmp;
 441         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
 442                 config->txqs_inline = tmp;
 443         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
 444                 config->mps = !!tmp ? config->mps : 0;
 445         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
 446                 config->mpw_hdr_dseg = !!tmp;
 447         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
 448                 config->inline_max_packet_sz = tmp;
 449         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
 450                 config->tx_vec_en = !!tmp;
 451         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
 452                 config->rx_vec_en = !!tmp;
 453         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
 454                 config->l3_vxlan_en = !!tmp;
 455         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
 456                 config->vf_nl_en = !!tmp;
 457         } else {
 458                 DRV_LOG(WARNING, "%s: unknown parameter", key);
 459                 rte_errno = EINVAL;
 460                 return -rte_errno;
 461         }
 462         return 0;
 463 }
 464
 465 /**
 466  * Parse device parameters.
 467  *
 468  * @param config
 469  *   Pointer to device configuration structure.
 470  * @param devargs
 471  *   Device arguments structure.
 472  *
 473  * @return
 474  *   0 on success, a negative errno value otherwise and rte_errno is set.
 475  */
 476 static int
 477 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
 478 {
 479         const char **params = (const char *[]){
 480                 MLX5_RXQ_CQE_COMP_EN,
 481                 MLX5_RX_MPRQ_EN,
 482                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
 483                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
 484                 MLX5_RXQS_MIN_MPRQ,
 485                 MLX5_TXQ_INLINE,
 486                 MLX5_TXQS_MIN_INLINE,
 487                 MLX5_TXQ_MPW_EN,
 488                 MLX5_TXQ_MPW_HDR_DSEG_EN,
 489                 MLX5_TXQ_MAX_INLINE_LEN,
 490                 MLX5_TX_VEC_EN,
 491                 MLX5_RX_VEC_EN,
 492                 MLX5_L3_VXLAN_EN,
 493                 MLX5_VF_NL_EN,
 494                 NULL,
 495         };
 496         struct rte_kvargs *kvlist;
 497         int ret = 0;
 498         int i;
 499
 500         if (devargs == NULL)
 501                 return 0;
 502         /* Following UGLY cast is done to pass checkpatch. */
 503         kvlist = rte_kvargs_parse(devargs->args, params);
 504         if (kvlist == NULL)
 505                 return 0;
 506         /* Process parameters. */
 507         for (i = 0; (params[i] != NULL); ++i) {
 508                 if (rte_kvargs_count(kvlist, params[i])) {
 509                         ret = rte_kvargs_process(kvlist, params[i],
 510                                                  mlx5_args_check, config);
 511                         if (ret) {
 512                                 rte_errno = EINVAL;
 513                                 rte_kvargs_free(kvlist);
 514                                 return -rte_errno;
 515                         }
 516                 }
 517         }
 518         rte_kvargs_free(kvlist);
 519         return 0;
 520 }
 521
 522 static struct rte_pci_driver mlx5_driver;
 523
 524 /*
 525  * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process
 526  * local resource used by both primary and secondary to avoid duplicate
 527  * reservation.
 528  * The space has to be available on both primary and secondary process,
 529  * TXQ UAR maps to this area using fixed mmap w/o double check.
 530  */
 531 static void *uar_base;
 532
 533 static int
 534 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused,
 535                 const struct rte_memseg *ms, void *arg)
 536 {
 537         void **addr = arg;
 538
 539         if (*addr == NULL)
 540                 *addr = ms->addr;
 541         else
 542                 *addr = RTE_MIN(*addr, ms->addr);
 543
 544         return 0;
 545 }
 546
 547 /**
 548  * Reserve UAR address space for primary process.
 549  *
 550  * @param[in] dev
 551  *   Pointer to Ethernet device.
 552  *
 553  * @return
 554  *   0 on success, a negative errno value otherwise and rte_errno is set.
 555  */
 556 static int
 557 mlx5_uar_init_primary(struct rte_eth_dev *dev)
 558 {
 559         struct priv *priv = dev->data->dev_private;
 560         void *addr = (void *)0;
 561
 562         if (uar_base) { /* UAR address space mapped. */
 563                 priv->uar_base = uar_base;
 564                 return 0;
 565         }
 566         /* find out lower bound of hugepage segments */
 567         rte_memseg_walk(find_lower_va_bound, &addr);
 568
 569         /* keep distance to hugepages to minimize potential conflicts. */
 570         addr = RTE_PTR_SUB(addr, MLX5_UAR_OFFSET + MLX5_UAR_SIZE);
 571         /* anonymous mmap, no real memory consumption. */
 572         addr = mmap(addr, MLX5_UAR_SIZE,
 573                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 574         if (addr == MAP_FAILED) {
 575                 DRV_LOG(ERR,
 576                         "port %u failed to reserve UAR address space, please"
 577                         " adjust MLX5_UAR_SIZE or try --base-virtaddr",
 578                         dev->data->port_id);
 579                 rte_errno = ENOMEM;
 580                 return -rte_errno;
 581         }
 582         /* Accept either same addr or a new addr returned from mmap if target
 583          * range occupied.
 584          */
 585         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 586                 dev->data->port_id, addr);
 587         priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */
 588         uar_base = addr; /* process local, don't reserve again. */
 589         return 0;
 590 }
 591
 592 /**
 593  * Reserve UAR address space for secondary process, align with
 594  * primary process.
 595  *
 596  * @param[in] dev
 597  *   Pointer to Ethernet device.
 598  *
 599  * @return
 600  *   0 on success, a negative errno value otherwise and rte_errno is set.
 601  */
 602 static int
 603 mlx5_uar_init_secondary(struct rte_eth_dev *dev)
 604 {
 605         struct priv *priv = dev->data->dev_private;
 606         void *addr;
 607
 608         assert(priv->uar_base);
 609         if (uar_base) { /* already reserved. */
 610                 assert(uar_base == priv->uar_base);
 611                 return 0;
 612         }
 613         /* anonymous mmap, no real memory consumption. */
 614         addr = mmap(priv->uar_base, MLX5_UAR_SIZE,
 615                     PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 616         if (addr == MAP_FAILED) {
 617                 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu",
 618                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 619                 rte_errno = ENXIO;
 620                 return -rte_errno;
 621         }
 622         if (priv->uar_base != addr) {
 623                 DRV_LOG(ERR,
 624                         "port %u UAR address %p size %llu occupied, please"
 625                         " adjust MLX5_UAR_OFFSET or try EAL parameter"
 626                         " --base-virtaddr",
 627                         dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE);
 628                 rte_errno = ENXIO;
 629                 return -rte_errno;
 630         }
 631         uar_base = addr; /* process local, don't reserve again */
 632         DRV_LOG(INFO, "port %u reserved UAR address space: %p",
 633                 dev->data->port_id, addr);
 634         return 0;
 635 }
 636
 637 /**
 638  * DPDK callback to register a PCI device.
 639  *
 640  * This function creates an Ethernet device for each port of a given
 641  * PCI device.
 642  *
 643  * @param[in] pci_drv
 644  *   PCI driver structure (mlx5_driver).
 645  * @param[in] pci_dev
 646  *   PCI device information.
 647  *
 648  * @return
 649  *   0 on success, a negative errno value otherwise and rte_errno is set.
 650  */
 651 static int
 652 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 653                struct rte_pci_device *pci_dev)
 654 {
 655         struct ibv_device **list;
 656         struct ibv_context *ctx = NULL;
 657         struct ibv_device_attr_ex attr;
 658         struct ibv_pd *pd = NULL;
 659         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
 660         struct rte_eth_dev *eth_dev = NULL;
 661         struct priv *priv = NULL;
 662         int err = 0;
 663         unsigned int vf = 0;
 664         unsigned int mps;
 665         unsigned int cqe_comp;
 666         unsigned int tunnel_en = 0;
 667         unsigned int mpls_en = 0;
 668         unsigned int swp = 0;
 669         unsigned int verb_priorities = 0;
 670         unsigned int mprq = 0;
 671         unsigned int mprq_min_stride_size_n = 0;
 672         unsigned int mprq_max_stride_size_n = 0;
 673         unsigned int mprq_min_stride_num_n = 0;
 674         unsigned int mprq_max_stride_num_n = 0;
 675         int i;
 676 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 677         struct ibv_counter_set_description cs_desc = { .counter_type = 0 };
 678 #endif
 679
 680         /* Prepare shared data between primary and secondary process. */
 681         mlx5_prepare_shared_data();
 682         assert(pci_drv == &mlx5_driver);
 683         list = mlx5_glue->get_device_list(&i);
 684         if (list == NULL) {
 685                 assert(errno);
 686                 err = errno;
 687                 if (errno == ENOSYS)
 688                         DRV_LOG(ERR,
 689                                 "cannot list devices, is ib_uverbs loaded?");
 690                 goto error;
 691         }
 692         assert(i >= 0);
 693         /*
 694          * For each listed device, check related sysfs entry against
 695          * the provided PCI ID.
 696          */
 697         while (i != 0) {
 698                 struct rte_pci_addr pci_addr;
 699
 700                 --i;
 701                 DRV_LOG(DEBUG, "checking device \"%s\"", list[i]->name);
 702                 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr))
 703                         continue;
 704                 if ((pci_dev->addr.domain != pci_addr.domain) ||
 705                     (pci_dev->addr.bus != pci_addr.bus) ||
 706                     (pci_dev->addr.devid != pci_addr.devid) ||
 707                     (pci_dev->addr.function != pci_addr.function))
 708                         continue;
 709                 DRV_LOG(INFO, "PCI information matches, using device \"%s\"",
 710                         list[i]->name);
 711                 vf = ((pci_dev->id.device_id ==
 712                        PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) ||
 713                       (pci_dev->id.device_id ==
 714                        PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) ||
 715                       (pci_dev->id.device_id ==
 716                        PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) ||
 717                       (pci_dev->id.device_id ==
 718                        PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF));
 719                 ctx = mlx5_glue->open_device(list[i]);
 720                 rte_errno = errno;
 721                 err = rte_errno;
 722                 break;
 723         }
 724         mlx5_glue->free_device_list(list);
 725         if (ctx == NULL) {
 726                 switch (err) {
 727                 case 0:
 728                         DRV_LOG(ERR,
 729                                 "cannot access device, is mlx5_ib loaded?");
 730                         err = ENODEV;
 731                         break;
 732                 case EINVAL:
 733                         DRV_LOG(ERR,
 734                                 "cannot use device, are drivers up to date?");
 735                         break;
 736                 }
 737                 goto error;
 738         }
 739         DRV_LOG(DEBUG, "device opened");
 740 #ifdef HAVE_IBV_MLX5_MOD_SWP
 741         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
 742 #endif
 743         /*
 744          * Multi-packet send is supported by ConnectX-4 Lx PF as well
 745          * as all ConnectX-5 devices.
 746          */
 747 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 748         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
 749 #endif
 750 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 751         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
 752 #endif
 753         mlx5_glue->dv_query_device(ctx, &dv_attr);
 754         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
 755                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
 756                         DRV_LOG(DEBUG, "enhanced MPW is supported");
 757                         mps = MLX5_MPW_ENHANCED;
 758                 } else {
 759                         DRV_LOG(DEBUG, "MPW is supported");
 760                         mps = MLX5_MPW;
 761                 }
 762         } else {
 763                 DRV_LOG(DEBUG, "MPW isn't supported");
 764                 mps = MLX5_MPW_DISABLED;
 765         }
 766 #ifdef HAVE_IBV_MLX5_MOD_SWP
 767         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
 768                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
 769         DRV_LOG(DEBUG, "SWP support: %u", swp);
 770 #endif
 771 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 772         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
 773                 struct mlx5dv_striding_rq_caps mprq_caps =
 774                         dv_attr.striding_rq_caps;
 775
 776                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
 777                         mprq_caps.min_single_stride_log_num_of_bytes);
 778                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
 779                         mprq_caps.max_single_stride_log_num_of_bytes);
 780                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
 781                         mprq_caps.min_single_wqe_log_num_of_strides);
 782                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
 783                         mprq_caps.max_single_wqe_log_num_of_strides);
 784                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
 785                         mprq_caps.supported_qpts);
 786                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
 787                 mprq = 1;
 788                 mprq_min_stride_size_n =
 789                         mprq_caps.min_single_stride_log_num_of_bytes;
 790                 mprq_max_stride_size_n =
 791                         mprq_caps.max_single_stride_log_num_of_bytes;
 792                 mprq_min_stride_num_n =
 793                         mprq_caps.min_single_wqe_log_num_of_strides;
 794                 mprq_max_stride_num_n =
 795                         mprq_caps.max_single_wqe_log_num_of_strides;
 796         }
 797 #endif
 798         if (RTE_CACHE_LINE_SIZE == 128 &&
 799             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
 800                 cqe_comp = 0;
 801         else
 802                 cqe_comp = 1;
 803 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 804         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
 805                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
 806                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
 807                              (dv_attr.tunnel_offloads_caps &
 808                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
 809         }
 810         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
 811                 tunnel_en ? "" : "not ");
 812 #else
 813         DRV_LOG(WARNING,
 814                 "tunnel offloading disabled due to old OFED/rdma-core version");
 815 #endif
 816 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
 817         mpls_en = ((dv_attr.tunnel_offloads_caps &
 818                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
 819                    (dv_attr.tunnel_offloads_caps &
 820                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
 821         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
 822                 mpls_en ? "" : "not ");
 823 #else
 824         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
 825                 " old OFED/rdma-core version or firmware configuration");
 826 #endif
 827         err = mlx5_glue->query_device_ex(ctx, NULL, &attr);
 828         if (err) {
 829                 DEBUG("ibv_query_device_ex() failed");
 830                 goto error;
 831         }
 832         {
 833                 char name[RTE_ETH_NAME_MAX_LEN];
 834                 struct ibv_port_attr port_attr;
 835                 struct ether_addr mac;
 836                 struct mlx5_dev_config config = {
 837                         .cqe_comp = cqe_comp,
 838                         .mps = mps,
 839                         .tunnel_en = tunnel_en,
 840                         .mpls_en = mpls_en,
 841                         .tx_vec_en = 1,
 842                         .rx_vec_en = 1,
 843                         .mpw_hdr_dseg = 0,
 844                         .txq_inline = MLX5_ARG_UNSET,
 845                         .txqs_inline = MLX5_ARG_UNSET,
 846                         .inline_max_packet_sz = MLX5_ARG_UNSET,
 847                         .vf_nl_en = 1,
 848                         .swp = !!swp,
 849                         .mprq = {
 850                                 .enabled = 0, /* Disabled by default. */
 851                                 .stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
 852                                                         mprq_min_stride_num_n),
 853                                 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
 854                                 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
 855                         },
 856                 };
 857
 858                 snprintf(name, sizeof(name), PCI_PRI_FMT,
 859                          pci_dev->addr.domain, pci_dev->addr.bus,
 860                          pci_dev->addr.devid, pci_dev->addr.function);
 861                 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
 862                         eth_dev = rte_eth_dev_attach_secondary(name);
 863                         if (eth_dev == NULL) {
 864                                 DRV_LOG(ERR, "can not attach rte ethdev");
 865                                 rte_errno = ENOMEM;
 866                                 err = rte_errno;
 867                                 goto error;
 868                         }
 869                         eth_dev->device = &pci_dev->device;
 870                         eth_dev->dev_ops = &mlx5_dev_sec_ops;
 871                         err = mlx5_uar_init_secondary(eth_dev);
 872                         if (err) {
 873                                 err = rte_errno;
 874                                 goto error;
 875                         }
 876                         /* Receive command fd from primary process */
 877                         err = mlx5_socket_connect(eth_dev);
 878                         if (err < 0) {
 879                                 err = rte_errno;
 880                                 goto error;
 881                         }
 882                         /* Remap UAR for Tx queues. */
 883                         err = mlx5_tx_uar_remap(eth_dev, err);
 884                         if (err) {
 885                                 err = rte_errno;
 886                                 goto error;
 887                         }
 888                         /*
 889                          * Ethdev pointer is still required as input since
 890                          * the primary device is not accessible from the
 891                          * secondary process.
 892                          */
 893                         eth_dev->rx_pkt_burst =
 894                                 mlx5_select_rx_function(eth_dev);
 895                         eth_dev->tx_pkt_burst =
 896                                 mlx5_select_tx_function(eth_dev);
 897                         rte_eth_dev_probing_finish(eth_dev);
 898                         claim_zero(mlx5_glue->close_device(ctx));
 899                         return 0;
 900                 }
 901                 /* Check port status. */
 902                 err = mlx5_glue->query_port(ctx, 1, &port_attr);
 903                 if (err) {
 904                         DRV_LOG(ERR, "port query failed: %s", strerror(err));
 905                         goto error;
 906                 }
 907                 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
 908                         DRV_LOG(ERR, "port is not configured in Ethernet mode");
 909                         err = EINVAL;
 910                         goto error;
 911                 }
 912                 if (port_attr.state != IBV_PORT_ACTIVE)
 913                         DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
 914                                 mlx5_glue->port_state_str(port_attr.state),
 915                                 port_attr.state);
 916                 /* Allocate protection domain. */
 917                 pd = mlx5_glue->alloc_pd(ctx);
 918                 if (pd == NULL) {
 919                         DRV_LOG(ERR, "PD allocation failure");
 920                         err = ENOMEM;
 921                         goto error;
 922                 }
 923                 /* from rte_ethdev.c */
 924                 priv = rte_zmalloc("ethdev private structure",
 925                                    sizeof(*priv),
 926                                    RTE_CACHE_LINE_SIZE);
 927                 if (priv == NULL) {
 928                         DRV_LOG(ERR, "priv allocation failure");
 929                         err = ENOMEM;
 930                         goto error;
 931                 }
 932                 priv->ctx = ctx;
 933                 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path,
 934                         sizeof(priv->ibdev_path));
 935                 priv->device_attr = attr;
 936                 priv->pd = pd;
 937                 priv->mtu = ETHER_MTU;
 938                 err = mlx5_args(&config, pci_dev->device.devargs);
 939                 if (err) {
 940                         err = rte_errno;
 941                         DRV_LOG(ERR, "failed to process device arguments: %s",
 942                                 strerror(rte_errno));
 943                         goto error;
 944                 }
 945                 config.hw_csum = !!(attr.device_cap_flags_ex &
 946                                     IBV_DEVICE_RAW_IP_CSUM);
 947                 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
 948                         (config.hw_csum ? "" : "not "));
 949 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT
 950                 config.flow_counter_en = !!attr.max_counter_sets;
 951                 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc);
 952                 DRV_LOG(DEBUG,
 953                         "counter type = %d, num of cs = %ld, attributes = %d",
 954                         cs_desc.counter_type, cs_desc.num_of_cs,
 955                         cs_desc.attributes);
 956 #endif
 957                 config.ind_table_max_size =
 958                         attr.rss_caps.max_rwq_indirection_table_size;
 959                 /* Remove this check once DPDK supports larger/variable
 960                  * indirection tables. */
 961                 if (config.ind_table_max_size >
 962                                 (unsigned int)ETH_RSS_RETA_SIZE_512)
 963                         config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
 964                 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
 965                         config.ind_table_max_size);
 966                 config.hw_vlan_strip = !!(attr.raw_packet_caps &
 967                                          IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
 968                 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
 969                         (config.hw_vlan_strip ? "" : "not "));
 970
 971                 config.hw_fcs_strip = !!(attr.raw_packet_caps &
 972                                          IBV_RAW_PACKET_CAP_SCATTER_FCS);
 973                 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
 974                         (config.hw_fcs_strip ? "" : "not "));
 975
 976 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING
 977                 config.hw_padding = !!attr.rx_pad_end_addr_align;
 978 #endif
 979                 DRV_LOG(DEBUG,
 980                         "hardware Rx end alignment padding is %ssupported",
 981                         (config.hw_padding ? "" : "not "));
 982                 config.vf = vf;
 983                 config.tso = (attr.tso_caps.max_tso > 0 &&
 984                               (attr.tso_caps.supported_qpts &
 985                                (1 << IBV_QPT_RAW_PACKET)));
 986                 if (config.tso)
 987                         config.tso_max_payload_sz = attr.tso_caps.max_tso;
 988                 if (config.mps && !mps) {
 989                         DRV_LOG(ERR,
 990                                 "multi-packet send not supported on this device"
 991                                 " (" MLX5_TXQ_MPW_EN ")");
 992                         err = ENOTSUP;
 993                         goto error;
 994                 }
 995                 DRV_LOG(INFO, "%s MPS is %s",
 996                         config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
 997                         config.mps != MLX5_MPW_DISABLED ? "enabled" :
 998                         "disabled");
 999                 if (config.cqe_comp && !cqe_comp) {
1000                         DRV_LOG(WARNING, "Rx CQE compression isn't supported");
1001                         config.cqe_comp = 0;
1002                 }
1003                 if (config.mprq.enabled && mprq) {
1004                         if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
1005                             config.mprq.stride_num_n < mprq_min_stride_num_n) {
1006                                 config.mprq.stride_num_n =
1007                                         RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
1008                                                 mprq_min_stride_num_n);
1009                                 DRV_LOG(WARNING,
1010                                         "the number of strides"
1011                                         " for Multi-Packet RQ is out of range,"
1012                                         " setting default value (%u)",
1013                                         1 << config.mprq.stride_num_n);
1014                         }
1015                         config.mprq.min_stride_size_n = mprq_min_stride_size_n;
1016                         config.mprq.max_stride_size_n = mprq_max_stride_size_n;
1017                 } else if (config.mprq.enabled && !mprq) {
1018                         DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
1019                         config.mprq.enabled = 0;
1020                 }
1021                 eth_dev = rte_eth_dev_allocate(name);
1022                 if (eth_dev == NULL) {
1023                         DRV_LOG(ERR, "can not allocate rte ethdev");
1024                         err = ENOMEM;
1025                         goto error;
1026                 }
1027                 eth_dev->data->dev_private = priv;
1028                 priv->dev_data = eth_dev->data;
1029                 eth_dev->data->mac_addrs = priv->mac;
1030                 eth_dev->device = &pci_dev->device;
1031                 rte_eth_copy_pci_info(eth_dev, pci_dev);
1032                 eth_dev->device->driver = &mlx5_driver.driver;
1033                 err = mlx5_uar_init_primary(eth_dev);
1034                 if (err) {
1035                         err = rte_errno;
1036                         goto error;
1037                 }
1038                 /* Configure the first MAC address by default. */
1039                 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1040                         DRV_LOG(ERR,
1041                                 "port %u cannot get MAC address, is mlx5_en"
1042                                 " loaded? (errno: %s)",
1043                                 eth_dev->data->port_id, strerror(rte_errno));
1044                         err = ENODEV;
1045                         goto error;
1046                 }
1047                 DRV_LOG(INFO,
1048                         "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
1049                         eth_dev->data->port_id,
1050                         mac.addr_bytes[0], mac.addr_bytes[1],
1051                         mac.addr_bytes[2], mac.addr_bytes[3],
1052                         mac.addr_bytes[4], mac.addr_bytes[5]);
1053 #ifndef NDEBUG
1054                 {
1055                         char ifname[IF_NAMESIZE];
1056
1057                         if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1058                                 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
1059                                         eth_dev->data->port_id, ifname);
1060                         else
1061                                 DRV_LOG(DEBUG, "port %u ifname is unknown",
1062                                         eth_dev->data->port_id);
1063                 }
1064 #endif
1065                 /* Get actual MTU if possible. */
1066                 err = mlx5_get_mtu(eth_dev, &priv->mtu);
1067                 if (err) {
1068                         err = rte_errno;
1069                         goto error;
1070                 }
1071                 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1072                         priv->mtu);
1073                 /*
1074                  * Initialize burst functions to prevent crashes before link-up.
1075                  */
1076                 eth_dev->rx_pkt_burst = removed_rx_burst;
1077                 eth_dev->tx_pkt_burst = removed_tx_burst;
1078                 eth_dev->dev_ops = &mlx5_dev_ops;
1079                 /* Register MAC address. */
1080                 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1081                 priv->nl_socket = -1;
1082                 priv->nl_sn = 0;
1083                 if (vf && config.vf_nl_en) {
1084                         priv->nl_socket = mlx5_nl_init(RTMGRP_LINK);
1085                         if (priv->nl_socket < 0)
1086                                 priv->nl_socket = -1;
1087                         mlx5_nl_mac_addr_sync(eth_dev);
1088                 }
1089                 TAILQ_INIT(&priv->flows);
1090                 TAILQ_INIT(&priv->ctrl_flows);
1091                 /* Hint libmlx5 to use PMD allocator for data plane resources */
1092                 struct mlx5dv_ctx_allocators alctr = {
1093                         .alloc = &mlx5_alloc_verbs_buf,
1094                         .free = &mlx5_free_verbs_buf,
1095                         .data = priv,
1096                 };
1097                 mlx5_glue->dv_set_context_attr(ctx,
1098                                                MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
1099                                                (void *)((uintptr_t)&alctr));
1100                 /* Bring Ethernet device up. */
1101                 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
1102                         eth_dev->data->port_id);
1103                 mlx5_set_link_up(eth_dev);
1104                 /*
1105                  * Even though the interrupt handler is not installed yet,
1106                  * interrupts will still trigger on the asyn_fd from
1107                  * Verbs context returned by ibv_open_device().
1108                  */
1109                 mlx5_link_update(eth_dev, 0);
1110                 /* Store device configuration on private structure. */
1111                 priv->config = config;
1112                 /* Create drop queue. */
1113                 err = mlx5_flow_create_drop_queue(eth_dev);
1114                 if (err) {
1115                         DRV_LOG(ERR, "port %u drop queue allocation failed: %s",
1116                                 eth_dev->data->port_id, strerror(rte_errno));
1117                         err = rte_errno;
1118                         goto error;
1119                 }
1120                 /* Supported Verbs flow priority number detection. */
1121                 if (verb_priorities == 0)
1122                         verb_priorities = mlx5_get_max_verbs_prio(eth_dev);
1123                 if (verb_priorities < MLX5_VERBS_FLOW_PRIO_8) {
1124                         DRV_LOG(ERR, "port %u wrong Verbs flow priorities: %u",
1125                                 eth_dev->data->port_id, verb_priorities);
1126                         err = ENOTSUP;
1127                         goto error;
1128                 }
1129                 priv->config.max_verbs_prio = verb_priorities;
1130                 /*
1131                  * Once the device is added to the list of memory event
1132                  * callback, its global MR cache table cannot be expanded
1133                  * on the fly because of deadlock. If it overflows, lookup
1134                  * should be done by searching MR list linearly, which is slow.
1135                  */
1136                 err = mlx5_mr_btree_init(&priv->mr.cache,
1137                                          MLX5_MR_BTREE_CACHE_N * 2,
1138                                          eth_dev->device->numa_node);
1139                 if (err) {
1140                         err = rte_errno;
1141                         goto error;
1142                 }
1143                 /* Add device to memory callback list. */
1144                 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1145                 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1146                                  priv, mem_event_cb);
1147                 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1148                 rte_eth_dev_probing_finish(eth_dev);
1149                 return 0;
1150         }
1151 error:
1152         if (priv)
1153                 rte_free(priv);
1154         if (pd)
1155                 claim_zero(mlx5_glue->dealloc_pd(pd));
1156         if (eth_dev)
1157                 rte_eth_dev_release_port(eth_dev);
1158         if (ctx)
1159                 claim_zero(mlx5_glue->close_device(ctx));
1160         if (err) {
1161                 rte_errno = err;
1162                 return -rte_errno;
1163         }
1164         return 0;
1165 }
1166
1167 static const struct rte_pci_id mlx5_pci_id_map[] = {
1168         {
1169                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1170                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1171         },
1172         {
1173                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1174                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1175         },
1176         {
1177                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1178                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1179         },
1180         {
1181                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1182                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1183         },
1184         {
1185                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1186                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1187         },
1188         {
1189                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1190                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1191         },
1192         {
1193                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1194                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1195         },
1196         {
1197                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1198                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1199         },
1200         {
1201                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1202                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1203         },
1204         {
1205                 .vendor_id = 0
1206         }
1207 };
1208
1209 static struct rte_pci_driver mlx5_driver = {
1210         .driver = {
1211                 .name = MLX5_DRIVER_NAME
1212         },
1213         .id_table = mlx5_pci_id_map,
1214         .probe = mlx5_pci_probe,
1215         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV,
1216 };
1217
1218 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1219
1220 /**
1221  * Suffix RTE_EAL_PMD_PATH with "-glue".
1222  *
1223  * This function performs a sanity check on RTE_EAL_PMD_PATH before
1224  * suffixing its last component.
1225  *
1226  * @param buf[out]
1227  *   Output buffer, should be large enough otherwise NULL is returned.
1228  * @param size
1229  *   Size of @p out.
1230  *
1231  * @return
1232  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
1233  */
1234 static char *
1235 mlx5_glue_path(char *buf, size_t size)
1236 {
1237         static const char *const bad[] = { "/", ".", "..", NULL };
1238         const char *path = RTE_EAL_PMD_PATH;
1239         size_t len = strlen(path);
1240         size_t off;
1241         int i;
1242
1243         while (len && path[len - 1] == '/')
1244                 --len;
1245         for (off = len; off && path[off - 1] != '/'; --off)
1246                 ;
1247         for (i = 0; bad[i]; ++i)
1248                 if (!strncmp(path + off, bad[i], (int)(len - off)))
1249                         goto error;
1250         i = snprintf(buf, size, "%.*s-glue", (int)len, path);
1251         if (i == -1 || (size_t)i >= size)
1252                 goto error;
1253         return buf;
1254 error:
1255         DRV_LOG(ERR,
1256                 "unable to append \"-glue\" to last component of"
1257                 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
1258                 " please re-configure DPDK");
1259         return NULL;
1260 }
1261
1262 /**
1263  * Initialization routine for run-time dependency on rdma-core.
1264  */
1265 static int
1266 mlx5_glue_init(void)
1267 {
1268         char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
1269         const char *path[] = {
1270                 /*
1271                  * A basic security check is necessary before trusting
1272                  * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
1273                  */
1274                 (geteuid() == getuid() && getegid() == getgid() ?
1275                  getenv("MLX5_GLUE_PATH") : NULL),
1276                 /*
1277                  * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
1278                  * variant, otherwise let dlopen() look up libraries on its
1279                  * own.
1280                  */
1281                 (*RTE_EAL_PMD_PATH ?
1282                  mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
1283         };
1284         unsigned int i = 0;
1285         void *handle = NULL;
1286         void **sym;
1287         const char *dlmsg;
1288
1289         while (!handle && i != RTE_DIM(path)) {
1290                 const char *end;
1291                 size_t len;
1292                 int ret;
1293
1294                 if (!path[i]) {
1295                         ++i;
1296                         continue;
1297                 }
1298                 end = strpbrk(path[i], ":;");
1299                 if (!end)
1300                         end = path[i] + strlen(path[i]);
1301                 len = end - path[i];
1302                 ret = 0;
1303                 do {
1304                         char name[ret + 1];
1305
1306                         ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
1307                                        (int)len, path[i],
1308                                        (!len || *(end - 1) == '/') ? "" : "/");
1309                         if (ret == -1)
1310                                 break;
1311                         if (sizeof(name) != (size_t)ret + 1)
1312                                 continue;
1313                         DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
1314                                 name);
1315                         handle = dlopen(name, RTLD_LAZY);
1316                         break;
1317                 } while (1);
1318                 path[i] = end + 1;
1319                 if (!*end)
1320                         ++i;
1321         }
1322         if (!handle) {
1323                 rte_errno = EINVAL;
1324                 dlmsg = dlerror();
1325                 if (dlmsg)
1326                         DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
1327                 goto glue_error;
1328         }
1329         sym = dlsym(handle, "mlx5_glue");
1330         if (!sym || !*sym) {
1331                 rte_errno = EINVAL;
1332                 dlmsg = dlerror();
1333                 if (dlmsg)
1334                         DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
1335                 goto glue_error;
1336         }
1337         mlx5_glue = *sym;
1338         return 0;
1339 glue_error:
1340         if (handle)
1341                 dlclose(handle);
1342         DRV_LOG(WARNING,
1343                 "cannot initialize PMD due to missing run-time dependency on"
1344                 " rdma-core libraries (libibverbs, libmlx5)");
1345         return -rte_errno;
1346 }
1347
1348 #endif
1349
1350 /**
1351  * Driver initialization routine.
1352  */
1353 RTE_INIT(rte_mlx5_pmd_init)
1354 {
1355         /* Initialize driver log type. */
1356         mlx5_logtype = rte_log_register("pmd.net.mlx5");
1357         if (mlx5_logtype >= 0)
1358                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
1359
1360         /* Build the static tables for Verbs conversion. */
1361         mlx5_set_ptype_table();
1362         mlx5_set_cksum_table();
1363         mlx5_set_swp_types_table();
1364         /*
1365          * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
1366          * huge pages. Calling ibv_fork_init() during init allows
1367          * applications to use fork() safely for purposes other than
1368          * using this PMD, which is not supported in forked processes.
1369          */
1370         setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
1371         /* Match the size of Rx completion entry to the size of a cacheline. */
1372         if (RTE_CACHE_LINE_SIZE == 128)
1373                 setenv("MLX5_CQE_SIZE", "128", 0);
1374         /*
1375          * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
1376          * cleanup all the Verbs resources even when the device was removed.
1377          */
1378         setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
1379 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS
1380         if (mlx5_glue_init())
1381                 return;
1382         assert(mlx5_glue);
1383 #endif
1384 #ifndef NDEBUG
1385         /* Glue structure must not contain any NULL pointers. */
1386         {
1387                 unsigned int i;
1388
1389                 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
1390                         assert(((const void *const *)mlx5_glue)[i]);
1391         }
1392 #endif
1393         if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
1394                 DRV_LOG(ERR,
1395                         "rdma-core glue \"%s\" mismatch: \"%s\" is required",
1396                         mlx5_glue->version, MLX5_GLUE_VERSION);
1397                 return;
1398         }
1399         mlx5_glue->fork_init();
1400         rte_pci_register(&mlx5_driver);
1401 }
1402
1403 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1404 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1405 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");