drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_legacy_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355 };
 356
 357
 358 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 359 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 360
 361 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 362
 363 /**
 364  * Decide whether representor ID is a HPF(host PF) port on BF2.
 365  *
 366  * @param dev
 367  *   Pointer to Ethernet device structure.
 368  *
 369  * @return
 370  *   Non-zero if HPF, otherwise 0.
 371  */
 372 bool
 373 mlx5_is_hpf(struct rte_eth_dev *dev)
 374 {
 375         struct mlx5_priv *priv = dev->data->dev_private;
 376         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 377         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 378
 379         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 380                MLX5_REPRESENTOR_REPR(-1) == repr;
 381 }
 382
 383 /**
 384  * Initialize the ASO aging management structure.
 385  *
 386  * @param[in] sh
 387  *   Pointer to mlx5_dev_ctx_shared object to free
 388  *
 389  * @return
 390  *   0 on success, a negative errno value otherwise and rte_errno is set.
 391  */
 392 int
 393 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 394 {
 395         int err;
 396
 397         if (sh->aso_age_mng)
 398                 return 0;
 399         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 400                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 401         if (!sh->aso_age_mng) {
 402                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 403                 rte_errno = ENOMEM;
 404                 return -ENOMEM;
 405         }
 406         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 407         if (err) {
 408                 mlx5_free(sh->aso_age_mng);
 409                 return -1;
 410         }
 411         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 412         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 413         LIST_INIT(&sh->aso_age_mng->free);
 414         return 0;
 415 }
 416
 417 /**
 418  * Close and release all the resources of the ASO aging management structure.
 419  *
 420  * @param[in] sh
 421  *   Pointer to mlx5_dev_ctx_shared object to free.
 422  */
 423 static void
 424 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 425 {
 426         int i, j;
 427
 428         mlx5_aso_flow_hit_queue_poll_stop(sh);
 429         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 430         if (sh->aso_age_mng->pools) {
 431                 struct mlx5_aso_age_pool *pool;
 432
 433                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 434                         pool = sh->aso_age_mng->pools[i];
 435                         claim_zero(mlx5_devx_cmd_destroy
 436                                                 (pool->flow_hit_aso_obj));
 437                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 438                                 if (pool->actions[j].dr_action)
 439                                         claim_zero
 440                                             (mlx5_flow_os_destroy_flow_action
 441                                               (pool->actions[j].dr_action));
 442                         mlx5_free(pool);
 443                 }
 444                 mlx5_free(sh->aso_age_mng->pools);
 445         }
 446         mlx5_free(sh->aso_age_mng);
 447 }
 448
 449 /**
 450  * Initialize the shared aging list information per port.
 451  *
 452  * @param[in] sh
 453  *   Pointer to mlx5_dev_ctx_shared object.
 454  */
 455 static void
 456 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 457 {
 458         uint32_t i;
 459         struct mlx5_age_info *age_info;
 460
 461         for (i = 0; i < sh->max_port; i++) {
 462                 age_info = &sh->port[i].age_info;
 463                 age_info->flags = 0;
 464                 TAILQ_INIT(&age_info->aged_counters);
 465                 LIST_INIT(&age_info->aged_aso);
 466                 rte_spinlock_init(&age_info->aged_sl);
 467                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 468         }
 469 }
 470
 471 /**
 472  * Initialize the counters management structure.
 473  *
 474  * @param[in] sh
 475  *   Pointer to mlx5_dev_ctx_shared object to free
 476  */
 477 static void
 478 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 479 {
 480         int i;
 481
 482         memset(&sh->cmng, 0, sizeof(sh->cmng));
 483         TAILQ_INIT(&sh->cmng.flow_counters);
 484         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 485         sh->cmng.max_id = -1;
 486         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 487         rte_spinlock_init(&sh->cmng.pool_update_sl);
 488         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 489                 TAILQ_INIT(&sh->cmng.counters[i]);
 490                 rte_spinlock_init(&sh->cmng.csl[i]);
 491         }
 492 }
 493
 494 /**
 495  * Destroy all the resources allocated for a counter memory management.
 496  *
 497  * @param[in] mng
 498  *   Pointer to the memory management structure.
 499  */
 500 static void
 501 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 502 {
 503         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 504
 505         LIST_REMOVE(mng, next);
 506         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 507         claim_zero(mlx5_os_umem_dereg(mng->umem));
 508         mlx5_free(mem);
 509 }
 510
 511 /**
 512  * Close and release all the resources of the counters management.
 513  *
 514  * @param[in] sh
 515  *   Pointer to mlx5_dev_ctx_shared object to free.
 516  */
 517 static void
 518 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 519 {
 520         struct mlx5_counter_stats_mem_mng *mng;
 521         int i, j;
 522         int retries = 1024;
 523
 524         rte_errno = 0;
 525         while (--retries) {
 526                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 527                 if (rte_errno != EINPROGRESS)
 528                         break;
 529                 rte_pause();
 530         }
 531
 532         if (sh->cmng.pools) {
 533                 struct mlx5_flow_counter_pool *pool;
 534                 uint16_t n_valid = sh->cmng.n_valid;
 535                 bool fallback = sh->cmng.counter_fallback;
 536
 537                 for (i = 0; i < n_valid; ++i) {
 538                         pool = sh->cmng.pools[i];
 539                         if (!fallback && pool->min_dcs)
 540                                 claim_zero(mlx5_devx_cmd_destroy
 541                                                                (pool->min_dcs));
 542                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 543                                 struct mlx5_flow_counter *cnt =
 544                                                 MLX5_POOL_GET_CNT(pool, j);
 545
 546                                 if (cnt->action)
 547                                         claim_zero
 548                                          (mlx5_flow_os_destroy_flow_action
 549                                           (cnt->action));
 550                                 if (fallback && MLX5_POOL_GET_CNT
 551                                     (pool, j)->dcs_when_free)
 552                                         claim_zero(mlx5_devx_cmd_destroy
 553                                                    (cnt->dcs_when_free));
 554                         }
 555                         mlx5_free(pool);
 556                 }
 557                 mlx5_free(sh->cmng.pools);
 558         }
 559         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 560         while (mng) {
 561                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 562                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 563         }
 564         memset(&sh->cmng, 0, sizeof(sh->cmng));
 565 }
 566
 567 /**
 568  * Initialize the aso flow meters management structure.
 569  *
 570  * @param[in] sh
 571  *   Pointer to mlx5_dev_ctx_shared object to free
 572  */
 573 int
 574 mlx5_aso_flow_mtrs_mng_init(struct mlx5_priv *priv)
 575 {
 576         if (!priv->mtr_idx_tbl) {
 577                 priv->mtr_idx_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 578                 if (!priv->mtr_idx_tbl) {
 579                         DRV_LOG(ERR, "fail to create meter lookup table.");
 580                         rte_errno = ENOMEM;
 581                         return -ENOMEM;
 582                 }
 583         }
 584         if (!priv->sh->mtrmng) {
 585                 priv->sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 586                         sizeof(*priv->sh->mtrmng),
 587                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 588                 if (!priv->sh->mtrmng) {
 589                         DRV_LOG(ERR, "mlx5_aso_mtr_pools_mng allocation was failed.");
 590                         rte_errno = ENOMEM;
 591                         return -ENOMEM;
 592                 }
 593                 rte_spinlock_init(&priv->sh->mtrmng->mtrsl);
 594                 LIST_INIT(&priv->sh->mtrmng->meters);
 595         }
 596         return 0;
 597 }
 598
 599 /**
 600  * Close and release all the resources of
 601  * the ASO flow meter management structure.
 602  *
 603  * @param[in] sh
 604  *   Pointer to mlx5_dev_ctx_shared object to free.
 605  */
 606 static void
 607 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 608 {
 609         struct mlx5_aso_mtr_pool *mtr_pool;
 610         struct mlx5_aso_mtr_pools_mng *mtrmng = sh->mtrmng;
 611         uint32_t idx;
 612 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 613         struct mlx5_aso_mtr *aso_mtr;
 614         int i;
 615 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 616
 617         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 618         idx = mtrmng->n_valid;
 619         while (idx--) {
 620                 mtr_pool = mtrmng->pools[idx];
 621 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 622                 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 623                         aso_mtr = &mtr_pool->mtrs[i];
 624                         if (aso_mtr->fm.meter_action)
 625                                 claim_zero(mlx5_glue->destroy_flow_action
 626                                                 (aso_mtr->fm.meter_action));
 627                 }
 628 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 629                 claim_zero(mlx5_devx_cmd_destroy
 630                                                 (mtr_pool->devx_obj));
 631                 mtrmng->n_valid--;
 632                 mlx5_free(mtr_pool);
 633         }
 634         mlx5_free(sh->mtrmng->pools);
 635         mlx5_free(sh->mtrmng);
 636         sh->mtrmng = NULL;
 637 }
 638
 639 /* Send FLOW_AGED event if needed. */
 640 void
 641 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 642 {
 643         struct mlx5_age_info *age_info;
 644         uint32_t i;
 645
 646         for (i = 0; i < sh->max_port; i++) {
 647                 age_info = &sh->port[i].age_info;
 648                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 649                         continue;
 650                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 651                         rte_eth_dev_callback_process
 652                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 653                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 654                 age_info->flags = 0;
 655         }
 656 }
 657
 658 /**
 659  * Initialize the flow resources' indexed mempool.
 660  *
 661  * @param[in] sh
 662  *   Pointer to mlx5_dev_ctx_shared object.
 663  * @param[in] sh
 664  *   Pointer to user dev config.
 665  */
 666 static void
 667 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 668                        const struct mlx5_dev_config *config)
 669 {
 670         uint8_t i;
 671         struct mlx5_indexed_pool_config cfg;
 672
 673         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 674                 cfg = mlx5_ipool_cfg[i];
 675                 switch (i) {
 676                 default:
 677                         break;
 678                 /*
 679                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 680                  * according to PCI function flow configuration.
 681                  */
 682                 case MLX5_IPOOL_MLX5_FLOW:
 683                         cfg.size = config->dv_flow_en ?
 684                                 sizeof(struct mlx5_flow_handle) :
 685                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 686                         break;
 687                 }
 688                 if (config->reclaim_mode)
 689                         cfg.release_mem_en = 1;
 690                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 691         }
 692 }
 693
 694 /**
 695  * Release the flow resources' indexed mempool.
 696  *
 697  * @param[in] sh
 698  *   Pointer to mlx5_dev_ctx_shared object.
 699  */
 700 static void
 701 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 702 {
 703         uint8_t i;
 704
 705         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 706                 mlx5_ipool_destroy(sh->ipool[i]);
 707 }
 708
 709 /*
 710  * Check if dynamic flex parser for eCPRI already exists.
 711  *
 712  * @param dev
 713  *   Pointer to Ethernet device structure.
 714  *
 715  * @return
 716  *   true on exists, false on not.
 717  */
 718 bool
 719 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 720 {
 721         struct mlx5_priv *priv = dev->data->dev_private;
 722         struct mlx5_flex_parser_profiles *prf =
 723                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 724
 725         return !!prf->obj;
 726 }
 727
 728 /*
 729  * Allocation of a flex parser for eCPRI. Once created, this parser related
 730  * resources will be held until the device is closed.
 731  *
 732  * @param dev
 733  *   Pointer to Ethernet device structure.
 734  *
 735  * @return
 736  *   0 on success, a negative errno value otherwise and rte_errno is set.
 737  */
 738 int
 739 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 740 {
 741         struct mlx5_priv *priv = dev->data->dev_private;
 742         struct mlx5_flex_parser_profiles *prf =
 743                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 744         struct mlx5_devx_graph_node_attr node = {
 745                 .modify_field_select = 0,
 746         };
 747         uint32_t ids[8];
 748         int ret;
 749
 750         if (!priv->config.hca_attr.parse_graph_flex_node) {
 751                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 752                         "for device %s.", priv->dev_data->name);
 753                 return -ENOTSUP;
 754         }
 755         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 756         /* 8 bytes now: 4B common header + 4B message body header. */
 757         node.header_length_base_value = 0x8;
 758         /* After MAC layer: Ether / VLAN. */
 759         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 760         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 761         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 762         /* Sample #0: type in common header. */
 763         node.sample[0].flow_match_sample_en = 1;
 764         /* Fixed offset. */
 765         node.sample[0].flow_match_sample_offset_mode = 0x0;
 766         /* Only the 2nd byte will be used. */
 767         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 768         /* Sample #1: message payload. */
 769         node.sample[1].flow_match_sample_en = 1;
 770         /* Fixed offset. */
 771         node.sample[1].flow_match_sample_offset_mode = 0x0;
 772         /*
 773          * Only the first two bytes will be used right now, and its offset will
 774          * start after the common header that with the length of a DW(u32).
 775          */
 776         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 777         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 778         if (!prf->obj) {
 779                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 780                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 781         }
 782         prf->num = 2;
 783         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 784         if (ret) {
 785                 DRV_LOG(ERR, "Failed to query sample IDs.");
 786                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 787         }
 788         prf->offset[0] = 0x0;
 789         prf->offset[1] = sizeof(uint32_t);
 790         prf->ids[0] = ids[0];
 791         prf->ids[1] = ids[1];
 792         return 0;
 793 }
 794
 795 /*
 796  * Destroy the flex parser node, including the parser itself, input / output
 797  * arcs and DW samples. Resources could be reused then.
 798  *
 799  * @param dev
 800  *   Pointer to Ethernet device structure.
 801  */
 802 static void
 803 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 804 {
 805         struct mlx5_priv *priv = dev->data->dev_private;
 806         struct mlx5_flex_parser_profiles *prf =
 807                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 808
 809         if (prf->obj)
 810                 mlx5_devx_cmd_destroy(prf->obj);
 811         prf->obj = NULL;
 812 }
 813
 814 /*
 815  * Allocate Rx and Tx UARs in robust fashion.
 816  * This routine handles the following UAR allocation issues:
 817  *
 818  *  - tries to allocate the UAR with the most appropriate memory
 819  *    mapping type from the ones supported by the host
 820  *
 821  *  - tries to allocate the UAR with non-NULL base address
 822  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 823  *    UAR base address if UAR was not the first object in the UAR page.
 824  *    It caused the PMD failure and we should try to get another UAR
 825  *    till we get the first one with non-NULL base address returned.
 826  */
 827 static int
 828 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 829                      const struct mlx5_dev_config *config)
 830 {
 831         uint32_t uar_mapping, retry;
 832         int err = 0;
 833         void *base_addr;
 834
 835         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 836 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 837                 /* Control the mapping type according to the settings. */
 838                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 839                               MLX5DV_UAR_ALLOC_TYPE_NC :
 840                               MLX5DV_UAR_ALLOC_TYPE_BF;
 841 #else
 842                 RTE_SET_USED(config);
 843                 /*
 844                  * It seems we have no way to control the memory mapping type
 845                  * for the UAR, the default "Write-Combining" type is supposed.
 846                  * The UAR initialization on queue creation queries the
 847                  * actual mapping type done by Verbs/kernel and setups the
 848                  * PMD datapath accordingly.
 849                  */
 850                 uar_mapping = 0;
 851 #endif
 852                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 853 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 854                 if (!sh->tx_uar &&
 855                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 856                         if (config->dbnc == MLX5_TXDB_CACHED ||
 857                             config->dbnc == MLX5_TXDB_HEURISTIC)
 858                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 859                                                  "is not supported by DevX");
 860                         /*
 861                          * In some environments like virtual machine
 862                          * the Write Combining mapped might be not supported
 863                          * and UAR allocation fails. We try "Non-Cached"
 864                          * mapping for the case. The tx_burst routines take
 865                          * the UAR mapping type into account on UAR setup
 866                          * on queue creation.
 867                          */
 868                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 869                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 870                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 871                                                         (sh->ctx, uar_mapping);
 872                 } else if (!sh->tx_uar &&
 873                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 874                         if (config->dbnc == MLX5_TXDB_NCACHED)
 875                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 876                                                  "is not supported by DevX");
 877                         /*
 878                          * If Verbs/kernel does not support "Non-Cached"
 879                          * try the "Write-Combining".
 880                          */
 881                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 882                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 883                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 884                                                         (sh->ctx, uar_mapping);
 885                 }
 886 #endif
 887                 if (!sh->tx_uar) {
 888                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 889                         err = ENOMEM;
 890                         goto exit;
 891                 }
 892                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 893                 if (base_addr)
 894                         break;
 895                 /*
 896                  * The UARs are allocated by rdma_core within the
 897                  * IB device context, on context closure all UARs
 898                  * will be freed, should be no memory/object leakage.
 899                  */
 900                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 901                 sh->tx_uar = NULL;
 902         }
 903         /* Check whether we finally succeeded with valid UAR allocation. */
 904         if (!sh->tx_uar) {
 905                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 906                 err = ENOMEM;
 907                 goto exit;
 908         }
 909         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 910                 uar_mapping = 0;
 911                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 912                                                         (sh->ctx, uar_mapping);
 913 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 914                 if (!sh->devx_rx_uar &&
 915                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 916                         /*
 917                          * Rx UAR is used to control interrupts only,
 918                          * should be no datapath noticeable impact,
 919                          * can try "Non-Cached" mapping safely.
 920                          */
 921                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 922                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 923                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 924                                                         (sh->ctx, uar_mapping);
 925                 }
 926 #endif
 927                 if (!sh->devx_rx_uar) {
 928                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 929                         err = ENOMEM;
 930                         goto exit;
 931                 }
 932                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 933                 if (base_addr)
 934                         break;
 935                 /*
 936                  * The UARs are allocated by rdma_core within the
 937                  * IB device context, on context closure all UARs
 938                  * will be freed, should be no memory/object leakage.
 939                  */
 940                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 941                 sh->devx_rx_uar = NULL;
 942         }
 943         /* Check whether we finally succeeded with valid UAR allocation. */
 944         if (!sh->devx_rx_uar) {
 945                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 946                 err = ENOMEM;
 947         }
 948 exit:
 949         return err;
 950 }
 951
 952 /**
 953  * Allocate shared device context. If there is multiport device the
 954  * master and representors will share this context, if there is single
 955  * port dedicated device, the context will be used by only given
 956  * port due to unification.
 957  *
 958  * Routine first searches the context for the specified device name,
 959  * if found the shared context assumed and reference counter is incremented.
 960  * If no context found the new one is created and initialized with specified
 961  * device context and parameters.
 962  *
 963  * @param[in] spawn
 964  *   Pointer to the device attributes (name, port, etc).
 965  * @param[in] config
 966  *   Pointer to device configuration structure.
 967  *
 968  * @return
 969  *   Pointer to mlx5_dev_ctx_shared object on success,
 970  *   otherwise NULL and rte_errno is set.
 971  */
 972 struct mlx5_dev_ctx_shared *
 973 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 974                            const struct mlx5_dev_config *config)
 975 {
 976         struct mlx5_dev_ctx_shared *sh;
 977         int err = 0;
 978         uint32_t i;
 979         struct mlx5_devx_tis_attr tis_attr = { 0 };
 980
 981         MLX5_ASSERT(spawn);
 982         /* Secondary process should not create the shared context. */
 983         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 984         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 985         /* Search for IB context by device name. */
 986         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 987                 if (!strcmp(sh->ibdev_name,
 988                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 989                         sh->refcnt++;
 990                         goto exit;
 991                 }
 992         }
 993         /* No device found, we have to create new shared context. */
 994         MLX5_ASSERT(spawn->max_port);
 995         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 996                          sizeof(struct mlx5_dev_ctx_shared) +
 997                          spawn->max_port *
 998                          sizeof(struct mlx5_dev_shared_port),
 999                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1000         if (!sh) {
1001                 DRV_LOG(ERR, "shared context allocation failure");
1002                 rte_errno  = ENOMEM;
1003                 goto exit;
1004         }
1005         if (spawn->bond_info)
1006                 sh->bond = *spawn->bond_info;
1007         err = mlx5_os_open_device(spawn, config, sh);
1008         if (!sh->ctx)
1009                 goto error;
1010         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1011         if (err) {
1012                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1013                 goto error;
1014         }
1015         sh->refcnt = 1;
1016         sh->max_port = spawn->max_port;
1017         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1018                 sizeof(sh->ibdev_name) - 1);
1019         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1020                 sizeof(sh->ibdev_path) - 1);
1021         /*
1022          * Setting port_id to max unallowed value means
1023          * there is no interrupt subhandler installed for
1024          * the given port index i.
1025          */
1026         for (i = 0; i < sh->max_port; i++) {
1027                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1028                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1029         }
1030         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1031         if (sh->pd == NULL) {
1032                 DRV_LOG(ERR, "PD allocation failure");
1033                 err = ENOMEM;
1034                 goto error;
1035         }
1036         if (sh->devx) {
1037                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1038                 if (err) {
1039                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1040                         goto error;
1041                 }
1042                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1043                 if (!sh->td) {
1044                         DRV_LOG(ERR, "TD allocation failure");
1045                         err = ENOMEM;
1046                         goto error;
1047                 }
1048                 tis_attr.transport_domain = sh->td->id;
1049                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1050                 if (!sh->tis) {
1051                         DRV_LOG(ERR, "TIS allocation failure");
1052                         err = ENOMEM;
1053                         goto error;
1054                 }
1055                 err = mlx5_alloc_rxtx_uars(sh, config);
1056                 if (err)
1057                         goto error;
1058                 MLX5_ASSERT(sh->tx_uar);
1059                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1060
1061                 MLX5_ASSERT(sh->devx_rx_uar);
1062                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1063         }
1064 #ifndef RTE_ARCH_64
1065         /* Initialize UAR access locks for 32bit implementations. */
1066         rte_spinlock_init(&sh->uar_lock_cq);
1067         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1068                 rte_spinlock_init(&sh->uar_lock[i]);
1069 #endif
1070         /*
1071          * Once the device is added to the list of memory event
1072          * callback, its global MR cache table cannot be expanded
1073          * on the fly because of deadlock. If it overflows, lookup
1074          * should be done by searching MR list linearly, which is slow.
1075          *
1076          * At this point the device is not added to the memory
1077          * event list yet, context is just being created.
1078          */
1079         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1080                                  MLX5_MR_BTREE_CACHE_N * 2,
1081                                  spawn->pci_dev->device.numa_node);
1082         if (err) {
1083                 err = rte_errno;
1084                 goto error;
1085         }
1086         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1087                               &sh->share_cache.dereg_mr_cb);
1088         mlx5_os_dev_shared_handler_install(sh);
1089         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1090         if (!sh->cnt_id_tbl) {
1091                 err = rte_errno;
1092                 goto error;
1093         }
1094         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1095                 err = mlx5_flow_os_init_workspace_once();
1096                 if (err)
1097                         goto error;
1098         }
1099         mlx5_flow_aging_init(sh);
1100         mlx5_flow_counters_mng_init(sh);
1101         mlx5_flow_ipool_create(sh, config);
1102         /* Add device to memory callback list. */
1103         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1104         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1105                          sh, mem_event_cb);
1106         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1107         /* Add context to the global device list. */
1108         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1109         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1110 exit:
1111         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1112         return sh;
1113 error:
1114         pthread_mutex_destroy(&sh->txpp.mutex);
1115         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1116         MLX5_ASSERT(sh);
1117         if (sh->cnt_id_tbl)
1118                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1119         if (sh->tis)
1120                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1121         if (sh->td)
1122                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1123         if (sh->devx_rx_uar)
1124                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1125         if (sh->tx_uar)
1126                 mlx5_glue->devx_free_uar(sh->tx_uar);
1127         if (sh->pd)
1128                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1129         if (sh->ctx)
1130                 claim_zero(mlx5_glue->close_device(sh->ctx));
1131         mlx5_free(sh);
1132         MLX5_ASSERT(err > 0);
1133         rte_errno = err;
1134         return NULL;
1135 }
1136
1137 /**
1138  * Free shared IB device context. Decrement counter and if zero free
1139  * all allocated resources and close handles.
1140  *
1141  * @param[in] sh
1142  *   Pointer to mlx5_dev_ctx_shared object to free
1143  */
1144 void
1145 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1146 {
1147         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1148 #ifdef RTE_LIBRTE_MLX5_DEBUG
1149         /* Check the object presence in the list. */
1150         struct mlx5_dev_ctx_shared *lctx;
1151
1152         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1153                 if (lctx == sh)
1154                         break;
1155         MLX5_ASSERT(lctx);
1156         if (lctx != sh) {
1157                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1158                 goto exit;
1159         }
1160 #endif
1161         MLX5_ASSERT(sh);
1162         MLX5_ASSERT(sh->refcnt);
1163         /* Secondary process should not free the shared context. */
1164         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1165         if (--sh->refcnt)
1166                 goto exit;
1167         /* Remove from memory callback device list. */
1168         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1169         LIST_REMOVE(sh, mem_event_cb);
1170         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1171         /* Release created Memory Regions. */
1172         mlx5_mr_release_cache(&sh->share_cache);
1173         /* Remove context from the global device list. */
1174         LIST_REMOVE(sh, next);
1175         /* Release flow workspaces objects on the last device. */
1176         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1177                 mlx5_flow_os_release_workspace();
1178         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1179         /*
1180          *  Ensure there is no async event handler installed.
1181          *  Only primary process handles async device events.
1182          **/
1183         mlx5_flow_counters_mng_close(sh);
1184         if (sh->aso_age_mng) {
1185                 mlx5_flow_aso_age_mng_close(sh);
1186                 sh->aso_age_mng = NULL;
1187         }
1188         if (sh->mtrmng)
1189                 mlx5_aso_flow_mtrs_mng_close(sh);
1190         mlx5_flow_ipool_destroy(sh);
1191         mlx5_os_dev_shared_handler_uninstall(sh);
1192         if (sh->cnt_id_tbl) {
1193                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1194                 sh->cnt_id_tbl = NULL;
1195         }
1196         if (sh->tx_uar) {
1197                 mlx5_glue->devx_free_uar(sh->tx_uar);
1198                 sh->tx_uar = NULL;
1199         }
1200         if (sh->pd)
1201                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1202         if (sh->tis)
1203                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1204         if (sh->td)
1205                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1206         if (sh->devx_rx_uar)
1207                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1208         if (sh->ctx)
1209                 claim_zero(mlx5_glue->close_device(sh->ctx));
1210         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1211         pthread_mutex_destroy(&sh->txpp.mutex);
1212         mlx5_free(sh);
1213         return;
1214 exit:
1215         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1216 }
1217
1218 /**
1219  * Destroy table hash list.
1220  *
1221  * @param[in] priv
1222  *   Pointer to the private device data structure.
1223  */
1224 void
1225 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1226 {
1227         struct mlx5_dev_ctx_shared *sh = priv->sh;
1228
1229         if (!sh->flow_tbls)
1230                 return;
1231         mlx5_hlist_destroy(sh->flow_tbls);
1232 }
1233
1234 /**
1235  * Initialize flow table hash list and create the root tables entry
1236  * for each domain.
1237  *
1238  * @param[in] priv
1239  *   Pointer to the private device data structure.
1240  *
1241  * @return
1242  *   Zero on success, positive error code otherwise.
1243  */
1244 int
1245 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1246 {
1247         int err = 0;
1248         /* Tables are only used in DV and DR modes. */
1249 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1250         struct mlx5_dev_ctx_shared *sh = priv->sh;
1251         char s[MLX5_HLIST_NAMESIZE];
1252
1253         MLX5_ASSERT(sh);
1254         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1255         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1256                                           0, 0, flow_dv_tbl_create_cb,
1257                                           flow_dv_tbl_match_cb,
1258                                           flow_dv_tbl_remove_cb);
1259         if (!sh->flow_tbls) {
1260                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1261                 err = ENOMEM;
1262                 return err;
1263         }
1264         sh->flow_tbls->ctx = sh;
1265 #ifndef HAVE_MLX5DV_DR
1266         struct rte_flow_error error;
1267         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1268
1269         /*
1270          * In case we have not DR support, the zero tables should be created
1271          * because DV expect to see them even if they cannot be created by
1272          * RDMA-CORE.
1273          */
1274         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1275             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1276             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1277                 err = ENOMEM;
1278                 goto error;
1279         }
1280         return err;
1281 error:
1282         mlx5_free_table_hash_list(priv);
1283 #endif /* HAVE_MLX5DV_DR */
1284 #endif
1285         return err;
1286 }
1287
1288 /**
1289  * Retrieve integer value from environment variable.
1290  *
1291  * @param[in] name
1292  *   Environment variable name.
1293  *
1294  * @return
1295  *   Integer value, 0 if the variable is not set.
1296  */
1297 int
1298 mlx5_getenv_int(const char *name)
1299 {
1300         const char *val = getenv(name);
1301
1302         if (val == NULL)
1303                 return 0;
1304         return atoi(val);
1305 }
1306
1307 /**
1308  * DPDK callback to add udp tunnel port
1309  *
1310  * @param[in] dev
1311  *   A pointer to eth_dev
1312  * @param[in] udp_tunnel
1313  *   A pointer to udp tunnel
1314  *
1315  * @return
1316  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1317  */
1318 int
1319 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1320                          struct rte_eth_udp_tunnel *udp_tunnel)
1321 {
1322         MLX5_ASSERT(udp_tunnel != NULL);
1323         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1324             udp_tunnel->udp_port == 4789)
1325                 return 0;
1326         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1327             udp_tunnel->udp_port == 4790)
1328                 return 0;
1329         return -ENOTSUP;
1330 }
1331
1332 /**
1333  * Initialize process private data structure.
1334  *
1335  * @param dev
1336  *   Pointer to Ethernet device structure.
1337  *
1338  * @return
1339  *   0 on success, a negative errno value otherwise and rte_errno is set.
1340  */
1341 int
1342 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1343 {
1344         struct mlx5_priv *priv = dev->data->dev_private;
1345         struct mlx5_proc_priv *ppriv;
1346         size_t ppriv_size;
1347
1348         /*
1349          * UAR register table follows the process private structure. BlueFlame
1350          * registers for Tx queues are stored in the table.
1351          */
1352         ppriv_size =
1353                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1354         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1355                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1356         if (!ppriv) {
1357                 rte_errno = ENOMEM;
1358                 return -rte_errno;
1359         }
1360         ppriv->uar_table_sz = priv->txqs_n;
1361         dev->process_private = ppriv;
1362         return 0;
1363 }
1364
1365 /**
1366  * Un-initialize process private data structure.
1367  *
1368  * @param dev
1369  *   Pointer to Ethernet device structure.
1370  */
1371 void
1372 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1373 {
1374         if (!dev->process_private)
1375                 return;
1376         mlx5_free(dev->process_private);
1377         dev->process_private = NULL;
1378 }
1379
1380 /**
1381  * DPDK callback to close the device.
1382  *
1383  * Destroy all queues and objects, free memory.
1384  *
1385  * @param dev
1386  *   Pointer to Ethernet device structure.
1387  */
1388 int
1389 mlx5_dev_close(struct rte_eth_dev *dev)
1390 {
1391         struct mlx5_priv *priv = dev->data->dev_private;
1392         unsigned int i;
1393         int ret;
1394
1395         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1396                 /* Check if process_private released. */
1397                 if (!dev->process_private)
1398                         return 0;
1399                 mlx5_tx_uar_uninit_secondary(dev);
1400                 mlx5_proc_priv_uninit(dev);
1401                 rte_eth_dev_release_port(dev);
1402                 return 0;
1403         }
1404         if (!priv->sh)
1405                 return 0;
1406         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1407                 dev->data->port_id,
1408                 ((priv->sh->ctx != NULL) ?
1409                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1410         /*
1411          * If default mreg copy action is removed at the stop stage,
1412          * the search will return none and nothing will be done anymore.
1413          */
1414         mlx5_flow_stop_default(dev);
1415         mlx5_traffic_disable(dev);
1416         /*
1417          * If all the flows are already flushed in the device stop stage,
1418          * then this will return directly without any action.
1419          */
1420         mlx5_flow_list_flush(dev, &priv->flows, true);
1421         mlx5_action_handle_flush(dev);
1422         mlx5_flow_meter_flush(dev, NULL);
1423         /* Prevent crashes when queues are still in use. */
1424         dev->rx_pkt_burst = removed_rx_burst;
1425         dev->tx_pkt_burst = removed_tx_burst;
1426         rte_wmb();
1427         /* Disable datapath on secondary process. */
1428         mlx5_mp_os_req_stop_rxtx(dev);
1429         /* Free the eCPRI flex parser resource. */
1430         mlx5_flex_parser_ecpri_release(dev);
1431         if (priv->rxqs != NULL) {
1432                 /* XXX race condition if mlx5_rx_burst() is still running. */
1433                 rte_delay_us_sleep(1000);
1434                 for (i = 0; (i != priv->rxqs_n); ++i)
1435                         mlx5_rxq_release(dev, i);
1436                 priv->rxqs_n = 0;
1437                 priv->rxqs = NULL;
1438         }
1439         if (priv->txqs != NULL) {
1440                 /* XXX race condition if mlx5_tx_burst() is still running. */
1441                 rte_delay_us_sleep(1000);
1442                 for (i = 0; (i != priv->txqs_n); ++i)
1443                         mlx5_txq_release(dev, i);
1444                 priv->txqs_n = 0;
1445                 priv->txqs = NULL;
1446         }
1447         mlx5_proc_priv_uninit(dev);
1448         if (priv->q_counters) {
1449                 mlx5_devx_cmd_destroy(priv->q_counters);
1450                 priv->q_counters = NULL;
1451         }
1452         if (priv->drop_queue.hrxq)
1453                 mlx5_drop_action_destroy(dev);
1454         if (priv->mreg_cp_tbl)
1455                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1456         mlx5_mprq_free_mp(dev);
1457         mlx5_os_free_shared_dr(priv);
1458         if (priv->rss_conf.rss_key != NULL)
1459                 mlx5_free(priv->rss_conf.rss_key);
1460         if (priv->reta_idx != NULL)
1461                 mlx5_free(priv->reta_idx);
1462         if (priv->config.vf)
1463                 mlx5_os_mac_addr_flush(dev);
1464         if (priv->nl_socket_route >= 0)
1465                 close(priv->nl_socket_route);
1466         if (priv->nl_socket_rdma >= 0)
1467                 close(priv->nl_socket_rdma);
1468         if (priv->vmwa_context)
1469                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1470         ret = mlx5_hrxq_verify(dev);
1471         if (ret)
1472                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1473                         dev->data->port_id);
1474         ret = mlx5_ind_table_obj_verify(dev);
1475         if (ret)
1476                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1477                         dev->data->port_id);
1478         ret = mlx5_rxq_obj_verify(dev);
1479         if (ret)
1480                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1481                         dev->data->port_id);
1482         ret = mlx5_rxq_verify(dev);
1483         if (ret)
1484                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1485                         dev->data->port_id);
1486         ret = mlx5_txq_obj_verify(dev);
1487         if (ret)
1488                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1489                         dev->data->port_id);
1490         ret = mlx5_txq_verify(dev);
1491         if (ret)
1492                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1493                         dev->data->port_id);
1494         ret = mlx5_flow_verify(dev);
1495         if (ret)
1496                 DRV_LOG(WARNING, "port %u some flows still remain",
1497                         dev->data->port_id);
1498         mlx5_cache_list_destroy(&priv->hrxqs);
1499         /*
1500          * Free the shared context in last turn, because the cleanup
1501          * routines above may use some shared fields, like
1502          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1503          * ifindex if Netlink fails.
1504          */
1505         mlx5_free_shared_dev_ctx(priv->sh);
1506         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1507                 unsigned int c = 0;
1508                 uint16_t port_id;
1509
1510                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1511                         struct mlx5_priv *opriv =
1512                                 rte_eth_devices[port_id].data->dev_private;
1513
1514                         if (!opriv ||
1515                             opriv->domain_id != priv->domain_id ||
1516                             &rte_eth_devices[port_id] == dev)
1517                                 continue;
1518                         ++c;
1519                         break;
1520                 }
1521                 if (!c)
1522                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1523         }
1524         memset(priv, 0, sizeof(*priv));
1525         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1526         /*
1527          * Reset mac_addrs to NULL such that it is not freed as part of
1528          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1529          * it is freed when dev_private is freed.
1530          */
1531         dev->data->mac_addrs = NULL;
1532         return 0;
1533 }
1534
1535 const struct eth_dev_ops mlx5_dev_ops = {
1536         .dev_configure = mlx5_dev_configure,
1537         .dev_start = mlx5_dev_start,
1538         .dev_stop = mlx5_dev_stop,
1539         .dev_set_link_down = mlx5_set_link_down,
1540         .dev_set_link_up = mlx5_set_link_up,
1541         .dev_close = mlx5_dev_close,
1542         .promiscuous_enable = mlx5_promiscuous_enable,
1543         .promiscuous_disable = mlx5_promiscuous_disable,
1544         .allmulticast_enable = mlx5_allmulticast_enable,
1545         .allmulticast_disable = mlx5_allmulticast_disable,
1546         .link_update = mlx5_link_update,
1547         .stats_get = mlx5_stats_get,
1548         .stats_reset = mlx5_stats_reset,
1549         .xstats_get = mlx5_xstats_get,
1550         .xstats_reset = mlx5_xstats_reset,
1551         .xstats_get_names = mlx5_xstats_get_names,
1552         .fw_version_get = mlx5_fw_version_get,
1553         .dev_infos_get = mlx5_dev_infos_get,
1554         .representor_info_get = mlx5_representor_info_get,
1555         .read_clock = mlx5_txpp_read_clock,
1556         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1557         .vlan_filter_set = mlx5_vlan_filter_set,
1558         .rx_queue_setup = mlx5_rx_queue_setup,
1559         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1560         .tx_queue_setup = mlx5_tx_queue_setup,
1561         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1562         .rx_queue_release = mlx5_rx_queue_release,
1563         .tx_queue_release = mlx5_tx_queue_release,
1564         .rx_queue_start = mlx5_rx_queue_start,
1565         .rx_queue_stop = mlx5_rx_queue_stop,
1566         .tx_queue_start = mlx5_tx_queue_start,
1567         .tx_queue_stop = mlx5_tx_queue_stop,
1568         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1569         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1570         .mac_addr_remove = mlx5_mac_addr_remove,
1571         .mac_addr_add = mlx5_mac_addr_add,
1572         .mac_addr_set = mlx5_mac_addr_set,
1573         .set_mc_addr_list = mlx5_set_mc_addr_list,
1574         .mtu_set = mlx5_dev_set_mtu,
1575         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1576         .vlan_offload_set = mlx5_vlan_offload_set,
1577         .reta_update = mlx5_dev_rss_reta_update,
1578         .reta_query = mlx5_dev_rss_reta_query,
1579         .rss_hash_update = mlx5_rss_hash_update,
1580         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1581         .flow_ops_get = mlx5_flow_ops_get,
1582         .rxq_info_get = mlx5_rxq_info_get,
1583         .txq_info_get = mlx5_txq_info_get,
1584         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1585         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1586         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1587         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1588         .is_removed = mlx5_is_removed,
1589         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1590         .get_module_info = mlx5_get_module_info,
1591         .get_module_eeprom = mlx5_get_module_eeprom,
1592         .hairpin_cap_get = mlx5_hairpin_cap_get,
1593         .mtr_ops_get = mlx5_flow_meter_ops_get,
1594         .hairpin_bind = mlx5_hairpin_bind,
1595         .hairpin_unbind = mlx5_hairpin_unbind,
1596         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1597         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1598         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1599         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1600 };
1601
1602 /* Available operations from secondary process. */
1603 const struct eth_dev_ops mlx5_dev_sec_ops = {
1604         .stats_get = mlx5_stats_get,
1605         .stats_reset = mlx5_stats_reset,
1606         .xstats_get = mlx5_xstats_get,
1607         .xstats_reset = mlx5_xstats_reset,
1608         .xstats_get_names = mlx5_xstats_get_names,
1609         .fw_version_get = mlx5_fw_version_get,
1610         .dev_infos_get = mlx5_dev_infos_get,
1611         .read_clock = mlx5_txpp_read_clock,
1612         .rx_queue_start = mlx5_rx_queue_start,
1613         .rx_queue_stop = mlx5_rx_queue_stop,
1614         .tx_queue_start = mlx5_tx_queue_start,
1615         .tx_queue_stop = mlx5_tx_queue_stop,
1616         .rxq_info_get = mlx5_rxq_info_get,
1617         .txq_info_get = mlx5_txq_info_get,
1618         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1619         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1620         .get_module_info = mlx5_get_module_info,
1621         .get_module_eeprom = mlx5_get_module_eeprom,
1622 };
1623
1624 /* Available operations in flow isolated mode. */
1625 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1626         .dev_configure = mlx5_dev_configure,
1627         .dev_start = mlx5_dev_start,
1628         .dev_stop = mlx5_dev_stop,
1629         .dev_set_link_down = mlx5_set_link_down,
1630         .dev_set_link_up = mlx5_set_link_up,
1631         .dev_close = mlx5_dev_close,
1632         .promiscuous_enable = mlx5_promiscuous_enable,
1633         .promiscuous_disable = mlx5_promiscuous_disable,
1634         .allmulticast_enable = mlx5_allmulticast_enable,
1635         .allmulticast_disable = mlx5_allmulticast_disable,
1636         .link_update = mlx5_link_update,
1637         .stats_get = mlx5_stats_get,
1638         .stats_reset = mlx5_stats_reset,
1639         .xstats_get = mlx5_xstats_get,
1640         .xstats_reset = mlx5_xstats_reset,
1641         .xstats_get_names = mlx5_xstats_get_names,
1642         .fw_version_get = mlx5_fw_version_get,
1643         .dev_infos_get = mlx5_dev_infos_get,
1644         .read_clock = mlx5_txpp_read_clock,
1645         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1646         .vlan_filter_set = mlx5_vlan_filter_set,
1647         .rx_queue_setup = mlx5_rx_queue_setup,
1648         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1649         .tx_queue_setup = mlx5_tx_queue_setup,
1650         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1651         .rx_queue_release = mlx5_rx_queue_release,
1652         .tx_queue_release = mlx5_tx_queue_release,
1653         .rx_queue_start = mlx5_rx_queue_start,
1654         .rx_queue_stop = mlx5_rx_queue_stop,
1655         .tx_queue_start = mlx5_tx_queue_start,
1656         .tx_queue_stop = mlx5_tx_queue_stop,
1657         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1658         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1659         .mac_addr_remove = mlx5_mac_addr_remove,
1660         .mac_addr_add = mlx5_mac_addr_add,
1661         .mac_addr_set = mlx5_mac_addr_set,
1662         .set_mc_addr_list = mlx5_set_mc_addr_list,
1663         .mtu_set = mlx5_dev_set_mtu,
1664         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1665         .vlan_offload_set = mlx5_vlan_offload_set,
1666         .flow_ops_get = mlx5_flow_ops_get,
1667         .rxq_info_get = mlx5_rxq_info_get,
1668         .txq_info_get = mlx5_txq_info_get,
1669         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1670         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1671         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1672         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1673         .is_removed = mlx5_is_removed,
1674         .get_module_info = mlx5_get_module_info,
1675         .get_module_eeprom = mlx5_get_module_eeprom,
1676         .hairpin_cap_get = mlx5_hairpin_cap_get,
1677         .mtr_ops_get = mlx5_flow_meter_ops_get,
1678         .hairpin_bind = mlx5_hairpin_bind,
1679         .hairpin_unbind = mlx5_hairpin_unbind,
1680         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1681         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1682         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1683         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1684 };
1685
1686 /**
1687  * Verify and store value for device argument.
1688  *
1689  * @param[in] key
1690  *   Key argument to verify.
1691  * @param[in] val
1692  *   Value associated with key.
1693  * @param opaque
1694  *   User data.
1695  *
1696  * @return
1697  *   0 on success, a negative errno value otherwise and rte_errno is set.
1698  */
1699 static int
1700 mlx5_args_check(const char *key, const char *val, void *opaque)
1701 {
1702         struct mlx5_dev_config *config = opaque;
1703         unsigned long mod;
1704         signed long tmp;
1705
1706         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1707         if (!strcmp(MLX5_REPRESENTOR, key))
1708                 return 0;
1709         errno = 0;
1710         tmp = strtol(val, NULL, 0);
1711         if (errno) {
1712                 rte_errno = errno;
1713                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1714                 return -rte_errno;
1715         }
1716         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1717                 /* Negative values are acceptable for some keys only. */
1718                 rte_errno = EINVAL;
1719                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1720                 return -rte_errno;
1721         }
1722         mod = tmp >= 0 ? tmp : -tmp;
1723         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1724                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1725                         DRV_LOG(ERR, "invalid CQE compression "
1726                                      "format parameter");
1727                         rte_errno = EINVAL;
1728                         return -rte_errno;
1729                 }
1730                 config->cqe_comp = !!tmp;
1731                 config->cqe_comp_fmt = tmp;
1732         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1733                 config->hw_padding = !!tmp;
1734         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1735                 config->mprq.enabled = !!tmp;
1736         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1737                 config->mprq.stride_num_n = tmp;
1738         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1739                 config->mprq.stride_size_n = tmp;
1740         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1741                 config->mprq.max_memcpy_len = tmp;
1742         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1743                 config->mprq.min_rxqs_num = tmp;
1744         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1745                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1746                                  " converted to txq_inline_max", key);
1747                 config->txq_inline_max = tmp;
1748         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1749                 config->txq_inline_max = tmp;
1750         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1751                 config->txq_inline_min = tmp;
1752         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1753                 config->txq_inline_mpw = tmp;
1754         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1755                 config->txqs_inline = tmp;
1756         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1757                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1758         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1759                 config->mps = !!tmp;
1760         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1761                 if (tmp != MLX5_TXDB_CACHED &&
1762                     tmp != MLX5_TXDB_NCACHED &&
1763                     tmp != MLX5_TXDB_HEURISTIC) {
1764                         DRV_LOG(ERR, "invalid Tx doorbell "
1765                                      "mapping parameter");
1766                         rte_errno = EINVAL;
1767                         return -rte_errno;
1768                 }
1769                 config->dbnc = tmp;
1770         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1771                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1772         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1773                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1774                                  " converted to txq_inline_mpw", key);
1775                 config->txq_inline_mpw = tmp;
1776         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1777                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1778         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1779                 if (!mod) {
1780                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1781                         rte_errno = EINVAL;
1782                         return -rte_errno;
1783                 }
1784                 config->tx_pp = tmp;
1785         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1786                 config->tx_skew = tmp;
1787         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1788                 config->rx_vec_en = !!tmp;
1789         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1790                 config->l3_vxlan_en = !!tmp;
1791         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1792                 config->vf_nl_en = !!tmp;
1793         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1794                 config->dv_esw_en = !!tmp;
1795         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1796                 config->dv_flow_en = !!tmp;
1797         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1798                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1799                     tmp != MLX5_XMETA_MODE_META16 &&
1800                     tmp != MLX5_XMETA_MODE_META32 &&
1801                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1802                         DRV_LOG(ERR, "invalid extensive "
1803                                      "metadata parameter");
1804                         rte_errno = EINVAL;
1805                         return -rte_errno;
1806                 }
1807                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1808                         config->dv_xmeta_en = tmp;
1809                 else
1810                         config->dv_miss_info = 1;
1811         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1812                 config->lacp_by_user = !!tmp;
1813         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1814                 config->mr_ext_memseg_en = !!tmp;
1815         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1816                 config->max_dump_files_num = tmp;
1817         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1818                 config->lro.timeout = tmp;
1819         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1820                 DRV_LOG(DEBUG, "class argument is %s.", val);
1821         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1822                 config->log_hp_size = tmp;
1823         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1824                 if (tmp != MLX5_RCM_NONE &&
1825                     tmp != MLX5_RCM_LIGHT &&
1826                     tmp != MLX5_RCM_AGGR) {
1827                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1828                         rte_errno = EINVAL;
1829                         return -rte_errno;
1830                 }
1831                 config->reclaim_mode = tmp;
1832         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1833                 config->sys_mem_en = !!tmp;
1834         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1835                 config->decap_en = !!tmp;
1836         } else {
1837                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1838                 rte_errno = EINVAL;
1839                 return -rte_errno;
1840         }
1841         return 0;
1842 }
1843
1844 /**
1845  * Parse device parameters.
1846  *
1847  * @param config
1848  *   Pointer to device configuration structure.
1849  * @param devargs
1850  *   Device arguments structure.
1851  *
1852  * @return
1853  *   0 on success, a negative errno value otherwise and rte_errno is set.
1854  */
1855 int
1856 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1857 {
1858         const char **params = (const char *[]){
1859                 MLX5_RXQ_CQE_COMP_EN,
1860                 MLX5_RXQ_PKT_PAD_EN,
1861                 MLX5_RX_MPRQ_EN,
1862                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1863                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1864                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1865                 MLX5_RXQS_MIN_MPRQ,
1866                 MLX5_TXQ_INLINE,
1867                 MLX5_TXQ_INLINE_MIN,
1868                 MLX5_TXQ_INLINE_MAX,
1869                 MLX5_TXQ_INLINE_MPW,
1870                 MLX5_TXQS_MIN_INLINE,
1871                 MLX5_TXQS_MAX_VEC,
1872                 MLX5_TXQ_MPW_EN,
1873                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1874                 MLX5_TXQ_MAX_INLINE_LEN,
1875                 MLX5_TX_DB_NC,
1876                 MLX5_TX_PP,
1877                 MLX5_TX_SKEW,
1878                 MLX5_TX_VEC_EN,
1879                 MLX5_RX_VEC_EN,
1880                 MLX5_L3_VXLAN_EN,
1881                 MLX5_VF_NL_EN,
1882                 MLX5_DV_ESW_EN,
1883                 MLX5_DV_FLOW_EN,
1884                 MLX5_DV_XMETA_EN,
1885                 MLX5_LACP_BY_USER,
1886                 MLX5_MR_EXT_MEMSEG_EN,
1887                 MLX5_REPRESENTOR,
1888                 MLX5_MAX_DUMP_FILES_NUM,
1889                 MLX5_LRO_TIMEOUT_USEC,
1890                 MLX5_CLASS_ARG_NAME,
1891                 MLX5_HP_BUF_SIZE,
1892                 MLX5_RECLAIM_MEM,
1893                 MLX5_SYS_MEM_EN,
1894                 MLX5_DECAP_EN,
1895                 NULL,
1896         };
1897         struct rte_kvargs *kvlist;
1898         int ret = 0;
1899         int i;
1900
1901         if (devargs == NULL)
1902                 return 0;
1903         /* Following UGLY cast is done to pass checkpatch. */
1904         kvlist = rte_kvargs_parse(devargs->args, params);
1905         if (kvlist == NULL) {
1906                 rte_errno = EINVAL;
1907                 return -rte_errno;
1908         }
1909         /* Process parameters. */
1910         for (i = 0; (params[i] != NULL); ++i) {
1911                 if (rte_kvargs_count(kvlist, params[i])) {
1912                         ret = rte_kvargs_process(kvlist, params[i],
1913                                                  mlx5_args_check, config);
1914                         if (ret) {
1915                                 rte_errno = EINVAL;
1916                                 rte_kvargs_free(kvlist);
1917                                 return -rte_errno;
1918                         }
1919                 }
1920         }
1921         rte_kvargs_free(kvlist);
1922         return 0;
1923 }
1924
1925 /**
1926  * Configures the minimal amount of data to inline into WQE
1927  * while sending packets.
1928  *
1929  * - the txq_inline_min has the maximal priority, if this
1930  *   key is specified in devargs
1931  * - if DevX is enabled the inline mode is queried from the
1932  *   device (HCA attributes and NIC vport context if needed).
1933  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1934  *   and none (0 bytes) for other NICs
1935  *
1936  * @param spawn
1937  *   Verbs device parameters (name, port, switch_info) to spawn.
1938  * @param config
1939  *   Device configuration parameters.
1940  */
1941 void
1942 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1943                     struct mlx5_dev_config *config)
1944 {
1945         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1946                 /* Application defines size of inlined data explicitly. */
1947                 switch (spawn->pci_dev->id.device_id) {
1948                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1949                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1950                         if (config->txq_inline_min <
1951                                        (int)MLX5_INLINE_HSIZE_L2) {
1952                                 DRV_LOG(DEBUG,
1953                                         "txq_inline_mix aligned to minimal"
1954                                         " ConnectX-4 required value %d",
1955                                         (int)MLX5_INLINE_HSIZE_L2);
1956                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1957                         }
1958                         break;
1959                 }
1960                 goto exit;
1961         }
1962         if (config->hca_attr.eth_net_offloads) {
1963                 /* We have DevX enabled, inline mode queried successfully. */
1964                 switch (config->hca_attr.wqe_inline_mode) {
1965                 case MLX5_CAP_INLINE_MODE_L2:
1966                         /* outer L2 header must be inlined. */
1967                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1968                         goto exit;
1969                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1970                         /* No inline data are required by NIC. */
1971                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1972                         config->hw_vlan_insert =
1973                                 config->hca_attr.wqe_vlan_insert;
1974                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1975                         goto exit;
1976                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1977                         /* inline mode is defined by NIC vport context. */
1978                         if (!config->hca_attr.eth_virt)
1979                                 break;
1980                         switch (config->hca_attr.vport_inline_mode) {
1981                         case MLX5_INLINE_MODE_NONE:
1982                                 config->txq_inline_min =
1983                                         MLX5_INLINE_HSIZE_NONE;
1984                                 goto exit;
1985                         case MLX5_INLINE_MODE_L2:
1986                                 config->txq_inline_min =
1987                                         MLX5_INLINE_HSIZE_L2;
1988                                 goto exit;
1989                         case MLX5_INLINE_MODE_IP:
1990                                 config->txq_inline_min =
1991                                         MLX5_INLINE_HSIZE_L3;
1992                                 goto exit;
1993                         case MLX5_INLINE_MODE_TCP_UDP:
1994                                 config->txq_inline_min =
1995                                         MLX5_INLINE_HSIZE_L4;
1996                                 goto exit;
1997                         case MLX5_INLINE_MODE_INNER_L2:
1998                                 config->txq_inline_min =
1999                                         MLX5_INLINE_HSIZE_INNER_L2;
2000                                 goto exit;
2001                         case MLX5_INLINE_MODE_INNER_IP:
2002                                 config->txq_inline_min =
2003                                         MLX5_INLINE_HSIZE_INNER_L3;
2004                                 goto exit;
2005                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2006                                 config->txq_inline_min =
2007                                         MLX5_INLINE_HSIZE_INNER_L4;
2008                                 goto exit;
2009                         }
2010                 }
2011         }
2012         /*
2013          * We get here if we are unable to deduce
2014          * inline data size with DevX. Try PCI ID
2015          * to determine old NICs.
2016          */
2017         switch (spawn->pci_dev->id.device_id) {
2018         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2019         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2020         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2021         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2022                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2023                 config->hw_vlan_insert = 0;
2024                 break;
2025         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2026         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2027         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2028         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2029                 /*
2030                  * These NICs support VLAN insertion from WQE and
2031                  * report the wqe_vlan_insert flag. But there is the bug
2032                  * and PFC control may be broken, so disable feature.
2033                  */
2034                 config->hw_vlan_insert = 0;
2035                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2036                 break;
2037         default:
2038                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2039                 break;
2040         }
2041 exit:
2042         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2043 }
2044
2045 /**
2046  * Configures the metadata mask fields in the shared context.
2047  *
2048  * @param [in] dev
2049  *   Pointer to Ethernet device.
2050  */
2051 void
2052 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2053 {
2054         struct mlx5_priv *priv = dev->data->dev_private;
2055         struct mlx5_dev_ctx_shared *sh = priv->sh;
2056         uint32_t meta, mark, reg_c0;
2057
2058         reg_c0 = ~priv->vport_meta_mask;
2059         switch (priv->config.dv_xmeta_en) {
2060         case MLX5_XMETA_MODE_LEGACY:
2061                 meta = UINT32_MAX;
2062                 mark = MLX5_FLOW_MARK_MASK;
2063                 break;
2064         case MLX5_XMETA_MODE_META16:
2065                 meta = reg_c0 >> rte_bsf32(reg_c0);
2066                 mark = MLX5_FLOW_MARK_MASK;
2067                 break;
2068         case MLX5_XMETA_MODE_META32:
2069                 meta = UINT32_MAX;
2070                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2071                 break;
2072         default:
2073                 meta = 0;
2074                 mark = 0;
2075                 MLX5_ASSERT(false);
2076                 break;
2077         }
2078         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2079                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2080                                  sh->dv_mark_mask, mark);
2081         else
2082                 sh->dv_mark_mask = mark;
2083         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2084                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2085                                  sh->dv_meta_mask, meta);
2086         else
2087                 sh->dv_meta_mask = meta;
2088         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2089                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2090                                  sh->dv_meta_mask, reg_c0);
2091         else
2092                 sh->dv_regc0_mask = reg_c0;
2093         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2094         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2095         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2096         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2097 }
2098
2099 int
2100 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2101 {
2102         static const char *const dynf_names[] = {
2103                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2104                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2105                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2106         };
2107         unsigned int i;
2108
2109         if (n < RTE_DIM(dynf_names))
2110                 return -ENOMEM;
2111         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2112                 if (names[i] == NULL)
2113                         return -EINVAL;
2114                 strcpy(names[i], dynf_names[i]);
2115         }
2116         return RTE_DIM(dynf_names);
2117 }
2118
2119 /**
2120  * Comparison callback to sort device data.
2121  *
2122  * This is meant to be used with qsort().
2123  *
2124  * @param a[in]
2125  *   Pointer to pointer to first data object.
2126  * @param b[in]
2127  *   Pointer to pointer to second data object.
2128  *
2129  * @return
2130  *   0 if both objects are equal, less than 0 if the first argument is less
2131  *   than the second, greater than 0 otherwise.
2132  */
2133 int
2134 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2135                               struct mlx5_dev_config *config)
2136 {
2137         struct mlx5_dev_ctx_shared *sh = priv->sh;
2138         struct mlx5_dev_config *sh_conf = NULL;
2139         uint16_t port_id;
2140
2141         MLX5_ASSERT(sh);
2142         /* Nothing to compare for the single/first device. */
2143         if (sh->refcnt == 1)
2144                 return 0;
2145         /* Find the device with shared context. */
2146         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2147                 struct mlx5_priv *opriv =
2148                         rte_eth_devices[port_id].data->dev_private;
2149
2150                 if (opriv && opriv != priv && opriv->sh == sh) {
2151                         sh_conf = &opriv->config;
2152                         break;
2153                 }
2154         }
2155         if (!sh_conf)
2156                 return 0;
2157         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2158                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2159                              " for shared %s context", sh->ibdev_name);
2160                 rte_errno = EINVAL;
2161                 return rte_errno;
2162         }
2163         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2164                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2165                              " for shared %s context", sh->ibdev_name);
2166                 rte_errno = EINVAL;
2167                 return rte_errno;
2168         }
2169         return 0;
2170 }
2171
2172 /**
2173  * Look for the ethernet device belonging to mlx5 driver.
2174  *
2175  * @param[in] port_id
2176  *   port_id to start looking for device.
2177  * @param[in] pci_dev
2178  *   Pointer to the hint PCI device. When device is being probed
2179  *   the its siblings (master and preceding representors might
2180  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2181  *   is not completed yet, for this case match on hint PCI
2182  *   device may be used to detect sibling device.
2183  *
2184  * @return
2185  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2186  */
2187 uint16_t
2188 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2189 {
2190         while (port_id < RTE_MAX_ETHPORTS) {
2191                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2192
2193                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2194                     dev->device &&
2195                     (dev->device == &pci_dev->device ||
2196                      (dev->device->driver &&
2197                      dev->device->driver->name &&
2198                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2199                         break;
2200                 port_id++;
2201         }
2202         if (port_id >= RTE_MAX_ETHPORTS)
2203                 return RTE_MAX_ETHPORTS;
2204         return port_id;
2205 }
2206
2207 /**
2208  * DPDK callback to remove a PCI device.
2209  *
2210  * This function removes all Ethernet devices belong to a given PCI device.
2211  *
2212  * @param[in] pci_dev
2213  *   Pointer to the PCI device.
2214  *
2215  * @return
2216  *   0 on success, the function cannot fail.
2217  */
2218 static int
2219 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2220 {
2221         uint16_t port_id;
2222         int ret = 0;
2223
2224         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2225                 /*
2226                  * mlx5_dev_close() is not registered to secondary process,
2227                  * call the close function explicitly for secondary process.
2228                  */
2229                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2230                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2231                 else
2232                         ret |= rte_eth_dev_close(port_id);
2233         }
2234         return ret == 0 ? 0 : -EIO;
2235 }
2236
2237 static const struct rte_pci_id mlx5_pci_id_map[] = {
2238         {
2239                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2240                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2241         },
2242         {
2243                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2244                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2245         },
2246         {
2247                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2248                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2249         },
2250         {
2251                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2252                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2253         },
2254         {
2255                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2256                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2257         },
2258         {
2259                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2260                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2261         },
2262         {
2263                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2264                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2265         },
2266         {
2267                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2268                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2269         },
2270         {
2271                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2272                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2273         },
2274         {
2275                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2276                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2277         },
2278         {
2279                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2280                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2281         },
2282         {
2283                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2284                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2285         },
2286         {
2287                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2288                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2289         },
2290         {
2291                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2292                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2293         },
2294         {
2295                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2296                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2297         },
2298         {
2299                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2300                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2301         },
2302         {
2303                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2304                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2305         },
2306         {
2307                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2308                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2309         },
2310         {
2311                 .vendor_id = 0
2312         }
2313 };
2314
2315 static struct mlx5_pci_driver mlx5_driver = {
2316         .driver_class = MLX5_CLASS_NET,
2317         .pci_driver = {
2318                 .driver = {
2319                         .name = MLX5_PCI_DRIVER_NAME,
2320                 },
2321                 .id_table = mlx5_pci_id_map,
2322                 .probe = mlx5_os_pci_probe,
2323                 .remove = mlx5_pci_remove,
2324                 .dma_map = mlx5_dma_map,
2325                 .dma_unmap = mlx5_dma_unmap,
2326                 .drv_flags = PCI_DRV_FLAGS,
2327         },
2328 };
2329
2330 /* Initialize driver log type. */
2331 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2332
2333 /**
2334  * Driver initialization routine.
2335  */
2336 RTE_INIT(rte_mlx5_pmd_init)
2337 {
2338         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2339         mlx5_common_init();
2340         /* Build the static tables for Verbs conversion. */
2341         mlx5_set_ptype_table();
2342         mlx5_set_cksum_table();
2343         mlx5_set_swp_types_table();
2344         if (mlx5_glue)
2345                 mlx5_pci_driver_register(&mlx5_driver);
2346 }
2347
2348 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2349 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2350 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");