drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_mr.h"
  40 #include "mlx5_flow.h"
  41 #include "rte_pmd_mlx5.h"
  42
  43 /* Device parameter to enable RX completion queue compression. */
  44 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  45
  46 /* Device parameter to enable RX completion entry padding to 128B. */
  47 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 187
 188 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 189 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 190         [MLX5_IPOOL_DECAP_ENCAP] = {
 191                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 192                 .trunk_size = 64,
 193                 .grow_trunk = 3,
 194                 .grow_shift = 2,
 195                 .need_lock = 1,
 196                 .release_mem_en = 1,
 197                 .malloc = mlx5_malloc,
 198                 .free = mlx5_free,
 199                 .type = "mlx5_encap_decap_ipool",
 200         },
 201         [MLX5_IPOOL_PUSH_VLAN] = {
 202                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 203                 .trunk_size = 64,
 204                 .grow_trunk = 3,
 205                 .grow_shift = 2,
 206                 .need_lock = 1,
 207                 .release_mem_en = 1,
 208                 .malloc = mlx5_malloc,
 209                 .free = mlx5_free,
 210                 .type = "mlx5_push_vlan_ipool",
 211         },
 212         [MLX5_IPOOL_TAG] = {
 213                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 214                 .trunk_size = 64,
 215                 .grow_trunk = 3,
 216                 .grow_shift = 2,
 217                 .need_lock = 1,
 218                 .release_mem_en = 1,
 219                 .malloc = mlx5_malloc,
 220                 .free = mlx5_free,
 221                 .type = "mlx5_tag_ipool",
 222         },
 223         [MLX5_IPOOL_PORT_ID] = {
 224                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 225                 .trunk_size = 64,
 226                 .grow_trunk = 3,
 227                 .grow_shift = 2,
 228                 .need_lock = 1,
 229                 .release_mem_en = 1,
 230                 .malloc = mlx5_malloc,
 231                 .free = mlx5_free,
 232                 .type = "mlx5_port_id_ipool",
 233         },
 234         [MLX5_IPOOL_JUMP] = {
 235                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 236                 .trunk_size = 64,
 237                 .grow_trunk = 3,
 238                 .grow_shift = 2,
 239                 .need_lock = 1,
 240                 .release_mem_en = 1,
 241                 .malloc = mlx5_malloc,
 242                 .free = mlx5_free,
 243                 .type = "mlx5_jump_ipool",
 244         },
 245         [MLX5_IPOOL_SAMPLE] = {
 246                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 247                 .trunk_size = 64,
 248                 .grow_trunk = 3,
 249                 .grow_shift = 2,
 250                 .need_lock = 1,
 251                 .release_mem_en = 1,
 252                 .malloc = mlx5_malloc,
 253                 .free = mlx5_free,
 254                 .type = "mlx5_sample_ipool",
 255         },
 256         [MLX5_IPOOL_DEST_ARRAY] = {
 257                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 1,
 262                 .release_mem_en = 1,
 263                 .malloc = mlx5_malloc,
 264                 .free = mlx5_free,
 265                 .type = "mlx5_dest_array_ipool",
 266         },
 267         [MLX5_IPOOL_TUNNEL_ID] = {
 268                 .size = sizeof(struct mlx5_flow_tunnel),
 269                 .trunk_size = MLX5_MAX_TUNNELS,
 270                 .need_lock = 1,
 271                 .release_mem_en = 1,
 272                 .type = "mlx5_tunnel_offload",
 273         },
 274         [MLX5_IPOOL_TNL_TBL_ID] = {
 275                 .size = 0,
 276                 .need_lock = 1,
 277                 .type = "mlx5_flow_tnl_tbl_ipool",
 278         },
 279 #endif
 280         [MLX5_IPOOL_MTR] = {
 281                 .size = sizeof(struct mlx5_flow_meter),
 282                 .trunk_size = 64,
 283                 .grow_trunk = 3,
 284                 .grow_shift = 2,
 285                 .need_lock = 1,
 286                 .release_mem_en = 1,
 287                 .malloc = mlx5_malloc,
 288                 .free = mlx5_free,
 289                 .type = "mlx5_meter_ipool",
 290         },
 291         [MLX5_IPOOL_MCP] = {
 292                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 293                 .trunk_size = 64,
 294                 .grow_trunk = 3,
 295                 .grow_shift = 2,
 296                 .need_lock = 1,
 297                 .release_mem_en = 1,
 298                 .malloc = mlx5_malloc,
 299                 .free = mlx5_free,
 300                 .type = "mlx5_mcp_ipool",
 301         },
 302         [MLX5_IPOOL_HRXQ] = {
 303                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 304                 .trunk_size = 64,
 305                 .grow_trunk = 3,
 306                 .grow_shift = 2,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = mlx5_malloc,
 310                 .free = mlx5_free,
 311                 .type = "mlx5_hrxq_ipool",
 312         },
 313         [MLX5_IPOOL_MLX5_FLOW] = {
 314                 /*
 315                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 316                  * It set in run time according to PCI function configuration.
 317                  */
 318                 .size = 0,
 319                 .trunk_size = 64,
 320                 .grow_trunk = 3,
 321                 .grow_shift = 2,
 322                 .need_lock = 1,
 323                 .release_mem_en = 1,
 324                 .malloc = mlx5_malloc,
 325                 .free = mlx5_free,
 326                 .type = "mlx5_flow_handle_ipool",
 327         },
 328         [MLX5_IPOOL_RTE_FLOW] = {
 329                 .size = sizeof(struct rte_flow),
 330                 .trunk_size = 4096,
 331                 .need_lock = 1,
 332                 .release_mem_en = 1,
 333                 .malloc = mlx5_malloc,
 334                 .free = mlx5_free,
 335                 .type = "rte_flow_ipool",
 336         },
 337         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 338                 .size = 0,
 339                 .need_lock = 1,
 340                 .type = "mlx5_flow_rss_id_ipool",
 341         },
 342         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 343                 .size = sizeof(struct mlx5_shared_action_rss),
 344                 .trunk_size = 64,
 345                 .grow_trunk = 3,
 346                 .grow_shift = 2,
 347                 .need_lock = 1,
 348                 .release_mem_en = 1,
 349                 .malloc = mlx5_malloc,
 350                 .free = mlx5_free,
 351                 .type = "mlx5_shared_action_rss",
 352         },
 353 };
 354
 355
 356 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 357 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 358
 359 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 360
 361 /**
 362  * Initialize the ASO aging management structure.
 363  *
 364  * @param[in] sh
 365  *   Pointer to mlx5_dev_ctx_shared object to free
 366  *
 367  * @return
 368  *   0 on success, a negative errno value otherwise and rte_errno is set.
 369  */
 370 int
 371 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 372 {
 373         int err;
 374
 375         if (sh->aso_age_mng)
 376                 return 0;
 377         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 378                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 379         if (!sh->aso_age_mng) {
 380                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 381                 rte_errno = ENOMEM;
 382                 return -ENOMEM;
 383         }
 384         err = mlx5_aso_queue_init(sh);
 385         if (err) {
 386                 mlx5_free(sh->aso_age_mng);
 387                 return -1;
 388         }
 389         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 390         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 391         LIST_INIT(&sh->aso_age_mng->free);
 392         return 0;
 393 }
 394
 395 /**
 396  * Close and release all the resources of the ASO aging management structure.
 397  *
 398  * @param[in] sh
 399  *   Pointer to mlx5_dev_ctx_shared object to free.
 400  */
 401 static void
 402 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 403 {
 404         int i, j;
 405
 406         mlx5_aso_queue_stop(sh);
 407         mlx5_aso_queue_uninit(sh);
 408         if (sh->aso_age_mng->pools) {
 409                 struct mlx5_aso_age_pool *pool;
 410
 411                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 412                         pool = sh->aso_age_mng->pools[i];
 413                         claim_zero(mlx5_devx_cmd_destroy
 414                                                 (pool->flow_hit_aso_obj));
 415                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 416                                 if (pool->actions[j].dr_action)
 417                                         claim_zero
 418                                                 (mlx5_glue->destroy_flow_action
 419                                                   (pool->actions[j].dr_action));
 420                         mlx5_free(pool);
 421                 }
 422                 mlx5_free(sh->aso_age_mng->pools);
 423         }
 424         mlx5_free(sh->aso_age_mng);
 425 }
 426
 427 /**
 428  * Initialize the shared aging list information per port.
 429  *
 430  * @param[in] sh
 431  *   Pointer to mlx5_dev_ctx_shared object.
 432  */
 433 static void
 434 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 435 {
 436         uint32_t i;
 437         struct mlx5_age_info *age_info;
 438
 439         for (i = 0; i < sh->max_port; i++) {
 440                 age_info = &sh->port[i].age_info;
 441                 age_info->flags = 0;
 442                 TAILQ_INIT(&age_info->aged_counters);
 443                 LIST_INIT(&age_info->aged_aso);
 444                 rte_spinlock_init(&age_info->aged_sl);
 445                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 446         }
 447 }
 448
 449 /**
 450  * Initialize the counters management structure.
 451  *
 452  * @param[in] sh
 453  *   Pointer to mlx5_dev_ctx_shared object to free
 454  */
 455 static void
 456 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 457 {
 458         int i;
 459
 460         memset(&sh->cmng, 0, sizeof(sh->cmng));
 461         TAILQ_INIT(&sh->cmng.flow_counters);
 462         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 463         sh->cmng.max_id = -1;
 464         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 465         rte_spinlock_init(&sh->cmng.pool_update_sl);
 466         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 467                 TAILQ_INIT(&sh->cmng.counters[i]);
 468                 rte_spinlock_init(&sh->cmng.csl[i]);
 469         }
 470 }
 471
 472 /**
 473  * Destroy all the resources allocated for a counter memory management.
 474  *
 475  * @param[in] mng
 476  *   Pointer to the memory management structure.
 477  */
 478 static void
 479 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 480 {
 481         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 482
 483         LIST_REMOVE(mng, next);
 484         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 485         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 486         mlx5_free(mem);
 487 }
 488
 489 /**
 490  * Close and release all the resources of the counters management.
 491  *
 492  * @param[in] sh
 493  *   Pointer to mlx5_dev_ctx_shared object to free.
 494  */
 495 static void
 496 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 497 {
 498         struct mlx5_counter_stats_mem_mng *mng;
 499         int i, j;
 500         int retries = 1024;
 501
 502         rte_errno = 0;
 503         while (--retries) {
 504                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 505                 if (rte_errno != EINPROGRESS)
 506                         break;
 507                 rte_pause();
 508         }
 509
 510         if (sh->cmng.pools) {
 511                 struct mlx5_flow_counter_pool *pool;
 512                 uint16_t n_valid = sh->cmng.n_valid;
 513                 bool fallback = sh->cmng.counter_fallback;
 514
 515                 for (i = 0; i < n_valid; ++i) {
 516                         pool = sh->cmng.pools[i];
 517                         if (!fallback && pool->min_dcs)
 518                                 claim_zero(mlx5_devx_cmd_destroy
 519                                                                (pool->min_dcs));
 520                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 521                                 struct mlx5_flow_counter *cnt =
 522                                                 MLX5_POOL_GET_CNT(pool, j);
 523
 524                                 if (cnt->action)
 525                                         claim_zero
 526                                          (mlx5_glue->destroy_flow_action
 527                                           (cnt->action));
 528                                 if (fallback && MLX5_POOL_GET_CNT
 529                                     (pool, j)->dcs_when_free)
 530                                         claim_zero(mlx5_devx_cmd_destroy
 531                                                    (cnt->dcs_when_free));
 532                         }
 533                         mlx5_free(pool);
 534                 }
 535                 mlx5_free(sh->cmng.pools);
 536         }
 537         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 538         while (mng) {
 539                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 540                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 541         }
 542         memset(&sh->cmng, 0, sizeof(sh->cmng));
 543 }
 544
 545 /* Send FLOW_AGED event if needed. */
 546 void
 547 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 548 {
 549         struct mlx5_age_info *age_info;
 550         uint32_t i;
 551
 552         for (i = 0; i < sh->max_port; i++) {
 553                 age_info = &sh->port[i].age_info;
 554                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 555                         continue;
 556                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 557                         rte_eth_dev_callback_process
 558                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 559                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 560                 age_info->flags = 0;
 561         }
 562 }
 563
 564 /**
 565  * Initialize the flow resources' indexed mempool.
 566  *
 567  * @param[in] sh
 568  *   Pointer to mlx5_dev_ctx_shared object.
 569  * @param[in] sh
 570  *   Pointer to user dev config.
 571  */
 572 static void
 573 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 574                        const struct mlx5_dev_config *config)
 575 {
 576         uint8_t i;
 577         struct mlx5_indexed_pool_config cfg;
 578
 579         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 580                 cfg = mlx5_ipool_cfg[i];
 581                 switch (i) {
 582                 default:
 583                         break;
 584                 /*
 585                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 586                  * according to PCI function flow configuration.
 587                  */
 588                 case MLX5_IPOOL_MLX5_FLOW:
 589                         cfg.size = config->dv_flow_en ?
 590                                 sizeof(struct mlx5_flow_handle) :
 591                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 592                         break;
 593                 }
 594                 if (config->reclaim_mode)
 595                         cfg.release_mem_en = 1;
 596                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 597         }
 598 }
 599
 600 /**
 601  * Release the flow resources' indexed mempool.
 602  *
 603  * @param[in] sh
 604  *   Pointer to mlx5_dev_ctx_shared object.
 605  */
 606 static void
 607 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 608 {
 609         uint8_t i;
 610
 611         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 612                 mlx5_ipool_destroy(sh->ipool[i]);
 613 }
 614
 615 /*
 616  * Check if dynamic flex parser for eCPRI already exists.
 617  *
 618  * @param dev
 619  *   Pointer to Ethernet device structure.
 620  *
 621  * @return
 622  *   true on exists, false on not.
 623  */
 624 bool
 625 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 626 {
 627         struct mlx5_priv *priv = dev->data->dev_private;
 628         struct mlx5_flex_parser_profiles *prf =
 629                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 630
 631         return !!prf->obj;
 632 }
 633
 634 /*
 635  * Allocation of a flex parser for eCPRI. Once created, this parser related
 636  * resources will be held until the device is closed.
 637  *
 638  * @param dev
 639  *   Pointer to Ethernet device structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 int
 645 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 646 {
 647         struct mlx5_priv *priv = dev->data->dev_private;
 648         struct mlx5_flex_parser_profiles *prf =
 649                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 650         struct mlx5_devx_graph_node_attr node = {
 651                 .modify_field_select = 0,
 652         };
 653         uint32_t ids[8];
 654         int ret;
 655
 656         if (!priv->config.hca_attr.parse_graph_flex_node) {
 657                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 658                         "for device %s.", priv->dev_data->name);
 659                 return -ENOTSUP;
 660         }
 661         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 662         /* 8 bytes now: 4B common header + 4B message body header. */
 663         node.header_length_base_value = 0x8;
 664         /* After MAC layer: Ether / VLAN. */
 665         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 666         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 667         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 668         /* Sample #0: type in common header. */
 669         node.sample[0].flow_match_sample_en = 1;
 670         /* Fixed offset. */
 671         node.sample[0].flow_match_sample_offset_mode = 0x0;
 672         /* Only the 2nd byte will be used. */
 673         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 674         /* Sample #1: message payload. */
 675         node.sample[1].flow_match_sample_en = 1;
 676         /* Fixed offset. */
 677         node.sample[1].flow_match_sample_offset_mode = 0x0;
 678         /*
 679          * Only the first two bytes will be used right now, and its offset will
 680          * start after the common header that with the length of a DW(u32).
 681          */
 682         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 683         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 684         if (!prf->obj) {
 685                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 686                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 687         }
 688         prf->num = 2;
 689         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 690         if (ret) {
 691                 DRV_LOG(ERR, "Failed to query sample IDs.");
 692                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 693         }
 694         prf->offset[0] = 0x0;
 695         prf->offset[1] = sizeof(uint32_t);
 696         prf->ids[0] = ids[0];
 697         prf->ids[1] = ids[1];
 698         return 0;
 699 }
 700
 701 /*
 702  * Destroy the flex parser node, including the parser itself, input / output
 703  * arcs and DW samples. Resources could be reused then.
 704  *
 705  * @param dev
 706  *   Pointer to Ethernet device structure.
 707  */
 708 static void
 709 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 710 {
 711         struct mlx5_priv *priv = dev->data->dev_private;
 712         struct mlx5_flex_parser_profiles *prf =
 713                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 714
 715         if (prf->obj)
 716                 mlx5_devx_cmd_destroy(prf->obj);
 717         prf->obj = NULL;
 718 }
 719
 720 /*
 721  * Allocate Rx and Tx UARs in robust fashion.
 722  * This routine handles the following UAR allocation issues:
 723  *
 724  *  - tries to allocate the UAR with the most appropriate memory
 725  *    mapping type from the ones supported by the host
 726  *
 727  *  - tries to allocate the UAR with non-NULL base address
 728  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 729  *    UAR base address if UAR was not the first object in the UAR page.
 730  *    It caused the PMD failure and we should try to get another UAR
 731  *    till we get the first one with non-NULL base address returned.
 732  */
 733 static int
 734 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 735                      const struct mlx5_dev_config *config)
 736 {
 737         uint32_t uar_mapping, retry;
 738         int err = 0;
 739         void *base_addr;
 740
 741         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 742 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 743                 /* Control the mapping type according to the settings. */
 744                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 745                               MLX5DV_UAR_ALLOC_TYPE_NC :
 746                               MLX5DV_UAR_ALLOC_TYPE_BF;
 747 #else
 748                 RTE_SET_USED(config);
 749                 /*
 750                  * It seems we have no way to control the memory mapping type
 751                  * for the UAR, the default "Write-Combining" type is supposed.
 752                  * The UAR initialization on queue creation queries the
 753                  * actual mapping type done by Verbs/kernel and setups the
 754                  * PMD datapath accordingly.
 755                  */
 756                 uar_mapping = 0;
 757 #endif
 758                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 759 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 760                 if (!sh->tx_uar &&
 761                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 762                         if (config->dbnc == MLX5_TXDB_CACHED ||
 763                             config->dbnc == MLX5_TXDB_HEURISTIC)
 764                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 765                                                  "is not supported by DevX");
 766                         /*
 767                          * In some environments like virtual machine
 768                          * the Write Combining mapped might be not supported
 769                          * and UAR allocation fails. We try "Non-Cached"
 770                          * mapping for the case. The tx_burst routines take
 771                          * the UAR mapping type into account on UAR setup
 772                          * on queue creation.
 773                          */
 774                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
 775                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 776                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 777                                                         (sh->ctx, uar_mapping);
 778                 } else if (!sh->tx_uar &&
 779                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 780                         if (config->dbnc == MLX5_TXDB_NCACHED)
 781                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 782                                                  "is not supported by DevX");
 783                         /*
 784                          * If Verbs/kernel does not support "Non-Cached"
 785                          * try the "Write-Combining".
 786                          */
 787                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
 788                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 789                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 790                                                         (sh->ctx, uar_mapping);
 791                 }
 792 #endif
 793                 if (!sh->tx_uar) {
 794                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 795                         err = ENOMEM;
 796                         goto exit;
 797                 }
 798                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 799                 if (base_addr)
 800                         break;
 801                 /*
 802                  * The UARs are allocated by rdma_core within the
 803                  * IB device context, on context closure all UARs
 804                  * will be freed, should be no memory/object leakage.
 805                  */
 806                 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
 807                 sh->tx_uar = NULL;
 808         }
 809         /* Check whether we finally succeeded with valid UAR allocation. */
 810         if (!sh->tx_uar) {
 811                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 812                 err = ENOMEM;
 813                 goto exit;
 814         }
 815         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 816                 uar_mapping = 0;
 817                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 818                                                         (sh->ctx, uar_mapping);
 819 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 820                 if (!sh->devx_rx_uar &&
 821                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 822                         /*
 823                          * Rx UAR is used to control interrupts only,
 824                          * should be no datapath noticeable impact,
 825                          * can try "Non-Cached" mapping safely.
 826                          */
 827                         DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
 828                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 829                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 830                                                         (sh->ctx, uar_mapping);
 831                 }
 832 #endif
 833                 if (!sh->devx_rx_uar) {
 834                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 835                         err = ENOMEM;
 836                         goto exit;
 837                 }
 838                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 839                 if (base_addr)
 840                         break;
 841                 /*
 842                  * The UARs are allocated by rdma_core within the
 843                  * IB device context, on context closure all UARs
 844                  * will be freed, should be no memory/object leakage.
 845                  */
 846                 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
 847                 sh->devx_rx_uar = NULL;
 848         }
 849         /* Check whether we finally succeeded with valid UAR allocation. */
 850         if (!sh->devx_rx_uar) {
 851                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 852                 err = ENOMEM;
 853         }
 854 exit:
 855         return err;
 856 }
 857
 858 /**
 859  * Allocate shared device context. If there is multiport device the
 860  * master and representors will share this context, if there is single
 861  * port dedicated device, the context will be used by only given
 862  * port due to unification.
 863  *
 864  * Routine first searches the context for the specified device name,
 865  * if found the shared context assumed and reference counter is incremented.
 866  * If no context found the new one is created and initialized with specified
 867  * device context and parameters.
 868  *
 869  * @param[in] spawn
 870  *   Pointer to the device attributes (name, port, etc).
 871  * @param[in] config
 872  *   Pointer to device configuration structure.
 873  *
 874  * @return
 875  *   Pointer to mlx5_dev_ctx_shared object on success,
 876  *   otherwise NULL and rte_errno is set.
 877  */
 878 struct mlx5_dev_ctx_shared *
 879 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 880                            const struct mlx5_dev_config *config)
 881 {
 882         struct mlx5_dev_ctx_shared *sh;
 883         int err = 0;
 884         uint32_t i;
 885         struct mlx5_devx_tis_attr tis_attr = { 0 };
 886
 887         MLX5_ASSERT(spawn);
 888         /* Secondary process should not create the shared context. */
 889         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 890         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 891         /* Search for IB context by device name. */
 892         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 893                 if (!strcmp(sh->ibdev_name,
 894                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 895                         sh->refcnt++;
 896                         goto exit;
 897                 }
 898         }
 899         /* No device found, we have to create new shared context. */
 900         MLX5_ASSERT(spawn->max_port);
 901         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 902                          sizeof(struct mlx5_dev_ctx_shared) +
 903                          spawn->max_port *
 904                          sizeof(struct mlx5_dev_shared_port),
 905                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 906         if (!sh) {
 907                 DRV_LOG(ERR, "shared context allocation failure");
 908                 rte_errno  = ENOMEM;
 909                 goto exit;
 910         }
 911         err = mlx5_os_open_device(spawn, config, sh);
 912         if (!sh->ctx)
 913                 goto error;
 914         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 915         if (err) {
 916                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 917                 goto error;
 918         }
 919         sh->refcnt = 1;
 920         sh->bond_dev = UINT16_MAX;
 921         sh->max_port = spawn->max_port;
 922         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 923                 sizeof(sh->ibdev_name) - 1);
 924         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 925                 sizeof(sh->ibdev_path) - 1);
 926         /*
 927          * Setting port_id to max unallowed value means
 928          * there is no interrupt subhandler installed for
 929          * the given port index i.
 930          */
 931         for (i = 0; i < sh->max_port; i++) {
 932                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 933                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 934         }
 935         sh->pd = mlx5_os_alloc_pd(sh->ctx);
 936         if (sh->pd == NULL) {
 937                 DRV_LOG(ERR, "PD allocation failure");
 938                 err = ENOMEM;
 939                 goto error;
 940         }
 941         if (sh->devx) {
 942                 /* Query the EQN for this core. */
 943                 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
 944                 if (err) {
 945                         rte_errno = errno;
 946                         DRV_LOG(ERR, "Failed to query event queue number %d.",
 947                                 rte_errno);
 948                         goto error;
 949                 }
 950                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 951                 if (err) {
 952                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 953                         goto error;
 954                 }
 955                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 956                 if (!sh->td) {
 957                         DRV_LOG(ERR, "TD allocation failure");
 958                         err = ENOMEM;
 959                         goto error;
 960                 }
 961                 tis_attr.transport_domain = sh->td->id;
 962                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 963                 if (!sh->tis) {
 964                         DRV_LOG(ERR, "TIS allocation failure");
 965                         err = ENOMEM;
 966                         goto error;
 967                 }
 968                 err = mlx5_alloc_rxtx_uars(sh, config);
 969                 if (err)
 970                         goto error;
 971                 MLX5_ASSERT(sh->tx_uar);
 972                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 973
 974                 MLX5_ASSERT(sh->devx_rx_uar);
 975                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 976         }
 977 #ifndef RTE_ARCH_64
 978         /* Initialize UAR access locks for 32bit implementations. */
 979         rte_spinlock_init(&sh->uar_lock_cq);
 980         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 981                 rte_spinlock_init(&sh->uar_lock[i]);
 982 #endif
 983         /*
 984          * Once the device is added to the list of memory event
 985          * callback, its global MR cache table cannot be expanded
 986          * on the fly because of deadlock. If it overflows, lookup
 987          * should be done by searching MR list linearly, which is slow.
 988          *
 989          * At this point the device is not added to the memory
 990          * event list yet, context is just being created.
 991          */
 992         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 993                                  MLX5_MR_BTREE_CACHE_N * 2,
 994                                  spawn->pci_dev->device.numa_node);
 995         if (err) {
 996                 err = rte_errno;
 997                 goto error;
 998         }
 999         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1000                               &sh->share_cache.dereg_mr_cb);
1001         mlx5_os_dev_shared_handler_install(sh);
1002         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1003         if (!sh->cnt_id_tbl) {
1004                 err = rte_errno;
1005                 goto error;
1006         }
1007         mlx5_flow_aging_init(sh);
1008         mlx5_flow_counters_mng_init(sh);
1009         mlx5_flow_ipool_create(sh, config);
1010         /* Add device to memory callback list. */
1011         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1012         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1013                          sh, mem_event_cb);
1014         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1015         /* Add context to the global device list. */
1016         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1017 exit:
1018         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1019         return sh;
1020 error:
1021         pthread_mutex_destroy(&sh->txpp.mutex);
1022         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1023         MLX5_ASSERT(sh);
1024         if (sh->cnt_id_tbl)
1025                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1026         if (sh->tis)
1027                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1028         if (sh->td)
1029                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1030         if (sh->devx_rx_uar)
1031                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1032         if (sh->tx_uar)
1033                 mlx5_glue->devx_free_uar(sh->tx_uar);
1034         if (sh->pd)
1035                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1036         if (sh->ctx)
1037                 claim_zero(mlx5_glue->close_device(sh->ctx));
1038         mlx5_free(sh);
1039         MLX5_ASSERT(err > 0);
1040         rte_errno = err;
1041         return NULL;
1042 }
1043
1044 /**
1045  * Free shared IB device context. Decrement counter and if zero free
1046  * all allocated resources and close handles.
1047  *
1048  * @param[in] sh
1049  *   Pointer to mlx5_dev_ctx_shared object to free
1050  */
1051 void
1052 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1053 {
1054         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1055 #ifdef RTE_LIBRTE_MLX5_DEBUG
1056         /* Check the object presence in the list. */
1057         struct mlx5_dev_ctx_shared *lctx;
1058
1059         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1060                 if (lctx == sh)
1061                         break;
1062         MLX5_ASSERT(lctx);
1063         if (lctx != sh) {
1064                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1065                 goto exit;
1066         }
1067 #endif
1068         MLX5_ASSERT(sh);
1069         MLX5_ASSERT(sh->refcnt);
1070         /* Secondary process should not free the shared context. */
1071         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1072         if (--sh->refcnt)
1073                 goto exit;
1074         /* Remove from memory callback device list. */
1075         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1076         LIST_REMOVE(sh, mem_event_cb);
1077         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1078         /* Release created Memory Regions. */
1079         mlx5_mr_release_cache(&sh->share_cache);
1080         /* Remove context from the global device list. */
1081         LIST_REMOVE(sh, next);
1082         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1083         /*
1084          *  Ensure there is no async event handler installed.
1085          *  Only primary process handles async device events.
1086          **/
1087         mlx5_flow_counters_mng_close(sh);
1088         if (sh->aso_age_mng) {
1089                 mlx5_flow_aso_age_mng_close(sh);
1090                 sh->aso_age_mng = NULL;
1091         }
1092         mlx5_flow_ipool_destroy(sh);
1093         mlx5_os_dev_shared_handler_uninstall(sh);
1094         if (sh->cnt_id_tbl) {
1095                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1096                 sh->cnt_id_tbl = NULL;
1097         }
1098         if (sh->tx_uar) {
1099                 mlx5_glue->devx_free_uar(sh->tx_uar);
1100                 sh->tx_uar = NULL;
1101         }
1102         if (sh->pd)
1103                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1104         if (sh->tis)
1105                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1106         if (sh->td)
1107                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1108         if (sh->devx_rx_uar)
1109                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1110         if (sh->ctx)
1111                 claim_zero(mlx5_glue->close_device(sh->ctx));
1112         pthread_mutex_destroy(&sh->txpp.mutex);
1113         mlx5_free(sh);
1114         return;
1115 exit:
1116         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1117 }
1118
1119 /**
1120  * Destroy table hash list.
1121  *
1122  * @param[in] priv
1123  *   Pointer to the private device data structure.
1124  */
1125 void
1126 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1127 {
1128         struct mlx5_dev_ctx_shared *sh = priv->sh;
1129
1130         if (!sh->flow_tbls)
1131                 return;
1132         mlx5_hlist_destroy(sh->flow_tbls);
1133 }
1134
1135 /**
1136  * Initialize flow table hash list and create the root tables entry
1137  * for each domain.
1138  *
1139  * @param[in] priv
1140  *   Pointer to the private device data structure.
1141  *
1142  * @return
1143  *   Zero on success, positive error code otherwise.
1144  */
1145 int
1146 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1147 {
1148         int err = 0;
1149         /* Tables are only used in DV and DR modes. */
1150 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1151         struct mlx5_dev_ctx_shared *sh = priv->sh;
1152         char s[MLX5_HLIST_NAMESIZE];
1153
1154         MLX5_ASSERT(sh);
1155         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1156         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1157                                           0, 0, flow_dv_tbl_create_cb,
1158                                           flow_dv_tbl_match_cb,
1159                                           flow_dv_tbl_remove_cb);
1160         if (!sh->flow_tbls) {
1161                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1162                 err = ENOMEM;
1163                 return err;
1164         }
1165         sh->flow_tbls->ctx = sh;
1166 #ifndef HAVE_MLX5DV_DR
1167         struct rte_flow_error error;
1168         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1169
1170         /*
1171          * In case we have not DR support, the zero tables should be created
1172          * because DV expect to see them even if they cannot be created by
1173          * RDMA-CORE.
1174          */
1175         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1176             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1177             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1178                 err = ENOMEM;
1179                 goto error;
1180         }
1181         return err;
1182 error:
1183         mlx5_free_table_hash_list(priv);
1184 #endif /* HAVE_MLX5DV_DR */
1185 #endif
1186         return err;
1187 }
1188
1189 /**
1190  * Retrieve integer value from environment variable.
1191  *
1192  * @param[in] name
1193  *   Environment variable name.
1194  *
1195  * @return
1196  *   Integer value, 0 if the variable is not set.
1197  */
1198 int
1199 mlx5_getenv_int(const char *name)
1200 {
1201         const char *val = getenv(name);
1202
1203         if (val == NULL)
1204                 return 0;
1205         return atoi(val);
1206 }
1207
1208 /**
1209  * DPDK callback to add udp tunnel port
1210  *
1211  * @param[in] dev
1212  *   A pointer to eth_dev
1213  * @param[in] udp_tunnel
1214  *   A pointer to udp tunnel
1215  *
1216  * @return
1217  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1218  */
1219 int
1220 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1221                          struct rte_eth_udp_tunnel *udp_tunnel)
1222 {
1223         MLX5_ASSERT(udp_tunnel != NULL);
1224         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1225             udp_tunnel->udp_port == 4789)
1226                 return 0;
1227         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1228             udp_tunnel->udp_port == 4790)
1229                 return 0;
1230         return -ENOTSUP;
1231 }
1232
1233 /**
1234  * Initialize process private data structure.
1235  *
1236  * @param dev
1237  *   Pointer to Ethernet device structure.
1238  *
1239  * @return
1240  *   0 on success, a negative errno value otherwise and rte_errno is set.
1241  */
1242 int
1243 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1244 {
1245         struct mlx5_priv *priv = dev->data->dev_private;
1246         struct mlx5_proc_priv *ppriv;
1247         size_t ppriv_size;
1248
1249         /*
1250          * UAR register table follows the process private structure. BlueFlame
1251          * registers for Tx queues are stored in the table.
1252          */
1253         ppriv_size =
1254                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1255         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1256                             dev->device->numa_node);
1257         if (!ppriv) {
1258                 rte_errno = ENOMEM;
1259                 return -rte_errno;
1260         }
1261         ppriv->uar_table_sz = ppriv_size;
1262         dev->process_private = ppriv;
1263         return 0;
1264 }
1265
1266 /**
1267  * Un-initialize process private data structure.
1268  *
1269  * @param dev
1270  *   Pointer to Ethernet device structure.
1271  */
1272 static void
1273 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1274 {
1275         if (!dev->process_private)
1276                 return;
1277         mlx5_free(dev->process_private);
1278         dev->process_private = NULL;
1279 }
1280
1281 /**
1282  * DPDK callback to close the device.
1283  *
1284  * Destroy all queues and objects, free memory.
1285  *
1286  * @param dev
1287  *   Pointer to Ethernet device structure.
1288  */
1289 int
1290 mlx5_dev_close(struct rte_eth_dev *dev)
1291 {
1292         struct mlx5_priv *priv = dev->data->dev_private;
1293         unsigned int i;
1294         int ret;
1295
1296         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1297                 /* Check if process_private released. */
1298                 if (!dev->process_private)
1299                         return 0;
1300                 mlx5_tx_uar_uninit_secondary(dev);
1301                 mlx5_proc_priv_uninit(dev);
1302                 rte_eth_dev_release_port(dev);
1303                 return 0;
1304         }
1305         if (!priv->sh)
1306                 return 0;
1307         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1308                 dev->data->port_id,
1309                 ((priv->sh->ctx != NULL) ?
1310                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1311         /*
1312          * If default mreg copy action is removed at the stop stage,
1313          * the search will return none and nothing will be done anymore.
1314          */
1315         mlx5_flow_stop_default(dev);
1316         mlx5_traffic_disable(dev);
1317         /*
1318          * If all the flows are already flushed in the device stop stage,
1319          * then this will return directly without any action.
1320          */
1321         mlx5_flow_list_flush(dev, &priv->flows, true);
1322         mlx5_shared_action_flush(dev);
1323         mlx5_flow_meter_flush(dev, NULL);
1324         /* Prevent crashes when queues are still in use. */
1325         dev->rx_pkt_burst = removed_rx_burst;
1326         dev->tx_pkt_burst = removed_tx_burst;
1327         rte_wmb();
1328         /* Disable datapath on secondary process. */
1329         mlx5_mp_os_req_stop_rxtx(dev);
1330         /* Free the eCPRI flex parser resource. */
1331         mlx5_flex_parser_ecpri_release(dev);
1332         if (priv->rxqs != NULL) {
1333                 /* XXX race condition if mlx5_rx_burst() is still running. */
1334                 rte_delay_us_sleep(1000);
1335                 for (i = 0; (i != priv->rxqs_n); ++i)
1336                         mlx5_rxq_release(dev, i);
1337                 priv->rxqs_n = 0;
1338                 priv->rxqs = NULL;
1339         }
1340         if (priv->txqs != NULL) {
1341                 /* XXX race condition if mlx5_tx_burst() is still running. */
1342                 rte_delay_us_sleep(1000);
1343                 for (i = 0; (i != priv->txqs_n); ++i)
1344                         mlx5_txq_release(dev, i);
1345                 priv->txqs_n = 0;
1346                 priv->txqs = NULL;
1347         }
1348         mlx5_proc_priv_uninit(dev);
1349         if (priv->drop_queue.hrxq)
1350                 mlx5_drop_action_destroy(dev);
1351         if (priv->mreg_cp_tbl)
1352                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1353         mlx5_mprq_free_mp(dev);
1354         mlx5_os_free_shared_dr(priv);
1355         if (priv->rss_conf.rss_key != NULL)
1356                 mlx5_free(priv->rss_conf.rss_key);
1357         if (priv->reta_idx != NULL)
1358                 mlx5_free(priv->reta_idx);
1359         if (priv->config.vf)
1360                 mlx5_os_mac_addr_flush(dev);
1361         if (priv->nl_socket_route >= 0)
1362                 close(priv->nl_socket_route);
1363         if (priv->nl_socket_rdma >= 0)
1364                 close(priv->nl_socket_rdma);
1365         if (priv->vmwa_context)
1366                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1367         ret = mlx5_hrxq_verify(dev);
1368         if (ret)
1369                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1370                         dev->data->port_id);
1371         ret = mlx5_ind_table_obj_verify(dev);
1372         if (ret)
1373                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1374                         dev->data->port_id);
1375         ret = mlx5_rxq_obj_verify(dev);
1376         if (ret)
1377                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1378                         dev->data->port_id);
1379         ret = mlx5_rxq_verify(dev);
1380         if (ret)
1381                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1382                         dev->data->port_id);
1383         ret = mlx5_txq_obj_verify(dev);
1384         if (ret)
1385                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1386                         dev->data->port_id);
1387         ret = mlx5_txq_verify(dev);
1388         if (ret)
1389                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1390                         dev->data->port_id);
1391         ret = mlx5_flow_verify(dev);
1392         if (ret)
1393                 DRV_LOG(WARNING, "port %u some flows still remain",
1394                         dev->data->port_id);
1395         mlx5_cache_list_destroy(&priv->hrxqs);
1396         /*
1397          * Free the shared context in last turn, because the cleanup
1398          * routines above may use some shared fields, like
1399          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1400          * ifindex if Netlink fails.
1401          */
1402         mlx5_free_shared_dev_ctx(priv->sh);
1403         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1404                 unsigned int c = 0;
1405                 uint16_t port_id;
1406
1407                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1408                         struct mlx5_priv *opriv =
1409                                 rte_eth_devices[port_id].data->dev_private;
1410
1411                         if (!opriv ||
1412                             opriv->domain_id != priv->domain_id ||
1413                             &rte_eth_devices[port_id] == dev)
1414                                 continue;
1415                         ++c;
1416                         break;
1417                 }
1418                 if (!c)
1419                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1420         }
1421         memset(priv, 0, sizeof(*priv));
1422         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1423         /*
1424          * Reset mac_addrs to NULL such that it is not freed as part of
1425          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1426          * it is freed when dev_private is freed.
1427          */
1428         dev->data->mac_addrs = NULL;
1429         return 0;
1430 }
1431
1432 /**
1433  * Verify and store value for device argument.
1434  *
1435  * @param[in] key
1436  *   Key argument to verify.
1437  * @param[in] val
1438  *   Value associated with key.
1439  * @param opaque
1440  *   User data.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 mlx5_args_check(const char *key, const char *val, void *opaque)
1447 {
1448         struct mlx5_dev_config *config = opaque;
1449         unsigned long mod;
1450         signed long tmp;
1451
1452         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1453         if (!strcmp(MLX5_REPRESENTOR, key))
1454                 return 0;
1455         errno = 0;
1456         tmp = strtol(val, NULL, 0);
1457         if (errno) {
1458                 rte_errno = errno;
1459                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1460                 return -rte_errno;
1461         }
1462         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1463                 /* Negative values are acceptable for some keys only. */
1464                 rte_errno = EINVAL;
1465                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1466                 return -rte_errno;
1467         }
1468         mod = tmp >= 0 ? tmp : -tmp;
1469         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1470                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1471                         DRV_LOG(ERR, "invalid CQE compression "
1472                                      "format parameter");
1473                         rte_errno = EINVAL;
1474                         return -rte_errno;
1475                 }
1476                 config->cqe_comp = !!tmp;
1477                 config->cqe_comp_fmt = tmp;
1478         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1479                 config->cqe_pad = !!tmp;
1480         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1481                 config->hw_padding = !!tmp;
1482         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1483                 config->mprq.enabled = !!tmp;
1484         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1485                 config->mprq.stride_num_n = tmp;
1486         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1487                 config->mprq.stride_size_n = tmp;
1488         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1489                 config->mprq.max_memcpy_len = tmp;
1490         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1491                 config->mprq.min_rxqs_num = tmp;
1492         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1493                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1494                                  " converted to txq_inline_max", key);
1495                 config->txq_inline_max = tmp;
1496         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1497                 config->txq_inline_max = tmp;
1498         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1499                 config->txq_inline_min = tmp;
1500         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1501                 config->txq_inline_mpw = tmp;
1502         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1503                 config->txqs_inline = tmp;
1504         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1505                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1506         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1507                 config->mps = !!tmp;
1508         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1509                 if (tmp != MLX5_TXDB_CACHED &&
1510                     tmp != MLX5_TXDB_NCACHED &&
1511                     tmp != MLX5_TXDB_HEURISTIC) {
1512                         DRV_LOG(ERR, "invalid Tx doorbell "
1513                                      "mapping parameter");
1514                         rte_errno = EINVAL;
1515                         return -rte_errno;
1516                 }
1517                 config->dbnc = tmp;
1518         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1519                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1520         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1521                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1522                                  " converted to txq_inline_mpw", key);
1523                 config->txq_inline_mpw = tmp;
1524         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1525                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1526         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1527                 if (!mod) {
1528                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1529                         rte_errno = EINVAL;
1530                         return -rte_errno;
1531                 }
1532                 config->tx_pp = tmp;
1533         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1534                 config->tx_skew = tmp;
1535         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1536                 config->rx_vec_en = !!tmp;
1537         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1538                 config->l3_vxlan_en = !!tmp;
1539         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1540                 config->vf_nl_en = !!tmp;
1541         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1542                 config->dv_esw_en = !!tmp;
1543         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1544                 config->dv_flow_en = !!tmp;
1545         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1546                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1547                     tmp != MLX5_XMETA_MODE_META16 &&
1548                     tmp != MLX5_XMETA_MODE_META32 &&
1549                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1550                         DRV_LOG(ERR, "invalid extensive "
1551                                      "metadata parameter");
1552                         rte_errno = EINVAL;
1553                         return -rte_errno;
1554                 }
1555                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1556                         config->dv_xmeta_en = tmp;
1557                 else
1558                         config->dv_miss_info = 1;
1559         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1560                 config->lacp_by_user = !!tmp;
1561         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1562                 config->mr_ext_memseg_en = !!tmp;
1563         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1564                 config->max_dump_files_num = tmp;
1565         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1566                 config->lro.timeout = tmp;
1567         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1568                 DRV_LOG(DEBUG, "class argument is %s.", val);
1569         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1570                 config->log_hp_size = tmp;
1571         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1572                 if (tmp != MLX5_RCM_NONE &&
1573                     tmp != MLX5_RCM_LIGHT &&
1574                     tmp != MLX5_RCM_AGGR) {
1575                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1576                         rte_errno = EINVAL;
1577                         return -rte_errno;
1578                 }
1579                 config->reclaim_mode = tmp;
1580         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1581                 config->sys_mem_en = !!tmp;
1582         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1583                 config->decap_en = !!tmp;
1584         } else {
1585                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1586                 rte_errno = EINVAL;
1587                 return -rte_errno;
1588         }
1589         return 0;
1590 }
1591
1592 /**
1593  * Parse device parameters.
1594  *
1595  * @param config
1596  *   Pointer to device configuration structure.
1597  * @param devargs
1598  *   Device arguments structure.
1599  *
1600  * @return
1601  *   0 on success, a negative errno value otherwise and rte_errno is set.
1602  */
1603 int
1604 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1605 {
1606         const char **params = (const char *[]){
1607                 MLX5_RXQ_CQE_COMP_EN,
1608                 MLX5_RXQ_CQE_PAD_EN,
1609                 MLX5_RXQ_PKT_PAD_EN,
1610                 MLX5_RX_MPRQ_EN,
1611                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1612                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1613                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1614                 MLX5_RXQS_MIN_MPRQ,
1615                 MLX5_TXQ_INLINE,
1616                 MLX5_TXQ_INLINE_MIN,
1617                 MLX5_TXQ_INLINE_MAX,
1618                 MLX5_TXQ_INLINE_MPW,
1619                 MLX5_TXQS_MIN_INLINE,
1620                 MLX5_TXQS_MAX_VEC,
1621                 MLX5_TXQ_MPW_EN,
1622                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1623                 MLX5_TXQ_MAX_INLINE_LEN,
1624                 MLX5_TX_DB_NC,
1625                 MLX5_TX_PP,
1626                 MLX5_TX_SKEW,
1627                 MLX5_TX_VEC_EN,
1628                 MLX5_RX_VEC_EN,
1629                 MLX5_L3_VXLAN_EN,
1630                 MLX5_VF_NL_EN,
1631                 MLX5_DV_ESW_EN,
1632                 MLX5_DV_FLOW_EN,
1633                 MLX5_DV_XMETA_EN,
1634                 MLX5_LACP_BY_USER,
1635                 MLX5_MR_EXT_MEMSEG_EN,
1636                 MLX5_REPRESENTOR,
1637                 MLX5_MAX_DUMP_FILES_NUM,
1638                 MLX5_LRO_TIMEOUT_USEC,
1639                 MLX5_CLASS_ARG_NAME,
1640                 MLX5_HP_BUF_SIZE,
1641                 MLX5_RECLAIM_MEM,
1642                 MLX5_SYS_MEM_EN,
1643                 MLX5_DECAP_EN,
1644                 NULL,
1645         };
1646         struct rte_kvargs *kvlist;
1647         int ret = 0;
1648         int i;
1649
1650         if (devargs == NULL)
1651                 return 0;
1652         /* Following UGLY cast is done to pass checkpatch. */
1653         kvlist = rte_kvargs_parse(devargs->args, params);
1654         if (kvlist == NULL) {
1655                 rte_errno = EINVAL;
1656                 return -rte_errno;
1657         }
1658         /* Process parameters. */
1659         for (i = 0; (params[i] != NULL); ++i) {
1660                 if (rte_kvargs_count(kvlist, params[i])) {
1661                         ret = rte_kvargs_process(kvlist, params[i],
1662                                                  mlx5_args_check, config);
1663                         if (ret) {
1664                                 rte_errno = EINVAL;
1665                                 rte_kvargs_free(kvlist);
1666                                 return -rte_errno;
1667                         }
1668                 }
1669         }
1670         rte_kvargs_free(kvlist);
1671         return 0;
1672 }
1673
1674 /**
1675  * Configures the minimal amount of data to inline into WQE
1676  * while sending packets.
1677  *
1678  * - the txq_inline_min has the maximal priority, if this
1679  *   key is specified in devargs
1680  * - if DevX is enabled the inline mode is queried from the
1681  *   device (HCA attributes and NIC vport context if needed).
1682  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1683  *   and none (0 bytes) for other NICs
1684  *
1685  * @param spawn
1686  *   Verbs device parameters (name, port, switch_info) to spawn.
1687  * @param config
1688  *   Device configuration parameters.
1689  */
1690 void
1691 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1692                     struct mlx5_dev_config *config)
1693 {
1694         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1695                 /* Application defines size of inlined data explicitly. */
1696                 switch (spawn->pci_dev->id.device_id) {
1697                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1698                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1699                         if (config->txq_inline_min <
1700                                        (int)MLX5_INLINE_HSIZE_L2) {
1701                                 DRV_LOG(DEBUG,
1702                                         "txq_inline_mix aligned to minimal"
1703                                         " ConnectX-4 required value %d",
1704                                         (int)MLX5_INLINE_HSIZE_L2);
1705                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1706                         }
1707                         break;
1708                 }
1709                 goto exit;
1710         }
1711         if (config->hca_attr.eth_net_offloads) {
1712                 /* We have DevX enabled, inline mode queried successfully. */
1713                 switch (config->hca_attr.wqe_inline_mode) {
1714                 case MLX5_CAP_INLINE_MODE_L2:
1715                         /* outer L2 header must be inlined. */
1716                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1717                         goto exit;
1718                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1719                         /* No inline data are required by NIC. */
1720                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1721                         config->hw_vlan_insert =
1722                                 config->hca_attr.wqe_vlan_insert;
1723                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1724                         goto exit;
1725                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1726                         /* inline mode is defined by NIC vport context. */
1727                         if (!config->hca_attr.eth_virt)
1728                                 break;
1729                         switch (config->hca_attr.vport_inline_mode) {
1730                         case MLX5_INLINE_MODE_NONE:
1731                                 config->txq_inline_min =
1732                                         MLX5_INLINE_HSIZE_NONE;
1733                                 goto exit;
1734                         case MLX5_INLINE_MODE_L2:
1735                                 config->txq_inline_min =
1736                                         MLX5_INLINE_HSIZE_L2;
1737                                 goto exit;
1738                         case MLX5_INLINE_MODE_IP:
1739                                 config->txq_inline_min =
1740                                         MLX5_INLINE_HSIZE_L3;
1741                                 goto exit;
1742                         case MLX5_INLINE_MODE_TCP_UDP:
1743                                 config->txq_inline_min =
1744                                         MLX5_INLINE_HSIZE_L4;
1745                                 goto exit;
1746                         case MLX5_INLINE_MODE_INNER_L2:
1747                                 config->txq_inline_min =
1748                                         MLX5_INLINE_HSIZE_INNER_L2;
1749                                 goto exit;
1750                         case MLX5_INLINE_MODE_INNER_IP:
1751                                 config->txq_inline_min =
1752                                         MLX5_INLINE_HSIZE_INNER_L3;
1753                                 goto exit;
1754                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1755                                 config->txq_inline_min =
1756                                         MLX5_INLINE_HSIZE_INNER_L4;
1757                                 goto exit;
1758                         }
1759                 }
1760         }
1761         /*
1762          * We get here if we are unable to deduce
1763          * inline data size with DevX. Try PCI ID
1764          * to determine old NICs.
1765          */
1766         switch (spawn->pci_dev->id.device_id) {
1767         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1768         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1769         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1770         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1771                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1772                 config->hw_vlan_insert = 0;
1773                 break;
1774         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1775         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1776         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1777         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1778                 /*
1779                  * These NICs support VLAN insertion from WQE and
1780                  * report the wqe_vlan_insert flag. But there is the bug
1781                  * and PFC control may be broken, so disable feature.
1782                  */
1783                 config->hw_vlan_insert = 0;
1784                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1785                 break;
1786         default:
1787                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1788                 break;
1789         }
1790 exit:
1791         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1792 }
1793
1794 /**
1795  * Configures the metadata mask fields in the shared context.
1796  *
1797  * @param [in] dev
1798  *   Pointer to Ethernet device.
1799  */
1800 void
1801 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1802 {
1803         struct mlx5_priv *priv = dev->data->dev_private;
1804         struct mlx5_dev_ctx_shared *sh = priv->sh;
1805         uint32_t meta, mark, reg_c0;
1806
1807         reg_c0 = ~priv->vport_meta_mask;
1808         switch (priv->config.dv_xmeta_en) {
1809         case MLX5_XMETA_MODE_LEGACY:
1810                 meta = UINT32_MAX;
1811                 mark = MLX5_FLOW_MARK_MASK;
1812                 break;
1813         case MLX5_XMETA_MODE_META16:
1814                 meta = reg_c0 >> rte_bsf32(reg_c0);
1815                 mark = MLX5_FLOW_MARK_MASK;
1816                 break;
1817         case MLX5_XMETA_MODE_META32:
1818                 meta = UINT32_MAX;
1819                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1820                 break;
1821         default:
1822                 meta = 0;
1823                 mark = 0;
1824                 MLX5_ASSERT(false);
1825                 break;
1826         }
1827         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1828                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1829                                  sh->dv_mark_mask, mark);
1830         else
1831                 sh->dv_mark_mask = mark;
1832         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1833                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1834                                  sh->dv_meta_mask, meta);
1835         else
1836                 sh->dv_meta_mask = meta;
1837         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1838                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1839                                  sh->dv_meta_mask, reg_c0);
1840         else
1841                 sh->dv_regc0_mask = reg_c0;
1842         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1843         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1844         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1845         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1846 }
1847
1848 int
1849 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1850 {
1851         static const char *const dynf_names[] = {
1852                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1853                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1854                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1855         };
1856         unsigned int i;
1857
1858         if (n < RTE_DIM(dynf_names))
1859                 return -ENOMEM;
1860         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1861                 if (names[i] == NULL)
1862                         return -EINVAL;
1863                 strcpy(names[i], dynf_names[i]);
1864         }
1865         return RTE_DIM(dynf_names);
1866 }
1867
1868 /**
1869  * Comparison callback to sort device data.
1870  *
1871  * This is meant to be used with qsort().
1872  *
1873  * @param a[in]
1874  *   Pointer to pointer to first data object.
1875  * @param b[in]
1876  *   Pointer to pointer to second data object.
1877  *
1878  * @return
1879  *   0 if both objects are equal, less than 0 if the first argument is less
1880  *   than the second, greater than 0 otherwise.
1881  */
1882 int
1883 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1884                               struct mlx5_dev_config *config)
1885 {
1886         struct mlx5_dev_ctx_shared *sh = priv->sh;
1887         struct mlx5_dev_config *sh_conf = NULL;
1888         uint16_t port_id;
1889
1890         MLX5_ASSERT(sh);
1891         /* Nothing to compare for the single/first device. */
1892         if (sh->refcnt == 1)
1893                 return 0;
1894         /* Find the device with shared context. */
1895         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1896                 struct mlx5_priv *opriv =
1897                         rte_eth_devices[port_id].data->dev_private;
1898
1899                 if (opriv && opriv != priv && opriv->sh == sh) {
1900                         sh_conf = &opriv->config;
1901                         break;
1902                 }
1903         }
1904         if (!sh_conf)
1905                 return 0;
1906         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1907                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1908                              " for shared %s context", sh->ibdev_name);
1909                 rte_errno = EINVAL;
1910                 return rte_errno;
1911         }
1912         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1913                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1914                              " for shared %s context", sh->ibdev_name);
1915                 rte_errno = EINVAL;
1916                 return rte_errno;
1917         }
1918         return 0;
1919 }
1920
1921 /**
1922  * Look for the ethernet device belonging to mlx5 driver.
1923  *
1924  * @param[in] port_id
1925  *   port_id to start looking for device.
1926  * @param[in] pci_dev
1927  *   Pointer to the hint PCI device. When device is being probed
1928  *   the its siblings (master and preceding representors might
1929  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1930  *   is not completed yet, for this case match on hint PCI
1931  *   device may be used to detect sibling device.
1932  *
1933  * @return
1934  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1935  */
1936 uint16_t
1937 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1938 {
1939         while (port_id < RTE_MAX_ETHPORTS) {
1940                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1941
1942                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1943                     dev->device &&
1944                     (dev->device == &pci_dev->device ||
1945                      (dev->device->driver &&
1946                      dev->device->driver->name &&
1947                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1948                         break;
1949                 port_id++;
1950         }
1951         if (port_id >= RTE_MAX_ETHPORTS)
1952                 return RTE_MAX_ETHPORTS;
1953         return port_id;
1954 }
1955
1956 /**
1957  * DPDK callback to remove a PCI device.
1958  *
1959  * This function removes all Ethernet devices belong to a given PCI device.
1960  *
1961  * @param[in] pci_dev
1962  *   Pointer to the PCI device.
1963  *
1964  * @return
1965  *   0 on success, the function cannot fail.
1966  */
1967 static int
1968 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1969 {
1970         uint16_t port_id;
1971         int ret = 0;
1972
1973         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1974                 /*
1975                  * mlx5_dev_close() is not registered to secondary process,
1976                  * call the close function explicitly for secondary process.
1977                  */
1978                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1979                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
1980                 else
1981                         ret |= rte_eth_dev_close(port_id);
1982         }
1983         return ret == 0 ? 0 : -EIO;
1984 }
1985
1986 static const struct rte_pci_id mlx5_pci_id_map[] = {
1987         {
1988                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1989                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1990         },
1991         {
1992                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1993                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1994         },
1995         {
1996                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1997                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1998         },
1999         {
2000                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2001                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2002         },
2003         {
2004                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2005                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2006         },
2007         {
2008                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2009                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2010         },
2011         {
2012                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2013                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2014         },
2015         {
2016                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2017                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2018         },
2019         {
2020                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2021                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2022         },
2023         {
2024                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2025                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2026         },
2027         {
2028                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2029                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2030         },
2031         {
2032                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2033                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2034         },
2035         {
2036                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2037                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2038         },
2039         {
2040                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2041                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2042         },
2043         {
2044                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2045                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2046         },
2047         {
2048                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2049                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2050         },
2051         {
2052                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2053                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2054         },
2055         {
2056                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2057                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2058         },
2059         {
2060                 .vendor_id = 0
2061         }
2062 };
2063
2064 static struct mlx5_pci_driver mlx5_driver = {
2065         .driver_class = MLX5_CLASS_NET,
2066         .pci_driver = {
2067                 .driver = {
2068                         .name = MLX5_DRIVER_NAME,
2069                 },
2070                 .id_table = mlx5_pci_id_map,
2071                 .probe = mlx5_os_pci_probe,
2072                 .remove = mlx5_pci_remove,
2073                 .dma_map = mlx5_dma_map,
2074                 .dma_unmap = mlx5_dma_unmap,
2075                 .drv_flags = PCI_DRV_FLAGS,
2076         },
2077 };
2078
2079 /* Initialize driver log type. */
2080 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2081
2082 /**
2083  * Driver initialization routine.
2084  */
2085 RTE_INIT(rte_mlx5_pmd_init)
2086 {
2087         mlx5_common_init();
2088         /* Build the static tables for Verbs conversion. */
2089         mlx5_set_ptype_table();
2090         mlx5_set_cksum_table();
2091         mlx5_set_swp_types_table();
2092         if (mlx5_glue)
2093                 mlx5_pci_driver_register(&mlx5_driver);
2094 }
2095
2096 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2097 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2098 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");