drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 203         {
 204                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 0,
 209                 .release_mem_en = 1,
 210                 .malloc = rte_malloc_socket,
 211                 .free = rte_free,
 212                 .type = "mlx5_encap_decap_ipool",
 213         },
 214         {
 215                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 0,
 220                 .release_mem_en = 1,
 221                 .malloc = rte_malloc_socket,
 222                 .free = rte_free,
 223                 .type = "mlx5_push_vlan_ipool",
 224         },
 225         {
 226                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 0,
 231                 .release_mem_en = 1,
 232                 .malloc = rte_malloc_socket,
 233                 .free = rte_free,
 234                 .type = "mlx5_tag_ipool",
 235         },
 236         {
 237                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 0,
 242                 .release_mem_en = 1,
 243                 .malloc = rte_malloc_socket,
 244                 .free = rte_free,
 245                 .type = "mlx5_port_id_ipool",
 246         },
 247         {
 248                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 0,
 253                 .release_mem_en = 1,
 254                 .malloc = rte_malloc_socket,
 255                 .free = rte_free,
 256                 .type = "mlx5_jump_ipool",
 257         },
 258 #endif
 259         {
 260                 .size = sizeof(struct mlx5_flow_meter),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 0,
 265                 .release_mem_en = 1,
 266                 .malloc = rte_malloc_socket,
 267                 .free = rte_free,
 268                 .type = "mlx5_meter_ipool",
 269         },
 270         {
 271                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 272                 .trunk_size = 64,
 273                 .grow_trunk = 3,
 274                 .grow_shift = 2,
 275                 .need_lock = 0,
 276                 .release_mem_en = 1,
 277                 .malloc = rte_malloc_socket,
 278                 .free = rte_free,
 279                 .type = "mlx5_mcp_ipool",
 280         },
 281         {
 282                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 283                 .trunk_size = 64,
 284                 .grow_trunk = 3,
 285                 .grow_shift = 2,
 286                 .need_lock = 0,
 287                 .release_mem_en = 1,
 288                 .malloc = rte_malloc_socket,
 289                 .free = rte_free,
 290                 .type = "mlx5_hrxq_ipool",
 291         },
 292         {
 293                 .size = sizeof(struct mlx5_flow_handle),
 294                 .trunk_size = 64,
 295                 .grow_trunk = 3,
 296                 .grow_shift = 2,
 297                 .need_lock = 0,
 298                 .release_mem_en = 1,
 299                 .malloc = rte_malloc_socket,
 300                 .free = rte_free,
 301                 .type = "mlx5_flow_handle_ipool",
 302         },
 303         {
 304                 .size = sizeof(struct rte_flow),
 305                 .trunk_size = 4096,
 306                 .need_lock = 1,
 307                 .release_mem_en = 1,
 308                 .malloc = rte_malloc_socket,
 309                 .free = rte_free,
 310                 .type = "rte_flow_ipool",
 311         },
 312 };
 313
 314
 315 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 316 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 317
 318 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 319 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_ibv_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_ibv_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_ibv_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 476                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 477         }
 478 }
 479
 480 /**
 481  * Destroy all the resources allocated for a counter memory management.
 482  *
 483  * @param[in] mng
 484  *   Pointer to the memory management structure.
 485  */
 486 static void
 487 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 488 {
 489         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 490
 491         LIST_REMOVE(mng, next);
 492         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 493         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 494         rte_free(mem);
 495 }
 496
 497 /**
 498  * Close and release all the resources of the counters management.
 499  *
 500  * @param[in] sh
 501  *   Pointer to mlx5_ibv_shared object to free.
 502  */
 503 static void
 504 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 505 {
 506         struct mlx5_counter_stats_mem_mng *mng;
 507         int i;
 508         int j;
 509         int retries = 1024;
 510
 511         rte_errno = 0;
 512         while (--retries) {
 513                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 514                 if (rte_errno != EINPROGRESS)
 515                         break;
 516                 rte_pause();
 517         }
 518         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 519                 struct mlx5_flow_counter_pool *pool;
 520                 uint32_t batch = !!(i > 1);
 521
 522                 if (!sh->cmng.ccont[i].pools)
 523                         continue;
 524                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 525                 while (pool) {
 526                         if (batch && pool->min_dcs)
 527                                 claim_zero(mlx5_devx_cmd_destroy
 528                                                                (pool->min_dcs));
 529                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 530                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 531                                         claim_zero
 532                                          (mlx5_glue->destroy_flow_action
 533                                           (MLX5_POOL_GET_CNT
 534                                           (pool, j)->action));
 535                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 536                                     (pool, j)->dcs)
 537                                         claim_zero(mlx5_devx_cmd_destroy
 538                                                    (MLX5_GET_POOL_CNT_EXT
 539                                                     (pool, j)->dcs));
 540                         }
 541                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 542                         rte_free(pool);
 543                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 544                 }
 545                 rte_free(sh->cmng.ccont[i].pools);
 546         }
 547         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 548         while (mng) {
 549                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 550                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 551         }
 552         memset(&sh->cmng, 0, sizeof(sh->cmng));
 553 }
 554
 555 /**
 556  * Initialize the flow resources' indexed mempool.
 557  *
 558  * @param[in] sh
 559  *   Pointer to mlx5_ibv_shared object.
 560  * @param[in] sh
 561  *   Pointer to user dev config.
 562  */
 563 static void
 564 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh,
 565                        const struct mlx5_dev_config *config __rte_unused)
 566 {
 567         uint8_t i;
 568
 569 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 570         /*
 571          * While DV is supported, user chooses the verbs mode,
 572          * the mlx5 flow handle size is different with the
 573          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 574          */
 575         if (!config->dv_flow_en)
 576                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 577                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 578 #endif
 579         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 580                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 581 }
 582
 583 /**
 584  * Release the flow resources' indexed mempool.
 585  *
 586  * @param[in] sh
 587  *   Pointer to mlx5_ibv_shared object.
 588  */
 589 static void
 590 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 591 {
 592         uint8_t i;
 593
 594         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 595                 mlx5_ipool_destroy(sh->ipool[i]);
 596 }
 597
 598 /**
 599  * Extract pdn of PD object using DV API.
 600  *
 601  * @param[in] pd
 602  *   Pointer to the verbs PD object.
 603  * @param[out] pdn
 604  *   Pointer to the PD object number variable.
 605  *
 606  * @return
 607  *   0 on success, error value otherwise.
 608  */
 609 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 610 static int
 611 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 612 {
 613         struct mlx5dv_obj obj;
 614         struct mlx5dv_pd pd_info;
 615         int ret = 0;
 616
 617         obj.pd.in = pd;
 618         obj.pd.out = &pd_info;
 619         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 620         if (ret) {
 621                 DRV_LOG(DEBUG, "Fail to get PD object info");
 622                 return ret;
 623         }
 624         *pdn = pd_info.pdn;
 625         return 0;
 626 }
 627 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 628
 629 static int
 630 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 631 {
 632         char *env;
 633         int value;
 634
 635         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 636         /* Get environment variable to store. */
 637         env = getenv(MLX5_SHUT_UP_BF);
 638         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 639         if (config->dbnc == MLX5_ARG_UNSET)
 640                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 641         else
 642                 setenv(MLX5_SHUT_UP_BF,
 643                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 644         return value;
 645 }
 646
 647 static void
 648 mlx5_restore_doorbell_mapping_env(int value)
 649 {
 650         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 651         /* Restore the original environment variable state. */
 652         if (value == MLX5_ARG_UNSET)
 653                 unsetenv(MLX5_SHUT_UP_BF);
 654         else
 655                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 656 }
 657
 658 /**
 659  * Allocate shared IB device context. If there is multiport device the
 660  * master and representors will share this context, if there is single
 661  * port dedicated IB device, the context will be used by only given
 662  * port due to unification.
 663  *
 664  * Routine first searches the context for the specified IB device name,
 665  * if found the shared context assumed and reference counter is incremented.
 666  * If no context found the new one is created and initialized with specified
 667  * IB device context and parameters.
 668  *
 669  * @param[in] spawn
 670  *   Pointer to the IB device attributes (name, port, etc).
 671  * @param[in] config
 672  *   Pointer to device configuration structure.
 673  *
 674  * @return
 675  *   Pointer to mlx5_ibv_shared object on success,
 676  *   otherwise NULL and rte_errno is set.
 677  */
 678 static struct mlx5_ibv_shared *
 679 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 680                         const struct mlx5_dev_config *config)
 681 {
 682         struct mlx5_ibv_shared *sh;
 683         int dbmap_env;
 684         int err = 0;
 685         uint32_t i;
 686 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 687         struct mlx5_devx_tis_attr tis_attr = { 0 };
 688 #endif
 689
 690         MLX5_ASSERT(spawn);
 691         /* Secondary process should not create the shared context. */
 692         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 693         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 694         /* Search for IB context by device name. */
 695         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 696                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 697                         sh->refcnt++;
 698                         goto exit;
 699                 }
 700         }
 701         /* No device found, we have to create new shared context. */
 702         MLX5_ASSERT(spawn->max_port);
 703         sh = rte_zmalloc("ethdev shared ib context",
 704                          sizeof(struct mlx5_ibv_shared) +
 705                          spawn->max_port *
 706                          sizeof(struct mlx5_ibv_shared_port),
 707                          RTE_CACHE_LINE_SIZE);
 708         if (!sh) {
 709                 DRV_LOG(ERR, "shared context allocation failure");
 710                 rte_errno  = ENOMEM;
 711                 goto exit;
 712         }
 713         /*
 714          * Configure environment variable "MLX5_BF_SHUT_UP"
 715          * before the device creation. The rdma_core library
 716          * checks the variable at device creation and
 717          * stores the result internally.
 718          */
 719         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 720         /* Try to open IB device with DV first, then usual Verbs. */
 721         errno = 0;
 722         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 723         if (sh->ctx) {
 724                 sh->devx = 1;
 725                 DRV_LOG(DEBUG, "DevX is supported");
 726                 /* The device is created, no need for environment. */
 727                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 728         } else {
 729                 /* The environment variable is still configured. */
 730                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 731                 err = errno ? errno : ENODEV;
 732                 /*
 733                  * The environment variable is not needed anymore,
 734                  * all device creation attempts are completed.
 735                  */
 736                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 737                 if (!sh->ctx)
 738                         goto error;
 739                 DRV_LOG(DEBUG, "DevX is NOT supported");
 740         }
 741         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 742         if (err) {
 743                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 744                 goto error;
 745         }
 746         sh->refcnt = 1;
 747         sh->max_port = spawn->max_port;
 748         strncpy(sh->ibdev_name, sh->ctx->device->name,
 749                 sizeof(sh->ibdev_name));
 750         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 751                 sizeof(sh->ibdev_path));
 752         pthread_mutex_init(&sh->intr_mutex, NULL);
 753         /*
 754          * Setting port_id to max unallowed value means
 755          * there is no interrupt subhandler installed for
 756          * the given port index i.
 757          */
 758         for (i = 0; i < sh->max_port; i++) {
 759                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 760                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 761         }
 762         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 763         if (sh->pd == NULL) {
 764                 DRV_LOG(ERR, "PD allocation failure");
 765                 err = ENOMEM;
 766                 goto error;
 767         }
 768 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 769         if (sh->devx) {
 770                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 771                 if (err) {
 772                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 773                         goto error;
 774                 }
 775                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 776                 if (!sh->td) {
 777                         DRV_LOG(ERR, "TD allocation failure");
 778                         err = ENOMEM;
 779                         goto error;
 780                 }
 781                 tis_attr.transport_domain = sh->td->id;
 782                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 783                 if (!sh->tis) {
 784                         DRV_LOG(ERR, "TIS allocation failure");
 785                         err = ENOMEM;
 786                         goto error;
 787                 }
 788         }
 789         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 790                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 791         if (!sh->flow_id_pool) {
 792                 DRV_LOG(ERR, "can't create flow id pool");
 793                 err = ENOMEM;
 794                 goto error;
 795         }
 796 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 797         /*
 798          * Once the device is added to the list of memory event
 799          * callback, its global MR cache table cannot be expanded
 800          * on the fly because of deadlock. If it overflows, lookup
 801          * should be done by searching MR list linearly, which is slow.
 802          *
 803          * At this point the device is not added to the memory
 804          * event list yet, context is just being created.
 805          */
 806         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 807                                  MLX5_MR_BTREE_CACHE_N * 2,
 808                                  spawn->pci_dev->device.numa_node);
 809         if (err) {
 810                 err = rte_errno;
 811                 goto error;
 812         }
 813         mlx5_flow_aging_init(sh);
 814         mlx5_flow_counters_mng_init(sh);
 815         mlx5_flow_ipool_create(sh, config);
 816         /* Add device to memory callback list. */
 817         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 818         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 819                          sh, mem_event_cb);
 820         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 821         /* Add context to the global device list. */
 822         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 823 exit:
 824         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 825         return sh;
 826 error:
 827         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 828         MLX5_ASSERT(sh);
 829         if (sh->tis)
 830                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 831         if (sh->td)
 832                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 833         if (sh->pd)
 834                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 835         if (sh->ctx)
 836                 claim_zero(mlx5_glue->close_device(sh->ctx));
 837         if (sh->flow_id_pool)
 838                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 839         rte_free(sh);
 840         MLX5_ASSERT(err > 0);
 841         rte_errno = err;
 842         return NULL;
 843 }
 844
 845 /**
 846  * Free shared IB device context. Decrement counter and if zero free
 847  * all allocated resources and close handles.
 848  *
 849  * @param[in] sh
 850  *   Pointer to mlx5_ibv_shared object to free
 851  */
 852 static void
 853 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 854 {
 855         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 856 #ifdef RTE_LIBRTE_MLX5_DEBUG
 857         /* Check the object presence in the list. */
 858         struct mlx5_ibv_shared *lctx;
 859
 860         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 861                 if (lctx == sh)
 862                         break;
 863         MLX5_ASSERT(lctx);
 864         if (lctx != sh) {
 865                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 866                 goto exit;
 867         }
 868 #endif
 869         MLX5_ASSERT(sh);
 870         MLX5_ASSERT(sh->refcnt);
 871         /* Secondary process should not free the shared context. */
 872         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 873         if (--sh->refcnt)
 874                 goto exit;
 875         /* Remove from memory callback device list. */
 876         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 877         LIST_REMOVE(sh, mem_event_cb);
 878         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 879         /* Release created Memory Regions. */
 880         mlx5_mr_release_cache(&sh->share_cache);
 881         /* Remove context from the global device list. */
 882         LIST_REMOVE(sh, next);
 883         /*
 884          *  Ensure there is no async event handler installed.
 885          *  Only primary process handles async device events.
 886          **/
 887         mlx5_flow_counters_mng_close(sh);
 888         mlx5_flow_ipool_destroy(sh);
 889         MLX5_ASSERT(!sh->intr_cnt);
 890         if (sh->intr_cnt)
 891                 mlx5_intr_callback_unregister
 892                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 893 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 894         if (sh->devx_intr_cnt) {
 895                 if (sh->intr_handle_devx.fd)
 896                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 897                                           mlx5_dev_interrupt_handler_devx, sh);
 898                 if (sh->devx_comp)
 899                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 900         }
 901 #endif
 902         pthread_mutex_destroy(&sh->intr_mutex);
 903         if (sh->pd)
 904                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 905         if (sh->tis)
 906                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 907         if (sh->td)
 908                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 909         if (sh->ctx)
 910                 claim_zero(mlx5_glue->close_device(sh->ctx));
 911         if (sh->flow_id_pool)
 912                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 913         rte_free(sh);
 914 exit:
 915         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 916 }
 917
 918 /**
 919  * Destroy table hash list and all the root entries per domain.
 920  *
 921  * @param[in] priv
 922  *   Pointer to the private device data structure.
 923  */
 924 static void
 925 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 926 {
 927         struct mlx5_ibv_shared *sh = priv->sh;
 928         struct mlx5_flow_tbl_data_entry *tbl_data;
 929         union mlx5_flow_tbl_key table_key = {
 930                 {
 931                         .table_id = 0,
 932                         .reserved = 0,
 933                         .domain = 0,
 934                         .direction = 0,
 935                 }
 936         };
 937         struct mlx5_hlist_entry *pos;
 938
 939         if (!sh->flow_tbls)
 940                 return;
 941         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 942         if (pos) {
 943                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 944                                         entry);
 945                 MLX5_ASSERT(tbl_data);
 946                 mlx5_hlist_remove(sh->flow_tbls, pos);
 947                 rte_free(tbl_data);
 948         }
 949         table_key.direction = 1;
 950         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 951         if (pos) {
 952                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 953                                         entry);
 954                 MLX5_ASSERT(tbl_data);
 955                 mlx5_hlist_remove(sh->flow_tbls, pos);
 956                 rte_free(tbl_data);
 957         }
 958         table_key.direction = 0;
 959         table_key.domain = 1;
 960         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 961         if (pos) {
 962                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 963                                         entry);
 964                 MLX5_ASSERT(tbl_data);
 965                 mlx5_hlist_remove(sh->flow_tbls, pos);
 966                 rte_free(tbl_data);
 967         }
 968         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 969 }
 970
 971 /**
 972  * Initialize flow table hash list and create the root tables entry
 973  * for each domain.
 974  *
 975  * @param[in] priv
 976  *   Pointer to the private device data structure.
 977  *
 978  * @return
 979  *   Zero on success, positive error code otherwise.
 980  */
 981 static int
 982 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 983 {
 984         struct mlx5_ibv_shared *sh = priv->sh;
 985         char s[MLX5_HLIST_NAMESIZE];
 986         int err = 0;
 987
 988         MLX5_ASSERT(sh);
 989         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 990         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 991         if (!sh->flow_tbls) {
 992                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 993                 err = ENOMEM;
 994                 return err;
 995         }
 996 #ifndef HAVE_MLX5DV_DR
 997         /*
 998          * In case we have not DR support, the zero tables should be created
 999          * because DV expect to see them even if they cannot be created by
1000          * RDMA-CORE.
1001          */
1002         union mlx5_flow_tbl_key table_key = {
1003                 {
1004                         .table_id = 0,
1005                         .reserved = 0,
1006                         .domain = 0,
1007                         .direction = 0,
1008                 }
1009         };
1010         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1011                                                           sizeof(*tbl_data), 0);
1012
1013         if (!tbl_data) {
1014                 err = ENOMEM;
1015                 goto error;
1016         }
1017         tbl_data->entry.key = table_key.v64;
1018         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1019         if (err)
1020                 goto error;
1021         rte_atomic32_init(&tbl_data->tbl.refcnt);
1022         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1023         table_key.direction = 1;
1024         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1025         if (!tbl_data) {
1026                 err = ENOMEM;
1027                 goto error;
1028         }
1029         tbl_data->entry.key = table_key.v64;
1030         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1031         if (err)
1032                 goto error;
1033         rte_atomic32_init(&tbl_data->tbl.refcnt);
1034         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1035         table_key.direction = 0;
1036         table_key.domain = 1;
1037         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1038         if (!tbl_data) {
1039                 err = ENOMEM;
1040                 goto error;
1041         }
1042         tbl_data->entry.key = table_key.v64;
1043         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1044         if (err)
1045                 goto error;
1046         rte_atomic32_init(&tbl_data->tbl.refcnt);
1047         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1048         return err;
1049 error:
1050         mlx5_free_table_hash_list(priv);
1051 #endif /* HAVE_MLX5DV_DR */
1052         return err;
1053 }
1054
1055 /**
1056  * Initialize DR related data within private structure.
1057  * Routine checks the reference counter and does actual
1058  * resources creation/initialization only if counter is zero.
1059  *
1060  * @param[in] priv
1061  *   Pointer to the private device data structure.
1062  *
1063  * @return
1064  *   Zero on success, positive error code otherwise.
1065  */
1066 static int
1067 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1068 {
1069         struct mlx5_ibv_shared *sh = priv->sh;
1070         char s[MLX5_HLIST_NAMESIZE];
1071         int err = 0;
1072
1073         if (!sh->flow_tbls)
1074                 err = mlx5_alloc_table_hash_list(priv);
1075         else
1076                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1077                         (void *)sh->flow_tbls);
1078         if (err)
1079                 return err;
1080         /* Create tags hash list table. */
1081         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1082         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1083         if (!sh->tag_table) {
1084                 DRV_LOG(ERR, "tags with hash creation failed.\n");
1085                 err = ENOMEM;
1086                 goto error;
1087         }
1088 #ifdef HAVE_MLX5DV_DR
1089         void *domain;
1090
1091         if (sh->dv_refcnt) {
1092                 /* Shared DV/DR structures is already initialized. */
1093                 sh->dv_refcnt++;
1094                 priv->dr_shared = 1;
1095                 return 0;
1096         }
1097         /* Reference counter is zero, we should initialize structures. */
1098         domain = mlx5_glue->dr_create_domain(sh->ctx,
1099                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1100         if (!domain) {
1101                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1102                 err = errno;
1103                 goto error;
1104         }
1105         sh->rx_domain = domain;
1106         domain = mlx5_glue->dr_create_domain(sh->ctx,
1107                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1108         if (!domain) {
1109                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1110                 err = errno;
1111                 goto error;
1112         }
1113         pthread_mutex_init(&sh->dv_mutex, NULL);
1114         sh->tx_domain = domain;
1115 #ifdef HAVE_MLX5DV_DR_ESWITCH
1116         if (priv->config.dv_esw_en) {
1117                 domain  = mlx5_glue->dr_create_domain
1118                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1119                 if (!domain) {
1120                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1121                         err = errno;
1122                         goto error;
1123                 }
1124                 sh->fdb_domain = domain;
1125                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1126         }
1127 #endif
1128         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1129 #endif /* HAVE_MLX5DV_DR */
1130         sh->dv_refcnt++;
1131         priv->dr_shared = 1;
1132         return 0;
1133 error:
1134         /* Rollback the created objects. */
1135         if (sh->rx_domain) {
1136                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1137                 sh->rx_domain = NULL;
1138         }
1139         if (sh->tx_domain) {
1140                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1141                 sh->tx_domain = NULL;
1142         }
1143         if (sh->fdb_domain) {
1144                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1145                 sh->fdb_domain = NULL;
1146         }
1147         if (sh->esw_drop_action) {
1148                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1149                 sh->esw_drop_action = NULL;
1150         }
1151         if (sh->pop_vlan_action) {
1152                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1153                 sh->pop_vlan_action = NULL;
1154         }
1155         if (sh->tag_table) {
1156                 /* tags should be destroyed with flow before. */
1157                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1158                 sh->tag_table = NULL;
1159         }
1160         mlx5_free_table_hash_list(priv);
1161         return err;
1162 }
1163
1164 /**
1165  * Destroy DR related data within private structure.
1166  *
1167  * @param[in] priv
1168  *   Pointer to the private device data structure.
1169  */
1170 static void
1171 mlx5_free_shared_dr(struct mlx5_priv *priv)
1172 {
1173         struct mlx5_ibv_shared *sh;
1174
1175         if (!priv->dr_shared)
1176                 return;
1177         priv->dr_shared = 0;
1178         sh = priv->sh;
1179         MLX5_ASSERT(sh);
1180 #ifdef HAVE_MLX5DV_DR
1181         MLX5_ASSERT(sh->dv_refcnt);
1182         if (sh->dv_refcnt && --sh->dv_refcnt)
1183                 return;
1184         if (sh->rx_domain) {
1185                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1186                 sh->rx_domain = NULL;
1187         }
1188         if (sh->tx_domain) {
1189                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1190                 sh->tx_domain = NULL;
1191         }
1192 #ifdef HAVE_MLX5DV_DR_ESWITCH
1193         if (sh->fdb_domain) {
1194                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1195                 sh->fdb_domain = NULL;
1196         }
1197         if (sh->esw_drop_action) {
1198                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1199                 sh->esw_drop_action = NULL;
1200         }
1201 #endif
1202         if (sh->pop_vlan_action) {
1203                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1204                 sh->pop_vlan_action = NULL;
1205         }
1206         pthread_mutex_destroy(&sh->dv_mutex);
1207 #endif /* HAVE_MLX5DV_DR */
1208         if (sh->tag_table) {
1209                 /* tags should be destroyed with flow before. */
1210                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1211                 sh->tag_table = NULL;
1212         }
1213         mlx5_free_table_hash_list(priv);
1214 }
1215
1216 /**
1217  * Initialize shared data between primary and secondary process.
1218  *
1219  * A memzone is reserved by primary process and secondary processes attach to
1220  * the memzone.
1221  *
1222  * @return
1223  *   0 on success, a negative errno value otherwise and rte_errno is set.
1224  */
1225 static int
1226 mlx5_init_shared_data(void)
1227 {
1228         const struct rte_memzone *mz;
1229         int ret = 0;
1230
1231         rte_spinlock_lock(&mlx5_shared_data_lock);
1232         if (mlx5_shared_data == NULL) {
1233                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1234                         /* Allocate shared memory. */
1235                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1236                                                  sizeof(*mlx5_shared_data),
1237                                                  SOCKET_ID_ANY, 0);
1238                         if (mz == NULL) {
1239                                 DRV_LOG(ERR,
1240                                         "Cannot allocate mlx5 shared data");
1241                                 ret = -rte_errno;
1242                                 goto error;
1243                         }
1244                         mlx5_shared_data = mz->addr;
1245                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1246                         rte_spinlock_init(&mlx5_shared_data->lock);
1247                 } else {
1248                         /* Lookup allocated shared memory. */
1249                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1250                         if (mz == NULL) {
1251                                 DRV_LOG(ERR,
1252                                         "Cannot attach mlx5 shared data");
1253                                 ret = -rte_errno;
1254                                 goto error;
1255                         }
1256                         mlx5_shared_data = mz->addr;
1257                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1258                 }
1259         }
1260 error:
1261         rte_spinlock_unlock(&mlx5_shared_data_lock);
1262         return ret;
1263 }
1264
1265 /**
1266  * Retrieve integer value from environment variable.
1267  *
1268  * @param[in] name
1269  *   Environment variable name.
1270  *
1271  * @return
1272  *   Integer value, 0 if the variable is not set.
1273  */
1274 int
1275 mlx5_getenv_int(const char *name)
1276 {
1277         const char *val = getenv(name);
1278
1279         if (val == NULL)
1280                 return 0;
1281         return atoi(val);
1282 }
1283
1284 /**
1285  * Verbs callback to allocate a memory. This function should allocate the space
1286  * according to the size provided residing inside a huge page.
1287  * Please note that all allocation must respect the alignment from libmlx5
1288  * (i.e. currently sysconf(_SC_PAGESIZE)).
1289  *
1290  * @param[in] size
1291  *   The size in bytes of the memory to allocate.
1292  * @param[in] data
1293  *   A pointer to the callback data.
1294  *
1295  * @return
1296  *   Allocated buffer, NULL otherwise and rte_errno is set.
1297  */
1298 static void *
1299 mlx5_alloc_verbs_buf(size_t size, void *data)
1300 {
1301         struct mlx5_priv *priv = data;
1302         void *ret;
1303         size_t alignment = sysconf(_SC_PAGESIZE);
1304         unsigned int socket = SOCKET_ID_ANY;
1305
1306         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1307                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1308
1309                 socket = ctrl->socket;
1310         } else if (priv->verbs_alloc_ctx.type ==
1311                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1312                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1313
1314                 socket = ctrl->socket;
1315         }
1316         MLX5_ASSERT(data != NULL);
1317         ret = rte_malloc_socket(__func__, size, alignment, socket);
1318         if (!ret && size)
1319                 rte_errno = ENOMEM;
1320         return ret;
1321 }
1322
1323 /**
1324  * Verbs callback to free a memory.
1325  *
1326  * @param[in] ptr
1327  *   A pointer to the memory to free.
1328  * @param[in] data
1329  *   A pointer to the callback data.
1330  */
1331 static void
1332 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1333 {
1334         MLX5_ASSERT(data != NULL);
1335         rte_free(ptr);
1336 }
1337
1338 /**
1339  * DPDK callback to add udp tunnel port
1340  *
1341  * @param[in] dev
1342  *   A pointer to eth_dev
1343  * @param[in] udp_tunnel
1344  *   A pointer to udp tunnel
1345  *
1346  * @return
1347  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1348  */
1349 int
1350 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1351                          struct rte_eth_udp_tunnel *udp_tunnel)
1352 {
1353         MLX5_ASSERT(udp_tunnel != NULL);
1354         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1355             udp_tunnel->udp_port == 4789)
1356                 return 0;
1357         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1358             udp_tunnel->udp_port == 4790)
1359                 return 0;
1360         return -ENOTSUP;
1361 }
1362
1363 /**
1364  * Initialize process private data structure.
1365  *
1366  * @param dev
1367  *   Pointer to Ethernet device structure.
1368  *
1369  * @return
1370  *   0 on success, a negative errno value otherwise and rte_errno is set.
1371  */
1372 int
1373 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1374 {
1375         struct mlx5_priv *priv = dev->data->dev_private;
1376         struct mlx5_proc_priv *ppriv;
1377         size_t ppriv_size;
1378
1379         /*
1380          * UAR register table follows the process private structure. BlueFlame
1381          * registers for Tx queues are stored in the table.
1382          */
1383         ppriv_size =
1384                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1385         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1386                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1387         if (!ppriv) {
1388                 rte_errno = ENOMEM;
1389                 return -rte_errno;
1390         }
1391         ppriv->uar_table_sz = ppriv_size;
1392         dev->process_private = ppriv;
1393         return 0;
1394 }
1395
1396 /**
1397  * Un-initialize process private data structure.
1398  *
1399  * @param dev
1400  *   Pointer to Ethernet device structure.
1401  */
1402 static void
1403 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1404 {
1405         if (!dev->process_private)
1406                 return;
1407         rte_free(dev->process_private);
1408         dev->process_private = NULL;
1409 }
1410
1411 /**
1412  * DPDK callback to close the device.
1413  *
1414  * Destroy all queues and objects, free memory.
1415  *
1416  * @param dev
1417  *   Pointer to Ethernet device structure.
1418  */
1419 static void
1420 mlx5_dev_close(struct rte_eth_dev *dev)
1421 {
1422         struct mlx5_priv *priv = dev->data->dev_private;
1423         unsigned int i;
1424         int ret;
1425
1426         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1427                 /* Check if process_private released. */
1428                 if (!dev->process_private)
1429                         return;
1430                 mlx5_tx_uar_uninit_secondary(dev);
1431                 mlx5_proc_priv_uninit(dev);
1432                 rte_eth_dev_release_port(dev);
1433                 return;
1434         }
1435         if (!priv->sh)
1436                 return;
1437         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1438                 dev->data->port_id,
1439                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1440         /* In case mlx5_dev_stop() has not been called. */
1441         mlx5_dev_interrupt_handler_uninstall(dev);
1442         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1443         /*
1444          * If default mreg copy action is removed at the stop stage,
1445          * the search will return none and nothing will be done anymore.
1446          */
1447         mlx5_flow_stop_default(dev);
1448         mlx5_traffic_disable(dev);
1449         /*
1450          * If all the flows are already flushed in the device stop stage,
1451          * then this will return directly without any action.
1452          */
1453         mlx5_flow_list_flush(dev, &priv->flows, true);
1454         mlx5_flow_meter_flush(dev, NULL);
1455         /* Free the intermediate buffers for flow creation. */
1456         mlx5_flow_free_intermediate(dev);
1457         /* Prevent crashes when queues are still in use. */
1458         dev->rx_pkt_burst = removed_rx_burst;
1459         dev->tx_pkt_burst = removed_tx_burst;
1460         rte_wmb();
1461         /* Disable datapath on secondary process. */
1462         mlx5_mp_req_stop_rxtx(dev);
1463         if (priv->rxqs != NULL) {
1464                 /* XXX race condition if mlx5_rx_burst() is still running. */
1465                 usleep(1000);
1466                 for (i = 0; (i != priv->rxqs_n); ++i)
1467                         mlx5_rxq_release(dev, i);
1468                 priv->rxqs_n = 0;
1469                 priv->rxqs = NULL;
1470         }
1471         if (priv->txqs != NULL) {
1472                 /* XXX race condition if mlx5_tx_burst() is still running. */
1473                 usleep(1000);
1474                 for (i = 0; (i != priv->txqs_n); ++i)
1475                         mlx5_txq_release(dev, i);
1476                 priv->txqs_n = 0;
1477                 priv->txqs = NULL;
1478         }
1479         mlx5_proc_priv_uninit(dev);
1480         if (priv->mreg_cp_tbl)
1481                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1482         mlx5_mprq_free_mp(dev);
1483         mlx5_free_shared_dr(priv);
1484         if (priv->rss_conf.rss_key != NULL)
1485                 rte_free(priv->rss_conf.rss_key);
1486         if (priv->reta_idx != NULL)
1487                 rte_free(priv->reta_idx);
1488         if (priv->config.vf)
1489                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1490                                        dev->data->mac_addrs,
1491                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1492         if (priv->nl_socket_route >= 0)
1493                 close(priv->nl_socket_route);
1494         if (priv->nl_socket_rdma >= 0)
1495                 close(priv->nl_socket_rdma);
1496         if (priv->vmwa_context)
1497                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1498         ret = mlx5_hrxq_verify(dev);
1499         if (ret)
1500                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1501                         dev->data->port_id);
1502         ret = mlx5_ind_table_obj_verify(dev);
1503         if (ret)
1504                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1505                         dev->data->port_id);
1506         ret = mlx5_rxq_obj_verify(dev);
1507         if (ret)
1508                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1509                         dev->data->port_id);
1510         ret = mlx5_rxq_verify(dev);
1511         if (ret)
1512                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1513                         dev->data->port_id);
1514         ret = mlx5_txq_obj_verify(dev);
1515         if (ret)
1516                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1517                         dev->data->port_id);
1518         ret = mlx5_txq_verify(dev);
1519         if (ret)
1520                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1521                         dev->data->port_id);
1522         ret = mlx5_flow_verify(dev);
1523         if (ret)
1524                 DRV_LOG(WARNING, "port %u some flows still remain",
1525                         dev->data->port_id);
1526         /*
1527          * Free the shared context in last turn, because the cleanup
1528          * routines above may use some shared fields, like
1529          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1530          * ifindex if Netlink fails.
1531          */
1532         mlx5_free_shared_ibctx(priv->sh);
1533         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1534                 unsigned int c = 0;
1535                 uint16_t port_id;
1536
1537                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1538                         struct mlx5_priv *opriv =
1539                                 rte_eth_devices[port_id].data->dev_private;
1540
1541                         if (!opriv ||
1542                             opriv->domain_id != priv->domain_id ||
1543                             &rte_eth_devices[port_id] == dev)
1544                                 continue;
1545                         ++c;
1546                         break;
1547                 }
1548                 if (!c)
1549                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1550         }
1551         memset(priv, 0, sizeof(*priv));
1552         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1553         /*
1554          * Reset mac_addrs to NULL such that it is not freed as part of
1555          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1556          * it is freed when dev_private is freed.
1557          */
1558         dev->data->mac_addrs = NULL;
1559 }
1560
1561 const struct eth_dev_ops mlx5_dev_ops = {
1562         .dev_configure = mlx5_dev_configure,
1563         .dev_start = mlx5_dev_start,
1564         .dev_stop = mlx5_dev_stop,
1565         .dev_set_link_down = mlx5_set_link_down,
1566         .dev_set_link_up = mlx5_set_link_up,
1567         .dev_close = mlx5_dev_close,
1568         .promiscuous_enable = mlx5_promiscuous_enable,
1569         .promiscuous_disable = mlx5_promiscuous_disable,
1570         .allmulticast_enable = mlx5_allmulticast_enable,
1571         .allmulticast_disable = mlx5_allmulticast_disable,
1572         .link_update = mlx5_link_update,
1573         .stats_get = mlx5_stats_get,
1574         .stats_reset = mlx5_stats_reset,
1575         .xstats_get = mlx5_xstats_get,
1576         .xstats_reset = mlx5_xstats_reset,
1577         .xstats_get_names = mlx5_xstats_get_names,
1578         .fw_version_get = mlx5_fw_version_get,
1579         .dev_infos_get = mlx5_dev_infos_get,
1580         .read_clock = mlx5_read_clock,
1581         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1582         .vlan_filter_set = mlx5_vlan_filter_set,
1583         .rx_queue_setup = mlx5_rx_queue_setup,
1584         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1585         .tx_queue_setup = mlx5_tx_queue_setup,
1586         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1587         .rx_queue_release = mlx5_rx_queue_release,
1588         .tx_queue_release = mlx5_tx_queue_release,
1589         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1590         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1591         .mac_addr_remove = mlx5_mac_addr_remove,
1592         .mac_addr_add = mlx5_mac_addr_add,
1593         .mac_addr_set = mlx5_mac_addr_set,
1594         .set_mc_addr_list = mlx5_set_mc_addr_list,
1595         .mtu_set = mlx5_dev_set_mtu,
1596         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1597         .vlan_offload_set = mlx5_vlan_offload_set,
1598         .reta_update = mlx5_dev_rss_reta_update,
1599         .reta_query = mlx5_dev_rss_reta_query,
1600         .rss_hash_update = mlx5_rss_hash_update,
1601         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1602         .filter_ctrl = mlx5_dev_filter_ctrl,
1603         .rx_descriptor_status = mlx5_rx_descriptor_status,
1604         .tx_descriptor_status = mlx5_tx_descriptor_status,
1605         .rxq_info_get = mlx5_rxq_info_get,
1606         .txq_info_get = mlx5_txq_info_get,
1607         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1608         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1609         .rx_queue_count = mlx5_rx_queue_count,
1610         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1611         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1612         .is_removed = mlx5_is_removed,
1613         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1614         .get_module_info = mlx5_get_module_info,
1615         .get_module_eeprom = mlx5_get_module_eeprom,
1616         .hairpin_cap_get = mlx5_hairpin_cap_get,
1617         .mtr_ops_get = mlx5_flow_meter_ops_get,
1618 };
1619
1620 /* Available operations from secondary process. */
1621 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1622         .stats_get = mlx5_stats_get,
1623         .stats_reset = mlx5_stats_reset,
1624         .xstats_get = mlx5_xstats_get,
1625         .xstats_reset = mlx5_xstats_reset,
1626         .xstats_get_names = mlx5_xstats_get_names,
1627         .fw_version_get = mlx5_fw_version_get,
1628         .dev_infos_get = mlx5_dev_infos_get,
1629         .rx_descriptor_status = mlx5_rx_descriptor_status,
1630         .tx_descriptor_status = mlx5_tx_descriptor_status,
1631         .rxq_info_get = mlx5_rxq_info_get,
1632         .txq_info_get = mlx5_txq_info_get,
1633         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1634         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1635         .get_module_info = mlx5_get_module_info,
1636         .get_module_eeprom = mlx5_get_module_eeprom,
1637 };
1638
1639 /* Available operations in flow isolated mode. */
1640 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1641         .dev_configure = mlx5_dev_configure,
1642         .dev_start = mlx5_dev_start,
1643         .dev_stop = mlx5_dev_stop,
1644         .dev_set_link_down = mlx5_set_link_down,
1645         .dev_set_link_up = mlx5_set_link_up,
1646         .dev_close = mlx5_dev_close,
1647         .promiscuous_enable = mlx5_promiscuous_enable,
1648         .promiscuous_disable = mlx5_promiscuous_disable,
1649         .allmulticast_enable = mlx5_allmulticast_enable,
1650         .allmulticast_disable = mlx5_allmulticast_disable,
1651         .link_update = mlx5_link_update,
1652         .stats_get = mlx5_stats_get,
1653         .stats_reset = mlx5_stats_reset,
1654         .xstats_get = mlx5_xstats_get,
1655         .xstats_reset = mlx5_xstats_reset,
1656         .xstats_get_names = mlx5_xstats_get_names,
1657         .fw_version_get = mlx5_fw_version_get,
1658         .dev_infos_get = mlx5_dev_infos_get,
1659         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1660         .vlan_filter_set = mlx5_vlan_filter_set,
1661         .rx_queue_setup = mlx5_rx_queue_setup,
1662         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1663         .tx_queue_setup = mlx5_tx_queue_setup,
1664         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1665         .rx_queue_release = mlx5_rx_queue_release,
1666         .tx_queue_release = mlx5_tx_queue_release,
1667         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1668         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1669         .mac_addr_remove = mlx5_mac_addr_remove,
1670         .mac_addr_add = mlx5_mac_addr_add,
1671         .mac_addr_set = mlx5_mac_addr_set,
1672         .set_mc_addr_list = mlx5_set_mc_addr_list,
1673         .mtu_set = mlx5_dev_set_mtu,
1674         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1675         .vlan_offload_set = mlx5_vlan_offload_set,
1676         .filter_ctrl = mlx5_dev_filter_ctrl,
1677         .rx_descriptor_status = mlx5_rx_descriptor_status,
1678         .tx_descriptor_status = mlx5_tx_descriptor_status,
1679         .rxq_info_get = mlx5_rxq_info_get,
1680         .txq_info_get = mlx5_txq_info_get,
1681         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1682         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1683         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1684         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1685         .is_removed = mlx5_is_removed,
1686         .get_module_info = mlx5_get_module_info,
1687         .get_module_eeprom = mlx5_get_module_eeprom,
1688         .hairpin_cap_get = mlx5_hairpin_cap_get,
1689         .mtr_ops_get = mlx5_flow_meter_ops_get,
1690 };
1691
1692 /**
1693  * Verify and store value for device argument.
1694  *
1695  * @param[in] key
1696  *   Key argument to verify.
1697  * @param[in] val
1698  *   Value associated with key.
1699  * @param opaque
1700  *   User data.
1701  *
1702  * @return
1703  *   0 on success, a negative errno value otherwise and rte_errno is set.
1704  */
1705 static int
1706 mlx5_args_check(const char *key, const char *val, void *opaque)
1707 {
1708         struct mlx5_dev_config *config = opaque;
1709         unsigned long tmp;
1710
1711         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1712         if (!strcmp(MLX5_REPRESENTOR, key))
1713                 return 0;
1714         errno = 0;
1715         tmp = strtoul(val, NULL, 0);
1716         if (errno) {
1717                 rte_errno = errno;
1718                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1719                 return -rte_errno;
1720         }
1721         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1722                 config->cqe_comp = !!tmp;
1723         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1724                 config->cqe_pad = !!tmp;
1725         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1726                 config->hw_padding = !!tmp;
1727         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1728                 config->mprq.enabled = !!tmp;
1729         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1730                 config->mprq.stride_num_n = tmp;
1731         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1732                 config->mprq.stride_size_n = tmp;
1733         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1734                 config->mprq.max_memcpy_len = tmp;
1735         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1736                 config->mprq.min_rxqs_num = tmp;
1737         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1738                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1739                                  " converted to txq_inline_max", key);
1740                 config->txq_inline_max = tmp;
1741         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1742                 config->txq_inline_max = tmp;
1743         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1744                 config->txq_inline_min = tmp;
1745         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1746                 config->txq_inline_mpw = tmp;
1747         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1748                 config->txqs_inline = tmp;
1749         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1750                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1751         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1752                 config->mps = !!tmp;
1753         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1754                 if (tmp != MLX5_TXDB_CACHED &&
1755                     tmp != MLX5_TXDB_NCACHED &&
1756                     tmp != MLX5_TXDB_HEURISTIC) {
1757                         DRV_LOG(ERR, "invalid Tx doorbell "
1758                                      "mapping parameter");
1759                         rte_errno = EINVAL;
1760                         return -rte_errno;
1761                 }
1762                 config->dbnc = tmp;
1763         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1764                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1765         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1766                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1767                                  " converted to txq_inline_mpw", key);
1768                 config->txq_inline_mpw = tmp;
1769         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1770                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1771         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1772                 config->rx_vec_en = !!tmp;
1773         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1774                 config->l3_vxlan_en = !!tmp;
1775         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1776                 config->vf_nl_en = !!tmp;
1777         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1778                 config->dv_esw_en = !!tmp;
1779         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1780                 config->dv_flow_en = !!tmp;
1781         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1782                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1783                     tmp != MLX5_XMETA_MODE_META16 &&
1784                     tmp != MLX5_XMETA_MODE_META32) {
1785                         DRV_LOG(ERR, "invalid extensive "
1786                                      "metadata parameter");
1787                         rte_errno = EINVAL;
1788                         return -rte_errno;
1789                 }
1790                 config->dv_xmeta_en = tmp;
1791         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1792                 config->mr_ext_memseg_en = !!tmp;
1793         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1794                 config->max_dump_files_num = tmp;
1795         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1796                 config->lro.timeout = tmp;
1797         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1798                 DRV_LOG(DEBUG, "class argument is %s.", val);
1799         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1800                 config->log_hp_size = tmp;
1801         } else {
1802                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1803                 rte_errno = EINVAL;
1804                 return -rte_errno;
1805         }
1806         return 0;
1807 }
1808
1809 /**
1810  * Parse device parameters.
1811  *
1812  * @param config
1813  *   Pointer to device configuration structure.
1814  * @param devargs
1815  *   Device arguments structure.
1816  *
1817  * @return
1818  *   0 on success, a negative errno value otherwise and rte_errno is set.
1819  */
1820 static int
1821 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1822 {
1823         const char **params = (const char *[]){
1824                 MLX5_RXQ_CQE_COMP_EN,
1825                 MLX5_RXQ_CQE_PAD_EN,
1826                 MLX5_RXQ_PKT_PAD_EN,
1827                 MLX5_RX_MPRQ_EN,
1828                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1829                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1830                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1831                 MLX5_RXQS_MIN_MPRQ,
1832                 MLX5_TXQ_INLINE,
1833                 MLX5_TXQ_INLINE_MIN,
1834                 MLX5_TXQ_INLINE_MAX,
1835                 MLX5_TXQ_INLINE_MPW,
1836                 MLX5_TXQS_MIN_INLINE,
1837                 MLX5_TXQS_MAX_VEC,
1838                 MLX5_TXQ_MPW_EN,
1839                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1840                 MLX5_TXQ_MAX_INLINE_LEN,
1841                 MLX5_TX_DB_NC,
1842                 MLX5_TX_VEC_EN,
1843                 MLX5_RX_VEC_EN,
1844                 MLX5_L3_VXLAN_EN,
1845                 MLX5_VF_NL_EN,
1846                 MLX5_DV_ESW_EN,
1847                 MLX5_DV_FLOW_EN,
1848                 MLX5_DV_XMETA_EN,
1849                 MLX5_MR_EXT_MEMSEG_EN,
1850                 MLX5_REPRESENTOR,
1851                 MLX5_MAX_DUMP_FILES_NUM,
1852                 MLX5_LRO_TIMEOUT_USEC,
1853                 MLX5_CLASS_ARG_NAME,
1854                 MLX5_HP_BUF_SIZE,
1855                 NULL,
1856         };
1857         struct rte_kvargs *kvlist;
1858         int ret = 0;
1859         int i;
1860
1861         if (devargs == NULL)
1862                 return 0;
1863         /* Following UGLY cast is done to pass checkpatch. */
1864         kvlist = rte_kvargs_parse(devargs->args, params);
1865         if (kvlist == NULL) {
1866                 rte_errno = EINVAL;
1867                 return -rte_errno;
1868         }
1869         /* Process parameters. */
1870         for (i = 0; (params[i] != NULL); ++i) {
1871                 if (rte_kvargs_count(kvlist, params[i])) {
1872                         ret = rte_kvargs_process(kvlist, params[i],
1873                                                  mlx5_args_check, config);
1874                         if (ret) {
1875                                 rte_errno = EINVAL;
1876                                 rte_kvargs_free(kvlist);
1877                                 return -rte_errno;
1878                         }
1879                 }
1880         }
1881         rte_kvargs_free(kvlist);
1882         return 0;
1883 }
1884
1885 static struct rte_pci_driver mlx5_driver;
1886
1887 /**
1888  * PMD global initialization.
1889  *
1890  * Independent from individual device, this function initializes global
1891  * per-PMD data structures distinguishing primary and secondary processes.
1892  * Hence, each initialization is called once per a process.
1893  *
1894  * @return
1895  *   0 on success, a negative errno value otherwise and rte_errno is set.
1896  */
1897 static int
1898 mlx5_init_once(void)
1899 {
1900         struct mlx5_shared_data *sd;
1901         struct mlx5_local_data *ld = &mlx5_local_data;
1902         int ret = 0;
1903
1904         if (mlx5_init_shared_data())
1905                 return -rte_errno;
1906         sd = mlx5_shared_data;
1907         MLX5_ASSERT(sd);
1908         rte_spinlock_lock(&sd->lock);
1909         switch (rte_eal_process_type()) {
1910         case RTE_PROC_PRIMARY:
1911                 if (sd->init_done)
1912                         break;
1913                 LIST_INIT(&sd->mem_event_cb_list);
1914                 rte_rwlock_init(&sd->mem_event_rwlock);
1915                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1916                                                 mlx5_mr_mem_event_cb, NULL);
1917                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1918                                            mlx5_mp_primary_handle);
1919                 if (ret)
1920                         goto out;
1921                 sd->init_done = true;
1922                 break;
1923         case RTE_PROC_SECONDARY:
1924                 if (ld->init_done)
1925                         break;
1926                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1927                                              mlx5_mp_secondary_handle);
1928                 if (ret)
1929                         goto out;
1930                 ++sd->secondary_cnt;
1931                 ld->init_done = true;
1932                 break;
1933         default:
1934                 break;
1935         }
1936 out:
1937         rte_spinlock_unlock(&sd->lock);
1938         return ret;
1939 }
1940
1941 /**
1942  * Configures the minimal amount of data to inline into WQE
1943  * while sending packets.
1944  *
1945  * - the txq_inline_min has the maximal priority, if this
1946  *   key is specified in devargs
1947  * - if DevX is enabled the inline mode is queried from the
1948  *   device (HCA attributes and NIC vport context if needed).
1949  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1950  *   and none (0 bytes) for other NICs
1951  *
1952  * @param spawn
1953  *   Verbs device parameters (name, port, switch_info) to spawn.
1954  * @param config
1955  *   Device configuration parameters.
1956  */
1957 static void
1958 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1959                     struct mlx5_dev_config *config)
1960 {
1961         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1962                 /* Application defines size of inlined data explicitly. */
1963                 switch (spawn->pci_dev->id.device_id) {
1964                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1965                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1966                         if (config->txq_inline_min <
1967                                        (int)MLX5_INLINE_HSIZE_L2) {
1968                                 DRV_LOG(DEBUG,
1969                                         "txq_inline_mix aligned to minimal"
1970                                         " ConnectX-4 required value %d",
1971                                         (int)MLX5_INLINE_HSIZE_L2);
1972                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1973                         }
1974                         break;
1975                 }
1976                 goto exit;
1977         }
1978         if (config->hca_attr.eth_net_offloads) {
1979                 /* We have DevX enabled, inline mode queried successfully. */
1980                 switch (config->hca_attr.wqe_inline_mode) {
1981                 case MLX5_CAP_INLINE_MODE_L2:
1982                         /* outer L2 header must be inlined. */
1983                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1984                         goto exit;
1985                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1986                         /* No inline data are required by NIC. */
1987                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1988                         config->hw_vlan_insert =
1989                                 config->hca_attr.wqe_vlan_insert;
1990                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1991                         goto exit;
1992                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1993                         /* inline mode is defined by NIC vport context. */
1994                         if (!config->hca_attr.eth_virt)
1995                                 break;
1996                         switch (config->hca_attr.vport_inline_mode) {
1997                         case MLX5_INLINE_MODE_NONE:
1998                                 config->txq_inline_min =
1999                                         MLX5_INLINE_HSIZE_NONE;
2000                                 goto exit;
2001                         case MLX5_INLINE_MODE_L2:
2002                                 config->txq_inline_min =
2003                                         MLX5_INLINE_HSIZE_L2;
2004                                 goto exit;
2005                         case MLX5_INLINE_MODE_IP:
2006                                 config->txq_inline_min =
2007                                         MLX5_INLINE_HSIZE_L3;
2008                                 goto exit;
2009                         case MLX5_INLINE_MODE_TCP_UDP:
2010                                 config->txq_inline_min =
2011                                         MLX5_INLINE_HSIZE_L4;
2012                                 goto exit;
2013                         case MLX5_INLINE_MODE_INNER_L2:
2014                                 config->txq_inline_min =
2015                                         MLX5_INLINE_HSIZE_INNER_L2;
2016                                 goto exit;
2017                         case MLX5_INLINE_MODE_INNER_IP:
2018                                 config->txq_inline_min =
2019                                         MLX5_INLINE_HSIZE_INNER_L3;
2020                                 goto exit;
2021                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2022                                 config->txq_inline_min =
2023                                         MLX5_INLINE_HSIZE_INNER_L4;
2024                                 goto exit;
2025                         }
2026                 }
2027         }
2028         /*
2029          * We get here if we are unable to deduce
2030          * inline data size with DevX. Try PCI ID
2031          * to determine old NICs.
2032          */
2033         switch (spawn->pci_dev->id.device_id) {
2034         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2035         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2036         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2037         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2038                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2039                 config->hw_vlan_insert = 0;
2040                 break;
2041         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2042         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2043         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2044         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2045                 /*
2046                  * These NICs support VLAN insertion from WQE and
2047                  * report the wqe_vlan_insert flag. But there is the bug
2048                  * and PFC control may be broken, so disable feature.
2049                  */
2050                 config->hw_vlan_insert = 0;
2051                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2052                 break;
2053         default:
2054                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2055                 break;
2056         }
2057 exit:
2058         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2059 }
2060
2061 /**
2062  * Configures the metadata mask fields in the shared context.
2063  *
2064  * @param [in] dev
2065  *   Pointer to Ethernet device.
2066  */
2067 static void
2068 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2069 {
2070         struct mlx5_priv *priv = dev->data->dev_private;
2071         struct mlx5_ibv_shared *sh = priv->sh;
2072         uint32_t meta, mark, reg_c0;
2073
2074         reg_c0 = ~priv->vport_meta_mask;
2075         switch (priv->config.dv_xmeta_en) {
2076         case MLX5_XMETA_MODE_LEGACY:
2077                 meta = UINT32_MAX;
2078                 mark = MLX5_FLOW_MARK_MASK;
2079                 break;
2080         case MLX5_XMETA_MODE_META16:
2081                 meta = reg_c0 >> rte_bsf32(reg_c0);
2082                 mark = MLX5_FLOW_MARK_MASK;
2083                 break;
2084         case MLX5_XMETA_MODE_META32:
2085                 meta = UINT32_MAX;
2086                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2087                 break;
2088         default:
2089                 meta = 0;
2090                 mark = 0;
2091                 MLX5_ASSERT(false);
2092                 break;
2093         }
2094         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2095                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2096                                  sh->dv_mark_mask, mark);
2097         else
2098                 sh->dv_mark_mask = mark;
2099         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2100                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2101                                  sh->dv_meta_mask, meta);
2102         else
2103                 sh->dv_meta_mask = meta;
2104         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2105                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2106                                  sh->dv_meta_mask, reg_c0);
2107         else
2108                 sh->dv_regc0_mask = reg_c0;
2109         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2110         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2111         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2112         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2113 }
2114
2115 /**
2116  * Allocate page of door-bells and register it using DevX API.
2117  *
2118  * @param [in] dev
2119  *   Pointer to Ethernet device.
2120  *
2121  * @return
2122  *   Pointer to new page on success, NULL otherwise.
2123  */
2124 static struct mlx5_devx_dbr_page *
2125 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2126 {
2127         struct mlx5_priv *priv = dev->data->dev_private;
2128         struct mlx5_devx_dbr_page *page;
2129
2130         /* Allocate space for door-bell page and management data. */
2131         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2132                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2133         if (!page) {
2134                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2135                         dev->data->port_id);
2136                 return NULL;
2137         }
2138         /* Register allocated memory. */
2139         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2140                                               MLX5_DBR_PAGE_SIZE, 0);
2141         if (!page->umem) {
2142                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2143                         dev->data->port_id);
2144                 rte_free(page);
2145                 return NULL;
2146         }
2147         return page;
2148 }
2149
2150 /**
2151  * Find the next available door-bell, allocate new page if needed.
2152  *
2153  * @param [in] dev
2154  *   Pointer to Ethernet device.
2155  * @param [out] dbr_page
2156  *   Door-bell page containing the page data.
2157  *
2158  * @return
2159  *   Door-bell address offset on success, a negative error value otherwise.
2160  */
2161 int64_t
2162 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2163 {
2164         struct mlx5_priv *priv = dev->data->dev_private;
2165         struct mlx5_devx_dbr_page *page = NULL;
2166         uint32_t i, j;
2167
2168         LIST_FOREACH(page, &priv->dbrpgs, next)
2169                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2170                         break;
2171         if (!page) { /* No page with free door-bell exists. */
2172                 page = mlx5_alloc_dbr_page(dev);
2173                 if (!page) /* Failed to allocate new page. */
2174                         return (-1);
2175                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2176         }
2177         /* Loop to find bitmap part with clear bit. */
2178         for (i = 0;
2179              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2180              i++)
2181                 ; /* Empty. */
2182         /* Find the first clear bit. */
2183         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
2184         j = rte_bsf64(~page->dbr_bitmap[i]);
2185         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
2186         page->dbr_count++;
2187         *dbr_page = page;
2188         return (((i * 64) + j) * sizeof(uint64_t));
2189 }
2190
2191 /**
2192  * Release a door-bell record.
2193  *
2194  * @param [in] dev
2195  *   Pointer to Ethernet device.
2196  * @param [in] umem_id
2197  *   UMEM ID of page containing the door-bell record to release.
2198  * @param [in] offset
2199  *   Offset of door-bell record in page.
2200  *
2201  * @return
2202  *   0 on success, a negative error value otherwise.
2203  */
2204 int32_t
2205 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2206 {
2207         struct mlx5_priv *priv = dev->data->dev_private;
2208         struct mlx5_devx_dbr_page *page = NULL;
2209         int ret = 0;
2210
2211         LIST_FOREACH(page, &priv->dbrpgs, next)
2212                 /* Find the page this address belongs to. */
2213                 if (page->umem->umem_id == umem_id)
2214                         break;
2215         if (!page)
2216                 return -EINVAL;
2217         page->dbr_count--;
2218         if (!page->dbr_count) {
2219                 /* Page not used, free it and remove from list. */
2220                 LIST_REMOVE(page, next);
2221                 if (page->umem)
2222                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2223                 rte_free(page);
2224         } else {
2225                 /* Mark in bitmap that this door-bell is not in use. */
2226                 offset /= MLX5_DBR_SIZE;
2227                 int i = offset / 64;
2228                 int j = offset % 64;
2229
2230                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
2231         }
2232         return ret;
2233 }
2234
2235 int
2236 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2237 {
2238         static const char *const dynf_names[] = {
2239                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2240                 RTE_MBUF_DYNFLAG_METADATA_NAME
2241         };
2242         unsigned int i;
2243
2244         if (n < RTE_DIM(dynf_names))
2245                 return -ENOMEM;
2246         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2247                 if (names[i] == NULL)
2248                         return -EINVAL;
2249                 strcpy(names[i], dynf_names[i]);
2250         }
2251         return RTE_DIM(dynf_names);
2252 }
2253
2254 /**
2255  * Check sibling device configurations.
2256  *
2257  * Sibling devices sharing the Infiniband device context
2258  * should have compatible configurations. This regards
2259  * representors and bonding slaves.
2260  *
2261  * @param priv
2262  *   Private device descriptor.
2263  * @param config
2264  *   Configuration of the device is going to be created.
2265  *
2266  * @return
2267  *   0 on success, EINVAL otherwise
2268  */
2269 static int
2270 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2271                               struct mlx5_dev_config *config)
2272 {
2273         struct mlx5_ibv_shared *sh = priv->sh;
2274         struct mlx5_dev_config *sh_conf = NULL;
2275         uint16_t port_id;
2276
2277         MLX5_ASSERT(sh);
2278         /* Nothing to compare for the single/first device. */
2279         if (sh->refcnt == 1)
2280                 return 0;
2281         /* Find the device with shared context. */
2282         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2283                 struct mlx5_priv *opriv =
2284                         rte_eth_devices[port_id].data->dev_private;
2285
2286                 if (opriv && opriv != priv && opriv->sh == sh) {
2287                         sh_conf = &opriv->config;
2288                         break;
2289                 }
2290         }
2291         if (!sh_conf)
2292                 return 0;
2293         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2294                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2295                              " for shared %s context", sh->ibdev_name);
2296                 rte_errno = EINVAL;
2297                 return rte_errno;
2298         }
2299         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2300                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2301                              " for shared %s context", sh->ibdev_name);
2302                 rte_errno = EINVAL;
2303                 return rte_errno;
2304         }
2305         return 0;
2306 }
2307 /**
2308  * Spawn an Ethernet device from Verbs information.
2309  *
2310  * @param dpdk_dev
2311  *   Backing DPDK device.
2312  * @param spawn
2313  *   Verbs device parameters (name, port, switch_info) to spawn.
2314  * @param config
2315  *   Device configuration parameters.
2316  *
2317  * @return
2318  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2319  *   is set. The following errors are defined:
2320  *
2321  *   EBUSY: device is not supposed to be spawned.
2322  *   EEXIST: device is already spawned
2323  */
2324 static struct rte_eth_dev *
2325 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2326                struct mlx5_dev_spawn_data *spawn,
2327                struct mlx5_dev_config config)
2328 {
2329         const struct mlx5_switch_info *switch_info = &spawn->info;
2330         struct mlx5_ibv_shared *sh = NULL;
2331         struct ibv_port_attr port_attr;
2332         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2333         struct rte_eth_dev *eth_dev = NULL;
2334         struct mlx5_priv *priv = NULL;
2335         int err = 0;
2336         unsigned int hw_padding = 0;
2337         unsigned int mps;
2338         unsigned int cqe_comp;
2339         unsigned int cqe_pad = 0;
2340         unsigned int tunnel_en = 0;
2341         unsigned int mpls_en = 0;
2342         unsigned int swp = 0;
2343         unsigned int mprq = 0;
2344         unsigned int mprq_min_stride_size_n = 0;
2345         unsigned int mprq_max_stride_size_n = 0;
2346         unsigned int mprq_min_stride_num_n = 0;
2347         unsigned int mprq_max_stride_num_n = 0;
2348         struct rte_ether_addr mac;
2349         char name[RTE_ETH_NAME_MAX_LEN];
2350         int own_domain_id = 0;
2351         uint16_t port_id;
2352         unsigned int i;
2353 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2354         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2355 #endif
2356
2357         /* Determine if this port representor is supposed to be spawned. */
2358         if (switch_info->representor && dpdk_dev->devargs) {
2359                 struct rte_eth_devargs eth_da;
2360
2361                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2362                 if (err) {
2363                         rte_errno = -err;
2364                         DRV_LOG(ERR, "failed to process device arguments: %s",
2365                                 strerror(rte_errno));
2366                         return NULL;
2367                 }
2368                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2369                         if (eth_da.representor_ports[i] ==
2370                             (uint16_t)switch_info->port_name)
2371                                 break;
2372                 if (i == eth_da.nb_representor_ports) {
2373                         rte_errno = EBUSY;
2374                         return NULL;
2375                 }
2376         }
2377         /* Build device name. */
2378         if (spawn->pf_bond <  0) {
2379                 /* Single device. */
2380                 if (!switch_info->representor)
2381                         strlcpy(name, dpdk_dev->name, sizeof(name));
2382                 else
2383                         snprintf(name, sizeof(name), "%s_representor_%u",
2384                                  dpdk_dev->name, switch_info->port_name);
2385         } else {
2386                 /* Bonding device. */
2387                 if (!switch_info->representor)
2388                         snprintf(name, sizeof(name), "%s_%s",
2389                                  dpdk_dev->name, spawn->ibv_dev->name);
2390                 else
2391                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2392                                  dpdk_dev->name, spawn->ibv_dev->name,
2393                                  switch_info->port_name);
2394         }
2395         /* check if the device is already spawned */
2396         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2397                 rte_errno = EEXIST;
2398                 return NULL;
2399         }
2400         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2401         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2402                 struct mlx5_mp_id mp_id;
2403
2404                 eth_dev = rte_eth_dev_attach_secondary(name);
2405                 if (eth_dev == NULL) {
2406                         DRV_LOG(ERR, "can not attach rte ethdev");
2407                         rte_errno = ENOMEM;
2408                         return NULL;
2409                 }
2410                 eth_dev->device = dpdk_dev;
2411                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2412                 err = mlx5_proc_priv_init(eth_dev);
2413                 if (err)
2414                         return NULL;
2415                 mp_id.port_id = eth_dev->data->port_id;
2416                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2417                 /* Receive command fd from primary process */
2418                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2419                 if (err < 0)
2420                         goto err_secondary;
2421                 /* Remap UAR for Tx queues. */
2422                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2423                 if (err)
2424                         goto err_secondary;
2425                 /*
2426                  * Ethdev pointer is still required as input since
2427                  * the primary device is not accessible from the
2428                  * secondary process.
2429                  */
2430                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2431                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2432                 return eth_dev;
2433 err_secondary:
2434                 mlx5_dev_close(eth_dev);
2435                 return NULL;
2436         }
2437         /*
2438          * Some parameters ("tx_db_nc" in particularly) are needed in
2439          * advance to create dv/verbs device context. We proceed the
2440          * devargs here to get ones, and later proceed devargs again
2441          * to override some hardware settings.
2442          */
2443         err = mlx5_args(&config, dpdk_dev->devargs);
2444         if (err) {
2445                 err = rte_errno;
2446                 DRV_LOG(ERR, "failed to process device arguments: %s",
2447                         strerror(rte_errno));
2448                 goto error;
2449         }
2450         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2451         if (!sh)
2452                 return NULL;
2453         config.devx = sh->devx;
2454 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2455         config.dest_tir = 1;
2456 #endif
2457 #ifdef HAVE_IBV_MLX5_MOD_SWP
2458         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2459 #endif
2460         /*
2461          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2462          * as all ConnectX-5 devices.
2463          */
2464 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2465         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2466 #endif
2467 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2468         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2469 #endif
2470         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2471         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2472                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2473                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2474                         mps = MLX5_MPW_ENHANCED;
2475                 } else {
2476                         DRV_LOG(DEBUG, "MPW is supported");
2477                         mps = MLX5_MPW;
2478                 }
2479         } else {
2480                 DRV_LOG(DEBUG, "MPW isn't supported");
2481                 mps = MLX5_MPW_DISABLED;
2482         }
2483 #ifdef HAVE_IBV_MLX5_MOD_SWP
2484         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2485                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2486         DRV_LOG(DEBUG, "SWP support: %u", swp);
2487 #endif
2488         config.swp = !!swp;
2489 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2490         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2491                 struct mlx5dv_striding_rq_caps mprq_caps =
2492                         dv_attr.striding_rq_caps;
2493
2494                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2495                         mprq_caps.min_single_stride_log_num_of_bytes);
2496                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2497                         mprq_caps.max_single_stride_log_num_of_bytes);
2498                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2499                         mprq_caps.min_single_wqe_log_num_of_strides);
2500                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2501                         mprq_caps.max_single_wqe_log_num_of_strides);
2502                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2503                         mprq_caps.supported_qpts);
2504                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2505                 mprq = 1;
2506                 mprq_min_stride_size_n =
2507                         mprq_caps.min_single_stride_log_num_of_bytes;
2508                 mprq_max_stride_size_n =
2509                         mprq_caps.max_single_stride_log_num_of_bytes;
2510                 mprq_min_stride_num_n =
2511                         mprq_caps.min_single_wqe_log_num_of_strides;
2512                 mprq_max_stride_num_n =
2513                         mprq_caps.max_single_wqe_log_num_of_strides;
2514         }
2515 #endif
2516         if (RTE_CACHE_LINE_SIZE == 128 &&
2517             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2518                 cqe_comp = 0;
2519         else
2520                 cqe_comp = 1;
2521         config.cqe_comp = cqe_comp;
2522 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2523         /* Whether device supports 128B Rx CQE padding. */
2524         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2525                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2526 #endif
2527 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2528         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2529                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2530                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2531                              (dv_attr.tunnel_offloads_caps &
2532                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2533                              (dv_attr.tunnel_offloads_caps &
2534                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2535         }
2536         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2537                 tunnel_en ? "" : "not ");
2538 #else
2539         DRV_LOG(WARNING,
2540                 "tunnel offloading disabled due to old OFED/rdma-core version");
2541 #endif
2542         config.tunnel_en = tunnel_en;
2543 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2544         mpls_en = ((dv_attr.tunnel_offloads_caps &
2545                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2546                    (dv_attr.tunnel_offloads_caps &
2547                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2548         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2549                 mpls_en ? "" : "not ");
2550 #else
2551         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2552                 " old OFED/rdma-core version or firmware configuration");
2553 #endif
2554         config.mpls_en = mpls_en;
2555         /* Check port status. */
2556         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2557         if (err) {
2558                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2559                 goto error;
2560         }
2561         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2562                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2563                 err = EINVAL;
2564                 goto error;
2565         }
2566         if (port_attr.state != IBV_PORT_ACTIVE)
2567                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2568                         mlx5_glue->port_state_str(port_attr.state),
2569                         port_attr.state);
2570         /* Allocate private eth device data. */
2571         priv = rte_zmalloc("ethdev private structure",
2572                            sizeof(*priv),
2573                            RTE_CACHE_LINE_SIZE);
2574         if (priv == NULL) {
2575                 DRV_LOG(ERR, "priv allocation failure");
2576                 err = ENOMEM;
2577                 goto error;
2578         }
2579         priv->sh = sh;
2580         priv->ibv_port = spawn->ibv_port;
2581         priv->pci_dev = spawn->pci_dev;
2582         priv->mtu = RTE_ETHER_MTU;
2583         priv->mp_id.port_id = port_id;
2584         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2585 #ifndef RTE_ARCH_64
2586         /* Initialize UAR access locks for 32bit implementations. */
2587         rte_spinlock_init(&priv->uar_lock_cq);
2588         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2589                 rte_spinlock_init(&priv->uar_lock[i]);
2590 #endif
2591         /* Some internal functions rely on Netlink sockets, open them now. */
2592         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2593         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2594         priv->representor = !!switch_info->representor;
2595         priv->master = !!switch_info->master;
2596         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2597         priv->vport_meta_tag = 0;
2598         priv->vport_meta_mask = 0;
2599         priv->pf_bond = spawn->pf_bond;
2600 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2601         /*
2602          * The DevX port query API is implemented. E-Switch may use
2603          * either vport or reg_c[0] metadata register to match on
2604          * vport index. The engaged part of metadata register is
2605          * defined by mask.
2606          */
2607         if (switch_info->representor || switch_info->master) {
2608                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2609                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2610                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2611                                                  &devx_port);
2612                 if (err) {
2613                         DRV_LOG(WARNING,
2614                                 "can't query devx port %d on device %s",
2615                                 spawn->ibv_port, spawn->ibv_dev->name);
2616                         devx_port.comp_mask = 0;
2617                 }
2618         }
2619         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2620                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2621                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2622                 if (!priv->vport_meta_mask) {
2623                         DRV_LOG(ERR, "vport zero mask for port %d"
2624                                      " on bonding device %s",
2625                                      spawn->ibv_port, spawn->ibv_dev->name);
2626                         err = ENOTSUP;
2627                         goto error;
2628                 }
2629                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2630                         DRV_LOG(ERR, "invalid vport tag for port %d"
2631                                      " on bonding device %s",
2632                                      spawn->ibv_port, spawn->ibv_dev->name);
2633                         err = ENOTSUP;
2634                         goto error;
2635                 }
2636         }
2637         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2638                 priv->vport_id = devx_port.vport_num;
2639         } else if (spawn->pf_bond >= 0) {
2640                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2641                              " on bonding device %s",
2642                              spawn->ibv_port, spawn->ibv_dev->name);
2643                 err = ENOTSUP;
2644                 goto error;
2645         } else {
2646                 /* Suppose vport index in compatible way. */
2647                 priv->vport_id = switch_info->representor ?
2648                                  switch_info->port_name + 1 : -1;
2649         }
2650 #else
2651         /*
2652          * Kernel/rdma_core support single E-Switch per PF configurations
2653          * only and vport_id field contains the vport index for
2654          * associated VF, which is deduced from representor port name.
2655          * For example, let's have the IB device port 10, it has
2656          * attached network device eth0, which has port name attribute
2657          * pf0vf2, we can deduce the VF number as 2, and set vport index
2658          * as 3 (2+1). This assigning schema should be changed if the
2659          * multiple E-Switch instances per PF configurations or/and PCI
2660          * subfunctions are added.
2661          */
2662         priv->vport_id = switch_info->representor ?
2663                          switch_info->port_name + 1 : -1;
2664 #endif
2665         /* representor_id field keeps the unmodified VF index. */
2666         priv->representor_id = switch_info->representor ?
2667                                switch_info->port_name : -1;
2668         /*
2669          * Look for sibling devices in order to reuse their switch domain
2670          * if any, otherwise allocate one.
2671          */
2672         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2673                 const struct mlx5_priv *opriv =
2674                         rte_eth_devices[port_id].data->dev_private;
2675
2676                 if (!opriv ||
2677                     opriv->sh != priv->sh ||
2678                         opriv->domain_id ==
2679                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2680                         continue;
2681                 priv->domain_id = opriv->domain_id;
2682                 break;
2683         }
2684         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2685                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2686                 if (err) {
2687                         err = rte_errno;
2688                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2689                                 strerror(rte_errno));
2690                         goto error;
2691                 }
2692                 own_domain_id = 1;
2693         }
2694         /* Override some values set by hardware configuration. */
2695         mlx5_args(&config, dpdk_dev->devargs);
2696         err = mlx5_dev_check_sibling_config(priv, &config);
2697         if (err)
2698                 goto error;
2699         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2700                             IBV_DEVICE_RAW_IP_CSUM);
2701         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2702                 (config.hw_csum ? "" : "not "));
2703 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2704         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2705         DRV_LOG(DEBUG, "counters are not supported");
2706 #endif
2707 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2708         if (config.dv_flow_en) {
2709                 DRV_LOG(WARNING, "DV flow is not supported");
2710                 config.dv_flow_en = 0;
2711         }
2712 #endif
2713         config.ind_table_max_size =
2714                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2715         /*
2716          * Remove this check once DPDK supports larger/variable
2717          * indirection tables.
2718          */
2719         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2720                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2721         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2722                 config.ind_table_max_size);
2723         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2724                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2725         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2726                 (config.hw_vlan_strip ? "" : "not "));
2727         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2728                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2729         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2730                 (config.hw_fcs_strip ? "" : "not "));
2731 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2732         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2733 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2734         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2735                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2736 #endif
2737         if (config.hw_padding && !hw_padding) {
2738                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2739                 config.hw_padding = 0;
2740         } else if (config.hw_padding) {
2741                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2742         }
2743         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2744                       (sh->device_attr.tso_caps.supported_qpts &
2745                        (1 << IBV_QPT_RAW_PACKET)));
2746         if (config.tso)
2747                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2748         /*
2749          * MPW is disabled by default, while the Enhanced MPW is enabled
2750          * by default.
2751          */
2752         if (config.mps == MLX5_ARG_UNSET)
2753                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2754                                                           MLX5_MPW_DISABLED;
2755         else
2756                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2757         DRV_LOG(INFO, "%sMPS is %s",
2758                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2759                 config.mps == MLX5_MPW ? "legacy " : "",
2760                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2761         if (config.cqe_comp && !cqe_comp) {
2762                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2763                 config.cqe_comp = 0;
2764         }
2765         if (config.cqe_pad && !cqe_pad) {
2766                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2767                 config.cqe_pad = 0;
2768         } else if (config.cqe_pad) {
2769                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2770         }
2771         if (config.devx) {
2772                 priv->counter_fallback = 0;
2773                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2774                 if (err) {
2775                         err = -err;
2776                         goto error;
2777                 }
2778                 if (!config.hca_attr.flow_counters_dump)
2779                         priv->counter_fallback = 1;
2780 #ifndef HAVE_IBV_DEVX_ASYNC
2781                 priv->counter_fallback = 1;
2782 #endif
2783                 if (priv->counter_fallback)
2784                         DRV_LOG(INFO, "Use fall-back DV counter management");
2785                 /* Check for LRO support. */
2786                 if (config.dest_tir && config.hca_attr.lro_cap &&
2787                     config.dv_flow_en) {
2788                         /* TBD check tunnel lro caps. */
2789                         config.lro.supported = config.hca_attr.lro_cap;
2790                         DRV_LOG(DEBUG, "Device supports LRO");
2791                         /*
2792                          * If LRO timeout is not configured by application,
2793                          * use the minimal supported value.
2794                          */
2795                         if (!config.lro.timeout)
2796                                 config.lro.timeout =
2797                                 config.hca_attr.lro_timer_supported_periods[0];
2798                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2799                                 config.lro.timeout);
2800                 }
2801 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2802                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2803                     config.dv_flow_en) {
2804                         uint8_t reg_c_mask =
2805                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2806                         /*
2807                          * Meter needs two REG_C's for color match and pre-sfx
2808                          * flow match. Here get the REG_C for color match.
2809                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2810                          */
2811                         reg_c_mask &= 0xfc;
2812                         if (__builtin_popcount(reg_c_mask) < 1) {
2813                                 priv->mtr_en = 0;
2814                                 DRV_LOG(WARNING, "No available register for"
2815                                         " meter.");
2816                         } else {
2817                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2818                                                       REG_C_0;
2819                                 priv->mtr_en = 1;
2820                                 priv->mtr_reg_share =
2821                                       config.hca_attr.qos.flow_meter_reg_share;
2822                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2823                                         priv->mtr_color_reg);
2824                         }
2825                 }
2826 #endif
2827         }
2828         if (config.mprq.enabled && mprq) {
2829                 if (config.mprq.stride_num_n &&
2830                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2831                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2832                         config.mprq.stride_num_n =
2833                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2834                                                 mprq_min_stride_num_n),
2835                                         mprq_max_stride_num_n);
2836                         DRV_LOG(WARNING,
2837                                 "the number of strides"
2838                                 " for Multi-Packet RQ is out of range,"
2839                                 " setting default value (%u)",
2840                                 1 << config.mprq.stride_num_n);
2841                 }
2842                 if (config.mprq.stride_size_n &&
2843                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2844                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2845                         config.mprq.stride_size_n =
2846                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2847                                                 mprq_min_stride_size_n),
2848                                         mprq_max_stride_size_n);
2849                         DRV_LOG(WARNING,
2850                                 "the size of a stride"
2851                                 " for Multi-Packet RQ is out of range,"
2852                                 " setting default value (%u)",
2853                                 1 << config.mprq.stride_size_n);
2854                 }
2855                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2856                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2857         } else if (config.mprq.enabled && !mprq) {
2858                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2859                 config.mprq.enabled = 0;
2860         }
2861         if (config.max_dump_files_num == 0)
2862                 config.max_dump_files_num = 128;
2863         eth_dev = rte_eth_dev_allocate(name);
2864         if (eth_dev == NULL) {
2865                 DRV_LOG(ERR, "can not allocate rte ethdev");
2866                 err = ENOMEM;
2867                 goto error;
2868         }
2869         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2870         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2871         if (priv->representor) {
2872                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2873                 eth_dev->data->representor_id = priv->representor_id;
2874         }
2875         /*
2876          * Store associated network device interface index. This index
2877          * is permanent throughout the lifetime of device. So, we may store
2878          * the ifindex here and use the cached value further.
2879          */
2880         MLX5_ASSERT(spawn->ifindex);
2881         priv->if_index = spawn->ifindex;
2882         eth_dev->data->dev_private = priv;
2883         priv->dev_data = eth_dev->data;
2884         eth_dev->data->mac_addrs = priv->mac;
2885         eth_dev->device = dpdk_dev;
2886         /* Configure the first MAC address by default. */
2887         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2888                 DRV_LOG(ERR,
2889                         "port %u cannot get MAC address, is mlx5_en"
2890                         " loaded? (errno: %s)",
2891                         eth_dev->data->port_id, strerror(rte_errno));
2892                 err = ENODEV;
2893                 goto error;
2894         }
2895         DRV_LOG(INFO,
2896                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2897                 eth_dev->data->port_id,
2898                 mac.addr_bytes[0], mac.addr_bytes[1],
2899                 mac.addr_bytes[2], mac.addr_bytes[3],
2900                 mac.addr_bytes[4], mac.addr_bytes[5]);
2901 #ifdef RTE_LIBRTE_MLX5_DEBUG
2902         {
2903                 char ifname[IF_NAMESIZE];
2904
2905                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2906                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2907                                 eth_dev->data->port_id, ifname);
2908                 else
2909                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2910                                 eth_dev->data->port_id);
2911         }
2912 #endif
2913         /* Get actual MTU if possible. */
2914         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2915         if (err) {
2916                 err = rte_errno;
2917                 goto error;
2918         }
2919         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2920                 priv->mtu);
2921         /* Initialize burst functions to prevent crashes before link-up. */
2922         eth_dev->rx_pkt_burst = removed_rx_burst;
2923         eth_dev->tx_pkt_burst = removed_tx_burst;
2924         eth_dev->dev_ops = &mlx5_dev_ops;
2925         /* Register MAC address. */
2926         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2927         if (config.vf && config.vf_nl_en)
2928                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2929                                       mlx5_ifindex(eth_dev),
2930                                       eth_dev->data->mac_addrs,
2931                                       MLX5_MAX_MAC_ADDRESSES);
2932         priv->flows = 0;
2933         priv->ctrl_flows = 0;
2934         TAILQ_INIT(&priv->flow_meters);
2935         TAILQ_INIT(&priv->flow_meter_profiles);
2936         /* Hint libmlx5 to use PMD allocator for data plane resources */
2937         struct mlx5dv_ctx_allocators alctr = {
2938                 .alloc = &mlx5_alloc_verbs_buf,
2939                 .free = &mlx5_free_verbs_buf,
2940                 .data = priv,
2941         };
2942         mlx5_glue->dv_set_context_attr(sh->ctx,
2943                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2944                                        (void *)((uintptr_t)&alctr));
2945         /* Bring Ethernet device up. */
2946         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2947                 eth_dev->data->port_id);
2948         mlx5_set_link_up(eth_dev);
2949         /*
2950          * Even though the interrupt handler is not installed yet,
2951          * interrupts will still trigger on the async_fd from
2952          * Verbs context returned by ibv_open_device().
2953          */
2954         mlx5_link_update(eth_dev, 0);
2955 #ifdef HAVE_MLX5DV_DR_ESWITCH
2956         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2957               (switch_info->representor || switch_info->master)))
2958                 config.dv_esw_en = 0;
2959 #else
2960         config.dv_esw_en = 0;
2961 #endif
2962         /* Detect minimal data bytes to inline. */
2963         mlx5_set_min_inline(spawn, &config);
2964         /* Store device configuration on private structure. */
2965         priv->config = config;
2966         /* Create context for virtual machine VLAN workaround. */
2967         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2968         if (config.dv_flow_en) {
2969                 err = mlx5_alloc_shared_dr(priv);
2970                 if (err)
2971                         goto error;
2972                 /*
2973                  * RSS id is shared with meter flow id. Meter flow id can only
2974                  * use the 24 MSB of the register.
2975                  */
2976                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2977                                      MLX5_MTR_COLOR_BITS);
2978                 if (!priv->qrss_id_pool) {
2979                         DRV_LOG(ERR, "can't create flow id pool");
2980                         err = ENOMEM;
2981                         goto error;
2982                 }
2983         }
2984         /* Supported Verbs flow priority number detection. */
2985         err = mlx5_flow_discover_priorities(eth_dev);
2986         if (err < 0) {
2987                 err = -err;
2988                 goto error;
2989         }
2990         priv->config.flow_prio = err;
2991         if (!priv->config.dv_esw_en &&
2992             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2993                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2994                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2995                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2996         }
2997         mlx5_set_metadata_mask(eth_dev);
2998         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2999             !priv->sh->dv_regc0_mask) {
3000                 DRV_LOG(ERR, "metadata mode %u is not supported "
3001                              "(no metadata reg_c[0] is available)",
3002                              priv->config.dv_xmeta_en);
3003                         err = ENOTSUP;
3004                         goto error;
3005         }
3006         /*
3007          * Allocate the buffer for flow creating, just once.
3008          * The allocation must be done before any flow creating.
3009          */
3010         mlx5_flow_alloc_intermediate(eth_dev);
3011         /* Query availibility of metadata reg_c's. */
3012         err = mlx5_flow_discover_mreg_c(eth_dev);
3013         if (err < 0) {
3014                 err = -err;
3015                 goto error;
3016         }
3017         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
3018                 DRV_LOG(DEBUG,
3019                         "port %u extensive metadata register is not supported",
3020                         eth_dev->data->port_id);
3021                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
3022                         DRV_LOG(ERR, "metadata mode %u is not supported "
3023                                      "(no metadata registers available)",
3024                                      priv->config.dv_xmeta_en);
3025                         err = ENOTSUP;
3026                         goto error;
3027                 }
3028         }
3029         if (priv->config.dv_flow_en &&
3030             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3031             mlx5_flow_ext_mreg_supported(eth_dev) &&
3032             priv->sh->dv_regc0_mask) {
3033                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
3034                                                       MLX5_FLOW_MREG_HTABLE_SZ);
3035                 if (!priv->mreg_cp_tbl) {
3036                         err = ENOMEM;
3037                         goto error;
3038                 }
3039         }
3040         return eth_dev;
3041 error:
3042         if (priv) {
3043                 if (priv->mreg_cp_tbl)
3044                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
3045                 if (priv->sh)
3046                         mlx5_free_shared_dr(priv);
3047                 if (priv->nl_socket_route >= 0)
3048                         close(priv->nl_socket_route);
3049                 if (priv->nl_socket_rdma >= 0)
3050                         close(priv->nl_socket_rdma);
3051                 if (priv->vmwa_context)
3052                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
3053                 if (priv->qrss_id_pool)
3054                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
3055                 if (own_domain_id)
3056                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
3057                 rte_free(priv);
3058                 if (eth_dev != NULL)
3059                         eth_dev->data->dev_private = NULL;
3060         }
3061         if (eth_dev != NULL) {
3062                 /* mac_addrs must not be freed alone because part of dev_private */
3063                 eth_dev->data->mac_addrs = NULL;
3064                 rte_eth_dev_release_port(eth_dev);
3065         }
3066         if (sh)
3067                 mlx5_free_shared_ibctx(sh);
3068         MLX5_ASSERT(err > 0);
3069         rte_errno = err;
3070         return NULL;
3071 }
3072
3073 /**
3074  * Comparison callback to sort device data.
3075  *
3076  * This is meant to be used with qsort().
3077  *
3078  * @param a[in]
3079  *   Pointer to pointer to first data object.
3080  * @param b[in]
3081  *   Pointer to pointer to second data object.
3082  *
3083  * @return
3084  *   0 if both objects are equal, less than 0 if the first argument is less
3085  *   than the second, greater than 0 otherwise.
3086  */
3087 static int
3088 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3089 {
3090         const struct mlx5_switch_info *si_a =
3091                 &((const struct mlx5_dev_spawn_data *)a)->info;
3092         const struct mlx5_switch_info *si_b =
3093                 &((const struct mlx5_dev_spawn_data *)b)->info;
3094         int ret;
3095
3096         /* Master device first. */
3097         ret = si_b->master - si_a->master;
3098         if (ret)
3099                 return ret;
3100         /* Then representor devices. */
3101         ret = si_b->representor - si_a->representor;
3102         if (ret)
3103                 return ret;
3104         /* Unidentified devices come last in no specific order. */
3105         if (!si_a->representor)
3106                 return 0;
3107         /* Order representors by name. */
3108         return si_a->port_name - si_b->port_name;
3109 }
3110
3111 /**
3112  * Match PCI information for possible slaves of bonding device.
3113  *
3114  * @param[in] ibv_dev
3115  *   Pointer to Infiniband device structure.
3116  * @param[in] pci_dev
3117  *   Pointer to PCI device structure to match PCI address.
3118  * @param[in] nl_rdma
3119  *   Netlink RDMA group socket handle.
3120  *
3121  * @return
3122  *   negative value if no bonding device found, otherwise
3123  *   positive index of slave PF in bonding.
3124  */
3125 static int
3126 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3127                            const struct rte_pci_device *pci_dev,
3128                            int nl_rdma)
3129 {
3130         char ifname[IF_NAMESIZE + 1];
3131         unsigned int ifindex;
3132         unsigned int np, i;
3133         FILE *file = NULL;
3134         int pf = -1;
3135
3136         /*
3137          * Try to get master device name. If something goes
3138          * wrong suppose the lack of kernel support and no
3139          * bonding devices.
3140          */
3141         if (nl_rdma < 0)
3142                 return -1;
3143         if (!strstr(ibv_dev->name, "bond"))
3144                 return -1;
3145         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3146         if (!np)
3147                 return -1;
3148         /*
3149          * The Master device might not be on the predefined
3150          * port (not on port index 1, it is not garanted),
3151          * we have to scan all Infiniband device port and
3152          * find master.
3153          */
3154         for (i = 1; i <= np; ++i) {
3155                 /* Check whether Infiniband port is populated. */
3156                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3157                 if (!ifindex)
3158                         continue;
3159                 if (!if_indextoname(ifindex, ifname))
3160                         continue;
3161                 /* Try to read bonding slave names from sysfs. */
3162                 MKSTR(slaves,
3163                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3164                 file = fopen(slaves, "r");
3165                 if (file)
3166                         break;
3167         }
3168         if (!file)
3169                 return -1;
3170         /* Use safe format to check maximal buffer length. */
3171         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3172         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3173                 char tmp_str[IF_NAMESIZE + 32];
3174                 struct rte_pci_addr pci_addr;
3175                 struct mlx5_switch_info info;
3176
3177                 /* Process slave interface names in the loop. */
3178                 snprintf(tmp_str, sizeof(tmp_str),
3179                          "/sys/class/net/%s", ifname);
3180                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3181                         DRV_LOG(WARNING, "can not get PCI address"
3182                                          " for netdev \"%s\"", ifname);
3183                         continue;
3184                 }
3185                 if (pci_dev->addr.domain != pci_addr.domain ||
3186                     pci_dev->addr.bus != pci_addr.bus ||
3187                     pci_dev->addr.devid != pci_addr.devid ||
3188                     pci_dev->addr.function != pci_addr.function)
3189                         continue;
3190                 /* Slave interface PCI address match found. */
3191                 fclose(file);
3192                 snprintf(tmp_str, sizeof(tmp_str),
3193                          "/sys/class/net/%s/phys_port_name", ifname);
3194                 file = fopen(tmp_str, "rb");
3195                 if (!file)
3196                         break;
3197                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3198                 if (fscanf(file, "%32s", tmp_str) == 1)
3199                         mlx5_translate_port_name(tmp_str, &info);
3200                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3201                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3202                         pf = info.port_name;
3203                 break;
3204         }
3205         if (file)
3206                 fclose(file);
3207         return pf;
3208 }
3209
3210 /**
3211  * DPDK callback to register a PCI device.
3212  *
3213  * This function spawns Ethernet devices out of a given PCI device.
3214  *
3215  * @param[in] pci_drv
3216  *   PCI driver structure (mlx5_driver).
3217  * @param[in] pci_dev
3218  *   PCI device information.
3219  *
3220  * @return
3221  *   0 on success, a negative errno value otherwise and rte_errno is set.
3222  */
3223 static int
3224 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3225                struct rte_pci_device *pci_dev)
3226 {
3227         struct ibv_device **ibv_list;
3228         /*
3229          * Number of found IB Devices matching with requested PCI BDF.
3230          * nd != 1 means there are multiple IB devices over the same
3231          * PCI device and we have representors and master.
3232          */
3233         unsigned int nd = 0;
3234         /*
3235          * Number of found IB device Ports. nd = 1 and np = 1..n means
3236          * we have the single multiport IB device, and there may be
3237          * representors attached to some of found ports.
3238          */
3239         unsigned int np = 0;
3240         /*
3241          * Number of DPDK ethernet devices to Spawn - either over
3242          * multiple IB devices or multiple ports of single IB device.
3243          * Actually this is the number of iterations to spawn.
3244          */
3245         unsigned int ns = 0;
3246         /*
3247          * Bonding device
3248          *   < 0 - no bonding device (single one)
3249          *  >= 0 - bonding device (value is slave PF index)
3250          */
3251         int bd = -1;
3252         struct mlx5_dev_spawn_data *list = NULL;
3253         struct mlx5_dev_config dev_config;
3254         int ret;
3255
3256         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3257                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3258                         " driver.");
3259                 return 1;
3260         }
3261         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3262                 mlx5_pmd_socket_init();
3263         ret = mlx5_init_once();
3264         if (ret) {
3265                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3266                         strerror(rte_errno));
3267                 return -rte_errno;
3268         }
3269         MLX5_ASSERT(pci_drv == &mlx5_driver);
3270         errno = 0;
3271         ibv_list = mlx5_glue->get_device_list(&ret);
3272         if (!ibv_list) {
3273                 rte_errno = errno ? errno : ENOSYS;
3274                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3275                 return -rte_errno;
3276         }
3277         /*
3278          * First scan the list of all Infiniband devices to find
3279          * matching ones, gathering into the list.
3280          */
3281         struct ibv_device *ibv_match[ret + 1];
3282         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3283         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3284         unsigned int i;
3285
3286         while (ret-- > 0) {
3287                 struct rte_pci_addr pci_addr;
3288
3289                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3290                 bd = mlx5_device_bond_pci_match
3291                                 (ibv_list[ret], pci_dev, nl_rdma);
3292                 if (bd >= 0) {
3293                         /*
3294                          * Bonding device detected. Only one match is allowed,
3295                          * the bonding is supported over multi-port IB device,
3296                          * there should be no matches on representor PCI
3297                          * functions or non VF LAG bonding devices with
3298                          * specified address.
3299                          */
3300                         if (nd) {
3301                                 DRV_LOG(ERR,
3302                                         "multiple PCI match on bonding device"
3303                                         "\"%s\" found", ibv_list[ret]->name);
3304                                 rte_errno = ENOENT;
3305                                 ret = -rte_errno;
3306                                 goto exit;
3307                         }
3308                         DRV_LOG(INFO, "PCI information matches for"
3309                                       " slave %d bonding device \"%s\"",
3310                                       bd, ibv_list[ret]->name);
3311                         ibv_match[nd++] = ibv_list[ret];
3312                         break;
3313                 }
3314                 if (mlx5_dev_to_pci_addr
3315                         (ibv_list[ret]->ibdev_path, &pci_addr))
3316                         continue;
3317                 if (pci_dev->addr.domain != pci_addr.domain ||
3318                     pci_dev->addr.bus != pci_addr.bus ||
3319                     pci_dev->addr.devid != pci_addr.devid ||
3320                     pci_dev->addr.function != pci_addr.function)
3321                         continue;
3322                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3323                         ibv_list[ret]->name);
3324                 ibv_match[nd++] = ibv_list[ret];
3325         }
3326         ibv_match[nd] = NULL;
3327         if (!nd) {
3328                 /* No device matches, just complain and bail out. */
3329                 DRV_LOG(WARNING,
3330                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3331                         " are kernel drivers loaded?",
3332                         pci_dev->addr.domain, pci_dev->addr.bus,
3333                         pci_dev->addr.devid, pci_dev->addr.function);
3334                 rte_errno = ENOENT;
3335                 ret = -rte_errno;
3336                 goto exit;
3337         }
3338         if (nd == 1) {
3339                 /*
3340                  * Found single matching device may have multiple ports.
3341                  * Each port may be representor, we have to check the port
3342                  * number and check the representors existence.
3343                  */
3344                 if (nl_rdma >= 0)
3345                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3346                 if (!np)
3347                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3348                                          " ports number", ibv_match[0]->name);
3349                 if (bd >= 0 && !np) {
3350                         DRV_LOG(ERR, "can not get ports"
3351                                      " for bonding device");
3352                         rte_errno = ENOENT;
3353                         ret = -rte_errno;
3354                         goto exit;
3355                 }
3356         }
3357 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3358         if (bd >= 0) {
3359                 /*
3360                  * This may happen if there is VF LAG kernel support and
3361                  * application is compiled with older rdma_core library.
3362                  */
3363                 DRV_LOG(ERR,
3364                         "No kernel/verbs support for VF LAG bonding found.");
3365                 rte_errno = ENOTSUP;
3366                 ret = -rte_errno;
3367                 goto exit;
3368         }
3369 #endif
3370         /*
3371          * Now we can determine the maximal
3372          * amount of devices to be spawned.
3373          */
3374         list = rte_zmalloc("device spawn data",
3375                          sizeof(struct mlx5_dev_spawn_data) *
3376                          (np ? np : nd),
3377                          RTE_CACHE_LINE_SIZE);
3378         if (!list) {
3379                 DRV_LOG(ERR, "spawn data array allocation failure");
3380                 rte_errno = ENOMEM;
3381                 ret = -rte_errno;
3382                 goto exit;
3383         }
3384         if (bd >= 0 || np > 1) {
3385                 /*
3386                  * Single IB device with multiple ports found,
3387                  * it may be E-Switch master device and representors.
3388                  * We have to perform identification through the ports.
3389                  */
3390                 MLX5_ASSERT(nl_rdma >= 0);
3391                 MLX5_ASSERT(ns == 0);
3392                 MLX5_ASSERT(nd == 1);
3393                 MLX5_ASSERT(np);
3394                 for (i = 1; i <= np; ++i) {
3395                         list[ns].max_port = np;
3396                         list[ns].ibv_port = i;
3397                         list[ns].ibv_dev = ibv_match[0];
3398                         list[ns].eth_dev = NULL;
3399                         list[ns].pci_dev = pci_dev;
3400                         list[ns].pf_bond = bd;
3401                         list[ns].ifindex = mlx5_nl_ifindex
3402                                         (nl_rdma, list[ns].ibv_dev->name, i);
3403                         if (!list[ns].ifindex) {
3404                                 /*
3405                                  * No network interface index found for the
3406                                  * specified port, it means there is no
3407                                  * representor on this port. It's OK,
3408                                  * there can be disabled ports, for example
3409                                  * if sriov_numvfs < sriov_totalvfs.
3410                                  */
3411                                 continue;
3412                         }
3413                         ret = -1;
3414                         if (nl_route >= 0)
3415                                 ret = mlx5_nl_switch_info
3416                                                (nl_route,
3417                                                 list[ns].ifindex,
3418                                                 &list[ns].info);
3419                         if (ret || (!list[ns].info.representor &&
3420                                     !list[ns].info.master)) {
3421                                 /*
3422                                  * We failed to recognize representors with
3423                                  * Netlink, let's try to perform the task
3424                                  * with sysfs.
3425                                  */
3426                                 ret =  mlx5_sysfs_switch_info
3427                                                 (list[ns].ifindex,
3428                                                  &list[ns].info);
3429                         }
3430                         if (!ret && bd >= 0) {
3431                                 switch (list[ns].info.name_type) {
3432                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3433                                         if (list[ns].info.port_name == bd)
3434                                                 ns++;
3435                                         break;
3436                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3437                                         if (list[ns].info.pf_num == bd)
3438                                                 ns++;
3439                                         break;
3440                                 default:
3441                                         break;
3442                                 }
3443                                 continue;
3444                         }
3445                         if (!ret && (list[ns].info.representor ^
3446                                      list[ns].info.master))
3447                                 ns++;
3448                 }
3449                 if (!ns) {
3450                         DRV_LOG(ERR,
3451                                 "unable to recognize master/representors"
3452                                 " on the IB device with multiple ports");
3453                         rte_errno = ENOENT;
3454                         ret = -rte_errno;
3455                         goto exit;
3456                 }
3457         } else {
3458                 /*
3459                  * The existence of several matching entries (nd > 1) means
3460                  * port representors have been instantiated. No existing Verbs
3461                  * call nor sysfs entries can tell them apart, this can only
3462                  * be done through Netlink calls assuming kernel drivers are
3463                  * recent enough to support them.
3464                  *
3465                  * In the event of identification failure through Netlink,
3466                  * try again through sysfs, then:
3467                  *
3468                  * 1. A single IB device matches (nd == 1) with single
3469                  *    port (np=0/1) and is not a representor, assume
3470                  *    no switch support.
3471                  *
3472                  * 2. Otherwise no safe assumptions can be made;
3473                  *    complain louder and bail out.
3474                  */
3475                 np = 1;
3476                 for (i = 0; i != nd; ++i) {
3477                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3478                         list[ns].max_port = 1;
3479                         list[ns].ibv_port = 1;
3480                         list[ns].ibv_dev = ibv_match[i];
3481                         list[ns].eth_dev = NULL;
3482                         list[ns].pci_dev = pci_dev;
3483                         list[ns].pf_bond = -1;
3484                         list[ns].ifindex = 0;
3485                         if (nl_rdma >= 0)
3486                                 list[ns].ifindex = mlx5_nl_ifindex
3487                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3488                         if (!list[ns].ifindex) {
3489                                 char ifname[IF_NAMESIZE];
3490
3491                                 /*
3492                                  * Netlink failed, it may happen with old
3493                                  * ib_core kernel driver (before 4.16).
3494                                  * We can assume there is old driver because
3495                                  * here we are processing single ports IB
3496                                  * devices. Let's try sysfs to retrieve
3497                                  * the ifindex. The method works for
3498                                  * master device only.
3499                                  */
3500                                 if (nd > 1) {
3501                                         /*
3502                                          * Multiple devices found, assume
3503                                          * representors, can not distinguish
3504                                          * master/representor and retrieve
3505                                          * ifindex via sysfs.
3506                                          */
3507                                         continue;
3508                                 }
3509                                 ret = mlx5_get_master_ifname
3510                                         (ibv_match[i]->ibdev_path, &ifname);
3511                                 if (!ret)
3512                                         list[ns].ifindex =
3513                                                 if_nametoindex(ifname);
3514                                 if (!list[ns].ifindex) {
3515                                         /*
3516                                          * No network interface index found
3517                                          * for the specified device, it means
3518                                          * there it is neither representor
3519                                          * nor master.
3520                                          */
3521                                         continue;
3522                                 }
3523                         }
3524                         ret = -1;
3525                         if (nl_route >= 0)
3526                                 ret = mlx5_nl_switch_info
3527                                                (nl_route,
3528                                                 list[ns].ifindex,
3529                                                 &list[ns].info);
3530                         if (ret || (!list[ns].info.representor &&
3531                                     !list[ns].info.master)) {
3532                                 /*
3533                                  * We failed to recognize representors with
3534                                  * Netlink, let's try to perform the task
3535                                  * with sysfs.
3536                                  */
3537                                 ret =  mlx5_sysfs_switch_info
3538                                                 (list[ns].ifindex,
3539                                                  &list[ns].info);
3540                         }
3541                         if (!ret && (list[ns].info.representor ^
3542                                      list[ns].info.master)) {
3543                                 ns++;
3544                         } else if ((nd == 1) &&
3545                                    !list[ns].info.representor &&
3546                                    !list[ns].info.master) {
3547                                 /*
3548                                  * Single IB device with
3549                                  * one physical port and
3550                                  * attached network device.
3551                                  * May be SRIOV is not enabled
3552                                  * or there is no representors.
3553                                  */
3554                                 DRV_LOG(INFO, "no E-Switch support detected");
3555                                 ns++;
3556                                 break;
3557                         }
3558                 }
3559                 if (!ns) {
3560                         DRV_LOG(ERR,
3561                                 "unable to recognize master/representors"
3562                                 " on the multiple IB devices");
3563                         rte_errno = ENOENT;
3564                         ret = -rte_errno;
3565                         goto exit;
3566                 }
3567         }
3568         MLX5_ASSERT(ns);
3569         /*
3570          * Sort list to probe devices in natural order for users convenience
3571          * (i.e. master first, then representors from lowest to highest ID).
3572          */
3573         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3574         /* Default configuration. */
3575         dev_config = (struct mlx5_dev_config){
3576                 .hw_padding = 0,
3577                 .mps = MLX5_ARG_UNSET,
3578                 .dbnc = MLX5_ARG_UNSET,
3579                 .rx_vec_en = 1,
3580                 .txq_inline_max = MLX5_ARG_UNSET,
3581                 .txq_inline_min = MLX5_ARG_UNSET,
3582                 .txq_inline_mpw = MLX5_ARG_UNSET,
3583                 .txqs_inline = MLX5_ARG_UNSET,
3584                 .vf_nl_en = 1,
3585                 .mr_ext_memseg_en = 1,
3586                 .mprq = {
3587                         .enabled = 0, /* Disabled by default. */
3588                         .stride_num_n = 0,
3589                         .stride_size_n = 0,
3590                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3591                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3592                 },
3593                 .dv_esw_en = 1,
3594                 .dv_flow_en = 1,
3595                 .log_hp_size = MLX5_ARG_UNSET,
3596         };
3597         /* Device specific configuration. */
3598         switch (pci_dev->id.device_id) {
3599         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3600         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3601         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3602         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3603         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3604         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3605         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3606                 dev_config.vf = 1;
3607                 break;
3608         default:
3609                 break;
3610         }
3611         for (i = 0; i != ns; ++i) {
3612                 uint32_t restore;
3613
3614                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3615                                                  &list[i],
3616                                                  dev_config);
3617                 if (!list[i].eth_dev) {
3618                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3619                                 break;
3620                         /* Device is disabled or already spawned. Ignore it. */
3621                         continue;
3622                 }
3623                 restore = list[i].eth_dev->data->dev_flags;
3624                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3625                 /* Restore non-PCI flags cleared by the above call. */
3626                 list[i].eth_dev->data->dev_flags |= restore;
3627                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3628                 rte_eth_dev_probing_finish(list[i].eth_dev);
3629         }
3630         if (i != ns) {
3631                 DRV_LOG(ERR,
3632                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3633                         " encountering an error: %s",
3634                         pci_dev->addr.domain, pci_dev->addr.bus,
3635                         pci_dev->addr.devid, pci_dev->addr.function,
3636                         strerror(rte_errno));
3637                 ret = -rte_errno;
3638                 /* Roll back. */
3639                 while (i--) {
3640                         if (!list[i].eth_dev)
3641                                 continue;
3642                         mlx5_dev_close(list[i].eth_dev);
3643                         /* mac_addrs must not be freed because in dev_private */
3644                         list[i].eth_dev->data->mac_addrs = NULL;
3645                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3646                 }
3647                 /* Restore original error. */
3648                 rte_errno = -ret;
3649         } else {
3650                 ret = 0;
3651         }
3652 exit:
3653         /*
3654          * Do the routine cleanup:
3655          * - close opened Netlink sockets
3656          * - free allocated spawn data array
3657          * - free the Infiniband device list
3658          */
3659         if (nl_rdma >= 0)
3660                 close(nl_rdma);
3661         if (nl_route >= 0)
3662                 close(nl_route);
3663         if (list)
3664                 rte_free(list);
3665         MLX5_ASSERT(ibv_list);
3666         mlx5_glue->free_device_list(ibv_list);
3667         return ret;
3668 }
3669
3670 /**
3671  * Look for the ethernet device belonging to mlx5 driver.
3672  *
3673  * @param[in] port_id
3674  *   port_id to start looking for device.
3675  * @param[in] pci_dev
3676  *   Pointer to the hint PCI device. When device is being probed
3677  *   the its siblings (master and preceding representors might
3678  *   not have assigned driver yet (because the mlx5_pci_probe()
3679  *   is not completed yet, for this case match on hint PCI
3680  *   device may be used to detect sibling device.
3681  *
3682  * @return
3683  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3684  */
3685 uint16_t
3686 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3687 {
3688         while (port_id < RTE_MAX_ETHPORTS) {
3689                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3690
3691                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3692                     dev->device &&
3693                     (dev->device == &pci_dev->device ||
3694                      (dev->device->driver &&
3695                      dev->device->driver->name &&
3696                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3697                         break;
3698                 port_id++;
3699         }
3700         if (port_id >= RTE_MAX_ETHPORTS)
3701                 return RTE_MAX_ETHPORTS;
3702         return port_id;
3703 }
3704
3705 /**
3706  * DPDK callback to remove a PCI device.
3707  *
3708  * This function removes all Ethernet devices belong to a given PCI device.
3709  *
3710  * @param[in] pci_dev
3711  *   Pointer to the PCI device.
3712  *
3713  * @return
3714  *   0 on success, the function cannot fail.
3715  */
3716 static int
3717 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3718 {
3719         uint16_t port_id;
3720
3721         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
3722                 /*
3723                  * mlx5_dev_close() is not registered to secondary process,
3724                  * call the close function explicitly for secondary process.
3725                  */
3726                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
3727                         mlx5_dev_close(&rte_eth_devices[port_id]);
3728                 else
3729                         rte_eth_dev_close(port_id);
3730         }
3731         return 0;
3732 }
3733
3734 static const struct rte_pci_id mlx5_pci_id_map[] = {
3735         {
3736                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3737                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3738         },
3739         {
3740                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3741                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3742         },
3743         {
3744                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3745                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3746         },
3747         {
3748                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3749                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3750         },
3751         {
3752                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3753                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3754         },
3755         {
3756                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3757                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3758         },
3759         {
3760                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3761                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3762         },
3763         {
3764                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3765                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3766         },
3767         {
3768                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3769                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3770         },
3771         {
3772                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3773                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3774         },
3775         {
3776                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3777                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3778         },
3779         {
3780                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3781                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3782         },
3783         {
3784                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3785                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3786         },
3787         {
3788                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3789                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3790         },
3791         {
3792                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3793                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3794         },
3795         {
3796                 .vendor_id = 0
3797         }
3798 };
3799
3800 static struct rte_pci_driver mlx5_driver = {
3801         .driver = {
3802                 .name = MLX5_DRIVER_NAME
3803         },
3804         .id_table = mlx5_pci_id_map,
3805         .probe = mlx5_pci_probe,
3806         .remove = mlx5_pci_remove,
3807         .dma_map = mlx5_dma_map,
3808         .dma_unmap = mlx5_dma_unmap,
3809         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3810                      RTE_PCI_DRV_PROBE_AGAIN,
3811 };
3812
3813 /**
3814  * Driver initialization routine.
3815  */
3816 RTE_INIT(rte_mlx5_pmd_init)
3817 {
3818         /* Initialize driver log type. */
3819         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3820         if (mlx5_logtype >= 0)
3821                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3822
3823         /* Build the static tables for Verbs conversion. */
3824         mlx5_set_ptype_table();
3825         mlx5_set_cksum_table();
3826         mlx5_set_swp_types_table();
3827         if (mlx5_glue)
3828                 rte_pci_register(&mlx5_driver);
3829 }
3830
3831 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3832 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3833 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");