drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 180 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 181
 182 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 183 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 184         {
 185                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 186                 .trunk_size = 64,
 187                 .grow_trunk = 3,
 188                 .grow_shift = 2,
 189                 .need_lock = 0,
 190                 .release_mem_en = 1,
 191                 .malloc = rte_malloc_socket,
 192                 .free = rte_free,
 193                 .type = "mlx5_encap_decap_ipool",
 194         },
 195         {
 196                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 197                 .trunk_size = 64,
 198                 .grow_trunk = 3,
 199                 .grow_shift = 2,
 200                 .need_lock = 0,
 201                 .release_mem_en = 1,
 202                 .malloc = rte_malloc_socket,
 203                 .free = rte_free,
 204                 .type = "mlx5_push_vlan_ipool",
 205         },
 206         {
 207                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 208                 .trunk_size = 64,
 209                 .grow_trunk = 3,
 210                 .grow_shift = 2,
 211                 .need_lock = 0,
 212                 .release_mem_en = 1,
 213                 .malloc = rte_malloc_socket,
 214                 .free = rte_free,
 215                 .type = "mlx5_tag_ipool",
 216         },
 217         {
 218                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 219                 .trunk_size = 64,
 220                 .grow_trunk = 3,
 221                 .grow_shift = 2,
 222                 .need_lock = 0,
 223                 .release_mem_en = 1,
 224                 .malloc = rte_malloc_socket,
 225                 .free = rte_free,
 226                 .type = "mlx5_port_id_ipool",
 227         },
 228         {
 229                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 230                 .trunk_size = 64,
 231                 .grow_trunk = 3,
 232                 .grow_shift = 2,
 233                 .need_lock = 0,
 234                 .release_mem_en = 1,
 235                 .malloc = rte_malloc_socket,
 236                 .free = rte_free,
 237                 .type = "mlx5_jump_ipool",
 238         },
 239 #endif
 240         {
 241                 .size = sizeof(struct mlx5_flow_meter),
 242                 .trunk_size = 64,
 243                 .grow_trunk = 3,
 244                 .grow_shift = 2,
 245                 .need_lock = 0,
 246                 .release_mem_en = 1,
 247                 .malloc = rte_malloc_socket,
 248                 .free = rte_free,
 249                 .type = "mlx5_meter_ipool",
 250         },
 251         {
 252                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 253                 .trunk_size = 64,
 254                 .grow_trunk = 3,
 255                 .grow_shift = 2,
 256                 .need_lock = 0,
 257                 .release_mem_en = 1,
 258                 .malloc = rte_malloc_socket,
 259                 .free = rte_free,
 260                 .type = "mlx5_mcp_ipool",
 261         },
 262         {
 263                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 264                 .trunk_size = 64,
 265                 .grow_trunk = 3,
 266                 .grow_shift = 2,
 267                 .need_lock = 0,
 268                 .release_mem_en = 1,
 269                 .malloc = rte_malloc_socket,
 270                 .free = rte_free,
 271                 .type = "mlx5_hrxq_ipool",
 272         },
 273         {
 274                 .size = sizeof(struct mlx5_flow_handle),
 275                 .trunk_size = 64,
 276                 .grow_trunk = 3,
 277                 .grow_shift = 2,
 278                 .need_lock = 0,
 279                 .release_mem_en = 1,
 280                 .malloc = rte_malloc_socket,
 281                 .free = rte_free,
 282                 .type = "mlx5_flow_handle_ipool",
 283         },
 284         {
 285                 .size = sizeof(struct rte_flow),
 286                 .trunk_size = 4096,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = rte_malloc_socket,
 290                 .free = rte_free,
 291                 .type = "rte_flow_ipool",
 292         },
 293 };
 294
 295
 296 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 297 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 298
 299 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 300
 301 /**
 302  * Allocate ID pool structure.
 303  *
 304  * @param[in] max_id
 305  *   The maximum id can be allocated from the pool.
 306  *
 307  * @return
 308  *   Pointer to pool object, NULL value otherwise.
 309  */
 310 struct mlx5_flow_id_pool *
 311 mlx5_flow_id_pool_alloc(uint32_t max_id)
 312 {
 313         struct mlx5_flow_id_pool *pool;
 314         void *mem;
 315
 316         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 317                            RTE_CACHE_LINE_SIZE);
 318         if (!pool) {
 319                 DRV_LOG(ERR, "can't allocate id pool");
 320                 rte_errno  = ENOMEM;
 321                 return NULL;
 322         }
 323         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 324                           RTE_CACHE_LINE_SIZE);
 325         if (!mem) {
 326                 DRV_LOG(ERR, "can't allocate mem for id pool");
 327                 rte_errno  = ENOMEM;
 328                 goto error;
 329         }
 330         pool->free_arr = mem;
 331         pool->curr = pool->free_arr;
 332         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 333         pool->base_index = 0;
 334         pool->max_id = max_id;
 335         return pool;
 336 error:
 337         rte_free(pool);
 338         return NULL;
 339 }
 340
 341 /**
 342  * Release ID pool structure.
 343  *
 344  * @param[in] pool
 345  *   Pointer to flow id pool object to free.
 346  */
 347 void
 348 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 349 {
 350         rte_free(pool->free_arr);
 351         rte_free(pool);
 352 }
 353
 354 /**
 355  * Generate ID.
 356  *
 357  * @param[in] pool
 358  *   Pointer to flow id pool.
 359  * @param[out] id
 360  *   The generated ID.
 361  *
 362  * @return
 363  *   0 on success, error value otherwise.
 364  */
 365 uint32_t
 366 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 367 {
 368         if (pool->curr == pool->free_arr) {
 369                 if (pool->base_index == pool->max_id) {
 370                         rte_errno  = ENOMEM;
 371                         DRV_LOG(ERR, "no free id");
 372                         return -rte_errno;
 373                 }
 374                 *id = ++pool->base_index;
 375                 return 0;
 376         }
 377         *id = *(--pool->curr);
 378         return 0;
 379 }
 380
 381 /**
 382  * Release ID.
 383  *
 384  * @param[in] pool
 385  *   Pointer to flow id pool.
 386  * @param[out] id
 387  *   The generated ID.
 388  *
 389  * @return
 390  *   0 on success, error value otherwise.
 391  */
 392 uint32_t
 393 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 394 {
 395         uint32_t size;
 396         uint32_t size2;
 397         void *mem;
 398
 399         if (pool->curr == pool->last) {
 400                 size = pool->curr - pool->free_arr;
 401                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 402                 MLX5_ASSERT(size2 > size);
 403                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 404                 if (!mem) {
 405                         DRV_LOG(ERR, "can't allocate mem for id pool");
 406                         rte_errno  = ENOMEM;
 407                         return -rte_errno;
 408                 }
 409                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 410                 rte_free(pool->free_arr);
 411                 pool->free_arr = mem;
 412                 pool->curr = pool->free_arr + size;
 413                 pool->last = pool->free_arr + size2;
 414         }
 415         *pool->curr = id;
 416         pool->curr++;
 417         return 0;
 418 }
 419
 420 /**
 421  * Initialize the shared aging list information per port.
 422  *
 423  * @param[in] sh
 424  *   Pointer to mlx5_dev_ctx_shared object.
 425  */
 426 static void
 427 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 428 {
 429         uint32_t i;
 430         struct mlx5_age_info *age_info;
 431
 432         for (i = 0; i < sh->max_port; i++) {
 433                 age_info = &sh->port[i].age_info;
 434                 age_info->flags = 0;
 435                 TAILQ_INIT(&age_info->aged_counters);
 436                 rte_spinlock_init(&age_info->aged_sl);
 437                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 438         }
 439 }
 440
 441 /**
 442  * Initialize the counters management structure.
 443  *
 444  * @param[in] sh
 445  *   Pointer to mlx5_dev_ctx_shared object to free
 446  */
 447 static void
 448 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 449 {
 450         int i;
 451
 452         memset(&sh->cmng, 0, sizeof(sh->cmng));
 453         TAILQ_INIT(&sh->cmng.flow_counters);
 454         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 455                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 456                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 457         }
 458 }
 459
 460 /**
 461  * Destroy all the resources allocated for a counter memory management.
 462  *
 463  * @param[in] mng
 464  *   Pointer to the memory management structure.
 465  */
 466 static void
 467 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 468 {
 469         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 470
 471         LIST_REMOVE(mng, next);
 472         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 473         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 474         rte_free(mem);
 475 }
 476
 477 /**
 478  * Close and release all the resources of the counters management.
 479  *
 480  * @param[in] sh
 481  *   Pointer to mlx5_dev_ctx_shared object to free.
 482  */
 483 static void
 484 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 485 {
 486         struct mlx5_counter_stats_mem_mng *mng;
 487         int i;
 488         int j;
 489         int retries = 1024;
 490
 491         rte_errno = 0;
 492         while (--retries) {
 493                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 494                 if (rte_errno != EINPROGRESS)
 495                         break;
 496                 rte_pause();
 497         }
 498         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 499                 struct mlx5_flow_counter_pool *pool;
 500                 uint32_t batch = !!(i > 1);
 501
 502                 if (!sh->cmng.ccont[i].pools)
 503                         continue;
 504                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 505                 while (pool) {
 506                         if (batch && pool->min_dcs)
 507                                 claim_zero(mlx5_devx_cmd_destroy
 508                                                                (pool->min_dcs));
 509                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 510                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 511                                         claim_zero
 512                                          (mlx5_glue->destroy_flow_action
 513                                           (MLX5_POOL_GET_CNT
 514                                           (pool, j)->action));
 515                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 516                                     (pool, j)->dcs)
 517                                         claim_zero(mlx5_devx_cmd_destroy
 518                                                    (MLX5_GET_POOL_CNT_EXT
 519                                                     (pool, j)->dcs));
 520                         }
 521                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 522                         rte_free(pool);
 523                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 524                 }
 525                 rte_free(sh->cmng.ccont[i].pools);
 526         }
 527         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 528         while (mng) {
 529                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 530                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 531         }
 532         memset(&sh->cmng, 0, sizeof(sh->cmng));
 533 }
 534
 535 /**
 536  * Initialize the flow resources' indexed mempool.
 537  *
 538  * @param[in] sh
 539  *   Pointer to mlx5_dev_ctx_shared object.
 540  * @param[in] sh
 541  *   Pointer to user dev config.
 542  */
 543 static void
 544 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 545                        const struct mlx5_dev_config *config __rte_unused)
 546 {
 547         uint8_t i;
 548
 549 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 550         /*
 551          * While DV is supported, user chooses the verbs mode,
 552          * the mlx5 flow handle size is different with the
 553          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 554          */
 555         if (!config->dv_flow_en)
 556                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 557                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 558 #endif
 559         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 560                 if (config->reclaim_mode)
 561                         mlx5_ipool_cfg[i].release_mem_en = 1;
 562                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 563         }
 564 }
 565
 566 /**
 567  * Release the flow resources' indexed mempool.
 568  *
 569  * @param[in] sh
 570  *   Pointer to mlx5_dev_ctx_shared object.
 571  */
 572 static void
 573 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 574 {
 575         uint8_t i;
 576
 577         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 578                 mlx5_ipool_destroy(sh->ipool[i]);
 579 }
 580
 581 /**
 582  * Allocate shared IB device context. If there is multiport device the
 583  * master and representors will share this context, if there is single
 584  * port dedicated IB device, the context will be used by only given
 585  * port due to unification.
 586  *
 587  * Routine first searches the context for the specified IB device name,
 588  * if found the shared context assumed and reference counter is incremented.
 589  * If no context found the new one is created and initialized with specified
 590  * IB device context and parameters.
 591  *
 592  * @param[in] spawn
 593  *   Pointer to the IB device attributes (name, port, etc).
 594  * @param[in] config
 595  *   Pointer to device configuration structure.
 596  *
 597  * @return
 598  *   Pointer to mlx5_dev_ctx_shared object on success,
 599  *   otherwise NULL and rte_errno is set.
 600  */
 601 struct mlx5_dev_ctx_shared *
 602 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 603                         const struct mlx5_dev_config *config)
 604 {
 605         struct mlx5_dev_ctx_shared *sh;
 606         int err = 0;
 607         uint32_t i;
 608         struct mlx5_devx_tis_attr tis_attr = { 0 };
 609
 610         MLX5_ASSERT(spawn);
 611         /* Secondary process should not create the shared context. */
 612         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 613         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 614         /* Search for IB context by device name. */
 615         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 616                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 617                         sh->refcnt++;
 618                         goto exit;
 619                 }
 620         }
 621         /* No device found, we have to create new shared context. */
 622         MLX5_ASSERT(spawn->max_port);
 623         sh = rte_zmalloc("ethdev shared ib context",
 624                          sizeof(struct mlx5_dev_ctx_shared) +
 625                          spawn->max_port *
 626                          sizeof(struct mlx5_ibv_shared_port),
 627                          RTE_CACHE_LINE_SIZE);
 628         if (!sh) {
 629                 DRV_LOG(ERR, "shared context allocation failure");
 630                 rte_errno  = ENOMEM;
 631                 goto exit;
 632         }
 633         err = mlx5_os_open_device(spawn, config, sh);
 634         if (!sh->ctx)
 635                 goto error;
 636         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 637         if (err) {
 638                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 639                 goto error;
 640         }
 641         sh->refcnt = 1;
 642         sh->max_port = spawn->max_port;
 643         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 644                 sizeof(sh->ibdev_name) - 1);
 645         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 646                 sizeof(sh->ibdev_path) - 1);
 647         /*
 648          * Setting port_id to max unallowed value means
 649          * there is no interrupt subhandler installed for
 650          * the given port index i.
 651          */
 652         for (i = 0; i < sh->max_port; i++) {
 653                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 654                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 655         }
 656         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 657         if (sh->pd == NULL) {
 658                 DRV_LOG(ERR, "PD allocation failure");
 659                 err = ENOMEM;
 660                 goto error;
 661         }
 662         if (sh->devx) {
 663                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 664                 if (err) {
 665                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 666                         goto error;
 667                 }
 668                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 669                 if (!sh->td) {
 670                         DRV_LOG(ERR, "TD allocation failure");
 671                         err = ENOMEM;
 672                         goto error;
 673                 }
 674                 tis_attr.transport_domain = sh->td->id;
 675                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 676                 if (!sh->tis) {
 677                         DRV_LOG(ERR, "TIS allocation failure");
 678                         err = ENOMEM;
 679                         goto error;
 680                 }
 681         }
 682         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 683                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 684         if (!sh->flow_id_pool) {
 685                 DRV_LOG(ERR, "can't create flow id pool");
 686                 err = ENOMEM;
 687                 goto error;
 688         }
 689         /*
 690          * Once the device is added to the list of memory event
 691          * callback, its global MR cache table cannot be expanded
 692          * on the fly because of deadlock. If it overflows, lookup
 693          * should be done by searching MR list linearly, which is slow.
 694          *
 695          * At this point the device is not added to the memory
 696          * event list yet, context is just being created.
 697          */
 698         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 699                                  MLX5_MR_BTREE_CACHE_N * 2,
 700                                  spawn->pci_dev->device.numa_node);
 701         if (err) {
 702                 err = rte_errno;
 703                 goto error;
 704         }
 705         mlx5_os_dev_shared_handler_install(sh);
 706         mlx5_flow_aging_init(sh);
 707         mlx5_flow_counters_mng_init(sh);
 708         mlx5_flow_ipool_create(sh, config);
 709         /* Add device to memory callback list. */
 710         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 711         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 712                          sh, mem_event_cb);
 713         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 714         /* Add context to the global device list. */
 715         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 716 exit:
 717         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 718         return sh;
 719 error:
 720         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 721         MLX5_ASSERT(sh);
 722         if (sh->tis)
 723                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 724         if (sh->td)
 725                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 726         if (sh->pd)
 727                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 728         if (sh->ctx)
 729                 claim_zero(mlx5_glue->close_device(sh->ctx));
 730         if (sh->flow_id_pool)
 731                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 732         rte_free(sh);
 733         MLX5_ASSERT(err > 0);
 734         rte_errno = err;
 735         return NULL;
 736 }
 737
 738 /**
 739  * Free shared IB device context. Decrement counter and if zero free
 740  * all allocated resources and close handles.
 741  *
 742  * @param[in] sh
 743  *   Pointer to mlx5_dev_ctx_shared object to free
 744  */
 745 void
 746 mlx5_free_shared_ibctx(struct mlx5_dev_ctx_shared *sh)
 747 {
 748         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 749 #ifdef RTE_LIBRTE_MLX5_DEBUG
 750         /* Check the object presence in the list. */
 751         struct mlx5_dev_ctx_shared *lctx;
 752
 753         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 754                 if (lctx == sh)
 755                         break;
 756         MLX5_ASSERT(lctx);
 757         if (lctx != sh) {
 758                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 759                 goto exit;
 760         }
 761 #endif
 762         MLX5_ASSERT(sh);
 763         MLX5_ASSERT(sh->refcnt);
 764         /* Secondary process should not free the shared context. */
 765         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 766         if (--sh->refcnt)
 767                 goto exit;
 768         /* Remove from memory callback device list. */
 769         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 770         LIST_REMOVE(sh, mem_event_cb);
 771         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 772         /* Release created Memory Regions. */
 773         mlx5_mr_release_cache(&sh->share_cache);
 774         /* Remove context from the global device list. */
 775         LIST_REMOVE(sh, next);
 776         /*
 777          *  Ensure there is no async event handler installed.
 778          *  Only primary process handles async device events.
 779          **/
 780         mlx5_flow_counters_mng_close(sh);
 781         mlx5_flow_ipool_destroy(sh);
 782         mlx5_os_dev_shared_handler_uninstall(sh);
 783         if (sh->pd)
 784                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 785         if (sh->tis)
 786                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 787         if (sh->td)
 788                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 789         if (sh->ctx)
 790                 claim_zero(mlx5_glue->close_device(sh->ctx));
 791         if (sh->flow_id_pool)
 792                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 793         rte_free(sh);
 794 exit:
 795         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 796 }
 797
 798 /**
 799  * Destroy table hash list and all the root entries per domain.
 800  *
 801  * @param[in] priv
 802  *   Pointer to the private device data structure.
 803  */
 804 void
 805 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 806 {
 807         struct mlx5_dev_ctx_shared *sh = priv->sh;
 808         struct mlx5_flow_tbl_data_entry *tbl_data;
 809         union mlx5_flow_tbl_key table_key = {
 810                 {
 811                         .table_id = 0,
 812                         .reserved = 0,
 813                         .domain = 0,
 814                         .direction = 0,
 815                 }
 816         };
 817         struct mlx5_hlist_entry *pos;
 818
 819         if (!sh->flow_tbls)
 820                 return;
 821         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 822         if (pos) {
 823                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 824                                         entry);
 825                 MLX5_ASSERT(tbl_data);
 826                 mlx5_hlist_remove(sh->flow_tbls, pos);
 827                 rte_free(tbl_data);
 828         }
 829         table_key.direction = 1;
 830         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 831         if (pos) {
 832                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 833                                         entry);
 834                 MLX5_ASSERT(tbl_data);
 835                 mlx5_hlist_remove(sh->flow_tbls, pos);
 836                 rte_free(tbl_data);
 837         }
 838         table_key.direction = 0;
 839         table_key.domain = 1;
 840         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 841         if (pos) {
 842                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 843                                         entry);
 844                 MLX5_ASSERT(tbl_data);
 845                 mlx5_hlist_remove(sh->flow_tbls, pos);
 846                 rte_free(tbl_data);
 847         }
 848         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 849 }
 850
 851 /**
 852  * Initialize flow table hash list and create the root tables entry
 853  * for each domain.
 854  *
 855  * @param[in] priv
 856  *   Pointer to the private device data structure.
 857  *
 858  * @return
 859  *   Zero on success, positive error code otherwise.
 860  */
 861 int
 862 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 863 {
 864         struct mlx5_dev_ctx_shared *sh = priv->sh;
 865         char s[MLX5_HLIST_NAMESIZE];
 866         int err = 0;
 867
 868         MLX5_ASSERT(sh);
 869         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 870         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 871         if (!sh->flow_tbls) {
 872                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 873                 err = ENOMEM;
 874                 return err;
 875         }
 876 #ifndef HAVE_MLX5DV_DR
 877         /*
 878          * In case we have not DR support, the zero tables should be created
 879          * because DV expect to see them even if they cannot be created by
 880          * RDMA-CORE.
 881          */
 882         union mlx5_flow_tbl_key table_key = {
 883                 {
 884                         .table_id = 0,
 885                         .reserved = 0,
 886                         .domain = 0,
 887                         .direction = 0,
 888                 }
 889         };
 890         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 891                                                           sizeof(*tbl_data), 0);
 892
 893         if (!tbl_data) {
 894                 err = ENOMEM;
 895                 goto error;
 896         }
 897         tbl_data->entry.key = table_key.v64;
 898         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 899         if (err)
 900                 goto error;
 901         rte_atomic32_init(&tbl_data->tbl.refcnt);
 902         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 903         table_key.direction = 1;
 904         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 905         if (!tbl_data) {
 906                 err = ENOMEM;
 907                 goto error;
 908         }
 909         tbl_data->entry.key = table_key.v64;
 910         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 911         if (err)
 912                 goto error;
 913         rte_atomic32_init(&tbl_data->tbl.refcnt);
 914         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 915         table_key.direction = 0;
 916         table_key.domain = 1;
 917         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 918         if (!tbl_data) {
 919                 err = ENOMEM;
 920                 goto error;
 921         }
 922         tbl_data->entry.key = table_key.v64;
 923         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 924         if (err)
 925                 goto error;
 926         rte_atomic32_init(&tbl_data->tbl.refcnt);
 927         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 928         return err;
 929 error:
 930         mlx5_free_table_hash_list(priv);
 931 #endif /* HAVE_MLX5DV_DR */
 932         return err;
 933 }
 934
 935 /**
 936  * Initialize shared data between primary and secondary process.
 937  *
 938  * A memzone is reserved by primary process and secondary processes attach to
 939  * the memzone.
 940  *
 941  * @return
 942  *   0 on success, a negative errno value otherwise and rte_errno is set.
 943  */
 944 static int
 945 mlx5_init_shared_data(void)
 946 {
 947         const struct rte_memzone *mz;
 948         int ret = 0;
 949
 950         rte_spinlock_lock(&mlx5_shared_data_lock);
 951         if (mlx5_shared_data == NULL) {
 952                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 953                         /* Allocate shared memory. */
 954                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 955                                                  sizeof(*mlx5_shared_data),
 956                                                  SOCKET_ID_ANY, 0);
 957                         if (mz == NULL) {
 958                                 DRV_LOG(ERR,
 959                                         "Cannot allocate mlx5 shared data");
 960                                 ret = -rte_errno;
 961                                 goto error;
 962                         }
 963                         mlx5_shared_data = mz->addr;
 964                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 965                         rte_spinlock_init(&mlx5_shared_data->lock);
 966                 } else {
 967                         /* Lookup allocated shared memory. */
 968                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
 969                         if (mz == NULL) {
 970                                 DRV_LOG(ERR,
 971                                         "Cannot attach mlx5 shared data");
 972                                 ret = -rte_errno;
 973                                 goto error;
 974                         }
 975                         mlx5_shared_data = mz->addr;
 976                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
 977                 }
 978         }
 979 error:
 980         rte_spinlock_unlock(&mlx5_shared_data_lock);
 981         return ret;
 982 }
 983
 984 /**
 985  * Retrieve integer value from environment variable.
 986  *
 987  * @param[in] name
 988  *   Environment variable name.
 989  *
 990  * @return
 991  *   Integer value, 0 if the variable is not set.
 992  */
 993 int
 994 mlx5_getenv_int(const char *name)
 995 {
 996         const char *val = getenv(name);
 997
 998         if (val == NULL)
 999                 return 0;
1000         return atoi(val);
1001 }
1002
1003 /**
1004  * DPDK callback to add udp tunnel port
1005  *
1006  * @param[in] dev
1007  *   A pointer to eth_dev
1008  * @param[in] udp_tunnel
1009  *   A pointer to udp tunnel
1010  *
1011  * @return
1012  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1013  */
1014 int
1015 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1016                          struct rte_eth_udp_tunnel *udp_tunnel)
1017 {
1018         MLX5_ASSERT(udp_tunnel != NULL);
1019         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1020             udp_tunnel->udp_port == 4789)
1021                 return 0;
1022         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1023             udp_tunnel->udp_port == 4790)
1024                 return 0;
1025         return -ENOTSUP;
1026 }
1027
1028 /**
1029  * Initialize process private data structure.
1030  *
1031  * @param dev
1032  *   Pointer to Ethernet device structure.
1033  *
1034  * @return
1035  *   0 on success, a negative errno value otherwise and rte_errno is set.
1036  */
1037 int
1038 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1039 {
1040         struct mlx5_priv *priv = dev->data->dev_private;
1041         struct mlx5_proc_priv *ppriv;
1042         size_t ppriv_size;
1043
1044         /*
1045          * UAR register table follows the process private structure. BlueFlame
1046          * registers for Tx queues are stored in the table.
1047          */
1048         ppriv_size =
1049                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1050         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1051                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1052         if (!ppriv) {
1053                 rte_errno = ENOMEM;
1054                 return -rte_errno;
1055         }
1056         ppriv->uar_table_sz = ppriv_size;
1057         dev->process_private = ppriv;
1058         return 0;
1059 }
1060
1061 /**
1062  * Un-initialize process private data structure.
1063  *
1064  * @param dev
1065  *   Pointer to Ethernet device structure.
1066  */
1067 static void
1068 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1069 {
1070         if (!dev->process_private)
1071                 return;
1072         rte_free(dev->process_private);
1073         dev->process_private = NULL;
1074 }
1075
1076 /**
1077  * DPDK callback to close the device.
1078  *
1079  * Destroy all queues and objects, free memory.
1080  *
1081  * @param dev
1082  *   Pointer to Ethernet device structure.
1083  */
1084 void
1085 mlx5_dev_close(struct rte_eth_dev *dev)
1086 {
1087         struct mlx5_priv *priv = dev->data->dev_private;
1088         unsigned int i;
1089         int ret;
1090
1091         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1092                 /* Check if process_private released. */
1093                 if (!dev->process_private)
1094                         return;
1095                 mlx5_tx_uar_uninit_secondary(dev);
1096                 mlx5_proc_priv_uninit(dev);
1097                 rte_eth_dev_release_port(dev);
1098                 return;
1099         }
1100         if (!priv->sh)
1101                 return;
1102         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1103                 dev->data->port_id,
1104                 ((priv->sh->ctx != NULL) ?
1105                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1106         /*
1107          * If default mreg copy action is removed at the stop stage,
1108          * the search will return none and nothing will be done anymore.
1109          */
1110         mlx5_flow_stop_default(dev);
1111         mlx5_traffic_disable(dev);
1112         /*
1113          * If all the flows are already flushed in the device stop stage,
1114          * then this will return directly without any action.
1115          */
1116         mlx5_flow_list_flush(dev, &priv->flows, true);
1117         mlx5_flow_meter_flush(dev, NULL);
1118         /* Free the intermediate buffers for flow creation. */
1119         mlx5_flow_free_intermediate(dev);
1120         /* Prevent crashes when queues are still in use. */
1121         dev->rx_pkt_burst = removed_rx_burst;
1122         dev->tx_pkt_burst = removed_tx_burst;
1123         rte_wmb();
1124         /* Disable datapath on secondary process. */
1125         mlx5_mp_req_stop_rxtx(dev);
1126         if (priv->rxqs != NULL) {
1127                 /* XXX race condition if mlx5_rx_burst() is still running. */
1128                 usleep(1000);
1129                 for (i = 0; (i != priv->rxqs_n); ++i)
1130                         mlx5_rxq_release(dev, i);
1131                 priv->rxqs_n = 0;
1132                 priv->rxqs = NULL;
1133         }
1134         if (priv->txqs != NULL) {
1135                 /* XXX race condition if mlx5_tx_burst() is still running. */
1136                 usleep(1000);
1137                 for (i = 0; (i != priv->txqs_n); ++i)
1138                         mlx5_txq_release(dev, i);
1139                 priv->txqs_n = 0;
1140                 priv->txqs = NULL;
1141         }
1142         mlx5_proc_priv_uninit(dev);
1143         if (priv->mreg_cp_tbl)
1144                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1145         mlx5_mprq_free_mp(dev);
1146         mlx5_os_free_shared_dr(priv);
1147         if (priv->rss_conf.rss_key != NULL)
1148                 rte_free(priv->rss_conf.rss_key);
1149         if (priv->reta_idx != NULL)
1150                 rte_free(priv->reta_idx);
1151         if (priv->config.vf)
1152                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1153                                        dev->data->mac_addrs,
1154                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1155         if (priv->nl_socket_route >= 0)
1156                 close(priv->nl_socket_route);
1157         if (priv->nl_socket_rdma >= 0)
1158                 close(priv->nl_socket_rdma);
1159         if (priv->vmwa_context)
1160                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1161         ret = mlx5_hrxq_verify(dev);
1162         if (ret)
1163                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1164                         dev->data->port_id);
1165         ret = mlx5_ind_table_obj_verify(dev);
1166         if (ret)
1167                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1168                         dev->data->port_id);
1169         ret = mlx5_rxq_obj_verify(dev);
1170         if (ret)
1171                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1172                         dev->data->port_id);
1173         ret = mlx5_rxq_verify(dev);
1174         if (ret)
1175                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1176                         dev->data->port_id);
1177         ret = mlx5_txq_obj_verify(dev);
1178         if (ret)
1179                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1180                         dev->data->port_id);
1181         ret = mlx5_txq_verify(dev);
1182         if (ret)
1183                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1184                         dev->data->port_id);
1185         ret = mlx5_flow_verify(dev);
1186         if (ret)
1187                 DRV_LOG(WARNING, "port %u some flows still remain",
1188                         dev->data->port_id);
1189         /*
1190          * Free the shared context in last turn, because the cleanup
1191          * routines above may use some shared fields, like
1192          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1193          * ifindex if Netlink fails.
1194          */
1195         mlx5_free_shared_ibctx(priv->sh);
1196         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1197                 unsigned int c = 0;
1198                 uint16_t port_id;
1199
1200                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1201                         struct mlx5_priv *opriv =
1202                                 rte_eth_devices[port_id].data->dev_private;
1203
1204                         if (!opriv ||
1205                             opriv->domain_id != priv->domain_id ||
1206                             &rte_eth_devices[port_id] == dev)
1207                                 continue;
1208                         ++c;
1209                         break;
1210                 }
1211                 if (!c)
1212                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1213         }
1214         memset(priv, 0, sizeof(*priv));
1215         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1216         /*
1217          * Reset mac_addrs to NULL such that it is not freed as part of
1218          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1219          * it is freed when dev_private is freed.
1220          */
1221         dev->data->mac_addrs = NULL;
1222 }
1223
1224 const struct eth_dev_ops mlx5_dev_ops = {
1225         .dev_configure = mlx5_dev_configure,
1226         .dev_start = mlx5_dev_start,
1227         .dev_stop = mlx5_dev_stop,
1228         .dev_set_link_down = mlx5_set_link_down,
1229         .dev_set_link_up = mlx5_set_link_up,
1230         .dev_close = mlx5_dev_close,
1231         .promiscuous_enable = mlx5_promiscuous_enable,
1232         .promiscuous_disable = mlx5_promiscuous_disable,
1233         .allmulticast_enable = mlx5_allmulticast_enable,
1234         .allmulticast_disable = mlx5_allmulticast_disable,
1235         .link_update = mlx5_link_update,
1236         .stats_get = mlx5_stats_get,
1237         .stats_reset = mlx5_stats_reset,
1238         .xstats_get = mlx5_xstats_get,
1239         .xstats_reset = mlx5_xstats_reset,
1240         .xstats_get_names = mlx5_xstats_get_names,
1241         .fw_version_get = mlx5_fw_version_get,
1242         .dev_infos_get = mlx5_dev_infos_get,
1243         .read_clock = mlx5_read_clock,
1244         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1245         .vlan_filter_set = mlx5_vlan_filter_set,
1246         .rx_queue_setup = mlx5_rx_queue_setup,
1247         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1248         .tx_queue_setup = mlx5_tx_queue_setup,
1249         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1250         .rx_queue_release = mlx5_rx_queue_release,
1251         .tx_queue_release = mlx5_tx_queue_release,
1252         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1253         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1254         .mac_addr_remove = mlx5_mac_addr_remove,
1255         .mac_addr_add = mlx5_mac_addr_add,
1256         .mac_addr_set = mlx5_mac_addr_set,
1257         .set_mc_addr_list = mlx5_set_mc_addr_list,
1258         .mtu_set = mlx5_dev_set_mtu,
1259         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1260         .vlan_offload_set = mlx5_vlan_offload_set,
1261         .reta_update = mlx5_dev_rss_reta_update,
1262         .reta_query = mlx5_dev_rss_reta_query,
1263         .rss_hash_update = mlx5_rss_hash_update,
1264         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1265         .filter_ctrl = mlx5_dev_filter_ctrl,
1266         .rx_descriptor_status = mlx5_rx_descriptor_status,
1267         .tx_descriptor_status = mlx5_tx_descriptor_status,
1268         .rxq_info_get = mlx5_rxq_info_get,
1269         .txq_info_get = mlx5_txq_info_get,
1270         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1271         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1272         .rx_queue_count = mlx5_rx_queue_count,
1273         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1274         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1275         .is_removed = mlx5_is_removed,
1276         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1277         .get_module_info = mlx5_get_module_info,
1278         .get_module_eeprom = mlx5_get_module_eeprom,
1279         .hairpin_cap_get = mlx5_hairpin_cap_get,
1280         .mtr_ops_get = mlx5_flow_meter_ops_get,
1281 };
1282
1283 /* Available operations from secondary process. */
1284 const struct eth_dev_ops mlx5_dev_sec_ops = {
1285         .stats_get = mlx5_stats_get,
1286         .stats_reset = mlx5_stats_reset,
1287         .xstats_get = mlx5_xstats_get,
1288         .xstats_reset = mlx5_xstats_reset,
1289         .xstats_get_names = mlx5_xstats_get_names,
1290         .fw_version_get = mlx5_fw_version_get,
1291         .dev_infos_get = mlx5_dev_infos_get,
1292         .rx_descriptor_status = mlx5_rx_descriptor_status,
1293         .tx_descriptor_status = mlx5_tx_descriptor_status,
1294         .rxq_info_get = mlx5_rxq_info_get,
1295         .txq_info_get = mlx5_txq_info_get,
1296         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1297         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1298         .get_module_info = mlx5_get_module_info,
1299         .get_module_eeprom = mlx5_get_module_eeprom,
1300 };
1301
1302 /* Available operations in flow isolated mode. */
1303 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1304         .dev_configure = mlx5_dev_configure,
1305         .dev_start = mlx5_dev_start,
1306         .dev_stop = mlx5_dev_stop,
1307         .dev_set_link_down = mlx5_set_link_down,
1308         .dev_set_link_up = mlx5_set_link_up,
1309         .dev_close = mlx5_dev_close,
1310         .promiscuous_enable = mlx5_promiscuous_enable,
1311         .promiscuous_disable = mlx5_promiscuous_disable,
1312         .allmulticast_enable = mlx5_allmulticast_enable,
1313         .allmulticast_disable = mlx5_allmulticast_disable,
1314         .link_update = mlx5_link_update,
1315         .stats_get = mlx5_stats_get,
1316         .stats_reset = mlx5_stats_reset,
1317         .xstats_get = mlx5_xstats_get,
1318         .xstats_reset = mlx5_xstats_reset,
1319         .xstats_get_names = mlx5_xstats_get_names,
1320         .fw_version_get = mlx5_fw_version_get,
1321         .dev_infos_get = mlx5_dev_infos_get,
1322         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1323         .vlan_filter_set = mlx5_vlan_filter_set,
1324         .rx_queue_setup = mlx5_rx_queue_setup,
1325         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1326         .tx_queue_setup = mlx5_tx_queue_setup,
1327         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1328         .rx_queue_release = mlx5_rx_queue_release,
1329         .tx_queue_release = mlx5_tx_queue_release,
1330         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1331         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1332         .mac_addr_remove = mlx5_mac_addr_remove,
1333         .mac_addr_add = mlx5_mac_addr_add,
1334         .mac_addr_set = mlx5_mac_addr_set,
1335         .set_mc_addr_list = mlx5_set_mc_addr_list,
1336         .mtu_set = mlx5_dev_set_mtu,
1337         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1338         .vlan_offload_set = mlx5_vlan_offload_set,
1339         .filter_ctrl = mlx5_dev_filter_ctrl,
1340         .rx_descriptor_status = mlx5_rx_descriptor_status,
1341         .tx_descriptor_status = mlx5_tx_descriptor_status,
1342         .rxq_info_get = mlx5_rxq_info_get,
1343         .txq_info_get = mlx5_txq_info_get,
1344         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1345         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1346         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1347         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1348         .is_removed = mlx5_is_removed,
1349         .get_module_info = mlx5_get_module_info,
1350         .get_module_eeprom = mlx5_get_module_eeprom,
1351         .hairpin_cap_get = mlx5_hairpin_cap_get,
1352         .mtr_ops_get = mlx5_flow_meter_ops_get,
1353 };
1354
1355 /**
1356  * Verify and store value for device argument.
1357  *
1358  * @param[in] key
1359  *   Key argument to verify.
1360  * @param[in] val
1361  *   Value associated with key.
1362  * @param opaque
1363  *   User data.
1364  *
1365  * @return
1366  *   0 on success, a negative errno value otherwise and rte_errno is set.
1367  */
1368 static int
1369 mlx5_args_check(const char *key, const char *val, void *opaque)
1370 {
1371         struct mlx5_dev_config *config = opaque;
1372         unsigned long tmp;
1373
1374         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1375         if (!strcmp(MLX5_REPRESENTOR, key))
1376                 return 0;
1377         errno = 0;
1378         tmp = strtoul(val, NULL, 0);
1379         if (errno) {
1380                 rte_errno = errno;
1381                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1382                 return -rte_errno;
1383         }
1384         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1385                 config->cqe_comp = !!tmp;
1386         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1387                 config->cqe_pad = !!tmp;
1388         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1389                 config->hw_padding = !!tmp;
1390         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1391                 config->mprq.enabled = !!tmp;
1392         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1393                 config->mprq.stride_num_n = tmp;
1394         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1395                 config->mprq.stride_size_n = tmp;
1396         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1397                 config->mprq.max_memcpy_len = tmp;
1398         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1399                 config->mprq.min_rxqs_num = tmp;
1400         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1401                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1402                                  " converted to txq_inline_max", key);
1403                 config->txq_inline_max = tmp;
1404         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1405                 config->txq_inline_max = tmp;
1406         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1407                 config->txq_inline_min = tmp;
1408         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1409                 config->txq_inline_mpw = tmp;
1410         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1411                 config->txqs_inline = tmp;
1412         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1413                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1414         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1415                 config->mps = !!tmp;
1416         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1417                 if (tmp != MLX5_TXDB_CACHED &&
1418                     tmp != MLX5_TXDB_NCACHED &&
1419                     tmp != MLX5_TXDB_HEURISTIC) {
1420                         DRV_LOG(ERR, "invalid Tx doorbell "
1421                                      "mapping parameter");
1422                         rte_errno = EINVAL;
1423                         return -rte_errno;
1424                 }
1425                 config->dbnc = tmp;
1426         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1427                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1428         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1429                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1430                                  " converted to txq_inline_mpw", key);
1431                 config->txq_inline_mpw = tmp;
1432         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1433                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1434         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1435                 config->rx_vec_en = !!tmp;
1436         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1437                 config->l3_vxlan_en = !!tmp;
1438         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1439                 config->vf_nl_en = !!tmp;
1440         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1441                 config->dv_esw_en = !!tmp;
1442         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1443                 config->dv_flow_en = !!tmp;
1444         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1445                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1446                     tmp != MLX5_XMETA_MODE_META16 &&
1447                     tmp != MLX5_XMETA_MODE_META32) {
1448                         DRV_LOG(ERR, "invalid extensive "
1449                                      "metadata parameter");
1450                         rte_errno = EINVAL;
1451                         return -rte_errno;
1452                 }
1453                 config->dv_xmeta_en = tmp;
1454         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1455                 config->mr_ext_memseg_en = !!tmp;
1456         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1457                 config->max_dump_files_num = tmp;
1458         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1459                 config->lro.timeout = tmp;
1460         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1461                 DRV_LOG(DEBUG, "class argument is %s.", val);
1462         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1463                 config->log_hp_size = tmp;
1464         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1465                 if (tmp != MLX5_RCM_NONE &&
1466                     tmp != MLX5_RCM_LIGHT &&
1467                     tmp != MLX5_RCM_AGGR) {
1468                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1469                         rte_errno = EINVAL;
1470                         return -rte_errno;
1471                 }
1472                 config->reclaim_mode = tmp;
1473         } else {
1474                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1475                 rte_errno = EINVAL;
1476                 return -rte_errno;
1477         }
1478         return 0;
1479 }
1480
1481 /**
1482  * Parse device parameters.
1483  *
1484  * @param config
1485  *   Pointer to device configuration structure.
1486  * @param devargs
1487  *   Device arguments structure.
1488  *
1489  * @return
1490  *   0 on success, a negative errno value otherwise and rte_errno is set.
1491  */
1492 int
1493 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1494 {
1495         const char **params = (const char *[]){
1496                 MLX5_RXQ_CQE_COMP_EN,
1497                 MLX5_RXQ_CQE_PAD_EN,
1498                 MLX5_RXQ_PKT_PAD_EN,
1499                 MLX5_RX_MPRQ_EN,
1500                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1501                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1502                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1503                 MLX5_RXQS_MIN_MPRQ,
1504                 MLX5_TXQ_INLINE,
1505                 MLX5_TXQ_INLINE_MIN,
1506                 MLX5_TXQ_INLINE_MAX,
1507                 MLX5_TXQ_INLINE_MPW,
1508                 MLX5_TXQS_MIN_INLINE,
1509                 MLX5_TXQS_MAX_VEC,
1510                 MLX5_TXQ_MPW_EN,
1511                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1512                 MLX5_TXQ_MAX_INLINE_LEN,
1513                 MLX5_TX_DB_NC,
1514                 MLX5_TX_VEC_EN,
1515                 MLX5_RX_VEC_EN,
1516                 MLX5_L3_VXLAN_EN,
1517                 MLX5_VF_NL_EN,
1518                 MLX5_DV_ESW_EN,
1519                 MLX5_DV_FLOW_EN,
1520                 MLX5_DV_XMETA_EN,
1521                 MLX5_MR_EXT_MEMSEG_EN,
1522                 MLX5_REPRESENTOR,
1523                 MLX5_MAX_DUMP_FILES_NUM,
1524                 MLX5_LRO_TIMEOUT_USEC,
1525                 MLX5_CLASS_ARG_NAME,
1526                 MLX5_HP_BUF_SIZE,
1527                 MLX5_RECLAIM_MEM,
1528                 NULL,
1529         };
1530         struct rte_kvargs *kvlist;
1531         int ret = 0;
1532         int i;
1533
1534         if (devargs == NULL)
1535                 return 0;
1536         /* Following UGLY cast is done to pass checkpatch. */
1537         kvlist = rte_kvargs_parse(devargs->args, params);
1538         if (kvlist == NULL) {
1539                 rte_errno = EINVAL;
1540                 return -rte_errno;
1541         }
1542         /* Process parameters. */
1543         for (i = 0; (params[i] != NULL); ++i) {
1544                 if (rte_kvargs_count(kvlist, params[i])) {
1545                         ret = rte_kvargs_process(kvlist, params[i],
1546                                                  mlx5_args_check, config);
1547                         if (ret) {
1548                                 rte_errno = EINVAL;
1549                                 rte_kvargs_free(kvlist);
1550                                 return -rte_errno;
1551                         }
1552                 }
1553         }
1554         rte_kvargs_free(kvlist);
1555         return 0;
1556 }
1557
1558 /**
1559  * PMD global initialization.
1560  *
1561  * Independent from individual device, this function initializes global
1562  * per-PMD data structures distinguishing primary and secondary processes.
1563  * Hence, each initialization is called once per a process.
1564  *
1565  * @return
1566  *   0 on success, a negative errno value otherwise and rte_errno is set.
1567  */
1568 int
1569 mlx5_init_once(void)
1570 {
1571         struct mlx5_shared_data *sd;
1572         struct mlx5_local_data *ld = &mlx5_local_data;
1573         int ret = 0;
1574
1575         if (mlx5_init_shared_data())
1576                 return -rte_errno;
1577         sd = mlx5_shared_data;
1578         MLX5_ASSERT(sd);
1579         rte_spinlock_lock(&sd->lock);
1580         switch (rte_eal_process_type()) {
1581         case RTE_PROC_PRIMARY:
1582                 if (sd->init_done)
1583                         break;
1584                 LIST_INIT(&sd->mem_event_cb_list);
1585                 rte_rwlock_init(&sd->mem_event_rwlock);
1586                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1587                                                 mlx5_mr_mem_event_cb, NULL);
1588                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1589                                            mlx5_mp_primary_handle);
1590                 if (ret)
1591                         goto out;
1592                 sd->init_done = true;
1593                 break;
1594         case RTE_PROC_SECONDARY:
1595                 if (ld->init_done)
1596                         break;
1597                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1598                                              mlx5_mp_secondary_handle);
1599                 if (ret)
1600                         goto out;
1601                 ++sd->secondary_cnt;
1602                 ld->init_done = true;
1603                 break;
1604         default:
1605                 break;
1606         }
1607 out:
1608         rte_spinlock_unlock(&sd->lock);
1609         return ret;
1610 }
1611
1612 /**
1613  * Configures the minimal amount of data to inline into WQE
1614  * while sending packets.
1615  *
1616  * - the txq_inline_min has the maximal priority, if this
1617  *   key is specified in devargs
1618  * - if DevX is enabled the inline mode is queried from the
1619  *   device (HCA attributes and NIC vport context if needed).
1620  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1621  *   and none (0 bytes) for other NICs
1622  *
1623  * @param spawn
1624  *   Verbs device parameters (name, port, switch_info) to spawn.
1625  * @param config
1626  *   Device configuration parameters.
1627  */
1628 void
1629 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1630                     struct mlx5_dev_config *config)
1631 {
1632         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1633                 /* Application defines size of inlined data explicitly. */
1634                 switch (spawn->pci_dev->id.device_id) {
1635                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1636                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1637                         if (config->txq_inline_min <
1638                                        (int)MLX5_INLINE_HSIZE_L2) {
1639                                 DRV_LOG(DEBUG,
1640                                         "txq_inline_mix aligned to minimal"
1641                                         " ConnectX-4 required value %d",
1642                                         (int)MLX5_INLINE_HSIZE_L2);
1643                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1644                         }
1645                         break;
1646                 }
1647                 goto exit;
1648         }
1649         if (config->hca_attr.eth_net_offloads) {
1650                 /* We have DevX enabled, inline mode queried successfully. */
1651                 switch (config->hca_attr.wqe_inline_mode) {
1652                 case MLX5_CAP_INLINE_MODE_L2:
1653                         /* outer L2 header must be inlined. */
1654                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1655                         goto exit;
1656                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1657                         /* No inline data are required by NIC. */
1658                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1659                         config->hw_vlan_insert =
1660                                 config->hca_attr.wqe_vlan_insert;
1661                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1662                         goto exit;
1663                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1664                         /* inline mode is defined by NIC vport context. */
1665                         if (!config->hca_attr.eth_virt)
1666                                 break;
1667                         switch (config->hca_attr.vport_inline_mode) {
1668                         case MLX5_INLINE_MODE_NONE:
1669                                 config->txq_inline_min =
1670                                         MLX5_INLINE_HSIZE_NONE;
1671                                 goto exit;
1672                         case MLX5_INLINE_MODE_L2:
1673                                 config->txq_inline_min =
1674                                         MLX5_INLINE_HSIZE_L2;
1675                                 goto exit;
1676                         case MLX5_INLINE_MODE_IP:
1677                                 config->txq_inline_min =
1678                                         MLX5_INLINE_HSIZE_L3;
1679                                 goto exit;
1680                         case MLX5_INLINE_MODE_TCP_UDP:
1681                                 config->txq_inline_min =
1682                                         MLX5_INLINE_HSIZE_L4;
1683                                 goto exit;
1684                         case MLX5_INLINE_MODE_INNER_L2:
1685                                 config->txq_inline_min =
1686                                         MLX5_INLINE_HSIZE_INNER_L2;
1687                                 goto exit;
1688                         case MLX5_INLINE_MODE_INNER_IP:
1689                                 config->txq_inline_min =
1690                                         MLX5_INLINE_HSIZE_INNER_L3;
1691                                 goto exit;
1692                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1693                                 config->txq_inline_min =
1694                                         MLX5_INLINE_HSIZE_INNER_L4;
1695                                 goto exit;
1696                         }
1697                 }
1698         }
1699         /*
1700          * We get here if we are unable to deduce
1701          * inline data size with DevX. Try PCI ID
1702          * to determine old NICs.
1703          */
1704         switch (spawn->pci_dev->id.device_id) {
1705         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1706         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1707         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1708         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1709                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1710                 config->hw_vlan_insert = 0;
1711                 break;
1712         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1713         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1714         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1715         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1716                 /*
1717                  * These NICs support VLAN insertion from WQE and
1718                  * report the wqe_vlan_insert flag. But there is the bug
1719                  * and PFC control may be broken, so disable feature.
1720                  */
1721                 config->hw_vlan_insert = 0;
1722                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1723                 break;
1724         default:
1725                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1726                 break;
1727         }
1728 exit:
1729         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1730 }
1731
1732 /**
1733  * Configures the metadata mask fields in the shared context.
1734  *
1735  * @param [in] dev
1736  *   Pointer to Ethernet device.
1737  */
1738 void
1739 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1740 {
1741         struct mlx5_priv *priv = dev->data->dev_private;
1742         struct mlx5_dev_ctx_shared *sh = priv->sh;
1743         uint32_t meta, mark, reg_c0;
1744
1745         reg_c0 = ~priv->vport_meta_mask;
1746         switch (priv->config.dv_xmeta_en) {
1747         case MLX5_XMETA_MODE_LEGACY:
1748                 meta = UINT32_MAX;
1749                 mark = MLX5_FLOW_MARK_MASK;
1750                 break;
1751         case MLX5_XMETA_MODE_META16:
1752                 meta = reg_c0 >> rte_bsf32(reg_c0);
1753                 mark = MLX5_FLOW_MARK_MASK;
1754                 break;
1755         case MLX5_XMETA_MODE_META32:
1756                 meta = UINT32_MAX;
1757                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1758                 break;
1759         default:
1760                 meta = 0;
1761                 mark = 0;
1762                 MLX5_ASSERT(false);
1763                 break;
1764         }
1765         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1766                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1767                                  sh->dv_mark_mask, mark);
1768         else
1769                 sh->dv_mark_mask = mark;
1770         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1771                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1772                                  sh->dv_meta_mask, meta);
1773         else
1774                 sh->dv_meta_mask = meta;
1775         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1776                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1777                                  sh->dv_meta_mask, reg_c0);
1778         else
1779                 sh->dv_regc0_mask = reg_c0;
1780         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1781         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1782         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1783         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1784 }
1785
1786 /**
1787  * Allocate page of door-bells and register it using DevX API.
1788  *
1789  * @param [in] dev
1790  *   Pointer to Ethernet device.
1791  *
1792  * @return
1793  *   Pointer to new page on success, NULL otherwise.
1794  */
1795 static struct mlx5_devx_dbr_page *
1796 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1797 {
1798         struct mlx5_priv *priv = dev->data->dev_private;
1799         struct mlx5_devx_dbr_page *page;
1800
1801         /* Allocate space for door-bell page and management data. */
1802         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1803                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1804         if (!page) {
1805                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1806                         dev->data->port_id);
1807                 return NULL;
1808         }
1809         /* Register allocated memory. */
1810         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1811                                               MLX5_DBR_PAGE_SIZE, 0);
1812         if (!page->umem) {
1813                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1814                         dev->data->port_id);
1815                 rte_free(page);
1816                 return NULL;
1817         }
1818         return page;
1819 }
1820
1821 /**
1822  * Find the next available door-bell, allocate new page if needed.
1823  *
1824  * @param [in] dev
1825  *   Pointer to Ethernet device.
1826  * @param [out] dbr_page
1827  *   Door-bell page containing the page data.
1828  *
1829  * @return
1830  *   Door-bell address offset on success, a negative error value otherwise.
1831  */
1832 int64_t
1833 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1834 {
1835         struct mlx5_priv *priv = dev->data->dev_private;
1836         struct mlx5_devx_dbr_page *page = NULL;
1837         uint32_t i, j;
1838
1839         LIST_FOREACH(page, &priv->dbrpgs, next)
1840                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1841                         break;
1842         if (!page) { /* No page with free door-bell exists. */
1843                 page = mlx5_alloc_dbr_page(dev);
1844                 if (!page) /* Failed to allocate new page. */
1845                         return (-1);
1846                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1847         }
1848         /* Loop to find bitmap part with clear bit. */
1849         for (i = 0;
1850              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1851              i++)
1852                 ; /* Empty. */
1853         /* Find the first clear bit. */
1854         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1855         j = rte_bsf64(~page->dbr_bitmap[i]);
1856         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1857         page->dbr_count++;
1858         *dbr_page = page;
1859         return (((i * 64) + j) * sizeof(uint64_t));
1860 }
1861
1862 /**
1863  * Release a door-bell record.
1864  *
1865  * @param [in] dev
1866  *   Pointer to Ethernet device.
1867  * @param [in] umem_id
1868  *   UMEM ID of page containing the door-bell record to release.
1869  * @param [in] offset
1870  *   Offset of door-bell record in page.
1871  *
1872  * @return
1873  *   0 on success, a negative error value otherwise.
1874  */
1875 int32_t
1876 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1877 {
1878         struct mlx5_priv *priv = dev->data->dev_private;
1879         struct mlx5_devx_dbr_page *page = NULL;
1880         int ret = 0;
1881
1882         LIST_FOREACH(page, &priv->dbrpgs, next)
1883                 /* Find the page this address belongs to. */
1884                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1885                         break;
1886         if (!page)
1887                 return -EINVAL;
1888         page->dbr_count--;
1889         if (!page->dbr_count) {
1890                 /* Page not used, free it and remove from list. */
1891                 LIST_REMOVE(page, next);
1892                 if (page->umem)
1893                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1894                 rte_free(page);
1895         } else {
1896                 /* Mark in bitmap that this door-bell is not in use. */
1897                 offset /= MLX5_DBR_SIZE;
1898                 int i = offset / 64;
1899                 int j = offset % 64;
1900
1901                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1902         }
1903         return ret;
1904 }
1905
1906 int
1907 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1908 {
1909         static const char *const dynf_names[] = {
1910                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1911                 RTE_MBUF_DYNFLAG_METADATA_NAME
1912         };
1913         unsigned int i;
1914
1915         if (n < RTE_DIM(dynf_names))
1916                 return -ENOMEM;
1917         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1918                 if (names[i] == NULL)
1919                         return -EINVAL;
1920                 strcpy(names[i], dynf_names[i]);
1921         }
1922         return RTE_DIM(dynf_names);
1923 }
1924
1925 /**
1926  * Comparison callback to sort device data.
1927  *
1928  * This is meant to be used with qsort().
1929  *
1930  * @param a[in]
1931  *   Pointer to pointer to first data object.
1932  * @param b[in]
1933  *   Pointer to pointer to second data object.
1934  *
1935  * @return
1936  *   0 if both objects are equal, less than 0 if the first argument is less
1937  *   than the second, greater than 0 otherwise.
1938  */
1939 int
1940 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1941                               struct mlx5_dev_config *config)
1942 {
1943         struct mlx5_dev_ctx_shared *sh = priv->sh;
1944         struct mlx5_dev_config *sh_conf = NULL;
1945         uint16_t port_id;
1946
1947         MLX5_ASSERT(sh);
1948         /* Nothing to compare for the single/first device. */
1949         if (sh->refcnt == 1)
1950                 return 0;
1951         /* Find the device with shared context. */
1952         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1953                 struct mlx5_priv *opriv =
1954                         rte_eth_devices[port_id].data->dev_private;
1955
1956                 if (opriv && opriv != priv && opriv->sh == sh) {
1957                         sh_conf = &opriv->config;
1958                         break;
1959                 }
1960         }
1961         if (!sh_conf)
1962                 return 0;
1963         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1964                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1965                              " for shared %s context", sh->ibdev_name);
1966                 rte_errno = EINVAL;
1967                 return rte_errno;
1968         }
1969         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1970                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1971                              " for shared %s context", sh->ibdev_name);
1972                 rte_errno = EINVAL;
1973                 return rte_errno;
1974         }
1975         return 0;
1976 }
1977
1978 /**
1979  * Look for the ethernet device belonging to mlx5 driver.
1980  *
1981  * @param[in] port_id
1982  *   port_id to start looking for device.
1983  * @param[in] pci_dev
1984  *   Pointer to the hint PCI device. When device is being probed
1985  *   the its siblings (master and preceding representors might
1986  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1987  *   is not completed yet, for this case match on hint PCI
1988  *   device may be used to detect sibling device.
1989  *
1990  * @return
1991  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1992  */
1993 uint16_t
1994 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1995 {
1996         while (port_id < RTE_MAX_ETHPORTS) {
1997                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1998
1999                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2000                     dev->device &&
2001                     (dev->device == &pci_dev->device ||
2002                      (dev->device->driver &&
2003                      dev->device->driver->name &&
2004                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2005                         break;
2006                 port_id++;
2007         }
2008         if (port_id >= RTE_MAX_ETHPORTS)
2009                 return RTE_MAX_ETHPORTS;
2010         return port_id;
2011 }
2012
2013 /**
2014  * DPDK callback to remove a PCI device.
2015  *
2016  * This function removes all Ethernet devices belong to a given PCI device.
2017  *
2018  * @param[in] pci_dev
2019  *   Pointer to the PCI device.
2020  *
2021  * @return
2022  *   0 on success, the function cannot fail.
2023  */
2024 static int
2025 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2026 {
2027         uint16_t port_id;
2028
2029         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2030                 /*
2031                  * mlx5_dev_close() is not registered to secondary process,
2032                  * call the close function explicitly for secondary process.
2033                  */
2034                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2035                         mlx5_dev_close(&rte_eth_devices[port_id]);
2036                 else
2037                         rte_eth_dev_close(port_id);
2038         }
2039         return 0;
2040 }
2041
2042 static const struct rte_pci_id mlx5_pci_id_map[] = {
2043         {
2044                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2045                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2046         },
2047         {
2048                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2049                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2050         },
2051         {
2052                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2053                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2054         },
2055         {
2056                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2057                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2058         },
2059         {
2060                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2061                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2062         },
2063         {
2064                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2065                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2066         },
2067         {
2068                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2069                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2070         },
2071         {
2072                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2073                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2074         },
2075         {
2076                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2077                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2078         },
2079         {
2080                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2081                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2082         },
2083         {
2084                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2085                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2086         },
2087         {
2088                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2089                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2090         },
2091         {
2092                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2093                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2094         },
2095         {
2096                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2097                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2098         },
2099         {
2100                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2101                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2102         },
2103         {
2104                 .vendor_id = 0
2105         }
2106 };
2107
2108 struct rte_pci_driver mlx5_driver = {
2109         .driver = {
2110                 .name = MLX5_DRIVER_NAME
2111         },
2112         .id_table = mlx5_pci_id_map,
2113         .probe = mlx5_os_pci_probe,
2114         .remove = mlx5_pci_remove,
2115         .dma_map = mlx5_dma_map,
2116         .dma_unmap = mlx5_dma_unmap,
2117         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
2118                      RTE_PCI_DRV_PROBE_AGAIN,
2119 };
2120
2121 /**
2122  * Driver initialization routine.
2123  */
2124 RTE_INIT(rte_mlx5_pmd_init)
2125 {
2126         /* Initialize driver log type. */
2127         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2128         if (mlx5_logtype >= 0)
2129                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2130
2131         /* Build the static tables for Verbs conversion. */
2132         mlx5_set_ptype_table();
2133         mlx5_set_cksum_table();
2134         mlx5_set_swp_types_table();
2135         if (mlx5_glue)
2136                 rte_pci_register(&mlx5_driver);
2137 }
2138
2139 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2140 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2141 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");