1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <ethdev_driver.h>
15 #include <ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
40 #include "mlx5_autoconf.h"
42 #include "mlx5_flow.h"
43 #include "mlx5_flow_os.h"
44 #include "rte_pmd_mlx5.h"
46 /* Device parameter to enable RX completion queue compression. */
47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
49 /* Device parameter to enable padding Rx packet to cacheline size. */
50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
52 /* Device parameter to enable Multi-Packet Rx queue. */
53 #define MLX5_RX_MPRQ_EN "mprq_en"
55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
67 /* Device parameter to configure inline send. Deprecated, ignored.*/
68 #define MLX5_TXQ_INLINE "txq_inline"
70 /* Device parameter to limit packet size to inline with ordinary SEND. */
71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
73 /* Device parameter to configure minimal data size to inline. */
74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
80 * Device parameter to configure the number of TX queues threshold for
81 * enabling inline send.
83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
86 * Device parameter to configure the number of TX queues threshold for
87 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
91 /* Device parameter to enable multi-packet send WQEs. */
92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
95 * Device parameter to force doorbell register mapping
96 * to non-cahed region eliminating the extra write memory barrier.
98 #define MLX5_TX_DB_NC "tx_db_nc"
101 * Device parameter to include 2 dsegs in the title WQEBB.
102 * Deprecated, ignored.
104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
107 * Device parameter to limit the size of inlining packet.
108 * Deprecated, ignored.
110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
113 * Device parameter to enable Tx scheduling on timestamps
114 * and specify the packet pacing granularity in nanoseconds.
116 #define MLX5_TX_PP "tx_pp"
119 * Device parameter to specify skew in nanoseconds on Tx datapath,
120 * it represents the time between SQ start WQE processing and
121 * appearing actual packet data on the wire.
123 #define MLX5_TX_SKEW "tx_skew"
126 * Device parameter to enable hardware Tx vector.
127 * Deprecated, ignored (no vectorized Tx routines anymore).
129 #define MLX5_TX_VEC_EN "tx_vec_en"
131 /* Device parameter to enable hardware Rx vector. */
132 #define MLX5_RX_VEC_EN "rx_vec_en"
134 /* Allow L3 VXLAN flow creation. */
135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
137 /* Activate DV E-Switch flow steering. */
138 #define MLX5_DV_ESW_EN "dv_esw_en"
140 /* Activate DV flow steering. */
141 #define MLX5_DV_FLOW_EN "dv_flow_en"
143 /* Enable extensive flow metadata support. */
144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
146 /* Device parameter to let the user manage the lacp traffic of bonded device */
147 #define MLX5_LACP_BY_USER "lacp_by_user"
149 /* Activate Netlink support in VF mode. */
150 #define MLX5_VF_NL_EN "vf_nl_en"
152 /* Enable extending memsegs when creating a MR. */
153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
155 /* Select port representors to instantiate. */
156 #define MLX5_REPRESENTOR "representor"
158 /* Device parameter to configure the maximum number of dump files per queue. */
159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
161 /* Configure timeout of LRO session (in microseconds). */
162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
165 * Device parameter to configure the total data buffer size for a single
166 * hairpin queue (logarithm value).
168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
170 /* Flow memory reclaim mode. */
171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
173 /* The default memory allocator used in PMD. */
174 #define MLX5_SYS_MEM_EN "sys_mem_en"
175 /* Decap will be used or not. */
176 #define MLX5_DECAP_EN "decap_en"
178 /* Shared memory between primary and secondary processes. */
179 struct mlx5_shared_data *mlx5_shared_data;
181 /** Driver-specific log messages type. */
184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
185 LIST_HEAD_INITIALIZER();
186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
189 [MLX5_IPOOL_DECAP_ENCAP] = {
190 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
196 .malloc = mlx5_malloc,
198 .type = "mlx5_encap_decap_ipool",
200 [MLX5_IPOOL_PUSH_VLAN] = {
201 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
207 .malloc = mlx5_malloc,
209 .type = "mlx5_push_vlan_ipool",
212 .size = sizeof(struct mlx5_flow_dv_tag_resource),
218 .malloc = mlx5_malloc,
220 .type = "mlx5_tag_ipool",
222 [MLX5_IPOOL_PORT_ID] = {
223 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
229 .malloc = mlx5_malloc,
231 .type = "mlx5_port_id_ipool",
233 [MLX5_IPOOL_JUMP] = {
234 .size = sizeof(struct mlx5_flow_tbl_data_entry),
240 .malloc = mlx5_malloc,
242 .type = "mlx5_jump_ipool",
244 [MLX5_IPOOL_SAMPLE] = {
245 .size = sizeof(struct mlx5_flow_dv_sample_resource),
251 .malloc = mlx5_malloc,
253 .type = "mlx5_sample_ipool",
255 [MLX5_IPOOL_DEST_ARRAY] = {
256 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
262 .malloc = mlx5_malloc,
264 .type = "mlx5_dest_array_ipool",
266 [MLX5_IPOOL_TUNNEL_ID] = {
267 .size = sizeof(struct mlx5_flow_tunnel),
268 .trunk_size = MLX5_MAX_TUNNELS,
271 .type = "mlx5_tunnel_offload",
273 [MLX5_IPOOL_TNL_TBL_ID] = {
276 .type = "mlx5_flow_tnl_tbl_ipool",
280 .size = sizeof(struct mlx5_flow_meter),
286 .malloc = mlx5_malloc,
288 .type = "mlx5_meter_ipool",
291 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
297 .malloc = mlx5_malloc,
299 .type = "mlx5_mcp_ipool",
301 [MLX5_IPOOL_HRXQ] = {
302 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
308 .malloc = mlx5_malloc,
310 .type = "mlx5_hrxq_ipool",
312 [MLX5_IPOOL_MLX5_FLOW] = {
314 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
315 * It set in run time according to PCI function configuration.
323 .malloc = mlx5_malloc,
325 .type = "mlx5_flow_handle_ipool",
327 [MLX5_IPOOL_RTE_FLOW] = {
328 .size = sizeof(struct rte_flow),
332 .malloc = mlx5_malloc,
334 .type = "rte_flow_ipool",
336 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
339 .type = "mlx5_flow_rss_id_ipool",
341 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
342 .size = sizeof(struct mlx5_shared_action_rss),
348 .malloc = mlx5_malloc,
350 .type = "mlx5_shared_action_rss",
355 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
356 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
358 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
361 * Decide whether representor ID is a HPF(host PF) port on BF2.
364 * Pointer to Ethernet device structure.
367 * Non-zero if HPF, otherwise 0.
370 mlx5_is_hpf(struct rte_eth_dev *dev)
372 struct mlx5_priv *priv = dev->data->dev_private;
373 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
374 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
376 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
377 MLX5_REPRESENTOR_REPR(-1) == repr;
381 * Initialize the ASO aging management structure.
384 * Pointer to mlx5_dev_ctx_shared object to free
387 * 0 on success, a negative errno value otherwise and rte_errno is set.
390 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
396 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
397 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
398 if (!sh->aso_age_mng) {
399 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
403 err = mlx5_aso_queue_init(sh);
405 mlx5_free(sh->aso_age_mng);
408 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
409 rte_spinlock_init(&sh->aso_age_mng->free_sl);
410 LIST_INIT(&sh->aso_age_mng->free);
415 * Close and release all the resources of the ASO aging management structure.
418 * Pointer to mlx5_dev_ctx_shared object to free.
421 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
425 mlx5_aso_queue_stop(sh);
426 mlx5_aso_queue_uninit(sh);
427 if (sh->aso_age_mng->pools) {
428 struct mlx5_aso_age_pool *pool;
430 for (i = 0; i < sh->aso_age_mng->next; ++i) {
431 pool = sh->aso_age_mng->pools[i];
432 claim_zero(mlx5_devx_cmd_destroy
433 (pool->flow_hit_aso_obj));
434 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
435 if (pool->actions[j].dr_action)
437 (mlx5_flow_os_destroy_flow_action
438 (pool->actions[j].dr_action));
441 mlx5_free(sh->aso_age_mng->pools);
443 mlx5_free(sh->aso_age_mng);
447 * Initialize the shared aging list information per port.
450 * Pointer to mlx5_dev_ctx_shared object.
453 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
456 struct mlx5_age_info *age_info;
458 for (i = 0; i < sh->max_port; i++) {
459 age_info = &sh->port[i].age_info;
461 TAILQ_INIT(&age_info->aged_counters);
462 LIST_INIT(&age_info->aged_aso);
463 rte_spinlock_init(&age_info->aged_sl);
464 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
469 * Initialize the counters management structure.
472 * Pointer to mlx5_dev_ctx_shared object to free
475 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
479 memset(&sh->cmng, 0, sizeof(sh->cmng));
480 TAILQ_INIT(&sh->cmng.flow_counters);
481 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
482 sh->cmng.max_id = -1;
483 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
484 rte_spinlock_init(&sh->cmng.pool_update_sl);
485 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
486 TAILQ_INIT(&sh->cmng.counters[i]);
487 rte_spinlock_init(&sh->cmng.csl[i]);
492 * Destroy all the resources allocated for a counter memory management.
495 * Pointer to the memory management structure.
498 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
500 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
502 LIST_REMOVE(mng, next);
503 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
504 claim_zero(mlx5_os_umem_dereg(mng->umem));
509 * Close and release all the resources of the counters management.
512 * Pointer to mlx5_dev_ctx_shared object to free.
515 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
517 struct mlx5_counter_stats_mem_mng *mng;
523 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
524 if (rte_errno != EINPROGRESS)
529 if (sh->cmng.pools) {
530 struct mlx5_flow_counter_pool *pool;
531 uint16_t n_valid = sh->cmng.n_valid;
532 bool fallback = sh->cmng.counter_fallback;
534 for (i = 0; i < n_valid; ++i) {
535 pool = sh->cmng.pools[i];
536 if (!fallback && pool->min_dcs)
537 claim_zero(mlx5_devx_cmd_destroy
539 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
540 struct mlx5_flow_counter *cnt =
541 MLX5_POOL_GET_CNT(pool, j);
545 (mlx5_flow_os_destroy_flow_action
547 if (fallback && MLX5_POOL_GET_CNT
548 (pool, j)->dcs_when_free)
549 claim_zero(mlx5_devx_cmd_destroy
550 (cnt->dcs_when_free));
554 mlx5_free(sh->cmng.pools);
556 mng = LIST_FIRST(&sh->cmng.mem_mngs);
558 mlx5_flow_destroy_counter_stat_mem_mng(mng);
559 mng = LIST_FIRST(&sh->cmng.mem_mngs);
561 memset(&sh->cmng, 0, sizeof(sh->cmng));
564 /* Send FLOW_AGED event if needed. */
566 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
568 struct mlx5_age_info *age_info;
571 for (i = 0; i < sh->max_port; i++) {
572 age_info = &sh->port[i].age_info;
573 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
575 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
576 rte_eth_dev_callback_process
577 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
578 RTE_ETH_EVENT_FLOW_AGED, NULL);
584 * Initialize the flow resources' indexed mempool.
587 * Pointer to mlx5_dev_ctx_shared object.
589 * Pointer to user dev config.
592 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
593 const struct mlx5_dev_config *config)
596 struct mlx5_indexed_pool_config cfg;
598 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
599 cfg = mlx5_ipool_cfg[i];
604 * Set MLX5_IPOOL_MLX5_FLOW ipool size
605 * according to PCI function flow configuration.
607 case MLX5_IPOOL_MLX5_FLOW:
608 cfg.size = config->dv_flow_en ?
609 sizeof(struct mlx5_flow_handle) :
610 MLX5_FLOW_HANDLE_VERBS_SIZE;
613 if (config->reclaim_mode)
614 cfg.release_mem_en = 1;
615 sh->ipool[i] = mlx5_ipool_create(&cfg);
620 * Release the flow resources' indexed mempool.
623 * Pointer to mlx5_dev_ctx_shared object.
626 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
630 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
631 mlx5_ipool_destroy(sh->ipool[i]);
635 * Check if dynamic flex parser for eCPRI already exists.
638 * Pointer to Ethernet device structure.
641 * true on exists, false on not.
644 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
646 struct mlx5_priv *priv = dev->data->dev_private;
647 struct mlx5_flex_parser_profiles *prf =
648 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
654 * Allocation of a flex parser for eCPRI. Once created, this parser related
655 * resources will be held until the device is closed.
658 * Pointer to Ethernet device structure.
661 * 0 on success, a negative errno value otherwise and rte_errno is set.
664 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
666 struct mlx5_priv *priv = dev->data->dev_private;
667 struct mlx5_flex_parser_profiles *prf =
668 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
669 struct mlx5_devx_graph_node_attr node = {
670 .modify_field_select = 0,
675 if (!priv->config.hca_attr.parse_graph_flex_node) {
676 DRV_LOG(ERR, "Dynamic flex parser is not supported "
677 "for device %s.", priv->dev_data->name);
680 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
681 /* 8 bytes now: 4B common header + 4B message body header. */
682 node.header_length_base_value = 0x8;
683 /* After MAC layer: Ether / VLAN. */
684 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
685 /* Type of compared condition should be 0xAEFE in the L2 layer. */
686 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
687 /* Sample #0: type in common header. */
688 node.sample[0].flow_match_sample_en = 1;
690 node.sample[0].flow_match_sample_offset_mode = 0x0;
691 /* Only the 2nd byte will be used. */
692 node.sample[0].flow_match_sample_field_base_offset = 0x0;
693 /* Sample #1: message payload. */
694 node.sample[1].flow_match_sample_en = 1;
696 node.sample[1].flow_match_sample_offset_mode = 0x0;
698 * Only the first two bytes will be used right now, and its offset will
699 * start after the common header that with the length of a DW(u32).
701 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
702 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
704 DRV_LOG(ERR, "Failed to create flex parser node object.");
705 return (rte_errno == 0) ? -ENODEV : -rte_errno;
708 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
710 DRV_LOG(ERR, "Failed to query sample IDs.");
711 return (rte_errno == 0) ? -ENODEV : -rte_errno;
713 prf->offset[0] = 0x0;
714 prf->offset[1] = sizeof(uint32_t);
715 prf->ids[0] = ids[0];
716 prf->ids[1] = ids[1];
721 * Destroy the flex parser node, including the parser itself, input / output
722 * arcs and DW samples. Resources could be reused then.
725 * Pointer to Ethernet device structure.
728 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
730 struct mlx5_priv *priv = dev->data->dev_private;
731 struct mlx5_flex_parser_profiles *prf =
732 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
735 mlx5_devx_cmd_destroy(prf->obj);
740 * Allocate Rx and Tx UARs in robust fashion.
741 * This routine handles the following UAR allocation issues:
743 * - tries to allocate the UAR with the most appropriate memory
744 * mapping type from the ones supported by the host
746 * - tries to allocate the UAR with non-NULL base address
747 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
748 * UAR base address if UAR was not the first object in the UAR page.
749 * It caused the PMD failure and we should try to get another UAR
750 * till we get the first one with non-NULL base address returned.
753 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
754 const struct mlx5_dev_config *config)
756 uint32_t uar_mapping, retry;
760 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
761 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
762 /* Control the mapping type according to the settings. */
763 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
764 MLX5DV_UAR_ALLOC_TYPE_NC :
765 MLX5DV_UAR_ALLOC_TYPE_BF;
767 RTE_SET_USED(config);
769 * It seems we have no way to control the memory mapping type
770 * for the UAR, the default "Write-Combining" type is supposed.
771 * The UAR initialization on queue creation queries the
772 * actual mapping type done by Verbs/kernel and setups the
773 * PMD datapath accordingly.
777 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
778 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
780 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
781 if (config->dbnc == MLX5_TXDB_CACHED ||
782 config->dbnc == MLX5_TXDB_HEURISTIC)
783 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
784 "is not supported by DevX");
786 * In some environments like virtual machine
787 * the Write Combining mapped might be not supported
788 * and UAR allocation fails. We try "Non-Cached"
789 * mapping for the case. The tx_burst routines take
790 * the UAR mapping type into account on UAR setup
793 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
794 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
795 sh->tx_uar = mlx5_glue->devx_alloc_uar
796 (sh->ctx, uar_mapping);
797 } else if (!sh->tx_uar &&
798 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
799 if (config->dbnc == MLX5_TXDB_NCACHED)
800 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
801 "is not supported by DevX");
803 * If Verbs/kernel does not support "Non-Cached"
804 * try the "Write-Combining".
806 DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
807 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
808 sh->tx_uar = mlx5_glue->devx_alloc_uar
809 (sh->ctx, uar_mapping);
813 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
817 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
821 * The UARs are allocated by rdma_core within the
822 * IB device context, on context closure all UARs
823 * will be freed, should be no memory/object leakage.
825 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
828 /* Check whether we finally succeeded with valid UAR allocation. */
830 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
834 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
836 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
837 (sh->ctx, uar_mapping);
838 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
839 if (!sh->devx_rx_uar &&
840 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
842 * Rx UAR is used to control interrupts only,
843 * should be no datapath noticeable impact,
844 * can try "Non-Cached" mapping safely.
846 DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
847 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
848 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
849 (sh->ctx, uar_mapping);
852 if (!sh->devx_rx_uar) {
853 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
857 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
861 * The UARs are allocated by rdma_core within the
862 * IB device context, on context closure all UARs
863 * will be freed, should be no memory/object leakage.
865 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
866 sh->devx_rx_uar = NULL;
868 /* Check whether we finally succeeded with valid UAR allocation. */
869 if (!sh->devx_rx_uar) {
870 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
878 * Allocate shared device context. If there is multiport device the
879 * master and representors will share this context, if there is single
880 * port dedicated device, the context will be used by only given
881 * port due to unification.
883 * Routine first searches the context for the specified device name,
884 * if found the shared context assumed and reference counter is incremented.
885 * If no context found the new one is created and initialized with specified
886 * device context and parameters.
889 * Pointer to the device attributes (name, port, etc).
891 * Pointer to device configuration structure.
894 * Pointer to mlx5_dev_ctx_shared object on success,
895 * otherwise NULL and rte_errno is set.
897 struct mlx5_dev_ctx_shared *
898 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
899 const struct mlx5_dev_config *config)
901 struct mlx5_dev_ctx_shared *sh;
904 struct mlx5_devx_tis_attr tis_attr = { 0 };
907 /* Secondary process should not create the shared context. */
908 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
909 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
910 /* Search for IB context by device name. */
911 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
912 if (!strcmp(sh->ibdev_name,
913 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
918 /* No device found, we have to create new shared context. */
919 MLX5_ASSERT(spawn->max_port);
920 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
921 sizeof(struct mlx5_dev_ctx_shared) +
923 sizeof(struct mlx5_dev_shared_port),
924 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
926 DRV_LOG(ERR, "shared context allocation failure");
930 if (spawn->bond_info)
931 sh->bond = *spawn->bond_info;
932 err = mlx5_os_open_device(spawn, config, sh);
935 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
937 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
941 sh->max_port = spawn->max_port;
942 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
943 sizeof(sh->ibdev_name) - 1);
944 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
945 sizeof(sh->ibdev_path) - 1);
947 * Setting port_id to max unallowed value means
948 * there is no interrupt subhandler installed for
949 * the given port index i.
951 for (i = 0; i < sh->max_port; i++) {
952 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
953 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
955 sh->pd = mlx5_os_alloc_pd(sh->ctx);
956 if (sh->pd == NULL) {
957 DRV_LOG(ERR, "PD allocation failure");
962 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
964 DRV_LOG(ERR, "Fail to extract pdn from PD");
967 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
969 DRV_LOG(ERR, "TD allocation failure");
973 tis_attr.transport_domain = sh->td->id;
974 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
976 DRV_LOG(ERR, "TIS allocation failure");
980 err = mlx5_alloc_rxtx_uars(sh, config);
983 MLX5_ASSERT(sh->tx_uar);
984 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
986 MLX5_ASSERT(sh->devx_rx_uar);
987 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
990 /* Initialize UAR access locks for 32bit implementations. */
991 rte_spinlock_init(&sh->uar_lock_cq);
992 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
993 rte_spinlock_init(&sh->uar_lock[i]);
996 * Once the device is added to the list of memory event
997 * callback, its global MR cache table cannot be expanded
998 * on the fly because of deadlock. If it overflows, lookup
999 * should be done by searching MR list linearly, which is slow.
1001 * At this point the device is not added to the memory
1002 * event list yet, context is just being created.
1004 err = mlx5_mr_btree_init(&sh->share_cache.cache,
1005 MLX5_MR_BTREE_CACHE_N * 2,
1006 spawn->pci_dev->device.numa_node);
1011 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1012 &sh->share_cache.dereg_mr_cb);
1013 mlx5_os_dev_shared_handler_install(sh);
1014 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1015 if (!sh->cnt_id_tbl) {
1019 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1020 err = mlx5_flow_os_init_workspace_once();
1024 mlx5_flow_aging_init(sh);
1025 mlx5_flow_counters_mng_init(sh);
1026 mlx5_flow_ipool_create(sh, config);
1027 /* Add device to memory callback list. */
1028 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1029 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1031 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1032 /* Add context to the global device list. */
1033 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1034 rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1036 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1039 pthread_mutex_destroy(&sh->txpp.mutex);
1040 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1043 mlx5_l3t_destroy(sh->cnt_id_tbl);
1045 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1047 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1048 if (sh->devx_rx_uar)
1049 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1051 mlx5_glue->devx_free_uar(sh->tx_uar);
1053 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1055 claim_zero(mlx5_glue->close_device(sh->ctx));
1057 MLX5_ASSERT(err > 0);
1063 * Free shared IB device context. Decrement counter and if zero free
1064 * all allocated resources and close handles.
1067 * Pointer to mlx5_dev_ctx_shared object to free
1070 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1072 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1073 #ifdef RTE_LIBRTE_MLX5_DEBUG
1074 /* Check the object presence in the list. */
1075 struct mlx5_dev_ctx_shared *lctx;
1077 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1082 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1087 MLX5_ASSERT(sh->refcnt);
1088 /* Secondary process should not free the shared context. */
1089 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1092 /* Remove from memory callback device list. */
1093 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1094 LIST_REMOVE(sh, mem_event_cb);
1095 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1096 /* Release created Memory Regions. */
1097 mlx5_mr_release_cache(&sh->share_cache);
1098 /* Remove context from the global device list. */
1099 LIST_REMOVE(sh, next);
1100 /* Release flow workspaces objects on the last device. */
1101 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1102 mlx5_flow_os_release_workspace();
1103 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1105 * Ensure there is no async event handler installed.
1106 * Only primary process handles async device events.
1108 mlx5_flow_counters_mng_close(sh);
1109 if (sh->aso_age_mng) {
1110 mlx5_flow_aso_age_mng_close(sh);
1111 sh->aso_age_mng = NULL;
1113 mlx5_flow_ipool_destroy(sh);
1114 mlx5_os_dev_shared_handler_uninstall(sh);
1115 if (sh->cnt_id_tbl) {
1116 mlx5_l3t_destroy(sh->cnt_id_tbl);
1117 sh->cnt_id_tbl = NULL;
1120 mlx5_glue->devx_free_uar(sh->tx_uar);
1124 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1126 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1128 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1129 if (sh->devx_rx_uar)
1130 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1132 claim_zero(mlx5_glue->close_device(sh->ctx));
1133 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1134 pthread_mutex_destroy(&sh->txpp.mutex);
1138 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1142 * Destroy table hash list.
1145 * Pointer to the private device data structure.
1148 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1150 struct mlx5_dev_ctx_shared *sh = priv->sh;
1154 mlx5_hlist_destroy(sh->flow_tbls);
1158 * Initialize flow table hash list and create the root tables entry
1162 * Pointer to the private device data structure.
1165 * Zero on success, positive error code otherwise.
1168 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1171 /* Tables are only used in DV and DR modes. */
1172 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1173 struct mlx5_dev_ctx_shared *sh = priv->sh;
1174 char s[MLX5_HLIST_NAMESIZE];
1177 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1178 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1179 0, 0, flow_dv_tbl_create_cb,
1180 flow_dv_tbl_match_cb,
1181 flow_dv_tbl_remove_cb);
1182 if (!sh->flow_tbls) {
1183 DRV_LOG(ERR, "flow tables with hash creation failed.");
1187 sh->flow_tbls->ctx = sh;
1188 #ifndef HAVE_MLX5DV_DR
1189 struct rte_flow_error error;
1190 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1193 * In case we have not DR support, the zero tables should be created
1194 * because DV expect to see them even if they cannot be created by
1197 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1198 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1199 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1205 mlx5_free_table_hash_list(priv);
1206 #endif /* HAVE_MLX5DV_DR */
1212 * Retrieve integer value from environment variable.
1215 * Environment variable name.
1218 * Integer value, 0 if the variable is not set.
1221 mlx5_getenv_int(const char *name)
1223 const char *val = getenv(name);
1231 * DPDK callback to add udp tunnel port
1234 * A pointer to eth_dev
1235 * @param[in] udp_tunnel
1236 * A pointer to udp tunnel
1239 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1242 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1243 struct rte_eth_udp_tunnel *udp_tunnel)
1245 MLX5_ASSERT(udp_tunnel != NULL);
1246 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1247 udp_tunnel->udp_port == 4789)
1249 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1250 udp_tunnel->udp_port == 4790)
1256 * Initialize process private data structure.
1259 * Pointer to Ethernet device structure.
1262 * 0 on success, a negative errno value otherwise and rte_errno is set.
1265 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1267 struct mlx5_priv *priv = dev->data->dev_private;
1268 struct mlx5_proc_priv *ppriv;
1272 * UAR register table follows the process private structure. BlueFlame
1273 * registers for Tx queues are stored in the table.
1276 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1277 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1278 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1283 ppriv->uar_table_sz = priv->txqs_n;
1284 dev->process_private = ppriv;
1289 * Un-initialize process private data structure.
1292 * Pointer to Ethernet device structure.
1295 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1297 if (!dev->process_private)
1299 mlx5_free(dev->process_private);
1300 dev->process_private = NULL;
1304 * DPDK callback to close the device.
1306 * Destroy all queues and objects, free memory.
1309 * Pointer to Ethernet device structure.
1312 mlx5_dev_close(struct rte_eth_dev *dev)
1314 struct mlx5_priv *priv = dev->data->dev_private;
1318 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1319 /* Check if process_private released. */
1320 if (!dev->process_private)
1322 mlx5_tx_uar_uninit_secondary(dev);
1323 mlx5_proc_priv_uninit(dev);
1324 rte_eth_dev_release_port(dev);
1329 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1331 ((priv->sh->ctx != NULL) ?
1332 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1334 * If default mreg copy action is removed at the stop stage,
1335 * the search will return none and nothing will be done anymore.
1337 mlx5_flow_stop_default(dev);
1338 mlx5_traffic_disable(dev);
1340 * If all the flows are already flushed in the device stop stage,
1341 * then this will return directly without any action.
1343 mlx5_flow_list_flush(dev, &priv->flows, true);
1344 mlx5_action_handle_flush(dev);
1345 mlx5_flow_meter_flush(dev, NULL);
1346 /* Prevent crashes when queues are still in use. */
1347 dev->rx_pkt_burst = removed_rx_burst;
1348 dev->tx_pkt_burst = removed_tx_burst;
1350 /* Disable datapath on secondary process. */
1351 mlx5_mp_os_req_stop_rxtx(dev);
1352 /* Free the eCPRI flex parser resource. */
1353 mlx5_flex_parser_ecpri_release(dev);
1354 if (priv->rxqs != NULL) {
1355 /* XXX race condition if mlx5_rx_burst() is still running. */
1356 rte_delay_us_sleep(1000);
1357 for (i = 0; (i != priv->rxqs_n); ++i)
1358 mlx5_rxq_release(dev, i);
1362 if (priv->txqs != NULL) {
1363 /* XXX race condition if mlx5_tx_burst() is still running. */
1364 rte_delay_us_sleep(1000);
1365 for (i = 0; (i != priv->txqs_n); ++i)
1366 mlx5_txq_release(dev, i);
1370 mlx5_proc_priv_uninit(dev);
1371 if (priv->q_counters) {
1372 mlx5_devx_cmd_destroy(priv->q_counters);
1373 priv->q_counters = NULL;
1375 if (priv->drop_queue.hrxq)
1376 mlx5_drop_action_destroy(dev);
1377 if (priv->mreg_cp_tbl)
1378 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1379 mlx5_mprq_free_mp(dev);
1380 mlx5_os_free_shared_dr(priv);
1381 if (priv->rss_conf.rss_key != NULL)
1382 mlx5_free(priv->rss_conf.rss_key);
1383 if (priv->reta_idx != NULL)
1384 mlx5_free(priv->reta_idx);
1385 if (priv->config.vf)
1386 mlx5_os_mac_addr_flush(dev);
1387 if (priv->nl_socket_route >= 0)
1388 close(priv->nl_socket_route);
1389 if (priv->nl_socket_rdma >= 0)
1390 close(priv->nl_socket_rdma);
1391 if (priv->vmwa_context)
1392 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1393 ret = mlx5_hrxq_verify(dev);
1395 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1396 dev->data->port_id);
1397 ret = mlx5_ind_table_obj_verify(dev);
1399 DRV_LOG(WARNING, "port %u some indirection table still remain",
1400 dev->data->port_id);
1401 ret = mlx5_rxq_obj_verify(dev);
1403 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1404 dev->data->port_id);
1405 ret = mlx5_rxq_verify(dev);
1407 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1408 dev->data->port_id);
1409 ret = mlx5_txq_obj_verify(dev);
1411 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1412 dev->data->port_id);
1413 ret = mlx5_txq_verify(dev);
1415 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1416 dev->data->port_id);
1417 ret = mlx5_flow_verify(dev);
1419 DRV_LOG(WARNING, "port %u some flows still remain",
1420 dev->data->port_id);
1421 mlx5_cache_list_destroy(&priv->hrxqs);
1423 * Free the shared context in last turn, because the cleanup
1424 * routines above may use some shared fields, like
1425 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1426 * ifindex if Netlink fails.
1428 mlx5_free_shared_dev_ctx(priv->sh);
1429 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1433 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1434 struct mlx5_priv *opriv =
1435 rte_eth_devices[port_id].data->dev_private;
1438 opriv->domain_id != priv->domain_id ||
1439 &rte_eth_devices[port_id] == dev)
1445 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1447 memset(priv, 0, sizeof(*priv));
1448 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1450 * Reset mac_addrs to NULL such that it is not freed as part of
1451 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1452 * it is freed when dev_private is freed.
1454 dev->data->mac_addrs = NULL;
1458 const struct eth_dev_ops mlx5_dev_ops = {
1459 .dev_configure = mlx5_dev_configure,
1460 .dev_start = mlx5_dev_start,
1461 .dev_stop = mlx5_dev_stop,
1462 .dev_set_link_down = mlx5_set_link_down,
1463 .dev_set_link_up = mlx5_set_link_up,
1464 .dev_close = mlx5_dev_close,
1465 .promiscuous_enable = mlx5_promiscuous_enable,
1466 .promiscuous_disable = mlx5_promiscuous_disable,
1467 .allmulticast_enable = mlx5_allmulticast_enable,
1468 .allmulticast_disable = mlx5_allmulticast_disable,
1469 .link_update = mlx5_link_update,
1470 .stats_get = mlx5_stats_get,
1471 .stats_reset = mlx5_stats_reset,
1472 .xstats_get = mlx5_xstats_get,
1473 .xstats_reset = mlx5_xstats_reset,
1474 .xstats_get_names = mlx5_xstats_get_names,
1475 .fw_version_get = mlx5_fw_version_get,
1476 .dev_infos_get = mlx5_dev_infos_get,
1477 .representor_info_get = mlx5_representor_info_get,
1478 .read_clock = mlx5_txpp_read_clock,
1479 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1480 .vlan_filter_set = mlx5_vlan_filter_set,
1481 .rx_queue_setup = mlx5_rx_queue_setup,
1482 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1483 .tx_queue_setup = mlx5_tx_queue_setup,
1484 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1485 .rx_queue_release = mlx5_rx_queue_release,
1486 .tx_queue_release = mlx5_tx_queue_release,
1487 .rx_queue_start = mlx5_rx_queue_start,
1488 .rx_queue_stop = mlx5_rx_queue_stop,
1489 .tx_queue_start = mlx5_tx_queue_start,
1490 .tx_queue_stop = mlx5_tx_queue_stop,
1491 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1492 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1493 .mac_addr_remove = mlx5_mac_addr_remove,
1494 .mac_addr_add = mlx5_mac_addr_add,
1495 .mac_addr_set = mlx5_mac_addr_set,
1496 .set_mc_addr_list = mlx5_set_mc_addr_list,
1497 .mtu_set = mlx5_dev_set_mtu,
1498 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1499 .vlan_offload_set = mlx5_vlan_offload_set,
1500 .reta_update = mlx5_dev_rss_reta_update,
1501 .reta_query = mlx5_dev_rss_reta_query,
1502 .rss_hash_update = mlx5_rss_hash_update,
1503 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1504 .flow_ops_get = mlx5_flow_ops_get,
1505 .rxq_info_get = mlx5_rxq_info_get,
1506 .txq_info_get = mlx5_txq_info_get,
1507 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1508 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1509 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1510 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1511 .is_removed = mlx5_is_removed,
1512 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1513 .get_module_info = mlx5_get_module_info,
1514 .get_module_eeprom = mlx5_get_module_eeprom,
1515 .hairpin_cap_get = mlx5_hairpin_cap_get,
1516 .mtr_ops_get = mlx5_flow_meter_ops_get,
1517 .hairpin_bind = mlx5_hairpin_bind,
1518 .hairpin_unbind = mlx5_hairpin_unbind,
1519 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1520 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1521 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1522 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1525 /* Available operations from secondary process. */
1526 const struct eth_dev_ops mlx5_dev_sec_ops = {
1527 .stats_get = mlx5_stats_get,
1528 .stats_reset = mlx5_stats_reset,
1529 .xstats_get = mlx5_xstats_get,
1530 .xstats_reset = mlx5_xstats_reset,
1531 .xstats_get_names = mlx5_xstats_get_names,
1532 .fw_version_get = mlx5_fw_version_get,
1533 .dev_infos_get = mlx5_dev_infos_get,
1534 .read_clock = mlx5_txpp_read_clock,
1535 .rx_queue_start = mlx5_rx_queue_start,
1536 .rx_queue_stop = mlx5_rx_queue_stop,
1537 .tx_queue_start = mlx5_tx_queue_start,
1538 .tx_queue_stop = mlx5_tx_queue_stop,
1539 .rxq_info_get = mlx5_rxq_info_get,
1540 .txq_info_get = mlx5_txq_info_get,
1541 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1542 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1543 .get_module_info = mlx5_get_module_info,
1544 .get_module_eeprom = mlx5_get_module_eeprom,
1547 /* Available operations in flow isolated mode. */
1548 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1549 .dev_configure = mlx5_dev_configure,
1550 .dev_start = mlx5_dev_start,
1551 .dev_stop = mlx5_dev_stop,
1552 .dev_set_link_down = mlx5_set_link_down,
1553 .dev_set_link_up = mlx5_set_link_up,
1554 .dev_close = mlx5_dev_close,
1555 .promiscuous_enable = mlx5_promiscuous_enable,
1556 .promiscuous_disable = mlx5_promiscuous_disable,
1557 .allmulticast_enable = mlx5_allmulticast_enable,
1558 .allmulticast_disable = mlx5_allmulticast_disable,
1559 .link_update = mlx5_link_update,
1560 .stats_get = mlx5_stats_get,
1561 .stats_reset = mlx5_stats_reset,
1562 .xstats_get = mlx5_xstats_get,
1563 .xstats_reset = mlx5_xstats_reset,
1564 .xstats_get_names = mlx5_xstats_get_names,
1565 .fw_version_get = mlx5_fw_version_get,
1566 .dev_infos_get = mlx5_dev_infos_get,
1567 .read_clock = mlx5_txpp_read_clock,
1568 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1569 .vlan_filter_set = mlx5_vlan_filter_set,
1570 .rx_queue_setup = mlx5_rx_queue_setup,
1571 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1572 .tx_queue_setup = mlx5_tx_queue_setup,
1573 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1574 .rx_queue_release = mlx5_rx_queue_release,
1575 .tx_queue_release = mlx5_tx_queue_release,
1576 .rx_queue_start = mlx5_rx_queue_start,
1577 .rx_queue_stop = mlx5_rx_queue_stop,
1578 .tx_queue_start = mlx5_tx_queue_start,
1579 .tx_queue_stop = mlx5_tx_queue_stop,
1580 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1581 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1582 .mac_addr_remove = mlx5_mac_addr_remove,
1583 .mac_addr_add = mlx5_mac_addr_add,
1584 .mac_addr_set = mlx5_mac_addr_set,
1585 .set_mc_addr_list = mlx5_set_mc_addr_list,
1586 .mtu_set = mlx5_dev_set_mtu,
1587 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1588 .vlan_offload_set = mlx5_vlan_offload_set,
1589 .flow_ops_get = mlx5_flow_ops_get,
1590 .rxq_info_get = mlx5_rxq_info_get,
1591 .txq_info_get = mlx5_txq_info_get,
1592 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1593 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1594 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1595 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1596 .is_removed = mlx5_is_removed,
1597 .get_module_info = mlx5_get_module_info,
1598 .get_module_eeprom = mlx5_get_module_eeprom,
1599 .hairpin_cap_get = mlx5_hairpin_cap_get,
1600 .mtr_ops_get = mlx5_flow_meter_ops_get,
1601 .hairpin_bind = mlx5_hairpin_bind,
1602 .hairpin_unbind = mlx5_hairpin_unbind,
1603 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1604 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1605 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1606 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1610 * Verify and store value for device argument.
1613 * Key argument to verify.
1615 * Value associated with key.
1620 * 0 on success, a negative errno value otherwise and rte_errno is set.
1623 mlx5_args_check(const char *key, const char *val, void *opaque)
1625 struct mlx5_dev_config *config = opaque;
1629 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1630 if (!strcmp(MLX5_REPRESENTOR, key))
1633 tmp = strtol(val, NULL, 0);
1636 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1639 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1640 /* Negative values are acceptable for some keys only. */
1642 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1645 mod = tmp >= 0 ? tmp : -tmp;
1646 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1647 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1648 DRV_LOG(ERR, "invalid CQE compression "
1649 "format parameter");
1653 config->cqe_comp = !!tmp;
1654 config->cqe_comp_fmt = tmp;
1655 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1656 config->hw_padding = !!tmp;
1657 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1658 config->mprq.enabled = !!tmp;
1659 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1660 config->mprq.stride_num_n = tmp;
1661 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1662 config->mprq.stride_size_n = tmp;
1663 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1664 config->mprq.max_memcpy_len = tmp;
1665 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1666 config->mprq.min_rxqs_num = tmp;
1667 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1668 DRV_LOG(WARNING, "%s: deprecated parameter,"
1669 " converted to txq_inline_max", key);
1670 config->txq_inline_max = tmp;
1671 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1672 config->txq_inline_max = tmp;
1673 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1674 config->txq_inline_min = tmp;
1675 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1676 config->txq_inline_mpw = tmp;
1677 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1678 config->txqs_inline = tmp;
1679 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1680 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1681 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1682 config->mps = !!tmp;
1683 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1684 if (tmp != MLX5_TXDB_CACHED &&
1685 tmp != MLX5_TXDB_NCACHED &&
1686 tmp != MLX5_TXDB_HEURISTIC) {
1687 DRV_LOG(ERR, "invalid Tx doorbell "
1688 "mapping parameter");
1693 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1694 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1695 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1696 DRV_LOG(WARNING, "%s: deprecated parameter,"
1697 " converted to txq_inline_mpw", key);
1698 config->txq_inline_mpw = tmp;
1699 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1700 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1701 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1703 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1707 config->tx_pp = tmp;
1708 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1709 config->tx_skew = tmp;
1710 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1711 config->rx_vec_en = !!tmp;
1712 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1713 config->l3_vxlan_en = !!tmp;
1714 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1715 config->vf_nl_en = !!tmp;
1716 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1717 config->dv_esw_en = !!tmp;
1718 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1719 config->dv_flow_en = !!tmp;
1720 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1721 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1722 tmp != MLX5_XMETA_MODE_META16 &&
1723 tmp != MLX5_XMETA_MODE_META32 &&
1724 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1725 DRV_LOG(ERR, "invalid extensive "
1726 "metadata parameter");
1730 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1731 config->dv_xmeta_en = tmp;
1733 config->dv_miss_info = 1;
1734 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1735 config->lacp_by_user = !!tmp;
1736 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1737 config->mr_ext_memseg_en = !!tmp;
1738 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1739 config->max_dump_files_num = tmp;
1740 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1741 config->lro.timeout = tmp;
1742 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1743 DRV_LOG(DEBUG, "class argument is %s.", val);
1744 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1745 config->log_hp_size = tmp;
1746 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1747 if (tmp != MLX5_RCM_NONE &&
1748 tmp != MLX5_RCM_LIGHT &&
1749 tmp != MLX5_RCM_AGGR) {
1750 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1754 config->reclaim_mode = tmp;
1755 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1756 config->sys_mem_en = !!tmp;
1757 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1758 config->decap_en = !!tmp;
1760 DRV_LOG(WARNING, "%s: unknown parameter", key);
1768 * Parse device parameters.
1771 * Pointer to device configuration structure.
1773 * Device arguments structure.
1776 * 0 on success, a negative errno value otherwise and rte_errno is set.
1779 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1781 const char **params = (const char *[]){
1782 MLX5_RXQ_CQE_COMP_EN,
1783 MLX5_RXQ_PKT_PAD_EN,
1785 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1786 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1787 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1790 MLX5_TXQ_INLINE_MIN,
1791 MLX5_TXQ_INLINE_MAX,
1792 MLX5_TXQ_INLINE_MPW,
1793 MLX5_TXQS_MIN_INLINE,
1796 MLX5_TXQ_MPW_HDR_DSEG_EN,
1797 MLX5_TXQ_MAX_INLINE_LEN,
1809 MLX5_MR_EXT_MEMSEG_EN,
1811 MLX5_MAX_DUMP_FILES_NUM,
1812 MLX5_LRO_TIMEOUT_USEC,
1813 MLX5_CLASS_ARG_NAME,
1820 struct rte_kvargs *kvlist;
1824 if (devargs == NULL)
1826 /* Following UGLY cast is done to pass checkpatch. */
1827 kvlist = rte_kvargs_parse(devargs->args, params);
1828 if (kvlist == NULL) {
1832 /* Process parameters. */
1833 for (i = 0; (params[i] != NULL); ++i) {
1834 if (rte_kvargs_count(kvlist, params[i])) {
1835 ret = rte_kvargs_process(kvlist, params[i],
1836 mlx5_args_check, config);
1839 rte_kvargs_free(kvlist);
1844 rte_kvargs_free(kvlist);
1849 * Configures the minimal amount of data to inline into WQE
1850 * while sending packets.
1852 * - the txq_inline_min has the maximal priority, if this
1853 * key is specified in devargs
1854 * - if DevX is enabled the inline mode is queried from the
1855 * device (HCA attributes and NIC vport context if needed).
1856 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1857 * and none (0 bytes) for other NICs
1860 * Verbs device parameters (name, port, switch_info) to spawn.
1862 * Device configuration parameters.
1865 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1866 struct mlx5_dev_config *config)
1868 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1869 /* Application defines size of inlined data explicitly. */
1870 switch (spawn->pci_dev->id.device_id) {
1871 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1872 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1873 if (config->txq_inline_min <
1874 (int)MLX5_INLINE_HSIZE_L2) {
1876 "txq_inline_mix aligned to minimal"
1877 " ConnectX-4 required value %d",
1878 (int)MLX5_INLINE_HSIZE_L2);
1879 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1885 if (config->hca_attr.eth_net_offloads) {
1886 /* We have DevX enabled, inline mode queried successfully. */
1887 switch (config->hca_attr.wqe_inline_mode) {
1888 case MLX5_CAP_INLINE_MODE_L2:
1889 /* outer L2 header must be inlined. */
1890 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1892 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1893 /* No inline data are required by NIC. */
1894 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1895 config->hw_vlan_insert =
1896 config->hca_attr.wqe_vlan_insert;
1897 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1899 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1900 /* inline mode is defined by NIC vport context. */
1901 if (!config->hca_attr.eth_virt)
1903 switch (config->hca_attr.vport_inline_mode) {
1904 case MLX5_INLINE_MODE_NONE:
1905 config->txq_inline_min =
1906 MLX5_INLINE_HSIZE_NONE;
1908 case MLX5_INLINE_MODE_L2:
1909 config->txq_inline_min =
1910 MLX5_INLINE_HSIZE_L2;
1912 case MLX5_INLINE_MODE_IP:
1913 config->txq_inline_min =
1914 MLX5_INLINE_HSIZE_L3;
1916 case MLX5_INLINE_MODE_TCP_UDP:
1917 config->txq_inline_min =
1918 MLX5_INLINE_HSIZE_L4;
1920 case MLX5_INLINE_MODE_INNER_L2:
1921 config->txq_inline_min =
1922 MLX5_INLINE_HSIZE_INNER_L2;
1924 case MLX5_INLINE_MODE_INNER_IP:
1925 config->txq_inline_min =
1926 MLX5_INLINE_HSIZE_INNER_L3;
1928 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1929 config->txq_inline_min =
1930 MLX5_INLINE_HSIZE_INNER_L4;
1936 * We get here if we are unable to deduce
1937 * inline data size with DevX. Try PCI ID
1938 * to determine old NICs.
1940 switch (spawn->pci_dev->id.device_id) {
1941 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1942 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1943 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1944 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1945 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1946 config->hw_vlan_insert = 0;
1948 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1949 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1950 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1951 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1953 * These NICs support VLAN insertion from WQE and
1954 * report the wqe_vlan_insert flag. But there is the bug
1955 * and PFC control may be broken, so disable feature.
1957 config->hw_vlan_insert = 0;
1958 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1961 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1965 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1969 * Configures the metadata mask fields in the shared context.
1972 * Pointer to Ethernet device.
1975 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1977 struct mlx5_priv *priv = dev->data->dev_private;
1978 struct mlx5_dev_ctx_shared *sh = priv->sh;
1979 uint32_t meta, mark, reg_c0;
1981 reg_c0 = ~priv->vport_meta_mask;
1982 switch (priv->config.dv_xmeta_en) {
1983 case MLX5_XMETA_MODE_LEGACY:
1985 mark = MLX5_FLOW_MARK_MASK;
1987 case MLX5_XMETA_MODE_META16:
1988 meta = reg_c0 >> rte_bsf32(reg_c0);
1989 mark = MLX5_FLOW_MARK_MASK;
1991 case MLX5_XMETA_MODE_META32:
1993 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2001 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2002 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2003 sh->dv_mark_mask, mark);
2005 sh->dv_mark_mask = mark;
2006 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2007 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2008 sh->dv_meta_mask, meta);
2010 sh->dv_meta_mask = meta;
2011 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2012 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2013 sh->dv_meta_mask, reg_c0);
2015 sh->dv_regc0_mask = reg_c0;
2016 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2017 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2018 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2019 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2023 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2025 static const char *const dynf_names[] = {
2026 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2027 RTE_MBUF_DYNFLAG_METADATA_NAME,
2028 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2032 if (n < RTE_DIM(dynf_names))
2034 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2035 if (names[i] == NULL)
2037 strcpy(names[i], dynf_names[i]);
2039 return RTE_DIM(dynf_names);
2043 * Comparison callback to sort device data.
2045 * This is meant to be used with qsort().
2048 * Pointer to pointer to first data object.
2050 * Pointer to pointer to second data object.
2053 * 0 if both objects are equal, less than 0 if the first argument is less
2054 * than the second, greater than 0 otherwise.
2057 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2058 struct mlx5_dev_config *config)
2060 struct mlx5_dev_ctx_shared *sh = priv->sh;
2061 struct mlx5_dev_config *sh_conf = NULL;
2065 /* Nothing to compare for the single/first device. */
2066 if (sh->refcnt == 1)
2068 /* Find the device with shared context. */
2069 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2070 struct mlx5_priv *opriv =
2071 rte_eth_devices[port_id].data->dev_private;
2073 if (opriv && opriv != priv && opriv->sh == sh) {
2074 sh_conf = &opriv->config;
2080 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2081 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2082 " for shared %s context", sh->ibdev_name);
2086 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2087 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2088 " for shared %s context", sh->ibdev_name);
2096 * Look for the ethernet device belonging to mlx5 driver.
2098 * @param[in] port_id
2099 * port_id to start looking for device.
2100 * @param[in] pci_dev
2101 * Pointer to the hint PCI device. When device is being probed
2102 * the its siblings (master and preceding representors might
2103 * not have assigned driver yet (because the mlx5_os_pci_probe()
2104 * is not completed yet, for this case match on hint PCI
2105 * device may be used to detect sibling device.
2108 * port_id of found device, RTE_MAX_ETHPORT if not found.
2111 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2113 while (port_id < RTE_MAX_ETHPORTS) {
2114 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2116 if (dev->state != RTE_ETH_DEV_UNUSED &&
2118 (dev->device == &pci_dev->device ||
2119 (dev->device->driver &&
2120 dev->device->driver->name &&
2121 !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2125 if (port_id >= RTE_MAX_ETHPORTS)
2126 return RTE_MAX_ETHPORTS;
2131 * DPDK callback to remove a PCI device.
2133 * This function removes all Ethernet devices belong to a given PCI device.
2135 * @param[in] pci_dev
2136 * Pointer to the PCI device.
2139 * 0 on success, the function cannot fail.
2142 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2147 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2149 * mlx5_dev_close() is not registered to secondary process,
2150 * call the close function explicitly for secondary process.
2152 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2153 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2155 ret |= rte_eth_dev_close(port_id);
2157 return ret == 0 ? 0 : -EIO;
2160 static const struct rte_pci_id mlx5_pci_id_map[] = {
2162 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2163 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2166 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2167 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2170 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2171 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2174 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2175 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2178 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2179 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2182 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2183 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2186 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2187 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2190 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2191 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2194 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2195 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2198 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2199 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2202 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2203 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2206 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2207 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2210 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2211 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2214 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2215 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2218 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2219 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2222 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2223 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2226 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2227 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2230 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2231 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2238 static struct mlx5_pci_driver mlx5_driver = {
2239 .driver_class = MLX5_CLASS_NET,
2242 .name = MLX5_PCI_DRIVER_NAME,
2244 .id_table = mlx5_pci_id_map,
2245 .probe = mlx5_os_pci_probe,
2246 .remove = mlx5_pci_remove,
2247 .dma_map = mlx5_dma_map,
2248 .dma_unmap = mlx5_dma_unmap,
2249 .drv_flags = PCI_DRV_FLAGS,
2253 /* Initialize driver log type. */
2254 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2257 * Driver initialization routine.
2259 RTE_INIT(rte_mlx5_pmd_init)
2261 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2263 /* Build the static tables for Verbs conversion. */
2264 mlx5_set_ptype_table();
2265 mlx5_set_cksum_table();
2266 mlx5_set_swp_types_table();
2268 mlx5_pci_driver_register(&mlx5_driver);
2271 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2272 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2273 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");