drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 /* The default memory allocator used in PMD. */
 184 #define MLX5_SYS_MEM_EN "sys_mem_en"
 185
 186 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 187
 188 /* Shared memory between primary and secondary processes. */
 189 struct mlx5_shared_data *mlx5_shared_data;
 190
 191 /* Spinlock for mlx5_shared_data allocation. */
 192 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 193
 194 /* Process local data for secondary processes. */
 195 static struct mlx5_local_data mlx5_local_data;
 196
 197 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 198                                                 LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 203         {
 204                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 0,
 209                 .release_mem_en = 1,
 210                 .malloc = rte_malloc_socket,
 211                 .free = rte_free,
 212                 .type = "mlx5_encap_decap_ipool",
 213         },
 214         {
 215                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 0,
 220                 .release_mem_en = 1,
 221                 .malloc = rte_malloc_socket,
 222                 .free = rte_free,
 223                 .type = "mlx5_push_vlan_ipool",
 224         },
 225         {
 226                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 0,
 231                 .release_mem_en = 1,
 232                 .malloc = rte_malloc_socket,
 233                 .free = rte_free,
 234                 .type = "mlx5_tag_ipool",
 235         },
 236         {
 237                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 0,
 242                 .release_mem_en = 1,
 243                 .malloc = rte_malloc_socket,
 244                 .free = rte_free,
 245                 .type = "mlx5_port_id_ipool",
 246         },
 247         {
 248                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 0,
 253                 .release_mem_en = 1,
 254                 .malloc = rte_malloc_socket,
 255                 .free = rte_free,
 256                 .type = "mlx5_jump_ipool",
 257         },
 258 #endif
 259         {
 260                 .size = sizeof(struct mlx5_flow_meter),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 0,
 265                 .release_mem_en = 1,
 266                 .malloc = rte_malloc_socket,
 267                 .free = rte_free,
 268                 .type = "mlx5_meter_ipool",
 269         },
 270         {
 271                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 272                 .trunk_size = 64,
 273                 .grow_trunk = 3,
 274                 .grow_shift = 2,
 275                 .need_lock = 0,
 276                 .release_mem_en = 1,
 277                 .malloc = rte_malloc_socket,
 278                 .free = rte_free,
 279                 .type = "mlx5_mcp_ipool",
 280         },
 281         {
 282                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 283                 .trunk_size = 64,
 284                 .grow_trunk = 3,
 285                 .grow_shift = 2,
 286                 .need_lock = 0,
 287                 .release_mem_en = 1,
 288                 .malloc = rte_malloc_socket,
 289                 .free = rte_free,
 290                 .type = "mlx5_hrxq_ipool",
 291         },
 292         {
 293                 /*
 294                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 295                  * It set in run time according to PCI function configuration.
 296                  */
 297                 .size = 0,
 298                 .trunk_size = 64,
 299                 .grow_trunk = 3,
 300                 .grow_shift = 2,
 301                 .need_lock = 0,
 302                 .release_mem_en = 1,
 303                 .malloc = rte_malloc_socket,
 304                 .free = rte_free,
 305                 .type = "mlx5_flow_handle_ipool",
 306         },
 307         {
 308                 .size = sizeof(struct rte_flow),
 309                 .trunk_size = 4096,
 310                 .need_lock = 1,
 311                 .release_mem_en = 1,
 312                 .malloc = rte_malloc_socket,
 313                 .free = rte_free,
 314                 .type = "rte_flow_ipool",
 315         },
 316 };
 317
 318
 319 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 320 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 321
 322 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 323
 324 /**
 325  * Allocate ID pool structure.
 326  *
 327  * @param[in] max_id
 328  *   The maximum id can be allocated from the pool.
 329  *
 330  * @return
 331  *   Pointer to pool object, NULL value otherwise.
 332  */
 333 struct mlx5_flow_id_pool *
 334 mlx5_flow_id_pool_alloc(uint32_t max_id)
 335 {
 336         struct mlx5_flow_id_pool *pool;
 337         void *mem;
 338
 339         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 340                            RTE_CACHE_LINE_SIZE);
 341         if (!pool) {
 342                 DRV_LOG(ERR, "can't allocate id pool");
 343                 rte_errno  = ENOMEM;
 344                 return NULL;
 345         }
 346         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 347                           RTE_CACHE_LINE_SIZE);
 348         if (!mem) {
 349                 DRV_LOG(ERR, "can't allocate mem for id pool");
 350                 rte_errno  = ENOMEM;
 351                 goto error;
 352         }
 353         pool->free_arr = mem;
 354         pool->curr = pool->free_arr;
 355         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 356         pool->base_index = 0;
 357         pool->max_id = max_id;
 358         return pool;
 359 error:
 360         rte_free(pool);
 361         return NULL;
 362 }
 363
 364 /**
 365  * Release ID pool structure.
 366  *
 367  * @param[in] pool
 368  *   Pointer to flow id pool object to free.
 369  */
 370 void
 371 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 372 {
 373         rte_free(pool->free_arr);
 374         rte_free(pool);
 375 }
 376
 377 /**
 378  * Generate ID.
 379  *
 380  * @param[in] pool
 381  *   Pointer to flow id pool.
 382  * @param[out] id
 383  *   The generated ID.
 384  *
 385  * @return
 386  *   0 on success, error value otherwise.
 387  */
 388 uint32_t
 389 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 390 {
 391         if (pool->curr == pool->free_arr) {
 392                 if (pool->base_index == pool->max_id) {
 393                         rte_errno  = ENOMEM;
 394                         DRV_LOG(ERR, "no free id");
 395                         return -rte_errno;
 396                 }
 397                 *id = ++pool->base_index;
 398                 return 0;
 399         }
 400         *id = *(--pool->curr);
 401         return 0;
 402 }
 403
 404 /**
 405  * Release ID.
 406  *
 407  * @param[in] pool
 408  *   Pointer to flow id pool.
 409  * @param[out] id
 410  *   The generated ID.
 411  *
 412  * @return
 413  *   0 on success, error value otherwise.
 414  */
 415 uint32_t
 416 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 417 {
 418         uint32_t size;
 419         uint32_t size2;
 420         void *mem;
 421
 422         if (pool->curr == pool->last) {
 423                 size = pool->curr - pool->free_arr;
 424                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 425                 MLX5_ASSERT(size2 > size);
 426                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 427                 if (!mem) {
 428                         DRV_LOG(ERR, "can't allocate mem for id pool");
 429                         rte_errno  = ENOMEM;
 430                         return -rte_errno;
 431                 }
 432                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 433                 rte_free(pool->free_arr);
 434                 pool->free_arr = mem;
 435                 pool->curr = pool->free_arr + size;
 436                 pool->last = pool->free_arr + size2;
 437         }
 438         *pool->curr = id;
 439         pool->curr++;
 440         return 0;
 441 }
 442
 443 /**
 444  * Initialize the shared aging list information per port.
 445  *
 446  * @param[in] sh
 447  *   Pointer to mlx5_dev_ctx_shared object.
 448  */
 449 static void
 450 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 451 {
 452         uint32_t i;
 453         struct mlx5_age_info *age_info;
 454
 455         for (i = 0; i < sh->max_port; i++) {
 456                 age_info = &sh->port[i].age_info;
 457                 age_info->flags = 0;
 458                 TAILQ_INIT(&age_info->aged_counters);
 459                 rte_spinlock_init(&age_info->aged_sl);
 460                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 461         }
 462 }
 463
 464 /**
 465  * Initialize the counters management structure.
 466  *
 467  * @param[in] sh
 468  *   Pointer to mlx5_dev_ctx_shared object to free
 469  */
 470 static void
 471 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 472 {
 473         int i;
 474
 475         memset(&sh->cmng, 0, sizeof(sh->cmng));
 476         TAILQ_INIT(&sh->cmng.flow_counters);
 477         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 478                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 479                 sh->cmng.ccont[i].max_id = -1;
 480                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 481                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 482                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 483                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 484                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 485         }
 486 }
 487
 488 /**
 489  * Destroy all the resources allocated for a counter memory management.
 490  *
 491  * @param[in] mng
 492  *   Pointer to the memory management structure.
 493  */
 494 static void
 495 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 496 {
 497         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 498
 499         LIST_REMOVE(mng, next);
 500         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 501         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 502         rte_free(mem);
 503 }
 504
 505 /**
 506  * Close and release all the resources of the counters management.
 507  *
 508  * @param[in] sh
 509  *   Pointer to mlx5_dev_ctx_shared object to free.
 510  */
 511 static void
 512 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 513 {
 514         struct mlx5_counter_stats_mem_mng *mng;
 515         int i;
 516         int j;
 517         int retries = 1024;
 518
 519         rte_errno = 0;
 520         while (--retries) {
 521                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 522                 if (rte_errno != EINPROGRESS)
 523                         break;
 524                 rte_pause();
 525         }
 526         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 527                 struct mlx5_flow_counter_pool *pool;
 528                 uint32_t batch = !!(i > 1);
 529
 530                 if (!sh->cmng.ccont[i].pools)
 531                         continue;
 532                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 533                 while (pool) {
 534                         if (batch && pool->min_dcs)
 535                                 claim_zero(mlx5_devx_cmd_destroy
 536                                                                (pool->min_dcs));
 537                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 538                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 539                                         claim_zero
 540                                          (mlx5_glue->destroy_flow_action
 541                                           (MLX5_POOL_GET_CNT
 542                                           (pool, j)->action));
 543                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 544                                     (pool, j)->dcs)
 545                                         claim_zero(mlx5_devx_cmd_destroy
 546                                                    (MLX5_GET_POOL_CNT_EXT
 547                                                     (pool, j)->dcs));
 548                         }
 549                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 550                         rte_free(pool);
 551                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 552                 }
 553                 rte_free(sh->cmng.ccont[i].pools);
 554         }
 555         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         while (mng) {
 557                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 558                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 559         }
 560         memset(&sh->cmng, 0, sizeof(sh->cmng));
 561 }
 562
 563 /**
 564  * Initialize the flow resources' indexed mempool.
 565  *
 566  * @param[in] sh
 567  *   Pointer to mlx5_dev_ctx_shared object.
 568  * @param[in] sh
 569  *   Pointer to user dev config.
 570  */
 571 static void
 572 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 573                        const struct mlx5_dev_config *config)
 574 {
 575         uint8_t i;
 576         struct mlx5_indexed_pool_config cfg;
 577
 578         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 579                 cfg = mlx5_ipool_cfg[i];
 580                 switch (i) {
 581                 default:
 582                         break;
 583                 /*
 584                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 585                  * according to PCI function flow configuration.
 586                  */
 587                 case MLX5_IPOOL_MLX5_FLOW:
 588                         cfg.size = config->dv_flow_en ?
 589                                 sizeof(struct mlx5_flow_handle) :
 590                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 591                         break;
 592                 }
 593                 if (config->reclaim_mode)
 594                         cfg.release_mem_en = 1;
 595                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 596         }
 597 }
 598
 599 /**
 600  * Release the flow resources' indexed mempool.
 601  *
 602  * @param[in] sh
 603  *   Pointer to mlx5_dev_ctx_shared object.
 604  */
 605 static void
 606 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 607 {
 608         uint8_t i;
 609
 610         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 611                 mlx5_ipool_destroy(sh->ipool[i]);
 612 }
 613
 614 /*
 615  * Check if dynamic flex parser for eCPRI already exists.
 616  *
 617  * @param dev
 618  *   Pointer to Ethernet device structure.
 619  *
 620  * @return
 621  *   true on exists, false on not.
 622  */
 623 bool
 624 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 625 {
 626         struct mlx5_priv *priv = dev->data->dev_private;
 627         struct mlx5_flex_parser_profiles *prf =
 628                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 629
 630         return !!prf->obj;
 631 }
 632
 633 /*
 634  * Allocation of a flex parser for eCPRI. Once created, this parser related
 635  * resources will be held until the device is closed.
 636  *
 637  * @param dev
 638  *   Pointer to Ethernet device structure.
 639  *
 640  * @return
 641  *   0 on success, a negative errno value otherwise and rte_errno is set.
 642  */
 643 int
 644 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 645 {
 646         struct mlx5_priv *priv = dev->data->dev_private;
 647         struct mlx5_flex_parser_profiles *prf =
 648                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 649         struct mlx5_devx_graph_node_attr node = {
 650                 .modify_field_select = 0,
 651         };
 652         uint32_t ids[8];
 653         int ret;
 654
 655         if (!priv->config.hca_attr.parse_graph_flex_node) {
 656                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 657                         "for device %s.", priv->dev_data->name);
 658                 return -ENOTSUP;
 659         }
 660         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 661         /* 8 bytes now: 4B common header + 4B message body header. */
 662         node.header_length_base_value = 0x8;
 663         /* After MAC layer: Ether / VLAN. */
 664         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 665         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 666         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 667         /* Sample #0: type in common header. */
 668         node.sample[0].flow_match_sample_en = 1;
 669         /* Fixed offset. */
 670         node.sample[0].flow_match_sample_offset_mode = 0x0;
 671         /* Only the 2nd byte will be used. */
 672         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 673         /* Sample #1: message payload. */
 674         node.sample[1].flow_match_sample_en = 1;
 675         /* Fixed offset. */
 676         node.sample[1].flow_match_sample_offset_mode = 0x0;
 677         /*
 678          * Only the first two bytes will be used right now, and its offset will
 679          * start after the common header that with the length of a DW(u32).
 680          */
 681         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 682         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 683         if (!prf->obj) {
 684                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 685                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 686         }
 687         prf->num = 2;
 688         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 689         if (ret) {
 690                 DRV_LOG(ERR, "Failed to query sample IDs.");
 691                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 692         }
 693         prf->offset[0] = 0x0;
 694         prf->offset[1] = sizeof(uint32_t);
 695         prf->ids[0] = ids[0];
 696         prf->ids[1] = ids[1];
 697         return 0;
 698 }
 699
 700 /*
 701  * Destroy the flex parser node, including the parser itself, input / output
 702  * arcs and DW samples. Resources could be reused then.
 703  *
 704  * @param dev
 705  *   Pointer to Ethernet device structure.
 706  */
 707 static void
 708 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 709 {
 710         struct mlx5_priv *priv = dev->data->dev_private;
 711         struct mlx5_flex_parser_profiles *prf =
 712                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 713
 714         if (prf->obj)
 715                 mlx5_devx_cmd_destroy(prf->obj);
 716         prf->obj = NULL;
 717 }
 718
 719 /**
 720  * Allocate shared device context. If there is multiport device the
 721  * master and representors will share this context, if there is single
 722  * port dedicated device, the context will be used by only given
 723  * port due to unification.
 724  *
 725  * Routine first searches the context for the specified device name,
 726  * if found the shared context assumed and reference counter is incremented.
 727  * If no context found the new one is created and initialized with specified
 728  * device context and parameters.
 729  *
 730  * @param[in] spawn
 731  *   Pointer to the device attributes (name, port, etc).
 732  * @param[in] config
 733  *   Pointer to device configuration structure.
 734  *
 735  * @return
 736  *   Pointer to mlx5_dev_ctx_shared object on success,
 737  *   otherwise NULL and rte_errno is set.
 738  */
 739 struct mlx5_dev_ctx_shared *
 740 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 741                            const struct mlx5_dev_config *config)
 742 {
 743         struct mlx5_dev_ctx_shared *sh;
 744         int err = 0;
 745         uint32_t i;
 746         struct mlx5_devx_tis_attr tis_attr = { 0 };
 747
 748         MLX5_ASSERT(spawn);
 749         /* Secondary process should not create the shared context. */
 750         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 751         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 752         /* Search for IB context by device name. */
 753         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 754                 if (!strcmp(sh->ibdev_name,
 755                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 756                         sh->refcnt++;
 757                         goto exit;
 758                 }
 759         }
 760         /* No device found, we have to create new shared context. */
 761         MLX5_ASSERT(spawn->max_port);
 762         sh = rte_zmalloc("ethdev shared ib context",
 763                          sizeof(struct mlx5_dev_ctx_shared) +
 764                          spawn->max_port *
 765                          sizeof(struct mlx5_dev_shared_port),
 766                          RTE_CACHE_LINE_SIZE);
 767         if (!sh) {
 768                 DRV_LOG(ERR, "shared context allocation failure");
 769                 rte_errno  = ENOMEM;
 770                 goto exit;
 771         }
 772         err = mlx5_os_open_device(spawn, config, sh);
 773         if (!sh->ctx)
 774                 goto error;
 775         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 776         if (err) {
 777                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 778                 goto error;
 779         }
 780         sh->refcnt = 1;
 781         sh->max_port = spawn->max_port;
 782         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 783                 sizeof(sh->ibdev_name) - 1);
 784         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 785                 sizeof(sh->ibdev_path) - 1);
 786         /*
 787          * Setting port_id to max unallowed value means
 788          * there is no interrupt subhandler installed for
 789          * the given port index i.
 790          */
 791         for (i = 0; i < sh->max_port; i++) {
 792                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 793                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 794         }
 795         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 796         if (sh->pd == NULL) {
 797                 DRV_LOG(ERR, "PD allocation failure");
 798                 err = ENOMEM;
 799                 goto error;
 800         }
 801         if (sh->devx) {
 802                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 803                 if (err) {
 804                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 805                         goto error;
 806                 }
 807                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 808                 if (!sh->td) {
 809                         DRV_LOG(ERR, "TD allocation failure");
 810                         err = ENOMEM;
 811                         goto error;
 812                 }
 813                 tis_attr.transport_domain = sh->td->id;
 814                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 815                 if (!sh->tis) {
 816                         DRV_LOG(ERR, "TIS allocation failure");
 817                         err = ENOMEM;
 818                         goto error;
 819                 }
 820                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 821                 if (!sh->tx_uar) {
 822                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 823                         err = ENOMEM;
 824                         goto error;
 825                 }
 826         }
 827         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 828                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 829         if (!sh->flow_id_pool) {
 830                 DRV_LOG(ERR, "can't create flow id pool");
 831                 err = ENOMEM;
 832                 goto error;
 833         }
 834 #ifndef RTE_ARCH_64
 835         /* Initialize UAR access locks for 32bit implementations. */
 836         rte_spinlock_init(&sh->uar_lock_cq);
 837         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 838                 rte_spinlock_init(&sh->uar_lock[i]);
 839 #endif
 840         /*
 841          * Once the device is added to the list of memory event
 842          * callback, its global MR cache table cannot be expanded
 843          * on the fly because of deadlock. If it overflows, lookup
 844          * should be done by searching MR list linearly, which is slow.
 845          *
 846          * At this point the device is not added to the memory
 847          * event list yet, context is just being created.
 848          */
 849         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 850                                  MLX5_MR_BTREE_CACHE_N * 2,
 851                                  spawn->pci_dev->device.numa_node);
 852         if (err) {
 853                 err = rte_errno;
 854                 goto error;
 855         }
 856         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 857                               &sh->share_cache.dereg_mr_cb);
 858         mlx5_os_dev_shared_handler_install(sh);
 859         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 860         if (!sh->cnt_id_tbl) {
 861                 err = rte_errno;
 862                 goto error;
 863         }
 864         mlx5_flow_aging_init(sh);
 865         mlx5_flow_counters_mng_init(sh);
 866         mlx5_flow_ipool_create(sh, config);
 867         /* Add device to memory callback list. */
 868         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 869         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 870                          sh, mem_event_cb);
 871         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 872         /* Add context to the global device list. */
 873         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 874 exit:
 875         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 876         return sh;
 877 error:
 878         pthread_mutex_destroy(&sh->txpp.mutex);
 879         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 880         MLX5_ASSERT(sh);
 881         if (sh->cnt_id_tbl) {
 882                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 883                 sh->cnt_id_tbl = NULL;
 884         }
 885         if (sh->tx_uar) {
 886                 mlx5_glue->devx_free_uar(sh->tx_uar);
 887                 sh->tx_uar = NULL;
 888         }
 889         if (sh->tis)
 890                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 891         if (sh->td)
 892                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 893         if (sh->pd)
 894                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 895         if (sh->ctx)
 896                 claim_zero(mlx5_glue->close_device(sh->ctx));
 897         if (sh->flow_id_pool)
 898                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 899         rte_free(sh);
 900         MLX5_ASSERT(err > 0);
 901         rte_errno = err;
 902         return NULL;
 903 }
 904
 905 /**
 906  * Free shared IB device context. Decrement counter and if zero free
 907  * all allocated resources and close handles.
 908  *
 909  * @param[in] sh
 910  *   Pointer to mlx5_dev_ctx_shared object to free
 911  */
 912 void
 913 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 914 {
 915         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 916 #ifdef RTE_LIBRTE_MLX5_DEBUG
 917         /* Check the object presence in the list. */
 918         struct mlx5_dev_ctx_shared *lctx;
 919
 920         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 921                 if (lctx == sh)
 922                         break;
 923         MLX5_ASSERT(lctx);
 924         if (lctx != sh) {
 925                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 926                 goto exit;
 927         }
 928 #endif
 929         MLX5_ASSERT(sh);
 930         MLX5_ASSERT(sh->refcnt);
 931         /* Secondary process should not free the shared context. */
 932         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 933         if (--sh->refcnt)
 934                 goto exit;
 935         /* Remove from memory callback device list. */
 936         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 937         LIST_REMOVE(sh, mem_event_cb);
 938         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 939         /* Release created Memory Regions. */
 940         mlx5_mr_release_cache(&sh->share_cache);
 941         /* Remove context from the global device list. */
 942         LIST_REMOVE(sh, next);
 943         /*
 944          *  Ensure there is no async event handler installed.
 945          *  Only primary process handles async device events.
 946          **/
 947         mlx5_flow_counters_mng_close(sh);
 948         mlx5_flow_ipool_destroy(sh);
 949         mlx5_os_dev_shared_handler_uninstall(sh);
 950         if (sh->cnt_id_tbl) {
 951                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 952                 sh->cnt_id_tbl = NULL;
 953         }
 954         if (sh->tx_uar) {
 955                 mlx5_glue->devx_free_uar(sh->tx_uar);
 956                 sh->tx_uar = NULL;
 957         }
 958         if (sh->pd)
 959                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 960         if (sh->tis)
 961                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 962         if (sh->td)
 963                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 964         if (sh->ctx)
 965                 claim_zero(mlx5_glue->close_device(sh->ctx));
 966         if (sh->flow_id_pool)
 967                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 968         pthread_mutex_destroy(&sh->txpp.mutex);
 969         rte_free(sh);
 970 exit:
 971         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 972 }
 973
 974 /**
 975  * Destroy table hash list and all the root entries per domain.
 976  *
 977  * @param[in] priv
 978  *   Pointer to the private device data structure.
 979  */
 980 void
 981 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 982 {
 983         struct mlx5_dev_ctx_shared *sh = priv->sh;
 984         struct mlx5_flow_tbl_data_entry *tbl_data;
 985         union mlx5_flow_tbl_key table_key = {
 986                 {
 987                         .table_id = 0,
 988                         .reserved = 0,
 989                         .domain = 0,
 990                         .direction = 0,
 991                 }
 992         };
 993         struct mlx5_hlist_entry *pos;
 994
 995         if (!sh->flow_tbls)
 996                 return;
 997         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 998         if (pos) {
 999                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1000                                         entry);
1001                 MLX5_ASSERT(tbl_data);
1002                 mlx5_hlist_remove(sh->flow_tbls, pos);
1003                 rte_free(tbl_data);
1004         }
1005         table_key.direction = 1;
1006         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1007         if (pos) {
1008                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1009                                         entry);
1010                 MLX5_ASSERT(tbl_data);
1011                 mlx5_hlist_remove(sh->flow_tbls, pos);
1012                 rte_free(tbl_data);
1013         }
1014         table_key.direction = 0;
1015         table_key.domain = 1;
1016         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1017         if (pos) {
1018                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1019                                         entry);
1020                 MLX5_ASSERT(tbl_data);
1021                 mlx5_hlist_remove(sh->flow_tbls, pos);
1022                 rte_free(tbl_data);
1023         }
1024         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1025 }
1026
1027 /**
1028  * Initialize flow table hash list and create the root tables entry
1029  * for each domain.
1030  *
1031  * @param[in] priv
1032  *   Pointer to the private device data structure.
1033  *
1034  * @return
1035  *   Zero on success, positive error code otherwise.
1036  */
1037 int
1038 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1039 {
1040         struct mlx5_dev_ctx_shared *sh = priv->sh;
1041         char s[MLX5_HLIST_NAMESIZE];
1042         int err = 0;
1043
1044         MLX5_ASSERT(sh);
1045         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1046         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1047         if (!sh->flow_tbls) {
1048                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1049                 err = ENOMEM;
1050                 return err;
1051         }
1052 #ifndef HAVE_MLX5DV_DR
1053         /*
1054          * In case we have not DR support, the zero tables should be created
1055          * because DV expect to see them even if they cannot be created by
1056          * RDMA-CORE.
1057          */
1058         union mlx5_flow_tbl_key table_key = {
1059                 {
1060                         .table_id = 0,
1061                         .reserved = 0,
1062                         .domain = 0,
1063                         .direction = 0,
1064                 }
1065         };
1066         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1067                                                           sizeof(*tbl_data), 0);
1068
1069         if (!tbl_data) {
1070                 err = ENOMEM;
1071                 goto error;
1072         }
1073         tbl_data->entry.key = table_key.v64;
1074         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1075         if (err)
1076                 goto error;
1077         rte_atomic32_init(&tbl_data->tbl.refcnt);
1078         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1079         table_key.direction = 1;
1080         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1081         if (!tbl_data) {
1082                 err = ENOMEM;
1083                 goto error;
1084         }
1085         tbl_data->entry.key = table_key.v64;
1086         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1087         if (err)
1088                 goto error;
1089         rte_atomic32_init(&tbl_data->tbl.refcnt);
1090         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1091         table_key.direction = 0;
1092         table_key.domain = 1;
1093         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1094         if (!tbl_data) {
1095                 err = ENOMEM;
1096                 goto error;
1097         }
1098         tbl_data->entry.key = table_key.v64;
1099         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1100         if (err)
1101                 goto error;
1102         rte_atomic32_init(&tbl_data->tbl.refcnt);
1103         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1104         return err;
1105 error:
1106         mlx5_free_table_hash_list(priv);
1107 #endif /* HAVE_MLX5DV_DR */
1108         return err;
1109 }
1110
1111 /**
1112  * Initialize shared data between primary and secondary process.
1113  *
1114  * A memzone is reserved by primary process and secondary processes attach to
1115  * the memzone.
1116  *
1117  * @return
1118  *   0 on success, a negative errno value otherwise and rte_errno is set.
1119  */
1120 static int
1121 mlx5_init_shared_data(void)
1122 {
1123         const struct rte_memzone *mz;
1124         int ret = 0;
1125
1126         rte_spinlock_lock(&mlx5_shared_data_lock);
1127         if (mlx5_shared_data == NULL) {
1128                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1129                         /* Allocate shared memory. */
1130                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1131                                                  sizeof(*mlx5_shared_data),
1132                                                  SOCKET_ID_ANY, 0);
1133                         if (mz == NULL) {
1134                                 DRV_LOG(ERR,
1135                                         "Cannot allocate mlx5 shared data");
1136                                 ret = -rte_errno;
1137                                 goto error;
1138                         }
1139                         mlx5_shared_data = mz->addr;
1140                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1141                         rte_spinlock_init(&mlx5_shared_data->lock);
1142                 } else {
1143                         /* Lookup allocated shared memory. */
1144                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1145                         if (mz == NULL) {
1146                                 DRV_LOG(ERR,
1147                                         "Cannot attach mlx5 shared data");
1148                                 ret = -rte_errno;
1149                                 goto error;
1150                         }
1151                         mlx5_shared_data = mz->addr;
1152                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1153                 }
1154         }
1155 error:
1156         rte_spinlock_unlock(&mlx5_shared_data_lock);
1157         return ret;
1158 }
1159
1160 /**
1161  * Retrieve integer value from environment variable.
1162  *
1163  * @param[in] name
1164  *   Environment variable name.
1165  *
1166  * @return
1167  *   Integer value, 0 if the variable is not set.
1168  */
1169 int
1170 mlx5_getenv_int(const char *name)
1171 {
1172         const char *val = getenv(name);
1173
1174         if (val == NULL)
1175                 return 0;
1176         return atoi(val);
1177 }
1178
1179 /**
1180  * DPDK callback to add udp tunnel port
1181  *
1182  * @param[in] dev
1183  *   A pointer to eth_dev
1184  * @param[in] udp_tunnel
1185  *   A pointer to udp tunnel
1186  *
1187  * @return
1188  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1189  */
1190 int
1191 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1192                          struct rte_eth_udp_tunnel *udp_tunnel)
1193 {
1194         MLX5_ASSERT(udp_tunnel != NULL);
1195         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1196             udp_tunnel->udp_port == 4789)
1197                 return 0;
1198         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1199             udp_tunnel->udp_port == 4790)
1200                 return 0;
1201         return -ENOTSUP;
1202 }
1203
1204 /**
1205  * Initialize process private data structure.
1206  *
1207  * @param dev
1208  *   Pointer to Ethernet device structure.
1209  *
1210  * @return
1211  *   0 on success, a negative errno value otherwise and rte_errno is set.
1212  */
1213 int
1214 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1215 {
1216         struct mlx5_priv *priv = dev->data->dev_private;
1217         struct mlx5_proc_priv *ppriv;
1218         size_t ppriv_size;
1219
1220         /*
1221          * UAR register table follows the process private structure. BlueFlame
1222          * registers for Tx queues are stored in the table.
1223          */
1224         ppriv_size =
1225                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1226         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1227                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1228         if (!ppriv) {
1229                 rte_errno = ENOMEM;
1230                 return -rte_errno;
1231         }
1232         ppriv->uar_table_sz = ppriv_size;
1233         dev->process_private = ppriv;
1234         return 0;
1235 }
1236
1237 /**
1238  * Un-initialize process private data structure.
1239  *
1240  * @param dev
1241  *   Pointer to Ethernet device structure.
1242  */
1243 static void
1244 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1245 {
1246         if (!dev->process_private)
1247                 return;
1248         rte_free(dev->process_private);
1249         dev->process_private = NULL;
1250 }
1251
1252 /**
1253  * DPDK callback to close the device.
1254  *
1255  * Destroy all queues and objects, free memory.
1256  *
1257  * @param dev
1258  *   Pointer to Ethernet device structure.
1259  */
1260 void
1261 mlx5_dev_close(struct rte_eth_dev *dev)
1262 {
1263         struct mlx5_priv *priv = dev->data->dev_private;
1264         unsigned int i;
1265         int ret;
1266
1267         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1268                 /* Check if process_private released. */
1269                 if (!dev->process_private)
1270                         return;
1271                 mlx5_tx_uar_uninit_secondary(dev);
1272                 mlx5_proc_priv_uninit(dev);
1273                 rte_eth_dev_release_port(dev);
1274                 return;
1275         }
1276         if (!priv->sh)
1277                 return;
1278         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1279                 dev->data->port_id,
1280                 ((priv->sh->ctx != NULL) ?
1281                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1282         /*
1283          * If default mreg copy action is removed at the stop stage,
1284          * the search will return none and nothing will be done anymore.
1285          */
1286         mlx5_flow_stop_default(dev);
1287         mlx5_traffic_disable(dev);
1288         /*
1289          * If all the flows are already flushed in the device stop stage,
1290          * then this will return directly without any action.
1291          */
1292         mlx5_flow_list_flush(dev, &priv->flows, true);
1293         mlx5_flow_meter_flush(dev, NULL);
1294         /* Free the intermediate buffers for flow creation. */
1295         mlx5_flow_free_intermediate(dev);
1296         /* Prevent crashes when queues are still in use. */
1297         dev->rx_pkt_burst = removed_rx_burst;
1298         dev->tx_pkt_burst = removed_tx_burst;
1299         rte_wmb();
1300         /* Disable datapath on secondary process. */
1301         mlx5_mp_req_stop_rxtx(dev);
1302         /* Free the eCPRI flex parser resource. */
1303         mlx5_flex_parser_ecpri_release(dev);
1304         if (priv->rxqs != NULL) {
1305                 /* XXX race condition if mlx5_rx_burst() is still running. */
1306                 usleep(1000);
1307                 for (i = 0; (i != priv->rxqs_n); ++i)
1308                         mlx5_rxq_release(dev, i);
1309                 priv->rxqs_n = 0;
1310                 priv->rxqs = NULL;
1311         }
1312         if (priv->txqs != NULL) {
1313                 /* XXX race condition if mlx5_tx_burst() is still running. */
1314                 usleep(1000);
1315                 for (i = 0; (i != priv->txqs_n); ++i)
1316                         mlx5_txq_release(dev, i);
1317                 priv->txqs_n = 0;
1318                 priv->txqs = NULL;
1319         }
1320         mlx5_proc_priv_uninit(dev);
1321         if (priv->mreg_cp_tbl)
1322                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1323         mlx5_mprq_free_mp(dev);
1324         mlx5_os_free_shared_dr(priv);
1325         if (priv->rss_conf.rss_key != NULL)
1326                 rte_free(priv->rss_conf.rss_key);
1327         if (priv->reta_idx != NULL)
1328                 rte_free(priv->reta_idx);
1329         if (priv->config.vf)
1330                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1331                                        dev->data->mac_addrs,
1332                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1333         if (priv->nl_socket_route >= 0)
1334                 close(priv->nl_socket_route);
1335         if (priv->nl_socket_rdma >= 0)
1336                 close(priv->nl_socket_rdma);
1337         if (priv->vmwa_context)
1338                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1339         ret = mlx5_hrxq_verify(dev);
1340         if (ret)
1341                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1342                         dev->data->port_id);
1343         ret = mlx5_ind_table_obj_verify(dev);
1344         if (ret)
1345                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1346                         dev->data->port_id);
1347         ret = mlx5_rxq_obj_verify(dev);
1348         if (ret)
1349                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1350                         dev->data->port_id);
1351         ret = mlx5_rxq_verify(dev);
1352         if (ret)
1353                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1354                         dev->data->port_id);
1355         ret = mlx5_txq_obj_verify(dev);
1356         if (ret)
1357                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1358                         dev->data->port_id);
1359         ret = mlx5_txq_verify(dev);
1360         if (ret)
1361                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1362                         dev->data->port_id);
1363         ret = mlx5_flow_verify(dev);
1364         if (ret)
1365                 DRV_LOG(WARNING, "port %u some flows still remain",
1366                         dev->data->port_id);
1367         /*
1368          * Free the shared context in last turn, because the cleanup
1369          * routines above may use some shared fields, like
1370          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1371          * ifindex if Netlink fails.
1372          */
1373         mlx5_free_shared_dev_ctx(priv->sh);
1374         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1375                 unsigned int c = 0;
1376                 uint16_t port_id;
1377
1378                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1379                         struct mlx5_priv *opriv =
1380                                 rte_eth_devices[port_id].data->dev_private;
1381
1382                         if (!opriv ||
1383                             opriv->domain_id != priv->domain_id ||
1384                             &rte_eth_devices[port_id] == dev)
1385                                 continue;
1386                         ++c;
1387                         break;
1388                 }
1389                 if (!c)
1390                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1391         }
1392         memset(priv, 0, sizeof(*priv));
1393         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1394         /*
1395          * Reset mac_addrs to NULL such that it is not freed as part of
1396          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1397          * it is freed when dev_private is freed.
1398          */
1399         dev->data->mac_addrs = NULL;
1400 }
1401
1402 /**
1403  * Verify and store value for device argument.
1404  *
1405  * @param[in] key
1406  *   Key argument to verify.
1407  * @param[in] val
1408  *   Value associated with key.
1409  * @param opaque
1410  *   User data.
1411  *
1412  * @return
1413  *   0 on success, a negative errno value otherwise and rte_errno is set.
1414  */
1415 static int
1416 mlx5_args_check(const char *key, const char *val, void *opaque)
1417 {
1418         struct mlx5_dev_config *config = opaque;
1419         unsigned long mod;
1420         signed long tmp;
1421
1422         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1423         if (!strcmp(MLX5_REPRESENTOR, key))
1424                 return 0;
1425         errno = 0;
1426         tmp = strtol(val, NULL, 0);
1427         if (errno) {
1428                 rte_errno = errno;
1429                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1430                 return -rte_errno;
1431         }
1432         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1433                 /* Negative values are acceptable for some keys only. */
1434                 rte_errno = EINVAL;
1435                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1436                 return -rte_errno;
1437         }
1438         mod = tmp >= 0 ? tmp : -tmp;
1439         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1440                 config->cqe_comp = !!tmp;
1441         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1442                 config->cqe_pad = !!tmp;
1443         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1444                 config->hw_padding = !!tmp;
1445         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1446                 config->mprq.enabled = !!tmp;
1447         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1448                 config->mprq.stride_num_n = tmp;
1449         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1450                 config->mprq.stride_size_n = tmp;
1451         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1452                 config->mprq.max_memcpy_len = tmp;
1453         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1454                 config->mprq.min_rxqs_num = tmp;
1455         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1456                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1457                                  " converted to txq_inline_max", key);
1458                 config->txq_inline_max = tmp;
1459         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1460                 config->txq_inline_max = tmp;
1461         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1462                 config->txq_inline_min = tmp;
1463         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1464                 config->txq_inline_mpw = tmp;
1465         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1466                 config->txqs_inline = tmp;
1467         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1468                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1469         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1470                 config->mps = !!tmp;
1471         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1472                 if (tmp != MLX5_TXDB_CACHED &&
1473                     tmp != MLX5_TXDB_NCACHED &&
1474                     tmp != MLX5_TXDB_HEURISTIC) {
1475                         DRV_LOG(ERR, "invalid Tx doorbell "
1476                                      "mapping parameter");
1477                         rte_errno = EINVAL;
1478                         return -rte_errno;
1479                 }
1480                 config->dbnc = tmp;
1481         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1482                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1483         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1484                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1485                                  " converted to txq_inline_mpw", key);
1486                 config->txq_inline_mpw = tmp;
1487         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1488                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1489         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1490                 if (!mod) {
1491                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1492                         rte_errno = EINVAL;
1493                         return -rte_errno;
1494                 }
1495                 config->tx_pp = tmp;
1496         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1497                 config->tx_skew = tmp;
1498         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1499                 config->rx_vec_en = !!tmp;
1500         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1501                 config->l3_vxlan_en = !!tmp;
1502         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1503                 config->vf_nl_en = !!tmp;
1504         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1505                 config->dv_esw_en = !!tmp;
1506         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1507                 config->dv_flow_en = !!tmp;
1508         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1509                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1510                     tmp != MLX5_XMETA_MODE_META16 &&
1511                     tmp != MLX5_XMETA_MODE_META32) {
1512                         DRV_LOG(ERR, "invalid extensive "
1513                                      "metadata parameter");
1514                         rte_errno = EINVAL;
1515                         return -rte_errno;
1516                 }
1517                 config->dv_xmeta_en = tmp;
1518         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1519                 config->lacp_by_user = !!tmp;
1520         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1521                 config->mr_ext_memseg_en = !!tmp;
1522         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1523                 config->max_dump_files_num = tmp;
1524         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1525                 config->lro.timeout = tmp;
1526         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1527                 DRV_LOG(DEBUG, "class argument is %s.", val);
1528         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1529                 config->log_hp_size = tmp;
1530         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1531                 if (tmp != MLX5_RCM_NONE &&
1532                     tmp != MLX5_RCM_LIGHT &&
1533                     tmp != MLX5_RCM_AGGR) {
1534                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1535                         rte_errno = EINVAL;
1536                         return -rte_errno;
1537                 }
1538                 config->reclaim_mode = tmp;
1539         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1540                 config->sys_mem_en = !!tmp;
1541         } else {
1542                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1543                 rte_errno = EINVAL;
1544                 return -rte_errno;
1545         }
1546         return 0;
1547 }
1548
1549 /**
1550  * Parse device parameters.
1551  *
1552  * @param config
1553  *   Pointer to device configuration structure.
1554  * @param devargs
1555  *   Device arguments structure.
1556  *
1557  * @return
1558  *   0 on success, a negative errno value otherwise and rte_errno is set.
1559  */
1560 int
1561 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1562 {
1563         const char **params = (const char *[]){
1564                 MLX5_RXQ_CQE_COMP_EN,
1565                 MLX5_RXQ_CQE_PAD_EN,
1566                 MLX5_RXQ_PKT_PAD_EN,
1567                 MLX5_RX_MPRQ_EN,
1568                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1569                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1570                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1571                 MLX5_RXQS_MIN_MPRQ,
1572                 MLX5_TXQ_INLINE,
1573                 MLX5_TXQ_INLINE_MIN,
1574                 MLX5_TXQ_INLINE_MAX,
1575                 MLX5_TXQ_INLINE_MPW,
1576                 MLX5_TXQS_MIN_INLINE,
1577                 MLX5_TXQS_MAX_VEC,
1578                 MLX5_TXQ_MPW_EN,
1579                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1580                 MLX5_TXQ_MAX_INLINE_LEN,
1581                 MLX5_TX_DB_NC,
1582                 MLX5_TX_PP,
1583                 MLX5_TX_SKEW,
1584                 MLX5_TX_VEC_EN,
1585                 MLX5_RX_VEC_EN,
1586                 MLX5_L3_VXLAN_EN,
1587                 MLX5_VF_NL_EN,
1588                 MLX5_DV_ESW_EN,
1589                 MLX5_DV_FLOW_EN,
1590                 MLX5_DV_XMETA_EN,
1591                 MLX5_LACP_BY_USER,
1592                 MLX5_MR_EXT_MEMSEG_EN,
1593                 MLX5_REPRESENTOR,
1594                 MLX5_MAX_DUMP_FILES_NUM,
1595                 MLX5_LRO_TIMEOUT_USEC,
1596                 MLX5_CLASS_ARG_NAME,
1597                 MLX5_HP_BUF_SIZE,
1598                 MLX5_RECLAIM_MEM,
1599                 MLX5_SYS_MEM_EN,
1600                 NULL,
1601         };
1602         struct rte_kvargs *kvlist;
1603         int ret = 0;
1604         int i;
1605
1606         if (devargs == NULL)
1607                 return 0;
1608         /* Following UGLY cast is done to pass checkpatch. */
1609         kvlist = rte_kvargs_parse(devargs->args, params);
1610         if (kvlist == NULL) {
1611                 rte_errno = EINVAL;
1612                 return -rte_errno;
1613         }
1614         /* Process parameters. */
1615         for (i = 0; (params[i] != NULL); ++i) {
1616                 if (rte_kvargs_count(kvlist, params[i])) {
1617                         ret = rte_kvargs_process(kvlist, params[i],
1618                                                  mlx5_args_check, config);
1619                         if (ret) {
1620                                 rte_errno = EINVAL;
1621                                 rte_kvargs_free(kvlist);
1622                                 return -rte_errno;
1623                         }
1624                 }
1625         }
1626         rte_kvargs_free(kvlist);
1627         return 0;
1628 }
1629
1630 /**
1631  * PMD global initialization.
1632  *
1633  * Independent from individual device, this function initializes global
1634  * per-PMD data structures distinguishing primary and secondary processes.
1635  * Hence, each initialization is called once per a process.
1636  *
1637  * @return
1638  *   0 on success, a negative errno value otherwise and rte_errno is set.
1639  */
1640 int
1641 mlx5_init_once(void)
1642 {
1643         struct mlx5_shared_data *sd;
1644         struct mlx5_local_data *ld = &mlx5_local_data;
1645         int ret = 0;
1646
1647         if (mlx5_init_shared_data())
1648                 return -rte_errno;
1649         sd = mlx5_shared_data;
1650         MLX5_ASSERT(sd);
1651         rte_spinlock_lock(&sd->lock);
1652         switch (rte_eal_process_type()) {
1653         case RTE_PROC_PRIMARY:
1654                 if (sd->init_done)
1655                         break;
1656                 LIST_INIT(&sd->mem_event_cb_list);
1657                 rte_rwlock_init(&sd->mem_event_rwlock);
1658                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1659                                                 mlx5_mr_mem_event_cb, NULL);
1660                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1661                                            mlx5_mp_primary_handle);
1662                 if (ret)
1663                         goto out;
1664                 sd->init_done = true;
1665                 break;
1666         case RTE_PROC_SECONDARY:
1667                 if (ld->init_done)
1668                         break;
1669                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1670                                              mlx5_mp_secondary_handle);
1671                 if (ret)
1672                         goto out;
1673                 ++sd->secondary_cnt;
1674                 ld->init_done = true;
1675                 break;
1676         default:
1677                 break;
1678         }
1679 out:
1680         rte_spinlock_unlock(&sd->lock);
1681         return ret;
1682 }
1683
1684 /**
1685  * Configures the minimal amount of data to inline into WQE
1686  * while sending packets.
1687  *
1688  * - the txq_inline_min has the maximal priority, if this
1689  *   key is specified in devargs
1690  * - if DevX is enabled the inline mode is queried from the
1691  *   device (HCA attributes and NIC vport context if needed).
1692  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1693  *   and none (0 bytes) for other NICs
1694  *
1695  * @param spawn
1696  *   Verbs device parameters (name, port, switch_info) to spawn.
1697  * @param config
1698  *   Device configuration parameters.
1699  */
1700 void
1701 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1702                     struct mlx5_dev_config *config)
1703 {
1704         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1705                 /* Application defines size of inlined data explicitly. */
1706                 switch (spawn->pci_dev->id.device_id) {
1707                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1708                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1709                         if (config->txq_inline_min <
1710                                        (int)MLX5_INLINE_HSIZE_L2) {
1711                                 DRV_LOG(DEBUG,
1712                                         "txq_inline_mix aligned to minimal"
1713                                         " ConnectX-4 required value %d",
1714                                         (int)MLX5_INLINE_HSIZE_L2);
1715                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1716                         }
1717                         break;
1718                 }
1719                 goto exit;
1720         }
1721         if (config->hca_attr.eth_net_offloads) {
1722                 /* We have DevX enabled, inline mode queried successfully. */
1723                 switch (config->hca_attr.wqe_inline_mode) {
1724                 case MLX5_CAP_INLINE_MODE_L2:
1725                         /* outer L2 header must be inlined. */
1726                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1727                         goto exit;
1728                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1729                         /* No inline data are required by NIC. */
1730                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1731                         config->hw_vlan_insert =
1732                                 config->hca_attr.wqe_vlan_insert;
1733                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1734                         goto exit;
1735                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1736                         /* inline mode is defined by NIC vport context. */
1737                         if (!config->hca_attr.eth_virt)
1738                                 break;
1739                         switch (config->hca_attr.vport_inline_mode) {
1740                         case MLX5_INLINE_MODE_NONE:
1741                                 config->txq_inline_min =
1742                                         MLX5_INLINE_HSIZE_NONE;
1743                                 goto exit;
1744                         case MLX5_INLINE_MODE_L2:
1745                                 config->txq_inline_min =
1746                                         MLX5_INLINE_HSIZE_L2;
1747                                 goto exit;
1748                         case MLX5_INLINE_MODE_IP:
1749                                 config->txq_inline_min =
1750                                         MLX5_INLINE_HSIZE_L3;
1751                                 goto exit;
1752                         case MLX5_INLINE_MODE_TCP_UDP:
1753                                 config->txq_inline_min =
1754                                         MLX5_INLINE_HSIZE_L4;
1755                                 goto exit;
1756                         case MLX5_INLINE_MODE_INNER_L2:
1757                                 config->txq_inline_min =
1758                                         MLX5_INLINE_HSIZE_INNER_L2;
1759                                 goto exit;
1760                         case MLX5_INLINE_MODE_INNER_IP:
1761                                 config->txq_inline_min =
1762                                         MLX5_INLINE_HSIZE_INNER_L3;
1763                                 goto exit;
1764                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1765                                 config->txq_inline_min =
1766                                         MLX5_INLINE_HSIZE_INNER_L4;
1767                                 goto exit;
1768                         }
1769                 }
1770         }
1771         /*
1772          * We get here if we are unable to deduce
1773          * inline data size with DevX. Try PCI ID
1774          * to determine old NICs.
1775          */
1776         switch (spawn->pci_dev->id.device_id) {
1777         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1778         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1779         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1780         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1781                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1782                 config->hw_vlan_insert = 0;
1783                 break;
1784         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1785         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1786         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1787         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1788                 /*
1789                  * These NICs support VLAN insertion from WQE and
1790                  * report the wqe_vlan_insert flag. But there is the bug
1791                  * and PFC control may be broken, so disable feature.
1792                  */
1793                 config->hw_vlan_insert = 0;
1794                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1795                 break;
1796         default:
1797                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1798                 break;
1799         }
1800 exit:
1801         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1802 }
1803
1804 /**
1805  * Configures the metadata mask fields in the shared context.
1806  *
1807  * @param [in] dev
1808  *   Pointer to Ethernet device.
1809  */
1810 void
1811 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1812 {
1813         struct mlx5_priv *priv = dev->data->dev_private;
1814         struct mlx5_dev_ctx_shared *sh = priv->sh;
1815         uint32_t meta, mark, reg_c0;
1816
1817         reg_c0 = ~priv->vport_meta_mask;
1818         switch (priv->config.dv_xmeta_en) {
1819         case MLX5_XMETA_MODE_LEGACY:
1820                 meta = UINT32_MAX;
1821                 mark = MLX5_FLOW_MARK_MASK;
1822                 break;
1823         case MLX5_XMETA_MODE_META16:
1824                 meta = reg_c0 >> rte_bsf32(reg_c0);
1825                 mark = MLX5_FLOW_MARK_MASK;
1826                 break;
1827         case MLX5_XMETA_MODE_META32:
1828                 meta = UINT32_MAX;
1829                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1830                 break;
1831         default:
1832                 meta = 0;
1833                 mark = 0;
1834                 MLX5_ASSERT(false);
1835                 break;
1836         }
1837         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1838                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1839                                  sh->dv_mark_mask, mark);
1840         else
1841                 sh->dv_mark_mask = mark;
1842         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1843                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1844                                  sh->dv_meta_mask, meta);
1845         else
1846                 sh->dv_meta_mask = meta;
1847         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1848                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1849                                  sh->dv_meta_mask, reg_c0);
1850         else
1851                 sh->dv_regc0_mask = reg_c0;
1852         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1853         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1854         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1855         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1856 }
1857
1858 int
1859 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1860 {
1861         static const char *const dynf_names[] = {
1862                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1863                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1864                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1865         };
1866         unsigned int i;
1867
1868         if (n < RTE_DIM(dynf_names))
1869                 return -ENOMEM;
1870         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1871                 if (names[i] == NULL)
1872                         return -EINVAL;
1873                 strcpy(names[i], dynf_names[i]);
1874         }
1875         return RTE_DIM(dynf_names);
1876 }
1877
1878 /**
1879  * Comparison callback to sort device data.
1880  *
1881  * This is meant to be used with qsort().
1882  *
1883  * @param a[in]
1884  *   Pointer to pointer to first data object.
1885  * @param b[in]
1886  *   Pointer to pointer to second data object.
1887  *
1888  * @return
1889  *   0 if both objects are equal, less than 0 if the first argument is less
1890  *   than the second, greater than 0 otherwise.
1891  */
1892 int
1893 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1894                               struct mlx5_dev_config *config)
1895 {
1896         struct mlx5_dev_ctx_shared *sh = priv->sh;
1897         struct mlx5_dev_config *sh_conf = NULL;
1898         uint16_t port_id;
1899
1900         MLX5_ASSERT(sh);
1901         /* Nothing to compare for the single/first device. */
1902         if (sh->refcnt == 1)
1903                 return 0;
1904         /* Find the device with shared context. */
1905         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1906                 struct mlx5_priv *opriv =
1907                         rte_eth_devices[port_id].data->dev_private;
1908
1909                 if (opriv && opriv != priv && opriv->sh == sh) {
1910                         sh_conf = &opriv->config;
1911                         break;
1912                 }
1913         }
1914         if (!sh_conf)
1915                 return 0;
1916         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1917                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1918                              " for shared %s context", sh->ibdev_name);
1919                 rte_errno = EINVAL;
1920                 return rte_errno;
1921         }
1922         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1923                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1924                              " for shared %s context", sh->ibdev_name);
1925                 rte_errno = EINVAL;
1926                 return rte_errno;
1927         }
1928         return 0;
1929 }
1930
1931 /**
1932  * Look for the ethernet device belonging to mlx5 driver.
1933  *
1934  * @param[in] port_id
1935  *   port_id to start looking for device.
1936  * @param[in] pci_dev
1937  *   Pointer to the hint PCI device. When device is being probed
1938  *   the its siblings (master and preceding representors might
1939  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1940  *   is not completed yet, for this case match on hint PCI
1941  *   device may be used to detect sibling device.
1942  *
1943  * @return
1944  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1945  */
1946 uint16_t
1947 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1948 {
1949         while (port_id < RTE_MAX_ETHPORTS) {
1950                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1951
1952                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1953                     dev->device &&
1954                     (dev->device == &pci_dev->device ||
1955                      (dev->device->driver &&
1956                      dev->device->driver->name &&
1957                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1958                         break;
1959                 port_id++;
1960         }
1961         if (port_id >= RTE_MAX_ETHPORTS)
1962                 return RTE_MAX_ETHPORTS;
1963         return port_id;
1964 }
1965
1966 /**
1967  * DPDK callback to remove a PCI device.
1968  *
1969  * This function removes all Ethernet devices belong to a given PCI device.
1970  *
1971  * @param[in] pci_dev
1972  *   Pointer to the PCI device.
1973  *
1974  * @return
1975  *   0 on success, the function cannot fail.
1976  */
1977 static int
1978 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1979 {
1980         uint16_t port_id;
1981
1982         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1983                 /*
1984                  * mlx5_dev_close() is not registered to secondary process,
1985                  * call the close function explicitly for secondary process.
1986                  */
1987                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1988                         mlx5_dev_close(&rte_eth_devices[port_id]);
1989                 else
1990                         rte_eth_dev_close(port_id);
1991         }
1992         return 0;
1993 }
1994
1995 static const struct rte_pci_id mlx5_pci_id_map[] = {
1996         {
1997                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1998                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1999         },
2000         {
2001                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2002                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2003         },
2004         {
2005                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2006                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2007         },
2008         {
2009                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2010                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2011         },
2012         {
2013                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2014                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2015         },
2016         {
2017                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2018                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2019         },
2020         {
2021                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2022                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2023         },
2024         {
2025                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2026                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2027         },
2028         {
2029                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2030                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2031         },
2032         {
2033                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2034                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2035         },
2036         {
2037                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2038                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2039         },
2040         {
2041                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2042                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2043         },
2044         {
2045                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2046                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2047         },
2048         {
2049                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2050                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2051         },
2052         {
2053                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2054                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2055         },
2056         {
2057                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2058                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2059         },
2060         {
2061                 .vendor_id = 0
2062         }
2063 };
2064
2065 struct rte_pci_driver mlx5_driver = {
2066         .driver = {
2067                 .name = MLX5_DRIVER_NAME
2068         },
2069         .id_table = mlx5_pci_id_map,
2070         .probe = mlx5_os_pci_probe,
2071         .remove = mlx5_pci_remove,
2072         .dma_map = mlx5_dma_map,
2073         .dma_unmap = mlx5_dma_unmap,
2074         .drv_flags = PCI_DRV_FLAGS,
2075 };
2076
2077 /* Initialize driver log type. */
2078 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2079
2080 /**
2081  * Driver initialization routine.
2082  */
2083 RTE_INIT(rte_mlx5_pmd_init)
2084 {
2085         /* Build the static tables for Verbs conversion. */
2086         mlx5_set_ptype_table();
2087         mlx5_set_cksum_table();
2088         mlx5_set_swp_types_table();
2089         if (mlx5_glue)
2090                 rte_pci_register(&mlx5_driver);
2091 }
2092
2093 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2094 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2095 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");