drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_autoconf.h"
  39 #include "mlx5_mr.h"
  40 #include "mlx5_flow.h"
  41 #include "mlx5_flow_os.h"
  42 #include "rte_pmd_mlx5.h"
  43
  44 /* Device parameter to enable RX completion queue compression. */
  45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  46
  47 /* Device parameter to enable padding Rx packet to cacheline size. */
  48 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  49
  50 /* Device parameter to enable Multi-Packet Rx queue. */
  51 #define MLX5_RX_MPRQ_EN "mprq_en"
  52
  53 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  54 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  55
  56 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  57 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  58
  59 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  60 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  61
  62 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  63 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  64
  65 /* Device parameter to configure inline send. Deprecated, ignored.*/
  66 #define MLX5_TXQ_INLINE "txq_inline"
  67
  68 /* Device parameter to limit packet size to inline with ordinary SEND. */
  69 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  70
  71 /* Device parameter to configure minimal data size to inline. */
  72 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  73
  74 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  75 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  76
  77 /*
  78  * Device parameter to configure the number of TX queues threshold for
  79  * enabling inline send.
  80  */
  81 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  82
  83 /*
  84  * Device parameter to configure the number of TX queues threshold for
  85  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  86  */
  87 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  88
  89 /* Device parameter to enable multi-packet send WQEs. */
  90 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  91
  92 /*
  93  * Device parameter to force doorbell register mapping
  94  * to non-cahed region eliminating the extra write memory barrier.
  95  */
  96 #define MLX5_TX_DB_NC "tx_db_nc"
  97
  98 /*
  99  * Device parameter to include 2 dsegs in the title WQEBB.
 100  * Deprecated, ignored.
 101  */
 102 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 103
 104 /*
 105  * Device parameter to limit the size of inlining packet.
 106  * Deprecated, ignored.
 107  */
 108 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 109
 110 /*
 111  * Device parameter to enable Tx scheduling on timestamps
 112  * and specify the packet pacing granularity in nanoseconds.
 113  */
 114 #define MLX5_TX_PP "tx_pp"
 115
 116 /*
 117  * Device parameter to specify skew in nanoseconds on Tx datapath,
 118  * it represents the time between SQ start WQE processing and
 119  * appearing actual packet data on the wire.
 120  */
 121 #define MLX5_TX_SKEW "tx_skew"
 122
 123 /*
 124  * Device parameter to enable hardware Tx vector.
 125  * Deprecated, ignored (no vectorized Tx routines anymore).
 126  */
 127 #define MLX5_TX_VEC_EN "tx_vec_en"
 128
 129 /* Device parameter to enable hardware Rx vector. */
 130 #define MLX5_RX_VEC_EN "rx_vec_en"
 131
 132 /* Allow L3 VXLAN flow creation. */
 133 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 134
 135 /* Activate DV E-Switch flow steering. */
 136 #define MLX5_DV_ESW_EN "dv_esw_en"
 137
 138 /* Activate DV flow steering. */
 139 #define MLX5_DV_FLOW_EN "dv_flow_en"
 140
 141 /* Enable extensive flow metadata support. */
 142 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 143
 144 /* Device parameter to let the user manage the lacp traffic of bonded device */
 145 #define MLX5_LACP_BY_USER "lacp_by_user"
 146
 147 /* Activate Netlink support in VF mode. */
 148 #define MLX5_VF_NL_EN "vf_nl_en"
 149
 150 /* Enable extending memsegs when creating a MR. */
 151 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 152
 153 /* Select port representors to instantiate. */
 154 #define MLX5_REPRESENTOR "representor"
 155
 156 /* Device parameter to configure the maximum number of dump files per queue. */
 157 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 158
 159 /* Configure timeout of LRO session (in microseconds). */
 160 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 161
 162 /*
 163  * Device parameter to configure the total data buffer size for a single
 164  * hairpin queue (logarithm value).
 165  */
 166 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 167
 168 /* Flow memory reclaim mode. */
 169 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 170
 171 /* The default memory allocator used in PMD. */
 172 #define MLX5_SYS_MEM_EN "sys_mem_en"
 173 /* Decap will be used or not. */
 174 #define MLX5_DECAP_EN "decap_en"
 175
 176 /* Shared memory between primary and secondary processes. */
 177 struct mlx5_shared_data *mlx5_shared_data;
 178
 179 /** Driver-specific log messages type. */
 180 int mlx5_logtype;
 181
 182 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 183                                                 LIST_HEAD_INITIALIZER();
 184 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 185 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 186 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 187         [MLX5_IPOOL_DECAP_ENCAP] = {
 188                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 189                 .trunk_size = 64,
 190                 .grow_trunk = 3,
 191                 .grow_shift = 2,
 192                 .need_lock = 1,
 193                 .release_mem_en = 1,
 194                 .malloc = mlx5_malloc,
 195                 .free = mlx5_free,
 196                 .type = "mlx5_encap_decap_ipool",
 197         },
 198         [MLX5_IPOOL_PUSH_VLAN] = {
 199                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 200                 .trunk_size = 64,
 201                 .grow_trunk = 3,
 202                 .grow_shift = 2,
 203                 .need_lock = 1,
 204                 .release_mem_en = 1,
 205                 .malloc = mlx5_malloc,
 206                 .free = mlx5_free,
 207                 .type = "mlx5_push_vlan_ipool",
 208         },
 209         [MLX5_IPOOL_TAG] = {
 210                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 211                 .trunk_size = 64,
 212                 .grow_trunk = 3,
 213                 .grow_shift = 2,
 214                 .need_lock = 1,
 215                 .release_mem_en = 1,
 216                 .malloc = mlx5_malloc,
 217                 .free = mlx5_free,
 218                 .type = "mlx5_tag_ipool",
 219         },
 220         [MLX5_IPOOL_PORT_ID] = {
 221                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 222                 .trunk_size = 64,
 223                 .grow_trunk = 3,
 224                 .grow_shift = 2,
 225                 .need_lock = 1,
 226                 .release_mem_en = 1,
 227                 .malloc = mlx5_malloc,
 228                 .free = mlx5_free,
 229                 .type = "mlx5_port_id_ipool",
 230         },
 231         [MLX5_IPOOL_JUMP] = {
 232                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 233                 .trunk_size = 64,
 234                 .grow_trunk = 3,
 235                 .grow_shift = 2,
 236                 .need_lock = 1,
 237                 .release_mem_en = 1,
 238                 .malloc = mlx5_malloc,
 239                 .free = mlx5_free,
 240                 .type = "mlx5_jump_ipool",
 241         },
 242         [MLX5_IPOOL_SAMPLE] = {
 243                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 244                 .trunk_size = 64,
 245                 .grow_trunk = 3,
 246                 .grow_shift = 2,
 247                 .need_lock = 1,
 248                 .release_mem_en = 1,
 249                 .malloc = mlx5_malloc,
 250                 .free = mlx5_free,
 251                 .type = "mlx5_sample_ipool",
 252         },
 253         [MLX5_IPOOL_DEST_ARRAY] = {
 254                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 255                 .trunk_size = 64,
 256                 .grow_trunk = 3,
 257                 .grow_shift = 2,
 258                 .need_lock = 1,
 259                 .release_mem_en = 1,
 260                 .malloc = mlx5_malloc,
 261                 .free = mlx5_free,
 262                 .type = "mlx5_dest_array_ipool",
 263         },
 264         [MLX5_IPOOL_TUNNEL_ID] = {
 265                 .size = sizeof(struct mlx5_flow_tunnel),
 266                 .trunk_size = MLX5_MAX_TUNNELS,
 267                 .need_lock = 1,
 268                 .release_mem_en = 1,
 269                 .type = "mlx5_tunnel_offload",
 270         },
 271         [MLX5_IPOOL_TNL_TBL_ID] = {
 272                 .size = 0,
 273                 .need_lock = 1,
 274                 .type = "mlx5_flow_tnl_tbl_ipool",
 275         },
 276 #endif
 277         [MLX5_IPOOL_MTR] = {
 278                 .size = sizeof(struct mlx5_flow_meter),
 279                 .trunk_size = 64,
 280                 .grow_trunk = 3,
 281                 .grow_shift = 2,
 282                 .need_lock = 1,
 283                 .release_mem_en = 1,
 284                 .malloc = mlx5_malloc,
 285                 .free = mlx5_free,
 286                 .type = "mlx5_meter_ipool",
 287         },
 288         [MLX5_IPOOL_MCP] = {
 289                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 290                 .trunk_size = 64,
 291                 .grow_trunk = 3,
 292                 .grow_shift = 2,
 293                 .need_lock = 1,
 294                 .release_mem_en = 1,
 295                 .malloc = mlx5_malloc,
 296                 .free = mlx5_free,
 297                 .type = "mlx5_mcp_ipool",
 298         },
 299         [MLX5_IPOOL_HRXQ] = {
 300                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 301                 .trunk_size = 64,
 302                 .grow_trunk = 3,
 303                 .grow_shift = 2,
 304                 .need_lock = 1,
 305                 .release_mem_en = 1,
 306                 .malloc = mlx5_malloc,
 307                 .free = mlx5_free,
 308                 .type = "mlx5_hrxq_ipool",
 309         },
 310         [MLX5_IPOOL_MLX5_FLOW] = {
 311                 /*
 312                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 313                  * It set in run time according to PCI function configuration.
 314                  */
 315                 .size = 0,
 316                 .trunk_size = 64,
 317                 .grow_trunk = 3,
 318                 .grow_shift = 2,
 319                 .need_lock = 1,
 320                 .release_mem_en = 1,
 321                 .malloc = mlx5_malloc,
 322                 .free = mlx5_free,
 323                 .type = "mlx5_flow_handle_ipool",
 324         },
 325         [MLX5_IPOOL_RTE_FLOW] = {
 326                 .size = sizeof(struct rte_flow),
 327                 .trunk_size = 4096,
 328                 .need_lock = 1,
 329                 .release_mem_en = 1,
 330                 .malloc = mlx5_malloc,
 331                 .free = mlx5_free,
 332                 .type = "rte_flow_ipool",
 333         },
 334         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 335                 .size = 0,
 336                 .need_lock = 1,
 337                 .type = "mlx5_flow_rss_id_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 340                 .size = sizeof(struct mlx5_shared_action_rss),
 341                 .trunk_size = 64,
 342                 .grow_trunk = 3,
 343                 .grow_shift = 2,
 344                 .need_lock = 1,
 345                 .release_mem_en = 1,
 346                 .malloc = mlx5_malloc,
 347                 .free = mlx5_free,
 348                 .type = "mlx5_shared_action_rss",
 349         },
 350 };
 351
 352
 353 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 354 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 355
 356 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 357
 358 /**
 359  * Initialize the ASO aging management structure.
 360  *
 361  * @param[in] sh
 362  *   Pointer to mlx5_dev_ctx_shared object to free
 363  *
 364  * @return
 365  *   0 on success, a negative errno value otherwise and rte_errno is set.
 366  */
 367 int
 368 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 369 {
 370         int err;
 371
 372         if (sh->aso_age_mng)
 373                 return 0;
 374         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 375                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 376         if (!sh->aso_age_mng) {
 377                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 378                 rte_errno = ENOMEM;
 379                 return -ENOMEM;
 380         }
 381         err = mlx5_aso_queue_init(sh);
 382         if (err) {
 383                 mlx5_free(sh->aso_age_mng);
 384                 return -1;
 385         }
 386         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 387         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 388         LIST_INIT(&sh->aso_age_mng->free);
 389         return 0;
 390 }
 391
 392 /**
 393  * Close and release all the resources of the ASO aging management structure.
 394  *
 395  * @param[in] sh
 396  *   Pointer to mlx5_dev_ctx_shared object to free.
 397  */
 398 static void
 399 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 400 {
 401         int i, j;
 402
 403         mlx5_aso_queue_stop(sh);
 404         mlx5_aso_queue_uninit(sh);
 405         if (sh->aso_age_mng->pools) {
 406                 struct mlx5_aso_age_pool *pool;
 407
 408                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 409                         pool = sh->aso_age_mng->pools[i];
 410                         claim_zero(mlx5_devx_cmd_destroy
 411                                                 (pool->flow_hit_aso_obj));
 412                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 413                                 if (pool->actions[j].dr_action)
 414                                         claim_zero
 415                                             (mlx5_flow_os_destroy_flow_action
 416                                               (pool->actions[j].dr_action));
 417                         mlx5_free(pool);
 418                 }
 419                 mlx5_free(sh->aso_age_mng->pools);
 420         }
 421         mlx5_free(sh->aso_age_mng);
 422 }
 423
 424 /**
 425  * Initialize the shared aging list information per port.
 426  *
 427  * @param[in] sh
 428  *   Pointer to mlx5_dev_ctx_shared object.
 429  */
 430 static void
 431 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 432 {
 433         uint32_t i;
 434         struct mlx5_age_info *age_info;
 435
 436         for (i = 0; i < sh->max_port; i++) {
 437                 age_info = &sh->port[i].age_info;
 438                 age_info->flags = 0;
 439                 TAILQ_INIT(&age_info->aged_counters);
 440                 LIST_INIT(&age_info->aged_aso);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 460         sh->cmng.max_id = -1;
 461         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 462         rte_spinlock_init(&sh->cmng.pool_update_sl);
 463         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 464                 TAILQ_INIT(&sh->cmng.counters[i]);
 465                 rte_spinlock_init(&sh->cmng.csl[i]);
 466         }
 467 }
 468
 469 /**
 470  * Destroy all the resources allocated for a counter memory management.
 471  *
 472  * @param[in] mng
 473  *   Pointer to the memory management structure.
 474  */
 475 static void
 476 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 477 {
 478         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 479
 480         LIST_REMOVE(mng, next);
 481         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 482         claim_zero(mlx5_os_umem_dereg(mng->umem));
 483         mlx5_free(mem);
 484 }
 485
 486 /**
 487  * Close and release all the resources of the counters management.
 488  *
 489  * @param[in] sh
 490  *   Pointer to mlx5_dev_ctx_shared object to free.
 491  */
 492 static void
 493 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 494 {
 495         struct mlx5_counter_stats_mem_mng *mng;
 496         int i, j;
 497         int retries = 1024;
 498
 499         rte_errno = 0;
 500         while (--retries) {
 501                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 502                 if (rte_errno != EINPROGRESS)
 503                         break;
 504                 rte_pause();
 505         }
 506
 507         if (sh->cmng.pools) {
 508                 struct mlx5_flow_counter_pool *pool;
 509                 uint16_t n_valid = sh->cmng.n_valid;
 510                 bool fallback = sh->cmng.counter_fallback;
 511
 512                 for (i = 0; i < n_valid; ++i) {
 513                         pool = sh->cmng.pools[i];
 514                         if (!fallback && pool->min_dcs)
 515                                 claim_zero(mlx5_devx_cmd_destroy
 516                                                                (pool->min_dcs));
 517                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 518                                 struct mlx5_flow_counter *cnt =
 519                                                 MLX5_POOL_GET_CNT(pool, j);
 520
 521                                 if (cnt->action)
 522                                         claim_zero
 523                                          (mlx5_flow_os_destroy_flow_action
 524                                           (cnt->action));
 525                                 if (fallback && MLX5_POOL_GET_CNT
 526                                     (pool, j)->dcs_when_free)
 527                                         claim_zero(mlx5_devx_cmd_destroy
 528                                                    (cnt->dcs_when_free));
 529                         }
 530                         mlx5_free(pool);
 531                 }
 532                 mlx5_free(sh->cmng.pools);
 533         }
 534         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 535         while (mng) {
 536                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 537                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 538         }
 539         memset(&sh->cmng, 0, sizeof(sh->cmng));
 540 }
 541
 542 /* Send FLOW_AGED event if needed. */
 543 void
 544 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 545 {
 546         struct mlx5_age_info *age_info;
 547         uint32_t i;
 548
 549         for (i = 0; i < sh->max_port; i++) {
 550                 age_info = &sh->port[i].age_info;
 551                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 552                         continue;
 553                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 554                         rte_eth_dev_callback_process
 555                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 556                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 557                 age_info->flags = 0;
 558         }
 559 }
 560
 561 /**
 562  * Initialize the flow resources' indexed mempool.
 563  *
 564  * @param[in] sh
 565  *   Pointer to mlx5_dev_ctx_shared object.
 566  * @param[in] sh
 567  *   Pointer to user dev config.
 568  */
 569 static void
 570 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 571                        const struct mlx5_dev_config *config)
 572 {
 573         uint8_t i;
 574         struct mlx5_indexed_pool_config cfg;
 575
 576         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 577                 cfg = mlx5_ipool_cfg[i];
 578                 switch (i) {
 579                 default:
 580                         break;
 581                 /*
 582                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 583                  * according to PCI function flow configuration.
 584                  */
 585                 case MLX5_IPOOL_MLX5_FLOW:
 586                         cfg.size = config->dv_flow_en ?
 587                                 sizeof(struct mlx5_flow_handle) :
 588                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 589                         break;
 590                 }
 591                 if (config->reclaim_mode)
 592                         cfg.release_mem_en = 1;
 593                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 594         }
 595 }
 596
 597 /**
 598  * Release the flow resources' indexed mempool.
 599  *
 600  * @param[in] sh
 601  *   Pointer to mlx5_dev_ctx_shared object.
 602  */
 603 static void
 604 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 605 {
 606         uint8_t i;
 607
 608         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 609                 mlx5_ipool_destroy(sh->ipool[i]);
 610 }
 611
 612 /*
 613  * Check if dynamic flex parser for eCPRI already exists.
 614  *
 615  * @param dev
 616  *   Pointer to Ethernet device structure.
 617  *
 618  * @return
 619  *   true on exists, false on not.
 620  */
 621 bool
 622 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 623 {
 624         struct mlx5_priv *priv = dev->data->dev_private;
 625         struct mlx5_flex_parser_profiles *prf =
 626                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 627
 628         return !!prf->obj;
 629 }
 630
 631 /*
 632  * Allocation of a flex parser for eCPRI. Once created, this parser related
 633  * resources will be held until the device is closed.
 634  *
 635  * @param dev
 636  *   Pointer to Ethernet device structure.
 637  *
 638  * @return
 639  *   0 on success, a negative errno value otherwise and rte_errno is set.
 640  */
 641 int
 642 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 643 {
 644         struct mlx5_priv *priv = dev->data->dev_private;
 645         struct mlx5_flex_parser_profiles *prf =
 646                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 647         struct mlx5_devx_graph_node_attr node = {
 648                 .modify_field_select = 0,
 649         };
 650         uint32_t ids[8];
 651         int ret;
 652
 653         if (!priv->config.hca_attr.parse_graph_flex_node) {
 654                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 655                         "for device %s.", priv->dev_data->name);
 656                 return -ENOTSUP;
 657         }
 658         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 659         /* 8 bytes now: 4B common header + 4B message body header. */
 660         node.header_length_base_value = 0x8;
 661         /* After MAC layer: Ether / VLAN. */
 662         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 663         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 664         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 665         /* Sample #0: type in common header. */
 666         node.sample[0].flow_match_sample_en = 1;
 667         /* Fixed offset. */
 668         node.sample[0].flow_match_sample_offset_mode = 0x0;
 669         /* Only the 2nd byte will be used. */
 670         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 671         /* Sample #1: message payload. */
 672         node.sample[1].flow_match_sample_en = 1;
 673         /* Fixed offset. */
 674         node.sample[1].flow_match_sample_offset_mode = 0x0;
 675         /*
 676          * Only the first two bytes will be used right now, and its offset will
 677          * start after the common header that with the length of a DW(u32).
 678          */
 679         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 680         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 681         if (!prf->obj) {
 682                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 683                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 684         }
 685         prf->num = 2;
 686         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 687         if (ret) {
 688                 DRV_LOG(ERR, "Failed to query sample IDs.");
 689                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 690         }
 691         prf->offset[0] = 0x0;
 692         prf->offset[1] = sizeof(uint32_t);
 693         prf->ids[0] = ids[0];
 694         prf->ids[1] = ids[1];
 695         return 0;
 696 }
 697
 698 /*
 699  * Destroy the flex parser node, including the parser itself, input / output
 700  * arcs and DW samples. Resources could be reused then.
 701  *
 702  * @param dev
 703  *   Pointer to Ethernet device structure.
 704  */
 705 static void
 706 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 707 {
 708         struct mlx5_priv *priv = dev->data->dev_private;
 709         struct mlx5_flex_parser_profiles *prf =
 710                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 711
 712         if (prf->obj)
 713                 mlx5_devx_cmd_destroy(prf->obj);
 714         prf->obj = NULL;
 715 }
 716
 717 /*
 718  * Allocate Rx and Tx UARs in robust fashion.
 719  * This routine handles the following UAR allocation issues:
 720  *
 721  *  - tries to allocate the UAR with the most appropriate memory
 722  *    mapping type from the ones supported by the host
 723  *
 724  *  - tries to allocate the UAR with non-NULL base address
 725  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 726  *    UAR base address if UAR was not the first object in the UAR page.
 727  *    It caused the PMD failure and we should try to get another UAR
 728  *    till we get the first one with non-NULL base address returned.
 729  */
 730 static int
 731 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 732                      const struct mlx5_dev_config *config)
 733 {
 734         uint32_t uar_mapping, retry;
 735         int err = 0;
 736         void *base_addr;
 737
 738         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 739 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 740                 /* Control the mapping type according to the settings. */
 741                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 742                               MLX5DV_UAR_ALLOC_TYPE_NC :
 743                               MLX5DV_UAR_ALLOC_TYPE_BF;
 744 #else
 745                 RTE_SET_USED(config);
 746                 /*
 747                  * It seems we have no way to control the memory mapping type
 748                  * for the UAR, the default "Write-Combining" type is supposed.
 749                  * The UAR initialization on queue creation queries the
 750                  * actual mapping type done by Verbs/kernel and setups the
 751                  * PMD datapath accordingly.
 752                  */
 753                 uar_mapping = 0;
 754 #endif
 755                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 756 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 757                 if (!sh->tx_uar &&
 758                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 759                         if (config->dbnc == MLX5_TXDB_CACHED ||
 760                             config->dbnc == MLX5_TXDB_HEURISTIC)
 761                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 762                                                  "is not supported by DevX");
 763                         /*
 764                          * In some environments like virtual machine
 765                          * the Write Combining mapped might be not supported
 766                          * and UAR allocation fails. We try "Non-Cached"
 767                          * mapping for the case. The tx_burst routines take
 768                          * the UAR mapping type into account on UAR setup
 769                          * on queue creation.
 770                          */
 771                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
 772                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 773                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 774                                                         (sh->ctx, uar_mapping);
 775                 } else if (!sh->tx_uar &&
 776                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 777                         if (config->dbnc == MLX5_TXDB_NCACHED)
 778                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 779                                                  "is not supported by DevX");
 780                         /*
 781                          * If Verbs/kernel does not support "Non-Cached"
 782                          * try the "Write-Combining".
 783                          */
 784                         DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
 785                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 786                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 787                                                         (sh->ctx, uar_mapping);
 788                 }
 789 #endif
 790                 if (!sh->tx_uar) {
 791                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 792                         err = ENOMEM;
 793                         goto exit;
 794                 }
 795                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 796                 if (base_addr)
 797                         break;
 798                 /*
 799                  * The UARs are allocated by rdma_core within the
 800                  * IB device context, on context closure all UARs
 801                  * will be freed, should be no memory/object leakage.
 802                  */
 803                 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
 804                 sh->tx_uar = NULL;
 805         }
 806         /* Check whether we finally succeeded with valid UAR allocation. */
 807         if (!sh->tx_uar) {
 808                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 809                 err = ENOMEM;
 810                 goto exit;
 811         }
 812         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 813                 uar_mapping = 0;
 814                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 815                                                         (sh->ctx, uar_mapping);
 816 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 817                 if (!sh->devx_rx_uar &&
 818                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 819                         /*
 820                          * Rx UAR is used to control interrupts only,
 821                          * should be no datapath noticeable impact,
 822                          * can try "Non-Cached" mapping safely.
 823                          */
 824                         DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
 825                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 826                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 827                                                         (sh->ctx, uar_mapping);
 828                 }
 829 #endif
 830                 if (!sh->devx_rx_uar) {
 831                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 832                         err = ENOMEM;
 833                         goto exit;
 834                 }
 835                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 836                 if (base_addr)
 837                         break;
 838                 /*
 839                  * The UARs are allocated by rdma_core within the
 840                  * IB device context, on context closure all UARs
 841                  * will be freed, should be no memory/object leakage.
 842                  */
 843                 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
 844                 sh->devx_rx_uar = NULL;
 845         }
 846         /* Check whether we finally succeeded with valid UAR allocation. */
 847         if (!sh->devx_rx_uar) {
 848                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 849                 err = ENOMEM;
 850         }
 851 exit:
 852         return err;
 853 }
 854
 855 /**
 856  * Allocate shared device context. If there is multiport device the
 857  * master and representors will share this context, if there is single
 858  * port dedicated device, the context will be used by only given
 859  * port due to unification.
 860  *
 861  * Routine first searches the context for the specified device name,
 862  * if found the shared context assumed and reference counter is incremented.
 863  * If no context found the new one is created and initialized with specified
 864  * device context and parameters.
 865  *
 866  * @param[in] spawn
 867  *   Pointer to the device attributes (name, port, etc).
 868  * @param[in] config
 869  *   Pointer to device configuration structure.
 870  *
 871  * @return
 872  *   Pointer to mlx5_dev_ctx_shared object on success,
 873  *   otherwise NULL and rte_errno is set.
 874  */
 875 struct mlx5_dev_ctx_shared *
 876 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 877                            const struct mlx5_dev_config *config)
 878 {
 879         struct mlx5_dev_ctx_shared *sh;
 880         int err = 0;
 881         uint32_t i;
 882         struct mlx5_devx_tis_attr tis_attr = { 0 };
 883
 884         MLX5_ASSERT(spawn);
 885         /* Secondary process should not create the shared context. */
 886         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 887         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 888         /* Search for IB context by device name. */
 889         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 890                 if (!strcmp(sh->ibdev_name,
 891                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 892                         sh->refcnt++;
 893                         goto exit;
 894                 }
 895         }
 896         /* No device found, we have to create new shared context. */
 897         MLX5_ASSERT(spawn->max_port);
 898         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
 899                          sizeof(struct mlx5_dev_ctx_shared) +
 900                          spawn->max_port *
 901                          sizeof(struct mlx5_dev_shared_port),
 902                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 903         if (!sh) {
 904                 DRV_LOG(ERR, "shared context allocation failure");
 905                 rte_errno  = ENOMEM;
 906                 goto exit;
 907         }
 908         err = mlx5_os_open_device(spawn, config, sh);
 909         if (!sh->ctx)
 910                 goto error;
 911         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 912         if (err) {
 913                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 914                 goto error;
 915         }
 916         sh->refcnt = 1;
 917         sh->bond_dev = UINT16_MAX;
 918         sh->max_port = spawn->max_port;
 919         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 920                 sizeof(sh->ibdev_name) - 1);
 921         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 922                 sizeof(sh->ibdev_path) - 1);
 923         /*
 924          * Setting port_id to max unallowed value means
 925          * there is no interrupt subhandler installed for
 926          * the given port index i.
 927          */
 928         for (i = 0; i < sh->max_port; i++) {
 929                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 930                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 931         }
 932         sh->pd = mlx5_os_alloc_pd(sh->ctx);
 933         if (sh->pd == NULL) {
 934                 DRV_LOG(ERR, "PD allocation failure");
 935                 err = ENOMEM;
 936                 goto error;
 937         }
 938         if (sh->devx) {
 939                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 940                 if (err) {
 941                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 942                         goto error;
 943                 }
 944                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 945                 if (!sh->td) {
 946                         DRV_LOG(ERR, "TD allocation failure");
 947                         err = ENOMEM;
 948                         goto error;
 949                 }
 950                 tis_attr.transport_domain = sh->td->id;
 951                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 952                 if (!sh->tis) {
 953                         DRV_LOG(ERR, "TIS allocation failure");
 954                         err = ENOMEM;
 955                         goto error;
 956                 }
 957                 err = mlx5_alloc_rxtx_uars(sh, config);
 958                 if (err)
 959                         goto error;
 960                 MLX5_ASSERT(sh->tx_uar);
 961                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
 962
 963                 MLX5_ASSERT(sh->devx_rx_uar);
 964                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
 965         }
 966 #ifndef RTE_ARCH_64
 967         /* Initialize UAR access locks for 32bit implementations. */
 968         rte_spinlock_init(&sh->uar_lock_cq);
 969         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 970                 rte_spinlock_init(&sh->uar_lock[i]);
 971 #endif
 972         /*
 973          * Once the device is added to the list of memory event
 974          * callback, its global MR cache table cannot be expanded
 975          * on the fly because of deadlock. If it overflows, lookup
 976          * should be done by searching MR list linearly, which is slow.
 977          *
 978          * At this point the device is not added to the memory
 979          * event list yet, context is just being created.
 980          */
 981         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 982                                  MLX5_MR_BTREE_CACHE_N * 2,
 983                                  spawn->pci_dev->device.numa_node);
 984         if (err) {
 985                 err = rte_errno;
 986                 goto error;
 987         }
 988         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 989                               &sh->share_cache.dereg_mr_cb);
 990         mlx5_os_dev_shared_handler_install(sh);
 991         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 992         if (!sh->cnt_id_tbl) {
 993                 err = rte_errno;
 994                 goto error;
 995         }
 996         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
 997                 err = mlx5_flow_os_init_workspace_once();
 998                 if (err)
 999                         goto error;
1000         }
1001         mlx5_flow_aging_init(sh);
1002         mlx5_flow_counters_mng_init(sh);
1003         mlx5_flow_ipool_create(sh, config);
1004         /* Add device to memory callback list. */
1005         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1006         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1007                          sh, mem_event_cb);
1008         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1009         /* Add context to the global device list. */
1010         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1011 exit:
1012         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1013         return sh;
1014 error:
1015         pthread_mutex_destroy(&sh->txpp.mutex);
1016         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1017         MLX5_ASSERT(sh);
1018         if (sh->cnt_id_tbl)
1019                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1020         if (sh->tis)
1021                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1022         if (sh->td)
1023                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1024         if (sh->devx_rx_uar)
1025                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1026         if (sh->tx_uar)
1027                 mlx5_glue->devx_free_uar(sh->tx_uar);
1028         if (sh->pd)
1029                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1030         if (sh->ctx)
1031                 claim_zero(mlx5_glue->close_device(sh->ctx));
1032         mlx5_free(sh);
1033         MLX5_ASSERT(err > 0);
1034         rte_errno = err;
1035         return NULL;
1036 }
1037
1038 /**
1039  * Free shared IB device context. Decrement counter and if zero free
1040  * all allocated resources and close handles.
1041  *
1042  * @param[in] sh
1043  *   Pointer to mlx5_dev_ctx_shared object to free
1044  */
1045 void
1046 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1047 {
1048         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1049 #ifdef RTE_LIBRTE_MLX5_DEBUG
1050         /* Check the object presence in the list. */
1051         struct mlx5_dev_ctx_shared *lctx;
1052
1053         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1054                 if (lctx == sh)
1055                         break;
1056         MLX5_ASSERT(lctx);
1057         if (lctx != sh) {
1058                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1059                 goto exit;
1060         }
1061 #endif
1062         MLX5_ASSERT(sh);
1063         MLX5_ASSERT(sh->refcnt);
1064         /* Secondary process should not free the shared context. */
1065         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1066         if (--sh->refcnt)
1067                 goto exit;
1068         /* Remove from memory callback device list. */
1069         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1070         LIST_REMOVE(sh, mem_event_cb);
1071         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1072         /* Release created Memory Regions. */
1073         mlx5_mr_release_cache(&sh->share_cache);
1074         /* Remove context from the global device list. */
1075         LIST_REMOVE(sh, next);
1076         /* Release flow workspaces objects on the last device. */
1077         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1078                 mlx5_flow_os_release_workspace();
1079         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1080         /*
1081          *  Ensure there is no async event handler installed.
1082          *  Only primary process handles async device events.
1083          **/
1084         mlx5_flow_counters_mng_close(sh);
1085         if (sh->aso_age_mng) {
1086                 mlx5_flow_aso_age_mng_close(sh);
1087                 sh->aso_age_mng = NULL;
1088         }
1089         mlx5_flow_ipool_destroy(sh);
1090         mlx5_os_dev_shared_handler_uninstall(sh);
1091         if (sh->cnt_id_tbl) {
1092                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1093                 sh->cnt_id_tbl = NULL;
1094         }
1095         if (sh->tx_uar) {
1096                 mlx5_glue->devx_free_uar(sh->tx_uar);
1097                 sh->tx_uar = NULL;
1098         }
1099         if (sh->pd)
1100                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1101         if (sh->tis)
1102                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1103         if (sh->td)
1104                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1105         if (sh->devx_rx_uar)
1106                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1107         if (sh->ctx)
1108                 claim_zero(mlx5_glue->close_device(sh->ctx));
1109         pthread_mutex_destroy(&sh->txpp.mutex);
1110         mlx5_free(sh);
1111         return;
1112 exit:
1113         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1114 }
1115
1116 /**
1117  * Destroy table hash list.
1118  *
1119  * @param[in] priv
1120  *   Pointer to the private device data structure.
1121  */
1122 void
1123 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1124 {
1125         struct mlx5_dev_ctx_shared *sh = priv->sh;
1126
1127         if (!sh->flow_tbls)
1128                 return;
1129         mlx5_hlist_destroy(sh->flow_tbls);
1130 }
1131
1132 /**
1133  * Initialize flow table hash list and create the root tables entry
1134  * for each domain.
1135  *
1136  * @param[in] priv
1137  *   Pointer to the private device data structure.
1138  *
1139  * @return
1140  *   Zero on success, positive error code otherwise.
1141  */
1142 int
1143 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1144 {
1145         int err = 0;
1146         /* Tables are only used in DV and DR modes. */
1147 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1148         struct mlx5_dev_ctx_shared *sh = priv->sh;
1149         char s[MLX5_HLIST_NAMESIZE];
1150
1151         MLX5_ASSERT(sh);
1152         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1153         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1154                                           0, 0, flow_dv_tbl_create_cb,
1155                                           flow_dv_tbl_match_cb,
1156                                           flow_dv_tbl_remove_cb);
1157         if (!sh->flow_tbls) {
1158                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1159                 err = ENOMEM;
1160                 return err;
1161         }
1162         sh->flow_tbls->ctx = sh;
1163 #ifndef HAVE_MLX5DV_DR
1164         struct rte_flow_error error;
1165         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1166
1167         /*
1168          * In case we have not DR support, the zero tables should be created
1169          * because DV expect to see them even if they cannot be created by
1170          * RDMA-CORE.
1171          */
1172         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1173             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1174             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1175                 err = ENOMEM;
1176                 goto error;
1177         }
1178         return err;
1179 error:
1180         mlx5_free_table_hash_list(priv);
1181 #endif /* HAVE_MLX5DV_DR */
1182 #endif
1183         return err;
1184 }
1185
1186 /**
1187  * Retrieve integer value from environment variable.
1188  *
1189  * @param[in] name
1190  *   Environment variable name.
1191  *
1192  * @return
1193  *   Integer value, 0 if the variable is not set.
1194  */
1195 int
1196 mlx5_getenv_int(const char *name)
1197 {
1198         const char *val = getenv(name);
1199
1200         if (val == NULL)
1201                 return 0;
1202         return atoi(val);
1203 }
1204
1205 /**
1206  * DPDK callback to add udp tunnel port
1207  *
1208  * @param[in] dev
1209  *   A pointer to eth_dev
1210  * @param[in] udp_tunnel
1211  *   A pointer to udp tunnel
1212  *
1213  * @return
1214  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1215  */
1216 int
1217 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1218                          struct rte_eth_udp_tunnel *udp_tunnel)
1219 {
1220         MLX5_ASSERT(udp_tunnel != NULL);
1221         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1222             udp_tunnel->udp_port == 4789)
1223                 return 0;
1224         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1225             udp_tunnel->udp_port == 4790)
1226                 return 0;
1227         return -ENOTSUP;
1228 }
1229
1230 /**
1231  * Initialize process private data structure.
1232  *
1233  * @param dev
1234  *   Pointer to Ethernet device structure.
1235  *
1236  * @return
1237  *   0 on success, a negative errno value otherwise and rte_errno is set.
1238  */
1239 int
1240 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1241 {
1242         struct mlx5_priv *priv = dev->data->dev_private;
1243         struct mlx5_proc_priv *ppriv;
1244         size_t ppriv_size;
1245
1246         /*
1247          * UAR register table follows the process private structure. BlueFlame
1248          * registers for Tx queues are stored in the table.
1249          */
1250         ppriv_size =
1251                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1252         ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1253                             dev->device->numa_node);
1254         if (!ppriv) {
1255                 rte_errno = ENOMEM;
1256                 return -rte_errno;
1257         }
1258         ppriv->uar_table_sz = ppriv_size;
1259         dev->process_private = ppriv;
1260         return 0;
1261 }
1262
1263 /**
1264  * Un-initialize process private data structure.
1265  *
1266  * @param dev
1267  *   Pointer to Ethernet device structure.
1268  */
1269 static void
1270 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1271 {
1272         if (!dev->process_private)
1273                 return;
1274         mlx5_free(dev->process_private);
1275         dev->process_private = NULL;
1276 }
1277
1278 /**
1279  * DPDK callback to close the device.
1280  *
1281  * Destroy all queues and objects, free memory.
1282  *
1283  * @param dev
1284  *   Pointer to Ethernet device structure.
1285  */
1286 int
1287 mlx5_dev_close(struct rte_eth_dev *dev)
1288 {
1289         struct mlx5_priv *priv = dev->data->dev_private;
1290         unsigned int i;
1291         int ret;
1292
1293         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1294                 /* Check if process_private released. */
1295                 if (!dev->process_private)
1296                         return 0;
1297                 mlx5_tx_uar_uninit_secondary(dev);
1298                 mlx5_proc_priv_uninit(dev);
1299                 rte_eth_dev_release_port(dev);
1300                 return 0;
1301         }
1302         if (!priv->sh)
1303                 return 0;
1304         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1305                 dev->data->port_id,
1306                 ((priv->sh->ctx != NULL) ?
1307                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1308         /*
1309          * If default mreg copy action is removed at the stop stage,
1310          * the search will return none and nothing will be done anymore.
1311          */
1312         mlx5_flow_stop_default(dev);
1313         mlx5_traffic_disable(dev);
1314         /*
1315          * If all the flows are already flushed in the device stop stage,
1316          * then this will return directly without any action.
1317          */
1318         mlx5_flow_list_flush(dev, &priv->flows, true);
1319         mlx5_shared_action_flush(dev);
1320         mlx5_flow_meter_flush(dev, NULL);
1321         /* Prevent crashes when queues are still in use. */
1322         dev->rx_pkt_burst = removed_rx_burst;
1323         dev->tx_pkt_burst = removed_tx_burst;
1324         rte_wmb();
1325         /* Disable datapath on secondary process. */
1326         mlx5_mp_os_req_stop_rxtx(dev);
1327         /* Free the eCPRI flex parser resource. */
1328         mlx5_flex_parser_ecpri_release(dev);
1329         if (priv->rxqs != NULL) {
1330                 /* XXX race condition if mlx5_rx_burst() is still running. */
1331                 rte_delay_us_sleep(1000);
1332                 for (i = 0; (i != priv->rxqs_n); ++i)
1333                         mlx5_rxq_release(dev, i);
1334                 priv->rxqs_n = 0;
1335                 priv->rxqs = NULL;
1336         }
1337         if (priv->txqs != NULL) {
1338                 /* XXX race condition if mlx5_tx_burst() is still running. */
1339                 rte_delay_us_sleep(1000);
1340                 for (i = 0; (i != priv->txqs_n); ++i)
1341                         mlx5_txq_release(dev, i);
1342                 priv->txqs_n = 0;
1343                 priv->txqs = NULL;
1344         }
1345         mlx5_proc_priv_uninit(dev);
1346         if (priv->drop_queue.hrxq)
1347                 mlx5_drop_action_destroy(dev);
1348         if (priv->mreg_cp_tbl)
1349                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1350         mlx5_mprq_free_mp(dev);
1351         mlx5_os_free_shared_dr(priv);
1352         if (priv->rss_conf.rss_key != NULL)
1353                 mlx5_free(priv->rss_conf.rss_key);
1354         if (priv->reta_idx != NULL)
1355                 mlx5_free(priv->reta_idx);
1356         if (priv->config.vf)
1357                 mlx5_os_mac_addr_flush(dev);
1358         if (priv->nl_socket_route >= 0)
1359                 close(priv->nl_socket_route);
1360         if (priv->nl_socket_rdma >= 0)
1361                 close(priv->nl_socket_rdma);
1362         if (priv->vmwa_context)
1363                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1364         ret = mlx5_hrxq_verify(dev);
1365         if (ret)
1366                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1367                         dev->data->port_id);
1368         ret = mlx5_ind_table_obj_verify(dev);
1369         if (ret)
1370                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1371                         dev->data->port_id);
1372         ret = mlx5_rxq_obj_verify(dev);
1373         if (ret)
1374                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1375                         dev->data->port_id);
1376         ret = mlx5_rxq_verify(dev);
1377         if (ret)
1378                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1379                         dev->data->port_id);
1380         ret = mlx5_txq_obj_verify(dev);
1381         if (ret)
1382                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1383                         dev->data->port_id);
1384         ret = mlx5_txq_verify(dev);
1385         if (ret)
1386                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1387                         dev->data->port_id);
1388         ret = mlx5_flow_verify(dev);
1389         if (ret)
1390                 DRV_LOG(WARNING, "port %u some flows still remain",
1391                         dev->data->port_id);
1392         mlx5_cache_list_destroy(&priv->hrxqs);
1393         /*
1394          * Free the shared context in last turn, because the cleanup
1395          * routines above may use some shared fields, like
1396          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1397          * ifindex if Netlink fails.
1398          */
1399         mlx5_free_shared_dev_ctx(priv->sh);
1400         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1401                 unsigned int c = 0;
1402                 uint16_t port_id;
1403
1404                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1405                         struct mlx5_priv *opriv =
1406                                 rte_eth_devices[port_id].data->dev_private;
1407
1408                         if (!opriv ||
1409                             opriv->domain_id != priv->domain_id ||
1410                             &rte_eth_devices[port_id] == dev)
1411                                 continue;
1412                         ++c;
1413                         break;
1414                 }
1415                 if (!c)
1416                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1417         }
1418         memset(priv, 0, sizeof(*priv));
1419         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1420         /*
1421          * Reset mac_addrs to NULL such that it is not freed as part of
1422          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1423          * it is freed when dev_private is freed.
1424          */
1425         dev->data->mac_addrs = NULL;
1426         return 0;
1427 }
1428
1429 const struct eth_dev_ops mlx5_dev_ops = {
1430         .dev_configure = mlx5_dev_configure,
1431         .dev_start = mlx5_dev_start,
1432         .dev_stop = mlx5_dev_stop,
1433         .dev_set_link_down = mlx5_set_link_down,
1434         .dev_set_link_up = mlx5_set_link_up,
1435         .dev_close = mlx5_dev_close,
1436         .promiscuous_enable = mlx5_promiscuous_enable,
1437         .promiscuous_disable = mlx5_promiscuous_disable,
1438         .allmulticast_enable = mlx5_allmulticast_enable,
1439         .allmulticast_disable = mlx5_allmulticast_disable,
1440         .link_update = mlx5_link_update,
1441         .stats_get = mlx5_stats_get,
1442         .stats_reset = mlx5_stats_reset,
1443         .xstats_get = mlx5_xstats_get,
1444         .xstats_reset = mlx5_xstats_reset,
1445         .xstats_get_names = mlx5_xstats_get_names,
1446         .fw_version_get = mlx5_fw_version_get,
1447         .dev_infos_get = mlx5_dev_infos_get,
1448         .read_clock = mlx5_txpp_read_clock,
1449         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1450         .vlan_filter_set = mlx5_vlan_filter_set,
1451         .rx_queue_setup = mlx5_rx_queue_setup,
1452         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1453         .tx_queue_setup = mlx5_tx_queue_setup,
1454         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1455         .rx_queue_release = mlx5_rx_queue_release,
1456         .tx_queue_release = mlx5_tx_queue_release,
1457         .rx_queue_start = mlx5_rx_queue_start,
1458         .rx_queue_stop = mlx5_rx_queue_stop,
1459         .tx_queue_start = mlx5_tx_queue_start,
1460         .tx_queue_stop = mlx5_tx_queue_stop,
1461         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1462         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1463         .mac_addr_remove = mlx5_mac_addr_remove,
1464         .mac_addr_add = mlx5_mac_addr_add,
1465         .mac_addr_set = mlx5_mac_addr_set,
1466         .set_mc_addr_list = mlx5_set_mc_addr_list,
1467         .mtu_set = mlx5_dev_set_mtu,
1468         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1469         .vlan_offload_set = mlx5_vlan_offload_set,
1470         .reta_update = mlx5_dev_rss_reta_update,
1471         .reta_query = mlx5_dev_rss_reta_query,
1472         .rss_hash_update = mlx5_rss_hash_update,
1473         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1474         .filter_ctrl = mlx5_dev_filter_ctrl,
1475         .rxq_info_get = mlx5_rxq_info_get,
1476         .txq_info_get = mlx5_txq_info_get,
1477         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1478         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1479         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1480         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1481         .is_removed = mlx5_is_removed,
1482         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1483         .get_module_info = mlx5_get_module_info,
1484         .get_module_eeprom = mlx5_get_module_eeprom,
1485         .hairpin_cap_get = mlx5_hairpin_cap_get,
1486         .mtr_ops_get = mlx5_flow_meter_ops_get,
1487         .hairpin_bind = mlx5_hairpin_bind,
1488         .hairpin_unbind = mlx5_hairpin_unbind,
1489         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1490         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1491         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1492         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1493 };
1494
1495 /* Available operations from secondary process. */
1496 const struct eth_dev_ops mlx5_dev_sec_ops = {
1497         .stats_get = mlx5_stats_get,
1498         .stats_reset = mlx5_stats_reset,
1499         .xstats_get = mlx5_xstats_get,
1500         .xstats_reset = mlx5_xstats_reset,
1501         .xstats_get_names = mlx5_xstats_get_names,
1502         .fw_version_get = mlx5_fw_version_get,
1503         .dev_infos_get = mlx5_dev_infos_get,
1504         .read_clock = mlx5_txpp_read_clock,
1505         .rx_queue_start = mlx5_rx_queue_start,
1506         .rx_queue_stop = mlx5_rx_queue_stop,
1507         .tx_queue_start = mlx5_tx_queue_start,
1508         .tx_queue_stop = mlx5_tx_queue_stop,
1509         .rxq_info_get = mlx5_rxq_info_get,
1510         .txq_info_get = mlx5_txq_info_get,
1511         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1512         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1513         .get_module_info = mlx5_get_module_info,
1514         .get_module_eeprom = mlx5_get_module_eeprom,
1515 };
1516
1517 /* Available operations in flow isolated mode. */
1518 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1519         .dev_configure = mlx5_dev_configure,
1520         .dev_start = mlx5_dev_start,
1521         .dev_stop = mlx5_dev_stop,
1522         .dev_set_link_down = mlx5_set_link_down,
1523         .dev_set_link_up = mlx5_set_link_up,
1524         .dev_close = mlx5_dev_close,
1525         .promiscuous_enable = mlx5_promiscuous_enable,
1526         .promiscuous_disable = mlx5_promiscuous_disable,
1527         .allmulticast_enable = mlx5_allmulticast_enable,
1528         .allmulticast_disable = mlx5_allmulticast_disable,
1529         .link_update = mlx5_link_update,
1530         .stats_get = mlx5_stats_get,
1531         .stats_reset = mlx5_stats_reset,
1532         .xstats_get = mlx5_xstats_get,
1533         .xstats_reset = mlx5_xstats_reset,
1534         .xstats_get_names = mlx5_xstats_get_names,
1535         .fw_version_get = mlx5_fw_version_get,
1536         .dev_infos_get = mlx5_dev_infos_get,
1537         .read_clock = mlx5_txpp_read_clock,
1538         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1539         .vlan_filter_set = mlx5_vlan_filter_set,
1540         .rx_queue_setup = mlx5_rx_queue_setup,
1541         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1542         .tx_queue_setup = mlx5_tx_queue_setup,
1543         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1544         .rx_queue_release = mlx5_rx_queue_release,
1545         .tx_queue_release = mlx5_tx_queue_release,
1546         .rx_queue_start = mlx5_rx_queue_start,
1547         .rx_queue_stop = mlx5_rx_queue_stop,
1548         .tx_queue_start = mlx5_tx_queue_start,
1549         .tx_queue_stop = mlx5_tx_queue_stop,
1550         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1551         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1552         .mac_addr_remove = mlx5_mac_addr_remove,
1553         .mac_addr_add = mlx5_mac_addr_add,
1554         .mac_addr_set = mlx5_mac_addr_set,
1555         .set_mc_addr_list = mlx5_set_mc_addr_list,
1556         .mtu_set = mlx5_dev_set_mtu,
1557         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1558         .vlan_offload_set = mlx5_vlan_offload_set,
1559         .filter_ctrl = mlx5_dev_filter_ctrl,
1560         .rxq_info_get = mlx5_rxq_info_get,
1561         .txq_info_get = mlx5_txq_info_get,
1562         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1563         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1564         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1565         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1566         .is_removed = mlx5_is_removed,
1567         .get_module_info = mlx5_get_module_info,
1568         .get_module_eeprom = mlx5_get_module_eeprom,
1569         .hairpin_cap_get = mlx5_hairpin_cap_get,
1570         .mtr_ops_get = mlx5_flow_meter_ops_get,
1571         .hairpin_bind = mlx5_hairpin_bind,
1572         .hairpin_unbind = mlx5_hairpin_unbind,
1573         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1574         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1575         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1576         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1577 };
1578
1579 /**
1580  * Verify and store value for device argument.
1581  *
1582  * @param[in] key
1583  *   Key argument to verify.
1584  * @param[in] val
1585  *   Value associated with key.
1586  * @param opaque
1587  *   User data.
1588  *
1589  * @return
1590  *   0 on success, a negative errno value otherwise and rte_errno is set.
1591  */
1592 static int
1593 mlx5_args_check(const char *key, const char *val, void *opaque)
1594 {
1595         struct mlx5_dev_config *config = opaque;
1596         unsigned long mod;
1597         signed long tmp;
1598
1599         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1600         if (!strcmp(MLX5_REPRESENTOR, key))
1601                 return 0;
1602         errno = 0;
1603         tmp = strtol(val, NULL, 0);
1604         if (errno) {
1605                 rte_errno = errno;
1606                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1607                 return -rte_errno;
1608         }
1609         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1610                 /* Negative values are acceptable for some keys only. */
1611                 rte_errno = EINVAL;
1612                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1613                 return -rte_errno;
1614         }
1615         mod = tmp >= 0 ? tmp : -tmp;
1616         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1617                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1618                         DRV_LOG(ERR, "invalid CQE compression "
1619                                      "format parameter");
1620                         rte_errno = EINVAL;
1621                         return -rte_errno;
1622                 }
1623                 config->cqe_comp = !!tmp;
1624                 config->cqe_comp_fmt = tmp;
1625         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1626                 config->hw_padding = !!tmp;
1627         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1628                 config->mprq.enabled = !!tmp;
1629         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1630                 config->mprq.stride_num_n = tmp;
1631         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1632                 config->mprq.stride_size_n = tmp;
1633         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1634                 config->mprq.max_memcpy_len = tmp;
1635         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1636                 config->mprq.min_rxqs_num = tmp;
1637         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1638                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1639                                  " converted to txq_inline_max", key);
1640                 config->txq_inline_max = tmp;
1641         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1642                 config->txq_inline_max = tmp;
1643         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1644                 config->txq_inline_min = tmp;
1645         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1646                 config->txq_inline_mpw = tmp;
1647         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1648                 config->txqs_inline = tmp;
1649         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1650                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1651         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1652                 config->mps = !!tmp;
1653         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1654                 if (tmp != MLX5_TXDB_CACHED &&
1655                     tmp != MLX5_TXDB_NCACHED &&
1656                     tmp != MLX5_TXDB_HEURISTIC) {
1657                         DRV_LOG(ERR, "invalid Tx doorbell "
1658                                      "mapping parameter");
1659                         rte_errno = EINVAL;
1660                         return -rte_errno;
1661                 }
1662                 config->dbnc = tmp;
1663         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1664                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1665         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1666                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1667                                  " converted to txq_inline_mpw", key);
1668                 config->txq_inline_mpw = tmp;
1669         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1670                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1671         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1672                 if (!mod) {
1673                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1674                         rte_errno = EINVAL;
1675                         return -rte_errno;
1676                 }
1677                 config->tx_pp = tmp;
1678         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1679                 config->tx_skew = tmp;
1680         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1681                 config->rx_vec_en = !!tmp;
1682         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1683                 config->l3_vxlan_en = !!tmp;
1684         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1685                 config->vf_nl_en = !!tmp;
1686         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1687                 config->dv_esw_en = !!tmp;
1688         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1689                 config->dv_flow_en = !!tmp;
1690         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1691                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1692                     tmp != MLX5_XMETA_MODE_META16 &&
1693                     tmp != MLX5_XMETA_MODE_META32 &&
1694                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1695                         DRV_LOG(ERR, "invalid extensive "
1696                                      "metadata parameter");
1697                         rte_errno = EINVAL;
1698                         return -rte_errno;
1699                 }
1700                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1701                         config->dv_xmeta_en = tmp;
1702                 else
1703                         config->dv_miss_info = 1;
1704         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1705                 config->lacp_by_user = !!tmp;
1706         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1707                 config->mr_ext_memseg_en = !!tmp;
1708         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1709                 config->max_dump_files_num = tmp;
1710         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1711                 config->lro.timeout = tmp;
1712         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1713                 DRV_LOG(DEBUG, "class argument is %s.", val);
1714         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1715                 config->log_hp_size = tmp;
1716         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1717                 if (tmp != MLX5_RCM_NONE &&
1718                     tmp != MLX5_RCM_LIGHT &&
1719                     tmp != MLX5_RCM_AGGR) {
1720                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1721                         rte_errno = EINVAL;
1722                         return -rte_errno;
1723                 }
1724                 config->reclaim_mode = tmp;
1725         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1726                 config->sys_mem_en = !!tmp;
1727         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1728                 config->decap_en = !!tmp;
1729         } else {
1730                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1731                 rte_errno = EINVAL;
1732                 return -rte_errno;
1733         }
1734         return 0;
1735 }
1736
1737 /**
1738  * Parse device parameters.
1739  *
1740  * @param config
1741  *   Pointer to device configuration structure.
1742  * @param devargs
1743  *   Device arguments structure.
1744  *
1745  * @return
1746  *   0 on success, a negative errno value otherwise and rte_errno is set.
1747  */
1748 int
1749 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1750 {
1751         const char **params = (const char *[]){
1752                 MLX5_RXQ_CQE_COMP_EN,
1753                 MLX5_RXQ_PKT_PAD_EN,
1754                 MLX5_RX_MPRQ_EN,
1755                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1756                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1757                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1758                 MLX5_RXQS_MIN_MPRQ,
1759                 MLX5_TXQ_INLINE,
1760                 MLX5_TXQ_INLINE_MIN,
1761                 MLX5_TXQ_INLINE_MAX,
1762                 MLX5_TXQ_INLINE_MPW,
1763                 MLX5_TXQS_MIN_INLINE,
1764                 MLX5_TXQS_MAX_VEC,
1765                 MLX5_TXQ_MPW_EN,
1766                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1767                 MLX5_TXQ_MAX_INLINE_LEN,
1768                 MLX5_TX_DB_NC,
1769                 MLX5_TX_PP,
1770                 MLX5_TX_SKEW,
1771                 MLX5_TX_VEC_EN,
1772                 MLX5_RX_VEC_EN,
1773                 MLX5_L3_VXLAN_EN,
1774                 MLX5_VF_NL_EN,
1775                 MLX5_DV_ESW_EN,
1776                 MLX5_DV_FLOW_EN,
1777                 MLX5_DV_XMETA_EN,
1778                 MLX5_LACP_BY_USER,
1779                 MLX5_MR_EXT_MEMSEG_EN,
1780                 MLX5_REPRESENTOR,
1781                 MLX5_MAX_DUMP_FILES_NUM,
1782                 MLX5_LRO_TIMEOUT_USEC,
1783                 MLX5_CLASS_ARG_NAME,
1784                 MLX5_HP_BUF_SIZE,
1785                 MLX5_RECLAIM_MEM,
1786                 MLX5_SYS_MEM_EN,
1787                 MLX5_DECAP_EN,
1788                 NULL,
1789         };
1790         struct rte_kvargs *kvlist;
1791         int ret = 0;
1792         int i;
1793
1794         if (devargs == NULL)
1795                 return 0;
1796         /* Following UGLY cast is done to pass checkpatch. */
1797         kvlist = rte_kvargs_parse(devargs->args, params);
1798         if (kvlist == NULL) {
1799                 rte_errno = EINVAL;
1800                 return -rte_errno;
1801         }
1802         /* Process parameters. */
1803         for (i = 0; (params[i] != NULL); ++i) {
1804                 if (rte_kvargs_count(kvlist, params[i])) {
1805                         ret = rte_kvargs_process(kvlist, params[i],
1806                                                  mlx5_args_check, config);
1807                         if (ret) {
1808                                 rte_errno = EINVAL;
1809                                 rte_kvargs_free(kvlist);
1810                                 return -rte_errno;
1811                         }
1812                 }
1813         }
1814         rte_kvargs_free(kvlist);
1815         return 0;
1816 }
1817
1818 /**
1819  * Configures the minimal amount of data to inline into WQE
1820  * while sending packets.
1821  *
1822  * - the txq_inline_min has the maximal priority, if this
1823  *   key is specified in devargs
1824  * - if DevX is enabled the inline mode is queried from the
1825  *   device (HCA attributes and NIC vport context if needed).
1826  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1827  *   and none (0 bytes) for other NICs
1828  *
1829  * @param spawn
1830  *   Verbs device parameters (name, port, switch_info) to spawn.
1831  * @param config
1832  *   Device configuration parameters.
1833  */
1834 void
1835 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1836                     struct mlx5_dev_config *config)
1837 {
1838         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1839                 /* Application defines size of inlined data explicitly. */
1840                 switch (spawn->pci_dev->id.device_id) {
1841                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1842                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1843                         if (config->txq_inline_min <
1844                                        (int)MLX5_INLINE_HSIZE_L2) {
1845                                 DRV_LOG(DEBUG,
1846                                         "txq_inline_mix aligned to minimal"
1847                                         " ConnectX-4 required value %d",
1848                                         (int)MLX5_INLINE_HSIZE_L2);
1849                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1850                         }
1851                         break;
1852                 }
1853                 goto exit;
1854         }
1855         if (config->hca_attr.eth_net_offloads) {
1856                 /* We have DevX enabled, inline mode queried successfully. */
1857                 switch (config->hca_attr.wqe_inline_mode) {
1858                 case MLX5_CAP_INLINE_MODE_L2:
1859                         /* outer L2 header must be inlined. */
1860                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1861                         goto exit;
1862                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1863                         /* No inline data are required by NIC. */
1864                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1865                         config->hw_vlan_insert =
1866                                 config->hca_attr.wqe_vlan_insert;
1867                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1868                         goto exit;
1869                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1870                         /* inline mode is defined by NIC vport context. */
1871                         if (!config->hca_attr.eth_virt)
1872                                 break;
1873                         switch (config->hca_attr.vport_inline_mode) {
1874                         case MLX5_INLINE_MODE_NONE:
1875                                 config->txq_inline_min =
1876                                         MLX5_INLINE_HSIZE_NONE;
1877                                 goto exit;
1878                         case MLX5_INLINE_MODE_L2:
1879                                 config->txq_inline_min =
1880                                         MLX5_INLINE_HSIZE_L2;
1881                                 goto exit;
1882                         case MLX5_INLINE_MODE_IP:
1883                                 config->txq_inline_min =
1884                                         MLX5_INLINE_HSIZE_L3;
1885                                 goto exit;
1886                         case MLX5_INLINE_MODE_TCP_UDP:
1887                                 config->txq_inline_min =
1888                                         MLX5_INLINE_HSIZE_L4;
1889                                 goto exit;
1890                         case MLX5_INLINE_MODE_INNER_L2:
1891                                 config->txq_inline_min =
1892                                         MLX5_INLINE_HSIZE_INNER_L2;
1893                                 goto exit;
1894                         case MLX5_INLINE_MODE_INNER_IP:
1895                                 config->txq_inline_min =
1896                                         MLX5_INLINE_HSIZE_INNER_L3;
1897                                 goto exit;
1898                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1899                                 config->txq_inline_min =
1900                                         MLX5_INLINE_HSIZE_INNER_L4;
1901                                 goto exit;
1902                         }
1903                 }
1904         }
1905         /*
1906          * We get here if we are unable to deduce
1907          * inline data size with DevX. Try PCI ID
1908          * to determine old NICs.
1909          */
1910         switch (spawn->pci_dev->id.device_id) {
1911         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1912         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1913         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1914         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1915                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1916                 config->hw_vlan_insert = 0;
1917                 break;
1918         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1919         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1920         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1921         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1922                 /*
1923                  * These NICs support VLAN insertion from WQE and
1924                  * report the wqe_vlan_insert flag. But there is the bug
1925                  * and PFC control may be broken, so disable feature.
1926                  */
1927                 config->hw_vlan_insert = 0;
1928                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1929                 break;
1930         default:
1931                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1932                 break;
1933         }
1934 exit:
1935         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1936 }
1937
1938 /**
1939  * Configures the metadata mask fields in the shared context.
1940  *
1941  * @param [in] dev
1942  *   Pointer to Ethernet device.
1943  */
1944 void
1945 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1946 {
1947         struct mlx5_priv *priv = dev->data->dev_private;
1948         struct mlx5_dev_ctx_shared *sh = priv->sh;
1949         uint32_t meta, mark, reg_c0;
1950
1951         reg_c0 = ~priv->vport_meta_mask;
1952         switch (priv->config.dv_xmeta_en) {
1953         case MLX5_XMETA_MODE_LEGACY:
1954                 meta = UINT32_MAX;
1955                 mark = MLX5_FLOW_MARK_MASK;
1956                 break;
1957         case MLX5_XMETA_MODE_META16:
1958                 meta = reg_c0 >> rte_bsf32(reg_c0);
1959                 mark = MLX5_FLOW_MARK_MASK;
1960                 break;
1961         case MLX5_XMETA_MODE_META32:
1962                 meta = UINT32_MAX;
1963                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1964                 break;
1965         default:
1966                 meta = 0;
1967                 mark = 0;
1968                 MLX5_ASSERT(false);
1969                 break;
1970         }
1971         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1972                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1973                                  sh->dv_mark_mask, mark);
1974         else
1975                 sh->dv_mark_mask = mark;
1976         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1977                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1978                                  sh->dv_meta_mask, meta);
1979         else
1980                 sh->dv_meta_mask = meta;
1981         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1982                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1983                                  sh->dv_meta_mask, reg_c0);
1984         else
1985                 sh->dv_regc0_mask = reg_c0;
1986         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1987         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1988         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1989         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1990 }
1991
1992 int
1993 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1994 {
1995         static const char *const dynf_names[] = {
1996                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1997                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1998                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1999         };
2000         unsigned int i;
2001
2002         if (n < RTE_DIM(dynf_names))
2003                 return -ENOMEM;
2004         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2005                 if (names[i] == NULL)
2006                         return -EINVAL;
2007                 strcpy(names[i], dynf_names[i]);
2008         }
2009         return RTE_DIM(dynf_names);
2010 }
2011
2012 /**
2013  * Comparison callback to sort device data.
2014  *
2015  * This is meant to be used with qsort().
2016  *
2017  * @param a[in]
2018  *   Pointer to pointer to first data object.
2019  * @param b[in]
2020  *   Pointer to pointer to second data object.
2021  *
2022  * @return
2023  *   0 if both objects are equal, less than 0 if the first argument is less
2024  *   than the second, greater than 0 otherwise.
2025  */
2026 int
2027 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2028                               struct mlx5_dev_config *config)
2029 {
2030         struct mlx5_dev_ctx_shared *sh = priv->sh;
2031         struct mlx5_dev_config *sh_conf = NULL;
2032         uint16_t port_id;
2033
2034         MLX5_ASSERT(sh);
2035         /* Nothing to compare for the single/first device. */
2036         if (sh->refcnt == 1)
2037                 return 0;
2038         /* Find the device with shared context. */
2039         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2040                 struct mlx5_priv *opriv =
2041                         rte_eth_devices[port_id].data->dev_private;
2042
2043                 if (opriv && opriv != priv && opriv->sh == sh) {
2044                         sh_conf = &opriv->config;
2045                         break;
2046                 }
2047         }
2048         if (!sh_conf)
2049                 return 0;
2050         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2051                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2052                              " for shared %s context", sh->ibdev_name);
2053                 rte_errno = EINVAL;
2054                 return rte_errno;
2055         }
2056         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2057                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2058                              " for shared %s context", sh->ibdev_name);
2059                 rte_errno = EINVAL;
2060                 return rte_errno;
2061         }
2062         return 0;
2063 }
2064
2065 /**
2066  * Look for the ethernet device belonging to mlx5 driver.
2067  *
2068  * @param[in] port_id
2069  *   port_id to start looking for device.
2070  * @param[in] pci_dev
2071  *   Pointer to the hint PCI device. When device is being probed
2072  *   the its siblings (master and preceding representors might
2073  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2074  *   is not completed yet, for this case match on hint PCI
2075  *   device may be used to detect sibling device.
2076  *
2077  * @return
2078  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2079  */
2080 uint16_t
2081 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2082 {
2083         while (port_id < RTE_MAX_ETHPORTS) {
2084                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2085
2086                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2087                     dev->device &&
2088                     (dev->device == &pci_dev->device ||
2089                      (dev->device->driver &&
2090                      dev->device->driver->name &&
2091                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2092                         break;
2093                 port_id++;
2094         }
2095         if (port_id >= RTE_MAX_ETHPORTS)
2096                 return RTE_MAX_ETHPORTS;
2097         return port_id;
2098 }
2099
2100 /**
2101  * DPDK callback to remove a PCI device.
2102  *
2103  * This function removes all Ethernet devices belong to a given PCI device.
2104  *
2105  * @param[in] pci_dev
2106  *   Pointer to the PCI device.
2107  *
2108  * @return
2109  *   0 on success, the function cannot fail.
2110  */
2111 static int
2112 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2113 {
2114         uint16_t port_id;
2115         int ret = 0;
2116
2117         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2118                 /*
2119                  * mlx5_dev_close() is not registered to secondary process,
2120                  * call the close function explicitly for secondary process.
2121                  */
2122                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2123                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2124                 else
2125                         ret |= rte_eth_dev_close(port_id);
2126         }
2127         return ret == 0 ? 0 : -EIO;
2128 }
2129
2130 static const struct rte_pci_id mlx5_pci_id_map[] = {
2131         {
2132                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2133                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2134         },
2135         {
2136                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2137                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2138         },
2139         {
2140                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2141                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2142         },
2143         {
2144                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2145                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2146         },
2147         {
2148                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2149                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2150         },
2151         {
2152                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2153                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2154         },
2155         {
2156                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2157                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2158         },
2159         {
2160                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2161                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2162         },
2163         {
2164                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2165                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2166         },
2167         {
2168                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2169                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2170         },
2171         {
2172                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2173                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2174         },
2175         {
2176                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2177                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2178         },
2179         {
2180                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2181                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2182         },
2183         {
2184                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2185                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2186         },
2187         {
2188                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2189                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2190         },
2191         {
2192                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2193                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2194         },
2195         {
2196                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2197                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2198         },
2199         {
2200                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2201                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2202         },
2203         {
2204                 .vendor_id = 0
2205         }
2206 };
2207
2208 static struct mlx5_pci_driver mlx5_driver = {
2209         .driver_class = MLX5_CLASS_NET,
2210         .pci_driver = {
2211                 .driver = {
2212                         .name = MLX5_DRIVER_NAME,
2213                 },
2214                 .id_table = mlx5_pci_id_map,
2215                 .probe = mlx5_os_pci_probe,
2216                 .remove = mlx5_pci_remove,
2217                 .dma_map = mlx5_dma_map,
2218                 .dma_unmap = mlx5_dma_unmap,
2219                 .drv_flags = PCI_DRV_FLAGS,
2220         },
2221 };
2222
2223 /* Initialize driver log type. */
2224 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2225
2226 /**
2227  * Driver initialization routine.
2228  */
2229 RTE_INIT(rte_mlx5_pmd_init)
2230 {
2231         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2232         mlx5_common_init();
2233         /* Build the static tables for Verbs conversion. */
2234         mlx5_set_ptype_table();
2235         mlx5_set_cksum_table();
2236         mlx5_set_swp_types_table();
2237         if (mlx5_glue)
2238                 mlx5_pci_driver_register(&mlx5_driver);
2239 }
2240
2241 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2242 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2243 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");