1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <rte_malloc.h>
14 #include <rte_ethdev_driver.h>
15 #include <rte_ethdev_pci.h>
17 #include <rte_bus_pci.h>
18 #include <rte_common.h>
19 #include <rte_kvargs.h>
20 #include <rte_rwlock.h>
21 #include <rte_spinlock.h>
22 #include <rte_string_fns.h>
23 #include <rte_alarm.h>
24 #include <rte_cycles.h>
26 #include <mlx5_glue.h>
27 #include <mlx5_devx_cmds.h>
28 #include <mlx5_common.h>
29 #include <mlx5_common_os.h>
30 #include <mlx5_common_mp.h>
31 #include <mlx5_common_pci.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 #include "mlx5_flow.h"
41 #include "mlx5_flow_os.h"
42 #include "rte_pmd_mlx5.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to enable RX completion entry padding to 128B. */
48 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
50 /* Device parameter to enable padding Rx packet to cacheline size. */
51 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
53 /* Device parameter to enable Multi-Packet Rx queue. */
54 #define MLX5_RX_MPRQ_EN "mprq_en"
56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
59 /* Device parameter to configure log 2 of the stride size for MPRQ. */
60 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
62 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
63 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
65 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
66 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
68 /* Device parameter to configure inline send. Deprecated, ignored.*/
69 #define MLX5_TXQ_INLINE "txq_inline"
71 /* Device parameter to limit packet size to inline with ordinary SEND. */
72 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
74 /* Device parameter to configure minimal data size to inline. */
75 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
77 /* Device parameter to limit packet size to inline with Enhanced MPW. */
78 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
81 * Device parameter to configure the number of TX queues threshold for
82 * enabling inline send.
84 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
87 * Device parameter to configure the number of TX queues threshold for
88 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
90 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
92 /* Device parameter to enable multi-packet send WQEs. */
93 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
96 * Device parameter to force doorbell register mapping
97 * to non-cahed region eliminating the extra write memory barrier.
99 #define MLX5_TX_DB_NC "tx_db_nc"
102 * Device parameter to include 2 dsegs in the title WQEBB.
103 * Deprecated, ignored.
105 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
108 * Device parameter to limit the size of inlining packet.
109 * Deprecated, ignored.
111 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
114 * Device parameter to enable Tx scheduling on timestamps
115 * and specify the packet pacing granularity in nanoseconds.
117 #define MLX5_TX_PP "tx_pp"
120 * Device parameter to specify skew in nanoseconds on Tx datapath,
121 * it represents the time between SQ start WQE processing and
122 * appearing actual packet data on the wire.
124 #define MLX5_TX_SKEW "tx_skew"
127 * Device parameter to enable hardware Tx vector.
128 * Deprecated, ignored (no vectorized Tx routines anymore).
130 #define MLX5_TX_VEC_EN "tx_vec_en"
132 /* Device parameter to enable hardware Rx vector. */
133 #define MLX5_RX_VEC_EN "rx_vec_en"
135 /* Allow L3 VXLAN flow creation. */
136 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
138 /* Activate DV E-Switch flow steering. */
139 #define MLX5_DV_ESW_EN "dv_esw_en"
141 /* Activate DV flow steering. */
142 #define MLX5_DV_FLOW_EN "dv_flow_en"
144 /* Enable extensive flow metadata support. */
145 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
147 /* Device parameter to let the user manage the lacp traffic of bonded device */
148 #define MLX5_LACP_BY_USER "lacp_by_user"
150 /* Activate Netlink support in VF mode. */
151 #define MLX5_VF_NL_EN "vf_nl_en"
153 /* Enable extending memsegs when creating a MR. */
154 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
156 /* Select port representors to instantiate. */
157 #define MLX5_REPRESENTOR "representor"
159 /* Device parameter to configure the maximum number of dump files per queue. */
160 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
162 /* Configure timeout of LRO session (in microseconds). */
163 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
166 * Device parameter to configure the total data buffer size for a single
167 * hairpin queue (logarithm value).
169 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
171 /* Flow memory reclaim mode. */
172 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
174 /* The default memory allocator used in PMD. */
175 #define MLX5_SYS_MEM_EN "sys_mem_en"
176 /* Decap will be used or not. */
177 #define MLX5_DECAP_EN "decap_en"
179 /* Shared memory between primary and secondary processes. */
180 struct mlx5_shared_data *mlx5_shared_data;
182 /** Driver-specific log messages type. */
185 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
186 LIST_HEAD_INITIALIZER();
187 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
188 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
189 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
190 [MLX5_IPOOL_DECAP_ENCAP] = {
191 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
197 .malloc = mlx5_malloc,
199 .type = "mlx5_encap_decap_ipool",
201 [MLX5_IPOOL_PUSH_VLAN] = {
202 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
208 .malloc = mlx5_malloc,
210 .type = "mlx5_push_vlan_ipool",
213 .size = sizeof(struct mlx5_flow_dv_tag_resource),
219 .malloc = mlx5_malloc,
221 .type = "mlx5_tag_ipool",
223 [MLX5_IPOOL_PORT_ID] = {
224 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
230 .malloc = mlx5_malloc,
232 .type = "mlx5_port_id_ipool",
234 [MLX5_IPOOL_JUMP] = {
235 .size = sizeof(struct mlx5_flow_tbl_data_entry),
241 .malloc = mlx5_malloc,
243 .type = "mlx5_jump_ipool",
245 [MLX5_IPOOL_SAMPLE] = {
246 .size = sizeof(struct mlx5_flow_dv_sample_resource),
252 .malloc = mlx5_malloc,
254 .type = "mlx5_sample_ipool",
256 [MLX5_IPOOL_DEST_ARRAY] = {
257 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
263 .malloc = mlx5_malloc,
265 .type = "mlx5_dest_array_ipool",
267 [MLX5_IPOOL_TUNNEL_ID] = {
268 .size = sizeof(struct mlx5_flow_tunnel),
269 .trunk_size = MLX5_MAX_TUNNELS,
272 .type = "mlx5_tunnel_offload",
274 [MLX5_IPOOL_TNL_TBL_ID] = {
277 .type = "mlx5_flow_tnl_tbl_ipool",
281 .size = sizeof(struct mlx5_flow_meter),
287 .malloc = mlx5_malloc,
289 .type = "mlx5_meter_ipool",
292 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
298 .malloc = mlx5_malloc,
300 .type = "mlx5_mcp_ipool",
302 [MLX5_IPOOL_HRXQ] = {
303 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
309 .malloc = mlx5_malloc,
311 .type = "mlx5_hrxq_ipool",
313 [MLX5_IPOOL_MLX5_FLOW] = {
315 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
316 * It set in run time according to PCI function configuration.
324 .malloc = mlx5_malloc,
326 .type = "mlx5_flow_handle_ipool",
328 [MLX5_IPOOL_RTE_FLOW] = {
329 .size = sizeof(struct rte_flow),
333 .malloc = mlx5_malloc,
335 .type = "rte_flow_ipool",
337 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
340 .type = "mlx5_flow_rss_id_ipool",
342 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
343 .size = sizeof(struct mlx5_shared_action_rss),
349 .malloc = mlx5_malloc,
351 .type = "mlx5_shared_action_rss",
356 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
357 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
359 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
362 * Initialize the ASO aging management structure.
365 * Pointer to mlx5_dev_ctx_shared object to free
368 * 0 on success, a negative errno value otherwise and rte_errno is set.
371 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
377 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
378 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
379 if (!sh->aso_age_mng) {
380 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
384 err = mlx5_aso_queue_init(sh);
386 mlx5_free(sh->aso_age_mng);
389 rte_spinlock_init(&sh->aso_age_mng->resize_sl);
390 rte_spinlock_init(&sh->aso_age_mng->free_sl);
391 LIST_INIT(&sh->aso_age_mng->free);
396 * Close and release all the resources of the ASO aging management structure.
399 * Pointer to mlx5_dev_ctx_shared object to free.
402 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
406 mlx5_aso_queue_stop(sh);
407 mlx5_aso_queue_uninit(sh);
408 if (sh->aso_age_mng->pools) {
409 struct mlx5_aso_age_pool *pool;
411 for (i = 0; i < sh->aso_age_mng->next; ++i) {
412 pool = sh->aso_age_mng->pools[i];
413 claim_zero(mlx5_devx_cmd_destroy
414 (pool->flow_hit_aso_obj));
415 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
416 if (pool->actions[j].dr_action)
418 (mlx5_flow_os_destroy_flow_action
419 (pool->actions[j].dr_action));
422 mlx5_free(sh->aso_age_mng->pools);
424 mlx5_free(sh->aso_age_mng);
428 * Initialize the shared aging list information per port.
431 * Pointer to mlx5_dev_ctx_shared object.
434 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
437 struct mlx5_age_info *age_info;
439 for (i = 0; i < sh->max_port; i++) {
440 age_info = &sh->port[i].age_info;
442 TAILQ_INIT(&age_info->aged_counters);
443 LIST_INIT(&age_info->aged_aso);
444 rte_spinlock_init(&age_info->aged_sl);
445 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
450 * Initialize the counters management structure.
453 * Pointer to mlx5_dev_ctx_shared object to free
456 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
460 memset(&sh->cmng, 0, sizeof(sh->cmng));
461 TAILQ_INIT(&sh->cmng.flow_counters);
462 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
463 sh->cmng.max_id = -1;
464 sh->cmng.last_pool_idx = POOL_IDX_INVALID;
465 rte_spinlock_init(&sh->cmng.pool_update_sl);
466 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
467 TAILQ_INIT(&sh->cmng.counters[i]);
468 rte_spinlock_init(&sh->cmng.csl[i]);
473 * Destroy all the resources allocated for a counter memory management.
476 * Pointer to the memory management structure.
479 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
481 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
483 LIST_REMOVE(mng, next);
484 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
485 claim_zero(mlx5_os_umem_dereg(mng->umem));
490 * Close and release all the resources of the counters management.
493 * Pointer to mlx5_dev_ctx_shared object to free.
496 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
498 struct mlx5_counter_stats_mem_mng *mng;
504 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
505 if (rte_errno != EINPROGRESS)
510 if (sh->cmng.pools) {
511 struct mlx5_flow_counter_pool *pool;
512 uint16_t n_valid = sh->cmng.n_valid;
513 bool fallback = sh->cmng.counter_fallback;
515 for (i = 0; i < n_valid; ++i) {
516 pool = sh->cmng.pools[i];
517 if (!fallback && pool->min_dcs)
518 claim_zero(mlx5_devx_cmd_destroy
520 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
521 struct mlx5_flow_counter *cnt =
522 MLX5_POOL_GET_CNT(pool, j);
526 (mlx5_flow_os_destroy_flow_action
528 if (fallback && MLX5_POOL_GET_CNT
529 (pool, j)->dcs_when_free)
530 claim_zero(mlx5_devx_cmd_destroy
531 (cnt->dcs_when_free));
535 mlx5_free(sh->cmng.pools);
537 mng = LIST_FIRST(&sh->cmng.mem_mngs);
539 mlx5_flow_destroy_counter_stat_mem_mng(mng);
540 mng = LIST_FIRST(&sh->cmng.mem_mngs);
542 memset(&sh->cmng, 0, sizeof(sh->cmng));
545 /* Send FLOW_AGED event if needed. */
547 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
549 struct mlx5_age_info *age_info;
552 for (i = 0; i < sh->max_port; i++) {
553 age_info = &sh->port[i].age_info;
554 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
556 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
557 rte_eth_dev_callback_process
558 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
559 RTE_ETH_EVENT_FLOW_AGED, NULL);
565 * Initialize the flow resources' indexed mempool.
568 * Pointer to mlx5_dev_ctx_shared object.
570 * Pointer to user dev config.
573 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
574 const struct mlx5_dev_config *config)
577 struct mlx5_indexed_pool_config cfg;
579 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
580 cfg = mlx5_ipool_cfg[i];
585 * Set MLX5_IPOOL_MLX5_FLOW ipool size
586 * according to PCI function flow configuration.
588 case MLX5_IPOOL_MLX5_FLOW:
589 cfg.size = config->dv_flow_en ?
590 sizeof(struct mlx5_flow_handle) :
591 MLX5_FLOW_HANDLE_VERBS_SIZE;
594 if (config->reclaim_mode)
595 cfg.release_mem_en = 1;
596 sh->ipool[i] = mlx5_ipool_create(&cfg);
601 * Release the flow resources' indexed mempool.
604 * Pointer to mlx5_dev_ctx_shared object.
607 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
611 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
612 mlx5_ipool_destroy(sh->ipool[i]);
616 * Check if dynamic flex parser for eCPRI already exists.
619 * Pointer to Ethernet device structure.
622 * true on exists, false on not.
625 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
627 struct mlx5_priv *priv = dev->data->dev_private;
628 struct mlx5_flex_parser_profiles *prf =
629 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
635 * Allocation of a flex parser for eCPRI. Once created, this parser related
636 * resources will be held until the device is closed.
639 * Pointer to Ethernet device structure.
642 * 0 on success, a negative errno value otherwise and rte_errno is set.
645 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
647 struct mlx5_priv *priv = dev->data->dev_private;
648 struct mlx5_flex_parser_profiles *prf =
649 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
650 struct mlx5_devx_graph_node_attr node = {
651 .modify_field_select = 0,
656 if (!priv->config.hca_attr.parse_graph_flex_node) {
657 DRV_LOG(ERR, "Dynamic flex parser is not supported "
658 "for device %s.", priv->dev_data->name);
661 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
662 /* 8 bytes now: 4B common header + 4B message body header. */
663 node.header_length_base_value = 0x8;
664 /* After MAC layer: Ether / VLAN. */
665 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
666 /* Type of compared condition should be 0xAEFE in the L2 layer. */
667 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
668 /* Sample #0: type in common header. */
669 node.sample[0].flow_match_sample_en = 1;
671 node.sample[0].flow_match_sample_offset_mode = 0x0;
672 /* Only the 2nd byte will be used. */
673 node.sample[0].flow_match_sample_field_base_offset = 0x0;
674 /* Sample #1: message payload. */
675 node.sample[1].flow_match_sample_en = 1;
677 node.sample[1].flow_match_sample_offset_mode = 0x0;
679 * Only the first two bytes will be used right now, and its offset will
680 * start after the common header that with the length of a DW(u32).
682 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
683 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
685 DRV_LOG(ERR, "Failed to create flex parser node object.");
686 return (rte_errno == 0) ? -ENODEV : -rte_errno;
689 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
691 DRV_LOG(ERR, "Failed to query sample IDs.");
692 return (rte_errno == 0) ? -ENODEV : -rte_errno;
694 prf->offset[0] = 0x0;
695 prf->offset[1] = sizeof(uint32_t);
696 prf->ids[0] = ids[0];
697 prf->ids[1] = ids[1];
702 * Destroy the flex parser node, including the parser itself, input / output
703 * arcs and DW samples. Resources could be reused then.
706 * Pointer to Ethernet device structure.
709 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
711 struct mlx5_priv *priv = dev->data->dev_private;
712 struct mlx5_flex_parser_profiles *prf =
713 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
716 mlx5_devx_cmd_destroy(prf->obj);
721 * Allocate Rx and Tx UARs in robust fashion.
722 * This routine handles the following UAR allocation issues:
724 * - tries to allocate the UAR with the most appropriate memory
725 * mapping type from the ones supported by the host
727 * - tries to allocate the UAR with non-NULL base address
728 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
729 * UAR base address if UAR was not the first object in the UAR page.
730 * It caused the PMD failure and we should try to get another UAR
731 * till we get the first one with non-NULL base address returned.
734 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
735 const struct mlx5_dev_config *config)
737 uint32_t uar_mapping, retry;
741 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
742 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
743 /* Control the mapping type according to the settings. */
744 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
745 MLX5DV_UAR_ALLOC_TYPE_NC :
746 MLX5DV_UAR_ALLOC_TYPE_BF;
748 RTE_SET_USED(config);
750 * It seems we have no way to control the memory mapping type
751 * for the UAR, the default "Write-Combining" type is supposed.
752 * The UAR initialization on queue creation queries the
753 * actual mapping type done by Verbs/kernel and setups the
754 * PMD datapath accordingly.
758 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
759 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
761 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
762 if (config->dbnc == MLX5_TXDB_CACHED ||
763 config->dbnc == MLX5_TXDB_HEURISTIC)
764 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
765 "is not supported by DevX");
767 * In some environments like virtual machine
768 * the Write Combining mapped might be not supported
769 * and UAR allocation fails. We try "Non-Cached"
770 * mapping for the case. The tx_burst routines take
771 * the UAR mapping type into account on UAR setup
774 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
775 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
776 sh->tx_uar = mlx5_glue->devx_alloc_uar
777 (sh->ctx, uar_mapping);
778 } else if (!sh->tx_uar &&
779 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
780 if (config->dbnc == MLX5_TXDB_NCACHED)
781 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
782 "is not supported by DevX");
784 * If Verbs/kernel does not support "Non-Cached"
785 * try the "Write-Combining".
787 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
788 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
789 sh->tx_uar = mlx5_glue->devx_alloc_uar
790 (sh->ctx, uar_mapping);
794 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
798 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
802 * The UARs are allocated by rdma_core within the
803 * IB device context, on context closure all UARs
804 * will be freed, should be no memory/object leakage.
806 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
809 /* Check whether we finally succeeded with valid UAR allocation. */
811 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
815 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
817 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
818 (sh->ctx, uar_mapping);
819 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
820 if (!sh->devx_rx_uar &&
821 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
823 * Rx UAR is used to control interrupts only,
824 * should be no datapath noticeable impact,
825 * can try "Non-Cached" mapping safely.
827 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
828 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
829 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
830 (sh->ctx, uar_mapping);
833 if (!sh->devx_rx_uar) {
834 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
838 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
842 * The UARs are allocated by rdma_core within the
843 * IB device context, on context closure all UARs
844 * will be freed, should be no memory/object leakage.
846 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
847 sh->devx_rx_uar = NULL;
849 /* Check whether we finally succeeded with valid UAR allocation. */
850 if (!sh->devx_rx_uar) {
851 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
859 * Allocate shared device context. If there is multiport device the
860 * master and representors will share this context, if there is single
861 * port dedicated device, the context will be used by only given
862 * port due to unification.
864 * Routine first searches the context for the specified device name,
865 * if found the shared context assumed and reference counter is incremented.
866 * If no context found the new one is created and initialized with specified
867 * device context and parameters.
870 * Pointer to the device attributes (name, port, etc).
872 * Pointer to device configuration structure.
875 * Pointer to mlx5_dev_ctx_shared object on success,
876 * otherwise NULL and rte_errno is set.
878 struct mlx5_dev_ctx_shared *
879 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
880 const struct mlx5_dev_config *config)
882 struct mlx5_dev_ctx_shared *sh;
885 struct mlx5_devx_tis_attr tis_attr = { 0 };
888 /* Secondary process should not create the shared context. */
889 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
890 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
891 /* Search for IB context by device name. */
892 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
893 if (!strcmp(sh->ibdev_name,
894 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
899 /* No device found, we have to create new shared context. */
900 MLX5_ASSERT(spawn->max_port);
901 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
902 sizeof(struct mlx5_dev_ctx_shared) +
904 sizeof(struct mlx5_dev_shared_port),
905 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
907 DRV_LOG(ERR, "shared context allocation failure");
911 err = mlx5_os_open_device(spawn, config, sh);
914 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
916 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
920 sh->bond_dev = UINT16_MAX;
921 sh->max_port = spawn->max_port;
922 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
923 sizeof(sh->ibdev_name) - 1);
924 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
925 sizeof(sh->ibdev_path) - 1);
927 * Setting port_id to max unallowed value means
928 * there is no interrupt subhandler installed for
929 * the given port index i.
931 for (i = 0; i < sh->max_port; i++) {
932 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
933 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
935 sh->pd = mlx5_os_alloc_pd(sh->ctx);
936 if (sh->pd == NULL) {
937 DRV_LOG(ERR, "PD allocation failure");
942 /* Query the EQN for this core. */
943 err = mlx5_glue->devx_query_eqn(sh->ctx, 0, &sh->eqn);
946 DRV_LOG(ERR, "Failed to query event queue number %d.",
950 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
952 DRV_LOG(ERR, "Fail to extract pdn from PD");
955 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
957 DRV_LOG(ERR, "TD allocation failure");
961 tis_attr.transport_domain = sh->td->id;
962 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
964 DRV_LOG(ERR, "TIS allocation failure");
968 err = mlx5_alloc_rxtx_uars(sh, config);
971 MLX5_ASSERT(sh->tx_uar);
972 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
974 MLX5_ASSERT(sh->devx_rx_uar);
975 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
978 /* Initialize UAR access locks for 32bit implementations. */
979 rte_spinlock_init(&sh->uar_lock_cq);
980 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
981 rte_spinlock_init(&sh->uar_lock[i]);
984 * Once the device is added to the list of memory event
985 * callback, its global MR cache table cannot be expanded
986 * on the fly because of deadlock. If it overflows, lookup
987 * should be done by searching MR list linearly, which is slow.
989 * At this point the device is not added to the memory
990 * event list yet, context is just being created.
992 err = mlx5_mr_btree_init(&sh->share_cache.cache,
993 MLX5_MR_BTREE_CACHE_N * 2,
994 spawn->pci_dev->device.numa_node);
999 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1000 &sh->share_cache.dereg_mr_cb);
1001 mlx5_os_dev_shared_handler_install(sh);
1002 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1003 if (!sh->cnt_id_tbl) {
1007 if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1008 err = mlx5_flow_os_init_workspace_once();
1012 mlx5_flow_aging_init(sh);
1013 mlx5_flow_counters_mng_init(sh);
1014 mlx5_flow_ipool_create(sh, config);
1015 /* Add device to memory callback list. */
1016 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1017 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1019 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1020 /* Add context to the global device list. */
1021 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1023 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1026 pthread_mutex_destroy(&sh->txpp.mutex);
1027 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1030 mlx5_l3t_destroy(sh->cnt_id_tbl);
1032 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1034 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1035 if (sh->devx_rx_uar)
1036 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1038 mlx5_glue->devx_free_uar(sh->tx_uar);
1040 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1042 claim_zero(mlx5_glue->close_device(sh->ctx));
1044 MLX5_ASSERT(err > 0);
1050 * Free shared IB device context. Decrement counter and if zero free
1051 * all allocated resources and close handles.
1054 * Pointer to mlx5_dev_ctx_shared object to free
1057 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1059 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1060 #ifdef RTE_LIBRTE_MLX5_DEBUG
1061 /* Check the object presence in the list. */
1062 struct mlx5_dev_ctx_shared *lctx;
1064 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1069 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1074 MLX5_ASSERT(sh->refcnt);
1075 /* Secondary process should not free the shared context. */
1076 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1079 /* Remove from memory callback device list. */
1080 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1081 LIST_REMOVE(sh, mem_event_cb);
1082 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1083 /* Release created Memory Regions. */
1084 mlx5_mr_release_cache(&sh->share_cache);
1085 /* Remove context from the global device list. */
1086 LIST_REMOVE(sh, next);
1087 /* Release flow workspaces objects on the last device. */
1088 if (LIST_EMPTY(&mlx5_dev_ctx_list))
1089 mlx5_flow_os_release_workspace();
1090 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1092 * Ensure there is no async event handler installed.
1093 * Only primary process handles async device events.
1095 mlx5_flow_counters_mng_close(sh);
1096 if (sh->aso_age_mng) {
1097 mlx5_flow_aso_age_mng_close(sh);
1098 sh->aso_age_mng = NULL;
1100 mlx5_flow_ipool_destroy(sh);
1101 mlx5_os_dev_shared_handler_uninstall(sh);
1102 if (sh->cnt_id_tbl) {
1103 mlx5_l3t_destroy(sh->cnt_id_tbl);
1104 sh->cnt_id_tbl = NULL;
1107 mlx5_glue->devx_free_uar(sh->tx_uar);
1111 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1113 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1115 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1116 if (sh->devx_rx_uar)
1117 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1119 claim_zero(mlx5_glue->close_device(sh->ctx));
1120 pthread_mutex_destroy(&sh->txpp.mutex);
1124 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1128 * Destroy table hash list.
1131 * Pointer to the private device data structure.
1134 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1136 struct mlx5_dev_ctx_shared *sh = priv->sh;
1140 mlx5_hlist_destroy(sh->flow_tbls);
1144 * Initialize flow table hash list and create the root tables entry
1148 * Pointer to the private device data structure.
1151 * Zero on success, positive error code otherwise.
1154 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1157 /* Tables are only used in DV and DR modes. */
1158 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1159 struct mlx5_dev_ctx_shared *sh = priv->sh;
1160 char s[MLX5_HLIST_NAMESIZE];
1163 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1164 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1165 0, 0, flow_dv_tbl_create_cb,
1166 flow_dv_tbl_match_cb,
1167 flow_dv_tbl_remove_cb);
1168 if (!sh->flow_tbls) {
1169 DRV_LOG(ERR, "flow tables with hash creation failed.");
1173 sh->flow_tbls->ctx = sh;
1174 #ifndef HAVE_MLX5DV_DR
1175 struct rte_flow_error error;
1176 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1179 * In case we have not DR support, the zero tables should be created
1180 * because DV expect to see them even if they cannot be created by
1183 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, NULL, 0, 1, &error) ||
1184 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, NULL, 0, 1, &error) ||
1185 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, NULL, 0, 1, &error)) {
1191 mlx5_free_table_hash_list(priv);
1192 #endif /* HAVE_MLX5DV_DR */
1198 * Retrieve integer value from environment variable.
1201 * Environment variable name.
1204 * Integer value, 0 if the variable is not set.
1207 mlx5_getenv_int(const char *name)
1209 const char *val = getenv(name);
1217 * DPDK callback to add udp tunnel port
1220 * A pointer to eth_dev
1221 * @param[in] udp_tunnel
1222 * A pointer to udp tunnel
1225 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1228 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1229 struct rte_eth_udp_tunnel *udp_tunnel)
1231 MLX5_ASSERT(udp_tunnel != NULL);
1232 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1233 udp_tunnel->udp_port == 4789)
1235 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1236 udp_tunnel->udp_port == 4790)
1242 * Initialize process private data structure.
1245 * Pointer to Ethernet device structure.
1248 * 0 on success, a negative errno value otherwise and rte_errno is set.
1251 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1253 struct mlx5_priv *priv = dev->data->dev_private;
1254 struct mlx5_proc_priv *ppriv;
1258 * UAR register table follows the process private structure. BlueFlame
1259 * registers for Tx queues are stored in the table.
1262 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1263 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1264 dev->device->numa_node);
1269 ppriv->uar_table_sz = ppriv_size;
1270 dev->process_private = ppriv;
1275 * Un-initialize process private data structure.
1278 * Pointer to Ethernet device structure.
1281 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1283 if (!dev->process_private)
1285 mlx5_free(dev->process_private);
1286 dev->process_private = NULL;
1290 * DPDK callback to close the device.
1292 * Destroy all queues and objects, free memory.
1295 * Pointer to Ethernet device structure.
1298 mlx5_dev_close(struct rte_eth_dev *dev)
1300 struct mlx5_priv *priv = dev->data->dev_private;
1304 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1305 /* Check if process_private released. */
1306 if (!dev->process_private)
1308 mlx5_tx_uar_uninit_secondary(dev);
1309 mlx5_proc_priv_uninit(dev);
1310 rte_eth_dev_release_port(dev);
1315 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1317 ((priv->sh->ctx != NULL) ?
1318 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1320 * If default mreg copy action is removed at the stop stage,
1321 * the search will return none and nothing will be done anymore.
1323 mlx5_flow_stop_default(dev);
1324 mlx5_traffic_disable(dev);
1326 * If all the flows are already flushed in the device stop stage,
1327 * then this will return directly without any action.
1329 mlx5_flow_list_flush(dev, &priv->flows, true);
1330 mlx5_shared_action_flush(dev);
1331 mlx5_flow_meter_flush(dev, NULL);
1332 /* Prevent crashes when queues are still in use. */
1333 dev->rx_pkt_burst = removed_rx_burst;
1334 dev->tx_pkt_burst = removed_tx_burst;
1336 /* Disable datapath on secondary process. */
1337 mlx5_mp_os_req_stop_rxtx(dev);
1338 /* Free the eCPRI flex parser resource. */
1339 mlx5_flex_parser_ecpri_release(dev);
1340 if (priv->rxqs != NULL) {
1341 /* XXX race condition if mlx5_rx_burst() is still running. */
1342 rte_delay_us_sleep(1000);
1343 for (i = 0; (i != priv->rxqs_n); ++i)
1344 mlx5_rxq_release(dev, i);
1348 if (priv->txqs != NULL) {
1349 /* XXX race condition if mlx5_tx_burst() is still running. */
1350 rte_delay_us_sleep(1000);
1351 for (i = 0; (i != priv->txqs_n); ++i)
1352 mlx5_txq_release(dev, i);
1356 mlx5_proc_priv_uninit(dev);
1357 if (priv->drop_queue.hrxq)
1358 mlx5_drop_action_destroy(dev);
1359 if (priv->mreg_cp_tbl)
1360 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1361 mlx5_mprq_free_mp(dev);
1362 mlx5_os_free_shared_dr(priv);
1363 if (priv->rss_conf.rss_key != NULL)
1364 mlx5_free(priv->rss_conf.rss_key);
1365 if (priv->reta_idx != NULL)
1366 mlx5_free(priv->reta_idx);
1367 if (priv->config.vf)
1368 mlx5_os_mac_addr_flush(dev);
1369 if (priv->nl_socket_route >= 0)
1370 close(priv->nl_socket_route);
1371 if (priv->nl_socket_rdma >= 0)
1372 close(priv->nl_socket_rdma);
1373 if (priv->vmwa_context)
1374 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1375 ret = mlx5_hrxq_verify(dev);
1377 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1378 dev->data->port_id);
1379 ret = mlx5_ind_table_obj_verify(dev);
1381 DRV_LOG(WARNING, "port %u some indirection table still remain",
1382 dev->data->port_id);
1383 ret = mlx5_rxq_obj_verify(dev);
1385 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1386 dev->data->port_id);
1387 ret = mlx5_rxq_verify(dev);
1389 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1390 dev->data->port_id);
1391 ret = mlx5_txq_obj_verify(dev);
1393 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1394 dev->data->port_id);
1395 ret = mlx5_txq_verify(dev);
1397 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1398 dev->data->port_id);
1399 ret = mlx5_flow_verify(dev);
1401 DRV_LOG(WARNING, "port %u some flows still remain",
1402 dev->data->port_id);
1403 mlx5_cache_list_destroy(&priv->hrxqs);
1405 * Free the shared context in last turn, because the cleanup
1406 * routines above may use some shared fields, like
1407 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1408 * ifindex if Netlink fails.
1410 mlx5_free_shared_dev_ctx(priv->sh);
1411 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1415 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1416 struct mlx5_priv *opriv =
1417 rte_eth_devices[port_id].data->dev_private;
1420 opriv->domain_id != priv->domain_id ||
1421 &rte_eth_devices[port_id] == dev)
1427 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1429 memset(priv, 0, sizeof(*priv));
1430 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1432 * Reset mac_addrs to NULL such that it is not freed as part of
1433 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1434 * it is freed when dev_private is freed.
1436 dev->data->mac_addrs = NULL;
1440 const struct eth_dev_ops mlx5_dev_ops = {
1441 .dev_configure = mlx5_dev_configure,
1442 .dev_start = mlx5_dev_start,
1443 .dev_stop = mlx5_dev_stop,
1444 .dev_set_link_down = mlx5_set_link_down,
1445 .dev_set_link_up = mlx5_set_link_up,
1446 .dev_close = mlx5_dev_close,
1447 .promiscuous_enable = mlx5_promiscuous_enable,
1448 .promiscuous_disable = mlx5_promiscuous_disable,
1449 .allmulticast_enable = mlx5_allmulticast_enable,
1450 .allmulticast_disable = mlx5_allmulticast_disable,
1451 .link_update = mlx5_link_update,
1452 .stats_get = mlx5_stats_get,
1453 .stats_reset = mlx5_stats_reset,
1454 .xstats_get = mlx5_xstats_get,
1455 .xstats_reset = mlx5_xstats_reset,
1456 .xstats_get_names = mlx5_xstats_get_names,
1457 .fw_version_get = mlx5_fw_version_get,
1458 .dev_infos_get = mlx5_dev_infos_get,
1459 .read_clock = mlx5_txpp_read_clock,
1460 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1461 .vlan_filter_set = mlx5_vlan_filter_set,
1462 .rx_queue_setup = mlx5_rx_queue_setup,
1463 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1464 .tx_queue_setup = mlx5_tx_queue_setup,
1465 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1466 .rx_queue_release = mlx5_rx_queue_release,
1467 .tx_queue_release = mlx5_tx_queue_release,
1468 .rx_queue_start = mlx5_rx_queue_start,
1469 .rx_queue_stop = mlx5_rx_queue_stop,
1470 .tx_queue_start = mlx5_tx_queue_start,
1471 .tx_queue_stop = mlx5_tx_queue_stop,
1472 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1473 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1474 .mac_addr_remove = mlx5_mac_addr_remove,
1475 .mac_addr_add = mlx5_mac_addr_add,
1476 .mac_addr_set = mlx5_mac_addr_set,
1477 .set_mc_addr_list = mlx5_set_mc_addr_list,
1478 .mtu_set = mlx5_dev_set_mtu,
1479 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1480 .vlan_offload_set = mlx5_vlan_offload_set,
1481 .reta_update = mlx5_dev_rss_reta_update,
1482 .reta_query = mlx5_dev_rss_reta_query,
1483 .rss_hash_update = mlx5_rss_hash_update,
1484 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1485 .filter_ctrl = mlx5_dev_filter_ctrl,
1486 .rxq_info_get = mlx5_rxq_info_get,
1487 .txq_info_get = mlx5_txq_info_get,
1488 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1489 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1490 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1491 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1492 .is_removed = mlx5_is_removed,
1493 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1494 .get_module_info = mlx5_get_module_info,
1495 .get_module_eeprom = mlx5_get_module_eeprom,
1496 .hairpin_cap_get = mlx5_hairpin_cap_get,
1497 .mtr_ops_get = mlx5_flow_meter_ops_get,
1498 .hairpin_bind = mlx5_hairpin_bind,
1499 .hairpin_unbind = mlx5_hairpin_unbind,
1500 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1501 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1502 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1503 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1506 /* Available operations from secondary process. */
1507 const struct eth_dev_ops mlx5_dev_sec_ops = {
1508 .stats_get = mlx5_stats_get,
1509 .stats_reset = mlx5_stats_reset,
1510 .xstats_get = mlx5_xstats_get,
1511 .xstats_reset = mlx5_xstats_reset,
1512 .xstats_get_names = mlx5_xstats_get_names,
1513 .fw_version_get = mlx5_fw_version_get,
1514 .dev_infos_get = mlx5_dev_infos_get,
1515 .read_clock = mlx5_txpp_read_clock,
1516 .rx_queue_start = mlx5_rx_queue_start,
1517 .rx_queue_stop = mlx5_rx_queue_stop,
1518 .tx_queue_start = mlx5_tx_queue_start,
1519 .tx_queue_stop = mlx5_tx_queue_stop,
1520 .rxq_info_get = mlx5_rxq_info_get,
1521 .txq_info_get = mlx5_txq_info_get,
1522 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1523 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1524 .get_module_info = mlx5_get_module_info,
1525 .get_module_eeprom = mlx5_get_module_eeprom,
1528 /* Available operations in flow isolated mode. */
1529 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1530 .dev_configure = mlx5_dev_configure,
1531 .dev_start = mlx5_dev_start,
1532 .dev_stop = mlx5_dev_stop,
1533 .dev_set_link_down = mlx5_set_link_down,
1534 .dev_set_link_up = mlx5_set_link_up,
1535 .dev_close = mlx5_dev_close,
1536 .promiscuous_enable = mlx5_promiscuous_enable,
1537 .promiscuous_disable = mlx5_promiscuous_disable,
1538 .allmulticast_enable = mlx5_allmulticast_enable,
1539 .allmulticast_disable = mlx5_allmulticast_disable,
1540 .link_update = mlx5_link_update,
1541 .stats_get = mlx5_stats_get,
1542 .stats_reset = mlx5_stats_reset,
1543 .xstats_get = mlx5_xstats_get,
1544 .xstats_reset = mlx5_xstats_reset,
1545 .xstats_get_names = mlx5_xstats_get_names,
1546 .fw_version_get = mlx5_fw_version_get,
1547 .dev_infos_get = mlx5_dev_infos_get,
1548 .read_clock = mlx5_txpp_read_clock,
1549 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1550 .vlan_filter_set = mlx5_vlan_filter_set,
1551 .rx_queue_setup = mlx5_rx_queue_setup,
1552 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1553 .tx_queue_setup = mlx5_tx_queue_setup,
1554 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1555 .rx_queue_release = mlx5_rx_queue_release,
1556 .tx_queue_release = mlx5_tx_queue_release,
1557 .rx_queue_start = mlx5_rx_queue_start,
1558 .rx_queue_stop = mlx5_rx_queue_stop,
1559 .tx_queue_start = mlx5_tx_queue_start,
1560 .tx_queue_stop = mlx5_tx_queue_stop,
1561 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1562 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1563 .mac_addr_remove = mlx5_mac_addr_remove,
1564 .mac_addr_add = mlx5_mac_addr_add,
1565 .mac_addr_set = mlx5_mac_addr_set,
1566 .set_mc_addr_list = mlx5_set_mc_addr_list,
1567 .mtu_set = mlx5_dev_set_mtu,
1568 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1569 .vlan_offload_set = mlx5_vlan_offload_set,
1570 .filter_ctrl = mlx5_dev_filter_ctrl,
1571 .rxq_info_get = mlx5_rxq_info_get,
1572 .txq_info_get = mlx5_txq_info_get,
1573 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1574 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1575 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1576 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1577 .is_removed = mlx5_is_removed,
1578 .get_module_info = mlx5_get_module_info,
1579 .get_module_eeprom = mlx5_get_module_eeprom,
1580 .hairpin_cap_get = mlx5_hairpin_cap_get,
1581 .mtr_ops_get = mlx5_flow_meter_ops_get,
1582 .hairpin_bind = mlx5_hairpin_bind,
1583 .hairpin_unbind = mlx5_hairpin_unbind,
1584 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1585 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1586 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1587 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1591 * Verify and store value for device argument.
1594 * Key argument to verify.
1596 * Value associated with key.
1601 * 0 on success, a negative errno value otherwise and rte_errno is set.
1604 mlx5_args_check(const char *key, const char *val, void *opaque)
1606 struct mlx5_dev_config *config = opaque;
1610 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1611 if (!strcmp(MLX5_REPRESENTOR, key))
1614 tmp = strtol(val, NULL, 0);
1617 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1620 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1621 /* Negative values are acceptable for some keys only. */
1623 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1626 mod = tmp >= 0 ? tmp : -tmp;
1627 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1628 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1629 DRV_LOG(ERR, "invalid CQE compression "
1630 "format parameter");
1634 config->cqe_comp = !!tmp;
1635 config->cqe_comp_fmt = tmp;
1636 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1637 config->cqe_pad = !!tmp;
1638 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1639 config->hw_padding = !!tmp;
1640 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1641 config->mprq.enabled = !!tmp;
1642 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1643 config->mprq.stride_num_n = tmp;
1644 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1645 config->mprq.stride_size_n = tmp;
1646 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1647 config->mprq.max_memcpy_len = tmp;
1648 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1649 config->mprq.min_rxqs_num = tmp;
1650 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1651 DRV_LOG(WARNING, "%s: deprecated parameter,"
1652 " converted to txq_inline_max", key);
1653 config->txq_inline_max = tmp;
1654 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1655 config->txq_inline_max = tmp;
1656 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1657 config->txq_inline_min = tmp;
1658 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1659 config->txq_inline_mpw = tmp;
1660 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1661 config->txqs_inline = tmp;
1662 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1663 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1664 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1665 config->mps = !!tmp;
1666 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1667 if (tmp != MLX5_TXDB_CACHED &&
1668 tmp != MLX5_TXDB_NCACHED &&
1669 tmp != MLX5_TXDB_HEURISTIC) {
1670 DRV_LOG(ERR, "invalid Tx doorbell "
1671 "mapping parameter");
1676 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1677 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1678 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1679 DRV_LOG(WARNING, "%s: deprecated parameter,"
1680 " converted to txq_inline_mpw", key);
1681 config->txq_inline_mpw = tmp;
1682 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1683 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1684 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1686 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1690 config->tx_pp = tmp;
1691 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1692 config->tx_skew = tmp;
1693 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1694 config->rx_vec_en = !!tmp;
1695 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1696 config->l3_vxlan_en = !!tmp;
1697 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1698 config->vf_nl_en = !!tmp;
1699 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1700 config->dv_esw_en = !!tmp;
1701 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1702 config->dv_flow_en = !!tmp;
1703 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1704 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1705 tmp != MLX5_XMETA_MODE_META16 &&
1706 tmp != MLX5_XMETA_MODE_META32 &&
1707 tmp != MLX5_XMETA_MODE_MISS_INFO) {
1708 DRV_LOG(ERR, "invalid extensive "
1709 "metadata parameter");
1713 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1714 config->dv_xmeta_en = tmp;
1716 config->dv_miss_info = 1;
1717 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1718 config->lacp_by_user = !!tmp;
1719 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1720 config->mr_ext_memseg_en = !!tmp;
1721 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1722 config->max_dump_files_num = tmp;
1723 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1724 config->lro.timeout = tmp;
1725 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1726 DRV_LOG(DEBUG, "class argument is %s.", val);
1727 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1728 config->log_hp_size = tmp;
1729 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1730 if (tmp != MLX5_RCM_NONE &&
1731 tmp != MLX5_RCM_LIGHT &&
1732 tmp != MLX5_RCM_AGGR) {
1733 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1737 config->reclaim_mode = tmp;
1738 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1739 config->sys_mem_en = !!tmp;
1740 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1741 config->decap_en = !!tmp;
1743 DRV_LOG(WARNING, "%s: unknown parameter", key);
1751 * Parse device parameters.
1754 * Pointer to device configuration structure.
1756 * Device arguments structure.
1759 * 0 on success, a negative errno value otherwise and rte_errno is set.
1762 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1764 const char **params = (const char *[]){
1765 MLX5_RXQ_CQE_COMP_EN,
1766 MLX5_RXQ_CQE_PAD_EN,
1767 MLX5_RXQ_PKT_PAD_EN,
1769 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1770 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1771 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1774 MLX5_TXQ_INLINE_MIN,
1775 MLX5_TXQ_INLINE_MAX,
1776 MLX5_TXQ_INLINE_MPW,
1777 MLX5_TXQS_MIN_INLINE,
1780 MLX5_TXQ_MPW_HDR_DSEG_EN,
1781 MLX5_TXQ_MAX_INLINE_LEN,
1793 MLX5_MR_EXT_MEMSEG_EN,
1795 MLX5_MAX_DUMP_FILES_NUM,
1796 MLX5_LRO_TIMEOUT_USEC,
1797 MLX5_CLASS_ARG_NAME,
1804 struct rte_kvargs *kvlist;
1808 if (devargs == NULL)
1810 /* Following UGLY cast is done to pass checkpatch. */
1811 kvlist = rte_kvargs_parse(devargs->args, params);
1812 if (kvlist == NULL) {
1816 /* Process parameters. */
1817 for (i = 0; (params[i] != NULL); ++i) {
1818 if (rte_kvargs_count(kvlist, params[i])) {
1819 ret = rte_kvargs_process(kvlist, params[i],
1820 mlx5_args_check, config);
1823 rte_kvargs_free(kvlist);
1828 rte_kvargs_free(kvlist);
1833 * Configures the minimal amount of data to inline into WQE
1834 * while sending packets.
1836 * - the txq_inline_min has the maximal priority, if this
1837 * key is specified in devargs
1838 * - if DevX is enabled the inline mode is queried from the
1839 * device (HCA attributes and NIC vport context if needed).
1840 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1841 * and none (0 bytes) for other NICs
1844 * Verbs device parameters (name, port, switch_info) to spawn.
1846 * Device configuration parameters.
1849 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1850 struct mlx5_dev_config *config)
1852 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1853 /* Application defines size of inlined data explicitly. */
1854 switch (spawn->pci_dev->id.device_id) {
1855 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1856 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1857 if (config->txq_inline_min <
1858 (int)MLX5_INLINE_HSIZE_L2) {
1860 "txq_inline_mix aligned to minimal"
1861 " ConnectX-4 required value %d",
1862 (int)MLX5_INLINE_HSIZE_L2);
1863 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1869 if (config->hca_attr.eth_net_offloads) {
1870 /* We have DevX enabled, inline mode queried successfully. */
1871 switch (config->hca_attr.wqe_inline_mode) {
1872 case MLX5_CAP_INLINE_MODE_L2:
1873 /* outer L2 header must be inlined. */
1874 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1876 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1877 /* No inline data are required by NIC. */
1878 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1879 config->hw_vlan_insert =
1880 config->hca_attr.wqe_vlan_insert;
1881 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1883 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1884 /* inline mode is defined by NIC vport context. */
1885 if (!config->hca_attr.eth_virt)
1887 switch (config->hca_attr.vport_inline_mode) {
1888 case MLX5_INLINE_MODE_NONE:
1889 config->txq_inline_min =
1890 MLX5_INLINE_HSIZE_NONE;
1892 case MLX5_INLINE_MODE_L2:
1893 config->txq_inline_min =
1894 MLX5_INLINE_HSIZE_L2;
1896 case MLX5_INLINE_MODE_IP:
1897 config->txq_inline_min =
1898 MLX5_INLINE_HSIZE_L3;
1900 case MLX5_INLINE_MODE_TCP_UDP:
1901 config->txq_inline_min =
1902 MLX5_INLINE_HSIZE_L4;
1904 case MLX5_INLINE_MODE_INNER_L2:
1905 config->txq_inline_min =
1906 MLX5_INLINE_HSIZE_INNER_L2;
1908 case MLX5_INLINE_MODE_INNER_IP:
1909 config->txq_inline_min =
1910 MLX5_INLINE_HSIZE_INNER_L3;
1912 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1913 config->txq_inline_min =
1914 MLX5_INLINE_HSIZE_INNER_L4;
1920 * We get here if we are unable to deduce
1921 * inline data size with DevX. Try PCI ID
1922 * to determine old NICs.
1924 switch (spawn->pci_dev->id.device_id) {
1925 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1926 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1927 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1928 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1929 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1930 config->hw_vlan_insert = 0;
1932 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1933 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1934 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1935 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1937 * These NICs support VLAN insertion from WQE and
1938 * report the wqe_vlan_insert flag. But there is the bug
1939 * and PFC control may be broken, so disable feature.
1941 config->hw_vlan_insert = 0;
1942 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1945 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1949 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1953 * Configures the metadata mask fields in the shared context.
1956 * Pointer to Ethernet device.
1959 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1961 struct mlx5_priv *priv = dev->data->dev_private;
1962 struct mlx5_dev_ctx_shared *sh = priv->sh;
1963 uint32_t meta, mark, reg_c0;
1965 reg_c0 = ~priv->vport_meta_mask;
1966 switch (priv->config.dv_xmeta_en) {
1967 case MLX5_XMETA_MODE_LEGACY:
1969 mark = MLX5_FLOW_MARK_MASK;
1971 case MLX5_XMETA_MODE_META16:
1972 meta = reg_c0 >> rte_bsf32(reg_c0);
1973 mark = MLX5_FLOW_MARK_MASK;
1975 case MLX5_XMETA_MODE_META32:
1977 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1985 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1986 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1987 sh->dv_mark_mask, mark);
1989 sh->dv_mark_mask = mark;
1990 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1991 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1992 sh->dv_meta_mask, meta);
1994 sh->dv_meta_mask = meta;
1995 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1996 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1997 sh->dv_meta_mask, reg_c0);
1999 sh->dv_regc0_mask = reg_c0;
2000 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2001 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2002 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2003 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2007 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2009 static const char *const dynf_names[] = {
2010 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2011 RTE_MBUF_DYNFLAG_METADATA_NAME,
2012 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2016 if (n < RTE_DIM(dynf_names))
2018 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2019 if (names[i] == NULL)
2021 strcpy(names[i], dynf_names[i]);
2023 return RTE_DIM(dynf_names);
2027 * Comparison callback to sort device data.
2029 * This is meant to be used with qsort().
2032 * Pointer to pointer to first data object.
2034 * Pointer to pointer to second data object.
2037 * 0 if both objects are equal, less than 0 if the first argument is less
2038 * than the second, greater than 0 otherwise.
2041 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2042 struct mlx5_dev_config *config)
2044 struct mlx5_dev_ctx_shared *sh = priv->sh;
2045 struct mlx5_dev_config *sh_conf = NULL;
2049 /* Nothing to compare for the single/first device. */
2050 if (sh->refcnt == 1)
2052 /* Find the device with shared context. */
2053 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2054 struct mlx5_priv *opriv =
2055 rte_eth_devices[port_id].data->dev_private;
2057 if (opriv && opriv != priv && opriv->sh == sh) {
2058 sh_conf = &opriv->config;
2064 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2065 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2066 " for shared %s context", sh->ibdev_name);
2070 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2071 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2072 " for shared %s context", sh->ibdev_name);
2080 * Look for the ethernet device belonging to mlx5 driver.
2082 * @param[in] port_id
2083 * port_id to start looking for device.
2084 * @param[in] pci_dev
2085 * Pointer to the hint PCI device. When device is being probed
2086 * the its siblings (master and preceding representors might
2087 * not have assigned driver yet (because the mlx5_os_pci_probe()
2088 * is not completed yet, for this case match on hint PCI
2089 * device may be used to detect sibling device.
2092 * port_id of found device, RTE_MAX_ETHPORT if not found.
2095 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2097 while (port_id < RTE_MAX_ETHPORTS) {
2098 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2100 if (dev->state != RTE_ETH_DEV_UNUSED &&
2102 (dev->device == &pci_dev->device ||
2103 (dev->device->driver &&
2104 dev->device->driver->name &&
2105 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
2109 if (port_id >= RTE_MAX_ETHPORTS)
2110 return RTE_MAX_ETHPORTS;
2115 * DPDK callback to remove a PCI device.
2117 * This function removes all Ethernet devices belong to a given PCI device.
2119 * @param[in] pci_dev
2120 * Pointer to the PCI device.
2123 * 0 on success, the function cannot fail.
2126 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2131 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2133 * mlx5_dev_close() is not registered to secondary process,
2134 * call the close function explicitly for secondary process.
2136 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2137 ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2139 ret |= rte_eth_dev_close(port_id);
2141 return ret == 0 ? 0 : -EIO;
2144 static const struct rte_pci_id mlx5_pci_id_map[] = {
2146 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2147 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2150 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2151 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2154 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2155 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2158 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2159 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2162 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2163 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2166 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2167 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2170 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2171 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2174 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2175 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2178 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2179 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2182 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2183 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2186 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2187 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2190 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2191 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2194 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2195 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2198 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2199 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2202 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2203 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2206 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2207 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2210 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2211 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2214 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2215 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2222 static struct mlx5_pci_driver mlx5_driver = {
2223 .driver_class = MLX5_CLASS_NET,
2226 .name = MLX5_DRIVER_NAME,
2228 .id_table = mlx5_pci_id_map,
2229 .probe = mlx5_os_pci_probe,
2230 .remove = mlx5_pci_remove,
2231 .dma_map = mlx5_dma_map,
2232 .dma_unmap = mlx5_dma_unmap,
2233 .drv_flags = PCI_DRV_FLAGS,
2237 /* Initialize driver log type. */
2238 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2241 * Driver initialization routine.
2243 RTE_INIT(rte_mlx5_pmd_init)
2245 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2247 /* Build the static tables for Verbs conversion. */
2248 mlx5_set_ptype_table();
2249 mlx5_set_cksum_table();
2250 mlx5_set_swp_types_table();
2252 mlx5_pci_driver_register(&mlx5_driver);
2255 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2256 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2257 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");