drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 180
 181 /* Shared memory between primary and secondary processes. */
 182 struct mlx5_shared_data *mlx5_shared_data;
 183
 184 /** Driver-specific log messages type. */
 185 int mlx5_logtype;
 186
 187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 188                                                 LIST_HEAD_INITIALIZER();
 189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 192         [MLX5_IPOOL_DECAP_ENCAP] = {
 193                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 194                 .trunk_size = 64,
 195                 .grow_trunk = 3,
 196                 .grow_shift = 2,
 197                 .need_lock = 1,
 198                 .release_mem_en = 1,
 199                 .malloc = mlx5_malloc,
 200                 .free = mlx5_free,
 201                 .type = "mlx5_encap_decap_ipool",
 202         },
 203         [MLX5_IPOOL_PUSH_VLAN] = {
 204                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 1,
 209                 .release_mem_en = 1,
 210                 .malloc = mlx5_malloc,
 211                 .free = mlx5_free,
 212                 .type = "mlx5_push_vlan_ipool",
 213         },
 214         [MLX5_IPOOL_TAG] = {
 215                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 1,
 220                 .release_mem_en = 1,
 221                 .malloc = mlx5_malloc,
 222                 .free = mlx5_free,
 223                 .type = "mlx5_tag_ipool",
 224         },
 225         [MLX5_IPOOL_PORT_ID] = {
 226                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 1,
 231                 .release_mem_en = 1,
 232                 .malloc = mlx5_malloc,
 233                 .free = mlx5_free,
 234                 .type = "mlx5_port_id_ipool",
 235         },
 236         [MLX5_IPOOL_JUMP] = {
 237                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 1,
 242                 .release_mem_en = 1,
 243                 .malloc = mlx5_malloc,
 244                 .free = mlx5_free,
 245                 .type = "mlx5_jump_ipool",
 246         },
 247         [MLX5_IPOOL_SAMPLE] = {
 248                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 1,
 253                 .release_mem_en = 1,
 254                 .malloc = mlx5_malloc,
 255                 .free = mlx5_free,
 256                 .type = "mlx5_sample_ipool",
 257         },
 258         [MLX5_IPOOL_DEST_ARRAY] = {
 259                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 260                 .trunk_size = 64,
 261                 .grow_trunk = 3,
 262                 .grow_shift = 2,
 263                 .need_lock = 1,
 264                 .release_mem_en = 1,
 265                 .malloc = mlx5_malloc,
 266                 .free = mlx5_free,
 267                 .type = "mlx5_dest_array_ipool",
 268         },
 269         [MLX5_IPOOL_TUNNEL_ID] = {
 270                 .size = sizeof(struct mlx5_flow_tunnel),
 271                 .trunk_size = MLX5_MAX_TUNNELS,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .type = "mlx5_tunnel_offload",
 275         },
 276         [MLX5_IPOOL_TNL_TBL_ID] = {
 277                 .size = 0,
 278                 .need_lock = 1,
 279                 .type = "mlx5_flow_tnl_tbl_ipool",
 280         },
 281 #endif
 282         [MLX5_IPOOL_MTR] = {
 283                 /**
 284                  * The ipool index should grow continually from small to big,
 285                  * for meter idx, so not set grow_trunk to avoid meter index
 286                  * not jump continually.
 287                  */
 288                 .size = sizeof(struct mlx5_legacy_flow_meter),
 289                 .trunk_size = 64,
 290                 .need_lock = 1,
 291                 .release_mem_en = 1,
 292                 .malloc = mlx5_malloc,
 293                 .free = mlx5_free,
 294                 .type = "mlx5_meter_ipool",
 295         },
 296         [MLX5_IPOOL_MCP] = {
 297                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 298                 .trunk_size = 64,
 299                 .grow_trunk = 3,
 300                 .grow_shift = 2,
 301                 .need_lock = 1,
 302                 .release_mem_en = 1,
 303                 .malloc = mlx5_malloc,
 304                 .free = mlx5_free,
 305                 .type = "mlx5_mcp_ipool",
 306         },
 307         [MLX5_IPOOL_HRXQ] = {
 308                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 309                 .trunk_size = 64,
 310                 .grow_trunk = 3,
 311                 .grow_shift = 2,
 312                 .need_lock = 1,
 313                 .release_mem_en = 1,
 314                 .malloc = mlx5_malloc,
 315                 .free = mlx5_free,
 316                 .type = "mlx5_hrxq_ipool",
 317         },
 318         [MLX5_IPOOL_MLX5_FLOW] = {
 319                 /*
 320                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 321                  * It set in run time according to PCI function configuration.
 322                  */
 323                 .size = 0,
 324                 .trunk_size = 64,
 325                 .grow_trunk = 3,
 326                 .grow_shift = 2,
 327                 .need_lock = 1,
 328                 .release_mem_en = 0,
 329                 .per_core_cache = 1 << 19,
 330                 .malloc = mlx5_malloc,
 331                 .free = mlx5_free,
 332                 .type = "mlx5_flow_handle_ipool",
 333         },
 334         [MLX5_IPOOL_RTE_FLOW] = {
 335                 .size = sizeof(struct rte_flow),
 336                 .trunk_size = 4096,
 337                 .need_lock = 1,
 338                 .release_mem_en = 1,
 339                 .malloc = mlx5_malloc,
 340                 .free = mlx5_free,
 341                 .type = "rte_flow_ipool",
 342         },
 343         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 344                 .size = 0,
 345                 .need_lock = 1,
 346                 .type = "mlx5_flow_rss_id_ipool",
 347         },
 348         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 349                 .size = sizeof(struct mlx5_shared_action_rss),
 350                 .trunk_size = 64,
 351                 .grow_trunk = 3,
 352                 .grow_shift = 2,
 353                 .need_lock = 1,
 354                 .release_mem_en = 1,
 355                 .malloc = mlx5_malloc,
 356                 .free = mlx5_free,
 357                 .type = "mlx5_shared_action_rss",
 358         },
 359         [MLX5_IPOOL_MTR_POLICY] = {
 360                 /**
 361                  * The ipool index should grow continually from small to big,
 362                  * for policy idx, so not set grow_trunk to avoid policy index
 363                  * not jump continually.
 364                  */
 365                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 366                 .trunk_size = 64,
 367                 .need_lock = 1,
 368                 .release_mem_en = 1,
 369                 .malloc = mlx5_malloc,
 370                 .free = mlx5_free,
 371                 .type = "mlx5_meter_policy_ipool",
 372         },
 373 };
 374
 375
 376 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 377 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 378
 379 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 380
 381 /**
 382  * Decide whether representor ID is a HPF(host PF) port on BF2.
 383  *
 384  * @param dev
 385  *   Pointer to Ethernet device structure.
 386  *
 387  * @return
 388  *   Non-zero if HPF, otherwise 0.
 389  */
 390 bool
 391 mlx5_is_hpf(struct rte_eth_dev *dev)
 392 {
 393         struct mlx5_priv *priv = dev->data->dev_private;
 394         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 395         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 396
 397         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 398                MLX5_REPRESENTOR_REPR(-1) == repr;
 399 }
 400
 401 /**
 402  * Initialize the ASO aging management structure.
 403  *
 404  * @param[in] sh
 405  *   Pointer to mlx5_dev_ctx_shared object to free
 406  *
 407  * @return
 408  *   0 on success, a negative errno value otherwise and rte_errno is set.
 409  */
 410 int
 411 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 412 {
 413         int err;
 414
 415         if (sh->aso_age_mng)
 416                 return 0;
 417         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 418                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 419         if (!sh->aso_age_mng) {
 420                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 421                 rte_errno = ENOMEM;
 422                 return -ENOMEM;
 423         }
 424         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 425         if (err) {
 426                 mlx5_free(sh->aso_age_mng);
 427                 return -1;
 428         }
 429         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 430         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 431         LIST_INIT(&sh->aso_age_mng->free);
 432         return 0;
 433 }
 434
 435 /**
 436  * Close and release all the resources of the ASO aging management structure.
 437  *
 438  * @param[in] sh
 439  *   Pointer to mlx5_dev_ctx_shared object to free.
 440  */
 441 static void
 442 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 443 {
 444         int i, j;
 445
 446         mlx5_aso_flow_hit_queue_poll_stop(sh);
 447         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 448         if (sh->aso_age_mng->pools) {
 449                 struct mlx5_aso_age_pool *pool;
 450
 451                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 452                         pool = sh->aso_age_mng->pools[i];
 453                         claim_zero(mlx5_devx_cmd_destroy
 454                                                 (pool->flow_hit_aso_obj));
 455                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 456                                 if (pool->actions[j].dr_action)
 457                                         claim_zero
 458                                             (mlx5_flow_os_destroy_flow_action
 459                                               (pool->actions[j].dr_action));
 460                         mlx5_free(pool);
 461                 }
 462                 mlx5_free(sh->aso_age_mng->pools);
 463         }
 464         mlx5_free(sh->aso_age_mng);
 465 }
 466
 467 /**
 468  * Initialize the shared aging list information per port.
 469  *
 470  * @param[in] sh
 471  *   Pointer to mlx5_dev_ctx_shared object.
 472  */
 473 static void
 474 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 475 {
 476         uint32_t i;
 477         struct mlx5_age_info *age_info;
 478
 479         for (i = 0; i < sh->max_port; i++) {
 480                 age_info = &sh->port[i].age_info;
 481                 age_info->flags = 0;
 482                 TAILQ_INIT(&age_info->aged_counters);
 483                 LIST_INIT(&age_info->aged_aso);
 484                 rte_spinlock_init(&age_info->aged_sl);
 485                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 486         }
 487 }
 488
 489 /**
 490  * Initialize the counters management structure.
 491  *
 492  * @param[in] sh
 493  *   Pointer to mlx5_dev_ctx_shared object to free
 494  */
 495 static void
 496 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 497 {
 498         int i;
 499
 500         memset(&sh->cmng, 0, sizeof(sh->cmng));
 501         TAILQ_INIT(&sh->cmng.flow_counters);
 502         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 503         sh->cmng.max_id = -1;
 504         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 505         rte_spinlock_init(&sh->cmng.pool_update_sl);
 506         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 507                 TAILQ_INIT(&sh->cmng.counters[i]);
 508                 rte_spinlock_init(&sh->cmng.csl[i]);
 509         }
 510 }
 511
 512 /**
 513  * Destroy all the resources allocated for a counter memory management.
 514  *
 515  * @param[in] mng
 516  *   Pointer to the memory management structure.
 517  */
 518 static void
 519 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 520 {
 521         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 522
 523         LIST_REMOVE(mng, next);
 524         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 525         claim_zero(mlx5_os_umem_dereg(mng->umem));
 526         mlx5_free(mem);
 527 }
 528
 529 /**
 530  * Close and release all the resources of the counters management.
 531  *
 532  * @param[in] sh
 533  *   Pointer to mlx5_dev_ctx_shared object to free.
 534  */
 535 static void
 536 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 537 {
 538         struct mlx5_counter_stats_mem_mng *mng;
 539         int i, j;
 540         int retries = 1024;
 541
 542         rte_errno = 0;
 543         while (--retries) {
 544                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 545                 if (rte_errno != EINPROGRESS)
 546                         break;
 547                 rte_pause();
 548         }
 549
 550         if (sh->cmng.pools) {
 551                 struct mlx5_flow_counter_pool *pool;
 552                 uint16_t n_valid = sh->cmng.n_valid;
 553                 bool fallback = sh->cmng.counter_fallback;
 554
 555                 for (i = 0; i < n_valid; ++i) {
 556                         pool = sh->cmng.pools[i];
 557                         if (!fallback && pool->min_dcs)
 558                                 claim_zero(mlx5_devx_cmd_destroy
 559                                                                (pool->min_dcs));
 560                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 561                                 struct mlx5_flow_counter *cnt =
 562                                                 MLX5_POOL_GET_CNT(pool, j);
 563
 564                                 if (cnt->action)
 565                                         claim_zero
 566                                          (mlx5_flow_os_destroy_flow_action
 567                                           (cnt->action));
 568                                 if (fallback && MLX5_POOL_GET_CNT
 569                                     (pool, j)->dcs_when_free)
 570                                         claim_zero(mlx5_devx_cmd_destroy
 571                                                    (cnt->dcs_when_free));
 572                         }
 573                         mlx5_free(pool);
 574                 }
 575                 mlx5_free(sh->cmng.pools);
 576         }
 577         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 578         while (mng) {
 579                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 580                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 581         }
 582         memset(&sh->cmng, 0, sizeof(sh->cmng));
 583 }
 584
 585 /**
 586  * Initialize the aso flow meters management structure.
 587  *
 588  * @param[in] sh
 589  *   Pointer to mlx5_dev_ctx_shared object to free
 590  */
 591 int
 592 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 593 {
 594         if (!sh->mtrmng) {
 595                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 596                         sizeof(*sh->mtrmng),
 597                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 598                 if (!sh->mtrmng) {
 599                         DRV_LOG(ERR,
 600                         "meter management allocation was failed.");
 601                         rte_errno = ENOMEM;
 602                         return -ENOMEM;
 603                 }
 604                 if (sh->meter_aso_en) {
 605                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 606                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 607                 }
 608                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 609         }
 610         return 0;
 611 }
 612
 613 /**
 614  * Close and release all the resources of
 615  * the ASO flow meter management structure.
 616  *
 617  * @param[in] sh
 618  *   Pointer to mlx5_dev_ctx_shared object to free.
 619  */
 620 static void
 621 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 622 {
 623         struct mlx5_aso_mtr_pool *mtr_pool;
 624         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 625         uint32_t idx;
 626 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 627         struct mlx5_aso_mtr *aso_mtr;
 628         int i;
 629 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 630
 631         if (sh->meter_aso_en) {
 632                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 633                 idx = mtrmng->pools_mng.n_valid;
 634                 while (idx--) {
 635                         mtr_pool = mtrmng->pools_mng.pools[idx];
 636 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 637                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 638                                 aso_mtr = &mtr_pool->mtrs[i];
 639                                 if (aso_mtr->fm.meter_action)
 640                                         claim_zero
 641                                         (mlx5_glue->destroy_flow_action
 642                                         (aso_mtr->fm.meter_action));
 643                         }
 644 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 645                         claim_zero(mlx5_devx_cmd_destroy
 646                                                 (mtr_pool->devx_obj));
 647                         mtrmng->pools_mng.n_valid--;
 648                         mlx5_free(mtr_pool);
 649                 }
 650                 mlx5_free(sh->mtrmng->pools_mng.pools);
 651         }
 652         mlx5_free(sh->mtrmng);
 653         sh->mtrmng = NULL;
 654 }
 655
 656 /* Send FLOW_AGED event if needed. */
 657 void
 658 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 659 {
 660         struct mlx5_age_info *age_info;
 661         uint32_t i;
 662
 663         for (i = 0; i < sh->max_port; i++) {
 664                 age_info = &sh->port[i].age_info;
 665                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 666                         continue;
 667                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 668                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 669                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 670                         rte_eth_dev_callback_process
 671                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 672                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 673                 }
 674         }
 675 }
 676
 677 /*
 678  * Initialize the ASO connection tracking structure.
 679  *
 680  * @param[in] sh
 681  *   Pointer to mlx5_dev_ctx_shared object.
 682  *
 683  * @return
 684  *   0 on success, a negative errno value otherwise and rte_errno is set.
 685  */
 686 int
 687 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 688 {
 689         int err;
 690
 691         if (sh->ct_mng)
 692                 return 0;
 693         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 694                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 695         if (!sh->ct_mng) {
 696                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 697                 rte_errno = ENOMEM;
 698                 return -rte_errno;
 699         }
 700         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 701         if (err) {
 702                 mlx5_free(sh->ct_mng);
 703                 /* rte_errno should be extracted from the failure. */
 704                 rte_errno = EINVAL;
 705                 return -rte_errno;
 706         }
 707         rte_spinlock_init(&sh->ct_mng->ct_sl);
 708         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 709         LIST_INIT(&sh->ct_mng->free_cts);
 710         return 0;
 711 }
 712
 713 /*
 714  * Close and release all the resources of the
 715  * ASO connection tracking management structure.
 716  *
 717  * @param[in] sh
 718  *   Pointer to mlx5_dev_ctx_shared object to free.
 719  */
 720 static void
 721 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 722 {
 723         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 724         struct mlx5_aso_ct_pool *ct_pool;
 725         struct mlx5_aso_ct_action *ct;
 726         uint32_t idx;
 727         uint32_t val;
 728         uint32_t cnt;
 729         int i;
 730
 731         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 732         idx = mng->next;
 733         while (idx--) {
 734                 cnt = 0;
 735                 ct_pool = mng->pools[idx];
 736                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 737                         ct = &ct_pool->actions[i];
 738                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 739                                                  __ATOMIC_RELAXED);
 740                         MLX5_ASSERT(val == 1);
 741                         if (val > 1)
 742                                 cnt++;
 743 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 744                         if (ct->dr_action_orig)
 745                                 claim_zero(mlx5_glue->destroy_flow_action
 746                                                         (ct->dr_action_orig));
 747                         if (ct->dr_action_rply)
 748                                 claim_zero(mlx5_glue->destroy_flow_action
 749                                                         (ct->dr_action_rply));
 750 #endif
 751                 }
 752                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 753                 if (cnt) {
 754                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 755                                 cnt, i);
 756                 }
 757                 mlx5_free(ct_pool);
 758                 /* in case of failure. */
 759                 mng->next--;
 760         }
 761         mlx5_free(mng->pools);
 762         mlx5_free(mng);
 763         /* Management structure must be cleared to 0s during allocation. */
 764         sh->ct_mng = NULL;
 765 }
 766
 767 /**
 768  * Initialize the flow resources' indexed mempool.
 769  *
 770  * @param[in] sh
 771  *   Pointer to mlx5_dev_ctx_shared object.
 772  * @param[in] config
 773  *   Pointer to user dev config.
 774  */
 775 static void
 776 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 777                        const struct mlx5_dev_config *config)
 778 {
 779         uint8_t i;
 780         struct mlx5_indexed_pool_config cfg;
 781
 782         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 783                 cfg = mlx5_ipool_cfg[i];
 784                 switch (i) {
 785                 default:
 786                         break;
 787                 /*
 788                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 789                  * according to PCI function flow configuration.
 790                  */
 791                 case MLX5_IPOOL_MLX5_FLOW:
 792                         cfg.size = config->dv_flow_en ?
 793                                 sizeof(struct mlx5_flow_handle) :
 794                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 795                         break;
 796                 }
 797                 if (config->reclaim_mode) {
 798                         cfg.release_mem_en = 1;
 799                         cfg.per_core_cache = 0;
 800                 }
 801                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 802         }
 803 }
 804
 805 /**
 806  * Release the flow resources' indexed mempool.
 807  *
 808  * @param[in] sh
 809  *   Pointer to mlx5_dev_ctx_shared object.
 810  */
 811 static void
 812 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 813 {
 814         uint8_t i;
 815
 816         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 817                 mlx5_ipool_destroy(sh->ipool[i]);
 818 }
 819
 820 /*
 821  * Check if dynamic flex parser for eCPRI already exists.
 822  *
 823  * @param dev
 824  *   Pointer to Ethernet device structure.
 825  *
 826  * @return
 827  *   true on exists, false on not.
 828  */
 829 bool
 830 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 831 {
 832         struct mlx5_priv *priv = dev->data->dev_private;
 833         struct mlx5_flex_parser_profiles *prf =
 834                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 835
 836         return !!prf->obj;
 837 }
 838
 839 /*
 840  * Allocation of a flex parser for eCPRI. Once created, this parser related
 841  * resources will be held until the device is closed.
 842  *
 843  * @param dev
 844  *   Pointer to Ethernet device structure.
 845  *
 846  * @return
 847  *   0 on success, a negative errno value otherwise and rte_errno is set.
 848  */
 849 int
 850 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 851 {
 852         struct mlx5_priv *priv = dev->data->dev_private;
 853         struct mlx5_flex_parser_profiles *prf =
 854                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 855         struct mlx5_devx_graph_node_attr node = {
 856                 .modify_field_select = 0,
 857         };
 858         uint32_t ids[8];
 859         int ret;
 860
 861         if (!priv->config.hca_attr.parse_graph_flex_node) {
 862                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 863                         "for device %s.", priv->dev_data->name);
 864                 return -ENOTSUP;
 865         }
 866         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 867         /* 8 bytes now: 4B common header + 4B message body header. */
 868         node.header_length_base_value = 0x8;
 869         /* After MAC layer: Ether / VLAN. */
 870         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 871         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 872         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 873         /* Sample #0: type in common header. */
 874         node.sample[0].flow_match_sample_en = 1;
 875         /* Fixed offset. */
 876         node.sample[0].flow_match_sample_offset_mode = 0x0;
 877         /* Only the 2nd byte will be used. */
 878         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 879         /* Sample #1: message payload. */
 880         node.sample[1].flow_match_sample_en = 1;
 881         /* Fixed offset. */
 882         node.sample[1].flow_match_sample_offset_mode = 0x0;
 883         /*
 884          * Only the first two bytes will be used right now, and its offset will
 885          * start after the common header that with the length of a DW(u32).
 886          */
 887         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 888         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 889         if (!prf->obj) {
 890                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 891                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 892         }
 893         prf->num = 2;
 894         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 895         if (ret) {
 896                 DRV_LOG(ERR, "Failed to query sample IDs.");
 897                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 898         }
 899         prf->offset[0] = 0x0;
 900         prf->offset[1] = sizeof(uint32_t);
 901         prf->ids[0] = ids[0];
 902         prf->ids[1] = ids[1];
 903         return 0;
 904 }
 905
 906 /*
 907  * Destroy the flex parser node, including the parser itself, input / output
 908  * arcs and DW samples. Resources could be reused then.
 909  *
 910  * @param dev
 911  *   Pointer to Ethernet device structure.
 912  */
 913 static void
 914 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 915 {
 916         struct mlx5_priv *priv = dev->data->dev_private;
 917         struct mlx5_flex_parser_profiles *prf =
 918                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 919
 920         if (prf->obj)
 921                 mlx5_devx_cmd_destroy(prf->obj);
 922         prf->obj = NULL;
 923 }
 924
 925 /*
 926  * Allocate Rx and Tx UARs in robust fashion.
 927  * This routine handles the following UAR allocation issues:
 928  *
 929  *  - tries to allocate the UAR with the most appropriate memory
 930  *    mapping type from the ones supported by the host
 931  *
 932  *  - tries to allocate the UAR with non-NULL base address
 933  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 934  *    UAR base address if UAR was not the first object in the UAR page.
 935  *    It caused the PMD failure and we should try to get another UAR
 936  *    till we get the first one with non-NULL base address returned.
 937  */
 938 static int
 939 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 940                      const struct mlx5_dev_config *config)
 941 {
 942         uint32_t uar_mapping, retry;
 943         int err = 0;
 944         void *base_addr;
 945
 946         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 947 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 948                 /* Control the mapping type according to the settings. */
 949                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 950                               MLX5DV_UAR_ALLOC_TYPE_NC :
 951                               MLX5DV_UAR_ALLOC_TYPE_BF;
 952 #else
 953                 RTE_SET_USED(config);
 954                 /*
 955                  * It seems we have no way to control the memory mapping type
 956                  * for the UAR, the default "Write-Combining" type is supposed.
 957                  * The UAR initialization on queue creation queries the
 958                  * actual mapping type done by Verbs/kernel and setups the
 959                  * PMD datapath accordingly.
 960                  */
 961                 uar_mapping = 0;
 962 #endif
 963                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 964 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 965                 if (!sh->tx_uar &&
 966                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 967                         if (config->dbnc == MLX5_TXDB_CACHED ||
 968                             config->dbnc == MLX5_TXDB_HEURISTIC)
 969                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 970                                                  "is not supported by DevX");
 971                         /*
 972                          * In some environments like virtual machine
 973                          * the Write Combining mapped might be not supported
 974                          * and UAR allocation fails. We try "Non-Cached"
 975                          * mapping for the case. The tx_burst routines take
 976                          * the UAR mapping type into account on UAR setup
 977                          * on queue creation.
 978                          */
 979                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 980                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 981                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 982                                                         (sh->ctx, uar_mapping);
 983                 } else if (!sh->tx_uar &&
 984                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 985                         if (config->dbnc == MLX5_TXDB_NCACHED)
 986                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 987                                                  "is not supported by DevX");
 988                         /*
 989                          * If Verbs/kernel does not support "Non-Cached"
 990                          * try the "Write-Combining".
 991                          */
 992                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 993                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 994                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 995                                                         (sh->ctx, uar_mapping);
 996                 }
 997 #endif
 998                 if (!sh->tx_uar) {
 999                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1000                         err = ENOMEM;
1001                         goto exit;
1002                 }
1003                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1004                 if (base_addr)
1005                         break;
1006                 /*
1007                  * The UARs are allocated by rdma_core within the
1008                  * IB device context, on context closure all UARs
1009                  * will be freed, should be no memory/object leakage.
1010                  */
1011                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1012                 sh->tx_uar = NULL;
1013         }
1014         /* Check whether we finally succeeded with valid UAR allocation. */
1015         if (!sh->tx_uar) {
1016                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1017                 err = ENOMEM;
1018                 goto exit;
1019         }
1020         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1021                 uar_mapping = 0;
1022                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1023                                                         (sh->ctx, uar_mapping);
1024 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1025                 if (!sh->devx_rx_uar &&
1026                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1027                         /*
1028                          * Rx UAR is used to control interrupts only,
1029                          * should be no datapath noticeable impact,
1030                          * can try "Non-Cached" mapping safely.
1031                          */
1032                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1033                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1034                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1035                                                         (sh->ctx, uar_mapping);
1036                 }
1037 #endif
1038                 if (!sh->devx_rx_uar) {
1039                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1040                         err = ENOMEM;
1041                         goto exit;
1042                 }
1043                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1044                 if (base_addr)
1045                         break;
1046                 /*
1047                  * The UARs are allocated by rdma_core within the
1048                  * IB device context, on context closure all UARs
1049                  * will be freed, should be no memory/object leakage.
1050                  */
1051                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1052                 sh->devx_rx_uar = NULL;
1053         }
1054         /* Check whether we finally succeeded with valid UAR allocation. */
1055         if (!sh->devx_rx_uar) {
1056                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1057                 err = ENOMEM;
1058         }
1059 exit:
1060         return err;
1061 }
1062
1063 /**
1064  * Allocate shared device context. If there is multiport device the
1065  * master and representors will share this context, if there is single
1066  * port dedicated device, the context will be used by only given
1067  * port due to unification.
1068  *
1069  * Routine first searches the context for the specified device name,
1070  * if found the shared context assumed and reference counter is incremented.
1071  * If no context found the new one is created and initialized with specified
1072  * device context and parameters.
1073  *
1074  * @param[in] spawn
1075  *   Pointer to the device attributes (name, port, etc).
1076  * @param[in] config
1077  *   Pointer to device configuration structure.
1078  *
1079  * @return
1080  *   Pointer to mlx5_dev_ctx_shared object on success,
1081  *   otherwise NULL and rte_errno is set.
1082  */
1083 struct mlx5_dev_ctx_shared *
1084 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1085                            const struct mlx5_dev_config *config)
1086 {
1087         struct mlx5_dev_ctx_shared *sh;
1088         int err = 0;
1089         uint32_t i;
1090         struct mlx5_devx_tis_attr tis_attr = { 0 };
1091
1092         MLX5_ASSERT(spawn);
1093         /* Secondary process should not create the shared context. */
1094         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1095         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1096         /* Search for IB context by device name. */
1097         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1098                 if (!strcmp(sh->ibdev_name,
1099                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1100                         sh->refcnt++;
1101                         goto exit;
1102                 }
1103         }
1104         /* No device found, we have to create new shared context. */
1105         MLX5_ASSERT(spawn->max_port);
1106         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1107                          sizeof(struct mlx5_dev_ctx_shared) +
1108                          spawn->max_port *
1109                          sizeof(struct mlx5_dev_shared_port),
1110                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1111         if (!sh) {
1112                 DRV_LOG(ERR, "shared context allocation failure");
1113                 rte_errno  = ENOMEM;
1114                 goto exit;
1115         }
1116         if (spawn->bond_info)
1117                 sh->bond = *spawn->bond_info;
1118         err = mlx5_os_open_device(spawn, config, sh);
1119         if (!sh->ctx)
1120                 goto error;
1121         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1122         if (err) {
1123                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1124                 goto error;
1125         }
1126         sh->refcnt = 1;
1127         sh->max_port = spawn->max_port;
1128         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1129                 sizeof(sh->ibdev_name) - 1);
1130         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1131                 sizeof(sh->ibdev_path) - 1);
1132         /*
1133          * Setting port_id to max unallowed value means
1134          * there is no interrupt subhandler installed for
1135          * the given port index i.
1136          */
1137         for (i = 0; i < sh->max_port; i++) {
1138                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1139                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1140         }
1141         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1142         if (sh->pd == NULL) {
1143                 DRV_LOG(ERR, "PD allocation failure");
1144                 err = ENOMEM;
1145                 goto error;
1146         }
1147         if (sh->devx) {
1148                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1149                 if (err) {
1150                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1151                         goto error;
1152                 }
1153                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1154                 if (!sh->td) {
1155                         DRV_LOG(ERR, "TD allocation failure");
1156                         err = ENOMEM;
1157                         goto error;
1158                 }
1159                 tis_attr.transport_domain = sh->td->id;
1160                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1161                 if (!sh->tis) {
1162                         DRV_LOG(ERR, "TIS allocation failure");
1163                         err = ENOMEM;
1164                         goto error;
1165                 }
1166                 err = mlx5_alloc_rxtx_uars(sh, config);
1167                 if (err)
1168                         goto error;
1169                 MLX5_ASSERT(sh->tx_uar);
1170                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1171
1172                 MLX5_ASSERT(sh->devx_rx_uar);
1173                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1174         }
1175 #ifndef RTE_ARCH_64
1176         /* Initialize UAR access locks for 32bit implementations. */
1177         rte_spinlock_init(&sh->uar_lock_cq);
1178         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1179                 rte_spinlock_init(&sh->uar_lock[i]);
1180 #endif
1181         /*
1182          * Once the device is added to the list of memory event
1183          * callback, its global MR cache table cannot be expanded
1184          * on the fly because of deadlock. If it overflows, lookup
1185          * should be done by searching MR list linearly, which is slow.
1186          *
1187          * At this point the device is not added to the memory
1188          * event list yet, context is just being created.
1189          */
1190         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1191                                  MLX5_MR_BTREE_CACHE_N * 2,
1192                                  spawn->pci_dev->device.numa_node);
1193         if (err) {
1194                 err = rte_errno;
1195                 goto error;
1196         }
1197         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1198                               &sh->share_cache.dereg_mr_cb);
1199         mlx5_os_dev_shared_handler_install(sh);
1200         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1201         if (!sh->cnt_id_tbl) {
1202                 err = rte_errno;
1203                 goto error;
1204         }
1205         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1206                 err = mlx5_flow_os_init_workspace_once();
1207                 if (err)
1208                         goto error;
1209         }
1210         mlx5_flow_aging_init(sh);
1211         mlx5_flow_counters_mng_init(sh);
1212         mlx5_flow_ipool_create(sh, config);
1213         /* Add device to memory callback list. */
1214         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1215         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1216                          sh, mem_event_cb);
1217         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1218         /* Add context to the global device list. */
1219         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1220         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1221 exit:
1222         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1223         return sh;
1224 error:
1225         pthread_mutex_destroy(&sh->txpp.mutex);
1226         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1227         MLX5_ASSERT(sh);
1228         if (sh->cnt_id_tbl)
1229                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1230         if (sh->tis)
1231                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1232         if (sh->td)
1233                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1234         if (sh->devx_rx_uar)
1235                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1236         if (sh->tx_uar)
1237                 mlx5_glue->devx_free_uar(sh->tx_uar);
1238         if (sh->pd)
1239                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1240         if (sh->ctx)
1241                 claim_zero(mlx5_glue->close_device(sh->ctx));
1242         mlx5_free(sh);
1243         MLX5_ASSERT(err > 0);
1244         rte_errno = err;
1245         return NULL;
1246 }
1247
1248 /**
1249  * Free shared IB device context. Decrement counter and if zero free
1250  * all allocated resources and close handles.
1251  *
1252  * @param[in] sh
1253  *   Pointer to mlx5_dev_ctx_shared object to free
1254  */
1255 void
1256 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1257 {
1258         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1259 #ifdef RTE_LIBRTE_MLX5_DEBUG
1260         /* Check the object presence in the list. */
1261         struct mlx5_dev_ctx_shared *lctx;
1262
1263         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1264                 if (lctx == sh)
1265                         break;
1266         MLX5_ASSERT(lctx);
1267         if (lctx != sh) {
1268                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1269                 goto exit;
1270         }
1271 #endif
1272         MLX5_ASSERT(sh);
1273         MLX5_ASSERT(sh->refcnt);
1274         /* Secondary process should not free the shared context. */
1275         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1276         if (--sh->refcnt)
1277                 goto exit;
1278         /* Remove from memory callback device list. */
1279         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1280         LIST_REMOVE(sh, mem_event_cb);
1281         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1282         /* Release created Memory Regions. */
1283         mlx5_mr_release_cache(&sh->share_cache);
1284         /* Remove context from the global device list. */
1285         LIST_REMOVE(sh, next);
1286         /* Release flow workspaces objects on the last device. */
1287         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1288                 mlx5_flow_os_release_workspace();
1289         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1290         /*
1291          *  Ensure there is no async event handler installed.
1292          *  Only primary process handles async device events.
1293          **/
1294         mlx5_flow_counters_mng_close(sh);
1295         if (sh->aso_age_mng) {
1296                 mlx5_flow_aso_age_mng_close(sh);
1297                 sh->aso_age_mng = NULL;
1298         }
1299         if (sh->mtrmng)
1300                 mlx5_aso_flow_mtrs_mng_close(sh);
1301         mlx5_flow_ipool_destroy(sh);
1302         mlx5_os_dev_shared_handler_uninstall(sh);
1303         if (sh->cnt_id_tbl) {
1304                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1305                 sh->cnt_id_tbl = NULL;
1306         }
1307         if (sh->tx_uar) {
1308                 mlx5_glue->devx_free_uar(sh->tx_uar);
1309                 sh->tx_uar = NULL;
1310         }
1311         if (sh->pd)
1312                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1313         if (sh->tis)
1314                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1315         if (sh->td)
1316                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1317         if (sh->devx_rx_uar)
1318                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1319         if (sh->ctx)
1320                 claim_zero(mlx5_glue->close_device(sh->ctx));
1321         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1322         pthread_mutex_destroy(&sh->txpp.mutex);
1323         mlx5_free(sh);
1324         return;
1325 exit:
1326         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1327 }
1328
1329 /**
1330  * Destroy table hash list.
1331  *
1332  * @param[in] priv
1333  *   Pointer to the private device data structure.
1334  */
1335 void
1336 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1337 {
1338         struct mlx5_dev_ctx_shared *sh = priv->sh;
1339
1340         if (!sh->flow_tbls)
1341                 return;
1342         mlx5_hlist_destroy(sh->flow_tbls);
1343 }
1344
1345 /**
1346  * Initialize flow table hash list and create the root tables entry
1347  * for each domain.
1348  *
1349  * @param[in] priv
1350  *   Pointer to the private device data structure.
1351  *
1352  * @return
1353  *   Zero on success, positive error code otherwise.
1354  */
1355 int
1356 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1357 {
1358         int err = 0;
1359         /* Tables are only used in DV and DR modes. */
1360 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1361         struct mlx5_dev_ctx_shared *sh = priv->sh;
1362         char s[MLX5_HLIST_NAMESIZE];
1363
1364         MLX5_ASSERT(sh);
1365         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1366         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1367                                           0, 0, flow_dv_tbl_create_cb,
1368                                           flow_dv_tbl_match_cb,
1369                                           flow_dv_tbl_remove_cb);
1370         if (!sh->flow_tbls) {
1371                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1372                 err = ENOMEM;
1373                 return err;
1374         }
1375         sh->flow_tbls->ctx = sh;
1376 #ifndef HAVE_MLX5DV_DR
1377         struct rte_flow_error error;
1378         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1379
1380         /*
1381          * In case we have not DR support, the zero tables should be created
1382          * because DV expect to see them even if they cannot be created by
1383          * RDMA-CORE.
1384          */
1385         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1386                 NULL, 0, 1, 0, &error) ||
1387             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1388                 NULL, 0, 1, 0, &error) ||
1389             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1390                 NULL, 0, 1, 0, &error)) {
1391                 err = ENOMEM;
1392                 goto error;
1393         }
1394         return err;
1395 error:
1396         mlx5_free_table_hash_list(priv);
1397 #endif /* HAVE_MLX5DV_DR */
1398 #endif
1399         return err;
1400 }
1401
1402 /**
1403  * Retrieve integer value from environment variable.
1404  *
1405  * @param[in] name
1406  *   Environment variable name.
1407  *
1408  * @return
1409  *   Integer value, 0 if the variable is not set.
1410  */
1411 int
1412 mlx5_getenv_int(const char *name)
1413 {
1414         const char *val = getenv(name);
1415
1416         if (val == NULL)
1417                 return 0;
1418         return atoi(val);
1419 }
1420
1421 /**
1422  * DPDK callback to add udp tunnel port
1423  *
1424  * @param[in] dev
1425  *   A pointer to eth_dev
1426  * @param[in] udp_tunnel
1427  *   A pointer to udp tunnel
1428  *
1429  * @return
1430  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1431  */
1432 int
1433 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1434                          struct rte_eth_udp_tunnel *udp_tunnel)
1435 {
1436         MLX5_ASSERT(udp_tunnel != NULL);
1437         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1438             udp_tunnel->udp_port == 4789)
1439                 return 0;
1440         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1441             udp_tunnel->udp_port == 4790)
1442                 return 0;
1443         return -ENOTSUP;
1444 }
1445
1446 /**
1447  * Initialize process private data structure.
1448  *
1449  * @param dev
1450  *   Pointer to Ethernet device structure.
1451  *
1452  * @return
1453  *   0 on success, a negative errno value otherwise and rte_errno is set.
1454  */
1455 int
1456 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1457 {
1458         struct mlx5_priv *priv = dev->data->dev_private;
1459         struct mlx5_proc_priv *ppriv;
1460         size_t ppriv_size;
1461
1462         mlx5_proc_priv_uninit(dev);
1463         /*
1464          * UAR register table follows the process private structure. BlueFlame
1465          * registers for Tx queues are stored in the table.
1466          */
1467         ppriv_size =
1468                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1469         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1470                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1471         if (!ppriv) {
1472                 rte_errno = ENOMEM;
1473                 return -rte_errno;
1474         }
1475         ppriv->uar_table_sz = priv->txqs_n;
1476         dev->process_private = ppriv;
1477         return 0;
1478 }
1479
1480 /**
1481  * Un-initialize process private data structure.
1482  *
1483  * @param dev
1484  *   Pointer to Ethernet device structure.
1485  */
1486 void
1487 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1488 {
1489         if (!dev->process_private)
1490                 return;
1491         mlx5_free(dev->process_private);
1492         dev->process_private = NULL;
1493 }
1494
1495 /**
1496  * DPDK callback to close the device.
1497  *
1498  * Destroy all queues and objects, free memory.
1499  *
1500  * @param dev
1501  *   Pointer to Ethernet device structure.
1502  */
1503 int
1504 mlx5_dev_close(struct rte_eth_dev *dev)
1505 {
1506         struct mlx5_priv *priv = dev->data->dev_private;
1507         unsigned int i;
1508         int ret;
1509
1510         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1511                 /* Check if process_private released. */
1512                 if (!dev->process_private)
1513                         return 0;
1514                 mlx5_tx_uar_uninit_secondary(dev);
1515                 mlx5_proc_priv_uninit(dev);
1516                 rte_eth_dev_release_port(dev);
1517                 return 0;
1518         }
1519         if (!priv->sh)
1520                 return 0;
1521         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1522                 dev->data->port_id,
1523                 ((priv->sh->ctx != NULL) ?
1524                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1525         /*
1526          * If default mreg copy action is removed at the stop stage,
1527          * the search will return none and nothing will be done anymore.
1528          */
1529         mlx5_flow_stop_default(dev);
1530         mlx5_traffic_disable(dev);
1531         /*
1532          * If all the flows are already flushed in the device stop stage,
1533          * then this will return directly without any action.
1534          */
1535         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1536         mlx5_action_handle_flush(dev);
1537         mlx5_flow_meter_flush(dev, NULL);
1538         /* Prevent crashes when queues are still in use. */
1539         dev->rx_pkt_burst = removed_rx_burst;
1540         dev->tx_pkt_burst = removed_tx_burst;
1541         rte_wmb();
1542         /* Disable datapath on secondary process. */
1543         mlx5_mp_os_req_stop_rxtx(dev);
1544         /* Free the eCPRI flex parser resource. */
1545         mlx5_flex_parser_ecpri_release(dev);
1546         if (priv->rxqs != NULL) {
1547                 /* XXX race condition if mlx5_rx_burst() is still running. */
1548                 rte_delay_us_sleep(1000);
1549                 for (i = 0; (i != priv->rxqs_n); ++i)
1550                         mlx5_rxq_release(dev, i);
1551                 priv->rxqs_n = 0;
1552                 priv->rxqs = NULL;
1553         }
1554         if (priv->txqs != NULL) {
1555                 /* XXX race condition if mlx5_tx_burst() is still running. */
1556                 rte_delay_us_sleep(1000);
1557                 for (i = 0; (i != priv->txqs_n); ++i)
1558                         mlx5_txq_release(dev, i);
1559                 priv->txqs_n = 0;
1560                 priv->txqs = NULL;
1561         }
1562         mlx5_proc_priv_uninit(dev);
1563         if (priv->q_counters) {
1564                 mlx5_devx_cmd_destroy(priv->q_counters);
1565                 priv->q_counters = NULL;
1566         }
1567         if (priv->drop_queue.hrxq)
1568                 mlx5_drop_action_destroy(dev);
1569         if (priv->mreg_cp_tbl)
1570                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1571         mlx5_mprq_free_mp(dev);
1572         if (priv->sh->ct_mng)
1573                 mlx5_flow_aso_ct_mng_close(priv->sh);
1574         mlx5_os_free_shared_dr(priv);
1575         if (priv->rss_conf.rss_key != NULL)
1576                 mlx5_free(priv->rss_conf.rss_key);
1577         if (priv->reta_idx != NULL)
1578                 mlx5_free(priv->reta_idx);
1579         if (priv->config.vf)
1580                 mlx5_os_mac_addr_flush(dev);
1581         if (priv->nl_socket_route >= 0)
1582                 close(priv->nl_socket_route);
1583         if (priv->nl_socket_rdma >= 0)
1584                 close(priv->nl_socket_rdma);
1585         if (priv->vmwa_context)
1586                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1587         ret = mlx5_hrxq_verify(dev);
1588         if (ret)
1589                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1590                         dev->data->port_id);
1591         ret = mlx5_ind_table_obj_verify(dev);
1592         if (ret)
1593                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1594                         dev->data->port_id);
1595         ret = mlx5_rxq_obj_verify(dev);
1596         if (ret)
1597                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1598                         dev->data->port_id);
1599         ret = mlx5_rxq_verify(dev);
1600         if (ret)
1601                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1602                         dev->data->port_id);
1603         ret = mlx5_txq_obj_verify(dev);
1604         if (ret)
1605                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1606                         dev->data->port_id);
1607         ret = mlx5_txq_verify(dev);
1608         if (ret)
1609                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1610                         dev->data->port_id);
1611         ret = mlx5_flow_verify(dev);
1612         if (ret)
1613                 DRV_LOG(WARNING, "port %u some flows still remain",
1614                         dev->data->port_id);
1615         if (priv->hrxqs)
1616                 mlx5_list_destroy(priv->hrxqs);
1617         /*
1618          * Free the shared context in last turn, because the cleanup
1619          * routines above may use some shared fields, like
1620          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1621          * ifindex if Netlink fails.
1622          */
1623         mlx5_free_shared_dev_ctx(priv->sh);
1624         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1625                 unsigned int c = 0;
1626                 uint16_t port_id;
1627
1628                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1629                         struct mlx5_priv *opriv =
1630                                 rte_eth_devices[port_id].data->dev_private;
1631
1632                         if (!opriv ||
1633                             opriv->domain_id != priv->domain_id ||
1634                             &rte_eth_devices[port_id] == dev)
1635                                 continue;
1636                         ++c;
1637                         break;
1638                 }
1639                 if (!c)
1640                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1641         }
1642         memset(priv, 0, sizeof(*priv));
1643         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1644         /*
1645          * Reset mac_addrs to NULL such that it is not freed as part of
1646          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1647          * it is freed when dev_private is freed.
1648          */
1649         dev->data->mac_addrs = NULL;
1650         return 0;
1651 }
1652
1653 const struct eth_dev_ops mlx5_dev_ops = {
1654         .dev_configure = mlx5_dev_configure,
1655         .dev_start = mlx5_dev_start,
1656         .dev_stop = mlx5_dev_stop,
1657         .dev_set_link_down = mlx5_set_link_down,
1658         .dev_set_link_up = mlx5_set_link_up,
1659         .dev_close = mlx5_dev_close,
1660         .promiscuous_enable = mlx5_promiscuous_enable,
1661         .promiscuous_disable = mlx5_promiscuous_disable,
1662         .allmulticast_enable = mlx5_allmulticast_enable,
1663         .allmulticast_disable = mlx5_allmulticast_disable,
1664         .link_update = mlx5_link_update,
1665         .stats_get = mlx5_stats_get,
1666         .stats_reset = mlx5_stats_reset,
1667         .xstats_get = mlx5_xstats_get,
1668         .xstats_reset = mlx5_xstats_reset,
1669         .xstats_get_names = mlx5_xstats_get_names,
1670         .fw_version_get = mlx5_fw_version_get,
1671         .dev_infos_get = mlx5_dev_infos_get,
1672         .representor_info_get = mlx5_representor_info_get,
1673         .read_clock = mlx5_txpp_read_clock,
1674         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1675         .vlan_filter_set = mlx5_vlan_filter_set,
1676         .rx_queue_setup = mlx5_rx_queue_setup,
1677         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1678         .tx_queue_setup = mlx5_tx_queue_setup,
1679         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1680         .rx_queue_release = mlx5_rx_queue_release,
1681         .tx_queue_release = mlx5_tx_queue_release,
1682         .rx_queue_start = mlx5_rx_queue_start,
1683         .rx_queue_stop = mlx5_rx_queue_stop,
1684         .tx_queue_start = mlx5_tx_queue_start,
1685         .tx_queue_stop = mlx5_tx_queue_stop,
1686         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1687         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1688         .mac_addr_remove = mlx5_mac_addr_remove,
1689         .mac_addr_add = mlx5_mac_addr_add,
1690         .mac_addr_set = mlx5_mac_addr_set,
1691         .set_mc_addr_list = mlx5_set_mc_addr_list,
1692         .mtu_set = mlx5_dev_set_mtu,
1693         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1694         .vlan_offload_set = mlx5_vlan_offload_set,
1695         .reta_update = mlx5_dev_rss_reta_update,
1696         .reta_query = mlx5_dev_rss_reta_query,
1697         .rss_hash_update = mlx5_rss_hash_update,
1698         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1699         .flow_ops_get = mlx5_flow_ops_get,
1700         .rxq_info_get = mlx5_rxq_info_get,
1701         .txq_info_get = mlx5_txq_info_get,
1702         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1703         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1704         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1705         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1706         .is_removed = mlx5_is_removed,
1707         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1708         .get_module_info = mlx5_get_module_info,
1709         .get_module_eeprom = mlx5_get_module_eeprom,
1710         .hairpin_cap_get = mlx5_hairpin_cap_get,
1711         .mtr_ops_get = mlx5_flow_meter_ops_get,
1712         .hairpin_bind = mlx5_hairpin_bind,
1713         .hairpin_unbind = mlx5_hairpin_unbind,
1714         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1715         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1716         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1717         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1718         .get_monitor_addr = mlx5_get_monitor_addr,
1719 };
1720
1721 /* Available operations from secondary process. */
1722 const struct eth_dev_ops mlx5_dev_sec_ops = {
1723         .stats_get = mlx5_stats_get,
1724         .stats_reset = mlx5_stats_reset,
1725         .xstats_get = mlx5_xstats_get,
1726         .xstats_reset = mlx5_xstats_reset,
1727         .xstats_get_names = mlx5_xstats_get_names,
1728         .fw_version_get = mlx5_fw_version_get,
1729         .dev_infos_get = mlx5_dev_infos_get,
1730         .read_clock = mlx5_txpp_read_clock,
1731         .rx_queue_start = mlx5_rx_queue_start,
1732         .rx_queue_stop = mlx5_rx_queue_stop,
1733         .tx_queue_start = mlx5_tx_queue_start,
1734         .tx_queue_stop = mlx5_tx_queue_stop,
1735         .rxq_info_get = mlx5_rxq_info_get,
1736         .txq_info_get = mlx5_txq_info_get,
1737         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1738         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1739         .get_module_info = mlx5_get_module_info,
1740         .get_module_eeprom = mlx5_get_module_eeprom,
1741 };
1742
1743 /* Available operations in flow isolated mode. */
1744 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1745         .dev_configure = mlx5_dev_configure,
1746         .dev_start = mlx5_dev_start,
1747         .dev_stop = mlx5_dev_stop,
1748         .dev_set_link_down = mlx5_set_link_down,
1749         .dev_set_link_up = mlx5_set_link_up,
1750         .dev_close = mlx5_dev_close,
1751         .promiscuous_enable = mlx5_promiscuous_enable,
1752         .promiscuous_disable = mlx5_promiscuous_disable,
1753         .allmulticast_enable = mlx5_allmulticast_enable,
1754         .allmulticast_disable = mlx5_allmulticast_disable,
1755         .link_update = mlx5_link_update,
1756         .stats_get = mlx5_stats_get,
1757         .stats_reset = mlx5_stats_reset,
1758         .xstats_get = mlx5_xstats_get,
1759         .xstats_reset = mlx5_xstats_reset,
1760         .xstats_get_names = mlx5_xstats_get_names,
1761         .fw_version_get = mlx5_fw_version_get,
1762         .dev_infos_get = mlx5_dev_infos_get,
1763         .read_clock = mlx5_txpp_read_clock,
1764         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1765         .vlan_filter_set = mlx5_vlan_filter_set,
1766         .rx_queue_setup = mlx5_rx_queue_setup,
1767         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1768         .tx_queue_setup = mlx5_tx_queue_setup,
1769         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1770         .rx_queue_release = mlx5_rx_queue_release,
1771         .tx_queue_release = mlx5_tx_queue_release,
1772         .rx_queue_start = mlx5_rx_queue_start,
1773         .rx_queue_stop = mlx5_rx_queue_stop,
1774         .tx_queue_start = mlx5_tx_queue_start,
1775         .tx_queue_stop = mlx5_tx_queue_stop,
1776         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1777         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1778         .mac_addr_remove = mlx5_mac_addr_remove,
1779         .mac_addr_add = mlx5_mac_addr_add,
1780         .mac_addr_set = mlx5_mac_addr_set,
1781         .set_mc_addr_list = mlx5_set_mc_addr_list,
1782         .mtu_set = mlx5_dev_set_mtu,
1783         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1784         .vlan_offload_set = mlx5_vlan_offload_set,
1785         .flow_ops_get = mlx5_flow_ops_get,
1786         .rxq_info_get = mlx5_rxq_info_get,
1787         .txq_info_get = mlx5_txq_info_get,
1788         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1789         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1790         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1791         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1792         .is_removed = mlx5_is_removed,
1793         .get_module_info = mlx5_get_module_info,
1794         .get_module_eeprom = mlx5_get_module_eeprom,
1795         .hairpin_cap_get = mlx5_hairpin_cap_get,
1796         .mtr_ops_get = mlx5_flow_meter_ops_get,
1797         .hairpin_bind = mlx5_hairpin_bind,
1798         .hairpin_unbind = mlx5_hairpin_unbind,
1799         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1800         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1801         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1802         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1803         .get_monitor_addr = mlx5_get_monitor_addr,
1804 };
1805
1806 /**
1807  * Verify and store value for device argument.
1808  *
1809  * @param[in] key
1810  *   Key argument to verify.
1811  * @param[in] val
1812  *   Value associated with key.
1813  * @param opaque
1814  *   User data.
1815  *
1816  * @return
1817  *   0 on success, a negative errno value otherwise and rte_errno is set.
1818  */
1819 static int
1820 mlx5_args_check(const char *key, const char *val, void *opaque)
1821 {
1822         struct mlx5_dev_config *config = opaque;
1823         unsigned long mod;
1824         signed long tmp;
1825
1826         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1827         if (!strcmp(MLX5_REPRESENTOR, key))
1828                 return 0;
1829         errno = 0;
1830         tmp = strtol(val, NULL, 0);
1831         if (errno) {
1832                 rte_errno = errno;
1833                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1834                 return -rte_errno;
1835         }
1836         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1837                 /* Negative values are acceptable for some keys only. */
1838                 rte_errno = EINVAL;
1839                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1840                 return -rte_errno;
1841         }
1842         mod = tmp >= 0 ? tmp : -tmp;
1843         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1844                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1845                         DRV_LOG(ERR, "invalid CQE compression "
1846                                      "format parameter");
1847                         rte_errno = EINVAL;
1848                         return -rte_errno;
1849                 }
1850                 config->cqe_comp = !!tmp;
1851                 config->cqe_comp_fmt = tmp;
1852         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1853                 config->hw_padding = !!tmp;
1854         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1855                 config->mprq.enabled = !!tmp;
1856         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1857                 config->mprq.stride_num_n = tmp;
1858         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1859                 config->mprq.stride_size_n = tmp;
1860         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1861                 config->mprq.max_memcpy_len = tmp;
1862         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1863                 config->mprq.min_rxqs_num = tmp;
1864         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1865                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1866                                  " converted to txq_inline_max", key);
1867                 config->txq_inline_max = tmp;
1868         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1869                 config->txq_inline_max = tmp;
1870         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1871                 config->txq_inline_min = tmp;
1872         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1873                 config->txq_inline_mpw = tmp;
1874         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1875                 config->txqs_inline = tmp;
1876         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1877                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1878         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1879                 config->mps = !!tmp;
1880         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1881                 if (tmp != MLX5_TXDB_CACHED &&
1882                     tmp != MLX5_TXDB_NCACHED &&
1883                     tmp != MLX5_TXDB_HEURISTIC) {
1884                         DRV_LOG(ERR, "invalid Tx doorbell "
1885                                      "mapping parameter");
1886                         rte_errno = EINVAL;
1887                         return -rte_errno;
1888                 }
1889                 config->dbnc = tmp;
1890         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1891                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1892         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1893                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1894                                  " converted to txq_inline_mpw", key);
1895                 config->txq_inline_mpw = tmp;
1896         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1897                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1898         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1899                 if (!mod) {
1900                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1901                         rte_errno = EINVAL;
1902                         return -rte_errno;
1903                 }
1904                 config->tx_pp = tmp;
1905         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1906                 config->tx_skew = tmp;
1907         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1908                 config->rx_vec_en = !!tmp;
1909         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1910                 config->l3_vxlan_en = !!tmp;
1911         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1912                 config->vf_nl_en = !!tmp;
1913         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1914                 config->dv_esw_en = !!tmp;
1915         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1916                 config->dv_flow_en = !!tmp;
1917         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1918                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1919                     tmp != MLX5_XMETA_MODE_META16 &&
1920                     tmp != MLX5_XMETA_MODE_META32 &&
1921                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1922                         DRV_LOG(ERR, "invalid extensive "
1923                                      "metadata parameter");
1924                         rte_errno = EINVAL;
1925                         return -rte_errno;
1926                 }
1927                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1928                         config->dv_xmeta_en = tmp;
1929                 else
1930                         config->dv_miss_info = 1;
1931         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1932                 config->lacp_by_user = !!tmp;
1933         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1934                 config->mr_ext_memseg_en = !!tmp;
1935         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1936                 config->max_dump_files_num = tmp;
1937         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1938                 config->lro.timeout = tmp;
1939         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1940                 DRV_LOG(DEBUG, "class argument is %s.", val);
1941         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1942                 config->log_hp_size = tmp;
1943         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1944                 if (tmp != MLX5_RCM_NONE &&
1945                     tmp != MLX5_RCM_LIGHT &&
1946                     tmp != MLX5_RCM_AGGR) {
1947                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1948                         rte_errno = EINVAL;
1949                         return -rte_errno;
1950                 }
1951                 config->reclaim_mode = tmp;
1952         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1953                 config->sys_mem_en = !!tmp;
1954         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1955                 config->decap_en = !!tmp;
1956         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1957                 config->allow_duplicate_pattern = !!tmp;
1958         } else {
1959                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1960                 rte_errno = EINVAL;
1961                 return -rte_errno;
1962         }
1963         return 0;
1964 }
1965
1966 /**
1967  * Parse device parameters.
1968  *
1969  * @param config
1970  *   Pointer to device configuration structure.
1971  * @param devargs
1972  *   Device arguments structure.
1973  *
1974  * @return
1975  *   0 on success, a negative errno value otherwise and rte_errno is set.
1976  */
1977 int
1978 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1979 {
1980         const char **params = (const char *[]){
1981                 MLX5_RXQ_CQE_COMP_EN,
1982                 MLX5_RXQ_PKT_PAD_EN,
1983                 MLX5_RX_MPRQ_EN,
1984                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1985                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1986                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1987                 MLX5_RXQS_MIN_MPRQ,
1988                 MLX5_TXQ_INLINE,
1989                 MLX5_TXQ_INLINE_MIN,
1990                 MLX5_TXQ_INLINE_MAX,
1991                 MLX5_TXQ_INLINE_MPW,
1992                 MLX5_TXQS_MIN_INLINE,
1993                 MLX5_TXQS_MAX_VEC,
1994                 MLX5_TXQ_MPW_EN,
1995                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1996                 MLX5_TXQ_MAX_INLINE_LEN,
1997                 MLX5_TX_DB_NC,
1998                 MLX5_TX_PP,
1999                 MLX5_TX_SKEW,
2000                 MLX5_TX_VEC_EN,
2001                 MLX5_RX_VEC_EN,
2002                 MLX5_L3_VXLAN_EN,
2003                 MLX5_VF_NL_EN,
2004                 MLX5_DV_ESW_EN,
2005                 MLX5_DV_FLOW_EN,
2006                 MLX5_DV_XMETA_EN,
2007                 MLX5_LACP_BY_USER,
2008                 MLX5_MR_EXT_MEMSEG_EN,
2009                 MLX5_REPRESENTOR,
2010                 MLX5_MAX_DUMP_FILES_NUM,
2011                 MLX5_LRO_TIMEOUT_USEC,
2012                 RTE_DEVARGS_KEY_CLASS,
2013                 MLX5_HP_BUF_SIZE,
2014                 MLX5_RECLAIM_MEM,
2015                 MLX5_SYS_MEM_EN,
2016                 MLX5_DECAP_EN,
2017                 MLX5_ALLOW_DUPLICATE_PATTERN,
2018                 NULL,
2019         };
2020         struct rte_kvargs *kvlist;
2021         int ret = 0;
2022         int i;
2023
2024         if (devargs == NULL)
2025                 return 0;
2026         /* Following UGLY cast is done to pass checkpatch. */
2027         kvlist = rte_kvargs_parse(devargs->args, params);
2028         if (kvlist == NULL) {
2029                 rte_errno = EINVAL;
2030                 return -rte_errno;
2031         }
2032         /* Process parameters. */
2033         for (i = 0; (params[i] != NULL); ++i) {
2034                 if (rte_kvargs_count(kvlist, params[i])) {
2035                         ret = rte_kvargs_process(kvlist, params[i],
2036                                                  mlx5_args_check, config);
2037                         if (ret) {
2038                                 rte_errno = EINVAL;
2039                                 rte_kvargs_free(kvlist);
2040                                 return -rte_errno;
2041                         }
2042                 }
2043         }
2044         rte_kvargs_free(kvlist);
2045         return 0;
2046 }
2047
2048 /**
2049  * Configures the minimal amount of data to inline into WQE
2050  * while sending packets.
2051  *
2052  * - the txq_inline_min has the maximal priority, if this
2053  *   key is specified in devargs
2054  * - if DevX is enabled the inline mode is queried from the
2055  *   device (HCA attributes and NIC vport context if needed).
2056  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2057  *   and none (0 bytes) for other NICs
2058  *
2059  * @param spawn
2060  *   Verbs device parameters (name, port, switch_info) to spawn.
2061  * @param config
2062  *   Device configuration parameters.
2063  */
2064 void
2065 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2066                     struct mlx5_dev_config *config)
2067 {
2068         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2069                 /* Application defines size of inlined data explicitly. */
2070                 switch (spawn->pci_dev->id.device_id) {
2071                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2072                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2073                         if (config->txq_inline_min <
2074                                        (int)MLX5_INLINE_HSIZE_L2) {
2075                                 DRV_LOG(DEBUG,
2076                                         "txq_inline_mix aligned to minimal"
2077                                         " ConnectX-4 required value %d",
2078                                         (int)MLX5_INLINE_HSIZE_L2);
2079                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2080                         }
2081                         break;
2082                 }
2083                 goto exit;
2084         }
2085         if (config->hca_attr.eth_net_offloads) {
2086                 /* We have DevX enabled, inline mode queried successfully. */
2087                 switch (config->hca_attr.wqe_inline_mode) {
2088                 case MLX5_CAP_INLINE_MODE_L2:
2089                         /* outer L2 header must be inlined. */
2090                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2091                         goto exit;
2092                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2093                         /* No inline data are required by NIC. */
2094                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2095                         config->hw_vlan_insert =
2096                                 config->hca_attr.wqe_vlan_insert;
2097                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2098                         goto exit;
2099                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2100                         /* inline mode is defined by NIC vport context. */
2101                         if (!config->hca_attr.eth_virt)
2102                                 break;
2103                         switch (config->hca_attr.vport_inline_mode) {
2104                         case MLX5_INLINE_MODE_NONE:
2105                                 config->txq_inline_min =
2106                                         MLX5_INLINE_HSIZE_NONE;
2107                                 goto exit;
2108                         case MLX5_INLINE_MODE_L2:
2109                                 config->txq_inline_min =
2110                                         MLX5_INLINE_HSIZE_L2;
2111                                 goto exit;
2112                         case MLX5_INLINE_MODE_IP:
2113                                 config->txq_inline_min =
2114                                         MLX5_INLINE_HSIZE_L3;
2115                                 goto exit;
2116                         case MLX5_INLINE_MODE_TCP_UDP:
2117                                 config->txq_inline_min =
2118                                         MLX5_INLINE_HSIZE_L4;
2119                                 goto exit;
2120                         case MLX5_INLINE_MODE_INNER_L2:
2121                                 config->txq_inline_min =
2122                                         MLX5_INLINE_HSIZE_INNER_L2;
2123                                 goto exit;
2124                         case MLX5_INLINE_MODE_INNER_IP:
2125                                 config->txq_inline_min =
2126                                         MLX5_INLINE_HSIZE_INNER_L3;
2127                                 goto exit;
2128                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2129                                 config->txq_inline_min =
2130                                         MLX5_INLINE_HSIZE_INNER_L4;
2131                                 goto exit;
2132                         }
2133                 }
2134         }
2135         /*
2136          * We get here if we are unable to deduce
2137          * inline data size with DevX. Try PCI ID
2138          * to determine old NICs.
2139          */
2140         switch (spawn->pci_dev->id.device_id) {
2141         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2142         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2143         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2144         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2145                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2146                 config->hw_vlan_insert = 0;
2147                 break;
2148         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2149         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2150         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2151         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2152                 /*
2153                  * These NICs support VLAN insertion from WQE and
2154                  * report the wqe_vlan_insert flag. But there is the bug
2155                  * and PFC control may be broken, so disable feature.
2156                  */
2157                 config->hw_vlan_insert = 0;
2158                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2159                 break;
2160         default:
2161                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2162                 break;
2163         }
2164 exit:
2165         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2166 }
2167
2168 /**
2169  * Configures the metadata mask fields in the shared context.
2170  *
2171  * @param [in] dev
2172  *   Pointer to Ethernet device.
2173  */
2174 void
2175 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2176 {
2177         struct mlx5_priv *priv = dev->data->dev_private;
2178         struct mlx5_dev_ctx_shared *sh = priv->sh;
2179         uint32_t meta, mark, reg_c0;
2180
2181         reg_c0 = ~priv->vport_meta_mask;
2182         switch (priv->config.dv_xmeta_en) {
2183         case MLX5_XMETA_MODE_LEGACY:
2184                 meta = UINT32_MAX;
2185                 mark = MLX5_FLOW_MARK_MASK;
2186                 break;
2187         case MLX5_XMETA_MODE_META16:
2188                 meta = reg_c0 >> rte_bsf32(reg_c0);
2189                 mark = MLX5_FLOW_MARK_MASK;
2190                 break;
2191         case MLX5_XMETA_MODE_META32:
2192                 meta = UINT32_MAX;
2193                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2194                 break;
2195         default:
2196                 meta = 0;
2197                 mark = 0;
2198                 MLX5_ASSERT(false);
2199                 break;
2200         }
2201         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2202                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2203                                  sh->dv_mark_mask, mark);
2204         else
2205                 sh->dv_mark_mask = mark;
2206         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2207                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2208                                  sh->dv_meta_mask, meta);
2209         else
2210                 sh->dv_meta_mask = meta;
2211         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2212                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2213                                  sh->dv_meta_mask, reg_c0);
2214         else
2215                 sh->dv_regc0_mask = reg_c0;
2216         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2217         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2218         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2219         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2220 }
2221
2222 int
2223 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2224 {
2225         static const char *const dynf_names[] = {
2226                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2227                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2228                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2229         };
2230         unsigned int i;
2231
2232         if (n < RTE_DIM(dynf_names))
2233                 return -ENOMEM;
2234         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2235                 if (names[i] == NULL)
2236                         return -EINVAL;
2237                 strcpy(names[i], dynf_names[i]);
2238         }
2239         return RTE_DIM(dynf_names);
2240 }
2241
2242 /**
2243  * Comparison callback to sort device data.
2244  *
2245  * This is meant to be used with qsort().
2246  *
2247  * @param a[in]
2248  *   Pointer to pointer to first data object.
2249  * @param b[in]
2250  *   Pointer to pointer to second data object.
2251  *
2252  * @return
2253  *   0 if both objects are equal, less than 0 if the first argument is less
2254  *   than the second, greater than 0 otherwise.
2255  */
2256 int
2257 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2258                               struct mlx5_dev_config *config)
2259 {
2260         struct mlx5_dev_ctx_shared *sh = priv->sh;
2261         struct mlx5_dev_config *sh_conf = NULL;
2262         uint16_t port_id;
2263
2264         MLX5_ASSERT(sh);
2265         /* Nothing to compare for the single/first device. */
2266         if (sh->refcnt == 1)
2267                 return 0;
2268         /* Find the device with shared context. */
2269         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2270                 struct mlx5_priv *opriv =
2271                         rte_eth_devices[port_id].data->dev_private;
2272
2273                 if (opriv && opriv != priv && opriv->sh == sh) {
2274                         sh_conf = &opriv->config;
2275                         break;
2276                 }
2277         }
2278         if (!sh_conf)
2279                 return 0;
2280         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2281                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2282                              " for shared %s context", sh->ibdev_name);
2283                 rte_errno = EINVAL;
2284                 return rte_errno;
2285         }
2286         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2287                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2288                              " for shared %s context", sh->ibdev_name);
2289                 rte_errno = EINVAL;
2290                 return rte_errno;
2291         }
2292         return 0;
2293 }
2294
2295 /**
2296  * Look for the ethernet device belonging to mlx5 driver.
2297  *
2298  * @param[in] port_id
2299  *   port_id to start looking for device.
2300  * @param[in] pci_dev
2301  *   Pointer to the hint PCI device. When device is being probed
2302  *   the its siblings (master and preceding representors might
2303  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2304  *   is not completed yet, for this case match on hint PCI
2305  *   device may be used to detect sibling device.
2306  *
2307  * @return
2308  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2309  */
2310 uint16_t
2311 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2312 {
2313         while (port_id < RTE_MAX_ETHPORTS) {
2314                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2315
2316                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2317                     dev->device &&
2318                     (dev->device == &pci_dev->device ||
2319                      (dev->device->driver &&
2320                      dev->device->driver->name &&
2321                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2322                         break;
2323                 port_id++;
2324         }
2325         if (port_id >= RTE_MAX_ETHPORTS)
2326                 return RTE_MAX_ETHPORTS;
2327         return port_id;
2328 }
2329
2330 /**
2331  * DPDK callback to remove a PCI device.
2332  *
2333  * This function removes all Ethernet devices belong to a given PCI device.
2334  *
2335  * @param[in] pci_dev
2336  *   Pointer to the PCI device.
2337  *
2338  * @return
2339  *   0 on success, the function cannot fail.
2340  */
2341 static int
2342 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2343 {
2344         uint16_t port_id;
2345         int ret = 0;
2346
2347         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2348                 /*
2349                  * mlx5_dev_close() is not registered to secondary process,
2350                  * call the close function explicitly for secondary process.
2351                  */
2352                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2353                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2354                 else
2355                         ret |= rte_eth_dev_close(port_id);
2356         }
2357         return ret == 0 ? 0 : -EIO;
2358 }
2359
2360 static const struct rte_pci_id mlx5_pci_id_map[] = {
2361         {
2362                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2363                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2364         },
2365         {
2366                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2367                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2368         },
2369         {
2370                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2371                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2372         },
2373         {
2374                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2375                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2376         },
2377         {
2378                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2379                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2380         },
2381         {
2382                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2383                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2384         },
2385         {
2386                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2387                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2388         },
2389         {
2390                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2391                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2392         },
2393         {
2394                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2395                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2396         },
2397         {
2398                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2399                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2400         },
2401         {
2402                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2403                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2404         },
2405         {
2406                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2407                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2408         },
2409         {
2410                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2411                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2412         },
2413         {
2414                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2415                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2416         },
2417         {
2418                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2419                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2420         },
2421         {
2422                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2424         },
2425         {
2426                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2428         },
2429         {
2430                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2431                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2432         },
2433         {
2434                 .vendor_id = 0
2435         }
2436 };
2437
2438 static struct mlx5_pci_driver mlx5_driver = {
2439         .driver_class = MLX5_CLASS_NET,
2440         .pci_driver = {
2441                 .driver = {
2442                         .name = MLX5_PCI_DRIVER_NAME,
2443                 },
2444                 .id_table = mlx5_pci_id_map,
2445                 .probe = mlx5_os_pci_probe,
2446                 .remove = mlx5_pci_remove,
2447                 .dma_map = mlx5_dma_map,
2448                 .dma_unmap = mlx5_dma_unmap,
2449                 .drv_flags = PCI_DRV_FLAGS,
2450         },
2451 };
2452
2453 /* Initialize driver log type. */
2454 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2455
2456 /**
2457  * Driver initialization routine.
2458  */
2459 RTE_INIT(rte_mlx5_pmd_init)
2460 {
2461         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2462         mlx5_common_init();
2463         /* Build the static tables for Verbs conversion. */
2464         mlx5_set_ptype_table();
2465         mlx5_set_cksum_table();
2466         mlx5_set_swp_types_table();
2467         if (mlx5_glue)
2468                 mlx5_pci_driver_register(&mlx5_driver);
2469 }
2470
2471 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2472 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2473 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");