1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_os.h>
42 #include <mlx5_common_mp.h>
43 #include <mlx5_malloc.h>
45 #include "mlx5_defs.h"
47 #include "mlx5_utils.h"
48 #include "mlx5_rxtx.h"
49 #include "mlx5_autoconf.h"
51 #include "mlx5_flow.h"
52 #include "rte_pmd_mlx5.h"
54 /* Device parameter to enable RX completion queue compression. */
55 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
57 /* Device parameter to enable RX completion entry padding to 128B. */
58 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
60 /* Device parameter to enable padding Rx packet to cacheline size. */
61 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
63 /* Device parameter to enable Multi-Packet Rx queue. */
64 #define MLX5_RX_MPRQ_EN "mprq_en"
66 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
67 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
69 /* Device parameter to configure log 2 of the stride size for MPRQ. */
70 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
72 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
73 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
75 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
76 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
78 /* Device parameter to configure inline send. Deprecated, ignored.*/
79 #define MLX5_TXQ_INLINE "txq_inline"
81 /* Device parameter to limit packet size to inline with ordinary SEND. */
82 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
84 /* Device parameter to configure minimal data size to inline. */
85 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
87 /* Device parameter to limit packet size to inline with Enhanced MPW. */
88 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
91 * Device parameter to configure the number of TX queues threshold for
92 * enabling inline send.
94 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
97 * Device parameter to configure the number of TX queues threshold for
98 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
100 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
102 /* Device parameter to enable multi-packet send WQEs. */
103 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
106 * Device parameter to force doorbell register mapping
107 * to non-cahed region eliminating the extra write memory barrier.
109 #define MLX5_TX_DB_NC "tx_db_nc"
112 * Device parameter to include 2 dsegs in the title WQEBB.
113 * Deprecated, ignored.
115 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
118 * Device parameter to limit the size of inlining packet.
119 * Deprecated, ignored.
121 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
124 * Device parameter to enable Tx scheduling on timestamps
125 * and specify the packet pacing granularity in nanoseconds.
127 #define MLX5_TX_PP "tx_pp"
130 * Device parameter to specify skew in nanoseconds on Tx datapath,
131 * it represents the time between SQ start WQE processing and
132 * appearing actual packet data on the wire.
134 #define MLX5_TX_SKEW "tx_skew"
137 * Device parameter to enable hardware Tx vector.
138 * Deprecated, ignored (no vectorized Tx routines anymore).
140 #define MLX5_TX_VEC_EN "tx_vec_en"
142 /* Device parameter to enable hardware Rx vector. */
143 #define MLX5_RX_VEC_EN "rx_vec_en"
145 /* Allow L3 VXLAN flow creation. */
146 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
148 /* Activate DV E-Switch flow steering. */
149 #define MLX5_DV_ESW_EN "dv_esw_en"
151 /* Activate DV flow steering. */
152 #define MLX5_DV_FLOW_EN "dv_flow_en"
154 /* Enable extensive flow metadata support. */
155 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
157 /* Device parameter to let the user manage the lacp traffic of bonded device */
158 #define MLX5_LACP_BY_USER "lacp_by_user"
160 /* Activate Netlink support in VF mode. */
161 #define MLX5_VF_NL_EN "vf_nl_en"
163 /* Enable extending memsegs when creating a MR. */
164 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
166 /* Select port representors to instantiate. */
167 #define MLX5_REPRESENTOR "representor"
169 /* Device parameter to configure the maximum number of dump files per queue. */
170 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
172 /* Configure timeout of LRO session (in microseconds). */
173 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
176 * Device parameter to configure the total data buffer size for a single
177 * hairpin queue (logarithm value).
179 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
181 /* Flow memory reclaim mode. */
182 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
184 /* The default memory allocator used in PMD. */
185 #define MLX5_SYS_MEM_EN "sys_mem_en"
187 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
189 /* Shared memory between primary and secondary processes. */
190 struct mlx5_shared_data *mlx5_shared_data;
192 /* Spinlock for mlx5_shared_data allocation. */
193 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
195 /* Process local data for secondary processes. */
196 static struct mlx5_local_data mlx5_local_data;
198 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
199 LIST_HEAD_INITIALIZER();
200 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
202 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
203 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
205 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
211 .malloc = mlx5_malloc,
213 .type = "mlx5_encap_decap_ipool",
216 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
222 .malloc = mlx5_malloc,
224 .type = "mlx5_push_vlan_ipool",
227 .size = sizeof(struct mlx5_flow_dv_tag_resource),
233 .malloc = mlx5_malloc,
235 .type = "mlx5_tag_ipool",
238 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
244 .malloc = mlx5_malloc,
246 .type = "mlx5_port_id_ipool",
249 .size = sizeof(struct mlx5_flow_tbl_data_entry),
255 .malloc = mlx5_malloc,
257 .type = "mlx5_jump_ipool",
261 .size = sizeof(struct mlx5_flow_meter),
267 .malloc = mlx5_malloc,
269 .type = "mlx5_meter_ipool",
272 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
278 .malloc = mlx5_malloc,
280 .type = "mlx5_mcp_ipool",
283 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
289 .malloc = mlx5_malloc,
291 .type = "mlx5_hrxq_ipool",
295 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
296 * It set in run time according to PCI function configuration.
304 .malloc = mlx5_malloc,
306 .type = "mlx5_flow_handle_ipool",
309 .size = sizeof(struct rte_flow),
313 .malloc = mlx5_malloc,
315 .type = "rte_flow_ipool",
320 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
321 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
323 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
326 * Allocate ID pool structure.
329 * The maximum id can be allocated from the pool.
332 * Pointer to pool object, NULL value otherwise.
334 struct mlx5_flow_id_pool *
335 mlx5_flow_id_pool_alloc(uint32_t max_id)
337 struct mlx5_flow_id_pool *pool;
340 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
341 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
343 DRV_LOG(ERR, "can't allocate id pool");
347 mem = mlx5_malloc(MLX5_MEM_ZERO,
348 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
349 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
351 DRV_LOG(ERR, "can't allocate mem for id pool");
355 pool->free_arr = mem;
356 pool->curr = pool->free_arr;
357 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
358 pool->base_index = 0;
359 pool->max_id = max_id;
367 * Release ID pool structure.
370 * Pointer to flow id pool object to free.
373 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
375 mlx5_free(pool->free_arr);
383 * Pointer to flow id pool.
388 * 0 on success, error value otherwise.
391 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
393 if (pool->curr == pool->free_arr) {
394 if (pool->base_index == pool->max_id) {
396 DRV_LOG(ERR, "no free id");
399 *id = ++pool->base_index;
402 *id = *(--pool->curr);
410 * Pointer to flow id pool.
415 * 0 on success, error value otherwise.
418 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
424 if (pool->curr == pool->last) {
425 size = pool->curr - pool->free_arr;
426 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
427 MLX5_ASSERT(size2 > size);
428 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
431 DRV_LOG(ERR, "can't allocate mem for id pool");
435 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
436 mlx5_free(pool->free_arr);
437 pool->free_arr = mem;
438 pool->curr = pool->free_arr + size;
439 pool->last = pool->free_arr + size2;
447 * Initialize the shared aging list information per port.
450 * Pointer to mlx5_dev_ctx_shared object.
453 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
456 struct mlx5_age_info *age_info;
458 for (i = 0; i < sh->max_port; i++) {
459 age_info = &sh->port[i].age_info;
461 TAILQ_INIT(&age_info->aged_counters);
462 rte_spinlock_init(&age_info->aged_sl);
463 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
468 * Initialize the counters management structure.
471 * Pointer to mlx5_dev_ctx_shared object to free
474 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
478 memset(&sh->cmng, 0, sizeof(sh->cmng));
479 TAILQ_INIT(&sh->cmng.flow_counters);
480 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
481 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
482 sh->cmng.ccont[i].max_id = -1;
483 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
484 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
485 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
486 TAILQ_INIT(&sh->cmng.ccont[i].counters);
487 rte_spinlock_init(&sh->cmng.ccont[i].csl);
492 * Destroy all the resources allocated for a counter memory management.
495 * Pointer to the memory management structure.
498 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
500 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
502 LIST_REMOVE(mng, next);
503 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
504 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
509 * Close and release all the resources of the counters management.
512 * Pointer to mlx5_dev_ctx_shared object to free.
515 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
517 struct mlx5_counter_stats_mem_mng *mng;
524 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
525 if (rte_errno != EINPROGRESS)
529 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
530 struct mlx5_flow_counter_pool *pool;
531 uint32_t batch = !!(i > 1);
533 if (!sh->cmng.ccont[i].pools)
535 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
537 if (batch && pool->min_dcs)
538 claim_zero(mlx5_devx_cmd_destroy
540 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
541 if (MLX5_POOL_GET_CNT(pool, j)->action)
543 (mlx5_glue->destroy_flow_action
546 if (!batch && MLX5_GET_POOL_CNT_EXT
548 claim_zero(mlx5_devx_cmd_destroy
549 (MLX5_GET_POOL_CNT_EXT
552 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
554 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
556 mlx5_free(sh->cmng.ccont[i].pools);
558 mng = LIST_FIRST(&sh->cmng.mem_mngs);
560 mlx5_flow_destroy_counter_stat_mem_mng(mng);
561 mng = LIST_FIRST(&sh->cmng.mem_mngs);
563 memset(&sh->cmng, 0, sizeof(sh->cmng));
567 * Initialize the flow resources' indexed mempool.
570 * Pointer to mlx5_dev_ctx_shared object.
572 * Pointer to user dev config.
575 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
576 const struct mlx5_dev_config *config)
579 struct mlx5_indexed_pool_config cfg;
581 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
582 cfg = mlx5_ipool_cfg[i];
587 * Set MLX5_IPOOL_MLX5_FLOW ipool size
588 * according to PCI function flow configuration.
590 case MLX5_IPOOL_MLX5_FLOW:
591 cfg.size = config->dv_flow_en ?
592 sizeof(struct mlx5_flow_handle) :
593 MLX5_FLOW_HANDLE_VERBS_SIZE;
596 if (config->reclaim_mode)
597 cfg.release_mem_en = 1;
598 sh->ipool[i] = mlx5_ipool_create(&cfg);
603 * Release the flow resources' indexed mempool.
606 * Pointer to mlx5_dev_ctx_shared object.
609 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
613 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
614 mlx5_ipool_destroy(sh->ipool[i]);
618 * Check if dynamic flex parser for eCPRI already exists.
621 * Pointer to Ethernet device structure.
624 * true on exists, false on not.
627 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
629 struct mlx5_priv *priv = dev->data->dev_private;
630 struct mlx5_flex_parser_profiles *prf =
631 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
637 * Allocation of a flex parser for eCPRI. Once created, this parser related
638 * resources will be held until the device is closed.
641 * Pointer to Ethernet device structure.
644 * 0 on success, a negative errno value otherwise and rte_errno is set.
647 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
649 struct mlx5_priv *priv = dev->data->dev_private;
650 struct mlx5_flex_parser_profiles *prf =
651 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
652 struct mlx5_devx_graph_node_attr node = {
653 .modify_field_select = 0,
658 if (!priv->config.hca_attr.parse_graph_flex_node) {
659 DRV_LOG(ERR, "Dynamic flex parser is not supported "
660 "for device %s.", priv->dev_data->name);
663 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
664 /* 8 bytes now: 4B common header + 4B message body header. */
665 node.header_length_base_value = 0x8;
666 /* After MAC layer: Ether / VLAN. */
667 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
668 /* Type of compared condition should be 0xAEFE in the L2 layer. */
669 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
670 /* Sample #0: type in common header. */
671 node.sample[0].flow_match_sample_en = 1;
673 node.sample[0].flow_match_sample_offset_mode = 0x0;
674 /* Only the 2nd byte will be used. */
675 node.sample[0].flow_match_sample_field_base_offset = 0x0;
676 /* Sample #1: message payload. */
677 node.sample[1].flow_match_sample_en = 1;
679 node.sample[1].flow_match_sample_offset_mode = 0x0;
681 * Only the first two bytes will be used right now, and its offset will
682 * start after the common header that with the length of a DW(u32).
684 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
685 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
687 DRV_LOG(ERR, "Failed to create flex parser node object.");
688 return (rte_errno == 0) ? -ENODEV : -rte_errno;
691 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
693 DRV_LOG(ERR, "Failed to query sample IDs.");
694 return (rte_errno == 0) ? -ENODEV : -rte_errno;
696 prf->offset[0] = 0x0;
697 prf->offset[1] = sizeof(uint32_t);
698 prf->ids[0] = ids[0];
699 prf->ids[1] = ids[1];
704 * Destroy the flex parser node, including the parser itself, input / output
705 * arcs and DW samples. Resources could be reused then.
708 * Pointer to Ethernet device structure.
711 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
713 struct mlx5_priv *priv = dev->data->dev_private;
714 struct mlx5_flex_parser_profiles *prf =
715 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
718 mlx5_devx_cmd_destroy(prf->obj);
723 * Allocate shared device context. If there is multiport device the
724 * master and representors will share this context, if there is single
725 * port dedicated device, the context will be used by only given
726 * port due to unification.
728 * Routine first searches the context for the specified device name,
729 * if found the shared context assumed and reference counter is incremented.
730 * If no context found the new one is created and initialized with specified
731 * device context and parameters.
734 * Pointer to the device attributes (name, port, etc).
736 * Pointer to device configuration structure.
739 * Pointer to mlx5_dev_ctx_shared object on success,
740 * otherwise NULL and rte_errno is set.
742 struct mlx5_dev_ctx_shared *
743 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
744 const struct mlx5_dev_config *config)
746 struct mlx5_dev_ctx_shared *sh;
749 struct mlx5_devx_tis_attr tis_attr = { 0 };
752 /* Secondary process should not create the shared context. */
753 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
754 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
755 /* Search for IB context by device name. */
756 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
757 if (!strcmp(sh->ibdev_name,
758 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
763 /* No device found, we have to create new shared context. */
764 MLX5_ASSERT(spawn->max_port);
765 sh = rte_zmalloc("ethdev shared ib context",
766 sizeof(struct mlx5_dev_ctx_shared) +
768 sizeof(struct mlx5_dev_shared_port),
769 RTE_CACHE_LINE_SIZE);
771 DRV_LOG(ERR, "shared context allocation failure");
775 err = mlx5_os_open_device(spawn, config, sh);
778 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
780 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
784 sh->max_port = spawn->max_port;
785 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
786 sizeof(sh->ibdev_name) - 1);
787 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
788 sizeof(sh->ibdev_path) - 1);
790 * Setting port_id to max unallowed value means
791 * there is no interrupt subhandler installed for
792 * the given port index i.
794 for (i = 0; i < sh->max_port; i++) {
795 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
796 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
798 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
799 if (sh->pd == NULL) {
800 DRV_LOG(ERR, "PD allocation failure");
805 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
807 DRV_LOG(ERR, "Fail to extract pdn from PD");
810 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
812 DRV_LOG(ERR, "TD allocation failure");
816 tis_attr.transport_domain = sh->td->id;
817 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
819 DRV_LOG(ERR, "TIS allocation failure");
823 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
825 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
830 sh->flow_id_pool = mlx5_flow_id_pool_alloc
831 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
832 if (!sh->flow_id_pool) {
833 DRV_LOG(ERR, "can't create flow id pool");
838 /* Initialize UAR access locks for 32bit implementations. */
839 rte_spinlock_init(&sh->uar_lock_cq);
840 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
841 rte_spinlock_init(&sh->uar_lock[i]);
844 * Once the device is added to the list of memory event
845 * callback, its global MR cache table cannot be expanded
846 * on the fly because of deadlock. If it overflows, lookup
847 * should be done by searching MR list linearly, which is slow.
849 * At this point the device is not added to the memory
850 * event list yet, context is just being created.
852 err = mlx5_mr_btree_init(&sh->share_cache.cache,
853 MLX5_MR_BTREE_CACHE_N * 2,
854 spawn->pci_dev->device.numa_node);
859 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
860 &sh->share_cache.dereg_mr_cb);
861 mlx5_os_dev_shared_handler_install(sh);
862 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
863 if (!sh->cnt_id_tbl) {
867 mlx5_flow_aging_init(sh);
868 mlx5_flow_counters_mng_init(sh);
869 mlx5_flow_ipool_create(sh, config);
870 /* Add device to memory callback list. */
871 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
872 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
874 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
875 /* Add context to the global device list. */
876 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
878 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
881 pthread_mutex_destroy(&sh->txpp.mutex);
882 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
884 if (sh->cnt_id_tbl) {
885 mlx5_l3t_destroy(sh->cnt_id_tbl);
886 sh->cnt_id_tbl = NULL;
889 mlx5_glue->devx_free_uar(sh->tx_uar);
893 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
895 claim_zero(mlx5_devx_cmd_destroy(sh->td));
897 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
899 claim_zero(mlx5_glue->close_device(sh->ctx));
900 if (sh->flow_id_pool)
901 mlx5_flow_id_pool_release(sh->flow_id_pool);
903 MLX5_ASSERT(err > 0);
909 * Free shared IB device context. Decrement counter and if zero free
910 * all allocated resources and close handles.
913 * Pointer to mlx5_dev_ctx_shared object to free
916 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
918 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
919 #ifdef RTE_LIBRTE_MLX5_DEBUG
920 /* Check the object presence in the list. */
921 struct mlx5_dev_ctx_shared *lctx;
923 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
928 DRV_LOG(ERR, "Freeing non-existing shared IB context");
933 MLX5_ASSERT(sh->refcnt);
934 /* Secondary process should not free the shared context. */
935 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
938 /* Remove from memory callback device list. */
939 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
940 LIST_REMOVE(sh, mem_event_cb);
941 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
942 /* Release created Memory Regions. */
943 mlx5_mr_release_cache(&sh->share_cache);
944 /* Remove context from the global device list. */
945 LIST_REMOVE(sh, next);
947 * Ensure there is no async event handler installed.
948 * Only primary process handles async device events.
950 mlx5_flow_counters_mng_close(sh);
951 mlx5_flow_ipool_destroy(sh);
952 mlx5_os_dev_shared_handler_uninstall(sh);
953 if (sh->cnt_id_tbl) {
954 mlx5_l3t_destroy(sh->cnt_id_tbl);
955 sh->cnt_id_tbl = NULL;
958 mlx5_glue->devx_free_uar(sh->tx_uar);
962 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
964 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
966 claim_zero(mlx5_devx_cmd_destroy(sh->td));
968 claim_zero(mlx5_glue->close_device(sh->ctx));
969 if (sh->flow_id_pool)
970 mlx5_flow_id_pool_release(sh->flow_id_pool);
971 pthread_mutex_destroy(&sh->txpp.mutex);
974 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
978 * Destroy table hash list and all the root entries per domain.
981 * Pointer to the private device data structure.
984 mlx5_free_table_hash_list(struct mlx5_priv *priv)
986 struct mlx5_dev_ctx_shared *sh = priv->sh;
987 struct mlx5_flow_tbl_data_entry *tbl_data;
988 union mlx5_flow_tbl_key table_key = {
996 struct mlx5_hlist_entry *pos;
1000 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1002 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1004 MLX5_ASSERT(tbl_data);
1005 mlx5_hlist_remove(sh->flow_tbls, pos);
1006 mlx5_free(tbl_data);
1008 table_key.direction = 1;
1009 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1011 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1013 MLX5_ASSERT(tbl_data);
1014 mlx5_hlist_remove(sh->flow_tbls, pos);
1015 mlx5_free(tbl_data);
1017 table_key.direction = 0;
1018 table_key.domain = 1;
1019 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1021 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1023 MLX5_ASSERT(tbl_data);
1024 mlx5_hlist_remove(sh->flow_tbls, pos);
1025 mlx5_free(tbl_data);
1027 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1031 * Initialize flow table hash list and create the root tables entry
1035 * Pointer to the private device data structure.
1038 * Zero on success, positive error code otherwise.
1041 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1043 struct mlx5_dev_ctx_shared *sh = priv->sh;
1044 char s[MLX5_HLIST_NAMESIZE];
1048 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1049 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1050 if (!sh->flow_tbls) {
1051 DRV_LOG(ERR, "flow tables with hash creation failed.");
1055 #ifndef HAVE_MLX5DV_DR
1057 * In case we have not DR support, the zero tables should be created
1058 * because DV expect to see them even if they cannot be created by
1061 union mlx5_flow_tbl_key table_key = {
1069 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1070 sizeof(*tbl_data), 0,
1077 tbl_data->entry.key = table_key.v64;
1078 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1081 rte_atomic32_init(&tbl_data->tbl.refcnt);
1082 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1083 table_key.direction = 1;
1084 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1090 tbl_data->entry.key = table_key.v64;
1091 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1094 rte_atomic32_init(&tbl_data->tbl.refcnt);
1095 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1096 table_key.direction = 0;
1097 table_key.domain = 1;
1098 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1104 tbl_data->entry.key = table_key.v64;
1105 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1108 rte_atomic32_init(&tbl_data->tbl.refcnt);
1109 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1112 mlx5_free_table_hash_list(priv);
1113 #endif /* HAVE_MLX5DV_DR */
1118 * Initialize shared data between primary and secondary process.
1120 * A memzone is reserved by primary process and secondary processes attach to
1124 * 0 on success, a negative errno value otherwise and rte_errno is set.
1127 mlx5_init_shared_data(void)
1129 const struct rte_memzone *mz;
1132 rte_spinlock_lock(&mlx5_shared_data_lock);
1133 if (mlx5_shared_data == NULL) {
1134 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1135 /* Allocate shared memory. */
1136 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1137 sizeof(*mlx5_shared_data),
1141 "Cannot allocate mlx5 shared data");
1145 mlx5_shared_data = mz->addr;
1146 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1147 rte_spinlock_init(&mlx5_shared_data->lock);
1149 /* Lookup allocated shared memory. */
1150 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1153 "Cannot attach mlx5 shared data");
1157 mlx5_shared_data = mz->addr;
1158 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1162 rte_spinlock_unlock(&mlx5_shared_data_lock);
1167 * Retrieve integer value from environment variable.
1170 * Environment variable name.
1173 * Integer value, 0 if the variable is not set.
1176 mlx5_getenv_int(const char *name)
1178 const char *val = getenv(name);
1186 * DPDK callback to add udp tunnel port
1189 * A pointer to eth_dev
1190 * @param[in] udp_tunnel
1191 * A pointer to udp tunnel
1194 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1197 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1198 struct rte_eth_udp_tunnel *udp_tunnel)
1200 MLX5_ASSERT(udp_tunnel != NULL);
1201 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1202 udp_tunnel->udp_port == 4789)
1204 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1205 udp_tunnel->udp_port == 4790)
1211 * Initialize process private data structure.
1214 * Pointer to Ethernet device structure.
1217 * 0 on success, a negative errno value otherwise and rte_errno is set.
1220 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1222 struct mlx5_priv *priv = dev->data->dev_private;
1223 struct mlx5_proc_priv *ppriv;
1227 * UAR register table follows the process private structure. BlueFlame
1228 * registers for Tx queues are stored in the table.
1231 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1232 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1233 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1238 ppriv->uar_table_sz = ppriv_size;
1239 dev->process_private = ppriv;
1244 * Un-initialize process private data structure.
1247 * Pointer to Ethernet device structure.
1250 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1252 if (!dev->process_private)
1254 rte_free(dev->process_private);
1255 dev->process_private = NULL;
1259 * DPDK callback to close the device.
1261 * Destroy all queues and objects, free memory.
1264 * Pointer to Ethernet device structure.
1267 mlx5_dev_close(struct rte_eth_dev *dev)
1269 struct mlx5_priv *priv = dev->data->dev_private;
1273 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1274 /* Check if process_private released. */
1275 if (!dev->process_private)
1277 mlx5_tx_uar_uninit_secondary(dev);
1278 mlx5_proc_priv_uninit(dev);
1279 rte_eth_dev_release_port(dev);
1284 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1286 ((priv->sh->ctx != NULL) ?
1287 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1289 * If default mreg copy action is removed at the stop stage,
1290 * the search will return none and nothing will be done anymore.
1292 mlx5_flow_stop_default(dev);
1293 mlx5_traffic_disable(dev);
1295 * If all the flows are already flushed in the device stop stage,
1296 * then this will return directly without any action.
1298 mlx5_flow_list_flush(dev, &priv->flows, true);
1299 mlx5_flow_meter_flush(dev, NULL);
1300 /* Free the intermediate buffers for flow creation. */
1301 mlx5_flow_free_intermediate(dev);
1302 /* Prevent crashes when queues are still in use. */
1303 dev->rx_pkt_burst = removed_rx_burst;
1304 dev->tx_pkt_burst = removed_tx_burst;
1306 /* Disable datapath on secondary process. */
1307 mlx5_mp_req_stop_rxtx(dev);
1308 /* Free the eCPRI flex parser resource. */
1309 mlx5_flex_parser_ecpri_release(dev);
1310 if (priv->rxqs != NULL) {
1311 /* XXX race condition if mlx5_rx_burst() is still running. */
1313 for (i = 0; (i != priv->rxqs_n); ++i)
1314 mlx5_rxq_release(dev, i);
1318 if (priv->txqs != NULL) {
1319 /* XXX race condition if mlx5_tx_burst() is still running. */
1321 for (i = 0; (i != priv->txqs_n); ++i)
1322 mlx5_txq_release(dev, i);
1326 mlx5_proc_priv_uninit(dev);
1327 if (priv->mreg_cp_tbl)
1328 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1329 mlx5_mprq_free_mp(dev);
1330 mlx5_os_free_shared_dr(priv);
1331 if (priv->rss_conf.rss_key != NULL)
1332 mlx5_free(priv->rss_conf.rss_key);
1333 if (priv->reta_idx != NULL)
1334 mlx5_free(priv->reta_idx);
1335 if (priv->config.vf)
1336 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1337 dev->data->mac_addrs,
1338 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1339 if (priv->nl_socket_route >= 0)
1340 close(priv->nl_socket_route);
1341 if (priv->nl_socket_rdma >= 0)
1342 close(priv->nl_socket_rdma);
1343 if (priv->vmwa_context)
1344 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1345 ret = mlx5_hrxq_verify(dev);
1347 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1348 dev->data->port_id);
1349 ret = mlx5_ind_table_obj_verify(dev);
1351 DRV_LOG(WARNING, "port %u some indirection table still remain",
1352 dev->data->port_id);
1353 ret = mlx5_rxq_obj_verify(dev);
1355 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1356 dev->data->port_id);
1357 ret = mlx5_rxq_verify(dev);
1359 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1360 dev->data->port_id);
1361 ret = mlx5_txq_obj_verify(dev);
1363 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1364 dev->data->port_id);
1365 ret = mlx5_txq_verify(dev);
1367 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1368 dev->data->port_id);
1369 ret = mlx5_flow_verify(dev);
1371 DRV_LOG(WARNING, "port %u some flows still remain",
1372 dev->data->port_id);
1374 * Free the shared context in last turn, because the cleanup
1375 * routines above may use some shared fields, like
1376 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1377 * ifindex if Netlink fails.
1379 mlx5_free_shared_dev_ctx(priv->sh);
1380 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1384 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1385 struct mlx5_priv *opriv =
1386 rte_eth_devices[port_id].data->dev_private;
1389 opriv->domain_id != priv->domain_id ||
1390 &rte_eth_devices[port_id] == dev)
1396 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1398 memset(priv, 0, sizeof(*priv));
1399 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1401 * Reset mac_addrs to NULL such that it is not freed as part of
1402 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1403 * it is freed when dev_private is freed.
1405 dev->data->mac_addrs = NULL;
1409 * Verify and store value for device argument.
1412 * Key argument to verify.
1414 * Value associated with key.
1419 * 0 on success, a negative errno value otherwise and rte_errno is set.
1422 mlx5_args_check(const char *key, const char *val, void *opaque)
1424 struct mlx5_dev_config *config = opaque;
1428 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1429 if (!strcmp(MLX5_REPRESENTOR, key))
1432 tmp = strtol(val, NULL, 0);
1435 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1438 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1439 /* Negative values are acceptable for some keys only. */
1441 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1444 mod = tmp >= 0 ? tmp : -tmp;
1445 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1446 config->cqe_comp = !!tmp;
1447 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1448 config->cqe_pad = !!tmp;
1449 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1450 config->hw_padding = !!tmp;
1451 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1452 config->mprq.enabled = !!tmp;
1453 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1454 config->mprq.stride_num_n = tmp;
1455 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1456 config->mprq.stride_size_n = tmp;
1457 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1458 config->mprq.max_memcpy_len = tmp;
1459 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1460 config->mprq.min_rxqs_num = tmp;
1461 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1462 DRV_LOG(WARNING, "%s: deprecated parameter,"
1463 " converted to txq_inline_max", key);
1464 config->txq_inline_max = tmp;
1465 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1466 config->txq_inline_max = tmp;
1467 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1468 config->txq_inline_min = tmp;
1469 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1470 config->txq_inline_mpw = tmp;
1471 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1472 config->txqs_inline = tmp;
1473 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1474 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1475 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1476 config->mps = !!tmp;
1477 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1478 if (tmp != MLX5_TXDB_CACHED &&
1479 tmp != MLX5_TXDB_NCACHED &&
1480 tmp != MLX5_TXDB_HEURISTIC) {
1481 DRV_LOG(ERR, "invalid Tx doorbell "
1482 "mapping parameter");
1487 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1488 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1489 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1490 DRV_LOG(WARNING, "%s: deprecated parameter,"
1491 " converted to txq_inline_mpw", key);
1492 config->txq_inline_mpw = tmp;
1493 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1494 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1495 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1497 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1501 config->tx_pp = tmp;
1502 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1503 config->tx_skew = tmp;
1504 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1505 config->rx_vec_en = !!tmp;
1506 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1507 config->l3_vxlan_en = !!tmp;
1508 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1509 config->vf_nl_en = !!tmp;
1510 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1511 config->dv_esw_en = !!tmp;
1512 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1513 config->dv_flow_en = !!tmp;
1514 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1515 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1516 tmp != MLX5_XMETA_MODE_META16 &&
1517 tmp != MLX5_XMETA_MODE_META32) {
1518 DRV_LOG(ERR, "invalid extensive "
1519 "metadata parameter");
1523 config->dv_xmeta_en = tmp;
1524 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1525 config->lacp_by_user = !!tmp;
1526 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1527 config->mr_ext_memseg_en = !!tmp;
1528 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1529 config->max_dump_files_num = tmp;
1530 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1531 config->lro.timeout = tmp;
1532 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1533 DRV_LOG(DEBUG, "class argument is %s.", val);
1534 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1535 config->log_hp_size = tmp;
1536 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1537 if (tmp != MLX5_RCM_NONE &&
1538 tmp != MLX5_RCM_LIGHT &&
1539 tmp != MLX5_RCM_AGGR) {
1540 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1544 config->reclaim_mode = tmp;
1545 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1546 config->sys_mem_en = !!tmp;
1548 DRV_LOG(WARNING, "%s: unknown parameter", key);
1556 * Parse device parameters.
1559 * Pointer to device configuration structure.
1561 * Device arguments structure.
1564 * 0 on success, a negative errno value otherwise and rte_errno is set.
1567 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1569 const char **params = (const char *[]){
1570 MLX5_RXQ_CQE_COMP_EN,
1571 MLX5_RXQ_CQE_PAD_EN,
1572 MLX5_RXQ_PKT_PAD_EN,
1574 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1575 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1576 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1579 MLX5_TXQ_INLINE_MIN,
1580 MLX5_TXQ_INLINE_MAX,
1581 MLX5_TXQ_INLINE_MPW,
1582 MLX5_TXQS_MIN_INLINE,
1585 MLX5_TXQ_MPW_HDR_DSEG_EN,
1586 MLX5_TXQ_MAX_INLINE_LEN,
1598 MLX5_MR_EXT_MEMSEG_EN,
1600 MLX5_MAX_DUMP_FILES_NUM,
1601 MLX5_LRO_TIMEOUT_USEC,
1602 MLX5_CLASS_ARG_NAME,
1608 struct rte_kvargs *kvlist;
1612 if (devargs == NULL)
1614 /* Following UGLY cast is done to pass checkpatch. */
1615 kvlist = rte_kvargs_parse(devargs->args, params);
1616 if (kvlist == NULL) {
1620 /* Process parameters. */
1621 for (i = 0; (params[i] != NULL); ++i) {
1622 if (rte_kvargs_count(kvlist, params[i])) {
1623 ret = rte_kvargs_process(kvlist, params[i],
1624 mlx5_args_check, config);
1627 rte_kvargs_free(kvlist);
1632 rte_kvargs_free(kvlist);
1637 * PMD global initialization.
1639 * Independent from individual device, this function initializes global
1640 * per-PMD data structures distinguishing primary and secondary processes.
1641 * Hence, each initialization is called once per a process.
1644 * 0 on success, a negative errno value otherwise and rte_errno is set.
1647 mlx5_init_once(void)
1649 struct mlx5_shared_data *sd;
1650 struct mlx5_local_data *ld = &mlx5_local_data;
1653 if (mlx5_init_shared_data())
1655 sd = mlx5_shared_data;
1657 rte_spinlock_lock(&sd->lock);
1658 switch (rte_eal_process_type()) {
1659 case RTE_PROC_PRIMARY:
1662 LIST_INIT(&sd->mem_event_cb_list);
1663 rte_rwlock_init(&sd->mem_event_rwlock);
1664 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1665 mlx5_mr_mem_event_cb, NULL);
1666 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1667 mlx5_mp_primary_handle);
1670 sd->init_done = true;
1672 case RTE_PROC_SECONDARY:
1675 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1676 mlx5_mp_secondary_handle);
1679 ++sd->secondary_cnt;
1680 ld->init_done = true;
1686 rte_spinlock_unlock(&sd->lock);
1691 * Configures the minimal amount of data to inline into WQE
1692 * while sending packets.
1694 * - the txq_inline_min has the maximal priority, if this
1695 * key is specified in devargs
1696 * - if DevX is enabled the inline mode is queried from the
1697 * device (HCA attributes and NIC vport context if needed).
1698 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1699 * and none (0 bytes) for other NICs
1702 * Verbs device parameters (name, port, switch_info) to spawn.
1704 * Device configuration parameters.
1707 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1708 struct mlx5_dev_config *config)
1710 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1711 /* Application defines size of inlined data explicitly. */
1712 switch (spawn->pci_dev->id.device_id) {
1713 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1714 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1715 if (config->txq_inline_min <
1716 (int)MLX5_INLINE_HSIZE_L2) {
1718 "txq_inline_mix aligned to minimal"
1719 " ConnectX-4 required value %d",
1720 (int)MLX5_INLINE_HSIZE_L2);
1721 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1727 if (config->hca_attr.eth_net_offloads) {
1728 /* We have DevX enabled, inline mode queried successfully. */
1729 switch (config->hca_attr.wqe_inline_mode) {
1730 case MLX5_CAP_INLINE_MODE_L2:
1731 /* outer L2 header must be inlined. */
1732 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1734 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1735 /* No inline data are required by NIC. */
1736 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1737 config->hw_vlan_insert =
1738 config->hca_attr.wqe_vlan_insert;
1739 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1741 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1742 /* inline mode is defined by NIC vport context. */
1743 if (!config->hca_attr.eth_virt)
1745 switch (config->hca_attr.vport_inline_mode) {
1746 case MLX5_INLINE_MODE_NONE:
1747 config->txq_inline_min =
1748 MLX5_INLINE_HSIZE_NONE;
1750 case MLX5_INLINE_MODE_L2:
1751 config->txq_inline_min =
1752 MLX5_INLINE_HSIZE_L2;
1754 case MLX5_INLINE_MODE_IP:
1755 config->txq_inline_min =
1756 MLX5_INLINE_HSIZE_L3;
1758 case MLX5_INLINE_MODE_TCP_UDP:
1759 config->txq_inline_min =
1760 MLX5_INLINE_HSIZE_L4;
1762 case MLX5_INLINE_MODE_INNER_L2:
1763 config->txq_inline_min =
1764 MLX5_INLINE_HSIZE_INNER_L2;
1766 case MLX5_INLINE_MODE_INNER_IP:
1767 config->txq_inline_min =
1768 MLX5_INLINE_HSIZE_INNER_L3;
1770 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1771 config->txq_inline_min =
1772 MLX5_INLINE_HSIZE_INNER_L4;
1778 * We get here if we are unable to deduce
1779 * inline data size with DevX. Try PCI ID
1780 * to determine old NICs.
1782 switch (spawn->pci_dev->id.device_id) {
1783 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1784 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1785 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1786 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1787 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1788 config->hw_vlan_insert = 0;
1790 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1791 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1792 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1793 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1795 * These NICs support VLAN insertion from WQE and
1796 * report the wqe_vlan_insert flag. But there is the bug
1797 * and PFC control may be broken, so disable feature.
1799 config->hw_vlan_insert = 0;
1800 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1803 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1807 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1811 * Configures the metadata mask fields in the shared context.
1814 * Pointer to Ethernet device.
1817 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1819 struct mlx5_priv *priv = dev->data->dev_private;
1820 struct mlx5_dev_ctx_shared *sh = priv->sh;
1821 uint32_t meta, mark, reg_c0;
1823 reg_c0 = ~priv->vport_meta_mask;
1824 switch (priv->config.dv_xmeta_en) {
1825 case MLX5_XMETA_MODE_LEGACY:
1827 mark = MLX5_FLOW_MARK_MASK;
1829 case MLX5_XMETA_MODE_META16:
1830 meta = reg_c0 >> rte_bsf32(reg_c0);
1831 mark = MLX5_FLOW_MARK_MASK;
1833 case MLX5_XMETA_MODE_META32:
1835 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1843 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1844 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1845 sh->dv_mark_mask, mark);
1847 sh->dv_mark_mask = mark;
1848 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1849 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1850 sh->dv_meta_mask, meta);
1852 sh->dv_meta_mask = meta;
1853 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1854 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1855 sh->dv_meta_mask, reg_c0);
1857 sh->dv_regc0_mask = reg_c0;
1858 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1859 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1860 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1861 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1865 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1867 static const char *const dynf_names[] = {
1868 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1869 RTE_MBUF_DYNFLAG_METADATA_NAME,
1870 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1874 if (n < RTE_DIM(dynf_names))
1876 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1877 if (names[i] == NULL)
1879 strcpy(names[i], dynf_names[i]);
1881 return RTE_DIM(dynf_names);
1885 * Comparison callback to sort device data.
1887 * This is meant to be used with qsort().
1890 * Pointer to pointer to first data object.
1892 * Pointer to pointer to second data object.
1895 * 0 if both objects are equal, less than 0 if the first argument is less
1896 * than the second, greater than 0 otherwise.
1899 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1900 struct mlx5_dev_config *config)
1902 struct mlx5_dev_ctx_shared *sh = priv->sh;
1903 struct mlx5_dev_config *sh_conf = NULL;
1907 /* Nothing to compare for the single/first device. */
1908 if (sh->refcnt == 1)
1910 /* Find the device with shared context. */
1911 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1912 struct mlx5_priv *opriv =
1913 rte_eth_devices[port_id].data->dev_private;
1915 if (opriv && opriv != priv && opriv->sh == sh) {
1916 sh_conf = &opriv->config;
1922 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1923 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1924 " for shared %s context", sh->ibdev_name);
1928 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1929 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1930 " for shared %s context", sh->ibdev_name);
1938 * Look for the ethernet device belonging to mlx5 driver.
1940 * @param[in] port_id
1941 * port_id to start looking for device.
1942 * @param[in] pci_dev
1943 * Pointer to the hint PCI device. When device is being probed
1944 * the its siblings (master and preceding representors might
1945 * not have assigned driver yet (because the mlx5_os_pci_probe()
1946 * is not completed yet, for this case match on hint PCI
1947 * device may be used to detect sibling device.
1950 * port_id of found device, RTE_MAX_ETHPORT if not found.
1953 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1955 while (port_id < RTE_MAX_ETHPORTS) {
1956 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1958 if (dev->state != RTE_ETH_DEV_UNUSED &&
1960 (dev->device == &pci_dev->device ||
1961 (dev->device->driver &&
1962 dev->device->driver->name &&
1963 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1967 if (port_id >= RTE_MAX_ETHPORTS)
1968 return RTE_MAX_ETHPORTS;
1973 * DPDK callback to remove a PCI device.
1975 * This function removes all Ethernet devices belong to a given PCI device.
1977 * @param[in] pci_dev
1978 * Pointer to the PCI device.
1981 * 0 on success, the function cannot fail.
1984 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1988 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1990 * mlx5_dev_close() is not registered to secondary process,
1991 * call the close function explicitly for secondary process.
1993 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1994 mlx5_dev_close(&rte_eth_devices[port_id]);
1996 rte_eth_dev_close(port_id);
2001 static const struct rte_pci_id mlx5_pci_id_map[] = {
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2015 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2019 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2023 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2056 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2059 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2060 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2063 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2064 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2071 struct rte_pci_driver mlx5_driver = {
2073 .name = MLX5_DRIVER_NAME
2075 .id_table = mlx5_pci_id_map,
2076 .probe = mlx5_os_pci_probe,
2077 .remove = mlx5_pci_remove,
2078 .dma_map = mlx5_dma_map,
2079 .dma_unmap = mlx5_dma_unmap,
2080 .drv_flags = PCI_DRV_FLAGS,
2083 /* Initialize driver log type. */
2084 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2087 * Driver initialization routine.
2089 RTE_INIT(rte_mlx5_pmd_init)
2091 /* Build the static tables for Verbs conversion. */
2092 mlx5_set_ptype_table();
2093 mlx5_set_cksum_table();
2094 mlx5_set_swp_types_table();
2096 rte_pci_register(&mlx5_driver);
2099 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2100 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2101 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");