1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
16 #include <rte_malloc.h>
17 #include <rte_ethdev_driver.h>
18 #include <rte_ethdev_pci.h>
20 #include <rte_bus_pci.h>
21 #include <rte_common.h>
22 #include <rte_kvargs.h>
23 #include <rte_rwlock.h>
24 #include <rte_spinlock.h>
25 #include <rte_string_fns.h>
26 #include <rte_alarm.h>
28 #include <mlx5_glue.h>
29 #include <mlx5_devx_cmds.h>
30 #include <mlx5_common.h>
31 #include <mlx5_common_os.h>
32 #include <mlx5_common_mp.h>
33 #include <mlx5_malloc.h>
35 #include "mlx5_defs.h"
37 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
41 #include "mlx5_flow.h"
42 #include "rte_pmd_mlx5.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to enable RX completion entry padding to 128B. */
48 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
50 /* Device parameter to enable padding Rx packet to cacheline size. */
51 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
53 /* Device parameter to enable Multi-Packet Rx queue. */
54 #define MLX5_RX_MPRQ_EN "mprq_en"
56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
59 /* Device parameter to configure log 2 of the stride size for MPRQ. */
60 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
62 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
63 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
65 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
66 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
68 /* Device parameter to configure inline send. Deprecated, ignored.*/
69 #define MLX5_TXQ_INLINE "txq_inline"
71 /* Device parameter to limit packet size to inline with ordinary SEND. */
72 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
74 /* Device parameter to configure minimal data size to inline. */
75 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
77 /* Device parameter to limit packet size to inline with Enhanced MPW. */
78 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
81 * Device parameter to configure the number of TX queues threshold for
82 * enabling inline send.
84 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
87 * Device parameter to configure the number of TX queues threshold for
88 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
90 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
92 /* Device parameter to enable multi-packet send WQEs. */
93 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
96 * Device parameter to force doorbell register mapping
97 * to non-cahed region eliminating the extra write memory barrier.
99 #define MLX5_TX_DB_NC "tx_db_nc"
102 * Device parameter to include 2 dsegs in the title WQEBB.
103 * Deprecated, ignored.
105 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
108 * Device parameter to limit the size of inlining packet.
109 * Deprecated, ignored.
111 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
114 * Device parameter to enable Tx scheduling on timestamps
115 * and specify the packet pacing granularity in nanoseconds.
117 #define MLX5_TX_PP "tx_pp"
120 * Device parameter to specify skew in nanoseconds on Tx datapath,
121 * it represents the time between SQ start WQE processing and
122 * appearing actual packet data on the wire.
124 #define MLX5_TX_SKEW "tx_skew"
127 * Device parameter to enable hardware Tx vector.
128 * Deprecated, ignored (no vectorized Tx routines anymore).
130 #define MLX5_TX_VEC_EN "tx_vec_en"
132 /* Device parameter to enable hardware Rx vector. */
133 #define MLX5_RX_VEC_EN "rx_vec_en"
135 /* Allow L3 VXLAN flow creation. */
136 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
138 /* Activate DV E-Switch flow steering. */
139 #define MLX5_DV_ESW_EN "dv_esw_en"
141 /* Activate DV flow steering. */
142 #define MLX5_DV_FLOW_EN "dv_flow_en"
144 /* Enable extensive flow metadata support. */
145 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
147 /* Device parameter to let the user manage the lacp traffic of bonded device */
148 #define MLX5_LACP_BY_USER "lacp_by_user"
150 /* Activate Netlink support in VF mode. */
151 #define MLX5_VF_NL_EN "vf_nl_en"
153 /* Enable extending memsegs when creating a MR. */
154 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
156 /* Select port representors to instantiate. */
157 #define MLX5_REPRESENTOR "representor"
159 /* Device parameter to configure the maximum number of dump files per queue. */
160 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
162 /* Configure timeout of LRO session (in microseconds). */
163 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
166 * Device parameter to configure the total data buffer size for a single
167 * hairpin queue (logarithm value).
169 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
171 /* Flow memory reclaim mode. */
172 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
174 /* The default memory allocator used in PMD. */
175 #define MLX5_SYS_MEM_EN "sys_mem_en"
176 /* Decap will be used or not. */
177 #define MLX5_DECAP_EN "decap_en"
179 /* Shared memory between primary and secondary processes. */
180 struct mlx5_shared_data *mlx5_shared_data;
182 /** Driver-specific log messages type. */
185 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
186 LIST_HEAD_INITIALIZER();
187 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
189 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
190 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
192 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
198 .malloc = mlx5_malloc,
200 .type = "mlx5_encap_decap_ipool",
203 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
209 .malloc = mlx5_malloc,
211 .type = "mlx5_push_vlan_ipool",
214 .size = sizeof(struct mlx5_flow_dv_tag_resource),
220 .malloc = mlx5_malloc,
222 .type = "mlx5_tag_ipool",
225 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
231 .malloc = mlx5_malloc,
233 .type = "mlx5_port_id_ipool",
236 .size = sizeof(struct mlx5_flow_tbl_data_entry),
242 .malloc = mlx5_malloc,
244 .type = "mlx5_jump_ipool",
248 .size = sizeof(struct mlx5_flow_meter),
254 .malloc = mlx5_malloc,
256 .type = "mlx5_meter_ipool",
259 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
265 .malloc = mlx5_malloc,
267 .type = "mlx5_mcp_ipool",
270 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
276 .malloc = mlx5_malloc,
278 .type = "mlx5_hrxq_ipool",
282 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
283 * It set in run time according to PCI function configuration.
291 .malloc = mlx5_malloc,
293 .type = "mlx5_flow_handle_ipool",
296 .size = sizeof(struct rte_flow),
300 .malloc = mlx5_malloc,
302 .type = "rte_flow_ipool",
307 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
308 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
310 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
313 * Allocate ID pool structure.
316 * The maximum id can be allocated from the pool.
319 * Pointer to pool object, NULL value otherwise.
321 struct mlx5_flow_id_pool *
322 mlx5_flow_id_pool_alloc(uint32_t max_id)
324 struct mlx5_flow_id_pool *pool;
327 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
328 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
330 DRV_LOG(ERR, "can't allocate id pool");
334 mem = mlx5_malloc(MLX5_MEM_ZERO,
335 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
336 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
338 DRV_LOG(ERR, "can't allocate mem for id pool");
342 pool->free_arr = mem;
343 pool->curr = pool->free_arr;
344 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
345 pool->base_index = 0;
346 pool->max_id = max_id;
354 * Release ID pool structure.
357 * Pointer to flow id pool object to free.
360 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
362 mlx5_free(pool->free_arr);
370 * Pointer to flow id pool.
375 * 0 on success, error value otherwise.
378 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
380 if (pool->curr == pool->free_arr) {
381 if (pool->base_index == pool->max_id) {
383 DRV_LOG(ERR, "no free id");
386 *id = ++pool->base_index;
389 *id = *(--pool->curr);
397 * Pointer to flow id pool.
402 * 0 on success, error value otherwise.
405 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
411 if (pool->curr == pool->last) {
412 size = pool->curr - pool->free_arr;
413 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
414 MLX5_ASSERT(size2 > size);
415 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
418 DRV_LOG(ERR, "can't allocate mem for id pool");
422 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
423 mlx5_free(pool->free_arr);
424 pool->free_arr = mem;
425 pool->curr = pool->free_arr + size;
426 pool->last = pool->free_arr + size2;
434 * Initialize the shared aging list information per port.
437 * Pointer to mlx5_dev_ctx_shared object.
440 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
443 struct mlx5_age_info *age_info;
445 for (i = 0; i < sh->max_port; i++) {
446 age_info = &sh->port[i].age_info;
448 TAILQ_INIT(&age_info->aged_counters);
449 rte_spinlock_init(&age_info->aged_sl);
450 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
455 * Initialize the counters management structure.
458 * Pointer to mlx5_dev_ctx_shared object to free
461 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
465 memset(&sh->cmng, 0, sizeof(sh->cmng));
466 TAILQ_INIT(&sh->cmng.flow_counters);
467 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
468 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
469 sh->cmng.ccont[i].max_id = -1;
470 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
471 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
472 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
473 TAILQ_INIT(&sh->cmng.ccont[i].counters);
474 rte_spinlock_init(&sh->cmng.ccont[i].csl);
479 * Destroy all the resources allocated for a counter memory management.
482 * Pointer to the memory management structure.
485 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
487 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
489 LIST_REMOVE(mng, next);
490 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
491 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
496 * Close and release all the resources of the counters management.
499 * Pointer to mlx5_dev_ctx_shared object to free.
502 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
504 struct mlx5_counter_stats_mem_mng *mng;
511 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
512 if (rte_errno != EINPROGRESS)
516 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
517 struct mlx5_flow_counter_pool *pool;
518 uint32_t batch = !!(i > 1);
520 if (!sh->cmng.ccont[i].pools)
522 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
524 if (batch && pool->min_dcs)
525 claim_zero(mlx5_devx_cmd_destroy
527 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
528 if (MLX5_POOL_GET_CNT(pool, j)->action)
530 (mlx5_glue->destroy_flow_action
533 if (!batch && MLX5_GET_POOL_CNT_EXT
535 claim_zero(mlx5_devx_cmd_destroy
536 (MLX5_GET_POOL_CNT_EXT
539 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
541 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
543 mlx5_free(sh->cmng.ccont[i].pools);
545 mng = LIST_FIRST(&sh->cmng.mem_mngs);
547 mlx5_flow_destroy_counter_stat_mem_mng(mng);
548 mng = LIST_FIRST(&sh->cmng.mem_mngs);
550 memset(&sh->cmng, 0, sizeof(sh->cmng));
554 * Initialize the flow resources' indexed mempool.
557 * Pointer to mlx5_dev_ctx_shared object.
559 * Pointer to user dev config.
562 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
563 const struct mlx5_dev_config *config)
566 struct mlx5_indexed_pool_config cfg;
568 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
569 cfg = mlx5_ipool_cfg[i];
574 * Set MLX5_IPOOL_MLX5_FLOW ipool size
575 * according to PCI function flow configuration.
577 case MLX5_IPOOL_MLX5_FLOW:
578 cfg.size = config->dv_flow_en ?
579 sizeof(struct mlx5_flow_handle) :
580 MLX5_FLOW_HANDLE_VERBS_SIZE;
583 if (config->reclaim_mode)
584 cfg.release_mem_en = 1;
585 sh->ipool[i] = mlx5_ipool_create(&cfg);
590 * Release the flow resources' indexed mempool.
593 * Pointer to mlx5_dev_ctx_shared object.
596 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
600 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
601 mlx5_ipool_destroy(sh->ipool[i]);
605 * Check if dynamic flex parser for eCPRI already exists.
608 * Pointer to Ethernet device structure.
611 * true on exists, false on not.
614 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
616 struct mlx5_priv *priv = dev->data->dev_private;
617 struct mlx5_flex_parser_profiles *prf =
618 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
624 * Allocation of a flex parser for eCPRI. Once created, this parser related
625 * resources will be held until the device is closed.
628 * Pointer to Ethernet device structure.
631 * 0 on success, a negative errno value otherwise and rte_errno is set.
634 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
636 struct mlx5_priv *priv = dev->data->dev_private;
637 struct mlx5_flex_parser_profiles *prf =
638 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
639 struct mlx5_devx_graph_node_attr node = {
640 .modify_field_select = 0,
645 if (!priv->config.hca_attr.parse_graph_flex_node) {
646 DRV_LOG(ERR, "Dynamic flex parser is not supported "
647 "for device %s.", priv->dev_data->name);
650 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
651 /* 8 bytes now: 4B common header + 4B message body header. */
652 node.header_length_base_value = 0x8;
653 /* After MAC layer: Ether / VLAN. */
654 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
655 /* Type of compared condition should be 0xAEFE in the L2 layer. */
656 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
657 /* Sample #0: type in common header. */
658 node.sample[0].flow_match_sample_en = 1;
660 node.sample[0].flow_match_sample_offset_mode = 0x0;
661 /* Only the 2nd byte will be used. */
662 node.sample[0].flow_match_sample_field_base_offset = 0x0;
663 /* Sample #1: message payload. */
664 node.sample[1].flow_match_sample_en = 1;
666 node.sample[1].flow_match_sample_offset_mode = 0x0;
668 * Only the first two bytes will be used right now, and its offset will
669 * start after the common header that with the length of a DW(u32).
671 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
672 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
674 DRV_LOG(ERR, "Failed to create flex parser node object.");
675 return (rte_errno == 0) ? -ENODEV : -rte_errno;
678 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
680 DRV_LOG(ERR, "Failed to query sample IDs.");
681 return (rte_errno == 0) ? -ENODEV : -rte_errno;
683 prf->offset[0] = 0x0;
684 prf->offset[1] = sizeof(uint32_t);
685 prf->ids[0] = ids[0];
686 prf->ids[1] = ids[1];
691 * Destroy the flex parser node, including the parser itself, input / output
692 * arcs and DW samples. Resources could be reused then.
695 * Pointer to Ethernet device structure.
698 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
700 struct mlx5_priv *priv = dev->data->dev_private;
701 struct mlx5_flex_parser_profiles *prf =
702 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
705 mlx5_devx_cmd_destroy(prf->obj);
710 * Allocate shared device context. If there is multiport device the
711 * master and representors will share this context, if there is single
712 * port dedicated device, the context will be used by only given
713 * port due to unification.
715 * Routine first searches the context for the specified device name,
716 * if found the shared context assumed and reference counter is incremented.
717 * If no context found the new one is created and initialized with specified
718 * device context and parameters.
721 * Pointer to the device attributes (name, port, etc).
723 * Pointer to device configuration structure.
726 * Pointer to mlx5_dev_ctx_shared object on success,
727 * otherwise NULL and rte_errno is set.
729 struct mlx5_dev_ctx_shared *
730 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
731 const struct mlx5_dev_config *config)
733 struct mlx5_dev_ctx_shared *sh;
736 struct mlx5_devx_tis_attr tis_attr = { 0 };
739 /* Secondary process should not create the shared context. */
740 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
741 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
742 /* Search for IB context by device name. */
743 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
744 if (!strcmp(sh->ibdev_name,
745 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
750 /* No device found, we have to create new shared context. */
751 MLX5_ASSERT(spawn->max_port);
752 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
753 sizeof(struct mlx5_dev_ctx_shared) +
755 sizeof(struct mlx5_dev_shared_port),
756 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
758 DRV_LOG(ERR, "shared context allocation failure");
762 err = mlx5_os_open_device(spawn, config, sh);
765 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
767 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
771 sh->max_port = spawn->max_port;
772 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
773 sizeof(sh->ibdev_name) - 1);
774 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
775 sizeof(sh->ibdev_path) - 1);
777 * Setting port_id to max unallowed value means
778 * there is no interrupt subhandler installed for
779 * the given port index i.
781 for (i = 0; i < sh->max_port; i++) {
782 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
783 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
785 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
786 if (sh->pd == NULL) {
787 DRV_LOG(ERR, "PD allocation failure");
792 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
794 DRV_LOG(ERR, "Fail to extract pdn from PD");
797 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
799 DRV_LOG(ERR, "TD allocation failure");
803 tis_attr.transport_domain = sh->td->id;
804 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
806 DRV_LOG(ERR, "TIS allocation failure");
810 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
812 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
817 sh->flow_id_pool = mlx5_flow_id_pool_alloc
818 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
819 if (!sh->flow_id_pool) {
820 DRV_LOG(ERR, "can't create flow id pool");
825 /* Initialize UAR access locks for 32bit implementations. */
826 rte_spinlock_init(&sh->uar_lock_cq);
827 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
828 rte_spinlock_init(&sh->uar_lock[i]);
831 * Once the device is added to the list of memory event
832 * callback, its global MR cache table cannot be expanded
833 * on the fly because of deadlock. If it overflows, lookup
834 * should be done by searching MR list linearly, which is slow.
836 * At this point the device is not added to the memory
837 * event list yet, context is just being created.
839 err = mlx5_mr_btree_init(&sh->share_cache.cache,
840 MLX5_MR_BTREE_CACHE_N * 2,
841 spawn->pci_dev->device.numa_node);
846 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
847 &sh->share_cache.dereg_mr_cb);
848 mlx5_os_dev_shared_handler_install(sh);
849 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
850 if (!sh->cnt_id_tbl) {
854 mlx5_flow_aging_init(sh);
855 mlx5_flow_counters_mng_init(sh);
856 mlx5_flow_ipool_create(sh, config);
857 /* Add device to memory callback list. */
858 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
859 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
861 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
862 /* Add context to the global device list. */
863 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
865 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
868 pthread_mutex_destroy(&sh->txpp.mutex);
869 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
871 if (sh->cnt_id_tbl) {
872 mlx5_l3t_destroy(sh->cnt_id_tbl);
873 sh->cnt_id_tbl = NULL;
876 mlx5_glue->devx_free_uar(sh->tx_uar);
880 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
882 claim_zero(mlx5_devx_cmd_destroy(sh->td));
884 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
886 claim_zero(mlx5_glue->close_device(sh->ctx));
887 if (sh->flow_id_pool)
888 mlx5_flow_id_pool_release(sh->flow_id_pool);
890 MLX5_ASSERT(err > 0);
896 * Free shared IB device context. Decrement counter and if zero free
897 * all allocated resources and close handles.
900 * Pointer to mlx5_dev_ctx_shared object to free
903 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
905 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
906 #ifdef RTE_LIBRTE_MLX5_DEBUG
907 /* Check the object presence in the list. */
908 struct mlx5_dev_ctx_shared *lctx;
910 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
915 DRV_LOG(ERR, "Freeing non-existing shared IB context");
920 MLX5_ASSERT(sh->refcnt);
921 /* Secondary process should not free the shared context. */
922 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
925 /* Remove from memory callback device list. */
926 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
927 LIST_REMOVE(sh, mem_event_cb);
928 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
929 /* Release created Memory Regions. */
930 mlx5_mr_release_cache(&sh->share_cache);
931 /* Remove context from the global device list. */
932 LIST_REMOVE(sh, next);
934 * Ensure there is no async event handler installed.
935 * Only primary process handles async device events.
937 mlx5_flow_counters_mng_close(sh);
938 mlx5_flow_ipool_destroy(sh);
939 mlx5_os_dev_shared_handler_uninstall(sh);
940 if (sh->cnt_id_tbl) {
941 mlx5_l3t_destroy(sh->cnt_id_tbl);
942 sh->cnt_id_tbl = NULL;
945 mlx5_glue->devx_free_uar(sh->tx_uar);
949 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
951 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
953 claim_zero(mlx5_devx_cmd_destroy(sh->td));
955 claim_zero(mlx5_glue->close_device(sh->ctx));
956 if (sh->flow_id_pool)
957 mlx5_flow_id_pool_release(sh->flow_id_pool);
958 pthread_mutex_destroy(&sh->txpp.mutex);
961 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
965 * Destroy table hash list and all the root entries per domain.
968 * Pointer to the private device data structure.
971 mlx5_free_table_hash_list(struct mlx5_priv *priv)
973 struct mlx5_dev_ctx_shared *sh = priv->sh;
974 struct mlx5_flow_tbl_data_entry *tbl_data;
975 union mlx5_flow_tbl_key table_key = {
983 struct mlx5_hlist_entry *pos;
987 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
989 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
991 MLX5_ASSERT(tbl_data);
992 mlx5_hlist_remove(sh->flow_tbls, pos);
995 table_key.direction = 1;
996 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
998 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1000 MLX5_ASSERT(tbl_data);
1001 mlx5_hlist_remove(sh->flow_tbls, pos);
1002 mlx5_free(tbl_data);
1004 table_key.direction = 0;
1005 table_key.domain = 1;
1006 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1008 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1010 MLX5_ASSERT(tbl_data);
1011 mlx5_hlist_remove(sh->flow_tbls, pos);
1012 mlx5_free(tbl_data);
1014 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1018 * Initialize flow table hash list and create the root tables entry
1022 * Pointer to the private device data structure.
1025 * Zero on success, positive error code otherwise.
1028 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1030 struct mlx5_dev_ctx_shared *sh = priv->sh;
1031 char s[MLX5_HLIST_NAMESIZE];
1035 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1036 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1037 if (!sh->flow_tbls) {
1038 DRV_LOG(ERR, "flow tables with hash creation failed.");
1042 #ifndef HAVE_MLX5DV_DR
1044 * In case we have not DR support, the zero tables should be created
1045 * because DV expect to see them even if they cannot be created by
1048 union mlx5_flow_tbl_key table_key = {
1056 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1057 sizeof(*tbl_data), 0,
1064 tbl_data->entry.key = table_key.v64;
1065 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1068 rte_atomic32_init(&tbl_data->tbl.refcnt);
1069 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1070 table_key.direction = 1;
1071 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1077 tbl_data->entry.key = table_key.v64;
1078 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1081 rte_atomic32_init(&tbl_data->tbl.refcnt);
1082 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1083 table_key.direction = 0;
1084 table_key.domain = 1;
1085 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1091 tbl_data->entry.key = table_key.v64;
1092 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1095 rte_atomic32_init(&tbl_data->tbl.refcnt);
1096 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1099 mlx5_free_table_hash_list(priv);
1100 #endif /* HAVE_MLX5DV_DR */
1105 * Retrieve integer value from environment variable.
1108 * Environment variable name.
1111 * Integer value, 0 if the variable is not set.
1114 mlx5_getenv_int(const char *name)
1116 const char *val = getenv(name);
1124 * DPDK callback to add udp tunnel port
1127 * A pointer to eth_dev
1128 * @param[in] udp_tunnel
1129 * A pointer to udp tunnel
1132 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1135 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1136 struct rte_eth_udp_tunnel *udp_tunnel)
1138 MLX5_ASSERT(udp_tunnel != NULL);
1139 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1140 udp_tunnel->udp_port == 4789)
1142 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1143 udp_tunnel->udp_port == 4790)
1149 * Initialize process private data structure.
1152 * Pointer to Ethernet device structure.
1155 * 0 on success, a negative errno value otherwise and rte_errno is set.
1158 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1160 struct mlx5_priv *priv = dev->data->dev_private;
1161 struct mlx5_proc_priv *ppriv;
1165 * UAR register table follows the process private structure. BlueFlame
1166 * registers for Tx queues are stored in the table.
1169 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1170 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1171 dev->device->numa_node);
1176 ppriv->uar_table_sz = ppriv_size;
1177 dev->process_private = ppriv;
1182 * Un-initialize process private data structure.
1185 * Pointer to Ethernet device structure.
1188 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1190 if (!dev->process_private)
1192 mlx5_free(dev->process_private);
1193 dev->process_private = NULL;
1197 * DPDK callback to close the device.
1199 * Destroy all queues and objects, free memory.
1202 * Pointer to Ethernet device structure.
1205 mlx5_dev_close(struct rte_eth_dev *dev)
1207 struct mlx5_priv *priv = dev->data->dev_private;
1211 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1212 /* Check if process_private released. */
1213 if (!dev->process_private)
1215 mlx5_tx_uar_uninit_secondary(dev);
1216 mlx5_proc_priv_uninit(dev);
1217 rte_eth_dev_release_port(dev);
1222 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1224 ((priv->sh->ctx != NULL) ?
1225 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1227 * If default mreg copy action is removed at the stop stage,
1228 * the search will return none and nothing will be done anymore.
1230 mlx5_flow_stop_default(dev);
1231 mlx5_traffic_disable(dev);
1233 * If all the flows are already flushed in the device stop stage,
1234 * then this will return directly without any action.
1236 mlx5_flow_list_flush(dev, &priv->flows, true);
1237 mlx5_flow_meter_flush(dev, NULL);
1238 /* Free the intermediate buffers for flow creation. */
1239 mlx5_flow_free_intermediate(dev);
1240 /* Prevent crashes when queues are still in use. */
1241 dev->rx_pkt_burst = removed_rx_burst;
1242 dev->tx_pkt_burst = removed_tx_burst;
1244 /* Disable datapath on secondary process. */
1245 mlx5_mp_os_req_stop_rxtx(dev);
1246 /* Free the eCPRI flex parser resource. */
1247 mlx5_flex_parser_ecpri_release(dev);
1248 if (priv->rxqs != NULL) {
1249 /* XXX race condition if mlx5_rx_burst() is still running. */
1251 for (i = 0; (i != priv->rxqs_n); ++i)
1252 mlx5_rxq_release(dev, i);
1256 if (priv->txqs != NULL) {
1257 /* XXX race condition if mlx5_tx_burst() is still running. */
1259 for (i = 0; (i != priv->txqs_n); ++i)
1260 mlx5_txq_release(dev, i);
1264 mlx5_proc_priv_uninit(dev);
1265 if (priv->mreg_cp_tbl)
1266 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1267 mlx5_mprq_free_mp(dev);
1268 mlx5_os_free_shared_dr(priv);
1269 if (priv->rss_conf.rss_key != NULL)
1270 mlx5_free(priv->rss_conf.rss_key);
1271 if (priv->reta_idx != NULL)
1272 mlx5_free(priv->reta_idx);
1273 if (priv->config.vf)
1274 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1275 dev->data->mac_addrs,
1276 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1277 if (priv->nl_socket_route >= 0)
1278 close(priv->nl_socket_route);
1279 if (priv->nl_socket_rdma >= 0)
1280 close(priv->nl_socket_rdma);
1281 if (priv->vmwa_context)
1282 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1283 ret = mlx5_hrxq_verify(dev);
1285 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1286 dev->data->port_id);
1287 ret = mlx5_ind_table_obj_verify(dev);
1289 DRV_LOG(WARNING, "port %u some indirection table still remain",
1290 dev->data->port_id);
1291 ret = mlx5_rxq_obj_verify(dev);
1293 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1294 dev->data->port_id);
1295 ret = mlx5_rxq_verify(dev);
1297 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1298 dev->data->port_id);
1299 ret = mlx5_txq_obj_verify(dev);
1301 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1302 dev->data->port_id);
1303 ret = mlx5_txq_verify(dev);
1305 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1306 dev->data->port_id);
1307 ret = mlx5_flow_verify(dev);
1309 DRV_LOG(WARNING, "port %u some flows still remain",
1310 dev->data->port_id);
1312 * Free the shared context in last turn, because the cleanup
1313 * routines above may use some shared fields, like
1314 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1315 * ifindex if Netlink fails.
1317 mlx5_free_shared_dev_ctx(priv->sh);
1318 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1322 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1323 struct mlx5_priv *opriv =
1324 rte_eth_devices[port_id].data->dev_private;
1327 opriv->domain_id != priv->domain_id ||
1328 &rte_eth_devices[port_id] == dev)
1334 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1336 memset(priv, 0, sizeof(*priv));
1337 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1339 * Reset mac_addrs to NULL such that it is not freed as part of
1340 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1341 * it is freed when dev_private is freed.
1343 dev->data->mac_addrs = NULL;
1347 * Verify and store value for device argument.
1350 * Key argument to verify.
1352 * Value associated with key.
1357 * 0 on success, a negative errno value otherwise and rte_errno is set.
1360 mlx5_args_check(const char *key, const char *val, void *opaque)
1362 struct mlx5_dev_config *config = opaque;
1366 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1367 if (!strcmp(MLX5_REPRESENTOR, key))
1370 tmp = strtol(val, NULL, 0);
1373 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1376 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1377 /* Negative values are acceptable for some keys only. */
1379 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1382 mod = tmp >= 0 ? tmp : -tmp;
1383 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1384 config->cqe_comp = !!tmp;
1385 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1386 config->cqe_pad = !!tmp;
1387 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1388 config->hw_padding = !!tmp;
1389 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1390 config->mprq.enabled = !!tmp;
1391 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1392 config->mprq.stride_num_n = tmp;
1393 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1394 config->mprq.stride_size_n = tmp;
1395 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1396 config->mprq.max_memcpy_len = tmp;
1397 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1398 config->mprq.min_rxqs_num = tmp;
1399 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1400 DRV_LOG(WARNING, "%s: deprecated parameter,"
1401 " converted to txq_inline_max", key);
1402 config->txq_inline_max = tmp;
1403 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1404 config->txq_inline_max = tmp;
1405 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1406 config->txq_inline_min = tmp;
1407 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1408 config->txq_inline_mpw = tmp;
1409 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1410 config->txqs_inline = tmp;
1411 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1412 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1413 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1414 config->mps = !!tmp;
1415 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1416 if (tmp != MLX5_TXDB_CACHED &&
1417 tmp != MLX5_TXDB_NCACHED &&
1418 tmp != MLX5_TXDB_HEURISTIC) {
1419 DRV_LOG(ERR, "invalid Tx doorbell "
1420 "mapping parameter");
1425 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1426 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1427 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1428 DRV_LOG(WARNING, "%s: deprecated parameter,"
1429 " converted to txq_inline_mpw", key);
1430 config->txq_inline_mpw = tmp;
1431 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1432 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1433 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1435 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1439 config->tx_pp = tmp;
1440 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1441 config->tx_skew = tmp;
1442 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1443 config->rx_vec_en = !!tmp;
1444 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1445 config->l3_vxlan_en = !!tmp;
1446 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1447 config->vf_nl_en = !!tmp;
1448 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1449 config->dv_esw_en = !!tmp;
1450 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1451 config->dv_flow_en = !!tmp;
1452 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1453 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1454 tmp != MLX5_XMETA_MODE_META16 &&
1455 tmp != MLX5_XMETA_MODE_META32) {
1456 DRV_LOG(ERR, "invalid extensive "
1457 "metadata parameter");
1461 config->dv_xmeta_en = tmp;
1462 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1463 config->lacp_by_user = !!tmp;
1464 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1465 config->mr_ext_memseg_en = !!tmp;
1466 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1467 config->max_dump_files_num = tmp;
1468 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1469 config->lro.timeout = tmp;
1470 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1471 DRV_LOG(DEBUG, "class argument is %s.", val);
1472 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1473 config->log_hp_size = tmp;
1474 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1475 if (tmp != MLX5_RCM_NONE &&
1476 tmp != MLX5_RCM_LIGHT &&
1477 tmp != MLX5_RCM_AGGR) {
1478 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1482 config->reclaim_mode = tmp;
1483 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1484 config->sys_mem_en = !!tmp;
1485 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1486 config->decap_en = !!tmp;
1488 DRV_LOG(WARNING, "%s: unknown parameter", key);
1496 * Parse device parameters.
1499 * Pointer to device configuration structure.
1501 * Device arguments structure.
1504 * 0 on success, a negative errno value otherwise and rte_errno is set.
1507 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1509 const char **params = (const char *[]){
1510 MLX5_RXQ_CQE_COMP_EN,
1511 MLX5_RXQ_CQE_PAD_EN,
1512 MLX5_RXQ_PKT_PAD_EN,
1514 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1515 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1516 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1519 MLX5_TXQ_INLINE_MIN,
1520 MLX5_TXQ_INLINE_MAX,
1521 MLX5_TXQ_INLINE_MPW,
1522 MLX5_TXQS_MIN_INLINE,
1525 MLX5_TXQ_MPW_HDR_DSEG_EN,
1526 MLX5_TXQ_MAX_INLINE_LEN,
1538 MLX5_MR_EXT_MEMSEG_EN,
1540 MLX5_MAX_DUMP_FILES_NUM,
1541 MLX5_LRO_TIMEOUT_USEC,
1542 MLX5_CLASS_ARG_NAME,
1549 struct rte_kvargs *kvlist;
1553 if (devargs == NULL)
1555 /* Following UGLY cast is done to pass checkpatch. */
1556 kvlist = rte_kvargs_parse(devargs->args, params);
1557 if (kvlist == NULL) {
1561 /* Process parameters. */
1562 for (i = 0; (params[i] != NULL); ++i) {
1563 if (rte_kvargs_count(kvlist, params[i])) {
1564 ret = rte_kvargs_process(kvlist, params[i],
1565 mlx5_args_check, config);
1568 rte_kvargs_free(kvlist);
1573 rte_kvargs_free(kvlist);
1578 * Configures the minimal amount of data to inline into WQE
1579 * while sending packets.
1581 * - the txq_inline_min has the maximal priority, if this
1582 * key is specified in devargs
1583 * - if DevX is enabled the inline mode is queried from the
1584 * device (HCA attributes and NIC vport context if needed).
1585 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1586 * and none (0 bytes) for other NICs
1589 * Verbs device parameters (name, port, switch_info) to spawn.
1591 * Device configuration parameters.
1594 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1595 struct mlx5_dev_config *config)
1597 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1598 /* Application defines size of inlined data explicitly. */
1599 switch (spawn->pci_dev->id.device_id) {
1600 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1601 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1602 if (config->txq_inline_min <
1603 (int)MLX5_INLINE_HSIZE_L2) {
1605 "txq_inline_mix aligned to minimal"
1606 " ConnectX-4 required value %d",
1607 (int)MLX5_INLINE_HSIZE_L2);
1608 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1614 if (config->hca_attr.eth_net_offloads) {
1615 /* We have DevX enabled, inline mode queried successfully. */
1616 switch (config->hca_attr.wqe_inline_mode) {
1617 case MLX5_CAP_INLINE_MODE_L2:
1618 /* outer L2 header must be inlined. */
1619 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1621 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1622 /* No inline data are required by NIC. */
1623 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1624 config->hw_vlan_insert =
1625 config->hca_attr.wqe_vlan_insert;
1626 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1628 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1629 /* inline mode is defined by NIC vport context. */
1630 if (!config->hca_attr.eth_virt)
1632 switch (config->hca_attr.vport_inline_mode) {
1633 case MLX5_INLINE_MODE_NONE:
1634 config->txq_inline_min =
1635 MLX5_INLINE_HSIZE_NONE;
1637 case MLX5_INLINE_MODE_L2:
1638 config->txq_inline_min =
1639 MLX5_INLINE_HSIZE_L2;
1641 case MLX5_INLINE_MODE_IP:
1642 config->txq_inline_min =
1643 MLX5_INLINE_HSIZE_L3;
1645 case MLX5_INLINE_MODE_TCP_UDP:
1646 config->txq_inline_min =
1647 MLX5_INLINE_HSIZE_L4;
1649 case MLX5_INLINE_MODE_INNER_L2:
1650 config->txq_inline_min =
1651 MLX5_INLINE_HSIZE_INNER_L2;
1653 case MLX5_INLINE_MODE_INNER_IP:
1654 config->txq_inline_min =
1655 MLX5_INLINE_HSIZE_INNER_L3;
1657 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1658 config->txq_inline_min =
1659 MLX5_INLINE_HSIZE_INNER_L4;
1665 * We get here if we are unable to deduce
1666 * inline data size with DevX. Try PCI ID
1667 * to determine old NICs.
1669 switch (spawn->pci_dev->id.device_id) {
1670 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1671 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1672 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1673 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1674 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1675 config->hw_vlan_insert = 0;
1677 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1678 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1679 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1680 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1682 * These NICs support VLAN insertion from WQE and
1683 * report the wqe_vlan_insert flag. But there is the bug
1684 * and PFC control may be broken, so disable feature.
1686 config->hw_vlan_insert = 0;
1687 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1690 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1694 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1698 * Configures the metadata mask fields in the shared context.
1701 * Pointer to Ethernet device.
1704 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1706 struct mlx5_priv *priv = dev->data->dev_private;
1707 struct mlx5_dev_ctx_shared *sh = priv->sh;
1708 uint32_t meta, mark, reg_c0;
1710 reg_c0 = ~priv->vport_meta_mask;
1711 switch (priv->config.dv_xmeta_en) {
1712 case MLX5_XMETA_MODE_LEGACY:
1714 mark = MLX5_FLOW_MARK_MASK;
1716 case MLX5_XMETA_MODE_META16:
1717 meta = reg_c0 >> rte_bsf32(reg_c0);
1718 mark = MLX5_FLOW_MARK_MASK;
1720 case MLX5_XMETA_MODE_META32:
1722 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1730 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1731 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1732 sh->dv_mark_mask, mark);
1734 sh->dv_mark_mask = mark;
1735 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1736 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1737 sh->dv_meta_mask, meta);
1739 sh->dv_meta_mask = meta;
1740 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1741 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1742 sh->dv_meta_mask, reg_c0);
1744 sh->dv_regc0_mask = reg_c0;
1745 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1746 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1747 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1748 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1752 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1754 static const char *const dynf_names[] = {
1755 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1756 RTE_MBUF_DYNFLAG_METADATA_NAME,
1757 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1761 if (n < RTE_DIM(dynf_names))
1763 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1764 if (names[i] == NULL)
1766 strcpy(names[i], dynf_names[i]);
1768 return RTE_DIM(dynf_names);
1772 * Comparison callback to sort device data.
1774 * This is meant to be used with qsort().
1777 * Pointer to pointer to first data object.
1779 * Pointer to pointer to second data object.
1782 * 0 if both objects are equal, less than 0 if the first argument is less
1783 * than the second, greater than 0 otherwise.
1786 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1787 struct mlx5_dev_config *config)
1789 struct mlx5_dev_ctx_shared *sh = priv->sh;
1790 struct mlx5_dev_config *sh_conf = NULL;
1794 /* Nothing to compare for the single/first device. */
1795 if (sh->refcnt == 1)
1797 /* Find the device with shared context. */
1798 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1799 struct mlx5_priv *opriv =
1800 rte_eth_devices[port_id].data->dev_private;
1802 if (opriv && opriv != priv && opriv->sh == sh) {
1803 sh_conf = &opriv->config;
1809 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1810 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1811 " for shared %s context", sh->ibdev_name);
1815 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1816 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1817 " for shared %s context", sh->ibdev_name);
1825 * Look for the ethernet device belonging to mlx5 driver.
1827 * @param[in] port_id
1828 * port_id to start looking for device.
1829 * @param[in] pci_dev
1830 * Pointer to the hint PCI device. When device is being probed
1831 * the its siblings (master and preceding representors might
1832 * not have assigned driver yet (because the mlx5_os_pci_probe()
1833 * is not completed yet, for this case match on hint PCI
1834 * device may be used to detect sibling device.
1837 * port_id of found device, RTE_MAX_ETHPORT if not found.
1840 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1842 while (port_id < RTE_MAX_ETHPORTS) {
1843 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1845 if (dev->state != RTE_ETH_DEV_UNUSED &&
1847 (dev->device == &pci_dev->device ||
1848 (dev->device->driver &&
1849 dev->device->driver->name &&
1850 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1854 if (port_id >= RTE_MAX_ETHPORTS)
1855 return RTE_MAX_ETHPORTS;
1860 * DPDK callback to remove a PCI device.
1862 * This function removes all Ethernet devices belong to a given PCI device.
1864 * @param[in] pci_dev
1865 * Pointer to the PCI device.
1868 * 0 on success, the function cannot fail.
1871 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1875 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1877 * mlx5_dev_close() is not registered to secondary process,
1878 * call the close function explicitly for secondary process.
1880 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1881 mlx5_dev_close(&rte_eth_devices[port_id]);
1883 rte_eth_dev_close(port_id);
1888 static const struct rte_pci_id mlx5_pci_id_map[] = {
1890 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1891 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1894 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1895 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1898 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1899 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1902 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1903 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1906 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1907 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1910 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1911 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1914 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1915 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1918 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1919 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1922 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1923 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1926 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1927 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1930 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1931 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1934 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1935 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1938 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1939 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1942 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1943 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1946 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1947 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1950 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1951 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1958 struct rte_pci_driver mlx5_driver = {
1960 .name = MLX5_DRIVER_NAME
1962 .id_table = mlx5_pci_id_map,
1963 .probe = mlx5_os_pci_probe,
1964 .remove = mlx5_pci_remove,
1965 .dma_map = mlx5_dma_map,
1966 .dma_unmap = mlx5_dma_unmap,
1967 .drv_flags = PCI_DRV_FLAGS,
1970 /* Initialize driver log type. */
1971 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1974 * Driver initialization routine.
1976 RTE_INIT(rte_mlx5_pmd_init)
1978 /* Build the static tables for Verbs conversion. */
1979 mlx5_set_ptype_table();
1980 mlx5_set_cksum_table();
1981 mlx5_set_swp_types_table();
1983 rte_pci_register(&mlx5_driver);
1986 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1987 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1988 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");