1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
15 #include <linux/rtnetlink.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_malloc.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_ethdev_pci.h>
31 #include <rte_bus_pci.h>
32 #include <rte_common.h>
33 #include <rte_kvargs.h>
34 #include <rte_rwlock.h>
35 #include <rte_spinlock.h>
36 #include <rte_string_fns.h>
37 #include <rte_alarm.h>
39 #include <mlx5_glue.h>
40 #include <mlx5_devx_cmds.h>
41 #include <mlx5_common.h>
42 #include <mlx5_common_mp.h>
44 #include "mlx5_defs.h"
46 #include "mlx5_utils.h"
47 #include "mlx5_rxtx.h"
48 #include "mlx5_autoconf.h"
50 #include "mlx5_flow.h"
51 #include "rte_pmd_mlx5.h"
53 /* Device parameter to enable RX completion queue compression. */
54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
56 /* Device parameter to enable RX completion entry padding to 128B. */
57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
59 /* Device parameter to enable padding Rx packet to cacheline size. */
60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
62 /* Device parameter to enable Multi-Packet Rx queue. */
63 #define MLX5_RX_MPRQ_EN "mprq_en"
65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
77 /* Device parameter to configure inline send. Deprecated, ignored.*/
78 #define MLX5_TXQ_INLINE "txq_inline"
80 /* Device parameter to limit packet size to inline with ordinary SEND. */
81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
83 /* Device parameter to configure minimal data size to inline. */
84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
90 * Device parameter to configure the number of TX queues threshold for
91 * enabling inline send.
93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
96 * Device parameter to configure the number of TX queues threshold for
97 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
101 /* Device parameter to enable multi-packet send WQEs. */
102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
105 * Device parameter to force doorbell register mapping
106 * to non-cahed region eliminating the extra write memory barrier.
108 #define MLX5_TX_DB_NC "tx_db_nc"
111 * Device parameter to include 2 dsegs in the title WQEBB.
112 * Deprecated, ignored.
114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
117 * Device parameter to limit the size of inlining packet.
118 * Deprecated, ignored.
120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
123 * Device parameter to enable hardware Tx vector.
124 * Deprecated, ignored (no vectorized Tx routines anymore).
126 #define MLX5_TX_VEC_EN "tx_vec_en"
128 /* Device parameter to enable hardware Rx vector. */
129 #define MLX5_RX_VEC_EN "rx_vec_en"
131 /* Allow L3 VXLAN flow creation. */
132 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
134 /* Activate DV E-Switch flow steering. */
135 #define MLX5_DV_ESW_EN "dv_esw_en"
137 /* Activate DV flow steering. */
138 #define MLX5_DV_FLOW_EN "dv_flow_en"
140 /* Enable extensive flow metadata support. */
141 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
143 /* Activate Netlink support in VF mode. */
144 #define MLX5_VF_NL_EN "vf_nl_en"
146 /* Enable extending memsegs when creating a MR. */
147 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
149 /* Select port representors to instantiate. */
150 #define MLX5_REPRESENTOR "representor"
152 /* Device parameter to configure the maximum number of dump files per queue. */
153 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
155 /* Configure timeout of LRO session (in microseconds). */
156 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
159 * Device parameter to configure the total data buffer size for a single
160 * hairpin queue (logarithm value).
162 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
164 /* Flow memory reclaim mode. */
165 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
167 #ifndef HAVE_IBV_MLX5_MOD_MPW
168 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
169 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
172 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
173 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
176 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
178 /* Shared memory between primary and secondary processes. */
179 struct mlx5_shared_data *mlx5_shared_data;
181 /* Spinlock for mlx5_shared_data allocation. */
182 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
184 /* Process local data for secondary processes. */
185 static struct mlx5_local_data mlx5_local_data;
187 /** Driver-specific log messages type. */
190 /** Data associated with devices to spawn. */
191 struct mlx5_dev_spawn_data {
192 uint32_t ifindex; /**< Network interface index. */
193 uint32_t max_port; /**< IB device maximal port index. */
194 uint32_t ibv_port; /**< IB device physical port index. */
195 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
196 struct mlx5_switch_info info; /**< Switch information. */
197 struct ibv_device *ibv_dev; /**< Associated IB device. */
198 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
199 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
202 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
203 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
205 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
206 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
208 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
214 .malloc = rte_malloc_socket,
216 .type = "mlx5_encap_decap_ipool",
219 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
225 .malloc = rte_malloc_socket,
227 .type = "mlx5_push_vlan_ipool",
230 .size = sizeof(struct mlx5_flow_dv_tag_resource),
236 .malloc = rte_malloc_socket,
238 .type = "mlx5_tag_ipool",
241 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
247 .malloc = rte_malloc_socket,
249 .type = "mlx5_port_id_ipool",
252 .size = sizeof(struct mlx5_flow_tbl_data_entry),
258 .malloc = rte_malloc_socket,
260 .type = "mlx5_jump_ipool",
264 .size = sizeof(struct mlx5_flow_meter),
270 .malloc = rte_malloc_socket,
272 .type = "mlx5_meter_ipool",
275 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
281 .malloc = rte_malloc_socket,
283 .type = "mlx5_mcp_ipool",
286 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
292 .malloc = rte_malloc_socket,
294 .type = "mlx5_hrxq_ipool",
297 .size = sizeof(struct mlx5_flow_handle),
303 .malloc = rte_malloc_socket,
305 .type = "mlx5_flow_handle_ipool",
308 .size = sizeof(struct rte_flow),
312 .malloc = rte_malloc_socket,
314 .type = "rte_flow_ipool",
319 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
320 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
322 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
323 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
326 * Allocate ID pool structure.
329 * The maximum id can be allocated from the pool.
332 * Pointer to pool object, NULL value otherwise.
334 struct mlx5_flow_id_pool *
335 mlx5_flow_id_pool_alloc(uint32_t max_id)
337 struct mlx5_flow_id_pool *pool;
340 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
341 RTE_CACHE_LINE_SIZE);
343 DRV_LOG(ERR, "can't allocate id pool");
347 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
348 RTE_CACHE_LINE_SIZE);
350 DRV_LOG(ERR, "can't allocate mem for id pool");
354 pool->free_arr = mem;
355 pool->curr = pool->free_arr;
356 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
357 pool->base_index = 0;
358 pool->max_id = max_id;
366 * Release ID pool structure.
369 * Pointer to flow id pool object to free.
372 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
374 rte_free(pool->free_arr);
382 * Pointer to flow id pool.
387 * 0 on success, error value otherwise.
390 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
392 if (pool->curr == pool->free_arr) {
393 if (pool->base_index == pool->max_id) {
395 DRV_LOG(ERR, "no free id");
398 *id = ++pool->base_index;
401 *id = *(--pool->curr);
409 * Pointer to flow id pool.
414 * 0 on success, error value otherwise.
417 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
423 if (pool->curr == pool->last) {
424 size = pool->curr - pool->free_arr;
425 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
426 MLX5_ASSERT(size2 > size);
427 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
429 DRV_LOG(ERR, "can't allocate mem for id pool");
433 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
434 rte_free(pool->free_arr);
435 pool->free_arr = mem;
436 pool->curr = pool->free_arr + size;
437 pool->last = pool->free_arr + size2;
445 * Initialize the shared aging list information per port.
448 * Pointer to mlx5_ibv_shared object.
451 mlx5_flow_aging_init(struct mlx5_ibv_shared *sh)
454 struct mlx5_age_info *age_info;
456 for (i = 0; i < sh->max_port; i++) {
457 age_info = &sh->port[i].age_info;
459 TAILQ_INIT(&age_info->aged_counters);
460 rte_spinlock_init(&age_info->aged_sl);
461 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
466 * Initialize the counters management structure.
469 * Pointer to mlx5_ibv_shared object to free
472 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
476 memset(&sh->cmng, 0, sizeof(sh->cmng));
477 TAILQ_INIT(&sh->cmng.flow_counters);
478 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
479 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
480 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
485 * Destroy all the resources allocated for a counter memory management.
488 * Pointer to the memory management structure.
491 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
493 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
495 LIST_REMOVE(mng, next);
496 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
497 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
502 * Close and release all the resources of the counters management.
505 * Pointer to mlx5_ibv_shared object to free.
508 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
510 struct mlx5_counter_stats_mem_mng *mng;
517 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
518 if (rte_errno != EINPROGRESS)
522 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
523 struct mlx5_flow_counter_pool *pool;
524 uint32_t batch = !!(i > 1);
526 if (!sh->cmng.ccont[i].pools)
528 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
530 if (batch && pool->min_dcs)
531 claim_zero(mlx5_devx_cmd_destroy
533 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
534 if (MLX5_POOL_GET_CNT(pool, j)->action)
536 (mlx5_glue->destroy_flow_action
539 if (!batch && MLX5_GET_POOL_CNT_EXT
541 claim_zero(mlx5_devx_cmd_destroy
542 (MLX5_GET_POOL_CNT_EXT
545 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
547 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
549 rte_free(sh->cmng.ccont[i].pools);
551 mng = LIST_FIRST(&sh->cmng.mem_mngs);
553 mlx5_flow_destroy_counter_stat_mem_mng(mng);
554 mng = LIST_FIRST(&sh->cmng.mem_mngs);
556 memset(&sh->cmng, 0, sizeof(sh->cmng));
560 * Initialize the flow resources' indexed mempool.
563 * Pointer to mlx5_ibv_shared object.
565 * Pointer to user dev config.
568 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh,
569 const struct mlx5_dev_config *config __rte_unused)
573 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
575 * While DV is supported, user chooses the verbs mode,
576 * the mlx5 flow handle size is different with the
577 * MLX5_FLOW_HANDLE_VERBS_SIZE.
579 if (!config->dv_flow_en)
580 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
581 MLX5_FLOW_HANDLE_VERBS_SIZE;
583 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
584 if (config->reclaim_mode)
585 mlx5_ipool_cfg[i].release_mem_en = 1;
586 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
591 * Release the flow resources' indexed mempool.
594 * Pointer to mlx5_ibv_shared object.
597 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
601 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
602 mlx5_ipool_destroy(sh->ipool[i]);
606 * Extract pdn of PD object using DV API.
609 * Pointer to the verbs PD object.
611 * Pointer to the PD object number variable.
614 * 0 on success, error value otherwise.
616 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
618 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
620 struct mlx5dv_obj obj;
621 struct mlx5dv_pd pd_info;
625 obj.pd.out = &pd_info;
626 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
628 DRV_LOG(DEBUG, "Fail to get PD object info");
634 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
637 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
642 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
643 /* Get environment variable to store. */
644 env = getenv(MLX5_SHUT_UP_BF);
645 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
646 if (config->dbnc == MLX5_ARG_UNSET)
647 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
649 setenv(MLX5_SHUT_UP_BF,
650 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
655 mlx5_restore_doorbell_mapping_env(int value)
657 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
658 /* Restore the original environment variable state. */
659 if (value == MLX5_ARG_UNSET)
660 unsetenv(MLX5_SHUT_UP_BF);
662 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
666 * Install shared asynchronous device events handler.
667 * This function is implemented to support event sharing
668 * between multiple ports of single IB device.
671 * Pointer to mlx5_ibv_shared object.
674 mlx5_dev_shared_handler_install(struct mlx5_ibv_shared *sh)
679 sh->intr_handle.fd = -1;
680 flags = fcntl(sh->ctx->async_fd, F_GETFL);
681 ret = fcntl(sh->ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
683 DRV_LOG(INFO, "failed to change file descriptor async event"
686 sh->intr_handle.fd = sh->ctx->async_fd;
687 sh->intr_handle.type = RTE_INTR_HANDLE_EXT;
688 if (rte_intr_callback_register(&sh->intr_handle,
689 mlx5_dev_interrupt_handler, sh)) {
690 DRV_LOG(INFO, "Fail to install the shared interrupt.");
691 sh->intr_handle.fd = -1;
695 #ifdef HAVE_IBV_DEVX_ASYNC
696 sh->intr_handle_devx.fd = -1;
697 sh->devx_comp = mlx5_glue->devx_create_cmd_comp(sh->ctx);
698 if (!sh->devx_comp) {
699 DRV_LOG(INFO, "failed to allocate devx_comp.");
702 flags = fcntl(sh->devx_comp->fd, F_GETFL);
703 ret = fcntl(sh->devx_comp->fd, F_SETFL, flags | O_NONBLOCK);
705 DRV_LOG(INFO, "failed to change file descriptor"
709 sh->intr_handle_devx.fd = sh->devx_comp->fd;
710 sh->intr_handle_devx.type = RTE_INTR_HANDLE_EXT;
711 if (rte_intr_callback_register(&sh->intr_handle_devx,
712 mlx5_dev_interrupt_handler_devx, sh)) {
713 DRV_LOG(INFO, "Fail to install the devx shared"
715 sh->intr_handle_devx.fd = -1;
717 #endif /* HAVE_IBV_DEVX_ASYNC */
722 * Uninstall shared asynchronous device events handler.
723 * This function is implemented to support event sharing
724 * between multiple ports of single IB device.
727 * Pointer to mlx5_ibv_shared object.
730 mlx5_dev_shared_handler_uninstall(struct mlx5_ibv_shared *sh)
732 if (sh->intr_handle.fd >= 0)
733 mlx5_intr_callback_unregister(&sh->intr_handle,
734 mlx5_dev_interrupt_handler, sh);
735 #ifdef HAVE_IBV_DEVX_ASYNC
736 if (sh->intr_handle_devx.fd >= 0)
737 rte_intr_callback_unregister(&sh->intr_handle_devx,
738 mlx5_dev_interrupt_handler_devx, sh);
740 mlx5_glue->devx_destroy_cmd_comp(sh->devx_comp);
745 * Allocate shared IB device context. If there is multiport device the
746 * master and representors will share this context, if there is single
747 * port dedicated IB device, the context will be used by only given
748 * port due to unification.
750 * Routine first searches the context for the specified IB device name,
751 * if found the shared context assumed and reference counter is incremented.
752 * If no context found the new one is created and initialized with specified
753 * IB device context and parameters.
756 * Pointer to the IB device attributes (name, port, etc).
758 * Pointer to device configuration structure.
761 * Pointer to mlx5_ibv_shared object on success,
762 * otherwise NULL and rte_errno is set.
764 static struct mlx5_ibv_shared *
765 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
766 const struct mlx5_dev_config *config)
768 struct mlx5_ibv_shared *sh;
772 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
773 struct mlx5_devx_tis_attr tis_attr = { 0 };
777 /* Secondary process should not create the shared context. */
778 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
779 pthread_mutex_lock(&mlx5_ibv_list_mutex);
780 /* Search for IB context by device name. */
781 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
782 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
787 /* No device found, we have to create new shared context. */
788 MLX5_ASSERT(spawn->max_port);
789 sh = rte_zmalloc("ethdev shared ib context",
790 sizeof(struct mlx5_ibv_shared) +
792 sizeof(struct mlx5_ibv_shared_port),
793 RTE_CACHE_LINE_SIZE);
795 DRV_LOG(ERR, "shared context allocation failure");
800 * Configure environment variable "MLX5_BF_SHUT_UP"
801 * before the device creation. The rdma_core library
802 * checks the variable at device creation and
803 * stores the result internally.
805 dbmap_env = mlx5_config_doorbell_mapping_env(config);
806 /* Try to open IB device with DV first, then usual Verbs. */
808 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
811 DRV_LOG(DEBUG, "DevX is supported");
812 /* The device is created, no need for environment. */
813 mlx5_restore_doorbell_mapping_env(dbmap_env);
815 /* The environment variable is still configured. */
816 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
817 err = errno ? errno : ENODEV;
819 * The environment variable is not needed anymore,
820 * all device creation attempts are completed.
822 mlx5_restore_doorbell_mapping_env(dbmap_env);
825 DRV_LOG(DEBUG, "DevX is NOT supported");
827 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
829 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
833 sh->max_port = spawn->max_port;
834 strncpy(sh->ibdev_name, sh->ctx->device->name,
835 sizeof(sh->ibdev_name));
836 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
837 sizeof(sh->ibdev_path));
839 * Setting port_id to max unallowed value means
840 * there is no interrupt subhandler installed for
841 * the given port index i.
843 for (i = 0; i < sh->max_port; i++) {
844 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
845 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
847 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
848 if (sh->pd == NULL) {
849 DRV_LOG(ERR, "PD allocation failure");
853 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
855 err = mlx5_get_pdn(sh->pd, &sh->pdn);
857 DRV_LOG(ERR, "Fail to extract pdn from PD");
860 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
862 DRV_LOG(ERR, "TD allocation failure");
866 tis_attr.transport_domain = sh->td->id;
867 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
869 DRV_LOG(ERR, "TIS allocation failure");
874 sh->flow_id_pool = mlx5_flow_id_pool_alloc
875 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
876 if (!sh->flow_id_pool) {
877 DRV_LOG(ERR, "can't create flow id pool");
881 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
883 * Once the device is added to the list of memory event
884 * callback, its global MR cache table cannot be expanded
885 * on the fly because of deadlock. If it overflows, lookup
886 * should be done by searching MR list linearly, which is slow.
888 * At this point the device is not added to the memory
889 * event list yet, context is just being created.
891 err = mlx5_mr_btree_init(&sh->share_cache.cache,
892 MLX5_MR_BTREE_CACHE_N * 2,
893 spawn->pci_dev->device.numa_node);
898 mlx5_dev_shared_handler_install(sh);
899 mlx5_flow_aging_init(sh);
900 mlx5_flow_counters_mng_init(sh);
901 mlx5_flow_ipool_create(sh, config);
902 /* Add device to memory callback list. */
903 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
904 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
906 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
907 /* Add context to the global device list. */
908 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
910 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
913 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
916 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
918 claim_zero(mlx5_devx_cmd_destroy(sh->td));
920 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
922 claim_zero(mlx5_glue->close_device(sh->ctx));
923 if (sh->flow_id_pool)
924 mlx5_flow_id_pool_release(sh->flow_id_pool);
926 MLX5_ASSERT(err > 0);
932 * Free shared IB device context. Decrement counter and if zero free
933 * all allocated resources and close handles.
936 * Pointer to mlx5_ibv_shared object to free
939 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
941 pthread_mutex_lock(&mlx5_ibv_list_mutex);
942 #ifdef RTE_LIBRTE_MLX5_DEBUG
943 /* Check the object presence in the list. */
944 struct mlx5_ibv_shared *lctx;
946 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
951 DRV_LOG(ERR, "Freeing non-existing shared IB context");
956 MLX5_ASSERT(sh->refcnt);
957 /* Secondary process should not free the shared context. */
958 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
961 /* Remove from memory callback device list. */
962 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
963 LIST_REMOVE(sh, mem_event_cb);
964 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
965 /* Release created Memory Regions. */
966 mlx5_mr_release_cache(&sh->share_cache);
967 /* Remove context from the global device list. */
968 LIST_REMOVE(sh, next);
970 * Ensure there is no async event handler installed.
971 * Only primary process handles async device events.
973 mlx5_flow_counters_mng_close(sh);
974 mlx5_flow_ipool_destroy(sh);
975 mlx5_dev_shared_handler_uninstall(sh);
977 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
979 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
981 claim_zero(mlx5_devx_cmd_destroy(sh->td));
983 claim_zero(mlx5_glue->close_device(sh->ctx));
984 if (sh->flow_id_pool)
985 mlx5_flow_id_pool_release(sh->flow_id_pool);
988 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
992 * Destroy table hash list and all the root entries per domain.
995 * Pointer to the private device data structure.
998 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1000 struct mlx5_ibv_shared *sh = priv->sh;
1001 struct mlx5_flow_tbl_data_entry *tbl_data;
1002 union mlx5_flow_tbl_key table_key = {
1010 struct mlx5_hlist_entry *pos;
1014 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1016 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1018 MLX5_ASSERT(tbl_data);
1019 mlx5_hlist_remove(sh->flow_tbls, pos);
1022 table_key.direction = 1;
1023 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1025 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1027 MLX5_ASSERT(tbl_data);
1028 mlx5_hlist_remove(sh->flow_tbls, pos);
1031 table_key.direction = 0;
1032 table_key.domain = 1;
1033 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1035 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1037 MLX5_ASSERT(tbl_data);
1038 mlx5_hlist_remove(sh->flow_tbls, pos);
1041 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1045 * Initialize flow table hash list and create the root tables entry
1049 * Pointer to the private device data structure.
1052 * Zero on success, positive error code otherwise.
1055 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1057 struct mlx5_ibv_shared *sh = priv->sh;
1058 char s[MLX5_HLIST_NAMESIZE];
1062 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1063 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1064 if (!sh->flow_tbls) {
1065 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
1069 #ifndef HAVE_MLX5DV_DR
1071 * In case we have not DR support, the zero tables should be created
1072 * because DV expect to see them even if they cannot be created by
1075 union mlx5_flow_tbl_key table_key = {
1083 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1084 sizeof(*tbl_data), 0);
1090 tbl_data->entry.key = table_key.v64;
1091 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1094 rte_atomic32_init(&tbl_data->tbl.refcnt);
1095 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1096 table_key.direction = 1;
1097 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1102 tbl_data->entry.key = table_key.v64;
1103 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1106 rte_atomic32_init(&tbl_data->tbl.refcnt);
1107 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1108 table_key.direction = 0;
1109 table_key.domain = 1;
1110 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1115 tbl_data->entry.key = table_key.v64;
1116 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1119 rte_atomic32_init(&tbl_data->tbl.refcnt);
1120 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1123 mlx5_free_table_hash_list(priv);
1124 #endif /* HAVE_MLX5DV_DR */
1129 * Initialize DR related data within private structure.
1130 * Routine checks the reference counter and does actual
1131 * resources creation/initialization only if counter is zero.
1134 * Pointer to the private device data structure.
1137 * Zero on success, positive error code otherwise.
1140 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1142 struct mlx5_ibv_shared *sh = priv->sh;
1143 char s[MLX5_HLIST_NAMESIZE];
1147 err = mlx5_alloc_table_hash_list(priv);
1149 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1150 (void *)sh->flow_tbls);
1153 /* Create tags hash list table. */
1154 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1155 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1156 if (!sh->tag_table) {
1157 DRV_LOG(ERR, "tags with hash creation failed.\n");
1161 #ifdef HAVE_MLX5DV_DR
1164 if (sh->dv_refcnt) {
1165 /* Shared DV/DR structures is already initialized. */
1167 priv->dr_shared = 1;
1170 /* Reference counter is zero, we should initialize structures. */
1171 domain = mlx5_glue->dr_create_domain(sh->ctx,
1172 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1174 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1178 sh->rx_domain = domain;
1179 domain = mlx5_glue->dr_create_domain(sh->ctx,
1180 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1182 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1186 pthread_mutex_init(&sh->dv_mutex, NULL);
1187 sh->tx_domain = domain;
1188 #ifdef HAVE_MLX5DV_DR_ESWITCH
1189 if (priv->config.dv_esw_en) {
1190 domain = mlx5_glue->dr_create_domain
1191 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1193 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1197 sh->fdb_domain = domain;
1198 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1201 if (priv->config.reclaim_mode == MLX5_RCM_AGGR) {
1202 mlx5_glue->dr_reclaim_domain_memory(sh->rx_domain, 1);
1203 mlx5_glue->dr_reclaim_domain_memory(sh->tx_domain, 1);
1205 mlx5_glue->dr_reclaim_domain_memory(sh->fdb_domain, 1);
1207 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1208 #endif /* HAVE_MLX5DV_DR */
1210 priv->dr_shared = 1;
1213 /* Rollback the created objects. */
1214 if (sh->rx_domain) {
1215 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1216 sh->rx_domain = NULL;
1218 if (sh->tx_domain) {
1219 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1220 sh->tx_domain = NULL;
1222 if (sh->fdb_domain) {
1223 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1224 sh->fdb_domain = NULL;
1226 if (sh->esw_drop_action) {
1227 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1228 sh->esw_drop_action = NULL;
1230 if (sh->pop_vlan_action) {
1231 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1232 sh->pop_vlan_action = NULL;
1234 if (sh->tag_table) {
1235 /* tags should be destroyed with flow before. */
1236 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1237 sh->tag_table = NULL;
1239 mlx5_free_table_hash_list(priv);
1244 * Destroy DR related data within private structure.
1247 * Pointer to the private device data structure.
1250 mlx5_free_shared_dr(struct mlx5_priv *priv)
1252 struct mlx5_ibv_shared *sh;
1254 if (!priv->dr_shared)
1256 priv->dr_shared = 0;
1259 #ifdef HAVE_MLX5DV_DR
1260 MLX5_ASSERT(sh->dv_refcnt);
1261 if (sh->dv_refcnt && --sh->dv_refcnt)
1263 if (sh->rx_domain) {
1264 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1265 sh->rx_domain = NULL;
1267 if (sh->tx_domain) {
1268 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1269 sh->tx_domain = NULL;
1271 #ifdef HAVE_MLX5DV_DR_ESWITCH
1272 if (sh->fdb_domain) {
1273 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1274 sh->fdb_domain = NULL;
1276 if (sh->esw_drop_action) {
1277 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1278 sh->esw_drop_action = NULL;
1281 if (sh->pop_vlan_action) {
1282 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1283 sh->pop_vlan_action = NULL;
1285 pthread_mutex_destroy(&sh->dv_mutex);
1286 #endif /* HAVE_MLX5DV_DR */
1287 if (sh->tag_table) {
1288 /* tags should be destroyed with flow before. */
1289 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1290 sh->tag_table = NULL;
1292 mlx5_free_table_hash_list(priv);
1296 * Initialize shared data between primary and secondary process.
1298 * A memzone is reserved by primary process and secondary processes attach to
1302 * 0 on success, a negative errno value otherwise and rte_errno is set.
1305 mlx5_init_shared_data(void)
1307 const struct rte_memzone *mz;
1310 rte_spinlock_lock(&mlx5_shared_data_lock);
1311 if (mlx5_shared_data == NULL) {
1312 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1313 /* Allocate shared memory. */
1314 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1315 sizeof(*mlx5_shared_data),
1319 "Cannot allocate mlx5 shared data");
1323 mlx5_shared_data = mz->addr;
1324 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1325 rte_spinlock_init(&mlx5_shared_data->lock);
1327 /* Lookup allocated shared memory. */
1328 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1331 "Cannot attach mlx5 shared data");
1335 mlx5_shared_data = mz->addr;
1336 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1340 rte_spinlock_unlock(&mlx5_shared_data_lock);
1345 * Retrieve integer value from environment variable.
1348 * Environment variable name.
1351 * Integer value, 0 if the variable is not set.
1354 mlx5_getenv_int(const char *name)
1356 const char *val = getenv(name);
1364 * Verbs callback to allocate a memory. This function should allocate the space
1365 * according to the size provided residing inside a huge page.
1366 * Please note that all allocation must respect the alignment from libmlx5
1367 * (i.e. currently sysconf(_SC_PAGESIZE)).
1370 * The size in bytes of the memory to allocate.
1372 * A pointer to the callback data.
1375 * Allocated buffer, NULL otherwise and rte_errno is set.
1378 mlx5_alloc_verbs_buf(size_t size, void *data)
1380 struct mlx5_priv *priv = data;
1382 size_t alignment = sysconf(_SC_PAGESIZE);
1383 unsigned int socket = SOCKET_ID_ANY;
1385 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1386 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1388 socket = ctrl->socket;
1389 } else if (priv->verbs_alloc_ctx.type ==
1390 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1391 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1393 socket = ctrl->socket;
1395 MLX5_ASSERT(data != NULL);
1396 ret = rte_malloc_socket(__func__, size, alignment, socket);
1403 * Verbs callback to free a memory.
1406 * A pointer to the memory to free.
1408 * A pointer to the callback data.
1411 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1413 MLX5_ASSERT(data != NULL);
1418 * DPDK callback to add udp tunnel port
1421 * A pointer to eth_dev
1422 * @param[in] udp_tunnel
1423 * A pointer to udp tunnel
1426 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1429 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1430 struct rte_eth_udp_tunnel *udp_tunnel)
1432 MLX5_ASSERT(udp_tunnel != NULL);
1433 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1434 udp_tunnel->udp_port == 4789)
1436 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1437 udp_tunnel->udp_port == 4790)
1443 * Initialize process private data structure.
1446 * Pointer to Ethernet device structure.
1449 * 0 on success, a negative errno value otherwise and rte_errno is set.
1452 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1454 struct mlx5_priv *priv = dev->data->dev_private;
1455 struct mlx5_proc_priv *ppriv;
1459 * UAR register table follows the process private structure. BlueFlame
1460 * registers for Tx queues are stored in the table.
1463 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1464 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1465 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1470 ppriv->uar_table_sz = ppriv_size;
1471 dev->process_private = ppriv;
1476 * Un-initialize process private data structure.
1479 * Pointer to Ethernet device structure.
1482 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1484 if (!dev->process_private)
1486 rte_free(dev->process_private);
1487 dev->process_private = NULL;
1491 * DPDK callback to close the device.
1493 * Destroy all queues and objects, free memory.
1496 * Pointer to Ethernet device structure.
1499 mlx5_dev_close(struct rte_eth_dev *dev)
1501 struct mlx5_priv *priv = dev->data->dev_private;
1505 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1506 /* Check if process_private released. */
1507 if (!dev->process_private)
1509 mlx5_tx_uar_uninit_secondary(dev);
1510 mlx5_proc_priv_uninit(dev);
1511 rte_eth_dev_release_port(dev);
1516 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1518 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1520 * If default mreg copy action is removed at the stop stage,
1521 * the search will return none and nothing will be done anymore.
1523 mlx5_flow_stop_default(dev);
1524 mlx5_traffic_disable(dev);
1526 * If all the flows are already flushed in the device stop stage,
1527 * then this will return directly without any action.
1529 mlx5_flow_list_flush(dev, &priv->flows, true);
1530 mlx5_flow_meter_flush(dev, NULL);
1531 /* Free the intermediate buffers for flow creation. */
1532 mlx5_flow_free_intermediate(dev);
1533 /* Prevent crashes when queues are still in use. */
1534 dev->rx_pkt_burst = removed_rx_burst;
1535 dev->tx_pkt_burst = removed_tx_burst;
1537 /* Disable datapath on secondary process. */
1538 mlx5_mp_req_stop_rxtx(dev);
1539 if (priv->rxqs != NULL) {
1540 /* XXX race condition if mlx5_rx_burst() is still running. */
1542 for (i = 0; (i != priv->rxqs_n); ++i)
1543 mlx5_rxq_release(dev, i);
1547 if (priv->txqs != NULL) {
1548 /* XXX race condition if mlx5_tx_burst() is still running. */
1550 for (i = 0; (i != priv->txqs_n); ++i)
1551 mlx5_txq_release(dev, i);
1555 mlx5_proc_priv_uninit(dev);
1556 if (priv->mreg_cp_tbl)
1557 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1558 mlx5_mprq_free_mp(dev);
1559 mlx5_free_shared_dr(priv);
1560 if (priv->rss_conf.rss_key != NULL)
1561 rte_free(priv->rss_conf.rss_key);
1562 if (priv->reta_idx != NULL)
1563 rte_free(priv->reta_idx);
1564 if (priv->config.vf)
1565 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1566 dev->data->mac_addrs,
1567 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1568 if (priv->nl_socket_route >= 0)
1569 close(priv->nl_socket_route);
1570 if (priv->nl_socket_rdma >= 0)
1571 close(priv->nl_socket_rdma);
1572 if (priv->vmwa_context)
1573 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1574 ret = mlx5_hrxq_verify(dev);
1576 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1577 dev->data->port_id);
1578 ret = mlx5_ind_table_obj_verify(dev);
1580 DRV_LOG(WARNING, "port %u some indirection table still remain",
1581 dev->data->port_id);
1582 ret = mlx5_rxq_obj_verify(dev);
1584 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1585 dev->data->port_id);
1586 ret = mlx5_rxq_verify(dev);
1588 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1589 dev->data->port_id);
1590 ret = mlx5_txq_obj_verify(dev);
1592 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1593 dev->data->port_id);
1594 ret = mlx5_txq_verify(dev);
1596 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1597 dev->data->port_id);
1598 ret = mlx5_flow_verify(dev);
1600 DRV_LOG(WARNING, "port %u some flows still remain",
1601 dev->data->port_id);
1603 * Free the shared context in last turn, because the cleanup
1604 * routines above may use some shared fields, like
1605 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1606 * ifindex if Netlink fails.
1608 mlx5_free_shared_ibctx(priv->sh);
1609 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1613 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1614 struct mlx5_priv *opriv =
1615 rte_eth_devices[port_id].data->dev_private;
1618 opriv->domain_id != priv->domain_id ||
1619 &rte_eth_devices[port_id] == dev)
1625 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1627 memset(priv, 0, sizeof(*priv));
1628 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1630 * Reset mac_addrs to NULL such that it is not freed as part of
1631 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1632 * it is freed when dev_private is freed.
1634 dev->data->mac_addrs = NULL;
1637 const struct eth_dev_ops mlx5_dev_ops = {
1638 .dev_configure = mlx5_dev_configure,
1639 .dev_start = mlx5_dev_start,
1640 .dev_stop = mlx5_dev_stop,
1641 .dev_set_link_down = mlx5_set_link_down,
1642 .dev_set_link_up = mlx5_set_link_up,
1643 .dev_close = mlx5_dev_close,
1644 .promiscuous_enable = mlx5_promiscuous_enable,
1645 .promiscuous_disable = mlx5_promiscuous_disable,
1646 .allmulticast_enable = mlx5_allmulticast_enable,
1647 .allmulticast_disable = mlx5_allmulticast_disable,
1648 .link_update = mlx5_link_update,
1649 .stats_get = mlx5_stats_get,
1650 .stats_reset = mlx5_stats_reset,
1651 .xstats_get = mlx5_xstats_get,
1652 .xstats_reset = mlx5_xstats_reset,
1653 .xstats_get_names = mlx5_xstats_get_names,
1654 .fw_version_get = mlx5_fw_version_get,
1655 .dev_infos_get = mlx5_dev_infos_get,
1656 .read_clock = mlx5_read_clock,
1657 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1658 .vlan_filter_set = mlx5_vlan_filter_set,
1659 .rx_queue_setup = mlx5_rx_queue_setup,
1660 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1661 .tx_queue_setup = mlx5_tx_queue_setup,
1662 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1663 .rx_queue_release = mlx5_rx_queue_release,
1664 .tx_queue_release = mlx5_tx_queue_release,
1665 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1666 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1667 .mac_addr_remove = mlx5_mac_addr_remove,
1668 .mac_addr_add = mlx5_mac_addr_add,
1669 .mac_addr_set = mlx5_mac_addr_set,
1670 .set_mc_addr_list = mlx5_set_mc_addr_list,
1671 .mtu_set = mlx5_dev_set_mtu,
1672 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1673 .vlan_offload_set = mlx5_vlan_offload_set,
1674 .reta_update = mlx5_dev_rss_reta_update,
1675 .reta_query = mlx5_dev_rss_reta_query,
1676 .rss_hash_update = mlx5_rss_hash_update,
1677 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1678 .filter_ctrl = mlx5_dev_filter_ctrl,
1679 .rx_descriptor_status = mlx5_rx_descriptor_status,
1680 .tx_descriptor_status = mlx5_tx_descriptor_status,
1681 .rxq_info_get = mlx5_rxq_info_get,
1682 .txq_info_get = mlx5_txq_info_get,
1683 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1684 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1685 .rx_queue_count = mlx5_rx_queue_count,
1686 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1687 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1688 .is_removed = mlx5_is_removed,
1689 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1690 .get_module_info = mlx5_get_module_info,
1691 .get_module_eeprom = mlx5_get_module_eeprom,
1692 .hairpin_cap_get = mlx5_hairpin_cap_get,
1693 .mtr_ops_get = mlx5_flow_meter_ops_get,
1696 /* Available operations from secondary process. */
1697 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1698 .stats_get = mlx5_stats_get,
1699 .stats_reset = mlx5_stats_reset,
1700 .xstats_get = mlx5_xstats_get,
1701 .xstats_reset = mlx5_xstats_reset,
1702 .xstats_get_names = mlx5_xstats_get_names,
1703 .fw_version_get = mlx5_fw_version_get,
1704 .dev_infos_get = mlx5_dev_infos_get,
1705 .rx_descriptor_status = mlx5_rx_descriptor_status,
1706 .tx_descriptor_status = mlx5_tx_descriptor_status,
1707 .rxq_info_get = mlx5_rxq_info_get,
1708 .txq_info_get = mlx5_txq_info_get,
1709 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1710 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1711 .get_module_info = mlx5_get_module_info,
1712 .get_module_eeprom = mlx5_get_module_eeprom,
1715 /* Available operations in flow isolated mode. */
1716 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1717 .dev_configure = mlx5_dev_configure,
1718 .dev_start = mlx5_dev_start,
1719 .dev_stop = mlx5_dev_stop,
1720 .dev_set_link_down = mlx5_set_link_down,
1721 .dev_set_link_up = mlx5_set_link_up,
1722 .dev_close = mlx5_dev_close,
1723 .promiscuous_enable = mlx5_promiscuous_enable,
1724 .promiscuous_disable = mlx5_promiscuous_disable,
1725 .allmulticast_enable = mlx5_allmulticast_enable,
1726 .allmulticast_disable = mlx5_allmulticast_disable,
1727 .link_update = mlx5_link_update,
1728 .stats_get = mlx5_stats_get,
1729 .stats_reset = mlx5_stats_reset,
1730 .xstats_get = mlx5_xstats_get,
1731 .xstats_reset = mlx5_xstats_reset,
1732 .xstats_get_names = mlx5_xstats_get_names,
1733 .fw_version_get = mlx5_fw_version_get,
1734 .dev_infos_get = mlx5_dev_infos_get,
1735 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1736 .vlan_filter_set = mlx5_vlan_filter_set,
1737 .rx_queue_setup = mlx5_rx_queue_setup,
1738 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1739 .tx_queue_setup = mlx5_tx_queue_setup,
1740 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1741 .rx_queue_release = mlx5_rx_queue_release,
1742 .tx_queue_release = mlx5_tx_queue_release,
1743 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1744 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1745 .mac_addr_remove = mlx5_mac_addr_remove,
1746 .mac_addr_add = mlx5_mac_addr_add,
1747 .mac_addr_set = mlx5_mac_addr_set,
1748 .set_mc_addr_list = mlx5_set_mc_addr_list,
1749 .mtu_set = mlx5_dev_set_mtu,
1750 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1751 .vlan_offload_set = mlx5_vlan_offload_set,
1752 .filter_ctrl = mlx5_dev_filter_ctrl,
1753 .rx_descriptor_status = mlx5_rx_descriptor_status,
1754 .tx_descriptor_status = mlx5_tx_descriptor_status,
1755 .rxq_info_get = mlx5_rxq_info_get,
1756 .txq_info_get = mlx5_txq_info_get,
1757 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1758 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1759 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1760 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1761 .is_removed = mlx5_is_removed,
1762 .get_module_info = mlx5_get_module_info,
1763 .get_module_eeprom = mlx5_get_module_eeprom,
1764 .hairpin_cap_get = mlx5_hairpin_cap_get,
1765 .mtr_ops_get = mlx5_flow_meter_ops_get,
1769 * Verify and store value for device argument.
1772 * Key argument to verify.
1774 * Value associated with key.
1779 * 0 on success, a negative errno value otherwise and rte_errno is set.
1782 mlx5_args_check(const char *key, const char *val, void *opaque)
1784 struct mlx5_dev_config *config = opaque;
1787 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1788 if (!strcmp(MLX5_REPRESENTOR, key))
1791 tmp = strtoul(val, NULL, 0);
1794 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1797 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1798 config->cqe_comp = !!tmp;
1799 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1800 config->cqe_pad = !!tmp;
1801 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1802 config->hw_padding = !!tmp;
1803 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1804 config->mprq.enabled = !!tmp;
1805 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1806 config->mprq.stride_num_n = tmp;
1807 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1808 config->mprq.stride_size_n = tmp;
1809 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1810 config->mprq.max_memcpy_len = tmp;
1811 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1812 config->mprq.min_rxqs_num = tmp;
1813 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1814 DRV_LOG(WARNING, "%s: deprecated parameter,"
1815 " converted to txq_inline_max", key);
1816 config->txq_inline_max = tmp;
1817 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1818 config->txq_inline_max = tmp;
1819 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1820 config->txq_inline_min = tmp;
1821 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1822 config->txq_inline_mpw = tmp;
1823 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1824 config->txqs_inline = tmp;
1825 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1826 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1827 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1828 config->mps = !!tmp;
1829 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1830 if (tmp != MLX5_TXDB_CACHED &&
1831 tmp != MLX5_TXDB_NCACHED &&
1832 tmp != MLX5_TXDB_HEURISTIC) {
1833 DRV_LOG(ERR, "invalid Tx doorbell "
1834 "mapping parameter");
1839 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1840 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1841 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1842 DRV_LOG(WARNING, "%s: deprecated parameter,"
1843 " converted to txq_inline_mpw", key);
1844 config->txq_inline_mpw = tmp;
1845 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1846 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1847 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1848 config->rx_vec_en = !!tmp;
1849 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1850 config->l3_vxlan_en = !!tmp;
1851 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1852 config->vf_nl_en = !!tmp;
1853 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1854 config->dv_esw_en = !!tmp;
1855 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1856 config->dv_flow_en = !!tmp;
1857 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1858 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1859 tmp != MLX5_XMETA_MODE_META16 &&
1860 tmp != MLX5_XMETA_MODE_META32) {
1861 DRV_LOG(ERR, "invalid extensive "
1862 "metadata parameter");
1866 config->dv_xmeta_en = tmp;
1867 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1868 config->mr_ext_memseg_en = !!tmp;
1869 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1870 config->max_dump_files_num = tmp;
1871 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1872 config->lro.timeout = tmp;
1873 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1874 DRV_LOG(DEBUG, "class argument is %s.", val);
1875 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1876 config->log_hp_size = tmp;
1877 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1878 if (tmp != MLX5_RCM_NONE &&
1879 tmp != MLX5_RCM_LIGHT &&
1880 tmp != MLX5_RCM_AGGR) {
1881 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1885 config->reclaim_mode = tmp;
1887 DRV_LOG(WARNING, "%s: unknown parameter", key);
1895 * Parse device parameters.
1898 * Pointer to device configuration structure.
1900 * Device arguments structure.
1903 * 0 on success, a negative errno value otherwise and rte_errno is set.
1906 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1908 const char **params = (const char *[]){
1909 MLX5_RXQ_CQE_COMP_EN,
1910 MLX5_RXQ_CQE_PAD_EN,
1911 MLX5_RXQ_PKT_PAD_EN,
1913 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1914 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1915 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1918 MLX5_TXQ_INLINE_MIN,
1919 MLX5_TXQ_INLINE_MAX,
1920 MLX5_TXQ_INLINE_MPW,
1921 MLX5_TXQS_MIN_INLINE,
1924 MLX5_TXQ_MPW_HDR_DSEG_EN,
1925 MLX5_TXQ_MAX_INLINE_LEN,
1934 MLX5_MR_EXT_MEMSEG_EN,
1936 MLX5_MAX_DUMP_FILES_NUM,
1937 MLX5_LRO_TIMEOUT_USEC,
1938 MLX5_CLASS_ARG_NAME,
1943 struct rte_kvargs *kvlist;
1947 if (devargs == NULL)
1949 /* Following UGLY cast is done to pass checkpatch. */
1950 kvlist = rte_kvargs_parse(devargs->args, params);
1951 if (kvlist == NULL) {
1955 /* Process parameters. */
1956 for (i = 0; (params[i] != NULL); ++i) {
1957 if (rte_kvargs_count(kvlist, params[i])) {
1958 ret = rte_kvargs_process(kvlist, params[i],
1959 mlx5_args_check, config);
1962 rte_kvargs_free(kvlist);
1967 rte_kvargs_free(kvlist);
1971 static struct rte_pci_driver mlx5_driver;
1974 * PMD global initialization.
1976 * Independent from individual device, this function initializes global
1977 * per-PMD data structures distinguishing primary and secondary processes.
1978 * Hence, each initialization is called once per a process.
1981 * 0 on success, a negative errno value otherwise and rte_errno is set.
1984 mlx5_init_once(void)
1986 struct mlx5_shared_data *sd;
1987 struct mlx5_local_data *ld = &mlx5_local_data;
1990 if (mlx5_init_shared_data())
1992 sd = mlx5_shared_data;
1994 rte_spinlock_lock(&sd->lock);
1995 switch (rte_eal_process_type()) {
1996 case RTE_PROC_PRIMARY:
1999 LIST_INIT(&sd->mem_event_cb_list);
2000 rte_rwlock_init(&sd->mem_event_rwlock);
2001 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
2002 mlx5_mr_mem_event_cb, NULL);
2003 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
2004 mlx5_mp_primary_handle);
2007 sd->init_done = true;
2009 case RTE_PROC_SECONDARY:
2012 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
2013 mlx5_mp_secondary_handle);
2016 ++sd->secondary_cnt;
2017 ld->init_done = true;
2023 rte_spinlock_unlock(&sd->lock);
2028 * Configures the minimal amount of data to inline into WQE
2029 * while sending packets.
2031 * - the txq_inline_min has the maximal priority, if this
2032 * key is specified in devargs
2033 * - if DevX is enabled the inline mode is queried from the
2034 * device (HCA attributes and NIC vport context if needed).
2035 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2036 * and none (0 bytes) for other NICs
2039 * Verbs device parameters (name, port, switch_info) to spawn.
2041 * Device configuration parameters.
2044 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2045 struct mlx5_dev_config *config)
2047 if (config->txq_inline_min != MLX5_ARG_UNSET) {
2048 /* Application defines size of inlined data explicitly. */
2049 switch (spawn->pci_dev->id.device_id) {
2050 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2051 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2052 if (config->txq_inline_min <
2053 (int)MLX5_INLINE_HSIZE_L2) {
2055 "txq_inline_mix aligned to minimal"
2056 " ConnectX-4 required value %d",
2057 (int)MLX5_INLINE_HSIZE_L2);
2058 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2064 if (config->hca_attr.eth_net_offloads) {
2065 /* We have DevX enabled, inline mode queried successfully. */
2066 switch (config->hca_attr.wqe_inline_mode) {
2067 case MLX5_CAP_INLINE_MODE_L2:
2068 /* outer L2 header must be inlined. */
2069 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2071 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2072 /* No inline data are required by NIC. */
2073 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2074 config->hw_vlan_insert =
2075 config->hca_attr.wqe_vlan_insert;
2076 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2078 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2079 /* inline mode is defined by NIC vport context. */
2080 if (!config->hca_attr.eth_virt)
2082 switch (config->hca_attr.vport_inline_mode) {
2083 case MLX5_INLINE_MODE_NONE:
2084 config->txq_inline_min =
2085 MLX5_INLINE_HSIZE_NONE;
2087 case MLX5_INLINE_MODE_L2:
2088 config->txq_inline_min =
2089 MLX5_INLINE_HSIZE_L2;
2091 case MLX5_INLINE_MODE_IP:
2092 config->txq_inline_min =
2093 MLX5_INLINE_HSIZE_L3;
2095 case MLX5_INLINE_MODE_TCP_UDP:
2096 config->txq_inline_min =
2097 MLX5_INLINE_HSIZE_L4;
2099 case MLX5_INLINE_MODE_INNER_L2:
2100 config->txq_inline_min =
2101 MLX5_INLINE_HSIZE_INNER_L2;
2103 case MLX5_INLINE_MODE_INNER_IP:
2104 config->txq_inline_min =
2105 MLX5_INLINE_HSIZE_INNER_L3;
2107 case MLX5_INLINE_MODE_INNER_TCP_UDP:
2108 config->txq_inline_min =
2109 MLX5_INLINE_HSIZE_INNER_L4;
2115 * We get here if we are unable to deduce
2116 * inline data size with DevX. Try PCI ID
2117 * to determine old NICs.
2119 switch (spawn->pci_dev->id.device_id) {
2120 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2121 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2122 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2123 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2124 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2125 config->hw_vlan_insert = 0;
2127 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2128 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2129 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2130 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2132 * These NICs support VLAN insertion from WQE and
2133 * report the wqe_vlan_insert flag. But there is the bug
2134 * and PFC control may be broken, so disable feature.
2136 config->hw_vlan_insert = 0;
2137 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2140 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2144 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2148 * Configures the metadata mask fields in the shared context.
2151 * Pointer to Ethernet device.
2154 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2156 struct mlx5_priv *priv = dev->data->dev_private;
2157 struct mlx5_ibv_shared *sh = priv->sh;
2158 uint32_t meta, mark, reg_c0;
2160 reg_c0 = ~priv->vport_meta_mask;
2161 switch (priv->config.dv_xmeta_en) {
2162 case MLX5_XMETA_MODE_LEGACY:
2164 mark = MLX5_FLOW_MARK_MASK;
2166 case MLX5_XMETA_MODE_META16:
2167 meta = reg_c0 >> rte_bsf32(reg_c0);
2168 mark = MLX5_FLOW_MARK_MASK;
2170 case MLX5_XMETA_MODE_META32:
2172 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2180 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2181 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2182 sh->dv_mark_mask, mark);
2184 sh->dv_mark_mask = mark;
2185 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2186 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2187 sh->dv_meta_mask, meta);
2189 sh->dv_meta_mask = meta;
2190 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2191 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2192 sh->dv_meta_mask, reg_c0);
2194 sh->dv_regc0_mask = reg_c0;
2195 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2196 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2197 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2198 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2202 * Allocate page of door-bells and register it using DevX API.
2205 * Pointer to Ethernet device.
2208 * Pointer to new page on success, NULL otherwise.
2210 static struct mlx5_devx_dbr_page *
2211 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2213 struct mlx5_priv *priv = dev->data->dev_private;
2214 struct mlx5_devx_dbr_page *page;
2216 /* Allocate space for door-bell page and management data. */
2217 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2218 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2220 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2221 dev->data->port_id);
2224 /* Register allocated memory. */
2225 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2226 MLX5_DBR_PAGE_SIZE, 0);
2228 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2229 dev->data->port_id);
2237 * Find the next available door-bell, allocate new page if needed.
2240 * Pointer to Ethernet device.
2241 * @param [out] dbr_page
2242 * Door-bell page containing the page data.
2245 * Door-bell address offset on success, a negative error value otherwise.
2248 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2250 struct mlx5_priv *priv = dev->data->dev_private;
2251 struct mlx5_devx_dbr_page *page = NULL;
2254 LIST_FOREACH(page, &priv->dbrpgs, next)
2255 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2257 if (!page) { /* No page with free door-bell exists. */
2258 page = mlx5_alloc_dbr_page(dev);
2259 if (!page) /* Failed to allocate new page. */
2261 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2263 /* Loop to find bitmap part with clear bit. */
2265 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2268 /* Find the first clear bit. */
2269 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
2270 j = rte_bsf64(~page->dbr_bitmap[i]);
2271 page->dbr_bitmap[i] |= (UINT64_C(1) << j);
2274 return (((i * 64) + j) * sizeof(uint64_t));
2278 * Release a door-bell record.
2281 * Pointer to Ethernet device.
2282 * @param [in] umem_id
2283 * UMEM ID of page containing the door-bell record to release.
2284 * @param [in] offset
2285 * Offset of door-bell record in page.
2288 * 0 on success, a negative error value otherwise.
2291 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2293 struct mlx5_priv *priv = dev->data->dev_private;
2294 struct mlx5_devx_dbr_page *page = NULL;
2297 LIST_FOREACH(page, &priv->dbrpgs, next)
2298 /* Find the page this address belongs to. */
2299 if (page->umem->umem_id == umem_id)
2304 if (!page->dbr_count) {
2305 /* Page not used, free it and remove from list. */
2306 LIST_REMOVE(page, next);
2308 ret = -mlx5_glue->devx_umem_dereg(page->umem);
2311 /* Mark in bitmap that this door-bell is not in use. */
2312 offset /= MLX5_DBR_SIZE;
2313 int i = offset / 64;
2314 int j = offset % 64;
2316 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
2322 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2324 static const char *const dynf_names[] = {
2325 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2326 RTE_MBUF_DYNFLAG_METADATA_NAME
2330 if (n < RTE_DIM(dynf_names))
2332 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2333 if (names[i] == NULL)
2335 strcpy(names[i], dynf_names[i]);
2337 return RTE_DIM(dynf_names);
2341 * Check sibling device configurations.
2343 * Sibling devices sharing the Infiniband device context
2344 * should have compatible configurations. This regards
2345 * representors and bonding slaves.
2348 * Private device descriptor.
2350 * Configuration of the device is going to be created.
2353 * 0 on success, EINVAL otherwise
2356 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2357 struct mlx5_dev_config *config)
2359 struct mlx5_ibv_shared *sh = priv->sh;
2360 struct mlx5_dev_config *sh_conf = NULL;
2364 /* Nothing to compare for the single/first device. */
2365 if (sh->refcnt == 1)
2367 /* Find the device with shared context. */
2368 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2369 struct mlx5_priv *opriv =
2370 rte_eth_devices[port_id].data->dev_private;
2372 if (opriv && opriv != priv && opriv->sh == sh) {
2373 sh_conf = &opriv->config;
2379 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2380 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2381 " for shared %s context", sh->ibdev_name);
2385 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2386 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2387 " for shared %s context", sh->ibdev_name);
2394 * Spawn an Ethernet device from Verbs information.
2397 * Backing DPDK device.
2399 * Verbs device parameters (name, port, switch_info) to spawn.
2401 * Device configuration parameters.
2404 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2405 * is set. The following errors are defined:
2407 * EBUSY: device is not supposed to be spawned.
2408 * EEXIST: device is already spawned
2410 static struct rte_eth_dev *
2411 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2412 struct mlx5_dev_spawn_data *spawn,
2413 struct mlx5_dev_config config)
2415 const struct mlx5_switch_info *switch_info = &spawn->info;
2416 struct mlx5_ibv_shared *sh = NULL;
2417 struct ibv_port_attr port_attr;
2418 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2419 struct rte_eth_dev *eth_dev = NULL;
2420 struct mlx5_priv *priv = NULL;
2422 unsigned int hw_padding = 0;
2424 unsigned int cqe_comp;
2425 unsigned int cqe_pad = 0;
2426 unsigned int tunnel_en = 0;
2427 unsigned int mpls_en = 0;
2428 unsigned int swp = 0;
2429 unsigned int mprq = 0;
2430 unsigned int mprq_min_stride_size_n = 0;
2431 unsigned int mprq_max_stride_size_n = 0;
2432 unsigned int mprq_min_stride_num_n = 0;
2433 unsigned int mprq_max_stride_num_n = 0;
2434 struct rte_ether_addr mac;
2435 char name[RTE_ETH_NAME_MAX_LEN];
2436 int own_domain_id = 0;
2439 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2440 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2443 /* Determine if this port representor is supposed to be spawned. */
2444 if (switch_info->representor && dpdk_dev->devargs) {
2445 struct rte_eth_devargs eth_da;
2447 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2450 DRV_LOG(ERR, "failed to process device arguments: %s",
2451 strerror(rte_errno));
2454 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2455 if (eth_da.representor_ports[i] ==
2456 (uint16_t)switch_info->port_name)
2458 if (i == eth_da.nb_representor_ports) {
2463 /* Build device name. */
2464 if (spawn->pf_bond < 0) {
2465 /* Single device. */
2466 if (!switch_info->representor)
2467 strlcpy(name, dpdk_dev->name, sizeof(name));
2469 snprintf(name, sizeof(name), "%s_representor_%u",
2470 dpdk_dev->name, switch_info->port_name);
2472 /* Bonding device. */
2473 if (!switch_info->representor)
2474 snprintf(name, sizeof(name), "%s_%s",
2475 dpdk_dev->name, spawn->ibv_dev->name);
2477 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2478 dpdk_dev->name, spawn->ibv_dev->name,
2479 switch_info->port_name);
2481 /* check if the device is already spawned */
2482 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2486 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2487 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2488 struct mlx5_mp_id mp_id;
2490 eth_dev = rte_eth_dev_attach_secondary(name);
2491 if (eth_dev == NULL) {
2492 DRV_LOG(ERR, "can not attach rte ethdev");
2496 eth_dev->device = dpdk_dev;
2497 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2498 err = mlx5_proc_priv_init(eth_dev);
2501 mp_id.port_id = eth_dev->data->port_id;
2502 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2503 /* Receive command fd from primary process */
2504 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2507 /* Remap UAR for Tx queues. */
2508 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2512 * Ethdev pointer is still required as input since
2513 * the primary device is not accessible from the
2514 * secondary process.
2516 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2517 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2520 mlx5_dev_close(eth_dev);
2524 * Some parameters ("tx_db_nc" in particularly) are needed in
2525 * advance to create dv/verbs device context. We proceed the
2526 * devargs here to get ones, and later proceed devargs again
2527 * to override some hardware settings.
2529 err = mlx5_args(&config, dpdk_dev->devargs);
2532 DRV_LOG(ERR, "failed to process device arguments: %s",
2533 strerror(rte_errno));
2536 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2539 config.devx = sh->devx;
2540 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2541 config.dest_tir = 1;
2543 #ifdef HAVE_IBV_MLX5_MOD_SWP
2544 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2547 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2548 * as all ConnectX-5 devices.
2550 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2551 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2553 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2554 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2556 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2557 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2558 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2559 DRV_LOG(DEBUG, "enhanced MPW is supported");
2560 mps = MLX5_MPW_ENHANCED;
2562 DRV_LOG(DEBUG, "MPW is supported");
2566 DRV_LOG(DEBUG, "MPW isn't supported");
2567 mps = MLX5_MPW_DISABLED;
2569 #ifdef HAVE_IBV_MLX5_MOD_SWP
2570 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2571 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2572 DRV_LOG(DEBUG, "SWP support: %u", swp);
2575 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2576 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2577 struct mlx5dv_striding_rq_caps mprq_caps =
2578 dv_attr.striding_rq_caps;
2580 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2581 mprq_caps.min_single_stride_log_num_of_bytes);
2582 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2583 mprq_caps.max_single_stride_log_num_of_bytes);
2584 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2585 mprq_caps.min_single_wqe_log_num_of_strides);
2586 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2587 mprq_caps.max_single_wqe_log_num_of_strides);
2588 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2589 mprq_caps.supported_qpts);
2590 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2592 mprq_min_stride_size_n =
2593 mprq_caps.min_single_stride_log_num_of_bytes;
2594 mprq_max_stride_size_n =
2595 mprq_caps.max_single_stride_log_num_of_bytes;
2596 mprq_min_stride_num_n =
2597 mprq_caps.min_single_wqe_log_num_of_strides;
2598 mprq_max_stride_num_n =
2599 mprq_caps.max_single_wqe_log_num_of_strides;
2602 if (RTE_CACHE_LINE_SIZE == 128 &&
2603 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2607 config.cqe_comp = cqe_comp;
2608 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2609 /* Whether device supports 128B Rx CQE padding. */
2610 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2611 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2613 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2614 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2615 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2616 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2617 (dv_attr.tunnel_offloads_caps &
2618 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2619 (dv_attr.tunnel_offloads_caps &
2620 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2622 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2623 tunnel_en ? "" : "not ");
2626 "tunnel offloading disabled due to old OFED/rdma-core version");
2628 config.tunnel_en = tunnel_en;
2629 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2630 mpls_en = ((dv_attr.tunnel_offloads_caps &
2631 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2632 (dv_attr.tunnel_offloads_caps &
2633 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2634 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2635 mpls_en ? "" : "not ");
2637 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2638 " old OFED/rdma-core version or firmware configuration");
2640 config.mpls_en = mpls_en;
2641 /* Check port status. */
2642 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2644 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2647 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2648 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2652 if (port_attr.state != IBV_PORT_ACTIVE)
2653 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2654 mlx5_glue->port_state_str(port_attr.state),
2656 /* Allocate private eth device data. */
2657 priv = rte_zmalloc("ethdev private structure",
2659 RTE_CACHE_LINE_SIZE);
2661 DRV_LOG(ERR, "priv allocation failure");
2666 priv->ibv_port = spawn->ibv_port;
2667 priv->pci_dev = spawn->pci_dev;
2668 priv->mtu = RTE_ETHER_MTU;
2669 priv->mp_id.port_id = port_id;
2670 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2672 /* Initialize UAR access locks for 32bit implementations. */
2673 rte_spinlock_init(&priv->uar_lock_cq);
2674 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2675 rte_spinlock_init(&priv->uar_lock[i]);
2677 /* Some internal functions rely on Netlink sockets, open them now. */
2678 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2679 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2680 priv->representor = !!switch_info->representor;
2681 priv->master = !!switch_info->master;
2682 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2683 priv->vport_meta_tag = 0;
2684 priv->vport_meta_mask = 0;
2685 priv->pf_bond = spawn->pf_bond;
2686 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2688 * The DevX port query API is implemented. E-Switch may use
2689 * either vport or reg_c[0] metadata register to match on
2690 * vport index. The engaged part of metadata register is
2693 if (switch_info->representor || switch_info->master) {
2694 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2695 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2696 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2700 "can't query devx port %d on device %s",
2701 spawn->ibv_port, spawn->ibv_dev->name);
2702 devx_port.comp_mask = 0;
2705 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2706 priv->vport_meta_tag = devx_port.reg_c_0.value;
2707 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2708 if (!priv->vport_meta_mask) {
2709 DRV_LOG(ERR, "vport zero mask for port %d"
2710 " on bonding device %s",
2711 spawn->ibv_port, spawn->ibv_dev->name);
2715 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2716 DRV_LOG(ERR, "invalid vport tag for port %d"
2717 " on bonding device %s",
2718 spawn->ibv_port, spawn->ibv_dev->name);
2723 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2724 priv->vport_id = devx_port.vport_num;
2725 } else if (spawn->pf_bond >= 0) {
2726 DRV_LOG(ERR, "can't deduce vport index for port %d"
2727 " on bonding device %s",
2728 spawn->ibv_port, spawn->ibv_dev->name);
2732 /* Suppose vport index in compatible way. */
2733 priv->vport_id = switch_info->representor ?
2734 switch_info->port_name + 1 : -1;
2738 * Kernel/rdma_core support single E-Switch per PF configurations
2739 * only and vport_id field contains the vport index for
2740 * associated VF, which is deduced from representor port name.
2741 * For example, let's have the IB device port 10, it has
2742 * attached network device eth0, which has port name attribute
2743 * pf0vf2, we can deduce the VF number as 2, and set vport index
2744 * as 3 (2+1). This assigning schema should be changed if the
2745 * multiple E-Switch instances per PF configurations or/and PCI
2746 * subfunctions are added.
2748 priv->vport_id = switch_info->representor ?
2749 switch_info->port_name + 1 : -1;
2751 /* representor_id field keeps the unmodified VF index. */
2752 priv->representor_id = switch_info->representor ?
2753 switch_info->port_name : -1;
2755 * Look for sibling devices in order to reuse their switch domain
2756 * if any, otherwise allocate one.
2758 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2759 const struct mlx5_priv *opriv =
2760 rte_eth_devices[port_id].data->dev_private;
2763 opriv->sh != priv->sh ||
2765 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2767 priv->domain_id = opriv->domain_id;
2770 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2771 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2774 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2775 strerror(rte_errno));
2780 /* Override some values set by hardware configuration. */
2781 mlx5_args(&config, dpdk_dev->devargs);
2782 err = mlx5_dev_check_sibling_config(priv, &config);
2785 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2786 IBV_DEVICE_RAW_IP_CSUM);
2787 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2788 (config.hw_csum ? "" : "not "));
2789 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2790 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2791 DRV_LOG(DEBUG, "counters are not supported");
2793 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2794 if (config.dv_flow_en) {
2795 DRV_LOG(WARNING, "DV flow is not supported");
2796 config.dv_flow_en = 0;
2799 config.ind_table_max_size =
2800 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2802 * Remove this check once DPDK supports larger/variable
2803 * indirection tables.
2805 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2806 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2807 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2808 config.ind_table_max_size);
2809 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2810 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2811 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2812 (config.hw_vlan_strip ? "" : "not "));
2813 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2814 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2815 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2816 (config.hw_fcs_strip ? "" : "not "));
2817 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2818 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2819 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2820 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2821 IBV_DEVICE_PCI_WRITE_END_PADDING);
2823 if (config.hw_padding && !hw_padding) {
2824 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2825 config.hw_padding = 0;
2826 } else if (config.hw_padding) {
2827 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2829 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2830 (sh->device_attr.tso_caps.supported_qpts &
2831 (1 << IBV_QPT_RAW_PACKET)));
2833 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2835 * MPW is disabled by default, while the Enhanced MPW is enabled
2838 if (config.mps == MLX5_ARG_UNSET)
2839 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2842 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2843 DRV_LOG(INFO, "%sMPS is %s",
2844 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2845 config.mps == MLX5_MPW ? "legacy " : "",
2846 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2847 if (config.cqe_comp && !cqe_comp) {
2848 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2849 config.cqe_comp = 0;
2851 if (config.cqe_pad && !cqe_pad) {
2852 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2854 } else if (config.cqe_pad) {
2855 DRV_LOG(INFO, "Rx CQE padding is enabled");
2858 priv->counter_fallback = 0;
2859 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2864 if (!config.hca_attr.flow_counters_dump)
2865 priv->counter_fallback = 1;
2866 #ifndef HAVE_IBV_DEVX_ASYNC
2867 priv->counter_fallback = 1;
2869 if (priv->counter_fallback)
2870 DRV_LOG(INFO, "Use fall-back DV counter management");
2871 /* Check for LRO support. */
2872 if (config.dest_tir && config.hca_attr.lro_cap &&
2873 config.dv_flow_en) {
2874 /* TBD check tunnel lro caps. */
2875 config.lro.supported = config.hca_attr.lro_cap;
2876 DRV_LOG(DEBUG, "Device supports LRO");
2878 * If LRO timeout is not configured by application,
2879 * use the minimal supported value.
2881 if (!config.lro.timeout)
2882 config.lro.timeout =
2883 config.hca_attr.lro_timer_supported_periods[0];
2884 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2885 config.lro.timeout);
2887 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2888 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2889 config.dv_flow_en) {
2890 uint8_t reg_c_mask =
2891 config.hca_attr.qos.flow_meter_reg_c_ids;
2893 * Meter needs two REG_C's for color match and pre-sfx
2894 * flow match. Here get the REG_C for color match.
2895 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2898 if (__builtin_popcount(reg_c_mask) < 1) {
2900 DRV_LOG(WARNING, "No available register for"
2903 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2906 priv->mtr_reg_share =
2907 config.hca_attr.qos.flow_meter_reg_share;
2908 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2909 priv->mtr_color_reg);
2914 if (config.mprq.enabled && mprq) {
2915 if (config.mprq.stride_num_n &&
2916 (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2917 config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2918 config.mprq.stride_num_n =
2919 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2920 mprq_min_stride_num_n),
2921 mprq_max_stride_num_n);
2923 "the number of strides"
2924 " for Multi-Packet RQ is out of range,"
2925 " setting default value (%u)",
2926 1 << config.mprq.stride_num_n);
2928 if (config.mprq.stride_size_n &&
2929 (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2930 config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2931 config.mprq.stride_size_n =
2932 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2933 mprq_min_stride_size_n),
2934 mprq_max_stride_size_n);
2936 "the size of a stride"
2937 " for Multi-Packet RQ is out of range,"
2938 " setting default value (%u)",
2939 1 << config.mprq.stride_size_n);
2941 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2942 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2943 } else if (config.mprq.enabled && !mprq) {
2944 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2945 config.mprq.enabled = 0;
2947 if (config.max_dump_files_num == 0)
2948 config.max_dump_files_num = 128;
2949 eth_dev = rte_eth_dev_allocate(name);
2950 if (eth_dev == NULL) {
2951 DRV_LOG(ERR, "can not allocate rte ethdev");
2955 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2956 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2957 if (priv->representor) {
2958 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2959 eth_dev->data->representor_id = priv->representor_id;
2962 * Store associated network device interface index. This index
2963 * is permanent throughout the lifetime of device. So, we may store
2964 * the ifindex here and use the cached value further.
2966 MLX5_ASSERT(spawn->ifindex);
2967 priv->if_index = spawn->ifindex;
2968 eth_dev->data->dev_private = priv;
2969 priv->dev_data = eth_dev->data;
2970 eth_dev->data->mac_addrs = priv->mac;
2971 eth_dev->device = dpdk_dev;
2972 /* Configure the first MAC address by default. */
2973 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2975 "port %u cannot get MAC address, is mlx5_en"
2976 " loaded? (errno: %s)",
2977 eth_dev->data->port_id, strerror(rte_errno));
2982 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2983 eth_dev->data->port_id,
2984 mac.addr_bytes[0], mac.addr_bytes[1],
2985 mac.addr_bytes[2], mac.addr_bytes[3],
2986 mac.addr_bytes[4], mac.addr_bytes[5]);
2987 #ifdef RTE_LIBRTE_MLX5_DEBUG
2989 char ifname[IF_NAMESIZE];
2991 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2992 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2993 eth_dev->data->port_id, ifname);
2995 DRV_LOG(DEBUG, "port %u ifname is unknown",
2996 eth_dev->data->port_id);
2999 /* Get actual MTU if possible. */
3000 err = mlx5_get_mtu(eth_dev, &priv->mtu);
3005 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
3007 /* Initialize burst functions to prevent crashes before link-up. */
3008 eth_dev->rx_pkt_burst = removed_rx_burst;
3009 eth_dev->tx_pkt_burst = removed_tx_burst;
3010 eth_dev->dev_ops = &mlx5_dev_ops;
3011 /* Register MAC address. */
3012 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
3013 if (config.vf && config.vf_nl_en)
3014 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
3015 mlx5_ifindex(eth_dev),
3016 eth_dev->data->mac_addrs,
3017 MLX5_MAX_MAC_ADDRESSES);
3019 priv->ctrl_flows = 0;
3020 TAILQ_INIT(&priv->flow_meters);
3021 TAILQ_INIT(&priv->flow_meter_profiles);
3022 /* Hint libmlx5 to use PMD allocator for data plane resources */
3023 struct mlx5dv_ctx_allocators alctr = {
3024 .alloc = &mlx5_alloc_verbs_buf,
3025 .free = &mlx5_free_verbs_buf,
3028 mlx5_glue->dv_set_context_attr(sh->ctx,
3029 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
3030 (void *)((uintptr_t)&alctr));
3031 /* Bring Ethernet device up. */
3032 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
3033 eth_dev->data->port_id);
3034 mlx5_set_link_up(eth_dev);
3036 * Even though the interrupt handler is not installed yet,
3037 * interrupts will still trigger on the async_fd from
3038 * Verbs context returned by ibv_open_device().
3040 mlx5_link_update(eth_dev, 0);
3041 #ifdef HAVE_MLX5DV_DR_ESWITCH
3042 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
3043 (switch_info->representor || switch_info->master)))
3044 config.dv_esw_en = 0;
3046 config.dv_esw_en = 0;
3048 /* Detect minimal data bytes to inline. */
3049 mlx5_set_min_inline(spawn, &config);
3050 /* Store device configuration on private structure. */
3051 priv->config = config;
3052 /* Create context for virtual machine VLAN workaround. */
3053 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
3054 if (config.dv_flow_en) {
3055 err = mlx5_alloc_shared_dr(priv);
3059 * RSS id is shared with meter flow id. Meter flow id can only
3060 * use the 24 MSB of the register.
3062 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
3063 MLX5_MTR_COLOR_BITS);
3064 if (!priv->qrss_id_pool) {
3065 DRV_LOG(ERR, "can't create flow id pool");
3070 /* Supported Verbs flow priority number detection. */
3071 err = mlx5_flow_discover_priorities(eth_dev);
3076 priv->config.flow_prio = err;
3077 if (!priv->config.dv_esw_en &&
3078 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
3079 DRV_LOG(WARNING, "metadata mode %u is not supported "
3080 "(no E-Switch)", priv->config.dv_xmeta_en);
3081 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
3083 mlx5_set_metadata_mask(eth_dev);
3084 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3085 !priv->sh->dv_regc0_mask) {
3086 DRV_LOG(ERR, "metadata mode %u is not supported "
3087 "(no metadata reg_c[0] is available)",
3088 priv->config.dv_xmeta_en);
3093 * Allocate the buffer for flow creating, just once.
3094 * The allocation must be done before any flow creating.
3096 mlx5_flow_alloc_intermediate(eth_dev);
3097 /* Query availibility of metadata reg_c's. */
3098 err = mlx5_flow_discover_mreg_c(eth_dev);
3103 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
3105 "port %u extensive metadata register is not supported",
3106 eth_dev->data->port_id);
3107 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
3108 DRV_LOG(ERR, "metadata mode %u is not supported "
3109 "(no metadata registers available)",
3110 priv->config.dv_xmeta_en);
3115 if (priv->config.dv_flow_en &&
3116 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3117 mlx5_flow_ext_mreg_supported(eth_dev) &&
3118 priv->sh->dv_regc0_mask) {
3119 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
3120 MLX5_FLOW_MREG_HTABLE_SZ);
3121 if (!priv->mreg_cp_tbl) {
3129 if (priv->mreg_cp_tbl)
3130 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
3132 mlx5_free_shared_dr(priv);
3133 if (priv->nl_socket_route >= 0)
3134 close(priv->nl_socket_route);
3135 if (priv->nl_socket_rdma >= 0)
3136 close(priv->nl_socket_rdma);
3137 if (priv->vmwa_context)
3138 mlx5_vlan_vmwa_exit(priv->vmwa_context);
3139 if (priv->qrss_id_pool)
3140 mlx5_flow_id_pool_release(priv->qrss_id_pool);
3142 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
3144 if (eth_dev != NULL)
3145 eth_dev->data->dev_private = NULL;
3147 if (eth_dev != NULL) {
3148 /* mac_addrs must not be freed alone because part of dev_private */
3149 eth_dev->data->mac_addrs = NULL;
3150 rte_eth_dev_release_port(eth_dev);
3153 mlx5_free_shared_ibctx(sh);
3154 MLX5_ASSERT(err > 0);
3160 * Comparison callback to sort device data.
3162 * This is meant to be used with qsort().
3165 * Pointer to pointer to first data object.
3167 * Pointer to pointer to second data object.
3170 * 0 if both objects are equal, less than 0 if the first argument is less
3171 * than the second, greater than 0 otherwise.
3174 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3176 const struct mlx5_switch_info *si_a =
3177 &((const struct mlx5_dev_spawn_data *)a)->info;
3178 const struct mlx5_switch_info *si_b =
3179 &((const struct mlx5_dev_spawn_data *)b)->info;
3182 /* Master device first. */
3183 ret = si_b->master - si_a->master;
3186 /* Then representor devices. */
3187 ret = si_b->representor - si_a->representor;
3190 /* Unidentified devices come last in no specific order. */
3191 if (!si_a->representor)
3193 /* Order representors by name. */
3194 return si_a->port_name - si_b->port_name;
3198 * Match PCI information for possible slaves of bonding device.
3200 * @param[in] ibv_dev
3201 * Pointer to Infiniband device structure.
3202 * @param[in] pci_dev
3203 * Pointer to PCI device structure to match PCI address.
3204 * @param[in] nl_rdma
3205 * Netlink RDMA group socket handle.
3208 * negative value if no bonding device found, otherwise
3209 * positive index of slave PF in bonding.
3212 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3213 const struct rte_pci_device *pci_dev,
3216 char ifname[IF_NAMESIZE + 1];
3217 unsigned int ifindex;
3223 * Try to get master device name. If something goes
3224 * wrong suppose the lack of kernel support and no
3229 if (!strstr(ibv_dev->name, "bond"))
3231 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3235 * The Master device might not be on the predefined
3236 * port (not on port index 1, it is not garanted),
3237 * we have to scan all Infiniband device port and
3240 for (i = 1; i <= np; ++i) {
3241 /* Check whether Infiniband port is populated. */
3242 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3245 if (!if_indextoname(ifindex, ifname))
3247 /* Try to read bonding slave names from sysfs. */
3249 "/sys/class/net/%s/master/bonding/slaves", ifname);
3250 file = fopen(slaves, "r");
3256 /* Use safe format to check maximal buffer length. */
3257 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3258 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3259 char tmp_str[IF_NAMESIZE + 32];
3260 struct rte_pci_addr pci_addr;
3261 struct mlx5_switch_info info;
3263 /* Process slave interface names in the loop. */
3264 snprintf(tmp_str, sizeof(tmp_str),
3265 "/sys/class/net/%s", ifname);
3266 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3267 DRV_LOG(WARNING, "can not get PCI address"
3268 " for netdev \"%s\"", ifname);
3271 if (pci_dev->addr.domain != pci_addr.domain ||
3272 pci_dev->addr.bus != pci_addr.bus ||
3273 pci_dev->addr.devid != pci_addr.devid ||
3274 pci_dev->addr.function != pci_addr.function)
3276 /* Slave interface PCI address match found. */
3278 snprintf(tmp_str, sizeof(tmp_str),
3279 "/sys/class/net/%s/phys_port_name", ifname);
3280 file = fopen(tmp_str, "rb");
3283 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3284 if (fscanf(file, "%32s", tmp_str) == 1)
3285 mlx5_translate_port_name(tmp_str, &info);
3286 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3287 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3288 pf = info.port_name;
3297 * DPDK callback to register a PCI device.
3299 * This function spawns Ethernet devices out of a given PCI device.
3301 * @param[in] pci_drv
3302 * PCI driver structure (mlx5_driver).
3303 * @param[in] pci_dev
3304 * PCI device information.
3307 * 0 on success, a negative errno value otherwise and rte_errno is set.
3310 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3311 struct rte_pci_device *pci_dev)
3313 struct ibv_device **ibv_list;
3315 * Number of found IB Devices matching with requested PCI BDF.
3316 * nd != 1 means there are multiple IB devices over the same
3317 * PCI device and we have representors and master.
3319 unsigned int nd = 0;
3321 * Number of found IB device Ports. nd = 1 and np = 1..n means
3322 * we have the single multiport IB device, and there may be
3323 * representors attached to some of found ports.
3325 unsigned int np = 0;
3327 * Number of DPDK ethernet devices to Spawn - either over
3328 * multiple IB devices or multiple ports of single IB device.
3329 * Actually this is the number of iterations to spawn.
3331 unsigned int ns = 0;
3334 * < 0 - no bonding device (single one)
3335 * >= 0 - bonding device (value is slave PF index)
3338 struct mlx5_dev_spawn_data *list = NULL;
3339 struct mlx5_dev_config dev_config;
3342 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3343 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3347 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3348 mlx5_pmd_socket_init();
3349 ret = mlx5_init_once();
3351 DRV_LOG(ERR, "unable to init PMD global data: %s",
3352 strerror(rte_errno));
3355 MLX5_ASSERT(pci_drv == &mlx5_driver);
3357 ibv_list = mlx5_glue->get_device_list(&ret);
3359 rte_errno = errno ? errno : ENOSYS;
3360 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3364 * First scan the list of all Infiniband devices to find
3365 * matching ones, gathering into the list.
3367 struct ibv_device *ibv_match[ret + 1];
3368 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3369 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3373 struct rte_pci_addr pci_addr;
3375 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3376 bd = mlx5_device_bond_pci_match
3377 (ibv_list[ret], pci_dev, nl_rdma);
3380 * Bonding device detected. Only one match is allowed,
3381 * the bonding is supported over multi-port IB device,
3382 * there should be no matches on representor PCI
3383 * functions or non VF LAG bonding devices with
3384 * specified address.
3388 "multiple PCI match on bonding device"
3389 "\"%s\" found", ibv_list[ret]->name);
3394 DRV_LOG(INFO, "PCI information matches for"
3395 " slave %d bonding device \"%s\"",
3396 bd, ibv_list[ret]->name);
3397 ibv_match[nd++] = ibv_list[ret];
3400 if (mlx5_dev_to_pci_addr
3401 (ibv_list[ret]->ibdev_path, &pci_addr))
3403 if (pci_dev->addr.domain != pci_addr.domain ||
3404 pci_dev->addr.bus != pci_addr.bus ||
3405 pci_dev->addr.devid != pci_addr.devid ||
3406 pci_dev->addr.function != pci_addr.function)
3408 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3409 ibv_list[ret]->name);
3410 ibv_match[nd++] = ibv_list[ret];
3412 ibv_match[nd] = NULL;
3414 /* No device matches, just complain and bail out. */
3416 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3417 " are kernel drivers loaded?",
3418 pci_dev->addr.domain, pci_dev->addr.bus,
3419 pci_dev->addr.devid, pci_dev->addr.function);
3426 * Found single matching device may have multiple ports.
3427 * Each port may be representor, we have to check the port
3428 * number and check the representors existence.
3431 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3433 DRV_LOG(WARNING, "can not get IB device \"%s\""
3434 " ports number", ibv_match[0]->name);
3435 if (bd >= 0 && !np) {
3436 DRV_LOG(ERR, "can not get ports"
3437 " for bonding device");
3443 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3446 * This may happen if there is VF LAG kernel support and
3447 * application is compiled with older rdma_core library.
3450 "No kernel/verbs support for VF LAG bonding found.");
3451 rte_errno = ENOTSUP;
3457 * Now we can determine the maximal
3458 * amount of devices to be spawned.
3460 list = rte_zmalloc("device spawn data",
3461 sizeof(struct mlx5_dev_spawn_data) *
3463 RTE_CACHE_LINE_SIZE);
3465 DRV_LOG(ERR, "spawn data array allocation failure");
3470 if (bd >= 0 || np > 1) {
3472 * Single IB device with multiple ports found,
3473 * it may be E-Switch master device and representors.
3474 * We have to perform identification through the ports.
3476 MLX5_ASSERT(nl_rdma >= 0);
3477 MLX5_ASSERT(ns == 0);
3478 MLX5_ASSERT(nd == 1);
3480 for (i = 1; i <= np; ++i) {
3481 list[ns].max_port = np;
3482 list[ns].ibv_port = i;
3483 list[ns].ibv_dev = ibv_match[0];
3484 list[ns].eth_dev = NULL;
3485 list[ns].pci_dev = pci_dev;
3486 list[ns].pf_bond = bd;
3487 list[ns].ifindex = mlx5_nl_ifindex
3488 (nl_rdma, list[ns].ibv_dev->name, i);
3489 if (!list[ns].ifindex) {
3491 * No network interface index found for the
3492 * specified port, it means there is no
3493 * representor on this port. It's OK,
3494 * there can be disabled ports, for example
3495 * if sriov_numvfs < sriov_totalvfs.
3501 ret = mlx5_nl_switch_info
3505 if (ret || (!list[ns].info.representor &&
3506 !list[ns].info.master)) {
3508 * We failed to recognize representors with
3509 * Netlink, let's try to perform the task
3512 ret = mlx5_sysfs_switch_info
3516 if (!ret && bd >= 0) {
3517 switch (list[ns].info.name_type) {
3518 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3519 if (list[ns].info.port_name == bd)
3522 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3523 if (list[ns].info.pf_num == bd)
3531 if (!ret && (list[ns].info.representor ^
3532 list[ns].info.master))
3537 "unable to recognize master/representors"
3538 " on the IB device with multiple ports");
3545 * The existence of several matching entries (nd > 1) means
3546 * port representors have been instantiated. No existing Verbs
3547 * call nor sysfs entries can tell them apart, this can only
3548 * be done through Netlink calls assuming kernel drivers are
3549 * recent enough to support them.
3551 * In the event of identification failure through Netlink,
3552 * try again through sysfs, then:
3554 * 1. A single IB device matches (nd == 1) with single
3555 * port (np=0/1) and is not a representor, assume
3556 * no switch support.
3558 * 2. Otherwise no safe assumptions can be made;
3559 * complain louder and bail out.
3562 for (i = 0; i != nd; ++i) {
3563 memset(&list[ns].info, 0, sizeof(list[ns].info));
3564 list[ns].max_port = 1;
3565 list[ns].ibv_port = 1;
3566 list[ns].ibv_dev = ibv_match[i];
3567 list[ns].eth_dev = NULL;
3568 list[ns].pci_dev = pci_dev;
3569 list[ns].pf_bond = -1;
3570 list[ns].ifindex = 0;
3572 list[ns].ifindex = mlx5_nl_ifindex
3573 (nl_rdma, list[ns].ibv_dev->name, 1);
3574 if (!list[ns].ifindex) {
3575 char ifname[IF_NAMESIZE];
3578 * Netlink failed, it may happen with old
3579 * ib_core kernel driver (before 4.16).
3580 * We can assume there is old driver because
3581 * here we are processing single ports IB
3582 * devices. Let's try sysfs to retrieve
3583 * the ifindex. The method works for
3584 * master device only.
3588 * Multiple devices found, assume
3589 * representors, can not distinguish
3590 * master/representor and retrieve
3591 * ifindex via sysfs.
3595 ret = mlx5_get_master_ifname
3596 (ibv_match[i]->ibdev_path, &ifname);
3599 if_nametoindex(ifname);
3600 if (!list[ns].ifindex) {
3602 * No network interface index found
3603 * for the specified device, it means
3604 * there it is neither representor
3612 ret = mlx5_nl_switch_info
3616 if (ret || (!list[ns].info.representor &&
3617 !list[ns].info.master)) {
3619 * We failed to recognize representors with
3620 * Netlink, let's try to perform the task
3623 ret = mlx5_sysfs_switch_info
3627 if (!ret && (list[ns].info.representor ^
3628 list[ns].info.master)) {
3630 } else if ((nd == 1) &&
3631 !list[ns].info.representor &&
3632 !list[ns].info.master) {
3634 * Single IB device with
3635 * one physical port and
3636 * attached network device.
3637 * May be SRIOV is not enabled
3638 * or there is no representors.
3640 DRV_LOG(INFO, "no E-Switch support detected");
3647 "unable to recognize master/representors"
3648 " on the multiple IB devices");
3656 * Sort list to probe devices in natural order for users convenience
3657 * (i.e. master first, then representors from lowest to highest ID).
3659 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3660 /* Default configuration. */
3661 dev_config = (struct mlx5_dev_config){
3663 .mps = MLX5_ARG_UNSET,
3664 .dbnc = MLX5_ARG_UNSET,
3666 .txq_inline_max = MLX5_ARG_UNSET,
3667 .txq_inline_min = MLX5_ARG_UNSET,
3668 .txq_inline_mpw = MLX5_ARG_UNSET,
3669 .txqs_inline = MLX5_ARG_UNSET,
3671 .mr_ext_memseg_en = 1,
3673 .enabled = 0, /* Disabled by default. */
3676 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3677 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3681 .log_hp_size = MLX5_ARG_UNSET,
3683 /* Device specific configuration. */
3684 switch (pci_dev->id.device_id) {
3685 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3686 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3687 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3688 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3689 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3690 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3691 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3697 for (i = 0; i != ns; ++i) {
3700 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3703 if (!list[i].eth_dev) {
3704 if (rte_errno != EBUSY && rte_errno != EEXIST)
3706 /* Device is disabled or already spawned. Ignore it. */
3709 restore = list[i].eth_dev->data->dev_flags;
3710 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3711 /* Restore non-PCI flags cleared by the above call. */
3712 list[i].eth_dev->data->dev_flags |= restore;
3713 rte_eth_dev_probing_finish(list[i].eth_dev);
3717 "probe of PCI device " PCI_PRI_FMT " aborted after"
3718 " encountering an error: %s",
3719 pci_dev->addr.domain, pci_dev->addr.bus,
3720 pci_dev->addr.devid, pci_dev->addr.function,
3721 strerror(rte_errno));
3725 if (!list[i].eth_dev)
3727 mlx5_dev_close(list[i].eth_dev);
3728 /* mac_addrs must not be freed because in dev_private */
3729 list[i].eth_dev->data->mac_addrs = NULL;
3730 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3732 /* Restore original error. */
3739 * Do the routine cleanup:
3740 * - close opened Netlink sockets
3741 * - free allocated spawn data array
3742 * - free the Infiniband device list
3750 MLX5_ASSERT(ibv_list);
3751 mlx5_glue->free_device_list(ibv_list);
3756 * Look for the ethernet device belonging to mlx5 driver.
3758 * @param[in] port_id
3759 * port_id to start looking for device.
3760 * @param[in] pci_dev
3761 * Pointer to the hint PCI device. When device is being probed
3762 * the its siblings (master and preceding representors might
3763 * not have assigned driver yet (because the mlx5_pci_probe()
3764 * is not completed yet, for this case match on hint PCI
3765 * device may be used to detect sibling device.
3768 * port_id of found device, RTE_MAX_ETHPORT if not found.
3771 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3773 while (port_id < RTE_MAX_ETHPORTS) {
3774 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3776 if (dev->state != RTE_ETH_DEV_UNUSED &&
3778 (dev->device == &pci_dev->device ||
3779 (dev->device->driver &&
3780 dev->device->driver->name &&
3781 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3785 if (port_id >= RTE_MAX_ETHPORTS)
3786 return RTE_MAX_ETHPORTS;
3791 * DPDK callback to remove a PCI device.
3793 * This function removes all Ethernet devices belong to a given PCI device.
3795 * @param[in] pci_dev
3796 * Pointer to the PCI device.
3799 * 0 on success, the function cannot fail.
3802 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3806 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
3808 * mlx5_dev_close() is not registered to secondary process,
3809 * call the close function explicitly for secondary process.
3811 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
3812 mlx5_dev_close(&rte_eth_devices[port_id]);
3814 rte_eth_dev_close(port_id);
3819 static const struct rte_pci_id mlx5_pci_id_map[] = {
3821 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3822 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3825 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3826 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3829 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3830 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3833 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3834 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3837 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3838 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3841 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3842 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3845 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3846 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3849 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3850 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3853 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3854 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3857 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3858 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3861 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3862 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3865 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3866 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3869 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3870 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3873 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3874 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3877 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3878 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3885 static struct rte_pci_driver mlx5_driver = {
3887 .name = MLX5_DRIVER_NAME
3889 .id_table = mlx5_pci_id_map,
3890 .probe = mlx5_pci_probe,
3891 .remove = mlx5_pci_remove,
3892 .dma_map = mlx5_dma_map,
3893 .dma_unmap = mlx5_dma_unmap,
3894 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3895 RTE_PCI_DRV_PROBE_AGAIN,
3899 * Driver initialization routine.
3901 RTE_INIT(rte_mlx5_pmd_init)
3903 /* Initialize driver log type. */
3904 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3905 if (mlx5_logtype >= 0)
3906 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3908 /* Build the static tables for Verbs conversion. */
3909 mlx5_set_ptype_table();
3910 mlx5_set_cksum_table();
3911 mlx5_set_swp_types_table();
3913 rte_pci_register(&mlx5_driver);
3916 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3917 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3918 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");