drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 #ifndef HAVE_IBV_MLX5_MOD_MPW
 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
 166 #endif
 167
 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
 170 #endif
 171
 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 173
 174 /* Shared memory between primary and secondary processes. */
 175 struct mlx5_shared_data *mlx5_shared_data;
 176
 177 /* Spinlock for mlx5_shared_data allocation. */
 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 179
 180 /* Process local data for secondary processes. */
 181 static struct mlx5_local_data mlx5_local_data;
 182
 183 /** Driver-specific log messages type. */
 184 int mlx5_logtype;
 185
 186 /** Data associated with devices to spawn. */
 187 struct mlx5_dev_spawn_data {
 188         uint32_t ifindex; /**< Network interface index. */
 189         uint32_t max_port; /**< IB device maximal port index. */
 190         uint32_t ibv_port; /**< IB device physical port index. */
 191         int pf_bond; /**< bonding device PF index. < 0 - no bonding */
 192         struct mlx5_switch_info info; /**< Switch information. */
 193         struct ibv_device *ibv_dev; /**< Associated IB device. */
 194         struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
 195         struct rte_pci_device *pci_dev; /**< Backend PCI device. */
 196 };
 197
 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 200
 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 203         {
 204                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 0,
 209                 .release_mem_en = 1,
 210                 .malloc = rte_malloc_socket,
 211                 .free = rte_free,
 212                 .type = "mlx5_encap_decap_ipool",
 213         },
 214         {
 215                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 0,
 220                 .release_mem_en = 1,
 221                 .malloc = rte_malloc_socket,
 222                 .free = rte_free,
 223                 .type = "mlx5_push_vlan_ipool",
 224         },
 225         {
 226                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 0,
 231                 .release_mem_en = 1,
 232                 .malloc = rte_malloc_socket,
 233                 .free = rte_free,
 234                 .type = "mlx5_tag_ipool",
 235         },
 236         {
 237                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 0,
 242                 .release_mem_en = 1,
 243                 .malloc = rte_malloc_socket,
 244                 .free = rte_free,
 245                 .type = "mlx5_port_id_ipool",
 246         },
 247         {
 248                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 0,
 253                 .release_mem_en = 1,
 254                 .malloc = rte_malloc_socket,
 255                 .free = rte_free,
 256                 .type = "mlx5_jump_ipool",
 257         },
 258 #endif
 259         {
 260                 .size = sizeof(struct mlx5_flow_meter),
 261                 .trunk_size = 64,
 262                 .grow_trunk = 3,
 263                 .grow_shift = 2,
 264                 .need_lock = 0,
 265                 .release_mem_en = 1,
 266                 .malloc = rte_malloc_socket,
 267                 .free = rte_free,
 268                 .type = "mlx5_meter_ipool",
 269         },
 270         {
 271                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 272                 .trunk_size = 64,
 273                 .grow_trunk = 3,
 274                 .grow_shift = 2,
 275                 .need_lock = 0,
 276                 .release_mem_en = 1,
 277                 .malloc = rte_malloc_socket,
 278                 .free = rte_free,
 279                 .type = "mlx5_mcp_ipool",
 280         },
 281         {
 282                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 283                 .trunk_size = 64,
 284                 .grow_trunk = 3,
 285                 .grow_shift = 2,
 286                 .need_lock = 0,
 287                 .release_mem_en = 1,
 288                 .malloc = rte_malloc_socket,
 289                 .free = rte_free,
 290                 .type = "mlx5_hrxq_ipool",
 291         },
 292         {
 293                 .size = sizeof(struct mlx5_flow_handle),
 294                 .trunk_size = 64,
 295                 .grow_trunk = 3,
 296                 .grow_shift = 2,
 297                 .need_lock = 0,
 298                 .release_mem_en = 1,
 299                 .malloc = rte_malloc_socket,
 300                 .free = rte_free,
 301                 .type = "mlx5_flow_handle_ipool",
 302         },
 303         {
 304                 .size = sizeof(struct rte_flow),
 305                 .trunk_size = 4096,
 306                 .need_lock = 1,
 307                 .release_mem_en = 1,
 308                 .malloc = rte_malloc_socket,
 309                 .free = rte_free,
 310                 .type = "rte_flow_ipool",
 311         },
 312 };
 313
 314
 315 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 316 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 317
 318 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 319 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the counters management structure.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_ibv_shared object to free
 445  */
 446 static void
 447 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
 448 {
 449         uint8_t i;
 450
 451         TAILQ_INIT(&sh->cmng.flow_counters);
 452         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
 453                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 454 }
 455
 456 /**
 457  * Destroy all the resources allocated for a counter memory management.
 458  *
 459  * @param[in] mng
 460  *   Pointer to the memory management structure.
 461  */
 462 static void
 463 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 464 {
 465         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 466
 467         LIST_REMOVE(mng, next);
 468         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 469         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 470         rte_free(mem);
 471 }
 472
 473 /**
 474  * Close and release all the resources of the counters management.
 475  *
 476  * @param[in] sh
 477  *   Pointer to mlx5_ibv_shared object to free.
 478  */
 479 static void
 480 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
 481 {
 482         struct mlx5_counter_stats_mem_mng *mng;
 483         uint8_t i;
 484         int j;
 485         int retries = 1024;
 486
 487         rte_errno = 0;
 488         while (--retries) {
 489                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 490                 if (rte_errno != EINPROGRESS)
 491                         break;
 492                 rte_pause();
 493         }
 494         for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
 495                 struct mlx5_flow_counter_pool *pool;
 496                 uint32_t batch = !!(i % 2);
 497
 498                 if (!sh->cmng.ccont[i].pools)
 499                         continue;
 500                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 501                 while (pool) {
 502                         if (batch) {
 503                                 if (pool->min_dcs)
 504                                         claim_zero
 505                                         (mlx5_devx_cmd_destroy(pool->min_dcs));
 506                         }
 507                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 508                                 if (pool->counters_raw[j].action)
 509                                         claim_zero
 510                                         (mlx5_glue->destroy_flow_action
 511                                                (pool->counters_raw[j].action));
 512                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 513                                     (pool, j)->dcs)
 514                                         claim_zero(mlx5_devx_cmd_destroy
 515                                                   (MLX5_GET_POOL_CNT_EXT
 516                                                   (pool, j)->dcs));
 517                         }
 518                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
 519                                      next);
 520                         rte_free(pool);
 521                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 522                 }
 523                 rte_free(sh->cmng.ccont[i].pools);
 524         }
 525         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 526         while (mng) {
 527                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 528                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 529         }
 530         memset(&sh->cmng, 0, sizeof(sh->cmng));
 531 }
 532
 533 /**
 534  * Initialize the flow resources' indexed mempool.
 535  *
 536  * @param[in] sh
 537  *   Pointer to mlx5_ibv_shared object.
 538  * @param[in] sh
 539  *   Pointer to user dev config.
 540  */
 541 static void
 542 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh,
 543                        const struct mlx5_dev_config *config __rte_unused)
 544 {
 545         uint8_t i;
 546
 547 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 548         /*
 549          * While DV is supported, user chooses the verbs mode,
 550          * the mlx5 flow handle size is different with the
 551          * MLX5_FLOW_HANDLE_VERBS_SIZE.
 552          */
 553         if (!config->dv_flow_en)
 554                 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
 555                                         MLX5_FLOW_HANDLE_VERBS_SIZE;
 556 #endif
 557         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 558                 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
 559 }
 560
 561 /**
 562  * Release the flow resources' indexed mempool.
 563  *
 564  * @param[in] sh
 565  *   Pointer to mlx5_ibv_shared object.
 566  */
 567 static void
 568 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
 569 {
 570         uint8_t i;
 571
 572         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 573                 mlx5_ipool_destroy(sh->ipool[i]);
 574 }
 575
 576 /**
 577  * Extract pdn of PD object using DV API.
 578  *
 579  * @param[in] pd
 580  *   Pointer to the verbs PD object.
 581  * @param[out] pdn
 582  *   Pointer to the PD object number variable.
 583  *
 584  * @return
 585  *   0 on success, error value otherwise.
 586  */
 587 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 588 static int
 589 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
 590 {
 591         struct mlx5dv_obj obj;
 592         struct mlx5dv_pd pd_info;
 593         int ret = 0;
 594
 595         obj.pd.in = pd;
 596         obj.pd.out = &pd_info;
 597         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 598         if (ret) {
 599                 DRV_LOG(DEBUG, "Fail to get PD object info");
 600                 return ret;
 601         }
 602         *pdn = pd_info.pdn;
 603         return 0;
 604 }
 605 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 606
 607 static int
 608 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
 609 {
 610         char *env;
 611         int value;
 612
 613         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 614         /* Get environment variable to store. */
 615         env = getenv(MLX5_SHUT_UP_BF);
 616         value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
 617         if (config->dbnc == MLX5_ARG_UNSET)
 618                 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
 619         else
 620                 setenv(MLX5_SHUT_UP_BF,
 621                        config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
 622         return value;
 623 }
 624
 625 static void
 626 mlx5_restore_doorbell_mapping_env(int value)
 627 {
 628         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 629         /* Restore the original environment variable state. */
 630         if (value == MLX5_ARG_UNSET)
 631                 unsetenv(MLX5_SHUT_UP_BF);
 632         else
 633                 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
 634 }
 635
 636 /**
 637  * Allocate shared IB device context. If there is multiport device the
 638  * master and representors will share this context, if there is single
 639  * port dedicated IB device, the context will be used by only given
 640  * port due to unification.
 641  *
 642  * Routine first searches the context for the specified IB device name,
 643  * if found the shared context assumed and reference counter is incremented.
 644  * If no context found the new one is created and initialized with specified
 645  * IB device context and parameters.
 646  *
 647  * @param[in] spawn
 648  *   Pointer to the IB device attributes (name, port, etc).
 649  * @param[in] config
 650  *   Pointer to device configuration structure.
 651  *
 652  * @return
 653  *   Pointer to mlx5_ibv_shared object on success,
 654  *   otherwise NULL and rte_errno is set.
 655  */
 656 static struct mlx5_ibv_shared *
 657 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
 658                         const struct mlx5_dev_config *config)
 659 {
 660         struct mlx5_ibv_shared *sh;
 661         int dbmap_env;
 662         int err = 0;
 663         uint32_t i;
 664 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 665         struct mlx5_devx_tis_attr tis_attr = { 0 };
 666 #endif
 667
 668         MLX5_ASSERT(spawn);
 669         /* Secondary process should not create the shared context. */
 670         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 671         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 672         /* Search for IB context by device name. */
 673         LIST_FOREACH(sh, &mlx5_ibv_list, next) {
 674                 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
 675                         sh->refcnt++;
 676                         goto exit;
 677                 }
 678         }
 679         /* No device found, we have to create new shared context. */
 680         MLX5_ASSERT(spawn->max_port);
 681         sh = rte_zmalloc("ethdev shared ib context",
 682                          sizeof(struct mlx5_ibv_shared) +
 683                          spawn->max_port *
 684                          sizeof(struct mlx5_ibv_shared_port),
 685                          RTE_CACHE_LINE_SIZE);
 686         if (!sh) {
 687                 DRV_LOG(ERR, "shared context allocation failure");
 688                 rte_errno  = ENOMEM;
 689                 goto exit;
 690         }
 691         /*
 692          * Configure environment variable "MLX5_BF_SHUT_UP"
 693          * before the device creation. The rdma_core library
 694          * checks the variable at device creation and
 695          * stores the result internally.
 696          */
 697         dbmap_env = mlx5_config_doorbell_mapping_env(config);
 698         /* Try to open IB device with DV first, then usual Verbs. */
 699         errno = 0;
 700         sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
 701         if (sh->ctx) {
 702                 sh->devx = 1;
 703                 DRV_LOG(DEBUG, "DevX is supported");
 704                 /* The device is created, no need for environment. */
 705                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 706         } else {
 707                 /* The environment variable is still configured. */
 708                 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
 709                 err = errno ? errno : ENODEV;
 710                 /*
 711                  * The environment variable is not needed anymore,
 712                  * all device creation attempts are completed.
 713                  */
 714                 mlx5_restore_doorbell_mapping_env(dbmap_env);
 715                 if (!sh->ctx)
 716                         goto error;
 717                 DRV_LOG(DEBUG, "DevX is NOT supported");
 718         }
 719         err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
 720         if (err) {
 721                 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
 722                 goto error;
 723         }
 724         sh->refcnt = 1;
 725         sh->max_port = spawn->max_port;
 726         strncpy(sh->ibdev_name, sh->ctx->device->name,
 727                 sizeof(sh->ibdev_name));
 728         strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
 729                 sizeof(sh->ibdev_path));
 730         pthread_mutex_init(&sh->intr_mutex, NULL);
 731         /*
 732          * Setting port_id to max unallowed value means
 733          * there is no interrupt subhandler installed for
 734          * the given port index i.
 735          */
 736         for (i = 0; i < sh->max_port; i++) {
 737                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 738                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 739         }
 740         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 741         if (sh->pd == NULL) {
 742                 DRV_LOG(ERR, "PD allocation failure");
 743                 err = ENOMEM;
 744                 goto error;
 745         }
 746 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 747         if (sh->devx) {
 748                 err = mlx5_get_pdn(sh->pd, &sh->pdn);
 749                 if (err) {
 750                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 751                         goto error;
 752                 }
 753                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 754                 if (!sh->td) {
 755                         DRV_LOG(ERR, "TD allocation failure");
 756                         err = ENOMEM;
 757                         goto error;
 758                 }
 759                 tis_attr.transport_domain = sh->td->id;
 760                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 761                 if (!sh->tis) {
 762                         DRV_LOG(ERR, "TIS allocation failure");
 763                         err = ENOMEM;
 764                         goto error;
 765                 }
 766         }
 767         sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
 768         if (!sh->flow_id_pool) {
 769                 DRV_LOG(ERR, "can't create flow id pool");
 770                 err = ENOMEM;
 771                 goto error;
 772         }
 773 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 774         /*
 775          * Once the device is added to the list of memory event
 776          * callback, its global MR cache table cannot be expanded
 777          * on the fly because of deadlock. If it overflows, lookup
 778          * should be done by searching MR list linearly, which is slow.
 779          *
 780          * At this point the device is not added to the memory
 781          * event list yet, context is just being created.
 782          */
 783         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 784                                  MLX5_MR_BTREE_CACHE_N * 2,
 785                                  spawn->pci_dev->device.numa_node);
 786         if (err) {
 787                 err = rte_errno;
 788                 goto error;
 789         }
 790         mlx5_flow_counters_mng_init(sh);
 791         mlx5_flow_ipool_create(sh, config);
 792         /* Add device to memory callback list. */
 793         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 794         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 795                          sh, mem_event_cb);
 796         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 797         /* Add context to the global device list. */
 798         LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
 799 exit:
 800         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 801         return sh;
 802 error:
 803         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 804         MLX5_ASSERT(sh);
 805         if (sh->tis)
 806                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 807         if (sh->td)
 808                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 809         if (sh->pd)
 810                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 811         if (sh->ctx)
 812                 claim_zero(mlx5_glue->close_device(sh->ctx));
 813         if (sh->flow_id_pool)
 814                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 815         rte_free(sh);
 816         MLX5_ASSERT(err > 0);
 817         rte_errno = err;
 818         return NULL;
 819 }
 820
 821 /**
 822  * Free shared IB device context. Decrement counter and if zero free
 823  * all allocated resources and close handles.
 824  *
 825  * @param[in] sh
 826  *   Pointer to mlx5_ibv_shared object to free
 827  */
 828 static void
 829 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
 830 {
 831         pthread_mutex_lock(&mlx5_ibv_list_mutex);
 832 #ifdef RTE_LIBRTE_MLX5_DEBUG
 833         /* Check the object presence in the list. */
 834         struct mlx5_ibv_shared *lctx;
 835
 836         LIST_FOREACH(lctx, &mlx5_ibv_list, next)
 837                 if (lctx == sh)
 838                         break;
 839         MLX5_ASSERT(lctx);
 840         if (lctx != sh) {
 841                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 842                 goto exit;
 843         }
 844 #endif
 845         MLX5_ASSERT(sh);
 846         MLX5_ASSERT(sh->refcnt);
 847         /* Secondary process should not free the shared context. */
 848         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 849         if (--sh->refcnt)
 850                 goto exit;
 851         /* Remove from memory callback device list. */
 852         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 853         LIST_REMOVE(sh, mem_event_cb);
 854         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 855         /* Release created Memory Regions. */
 856         mlx5_mr_release_cache(&sh->share_cache);
 857         /* Remove context from the global device list. */
 858         LIST_REMOVE(sh, next);
 859         /*
 860          *  Ensure there is no async event handler installed.
 861          *  Only primary process handles async device events.
 862          **/
 863         mlx5_flow_counters_mng_close(sh);
 864         mlx5_flow_ipool_destroy(sh);
 865         MLX5_ASSERT(!sh->intr_cnt);
 866         if (sh->intr_cnt)
 867                 mlx5_intr_callback_unregister
 868                         (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
 869 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
 870         if (sh->devx_intr_cnt) {
 871                 if (sh->intr_handle_devx.fd)
 872                         rte_intr_callback_unregister(&sh->intr_handle_devx,
 873                                           mlx5_dev_interrupt_handler_devx, sh);
 874                 if (sh->devx_comp)
 875                         mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
 876         }
 877 #endif
 878         pthread_mutex_destroy(&sh->intr_mutex);
 879         if (sh->pd)
 880                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 881         if (sh->tis)
 882                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 883         if (sh->td)
 884                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 885         if (sh->ctx)
 886                 claim_zero(mlx5_glue->close_device(sh->ctx));
 887         if (sh->flow_id_pool)
 888                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 889         rte_free(sh);
 890 exit:
 891         pthread_mutex_unlock(&mlx5_ibv_list_mutex);
 892 }
 893
 894 /**
 895  * Destroy table hash list and all the root entries per domain.
 896  *
 897  * @param[in] priv
 898  *   Pointer to the private device data structure.
 899  */
 900 static void
 901 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 902 {
 903         struct mlx5_ibv_shared *sh = priv->sh;
 904         struct mlx5_flow_tbl_data_entry *tbl_data;
 905         union mlx5_flow_tbl_key table_key = {
 906                 {
 907                         .table_id = 0,
 908                         .reserved = 0,
 909                         .domain = 0,
 910                         .direction = 0,
 911                 }
 912         };
 913         struct mlx5_hlist_entry *pos;
 914
 915         if (!sh->flow_tbls)
 916                 return;
 917         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 918         if (pos) {
 919                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 920                                         entry);
 921                 MLX5_ASSERT(tbl_data);
 922                 mlx5_hlist_remove(sh->flow_tbls, pos);
 923                 rte_free(tbl_data);
 924         }
 925         table_key.direction = 1;
 926         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 927         if (pos) {
 928                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 929                                         entry);
 930                 MLX5_ASSERT(tbl_data);
 931                 mlx5_hlist_remove(sh->flow_tbls, pos);
 932                 rte_free(tbl_data);
 933         }
 934         table_key.direction = 0;
 935         table_key.domain = 1;
 936         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 937         if (pos) {
 938                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 939                                         entry);
 940                 MLX5_ASSERT(tbl_data);
 941                 mlx5_hlist_remove(sh->flow_tbls, pos);
 942                 rte_free(tbl_data);
 943         }
 944         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 945 }
 946
 947 /**
 948  * Initialize flow table hash list and create the root tables entry
 949  * for each domain.
 950  *
 951  * @param[in] priv
 952  *   Pointer to the private device data structure.
 953  *
 954  * @return
 955  *   Zero on success, positive error code otherwise.
 956  */
 957 static int
 958 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 959 {
 960         struct mlx5_ibv_shared *sh = priv->sh;
 961         char s[MLX5_HLIST_NAMESIZE];
 962         int err = 0;
 963
 964         MLX5_ASSERT(sh);
 965         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 966         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 967         if (!sh->flow_tbls) {
 968                 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
 969                 err = ENOMEM;
 970                 return err;
 971         }
 972 #ifndef HAVE_MLX5DV_DR
 973         /*
 974          * In case we have not DR support, the zero tables should be created
 975          * because DV expect to see them even if they cannot be created by
 976          * RDMA-CORE.
 977          */
 978         union mlx5_flow_tbl_key table_key = {
 979                 {
 980                         .table_id = 0,
 981                         .reserved = 0,
 982                         .domain = 0,
 983                         .direction = 0,
 984                 }
 985         };
 986         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 987                                                           sizeof(*tbl_data), 0);
 988
 989         if (!tbl_data) {
 990                 err = ENOMEM;
 991                 goto error;
 992         }
 993         tbl_data->entry.key = table_key.v64;
 994         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 995         if (err)
 996                 goto error;
 997         rte_atomic32_init(&tbl_data->tbl.refcnt);
 998         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 999         table_key.direction = 1;
1000         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1001         if (!tbl_data) {
1002                 err = ENOMEM;
1003                 goto error;
1004         }
1005         tbl_data->entry.key = table_key.v64;
1006         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1007         if (err)
1008                 goto error;
1009         rte_atomic32_init(&tbl_data->tbl.refcnt);
1010         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1011         table_key.direction = 0;
1012         table_key.domain = 1;
1013         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1014         if (!tbl_data) {
1015                 err = ENOMEM;
1016                 goto error;
1017         }
1018         tbl_data->entry.key = table_key.v64;
1019         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1020         if (err)
1021                 goto error;
1022         rte_atomic32_init(&tbl_data->tbl.refcnt);
1023         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1024         return err;
1025 error:
1026         mlx5_free_table_hash_list(priv);
1027 #endif /* HAVE_MLX5DV_DR */
1028         return err;
1029 }
1030
1031 /**
1032  * Initialize DR related data within private structure.
1033  * Routine checks the reference counter and does actual
1034  * resources creation/initialization only if counter is zero.
1035  *
1036  * @param[in] priv
1037  *   Pointer to the private device data structure.
1038  *
1039  * @return
1040  *   Zero on success, positive error code otherwise.
1041  */
1042 static int
1043 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1044 {
1045         struct mlx5_ibv_shared *sh = priv->sh;
1046         char s[MLX5_HLIST_NAMESIZE];
1047         int err = 0;
1048
1049         if (!sh->flow_tbls)
1050                 err = mlx5_alloc_table_hash_list(priv);
1051         else
1052                 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1053                         (void *)sh->flow_tbls);
1054         if (err)
1055                 return err;
1056         /* Create tags hash list table. */
1057         snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1058         sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1059         if (!sh->tag_table) {
1060                 DRV_LOG(ERR, "tags with hash creation failed.\n");
1061                 err = ENOMEM;
1062                 goto error;
1063         }
1064 #ifdef HAVE_MLX5DV_DR
1065         void *domain;
1066
1067         if (sh->dv_refcnt) {
1068                 /* Shared DV/DR structures is already initialized. */
1069                 sh->dv_refcnt++;
1070                 priv->dr_shared = 1;
1071                 return 0;
1072         }
1073         /* Reference counter is zero, we should initialize structures. */
1074         domain = mlx5_glue->dr_create_domain(sh->ctx,
1075                                              MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1076         if (!domain) {
1077                 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1078                 err = errno;
1079                 goto error;
1080         }
1081         sh->rx_domain = domain;
1082         domain = mlx5_glue->dr_create_domain(sh->ctx,
1083                                              MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1084         if (!domain) {
1085                 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1086                 err = errno;
1087                 goto error;
1088         }
1089         pthread_mutex_init(&sh->dv_mutex, NULL);
1090         sh->tx_domain = domain;
1091 #ifdef HAVE_MLX5DV_DR_ESWITCH
1092         if (priv->config.dv_esw_en) {
1093                 domain  = mlx5_glue->dr_create_domain
1094                         (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1095                 if (!domain) {
1096                         DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1097                         err = errno;
1098                         goto error;
1099                 }
1100                 sh->fdb_domain = domain;
1101                 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1102         }
1103 #endif
1104         sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1105 #endif /* HAVE_MLX5DV_DR */
1106         sh->dv_refcnt++;
1107         priv->dr_shared = 1;
1108         return 0;
1109 error:
1110         /* Rollback the created objects. */
1111         if (sh->rx_domain) {
1112                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1113                 sh->rx_domain = NULL;
1114         }
1115         if (sh->tx_domain) {
1116                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1117                 sh->tx_domain = NULL;
1118         }
1119         if (sh->fdb_domain) {
1120                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1121                 sh->fdb_domain = NULL;
1122         }
1123         if (sh->esw_drop_action) {
1124                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1125                 sh->esw_drop_action = NULL;
1126         }
1127         if (sh->pop_vlan_action) {
1128                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1129                 sh->pop_vlan_action = NULL;
1130         }
1131         if (sh->tag_table) {
1132                 /* tags should be destroyed with flow before. */
1133                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1134                 sh->tag_table = NULL;
1135         }
1136         mlx5_free_table_hash_list(priv);
1137         return err;
1138 }
1139
1140 /**
1141  * Destroy DR related data within private structure.
1142  *
1143  * @param[in] priv
1144  *   Pointer to the private device data structure.
1145  */
1146 static void
1147 mlx5_free_shared_dr(struct mlx5_priv *priv)
1148 {
1149         struct mlx5_ibv_shared *sh;
1150
1151         if (!priv->dr_shared)
1152                 return;
1153         priv->dr_shared = 0;
1154         sh = priv->sh;
1155         MLX5_ASSERT(sh);
1156 #ifdef HAVE_MLX5DV_DR
1157         MLX5_ASSERT(sh->dv_refcnt);
1158         if (sh->dv_refcnt && --sh->dv_refcnt)
1159                 return;
1160         if (sh->rx_domain) {
1161                 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1162                 sh->rx_domain = NULL;
1163         }
1164         if (sh->tx_domain) {
1165                 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1166                 sh->tx_domain = NULL;
1167         }
1168 #ifdef HAVE_MLX5DV_DR_ESWITCH
1169         if (sh->fdb_domain) {
1170                 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1171                 sh->fdb_domain = NULL;
1172         }
1173         if (sh->esw_drop_action) {
1174                 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1175                 sh->esw_drop_action = NULL;
1176         }
1177 #endif
1178         if (sh->pop_vlan_action) {
1179                 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1180                 sh->pop_vlan_action = NULL;
1181         }
1182         pthread_mutex_destroy(&sh->dv_mutex);
1183 #endif /* HAVE_MLX5DV_DR */
1184         if (sh->tag_table) {
1185                 /* tags should be destroyed with flow before. */
1186                 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1187                 sh->tag_table = NULL;
1188         }
1189         mlx5_free_table_hash_list(priv);
1190 }
1191
1192 /**
1193  * Initialize shared data between primary and secondary process.
1194  *
1195  * A memzone is reserved by primary process and secondary processes attach to
1196  * the memzone.
1197  *
1198  * @return
1199  *   0 on success, a negative errno value otherwise and rte_errno is set.
1200  */
1201 static int
1202 mlx5_init_shared_data(void)
1203 {
1204         const struct rte_memzone *mz;
1205         int ret = 0;
1206
1207         rte_spinlock_lock(&mlx5_shared_data_lock);
1208         if (mlx5_shared_data == NULL) {
1209                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1210                         /* Allocate shared memory. */
1211                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1212                                                  sizeof(*mlx5_shared_data),
1213                                                  SOCKET_ID_ANY, 0);
1214                         if (mz == NULL) {
1215                                 DRV_LOG(ERR,
1216                                         "Cannot allocate mlx5 shared data");
1217                                 ret = -rte_errno;
1218                                 goto error;
1219                         }
1220                         mlx5_shared_data = mz->addr;
1221                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1222                         rte_spinlock_init(&mlx5_shared_data->lock);
1223                 } else {
1224                         /* Lookup allocated shared memory. */
1225                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1226                         if (mz == NULL) {
1227                                 DRV_LOG(ERR,
1228                                         "Cannot attach mlx5 shared data");
1229                                 ret = -rte_errno;
1230                                 goto error;
1231                         }
1232                         mlx5_shared_data = mz->addr;
1233                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1234                 }
1235         }
1236 error:
1237         rte_spinlock_unlock(&mlx5_shared_data_lock);
1238         return ret;
1239 }
1240
1241 /**
1242  * Retrieve integer value from environment variable.
1243  *
1244  * @param[in] name
1245  *   Environment variable name.
1246  *
1247  * @return
1248  *   Integer value, 0 if the variable is not set.
1249  */
1250 int
1251 mlx5_getenv_int(const char *name)
1252 {
1253         const char *val = getenv(name);
1254
1255         if (val == NULL)
1256                 return 0;
1257         return atoi(val);
1258 }
1259
1260 /**
1261  * Verbs callback to allocate a memory. This function should allocate the space
1262  * according to the size provided residing inside a huge page.
1263  * Please note that all allocation must respect the alignment from libmlx5
1264  * (i.e. currently sysconf(_SC_PAGESIZE)).
1265  *
1266  * @param[in] size
1267  *   The size in bytes of the memory to allocate.
1268  * @param[in] data
1269  *   A pointer to the callback data.
1270  *
1271  * @return
1272  *   Allocated buffer, NULL otherwise and rte_errno is set.
1273  */
1274 static void *
1275 mlx5_alloc_verbs_buf(size_t size, void *data)
1276 {
1277         struct mlx5_priv *priv = data;
1278         void *ret;
1279         size_t alignment = sysconf(_SC_PAGESIZE);
1280         unsigned int socket = SOCKET_ID_ANY;
1281
1282         if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1283                 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1284
1285                 socket = ctrl->socket;
1286         } else if (priv->verbs_alloc_ctx.type ==
1287                    MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1288                 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1289
1290                 socket = ctrl->socket;
1291         }
1292         MLX5_ASSERT(data != NULL);
1293         ret = rte_malloc_socket(__func__, size, alignment, socket);
1294         if (!ret && size)
1295                 rte_errno = ENOMEM;
1296         return ret;
1297 }
1298
1299 /**
1300  * Verbs callback to free a memory.
1301  *
1302  * @param[in] ptr
1303  *   A pointer to the memory to free.
1304  * @param[in] data
1305  *   A pointer to the callback data.
1306  */
1307 static void
1308 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1309 {
1310         MLX5_ASSERT(data != NULL);
1311         rte_free(ptr);
1312 }
1313
1314 /**
1315  * DPDK callback to add udp tunnel port
1316  *
1317  * @param[in] dev
1318  *   A pointer to eth_dev
1319  * @param[in] udp_tunnel
1320  *   A pointer to udp tunnel
1321  *
1322  * @return
1323  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1324  */
1325 int
1326 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1327                          struct rte_eth_udp_tunnel *udp_tunnel)
1328 {
1329         MLX5_ASSERT(udp_tunnel != NULL);
1330         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1331             udp_tunnel->udp_port == 4789)
1332                 return 0;
1333         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1334             udp_tunnel->udp_port == 4790)
1335                 return 0;
1336         return -ENOTSUP;
1337 }
1338
1339 /**
1340  * Initialize process private data structure.
1341  *
1342  * @param dev
1343  *   Pointer to Ethernet device structure.
1344  *
1345  * @return
1346  *   0 on success, a negative errno value otherwise and rte_errno is set.
1347  */
1348 int
1349 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1350 {
1351         struct mlx5_priv *priv = dev->data->dev_private;
1352         struct mlx5_proc_priv *ppriv;
1353         size_t ppriv_size;
1354
1355         /*
1356          * UAR register table follows the process private structure. BlueFlame
1357          * registers for Tx queues are stored in the table.
1358          */
1359         ppriv_size =
1360                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1361         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1362                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1363         if (!ppriv) {
1364                 rte_errno = ENOMEM;
1365                 return -rte_errno;
1366         }
1367         ppriv->uar_table_sz = ppriv_size;
1368         dev->process_private = ppriv;
1369         return 0;
1370 }
1371
1372 /**
1373  * Un-initialize process private data structure.
1374  *
1375  * @param dev
1376  *   Pointer to Ethernet device structure.
1377  */
1378 static void
1379 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1380 {
1381         if (!dev->process_private)
1382                 return;
1383         rte_free(dev->process_private);
1384         dev->process_private = NULL;
1385 }
1386
1387 /**
1388  * DPDK callback to close the device.
1389  *
1390  * Destroy all queues and objects, free memory.
1391  *
1392  * @param dev
1393  *   Pointer to Ethernet device structure.
1394  */
1395 static void
1396 mlx5_dev_close(struct rte_eth_dev *dev)
1397 {
1398         struct mlx5_priv *priv = dev->data->dev_private;
1399         unsigned int i;
1400         int ret;
1401
1402         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1403                 dev->data->port_id,
1404                 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1405         /* In case mlx5_dev_stop() has not been called. */
1406         mlx5_dev_interrupt_handler_uninstall(dev);
1407         mlx5_dev_interrupt_handler_devx_uninstall(dev);
1408         /*
1409          * If default mreg copy action is removed at the stop stage,
1410          * the search will return none and nothing will be done anymore.
1411          */
1412         mlx5_flow_stop_default(dev);
1413         mlx5_traffic_disable(dev);
1414         /*
1415          * If all the flows are already flushed in the device stop stage,
1416          * then this will return directly without any action.
1417          */
1418         mlx5_flow_list_flush(dev, &priv->flows, true);
1419         mlx5_flow_meter_flush(dev, NULL);
1420         /* Free the intermediate buffers for flow creation. */
1421         mlx5_flow_free_intermediate(dev);
1422         /* Prevent crashes when queues are still in use. */
1423         dev->rx_pkt_burst = removed_rx_burst;
1424         dev->tx_pkt_burst = removed_tx_burst;
1425         rte_wmb();
1426         /* Disable datapath on secondary process. */
1427         mlx5_mp_req_stop_rxtx(dev);
1428         if (priv->rxqs != NULL) {
1429                 /* XXX race condition if mlx5_rx_burst() is still running. */
1430                 usleep(1000);
1431                 for (i = 0; (i != priv->rxqs_n); ++i)
1432                         mlx5_rxq_release(dev, i);
1433                 priv->rxqs_n = 0;
1434                 priv->rxqs = NULL;
1435         }
1436         if (priv->txqs != NULL) {
1437                 /* XXX race condition if mlx5_tx_burst() is still running. */
1438                 usleep(1000);
1439                 for (i = 0; (i != priv->txqs_n); ++i)
1440                         mlx5_txq_release(dev, i);
1441                 priv->txqs_n = 0;
1442                 priv->txqs = NULL;
1443         }
1444         mlx5_proc_priv_uninit(dev);
1445         if (priv->mreg_cp_tbl)
1446                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1447         mlx5_mprq_free_mp(dev);
1448         mlx5_free_shared_dr(priv);
1449         if (priv->rss_conf.rss_key != NULL)
1450                 rte_free(priv->rss_conf.rss_key);
1451         if (priv->reta_idx != NULL)
1452                 rte_free(priv->reta_idx);
1453         if (priv->config.vf)
1454                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1455                                        dev->data->mac_addrs,
1456                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1457         if (priv->nl_socket_route >= 0)
1458                 close(priv->nl_socket_route);
1459         if (priv->nl_socket_rdma >= 0)
1460                 close(priv->nl_socket_rdma);
1461         if (priv->vmwa_context)
1462                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1463         ret = mlx5_hrxq_verify(dev);
1464         if (ret)
1465                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1466                         dev->data->port_id);
1467         ret = mlx5_ind_table_obj_verify(dev);
1468         if (ret)
1469                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1470                         dev->data->port_id);
1471         ret = mlx5_rxq_obj_verify(dev);
1472         if (ret)
1473                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1474                         dev->data->port_id);
1475         ret = mlx5_rxq_verify(dev);
1476         if (ret)
1477                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1478                         dev->data->port_id);
1479         ret = mlx5_txq_obj_verify(dev);
1480         if (ret)
1481                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1482                         dev->data->port_id);
1483         ret = mlx5_txq_verify(dev);
1484         if (ret)
1485                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1486                         dev->data->port_id);
1487         ret = mlx5_flow_verify(dev);
1488         if (ret)
1489                 DRV_LOG(WARNING, "port %u some flows still remain",
1490                         dev->data->port_id);
1491         if (priv->sh) {
1492                 /*
1493                  * Free the shared context in last turn, because the cleanup
1494                  * routines above may use some shared fields, like
1495                  * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1496                  * ifindex if Netlink fails.
1497                  */
1498                 mlx5_free_shared_ibctx(priv->sh);
1499                 priv->sh = NULL;
1500         }
1501         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1502                 unsigned int c = 0;
1503                 uint16_t port_id;
1504
1505                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1506                         struct mlx5_priv *opriv =
1507                                 rte_eth_devices[port_id].data->dev_private;
1508
1509                         if (!opriv ||
1510                             opriv->domain_id != priv->domain_id ||
1511                             &rte_eth_devices[port_id] == dev)
1512                                 continue;
1513                         ++c;
1514                         break;
1515                 }
1516                 if (!c)
1517                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1518         }
1519         memset(priv, 0, sizeof(*priv));
1520         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1521         /*
1522          * Reset mac_addrs to NULL such that it is not freed as part of
1523          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1524          * it is freed when dev_private is freed.
1525          */
1526         dev->data->mac_addrs = NULL;
1527 }
1528
1529 const struct eth_dev_ops mlx5_dev_ops = {
1530         .dev_configure = mlx5_dev_configure,
1531         .dev_start = mlx5_dev_start,
1532         .dev_stop = mlx5_dev_stop,
1533         .dev_set_link_down = mlx5_set_link_down,
1534         .dev_set_link_up = mlx5_set_link_up,
1535         .dev_close = mlx5_dev_close,
1536         .promiscuous_enable = mlx5_promiscuous_enable,
1537         .promiscuous_disable = mlx5_promiscuous_disable,
1538         .allmulticast_enable = mlx5_allmulticast_enable,
1539         .allmulticast_disable = mlx5_allmulticast_disable,
1540         .link_update = mlx5_link_update,
1541         .stats_get = mlx5_stats_get,
1542         .stats_reset = mlx5_stats_reset,
1543         .xstats_get = mlx5_xstats_get,
1544         .xstats_reset = mlx5_xstats_reset,
1545         .xstats_get_names = mlx5_xstats_get_names,
1546         .fw_version_get = mlx5_fw_version_get,
1547         .dev_infos_get = mlx5_dev_infos_get,
1548         .read_clock = mlx5_read_clock,
1549         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1550         .vlan_filter_set = mlx5_vlan_filter_set,
1551         .rx_queue_setup = mlx5_rx_queue_setup,
1552         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1553         .tx_queue_setup = mlx5_tx_queue_setup,
1554         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1555         .rx_queue_release = mlx5_rx_queue_release,
1556         .tx_queue_release = mlx5_tx_queue_release,
1557         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1558         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1559         .mac_addr_remove = mlx5_mac_addr_remove,
1560         .mac_addr_add = mlx5_mac_addr_add,
1561         .mac_addr_set = mlx5_mac_addr_set,
1562         .set_mc_addr_list = mlx5_set_mc_addr_list,
1563         .mtu_set = mlx5_dev_set_mtu,
1564         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1565         .vlan_offload_set = mlx5_vlan_offload_set,
1566         .reta_update = mlx5_dev_rss_reta_update,
1567         .reta_query = mlx5_dev_rss_reta_query,
1568         .rss_hash_update = mlx5_rss_hash_update,
1569         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1570         .filter_ctrl = mlx5_dev_filter_ctrl,
1571         .rx_descriptor_status = mlx5_rx_descriptor_status,
1572         .tx_descriptor_status = mlx5_tx_descriptor_status,
1573         .rxq_info_get = mlx5_rxq_info_get,
1574         .txq_info_get = mlx5_txq_info_get,
1575         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1576         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1577         .rx_queue_count = mlx5_rx_queue_count,
1578         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1579         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1580         .is_removed = mlx5_is_removed,
1581         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1582         .get_module_info = mlx5_get_module_info,
1583         .get_module_eeprom = mlx5_get_module_eeprom,
1584         .hairpin_cap_get = mlx5_hairpin_cap_get,
1585         .mtr_ops_get = mlx5_flow_meter_ops_get,
1586 };
1587
1588 /* Available operations from secondary process. */
1589 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1590         .stats_get = mlx5_stats_get,
1591         .stats_reset = mlx5_stats_reset,
1592         .xstats_get = mlx5_xstats_get,
1593         .xstats_reset = mlx5_xstats_reset,
1594         .xstats_get_names = mlx5_xstats_get_names,
1595         .fw_version_get = mlx5_fw_version_get,
1596         .dev_infos_get = mlx5_dev_infos_get,
1597         .rx_descriptor_status = mlx5_rx_descriptor_status,
1598         .tx_descriptor_status = mlx5_tx_descriptor_status,
1599         .rxq_info_get = mlx5_rxq_info_get,
1600         .txq_info_get = mlx5_txq_info_get,
1601         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1602         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1603         .get_module_info = mlx5_get_module_info,
1604         .get_module_eeprom = mlx5_get_module_eeprom,
1605 };
1606
1607 /* Available operations in flow isolated mode. */
1608 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1609         .dev_configure = mlx5_dev_configure,
1610         .dev_start = mlx5_dev_start,
1611         .dev_stop = mlx5_dev_stop,
1612         .dev_set_link_down = mlx5_set_link_down,
1613         .dev_set_link_up = mlx5_set_link_up,
1614         .dev_close = mlx5_dev_close,
1615         .promiscuous_enable = mlx5_promiscuous_enable,
1616         .promiscuous_disable = mlx5_promiscuous_disable,
1617         .allmulticast_enable = mlx5_allmulticast_enable,
1618         .allmulticast_disable = mlx5_allmulticast_disable,
1619         .link_update = mlx5_link_update,
1620         .stats_get = mlx5_stats_get,
1621         .stats_reset = mlx5_stats_reset,
1622         .xstats_get = mlx5_xstats_get,
1623         .xstats_reset = mlx5_xstats_reset,
1624         .xstats_get_names = mlx5_xstats_get_names,
1625         .fw_version_get = mlx5_fw_version_get,
1626         .dev_infos_get = mlx5_dev_infos_get,
1627         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1628         .vlan_filter_set = mlx5_vlan_filter_set,
1629         .rx_queue_setup = mlx5_rx_queue_setup,
1630         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1631         .tx_queue_setup = mlx5_tx_queue_setup,
1632         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1633         .rx_queue_release = mlx5_rx_queue_release,
1634         .tx_queue_release = mlx5_tx_queue_release,
1635         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1636         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1637         .mac_addr_remove = mlx5_mac_addr_remove,
1638         .mac_addr_add = mlx5_mac_addr_add,
1639         .mac_addr_set = mlx5_mac_addr_set,
1640         .set_mc_addr_list = mlx5_set_mc_addr_list,
1641         .mtu_set = mlx5_dev_set_mtu,
1642         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1643         .vlan_offload_set = mlx5_vlan_offload_set,
1644         .filter_ctrl = mlx5_dev_filter_ctrl,
1645         .rx_descriptor_status = mlx5_rx_descriptor_status,
1646         .tx_descriptor_status = mlx5_tx_descriptor_status,
1647         .rxq_info_get = mlx5_rxq_info_get,
1648         .txq_info_get = mlx5_txq_info_get,
1649         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1650         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1651         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1652         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1653         .is_removed = mlx5_is_removed,
1654         .get_module_info = mlx5_get_module_info,
1655         .get_module_eeprom = mlx5_get_module_eeprom,
1656         .hairpin_cap_get = mlx5_hairpin_cap_get,
1657         .mtr_ops_get = mlx5_flow_meter_ops_get,
1658 };
1659
1660 /**
1661  * Verify and store value for device argument.
1662  *
1663  * @param[in] key
1664  *   Key argument to verify.
1665  * @param[in] val
1666  *   Value associated with key.
1667  * @param opaque
1668  *   User data.
1669  *
1670  * @return
1671  *   0 on success, a negative errno value otherwise and rte_errno is set.
1672  */
1673 static int
1674 mlx5_args_check(const char *key, const char *val, void *opaque)
1675 {
1676         struct mlx5_dev_config *config = opaque;
1677         unsigned long tmp;
1678
1679         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1680         if (!strcmp(MLX5_REPRESENTOR, key))
1681                 return 0;
1682         errno = 0;
1683         tmp = strtoul(val, NULL, 0);
1684         if (errno) {
1685                 rte_errno = errno;
1686                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1687                 return -rte_errno;
1688         }
1689         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1690                 config->cqe_comp = !!tmp;
1691         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1692                 config->cqe_pad = !!tmp;
1693         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1694                 config->hw_padding = !!tmp;
1695         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1696                 config->mprq.enabled = !!tmp;
1697         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1698                 config->mprq.stride_num_n = tmp;
1699         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1700                 config->mprq.stride_size_n = tmp;
1701         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1702                 config->mprq.max_memcpy_len = tmp;
1703         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1704                 config->mprq.min_rxqs_num = tmp;
1705         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1706                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1707                                  " converted to txq_inline_max", key);
1708                 config->txq_inline_max = tmp;
1709         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1710                 config->txq_inline_max = tmp;
1711         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1712                 config->txq_inline_min = tmp;
1713         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1714                 config->txq_inline_mpw = tmp;
1715         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1716                 config->txqs_inline = tmp;
1717         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1718                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1719         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1720                 config->mps = !!tmp;
1721         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1722                 if (tmp != MLX5_TXDB_CACHED &&
1723                     tmp != MLX5_TXDB_NCACHED &&
1724                     tmp != MLX5_TXDB_HEURISTIC) {
1725                         DRV_LOG(ERR, "invalid Tx doorbell "
1726                                      "mapping parameter");
1727                         rte_errno = EINVAL;
1728                         return -rte_errno;
1729                 }
1730                 config->dbnc = tmp;
1731         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1732                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1733         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1734                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1735                                  " converted to txq_inline_mpw", key);
1736                 config->txq_inline_mpw = tmp;
1737         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1738                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1739         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1740                 config->rx_vec_en = !!tmp;
1741         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1742                 config->l3_vxlan_en = !!tmp;
1743         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1744                 config->vf_nl_en = !!tmp;
1745         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1746                 config->dv_esw_en = !!tmp;
1747         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1748                 config->dv_flow_en = !!tmp;
1749         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1750                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1751                     tmp != MLX5_XMETA_MODE_META16 &&
1752                     tmp != MLX5_XMETA_MODE_META32) {
1753                         DRV_LOG(ERR, "invalid extensive "
1754                                      "metadata parameter");
1755                         rte_errno = EINVAL;
1756                         return -rte_errno;
1757                 }
1758                 config->dv_xmeta_en = tmp;
1759         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1760                 config->mr_ext_memseg_en = !!tmp;
1761         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1762                 config->max_dump_files_num = tmp;
1763         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1764                 config->lro.timeout = tmp;
1765         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1766                 DRV_LOG(DEBUG, "class argument is %s.", val);
1767         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1768                 config->log_hp_size = tmp;
1769         } else {
1770                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1771                 rte_errno = EINVAL;
1772                 return -rte_errno;
1773         }
1774         return 0;
1775 }
1776
1777 /**
1778  * Parse device parameters.
1779  *
1780  * @param config
1781  *   Pointer to device configuration structure.
1782  * @param devargs
1783  *   Device arguments structure.
1784  *
1785  * @return
1786  *   0 on success, a negative errno value otherwise and rte_errno is set.
1787  */
1788 static int
1789 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1790 {
1791         const char **params = (const char *[]){
1792                 MLX5_RXQ_CQE_COMP_EN,
1793                 MLX5_RXQ_CQE_PAD_EN,
1794                 MLX5_RXQ_PKT_PAD_EN,
1795                 MLX5_RX_MPRQ_EN,
1796                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1797                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1798                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1799                 MLX5_RXQS_MIN_MPRQ,
1800                 MLX5_TXQ_INLINE,
1801                 MLX5_TXQ_INLINE_MIN,
1802                 MLX5_TXQ_INLINE_MAX,
1803                 MLX5_TXQ_INLINE_MPW,
1804                 MLX5_TXQS_MIN_INLINE,
1805                 MLX5_TXQS_MAX_VEC,
1806                 MLX5_TXQ_MPW_EN,
1807                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1808                 MLX5_TXQ_MAX_INLINE_LEN,
1809                 MLX5_TX_DB_NC,
1810                 MLX5_TX_VEC_EN,
1811                 MLX5_RX_VEC_EN,
1812                 MLX5_L3_VXLAN_EN,
1813                 MLX5_VF_NL_EN,
1814                 MLX5_DV_ESW_EN,
1815                 MLX5_DV_FLOW_EN,
1816                 MLX5_DV_XMETA_EN,
1817                 MLX5_MR_EXT_MEMSEG_EN,
1818                 MLX5_REPRESENTOR,
1819                 MLX5_MAX_DUMP_FILES_NUM,
1820                 MLX5_LRO_TIMEOUT_USEC,
1821                 MLX5_CLASS_ARG_NAME,
1822                 MLX5_HP_BUF_SIZE,
1823                 NULL,
1824         };
1825         struct rte_kvargs *kvlist;
1826         int ret = 0;
1827         int i;
1828
1829         if (devargs == NULL)
1830                 return 0;
1831         /* Following UGLY cast is done to pass checkpatch. */
1832         kvlist = rte_kvargs_parse(devargs->args, params);
1833         if (kvlist == NULL) {
1834                 rte_errno = EINVAL;
1835                 return -rte_errno;
1836         }
1837         /* Process parameters. */
1838         for (i = 0; (params[i] != NULL); ++i) {
1839                 if (rte_kvargs_count(kvlist, params[i])) {
1840                         ret = rte_kvargs_process(kvlist, params[i],
1841                                                  mlx5_args_check, config);
1842                         if (ret) {
1843                                 rte_errno = EINVAL;
1844                                 rte_kvargs_free(kvlist);
1845                                 return -rte_errno;
1846                         }
1847                 }
1848         }
1849         rte_kvargs_free(kvlist);
1850         return 0;
1851 }
1852
1853 static struct rte_pci_driver mlx5_driver;
1854
1855 /**
1856  * PMD global initialization.
1857  *
1858  * Independent from individual device, this function initializes global
1859  * per-PMD data structures distinguishing primary and secondary processes.
1860  * Hence, each initialization is called once per a process.
1861  *
1862  * @return
1863  *   0 on success, a negative errno value otherwise and rte_errno is set.
1864  */
1865 static int
1866 mlx5_init_once(void)
1867 {
1868         struct mlx5_shared_data *sd;
1869         struct mlx5_local_data *ld = &mlx5_local_data;
1870         int ret = 0;
1871
1872         if (mlx5_init_shared_data())
1873                 return -rte_errno;
1874         sd = mlx5_shared_data;
1875         MLX5_ASSERT(sd);
1876         rte_spinlock_lock(&sd->lock);
1877         switch (rte_eal_process_type()) {
1878         case RTE_PROC_PRIMARY:
1879                 if (sd->init_done)
1880                         break;
1881                 LIST_INIT(&sd->mem_event_cb_list);
1882                 rte_rwlock_init(&sd->mem_event_rwlock);
1883                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1884                                                 mlx5_mr_mem_event_cb, NULL);
1885                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1886                                            mlx5_mp_primary_handle);
1887                 if (ret)
1888                         goto out;
1889                 sd->init_done = true;
1890                 break;
1891         case RTE_PROC_SECONDARY:
1892                 if (ld->init_done)
1893                         break;
1894                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1895                                              mlx5_mp_secondary_handle);
1896                 if (ret)
1897                         goto out;
1898                 ++sd->secondary_cnt;
1899                 ld->init_done = true;
1900                 break;
1901         default:
1902                 break;
1903         }
1904 out:
1905         rte_spinlock_unlock(&sd->lock);
1906         return ret;
1907 }
1908
1909 /**
1910  * Configures the minimal amount of data to inline into WQE
1911  * while sending packets.
1912  *
1913  * - the txq_inline_min has the maximal priority, if this
1914  *   key is specified in devargs
1915  * - if DevX is enabled the inline mode is queried from the
1916  *   device (HCA attributes and NIC vport context if needed).
1917  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1918  *   and none (0 bytes) for other NICs
1919  *
1920  * @param spawn
1921  *   Verbs device parameters (name, port, switch_info) to spawn.
1922  * @param config
1923  *   Device configuration parameters.
1924  */
1925 static void
1926 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1927                     struct mlx5_dev_config *config)
1928 {
1929         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1930                 /* Application defines size of inlined data explicitly. */
1931                 switch (spawn->pci_dev->id.device_id) {
1932                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1933                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1934                         if (config->txq_inline_min <
1935                                        (int)MLX5_INLINE_HSIZE_L2) {
1936                                 DRV_LOG(DEBUG,
1937                                         "txq_inline_mix aligned to minimal"
1938                                         " ConnectX-4 required value %d",
1939                                         (int)MLX5_INLINE_HSIZE_L2);
1940                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1941                         }
1942                         break;
1943                 }
1944                 goto exit;
1945         }
1946         if (config->hca_attr.eth_net_offloads) {
1947                 /* We have DevX enabled, inline mode queried successfully. */
1948                 switch (config->hca_attr.wqe_inline_mode) {
1949                 case MLX5_CAP_INLINE_MODE_L2:
1950                         /* outer L2 header must be inlined. */
1951                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1952                         goto exit;
1953                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1954                         /* No inline data are required by NIC. */
1955                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1956                         config->hw_vlan_insert =
1957                                 config->hca_attr.wqe_vlan_insert;
1958                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1959                         goto exit;
1960                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1961                         /* inline mode is defined by NIC vport context. */
1962                         if (!config->hca_attr.eth_virt)
1963                                 break;
1964                         switch (config->hca_attr.vport_inline_mode) {
1965                         case MLX5_INLINE_MODE_NONE:
1966                                 config->txq_inline_min =
1967                                         MLX5_INLINE_HSIZE_NONE;
1968                                 goto exit;
1969                         case MLX5_INLINE_MODE_L2:
1970                                 config->txq_inline_min =
1971                                         MLX5_INLINE_HSIZE_L2;
1972                                 goto exit;
1973                         case MLX5_INLINE_MODE_IP:
1974                                 config->txq_inline_min =
1975                                         MLX5_INLINE_HSIZE_L3;
1976                                 goto exit;
1977                         case MLX5_INLINE_MODE_TCP_UDP:
1978                                 config->txq_inline_min =
1979                                         MLX5_INLINE_HSIZE_L4;
1980                                 goto exit;
1981                         case MLX5_INLINE_MODE_INNER_L2:
1982                                 config->txq_inline_min =
1983                                         MLX5_INLINE_HSIZE_INNER_L2;
1984                                 goto exit;
1985                         case MLX5_INLINE_MODE_INNER_IP:
1986                                 config->txq_inline_min =
1987                                         MLX5_INLINE_HSIZE_INNER_L3;
1988                                 goto exit;
1989                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1990                                 config->txq_inline_min =
1991                                         MLX5_INLINE_HSIZE_INNER_L4;
1992                                 goto exit;
1993                         }
1994                 }
1995         }
1996         /*
1997          * We get here if we are unable to deduce
1998          * inline data size with DevX. Try PCI ID
1999          * to determine old NICs.
2000          */
2001         switch (spawn->pci_dev->id.device_id) {
2002         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2003         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2004         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2005         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2006                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2007                 config->hw_vlan_insert = 0;
2008                 break;
2009         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2010         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2011         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2012         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2013                 /*
2014                  * These NICs support VLAN insertion from WQE and
2015                  * report the wqe_vlan_insert flag. But there is the bug
2016                  * and PFC control may be broken, so disable feature.
2017                  */
2018                 config->hw_vlan_insert = 0;
2019                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2020                 break;
2021         default:
2022                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2023                 break;
2024         }
2025 exit:
2026         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2027 }
2028
2029 /**
2030  * Configures the metadata mask fields in the shared context.
2031  *
2032  * @param [in] dev
2033  *   Pointer to Ethernet device.
2034  */
2035 static void
2036 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2037 {
2038         struct mlx5_priv *priv = dev->data->dev_private;
2039         struct mlx5_ibv_shared *sh = priv->sh;
2040         uint32_t meta, mark, reg_c0;
2041
2042         reg_c0 = ~priv->vport_meta_mask;
2043         switch (priv->config.dv_xmeta_en) {
2044         case MLX5_XMETA_MODE_LEGACY:
2045                 meta = UINT32_MAX;
2046                 mark = MLX5_FLOW_MARK_MASK;
2047                 break;
2048         case MLX5_XMETA_MODE_META16:
2049                 meta = reg_c0 >> rte_bsf32(reg_c0);
2050                 mark = MLX5_FLOW_MARK_MASK;
2051                 break;
2052         case MLX5_XMETA_MODE_META32:
2053                 meta = UINT32_MAX;
2054                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2055                 break;
2056         default:
2057                 meta = 0;
2058                 mark = 0;
2059                 MLX5_ASSERT(false);
2060                 break;
2061         }
2062         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2063                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2064                                  sh->dv_mark_mask, mark);
2065         else
2066                 sh->dv_mark_mask = mark;
2067         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2068                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2069                                  sh->dv_meta_mask, meta);
2070         else
2071                 sh->dv_meta_mask = meta;
2072         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2073                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2074                                  sh->dv_meta_mask, reg_c0);
2075         else
2076                 sh->dv_regc0_mask = reg_c0;
2077         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2078         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2079         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2080         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2081 }
2082
2083 /**
2084  * Allocate page of door-bells and register it using DevX API.
2085  *
2086  * @param [in] dev
2087  *   Pointer to Ethernet device.
2088  *
2089  * @return
2090  *   Pointer to new page on success, NULL otherwise.
2091  */
2092 static struct mlx5_devx_dbr_page *
2093 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2094 {
2095         struct mlx5_priv *priv = dev->data->dev_private;
2096         struct mlx5_devx_dbr_page *page;
2097
2098         /* Allocate space for door-bell page and management data. */
2099         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2100                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2101         if (!page) {
2102                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2103                         dev->data->port_id);
2104                 return NULL;
2105         }
2106         /* Register allocated memory. */
2107         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2108                                               MLX5_DBR_PAGE_SIZE, 0);
2109         if (!page->umem) {
2110                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2111                         dev->data->port_id);
2112                 rte_free(page);
2113                 return NULL;
2114         }
2115         return page;
2116 }
2117
2118 /**
2119  * Find the next available door-bell, allocate new page if needed.
2120  *
2121  * @param [in] dev
2122  *   Pointer to Ethernet device.
2123  * @param [out] dbr_page
2124  *   Door-bell page containing the page data.
2125  *
2126  * @return
2127  *   Door-bell address offset on success, a negative error value otherwise.
2128  */
2129 int64_t
2130 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2131 {
2132         struct mlx5_priv *priv = dev->data->dev_private;
2133         struct mlx5_devx_dbr_page *page = NULL;
2134         uint32_t i, j;
2135
2136         LIST_FOREACH(page, &priv->dbrpgs, next)
2137                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2138                         break;
2139         if (!page) { /* No page with free door-bell exists. */
2140                 page = mlx5_alloc_dbr_page(dev);
2141                 if (!page) /* Failed to allocate new page. */
2142                         return (-1);
2143                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2144         }
2145         /* Loop to find bitmap part with clear bit. */
2146         for (i = 0;
2147              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2148              i++)
2149                 ; /* Empty. */
2150         /* Find the first clear bit. */
2151         j = rte_bsf64(~page->dbr_bitmap[i]);
2152         MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2153         page->dbr_bitmap[i] |= (1 << j);
2154         page->dbr_count++;
2155         *dbr_page = page;
2156         return (((i * 64) + j) * sizeof(uint64_t));
2157 }
2158
2159 /**
2160  * Release a door-bell record.
2161  *
2162  * @param [in] dev
2163  *   Pointer to Ethernet device.
2164  * @param [in] umem_id
2165  *   UMEM ID of page containing the door-bell record to release.
2166  * @param [in] offset
2167  *   Offset of door-bell record in page.
2168  *
2169  * @return
2170  *   0 on success, a negative error value otherwise.
2171  */
2172 int32_t
2173 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2174 {
2175         struct mlx5_priv *priv = dev->data->dev_private;
2176         struct mlx5_devx_dbr_page *page = NULL;
2177         int ret = 0;
2178
2179         LIST_FOREACH(page, &priv->dbrpgs, next)
2180                 /* Find the page this address belongs to. */
2181                 if (page->umem->umem_id == umem_id)
2182                         break;
2183         if (!page)
2184                 return -EINVAL;
2185         page->dbr_count--;
2186         if (!page->dbr_count) {
2187                 /* Page not used, free it and remove from list. */
2188                 LIST_REMOVE(page, next);
2189                 if (page->umem)
2190                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
2191                 rte_free(page);
2192         } else {
2193                 /* Mark in bitmap that this door-bell is not in use. */
2194                 offset /= MLX5_DBR_SIZE;
2195                 int i = offset / 64;
2196                 int j = offset % 64;
2197
2198                 page->dbr_bitmap[i] &= ~(1 << j);
2199         }
2200         return ret;
2201 }
2202
2203 int
2204 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2205 {
2206         static const char *const dynf_names[] = {
2207                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2208                 RTE_MBUF_DYNFLAG_METADATA_NAME
2209         };
2210         unsigned int i;
2211
2212         if (n < RTE_DIM(dynf_names))
2213                 return -ENOMEM;
2214         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2215                 if (names[i] == NULL)
2216                         return -EINVAL;
2217                 strcpy(names[i], dynf_names[i]);
2218         }
2219         return RTE_DIM(dynf_names);
2220 }
2221
2222 /**
2223  * Check sibling device configurations.
2224  *
2225  * Sibling devices sharing the Infiniband device context
2226  * should have compatible configurations. This regards
2227  * representors and bonding slaves.
2228  *
2229  * @param priv
2230  *   Private device descriptor.
2231  * @param config
2232  *   Configuration of the device is going to be created.
2233  *
2234  * @return
2235  *   0 on success, EINVAL otherwise
2236  */
2237 static int
2238 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2239                               struct mlx5_dev_config *config)
2240 {
2241         struct mlx5_ibv_shared *sh = priv->sh;
2242         struct mlx5_dev_config *sh_conf = NULL;
2243         uint16_t port_id;
2244
2245         MLX5_ASSERT(sh);
2246         /* Nothing to compare for the single/first device. */
2247         if (sh->refcnt == 1)
2248                 return 0;
2249         /* Find the device with shared context. */
2250         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2251                 struct mlx5_priv *opriv =
2252                         rte_eth_devices[port_id].data->dev_private;
2253
2254                 if (opriv && opriv != priv && opriv->sh == sh) {
2255                         sh_conf = &opriv->config;
2256                         break;
2257                 }
2258         }
2259         if (!sh_conf)
2260                 return 0;
2261         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2262                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2263                              " for shared %s context", sh->ibdev_name);
2264                 rte_errno = EINVAL;
2265                 return rte_errno;
2266         }
2267         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2268                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2269                              " for shared %s context", sh->ibdev_name);
2270                 rte_errno = EINVAL;
2271                 return rte_errno;
2272         }
2273         return 0;
2274 }
2275 /**
2276  * Spawn an Ethernet device from Verbs information.
2277  *
2278  * @param dpdk_dev
2279  *   Backing DPDK device.
2280  * @param spawn
2281  *   Verbs device parameters (name, port, switch_info) to spawn.
2282  * @param config
2283  *   Device configuration parameters.
2284  *
2285  * @return
2286  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
2287  *   is set. The following errors are defined:
2288  *
2289  *   EBUSY: device is not supposed to be spawned.
2290  *   EEXIST: device is already spawned
2291  */
2292 static struct rte_eth_dev *
2293 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2294                struct mlx5_dev_spawn_data *spawn,
2295                struct mlx5_dev_config config)
2296 {
2297         const struct mlx5_switch_info *switch_info = &spawn->info;
2298         struct mlx5_ibv_shared *sh = NULL;
2299         struct ibv_port_attr port_attr;
2300         struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2301         struct rte_eth_dev *eth_dev = NULL;
2302         struct mlx5_priv *priv = NULL;
2303         int err = 0;
2304         unsigned int hw_padding = 0;
2305         unsigned int mps;
2306         unsigned int cqe_comp;
2307         unsigned int cqe_pad = 0;
2308         unsigned int tunnel_en = 0;
2309         unsigned int mpls_en = 0;
2310         unsigned int swp = 0;
2311         unsigned int mprq = 0;
2312         unsigned int mprq_min_stride_size_n = 0;
2313         unsigned int mprq_max_stride_size_n = 0;
2314         unsigned int mprq_min_stride_num_n = 0;
2315         unsigned int mprq_max_stride_num_n = 0;
2316         struct rte_ether_addr mac;
2317         char name[RTE_ETH_NAME_MAX_LEN];
2318         int own_domain_id = 0;
2319         uint16_t port_id;
2320         unsigned int i;
2321 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2322         struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2323 #endif
2324
2325         /* Determine if this port representor is supposed to be spawned. */
2326         if (switch_info->representor && dpdk_dev->devargs) {
2327                 struct rte_eth_devargs eth_da;
2328
2329                 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
2330                 if (err) {
2331                         rte_errno = -err;
2332                         DRV_LOG(ERR, "failed to process device arguments: %s",
2333                                 strerror(rte_errno));
2334                         return NULL;
2335                 }
2336                 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2337                         if (eth_da.representor_ports[i] ==
2338                             (uint16_t)switch_info->port_name)
2339                                 break;
2340                 if (i == eth_da.nb_representor_ports) {
2341                         rte_errno = EBUSY;
2342                         return NULL;
2343                 }
2344         }
2345         /* Build device name. */
2346         if (spawn->pf_bond <  0) {
2347                 /* Single device. */
2348                 if (!switch_info->representor)
2349                         strlcpy(name, dpdk_dev->name, sizeof(name));
2350                 else
2351                         snprintf(name, sizeof(name), "%s_representor_%u",
2352                                  dpdk_dev->name, switch_info->port_name);
2353         } else {
2354                 /* Bonding device. */
2355                 if (!switch_info->representor)
2356                         snprintf(name, sizeof(name), "%s_%s",
2357                                  dpdk_dev->name, spawn->ibv_dev->name);
2358                 else
2359                         snprintf(name, sizeof(name), "%s_%s_representor_%u",
2360                                  dpdk_dev->name, spawn->ibv_dev->name,
2361                                  switch_info->port_name);
2362         }
2363         /* check if the device is already spawned */
2364         if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2365                 rte_errno = EEXIST;
2366                 return NULL;
2367         }
2368         DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2369         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2370                 struct mlx5_mp_id mp_id;
2371
2372                 eth_dev = rte_eth_dev_attach_secondary(name);
2373                 if (eth_dev == NULL) {
2374                         DRV_LOG(ERR, "can not attach rte ethdev");
2375                         rte_errno = ENOMEM;
2376                         return NULL;
2377                 }
2378                 eth_dev->device = dpdk_dev;
2379                 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2380                 err = mlx5_proc_priv_init(eth_dev);
2381                 if (err)
2382                         return NULL;
2383                 mp_id.port_id = eth_dev->data->port_id;
2384                 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2385                 /* Receive command fd from primary process */
2386                 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2387                 if (err < 0)
2388                         return NULL;
2389                 /* Remap UAR for Tx queues. */
2390                 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2391                 if (err)
2392                         return NULL;
2393                 /*
2394                  * Ethdev pointer is still required as input since
2395                  * the primary device is not accessible from the
2396                  * secondary process.
2397                  */
2398                 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2399                 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2400                 return eth_dev;
2401         }
2402         /*
2403          * Some parameters ("tx_db_nc" in particularly) are needed in
2404          * advance to create dv/verbs device context. We proceed the
2405          * devargs here to get ones, and later proceed devargs again
2406          * to override some hardware settings.
2407          */
2408         err = mlx5_args(&config, dpdk_dev->devargs);
2409         if (err) {
2410                 err = rte_errno;
2411                 DRV_LOG(ERR, "failed to process device arguments: %s",
2412                         strerror(rte_errno));
2413                 goto error;
2414         }
2415         sh = mlx5_alloc_shared_ibctx(spawn, &config);
2416         if (!sh)
2417                 return NULL;
2418         config.devx = sh->devx;
2419 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2420         config.dest_tir = 1;
2421 #endif
2422 #ifdef HAVE_IBV_MLX5_MOD_SWP
2423         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2424 #endif
2425         /*
2426          * Multi-packet send is supported by ConnectX-4 Lx PF as well
2427          * as all ConnectX-5 devices.
2428          */
2429 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2430         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2431 #endif
2432 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2433         dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2434 #endif
2435         mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2436         if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2437                 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2438                         DRV_LOG(DEBUG, "enhanced MPW is supported");
2439                         mps = MLX5_MPW_ENHANCED;
2440                 } else {
2441                         DRV_LOG(DEBUG, "MPW is supported");
2442                         mps = MLX5_MPW;
2443                 }
2444         } else {
2445                 DRV_LOG(DEBUG, "MPW isn't supported");
2446                 mps = MLX5_MPW_DISABLED;
2447         }
2448 #ifdef HAVE_IBV_MLX5_MOD_SWP
2449         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2450                 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2451         DRV_LOG(DEBUG, "SWP support: %u", swp);
2452 #endif
2453         config.swp = !!swp;
2454 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2455         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2456                 struct mlx5dv_striding_rq_caps mprq_caps =
2457                         dv_attr.striding_rq_caps;
2458
2459                 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2460                         mprq_caps.min_single_stride_log_num_of_bytes);
2461                 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2462                         mprq_caps.max_single_stride_log_num_of_bytes);
2463                 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2464                         mprq_caps.min_single_wqe_log_num_of_strides);
2465                 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2466                         mprq_caps.max_single_wqe_log_num_of_strides);
2467                 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2468                         mprq_caps.supported_qpts);
2469                 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2470                 mprq = 1;
2471                 mprq_min_stride_size_n =
2472                         mprq_caps.min_single_stride_log_num_of_bytes;
2473                 mprq_max_stride_size_n =
2474                         mprq_caps.max_single_stride_log_num_of_bytes;
2475                 mprq_min_stride_num_n =
2476                         mprq_caps.min_single_wqe_log_num_of_strides;
2477                 mprq_max_stride_num_n =
2478                         mprq_caps.max_single_wqe_log_num_of_strides;
2479         }
2480 #endif
2481         if (RTE_CACHE_LINE_SIZE == 128 &&
2482             !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2483                 cqe_comp = 0;
2484         else
2485                 cqe_comp = 1;
2486         config.cqe_comp = cqe_comp;
2487 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2488         /* Whether device supports 128B Rx CQE padding. */
2489         cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2490                   (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2491 #endif
2492 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2493         if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2494                 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2495                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2496                              (dv_attr.tunnel_offloads_caps &
2497                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2498                              (dv_attr.tunnel_offloads_caps &
2499                               MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2500         }
2501         DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2502                 tunnel_en ? "" : "not ");
2503 #else
2504         DRV_LOG(WARNING,
2505                 "tunnel offloading disabled due to old OFED/rdma-core version");
2506 #endif
2507         config.tunnel_en = tunnel_en;
2508 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2509         mpls_en = ((dv_attr.tunnel_offloads_caps &
2510                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2511                    (dv_attr.tunnel_offloads_caps &
2512                     MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2513         DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2514                 mpls_en ? "" : "not ");
2515 #else
2516         DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2517                 " old OFED/rdma-core version or firmware configuration");
2518 #endif
2519         config.mpls_en = mpls_en;
2520         /* Check port status. */
2521         err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2522         if (err) {
2523                 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2524                 goto error;
2525         }
2526         if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2527                 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2528                 err = EINVAL;
2529                 goto error;
2530         }
2531         if (port_attr.state != IBV_PORT_ACTIVE)
2532                 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2533                         mlx5_glue->port_state_str(port_attr.state),
2534                         port_attr.state);
2535         /* Allocate private eth device data. */
2536         priv = rte_zmalloc("ethdev private structure",
2537                            sizeof(*priv),
2538                            RTE_CACHE_LINE_SIZE);
2539         if (priv == NULL) {
2540                 DRV_LOG(ERR, "priv allocation failure");
2541                 err = ENOMEM;
2542                 goto error;
2543         }
2544         priv->sh = sh;
2545         priv->ibv_port = spawn->ibv_port;
2546         priv->pci_dev = spawn->pci_dev;
2547         priv->mtu = RTE_ETHER_MTU;
2548         priv->mp_id.port_id = port_id;
2549         strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2550 #ifndef RTE_ARCH_64
2551         /* Initialize UAR access locks for 32bit implementations. */
2552         rte_spinlock_init(&priv->uar_lock_cq);
2553         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2554                 rte_spinlock_init(&priv->uar_lock[i]);
2555 #endif
2556         /* Some internal functions rely on Netlink sockets, open them now. */
2557         priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2558         priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2559         priv->representor = !!switch_info->representor;
2560         priv->master = !!switch_info->master;
2561         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2562         priv->vport_meta_tag = 0;
2563         priv->vport_meta_mask = 0;
2564         priv->pf_bond = spawn->pf_bond;
2565 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2566         /*
2567          * The DevX port query API is implemented. E-Switch may use
2568          * either vport or reg_c[0] metadata register to match on
2569          * vport index. The engaged part of metadata register is
2570          * defined by mask.
2571          */
2572         if (switch_info->representor || switch_info->master) {
2573                 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2574                                       MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2575                 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2576                                                  &devx_port);
2577                 if (err) {
2578                         DRV_LOG(WARNING,
2579                                 "can't query devx port %d on device %s",
2580                                 spawn->ibv_port, spawn->ibv_dev->name);
2581                         devx_port.comp_mask = 0;
2582                 }
2583         }
2584         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2585                 priv->vport_meta_tag = devx_port.reg_c_0.value;
2586                 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2587                 if (!priv->vport_meta_mask) {
2588                         DRV_LOG(ERR, "vport zero mask for port %d"
2589                                      " on bonding device %s",
2590                                      spawn->ibv_port, spawn->ibv_dev->name);
2591                         err = ENOTSUP;
2592                         goto error;
2593                 }
2594                 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2595                         DRV_LOG(ERR, "invalid vport tag for port %d"
2596                                      " on bonding device %s",
2597                                      spawn->ibv_port, spawn->ibv_dev->name);
2598                         err = ENOTSUP;
2599                         goto error;
2600                 }
2601         }
2602         if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2603                 priv->vport_id = devx_port.vport_num;
2604         } else if (spawn->pf_bond >= 0) {
2605                 DRV_LOG(ERR, "can't deduce vport index for port %d"
2606                              " on bonding device %s",
2607                              spawn->ibv_port, spawn->ibv_dev->name);
2608                 err = ENOTSUP;
2609                 goto error;
2610         } else {
2611                 /* Suppose vport index in compatible way. */
2612                 priv->vport_id = switch_info->representor ?
2613                                  switch_info->port_name + 1 : -1;
2614         }
2615 #else
2616         /*
2617          * Kernel/rdma_core support single E-Switch per PF configurations
2618          * only and vport_id field contains the vport index for
2619          * associated VF, which is deduced from representor port name.
2620          * For example, let's have the IB device port 10, it has
2621          * attached network device eth0, which has port name attribute
2622          * pf0vf2, we can deduce the VF number as 2, and set vport index
2623          * as 3 (2+1). This assigning schema should be changed if the
2624          * multiple E-Switch instances per PF configurations or/and PCI
2625          * subfunctions are added.
2626          */
2627         priv->vport_id = switch_info->representor ?
2628                          switch_info->port_name + 1 : -1;
2629 #endif
2630         /* representor_id field keeps the unmodified VF index. */
2631         priv->representor_id = switch_info->representor ?
2632                                switch_info->port_name : -1;
2633         /*
2634          * Look for sibling devices in order to reuse their switch domain
2635          * if any, otherwise allocate one.
2636          */
2637         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2638                 const struct mlx5_priv *opriv =
2639                         rte_eth_devices[port_id].data->dev_private;
2640
2641                 if (!opriv ||
2642                     opriv->sh != priv->sh ||
2643                         opriv->domain_id ==
2644                         RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2645                         continue;
2646                 priv->domain_id = opriv->domain_id;
2647                 break;
2648         }
2649         if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2650                 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2651                 if (err) {
2652                         err = rte_errno;
2653                         DRV_LOG(ERR, "unable to allocate switch domain: %s",
2654                                 strerror(rte_errno));
2655                         goto error;
2656                 }
2657                 own_domain_id = 1;
2658         }
2659         /* Override some values set by hardware configuration. */
2660         mlx5_args(&config, dpdk_dev->devargs);
2661         err = mlx5_dev_check_sibling_config(priv, &config);
2662         if (err)
2663                 goto error;
2664         config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2665                             IBV_DEVICE_RAW_IP_CSUM);
2666         DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2667                 (config.hw_csum ? "" : "not "));
2668 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2669         !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2670         DRV_LOG(DEBUG, "counters are not supported");
2671 #endif
2672 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2673         if (config.dv_flow_en) {
2674                 DRV_LOG(WARNING, "DV flow is not supported");
2675                 config.dv_flow_en = 0;
2676         }
2677 #endif
2678         config.ind_table_max_size =
2679                 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2680         /*
2681          * Remove this check once DPDK supports larger/variable
2682          * indirection tables.
2683          */
2684         if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2685                 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2686         DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2687                 config.ind_table_max_size);
2688         config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2689                                   IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2690         DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2691                 (config.hw_vlan_strip ? "" : "not "));
2692         config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2693                                  IBV_RAW_PACKET_CAP_SCATTER_FCS);
2694         DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2695                 (config.hw_fcs_strip ? "" : "not "));
2696 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2697         hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2698 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2699         hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2700                         IBV_DEVICE_PCI_WRITE_END_PADDING);
2701 #endif
2702         if (config.hw_padding && !hw_padding) {
2703                 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2704                 config.hw_padding = 0;
2705         } else if (config.hw_padding) {
2706                 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2707         }
2708         config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2709                       (sh->device_attr.tso_caps.supported_qpts &
2710                        (1 << IBV_QPT_RAW_PACKET)));
2711         if (config.tso)
2712                 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2713         /*
2714          * MPW is disabled by default, while the Enhanced MPW is enabled
2715          * by default.
2716          */
2717         if (config.mps == MLX5_ARG_UNSET)
2718                 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2719                                                           MLX5_MPW_DISABLED;
2720         else
2721                 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2722         DRV_LOG(INFO, "%sMPS is %s",
2723                 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2724                 config.mps == MLX5_MPW ? "legacy " : "",
2725                 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2726         if (config.cqe_comp && !cqe_comp) {
2727                 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2728                 config.cqe_comp = 0;
2729         }
2730         if (config.cqe_pad && !cqe_pad) {
2731                 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2732                 config.cqe_pad = 0;
2733         } else if (config.cqe_pad) {
2734                 DRV_LOG(INFO, "Rx CQE padding is enabled");
2735         }
2736         if (config.devx) {
2737                 priv->counter_fallback = 0;
2738                 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2739                 if (err) {
2740                         err = -err;
2741                         goto error;
2742                 }
2743                 if (!config.hca_attr.flow_counters_dump)
2744                         priv->counter_fallback = 1;
2745 #ifndef HAVE_IBV_DEVX_ASYNC
2746                 priv->counter_fallback = 1;
2747 #endif
2748                 if (priv->counter_fallback)
2749                         DRV_LOG(INFO, "Use fall-back DV counter management");
2750                 /* Check for LRO support. */
2751                 if (config.dest_tir && config.hca_attr.lro_cap &&
2752                     config.dv_flow_en) {
2753                         /* TBD check tunnel lro caps. */
2754                         config.lro.supported = config.hca_attr.lro_cap;
2755                         DRV_LOG(DEBUG, "Device supports LRO");
2756                         /*
2757                          * If LRO timeout is not configured by application,
2758                          * use the minimal supported value.
2759                          */
2760                         if (!config.lro.timeout)
2761                                 config.lro.timeout =
2762                                 config.hca_attr.lro_timer_supported_periods[0];
2763                         DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2764                                 config.lro.timeout);
2765                 }
2766 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2767                 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2768                     config.dv_flow_en) {
2769                         uint8_t reg_c_mask =
2770                                 config.hca_attr.qos.flow_meter_reg_c_ids;
2771                         /*
2772                          * Meter needs two REG_C's for color match and pre-sfx
2773                          * flow match. Here get the REG_C for color match.
2774                          * REG_C_0 and REG_C_1 is reserved for metadata feature.
2775                          */
2776                         reg_c_mask &= 0xfc;
2777                         if (__builtin_popcount(reg_c_mask) < 1) {
2778                                 priv->mtr_en = 0;
2779                                 DRV_LOG(WARNING, "No available register for"
2780                                         " meter.");
2781                         } else {
2782                                 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2783                                                       REG_C_0;
2784                                 priv->mtr_en = 1;
2785                                 priv->mtr_reg_share =
2786                                       config.hca_attr.qos.flow_meter_reg_share;
2787                                 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2788                                         priv->mtr_color_reg);
2789                         }
2790                 }
2791 #endif
2792         }
2793         if (config.mprq.enabled && mprq) {
2794                 if (config.mprq.stride_num_n &&
2795                     (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2796                      config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2797                         config.mprq.stride_num_n =
2798                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2799                                                 mprq_min_stride_num_n),
2800                                         mprq_max_stride_num_n);
2801                         DRV_LOG(WARNING,
2802                                 "the number of strides"
2803                                 " for Multi-Packet RQ is out of range,"
2804                                 " setting default value (%u)",
2805                                 1 << config.mprq.stride_num_n);
2806                 }
2807                 if (config.mprq.stride_size_n &&
2808                     (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2809                      config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2810                         config.mprq.stride_size_n =
2811                                 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2812                                                 mprq_min_stride_size_n),
2813                                         mprq_max_stride_size_n);
2814                         DRV_LOG(WARNING,
2815                                 "the size of a stride"
2816                                 " for Multi-Packet RQ is out of range,"
2817                                 " setting default value (%u)",
2818                                 1 << config.mprq.stride_size_n);
2819                 }
2820                 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2821                 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2822         } else if (config.mprq.enabled && !mprq) {
2823                 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2824                 config.mprq.enabled = 0;
2825         }
2826         if (config.max_dump_files_num == 0)
2827                 config.max_dump_files_num = 128;
2828         eth_dev = rte_eth_dev_allocate(name);
2829         if (eth_dev == NULL) {
2830                 DRV_LOG(ERR, "can not allocate rte ethdev");
2831                 err = ENOMEM;
2832                 goto error;
2833         }
2834         /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2835         eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2836         if (priv->representor) {
2837                 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2838                 eth_dev->data->representor_id = priv->representor_id;
2839         }
2840         /*
2841          * Store associated network device interface index. This index
2842          * is permanent throughout the lifetime of device. So, we may store
2843          * the ifindex here and use the cached value further.
2844          */
2845         MLX5_ASSERT(spawn->ifindex);
2846         priv->if_index = spawn->ifindex;
2847         eth_dev->data->dev_private = priv;
2848         priv->dev_data = eth_dev->data;
2849         eth_dev->data->mac_addrs = priv->mac;
2850         eth_dev->device = dpdk_dev;
2851         /* Configure the first MAC address by default. */
2852         if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2853                 DRV_LOG(ERR,
2854                         "port %u cannot get MAC address, is mlx5_en"
2855                         " loaded? (errno: %s)",
2856                         eth_dev->data->port_id, strerror(rte_errno));
2857                 err = ENODEV;
2858                 goto error;
2859         }
2860         DRV_LOG(INFO,
2861                 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2862                 eth_dev->data->port_id,
2863                 mac.addr_bytes[0], mac.addr_bytes[1],
2864                 mac.addr_bytes[2], mac.addr_bytes[3],
2865                 mac.addr_bytes[4], mac.addr_bytes[5]);
2866 #ifdef RTE_LIBRTE_MLX5_DEBUG
2867         {
2868                 char ifname[IF_NAMESIZE];
2869
2870                 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2871                         DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2872                                 eth_dev->data->port_id, ifname);
2873                 else
2874                         DRV_LOG(DEBUG, "port %u ifname is unknown",
2875                                 eth_dev->data->port_id);
2876         }
2877 #endif
2878         /* Get actual MTU if possible. */
2879         err = mlx5_get_mtu(eth_dev, &priv->mtu);
2880         if (err) {
2881                 err = rte_errno;
2882                 goto error;
2883         }
2884         DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2885                 priv->mtu);
2886         /* Initialize burst functions to prevent crashes before link-up. */
2887         eth_dev->rx_pkt_burst = removed_rx_burst;
2888         eth_dev->tx_pkt_burst = removed_tx_burst;
2889         eth_dev->dev_ops = &mlx5_dev_ops;
2890         /* Register MAC address. */
2891         claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2892         if (config.vf && config.vf_nl_en)
2893                 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2894                                       mlx5_ifindex(eth_dev),
2895                                       eth_dev->data->mac_addrs,
2896                                       MLX5_MAX_MAC_ADDRESSES);
2897         priv->flows = 0;
2898         priv->ctrl_flows = 0;
2899         TAILQ_INIT(&priv->flow_meters);
2900         TAILQ_INIT(&priv->flow_meter_profiles);
2901         /* Hint libmlx5 to use PMD allocator for data plane resources */
2902         struct mlx5dv_ctx_allocators alctr = {
2903                 .alloc = &mlx5_alloc_verbs_buf,
2904                 .free = &mlx5_free_verbs_buf,
2905                 .data = priv,
2906         };
2907         mlx5_glue->dv_set_context_attr(sh->ctx,
2908                                        MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2909                                        (void *)((uintptr_t)&alctr));
2910         /* Bring Ethernet device up. */
2911         DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2912                 eth_dev->data->port_id);
2913         mlx5_set_link_up(eth_dev);
2914         /*
2915          * Even though the interrupt handler is not installed yet,
2916          * interrupts will still trigger on the async_fd from
2917          * Verbs context returned by ibv_open_device().
2918          */
2919         mlx5_link_update(eth_dev, 0);
2920 #ifdef HAVE_MLX5DV_DR_ESWITCH
2921         if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2922               (switch_info->representor || switch_info->master)))
2923                 config.dv_esw_en = 0;
2924 #else
2925         config.dv_esw_en = 0;
2926 #endif
2927         /* Detect minimal data bytes to inline. */
2928         mlx5_set_min_inline(spawn, &config);
2929         /* Store device configuration on private structure. */
2930         priv->config = config;
2931         /* Create context for virtual machine VLAN workaround. */
2932         priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2933         if (config.dv_flow_en) {
2934                 err = mlx5_alloc_shared_dr(priv);
2935                 if (err)
2936                         goto error;
2937                 /*
2938                  * RSS id is shared with meter flow id. Meter flow id can only
2939                  * use the 24 MSB of the register.
2940                  */
2941                 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2942                                      MLX5_MTR_COLOR_BITS);
2943                 if (!priv->qrss_id_pool) {
2944                         DRV_LOG(ERR, "can't create flow id pool");
2945                         err = ENOMEM;
2946                         goto error;
2947                 }
2948         }
2949         /* Supported Verbs flow priority number detection. */
2950         err = mlx5_flow_discover_priorities(eth_dev);
2951         if (err < 0) {
2952                 err = -err;
2953                 goto error;
2954         }
2955         priv->config.flow_prio = err;
2956         if (!priv->config.dv_esw_en &&
2957             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2958                 DRV_LOG(WARNING, "metadata mode %u is not supported "
2959                                  "(no E-Switch)", priv->config.dv_xmeta_en);
2960                 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2961         }
2962         mlx5_set_metadata_mask(eth_dev);
2963         if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2964             !priv->sh->dv_regc0_mask) {
2965                 DRV_LOG(ERR, "metadata mode %u is not supported "
2966                              "(no metadata reg_c[0] is available)",
2967                              priv->config.dv_xmeta_en);
2968                         err = ENOTSUP;
2969                         goto error;
2970         }
2971         /*
2972          * Allocate the buffer for flow creating, just once.
2973          * The allocation must be done before any flow creating.
2974          */
2975         mlx5_flow_alloc_intermediate(eth_dev);
2976         /* Query availibility of metadata reg_c's. */
2977         err = mlx5_flow_discover_mreg_c(eth_dev);
2978         if (err < 0) {
2979                 err = -err;
2980                 goto error;
2981         }
2982         if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2983                 DRV_LOG(DEBUG,
2984                         "port %u extensive metadata register is not supported",
2985                         eth_dev->data->port_id);
2986                 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2987                         DRV_LOG(ERR, "metadata mode %u is not supported "
2988                                      "(no metadata registers available)",
2989                                      priv->config.dv_xmeta_en);
2990                         err = ENOTSUP;
2991                         goto error;
2992                 }
2993         }
2994         if (priv->config.dv_flow_en &&
2995             priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2996             mlx5_flow_ext_mreg_supported(eth_dev) &&
2997             priv->sh->dv_regc0_mask) {
2998                 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2999                                                       MLX5_FLOW_MREG_HTABLE_SZ);
3000                 if (!priv->mreg_cp_tbl) {
3001                         err = ENOMEM;
3002                         goto error;
3003                 }
3004         }
3005         return eth_dev;
3006 error:
3007         if (priv) {
3008                 if (priv->mreg_cp_tbl)
3009                         mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
3010                 if (priv->sh)
3011                         mlx5_free_shared_dr(priv);
3012                 if (priv->nl_socket_route >= 0)
3013                         close(priv->nl_socket_route);
3014                 if (priv->nl_socket_rdma >= 0)
3015                         close(priv->nl_socket_rdma);
3016                 if (priv->vmwa_context)
3017                         mlx5_vlan_vmwa_exit(priv->vmwa_context);
3018                 if (priv->qrss_id_pool)
3019                         mlx5_flow_id_pool_release(priv->qrss_id_pool);
3020                 if (own_domain_id)
3021                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
3022                 rte_free(priv);
3023                 if (eth_dev != NULL)
3024                         eth_dev->data->dev_private = NULL;
3025         }
3026         if (eth_dev != NULL) {
3027                 /* mac_addrs must not be freed alone because part of dev_private */
3028                 eth_dev->data->mac_addrs = NULL;
3029                 rte_eth_dev_release_port(eth_dev);
3030         }
3031         if (sh)
3032                 mlx5_free_shared_ibctx(sh);
3033         MLX5_ASSERT(err > 0);
3034         rte_errno = err;
3035         return NULL;
3036 }
3037
3038 /**
3039  * Comparison callback to sort device data.
3040  *
3041  * This is meant to be used with qsort().
3042  *
3043  * @param a[in]
3044  *   Pointer to pointer to first data object.
3045  * @param b[in]
3046  *   Pointer to pointer to second data object.
3047  *
3048  * @return
3049  *   0 if both objects are equal, less than 0 if the first argument is less
3050  *   than the second, greater than 0 otherwise.
3051  */
3052 static int
3053 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3054 {
3055         const struct mlx5_switch_info *si_a =
3056                 &((const struct mlx5_dev_spawn_data *)a)->info;
3057         const struct mlx5_switch_info *si_b =
3058                 &((const struct mlx5_dev_spawn_data *)b)->info;
3059         int ret;
3060
3061         /* Master device first. */
3062         ret = si_b->master - si_a->master;
3063         if (ret)
3064                 return ret;
3065         /* Then representor devices. */
3066         ret = si_b->representor - si_a->representor;
3067         if (ret)
3068                 return ret;
3069         /* Unidentified devices come last in no specific order. */
3070         if (!si_a->representor)
3071                 return 0;
3072         /* Order representors by name. */
3073         return si_a->port_name - si_b->port_name;
3074 }
3075
3076 /**
3077  * Match PCI information for possible slaves of bonding device.
3078  *
3079  * @param[in] ibv_dev
3080  *   Pointer to Infiniband device structure.
3081  * @param[in] pci_dev
3082  *   Pointer to PCI device structure to match PCI address.
3083  * @param[in] nl_rdma
3084  *   Netlink RDMA group socket handle.
3085  *
3086  * @return
3087  *   negative value if no bonding device found, otherwise
3088  *   positive index of slave PF in bonding.
3089  */
3090 static int
3091 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3092                            const struct rte_pci_device *pci_dev,
3093                            int nl_rdma)
3094 {
3095         char ifname[IF_NAMESIZE + 1];
3096         unsigned int ifindex;
3097         unsigned int np, i;
3098         FILE *file = NULL;
3099         int pf = -1;
3100
3101         /*
3102          * Try to get master device name. If something goes
3103          * wrong suppose the lack of kernel support and no
3104          * bonding devices.
3105          */
3106         if (nl_rdma < 0)
3107                 return -1;
3108         if (!strstr(ibv_dev->name, "bond"))
3109                 return -1;
3110         np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3111         if (!np)
3112                 return -1;
3113         /*
3114          * The Master device might not be on the predefined
3115          * port (not on port index 1, it is not garanted),
3116          * we have to scan all Infiniband device port and
3117          * find master.
3118          */
3119         for (i = 1; i <= np; ++i) {
3120                 /* Check whether Infiniband port is populated. */
3121                 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3122                 if (!ifindex)
3123                         continue;
3124                 if (!if_indextoname(ifindex, ifname))
3125                         continue;
3126                 /* Try to read bonding slave names from sysfs. */
3127                 MKSTR(slaves,
3128                       "/sys/class/net/%s/master/bonding/slaves", ifname);
3129                 file = fopen(slaves, "r");
3130                 if (file)
3131                         break;
3132         }
3133         if (!file)
3134                 return -1;
3135         /* Use safe format to check maximal buffer length. */
3136         MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3137         while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3138                 char tmp_str[IF_NAMESIZE + 32];
3139                 struct rte_pci_addr pci_addr;
3140                 struct mlx5_switch_info info;
3141
3142                 /* Process slave interface names in the loop. */
3143                 snprintf(tmp_str, sizeof(tmp_str),
3144                          "/sys/class/net/%s", ifname);
3145                 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3146                         DRV_LOG(WARNING, "can not get PCI address"
3147                                          " for netdev \"%s\"", ifname);
3148                         continue;
3149                 }
3150                 if (pci_dev->addr.domain != pci_addr.domain ||
3151                     pci_dev->addr.bus != pci_addr.bus ||
3152                     pci_dev->addr.devid != pci_addr.devid ||
3153                     pci_dev->addr.function != pci_addr.function)
3154                         continue;
3155                 /* Slave interface PCI address match found. */
3156                 fclose(file);
3157                 snprintf(tmp_str, sizeof(tmp_str),
3158                          "/sys/class/net/%s/phys_port_name", ifname);
3159                 file = fopen(tmp_str, "rb");
3160                 if (!file)
3161                         break;
3162                 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3163                 if (fscanf(file, "%32s", tmp_str) == 1)
3164                         mlx5_translate_port_name(tmp_str, &info);
3165                 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3166                     info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3167                         pf = info.port_name;
3168                 break;
3169         }
3170         if (file)
3171                 fclose(file);
3172         return pf;
3173 }
3174
3175 /**
3176  * DPDK callback to register a PCI device.
3177  *
3178  * This function spawns Ethernet devices out of a given PCI device.
3179  *
3180  * @param[in] pci_drv
3181  *   PCI driver structure (mlx5_driver).
3182  * @param[in] pci_dev
3183  *   PCI device information.
3184  *
3185  * @return
3186  *   0 on success, a negative errno value otherwise and rte_errno is set.
3187  */
3188 static int
3189 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3190                struct rte_pci_device *pci_dev)
3191 {
3192         struct ibv_device **ibv_list;
3193         /*
3194          * Number of found IB Devices matching with requested PCI BDF.
3195          * nd != 1 means there are multiple IB devices over the same
3196          * PCI device and we have representors and master.
3197          */
3198         unsigned int nd = 0;
3199         /*
3200          * Number of found IB device Ports. nd = 1 and np = 1..n means
3201          * we have the single multiport IB device, and there may be
3202          * representors attached to some of found ports.
3203          */
3204         unsigned int np = 0;
3205         /*
3206          * Number of DPDK ethernet devices to Spawn - either over
3207          * multiple IB devices or multiple ports of single IB device.
3208          * Actually this is the number of iterations to spawn.
3209          */
3210         unsigned int ns = 0;
3211         /*
3212          * Bonding device
3213          *   < 0 - no bonding device (single one)
3214          *  >= 0 - bonding device (value is slave PF index)
3215          */
3216         int bd = -1;
3217         struct mlx5_dev_spawn_data *list = NULL;
3218         struct mlx5_dev_config dev_config;
3219         int ret;
3220
3221         if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3222                 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3223                         " driver.");
3224                 return 1;
3225         }
3226         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3227                 mlx5_pmd_socket_init();
3228         ret = mlx5_init_once();
3229         if (ret) {
3230                 DRV_LOG(ERR, "unable to init PMD global data: %s",
3231                         strerror(rte_errno));
3232                 return -rte_errno;
3233         }
3234         MLX5_ASSERT(pci_drv == &mlx5_driver);
3235         errno = 0;
3236         ibv_list = mlx5_glue->get_device_list(&ret);
3237         if (!ibv_list) {
3238                 rte_errno = errno ? errno : ENOSYS;
3239                 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3240                 return -rte_errno;
3241         }
3242         /*
3243          * First scan the list of all Infiniband devices to find
3244          * matching ones, gathering into the list.
3245          */
3246         struct ibv_device *ibv_match[ret + 1];
3247         int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3248         int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3249         unsigned int i;
3250
3251         while (ret-- > 0) {
3252                 struct rte_pci_addr pci_addr;
3253
3254                 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3255                 bd = mlx5_device_bond_pci_match
3256                                 (ibv_list[ret], pci_dev, nl_rdma);
3257                 if (bd >= 0) {
3258                         /*
3259                          * Bonding device detected. Only one match is allowed,
3260                          * the bonding is supported over multi-port IB device,
3261                          * there should be no matches on representor PCI
3262                          * functions or non VF LAG bonding devices with
3263                          * specified address.
3264                          */
3265                         if (nd) {
3266                                 DRV_LOG(ERR,
3267                                         "multiple PCI match on bonding device"
3268                                         "\"%s\" found", ibv_list[ret]->name);
3269                                 rte_errno = ENOENT;
3270                                 ret = -rte_errno;
3271                                 goto exit;
3272                         }
3273                         DRV_LOG(INFO, "PCI information matches for"
3274                                       " slave %d bonding device \"%s\"",
3275                                       bd, ibv_list[ret]->name);
3276                         ibv_match[nd++] = ibv_list[ret];
3277                         break;
3278                 }
3279                 if (mlx5_dev_to_pci_addr
3280                         (ibv_list[ret]->ibdev_path, &pci_addr))
3281                         continue;
3282                 if (pci_dev->addr.domain != pci_addr.domain ||
3283                     pci_dev->addr.bus != pci_addr.bus ||
3284                     pci_dev->addr.devid != pci_addr.devid ||
3285                     pci_dev->addr.function != pci_addr.function)
3286                         continue;
3287                 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3288                         ibv_list[ret]->name);
3289                 ibv_match[nd++] = ibv_list[ret];
3290         }
3291         ibv_match[nd] = NULL;
3292         if (!nd) {
3293                 /* No device matches, just complain and bail out. */
3294                 DRV_LOG(WARNING,
3295                         "no Verbs device matches PCI device " PCI_PRI_FMT ","
3296                         " are kernel drivers loaded?",
3297                         pci_dev->addr.domain, pci_dev->addr.bus,
3298                         pci_dev->addr.devid, pci_dev->addr.function);
3299                 rte_errno = ENOENT;
3300                 ret = -rte_errno;
3301                 goto exit;
3302         }
3303         if (nd == 1) {
3304                 /*
3305                  * Found single matching device may have multiple ports.
3306                  * Each port may be representor, we have to check the port
3307                  * number and check the representors existence.
3308                  */
3309                 if (nl_rdma >= 0)
3310                         np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3311                 if (!np)
3312                         DRV_LOG(WARNING, "can not get IB device \"%s\""
3313                                          " ports number", ibv_match[0]->name);
3314                 if (bd >= 0 && !np) {
3315                         DRV_LOG(ERR, "can not get ports"
3316                                      " for bonding device");
3317                         rte_errno = ENOENT;
3318                         ret = -rte_errno;
3319                         goto exit;
3320                 }
3321         }
3322 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3323         if (bd >= 0) {
3324                 /*
3325                  * This may happen if there is VF LAG kernel support and
3326                  * application is compiled with older rdma_core library.
3327                  */
3328                 DRV_LOG(ERR,
3329                         "No kernel/verbs support for VF LAG bonding found.");
3330                 rte_errno = ENOTSUP;
3331                 ret = -rte_errno;
3332                 goto exit;
3333         }
3334 #endif
3335         /*
3336          * Now we can determine the maximal
3337          * amount of devices to be spawned.
3338          */
3339         list = rte_zmalloc("device spawn data",
3340                          sizeof(struct mlx5_dev_spawn_data) *
3341                          (np ? np : nd),
3342                          RTE_CACHE_LINE_SIZE);
3343         if (!list) {
3344                 DRV_LOG(ERR, "spawn data array allocation failure");
3345                 rte_errno = ENOMEM;
3346                 ret = -rte_errno;
3347                 goto exit;
3348         }
3349         if (bd >= 0 || np > 1) {
3350                 /*
3351                  * Single IB device with multiple ports found,
3352                  * it may be E-Switch master device and representors.
3353                  * We have to perform identification trough the ports.
3354                  */
3355                 MLX5_ASSERT(nl_rdma >= 0);
3356                 MLX5_ASSERT(ns == 0);
3357                 MLX5_ASSERT(nd == 1);
3358                 MLX5_ASSERT(np);
3359                 for (i = 1; i <= np; ++i) {
3360                         list[ns].max_port = np;
3361                         list[ns].ibv_port = i;
3362                         list[ns].ibv_dev = ibv_match[0];
3363                         list[ns].eth_dev = NULL;
3364                         list[ns].pci_dev = pci_dev;
3365                         list[ns].pf_bond = bd;
3366                         list[ns].ifindex = mlx5_nl_ifindex
3367                                         (nl_rdma, list[ns].ibv_dev->name, i);
3368                         if (!list[ns].ifindex) {
3369                                 /*
3370                                  * No network interface index found for the
3371                                  * specified port, it means there is no
3372                                  * representor on this port. It's OK,
3373                                  * there can be disabled ports, for example
3374                                  * if sriov_numvfs < sriov_totalvfs.
3375                                  */
3376                                 continue;
3377                         }
3378                         ret = -1;
3379                         if (nl_route >= 0)
3380                                 ret = mlx5_nl_switch_info
3381                                                (nl_route,
3382                                                 list[ns].ifindex,
3383                                                 &list[ns].info);
3384                         if (ret || (!list[ns].info.representor &&
3385                                     !list[ns].info.master)) {
3386                                 /*
3387                                  * We failed to recognize representors with
3388                                  * Netlink, let's try to perform the task
3389                                  * with sysfs.
3390                                  */
3391                                 ret =  mlx5_sysfs_switch_info
3392                                                 (list[ns].ifindex,
3393                                                  &list[ns].info);
3394                         }
3395                         if (!ret && bd >= 0) {
3396                                 switch (list[ns].info.name_type) {
3397                                 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3398                                         if (list[ns].info.port_name == bd)
3399                                                 ns++;
3400                                         break;
3401                                 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3402                                         if (list[ns].info.pf_num == bd)
3403                                                 ns++;
3404                                         break;
3405                                 default:
3406                                         break;
3407                                 }
3408                                 continue;
3409                         }
3410                         if (!ret && (list[ns].info.representor ^
3411                                      list[ns].info.master))
3412                                 ns++;
3413                 }
3414                 if (!ns) {
3415                         DRV_LOG(ERR,
3416                                 "unable to recognize master/representors"
3417                                 " on the IB device with multiple ports");
3418                         rte_errno = ENOENT;
3419                         ret = -rte_errno;
3420                         goto exit;
3421                 }
3422         } else {
3423                 /*
3424                  * The existence of several matching entries (nd > 1) means
3425                  * port representors have been instantiated. No existing Verbs
3426                  * call nor sysfs entries can tell them apart, this can only
3427                  * be done through Netlink calls assuming kernel drivers are
3428                  * recent enough to support them.
3429                  *
3430                  * In the event of identification failure through Netlink,
3431                  * try again through sysfs, then:
3432                  *
3433                  * 1. A single IB device matches (nd == 1) with single
3434                  *    port (np=0/1) and is not a representor, assume
3435                  *    no switch support.
3436                  *
3437                  * 2. Otherwise no safe assumptions can be made;
3438                  *    complain louder and bail out.
3439                  */
3440                 np = 1;
3441                 for (i = 0; i != nd; ++i) {
3442                         memset(&list[ns].info, 0, sizeof(list[ns].info));
3443                         list[ns].max_port = 1;
3444                         list[ns].ibv_port = 1;
3445                         list[ns].ibv_dev = ibv_match[i];
3446                         list[ns].eth_dev = NULL;
3447                         list[ns].pci_dev = pci_dev;
3448                         list[ns].pf_bond = -1;
3449                         list[ns].ifindex = 0;
3450                         if (nl_rdma >= 0)
3451                                 list[ns].ifindex = mlx5_nl_ifindex
3452                                         (nl_rdma, list[ns].ibv_dev->name, 1);
3453                         if (!list[ns].ifindex) {
3454                                 char ifname[IF_NAMESIZE];
3455
3456                                 /*
3457                                  * Netlink failed, it may happen with old
3458                                  * ib_core kernel driver (before 4.16).
3459                                  * We can assume there is old driver because
3460                                  * here we are processing single ports IB
3461                                  * devices. Let's try sysfs to retrieve
3462                                  * the ifindex. The method works for
3463                                  * master device only.
3464                                  */
3465                                 if (nd > 1) {
3466                                         /*
3467                                          * Multiple devices found, assume
3468                                          * representors, can not distinguish
3469                                          * master/representor and retrieve
3470                                          * ifindex via sysfs.
3471                                          */
3472                                         continue;
3473                                 }
3474                                 ret = mlx5_get_master_ifname
3475                                         (ibv_match[i]->ibdev_path, &ifname);
3476                                 if (!ret)
3477                                         list[ns].ifindex =
3478                                                 if_nametoindex(ifname);
3479                                 if (!list[ns].ifindex) {
3480                                         /*
3481                                          * No network interface index found
3482                                          * for the specified device, it means
3483                                          * there it is neither representor
3484                                          * nor master.
3485                                          */
3486                                         continue;
3487                                 }
3488                         }
3489                         ret = -1;
3490                         if (nl_route >= 0)
3491                                 ret = mlx5_nl_switch_info
3492                                                (nl_route,
3493                                                 list[ns].ifindex,
3494                                                 &list[ns].info);
3495                         if (ret || (!list[ns].info.representor &&
3496                                     !list[ns].info.master)) {
3497                                 /*
3498                                  * We failed to recognize representors with
3499                                  * Netlink, let's try to perform the task
3500                                  * with sysfs.
3501                                  */
3502                                 ret =  mlx5_sysfs_switch_info
3503                                                 (list[ns].ifindex,
3504                                                  &list[ns].info);
3505                         }
3506                         if (!ret && (list[ns].info.representor ^
3507                                      list[ns].info.master)) {
3508                                 ns++;
3509                         } else if ((nd == 1) &&
3510                                    !list[ns].info.representor &&
3511                                    !list[ns].info.master) {
3512                                 /*
3513                                  * Single IB device with
3514                                  * one physical port and
3515                                  * attached network device.
3516                                  * May be SRIOV is not enabled
3517                                  * or there is no representors.
3518                                  */
3519                                 DRV_LOG(INFO, "no E-Switch support detected");
3520                                 ns++;
3521                                 break;
3522                         }
3523                 }
3524                 if (!ns) {
3525                         DRV_LOG(ERR,
3526                                 "unable to recognize master/representors"
3527                                 " on the multiple IB devices");
3528                         rte_errno = ENOENT;
3529                         ret = -rte_errno;
3530                         goto exit;
3531                 }
3532         }
3533         MLX5_ASSERT(ns);
3534         /*
3535          * Sort list to probe devices in natural order for users convenience
3536          * (i.e. master first, then representors from lowest to highest ID).
3537          */
3538         qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3539         /* Default configuration. */
3540         dev_config = (struct mlx5_dev_config){
3541                 .hw_padding = 0,
3542                 .mps = MLX5_ARG_UNSET,
3543                 .dbnc = MLX5_ARG_UNSET,
3544                 .rx_vec_en = 1,
3545                 .txq_inline_max = MLX5_ARG_UNSET,
3546                 .txq_inline_min = MLX5_ARG_UNSET,
3547                 .txq_inline_mpw = MLX5_ARG_UNSET,
3548                 .txqs_inline = MLX5_ARG_UNSET,
3549                 .vf_nl_en = 1,
3550                 .mr_ext_memseg_en = 1,
3551                 .mprq = {
3552                         .enabled = 0, /* Disabled by default. */
3553                         .stride_num_n = 0,
3554                         .stride_size_n = 0,
3555                         .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3556                         .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3557                 },
3558                 .dv_esw_en = 1,
3559                 .dv_flow_en = 1,
3560                 .log_hp_size = MLX5_ARG_UNSET,
3561         };
3562         /* Device specific configuration. */
3563         switch (pci_dev->id.device_id) {
3564         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3565         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3566         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3567         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3568         case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3569         case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3570         case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3571                 dev_config.vf = 1;
3572                 break;
3573         default:
3574                 break;
3575         }
3576         for (i = 0; i != ns; ++i) {
3577                 uint32_t restore;
3578
3579                 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3580                                                  &list[i],
3581                                                  dev_config);
3582                 if (!list[i].eth_dev) {
3583                         if (rte_errno != EBUSY && rte_errno != EEXIST)
3584                                 break;
3585                         /* Device is disabled or already spawned. Ignore it. */
3586                         continue;
3587                 }
3588                 restore = list[i].eth_dev->data->dev_flags;
3589                 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3590                 /* Restore non-PCI flags cleared by the above call. */
3591                 list[i].eth_dev->data->dev_flags |= restore;
3592                 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3593                 rte_eth_dev_probing_finish(list[i].eth_dev);
3594         }
3595         if (i != ns) {
3596                 DRV_LOG(ERR,
3597                         "probe of PCI device " PCI_PRI_FMT " aborted after"
3598                         " encountering an error: %s",
3599                         pci_dev->addr.domain, pci_dev->addr.bus,
3600                         pci_dev->addr.devid, pci_dev->addr.function,
3601                         strerror(rte_errno));
3602                 ret = -rte_errno;
3603                 /* Roll back. */
3604                 while (i--) {
3605                         if (!list[i].eth_dev)
3606                                 continue;
3607                         mlx5_dev_close(list[i].eth_dev);
3608                         /* mac_addrs must not be freed because in dev_private */
3609                         list[i].eth_dev->data->mac_addrs = NULL;
3610                         claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3611                 }
3612                 /* Restore original error. */
3613                 rte_errno = -ret;
3614         } else {
3615                 ret = 0;
3616         }
3617 exit:
3618         /*
3619          * Do the routine cleanup:
3620          * - close opened Netlink sockets
3621          * - free allocated spawn data array
3622          * - free the Infiniband device list
3623          */
3624         if (nl_rdma >= 0)
3625                 close(nl_rdma);
3626         if (nl_route >= 0)
3627                 close(nl_route);
3628         if (list)
3629                 rte_free(list);
3630         MLX5_ASSERT(ibv_list);
3631         mlx5_glue->free_device_list(ibv_list);
3632         return ret;
3633 }
3634
3635 /**
3636  * Look for the ethernet device belonging to mlx5 driver.
3637  *
3638  * @param[in] port_id
3639  *   port_id to start looking for device.
3640  * @param[in] pci_dev
3641  *   Pointer to the hint PCI device. When device is being probed
3642  *   the its siblings (master and preceding representors might
3643  *   not have assigned driver yet (because the mlx5_pci_probe()
3644  *   is not completed yet, for this case match on hint PCI
3645  *   device may be used to detect sibling device.
3646  *
3647  * @return
3648  *   port_id of found device, RTE_MAX_ETHPORT if not found.
3649  */
3650 uint16_t
3651 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3652 {
3653         while (port_id < RTE_MAX_ETHPORTS) {
3654                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3655
3656                 if (dev->state != RTE_ETH_DEV_UNUSED &&
3657                     dev->device &&
3658                     (dev->device == &pci_dev->device ||
3659                      (dev->device->driver &&
3660                      dev->device->driver->name &&
3661                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3662                         break;
3663                 port_id++;
3664         }
3665         if (port_id >= RTE_MAX_ETHPORTS)
3666                 return RTE_MAX_ETHPORTS;
3667         return port_id;
3668 }
3669
3670 /**
3671  * DPDK callback to remove a PCI device.
3672  *
3673  * This function removes all Ethernet devices belong to a given PCI device.
3674  *
3675  * @param[in] pci_dev
3676  *   Pointer to the PCI device.
3677  *
3678  * @return
3679  *   0 on success, the function cannot fail.
3680  */
3681 static int
3682 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3683 {
3684         uint16_t port_id;
3685
3686         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3687                 rte_eth_dev_close(port_id);
3688         return 0;
3689 }
3690
3691 static const struct rte_pci_id mlx5_pci_id_map[] = {
3692         {
3693                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3694                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3695         },
3696         {
3697                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3698                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3699         },
3700         {
3701                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3702                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3703         },
3704         {
3705                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3706                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3707         },
3708         {
3709                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3710                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3711         },
3712         {
3713                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3714                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3715         },
3716         {
3717                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3718                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3719         },
3720         {
3721                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3722                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3723         },
3724         {
3725                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3726                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3727         },
3728         {
3729                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3730                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3731         },
3732         {
3733                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3734                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3735         },
3736         {
3737                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3738                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3739         },
3740         {
3741                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3742                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3743         },
3744         {
3745                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3746                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3747         },
3748         {
3749                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3750                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3751         },
3752         {
3753                 .vendor_id = 0
3754         }
3755 };
3756
3757 static struct rte_pci_driver mlx5_driver = {
3758         .driver = {
3759                 .name = MLX5_DRIVER_NAME
3760         },
3761         .id_table = mlx5_pci_id_map,
3762         .probe = mlx5_pci_probe,
3763         .remove = mlx5_pci_remove,
3764         .dma_map = mlx5_dma_map,
3765         .dma_unmap = mlx5_dma_unmap,
3766         .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3767                      RTE_PCI_DRV_PROBE_AGAIN,
3768 };
3769
3770 /**
3771  * Driver initialization routine.
3772  */
3773 RTE_INIT(rte_mlx5_pmd_init)
3774 {
3775         /* Initialize driver log type. */
3776         mlx5_logtype = rte_log_register("pmd.net.mlx5");
3777         if (mlx5_logtype >= 0)
3778                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3779
3780         /* Build the static tables for Verbs conversion. */
3781         mlx5_set_ptype_table();
3782         mlx5_set_cksum_table();
3783         mlx5_set_swp_types_table();
3784         if (mlx5_glue)
3785                 rte_pci_register(&mlx5_driver);
3786 }
3787
3788 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3789 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3790 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");