1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_mp.h>
43 #include "mlx5_defs.h"
45 #include "mlx5_utils.h"
46 #include "mlx5_rxtx.h"
47 #include "mlx5_autoconf.h"
49 #include "mlx5_flow.h"
50 #include "rte_pmd_mlx5.h"
52 /* Device parameter to enable RX completion queue compression. */
53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
55 /* Device parameter to enable RX completion entry padding to 128B. */
56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
58 /* Device parameter to enable padding Rx packet to cacheline size. */
59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
61 /* Device parameter to enable Multi-Packet Rx queue. */
62 #define MLX5_RX_MPRQ_EN "mprq_en"
64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
76 /* Device parameter to configure inline send. Deprecated, ignored.*/
77 #define MLX5_TXQ_INLINE "txq_inline"
79 /* Device parameter to limit packet size to inline with ordinary SEND. */
80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
82 /* Device parameter to configure minimal data size to inline. */
83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
89 * Device parameter to configure the number of TX queues threshold for
90 * enabling inline send.
92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
95 * Device parameter to configure the number of TX queues threshold for
96 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
100 /* Device parameter to enable multi-packet send WQEs. */
101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
104 * Device parameter to force doorbell register mapping
105 * to non-cahed region eliminating the extra write memory barrier.
107 #define MLX5_TX_DB_NC "tx_db_nc"
110 * Device parameter to include 2 dsegs in the title WQEBB.
111 * Deprecated, ignored.
113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
116 * Device parameter to limit the size of inlining packet.
117 * Deprecated, ignored.
119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
122 * Device parameter to enable hardware Tx vector.
123 * Deprecated, ignored (no vectorized Tx routines anymore).
125 #define MLX5_TX_VEC_EN "tx_vec_en"
127 /* Device parameter to enable hardware Rx vector. */
128 #define MLX5_RX_VEC_EN "rx_vec_en"
130 /* Allow L3 VXLAN flow creation. */
131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
133 /* Activate DV E-Switch flow steering. */
134 #define MLX5_DV_ESW_EN "dv_esw_en"
136 /* Activate DV flow steering. */
137 #define MLX5_DV_FLOW_EN "dv_flow_en"
139 /* Enable extensive flow metadata support. */
140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
142 /* Activate Netlink support in VF mode. */
143 #define MLX5_VF_NL_EN "vf_nl_en"
145 /* Enable extending memsegs when creating a MR. */
146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
148 /* Select port representors to instantiate. */
149 #define MLX5_REPRESENTOR "representor"
151 /* Device parameter to configure the maximum number of dump files per queue. */
152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
154 /* Configure timeout of LRO session (in microseconds). */
155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
158 * Device parameter to configure the total data buffer size for a single
159 * hairpin queue (logarithm value).
161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
163 #ifndef HAVE_IBV_MLX5_MOD_MPW
164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
174 /* Shared memory between primary and secondary processes. */
175 struct mlx5_shared_data *mlx5_shared_data;
177 /* Spinlock for mlx5_shared_data allocation. */
178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
180 /* Process local data for secondary processes. */
181 static struct mlx5_local_data mlx5_local_data;
183 /** Driver-specific log messages type. */
186 /** Data associated with devices to spawn. */
187 struct mlx5_dev_spawn_data {
188 uint32_t ifindex; /**< Network interface index. */
189 uint32_t max_port; /**< IB device maximal port index. */
190 uint32_t ibv_port; /**< IB device physical port index. */
191 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
192 struct mlx5_switch_info info; /**< Switch information. */
193 struct ibv_device *ibv_dev; /**< Associated IB device. */
194 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
195 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
204 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
210 .malloc = rte_malloc_socket,
212 .type = "mlx5_encap_decap_ipool",
215 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
221 .malloc = rte_malloc_socket,
223 .type = "mlx5_push_vlan_ipool",
226 .size = sizeof(struct mlx5_flow_dv_tag_resource),
232 .malloc = rte_malloc_socket,
234 .type = "mlx5_tag_ipool",
237 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
243 .malloc = rte_malloc_socket,
245 .type = "mlx5_port_id_ipool",
248 .size = sizeof(struct mlx5_flow_tbl_data_entry),
254 .malloc = rte_malloc_socket,
256 .type = "mlx5_jump_ipool",
260 .size = sizeof(struct mlx5_flow_meter),
266 .malloc = rte_malloc_socket,
268 .type = "mlx5_meter_ipool",
271 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
277 .malloc = rte_malloc_socket,
279 .type = "mlx5_mcp_ipool",
282 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
288 .malloc = rte_malloc_socket,
290 .type = "mlx5_hrxq_ipool",
293 .size = sizeof(struct mlx5_flow_handle),
299 .malloc = rte_malloc_socket,
301 .type = "mlx5_flow_handle_ipool",
304 .size = sizeof(struct rte_flow),
308 .malloc = rte_malloc_socket,
310 .type = "rte_flow_ipool",
315 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
316 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
318 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
319 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
322 * Allocate ID pool structure.
325 * The maximum id can be allocated from the pool.
328 * Pointer to pool object, NULL value otherwise.
330 struct mlx5_flow_id_pool *
331 mlx5_flow_id_pool_alloc(uint32_t max_id)
333 struct mlx5_flow_id_pool *pool;
336 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
337 RTE_CACHE_LINE_SIZE);
339 DRV_LOG(ERR, "can't allocate id pool");
343 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
344 RTE_CACHE_LINE_SIZE);
346 DRV_LOG(ERR, "can't allocate mem for id pool");
350 pool->free_arr = mem;
351 pool->curr = pool->free_arr;
352 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
353 pool->base_index = 0;
354 pool->max_id = max_id;
362 * Release ID pool structure.
365 * Pointer to flow id pool object to free.
368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
370 rte_free(pool->free_arr);
378 * Pointer to flow id pool.
383 * 0 on success, error value otherwise.
386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
388 if (pool->curr == pool->free_arr) {
389 if (pool->base_index == pool->max_id) {
391 DRV_LOG(ERR, "no free id");
394 *id = ++pool->base_index;
397 *id = *(--pool->curr);
405 * Pointer to flow id pool.
410 * 0 on success, error value otherwise.
413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
419 if (pool->curr == pool->last) {
420 size = pool->curr - pool->free_arr;
421 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
422 MLX5_ASSERT(size2 > size);
423 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
425 DRV_LOG(ERR, "can't allocate mem for id pool");
429 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
430 rte_free(pool->free_arr);
431 pool->free_arr = mem;
432 pool->curr = pool->free_arr + size;
433 pool->last = pool->free_arr + size2;
441 * Initialize the counters management structure.
444 * Pointer to mlx5_ibv_shared object to free
447 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
451 TAILQ_INIT(&sh->cmng.flow_counters);
452 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
453 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
457 * Destroy all the resources allocated for a counter memory management.
460 * Pointer to the memory management structure.
463 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
465 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
467 LIST_REMOVE(mng, next);
468 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
469 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
474 * Close and release all the resources of the counters management.
477 * Pointer to mlx5_ibv_shared object to free.
480 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
482 struct mlx5_counter_stats_mem_mng *mng;
489 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
490 if (rte_errno != EINPROGRESS)
494 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
495 struct mlx5_flow_counter_pool *pool;
496 uint32_t batch = !!(i % 2);
498 if (!sh->cmng.ccont[i].pools)
500 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
505 (mlx5_devx_cmd_destroy(pool->min_dcs));
507 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
508 if (pool->counters_raw[j].action)
510 (mlx5_glue->destroy_flow_action
511 (pool->counters_raw[j].action));
512 if (!batch && MLX5_GET_POOL_CNT_EXT
514 claim_zero(mlx5_devx_cmd_destroy
515 (MLX5_GET_POOL_CNT_EXT
518 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
521 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
523 rte_free(sh->cmng.ccont[i].pools);
525 mng = LIST_FIRST(&sh->cmng.mem_mngs);
527 mlx5_flow_destroy_counter_stat_mem_mng(mng);
528 mng = LIST_FIRST(&sh->cmng.mem_mngs);
530 memset(&sh->cmng, 0, sizeof(sh->cmng));
534 * Initialize the flow resources' indexed mempool.
537 * Pointer to mlx5_ibv_shared object.
539 * Pointer to user dev config.
542 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh,
543 const struct mlx5_dev_config *config __rte_unused)
547 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
549 * While DV is supported, user chooses the verbs mode,
550 * the mlx5 flow handle size is different with the
551 * MLX5_FLOW_HANDLE_VERBS_SIZE.
553 if (!config->dv_flow_en)
554 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size =
555 MLX5_FLOW_HANDLE_VERBS_SIZE;
557 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
558 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]);
562 * Release the flow resources' indexed mempool.
565 * Pointer to mlx5_ibv_shared object.
568 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh)
572 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
573 mlx5_ipool_destroy(sh->ipool[i]);
577 * Extract pdn of PD object using DV API.
580 * Pointer to the verbs PD object.
582 * Pointer to the PD object number variable.
585 * 0 on success, error value otherwise.
587 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
589 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
591 struct mlx5dv_obj obj;
592 struct mlx5dv_pd pd_info;
596 obj.pd.out = &pd_info;
597 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
599 DRV_LOG(DEBUG, "Fail to get PD object info");
605 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
608 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
613 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
614 /* Get environment variable to store. */
615 env = getenv(MLX5_SHUT_UP_BF);
616 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
617 if (config->dbnc == MLX5_ARG_UNSET)
618 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
620 setenv(MLX5_SHUT_UP_BF,
621 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
626 mlx5_restore_doorbell_mapping_env(int value)
628 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
629 /* Restore the original environment variable state. */
630 if (value == MLX5_ARG_UNSET)
631 unsetenv(MLX5_SHUT_UP_BF);
633 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
637 * Allocate shared IB device context. If there is multiport device the
638 * master and representors will share this context, if there is single
639 * port dedicated IB device, the context will be used by only given
640 * port due to unification.
642 * Routine first searches the context for the specified IB device name,
643 * if found the shared context assumed and reference counter is incremented.
644 * If no context found the new one is created and initialized with specified
645 * IB device context and parameters.
648 * Pointer to the IB device attributes (name, port, etc).
650 * Pointer to device configuration structure.
653 * Pointer to mlx5_ibv_shared object on success,
654 * otherwise NULL and rte_errno is set.
656 static struct mlx5_ibv_shared *
657 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
658 const struct mlx5_dev_config *config)
660 struct mlx5_ibv_shared *sh;
664 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
665 struct mlx5_devx_tis_attr tis_attr = { 0 };
669 /* Secondary process should not create the shared context. */
670 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
671 pthread_mutex_lock(&mlx5_ibv_list_mutex);
672 /* Search for IB context by device name. */
673 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
674 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
679 /* No device found, we have to create new shared context. */
680 MLX5_ASSERT(spawn->max_port);
681 sh = rte_zmalloc("ethdev shared ib context",
682 sizeof(struct mlx5_ibv_shared) +
684 sizeof(struct mlx5_ibv_shared_port),
685 RTE_CACHE_LINE_SIZE);
687 DRV_LOG(ERR, "shared context allocation failure");
692 * Configure environment variable "MLX5_BF_SHUT_UP"
693 * before the device creation. The rdma_core library
694 * checks the variable at device creation and
695 * stores the result internally.
697 dbmap_env = mlx5_config_doorbell_mapping_env(config);
698 /* Try to open IB device with DV first, then usual Verbs. */
700 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
703 DRV_LOG(DEBUG, "DevX is supported");
704 /* The device is created, no need for environment. */
705 mlx5_restore_doorbell_mapping_env(dbmap_env);
707 /* The environment variable is still configured. */
708 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
709 err = errno ? errno : ENODEV;
711 * The environment variable is not needed anymore,
712 * all device creation attempts are completed.
714 mlx5_restore_doorbell_mapping_env(dbmap_env);
717 DRV_LOG(DEBUG, "DevX is NOT supported");
719 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
721 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
725 sh->max_port = spawn->max_port;
726 strncpy(sh->ibdev_name, sh->ctx->device->name,
727 sizeof(sh->ibdev_name));
728 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
729 sizeof(sh->ibdev_path));
730 pthread_mutex_init(&sh->intr_mutex, NULL);
732 * Setting port_id to max unallowed value means
733 * there is no interrupt subhandler installed for
734 * the given port index i.
736 for (i = 0; i < sh->max_port; i++) {
737 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
738 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
740 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
741 if (sh->pd == NULL) {
742 DRV_LOG(ERR, "PD allocation failure");
746 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
748 err = mlx5_get_pdn(sh->pd, &sh->pdn);
750 DRV_LOG(ERR, "Fail to extract pdn from PD");
753 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
755 DRV_LOG(ERR, "TD allocation failure");
759 tis_attr.transport_domain = sh->td->id;
760 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
762 DRV_LOG(ERR, "TIS allocation failure");
767 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
768 if (!sh->flow_id_pool) {
769 DRV_LOG(ERR, "can't create flow id pool");
773 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
775 * Once the device is added to the list of memory event
776 * callback, its global MR cache table cannot be expanded
777 * on the fly because of deadlock. If it overflows, lookup
778 * should be done by searching MR list linearly, which is slow.
780 * At this point the device is not added to the memory
781 * event list yet, context is just being created.
783 err = mlx5_mr_btree_init(&sh->share_cache.cache,
784 MLX5_MR_BTREE_CACHE_N * 2,
785 spawn->pci_dev->device.numa_node);
790 mlx5_flow_counters_mng_init(sh);
791 mlx5_flow_ipool_create(sh, config);
792 /* Add device to memory callback list. */
793 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
794 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
796 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
797 /* Add context to the global device list. */
798 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
800 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
803 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
806 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
808 claim_zero(mlx5_devx_cmd_destroy(sh->td));
810 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
812 claim_zero(mlx5_glue->close_device(sh->ctx));
813 if (sh->flow_id_pool)
814 mlx5_flow_id_pool_release(sh->flow_id_pool);
816 MLX5_ASSERT(err > 0);
822 * Free shared IB device context. Decrement counter and if zero free
823 * all allocated resources and close handles.
826 * Pointer to mlx5_ibv_shared object to free
829 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
831 pthread_mutex_lock(&mlx5_ibv_list_mutex);
832 #ifdef RTE_LIBRTE_MLX5_DEBUG
833 /* Check the object presence in the list. */
834 struct mlx5_ibv_shared *lctx;
836 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
841 DRV_LOG(ERR, "Freeing non-existing shared IB context");
846 MLX5_ASSERT(sh->refcnt);
847 /* Secondary process should not free the shared context. */
848 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
851 /* Remove from memory callback device list. */
852 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
853 LIST_REMOVE(sh, mem_event_cb);
854 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
855 /* Release created Memory Regions. */
856 mlx5_mr_release_cache(&sh->share_cache);
857 /* Remove context from the global device list. */
858 LIST_REMOVE(sh, next);
860 * Ensure there is no async event handler installed.
861 * Only primary process handles async device events.
863 mlx5_flow_counters_mng_close(sh);
864 mlx5_flow_ipool_destroy(sh);
865 MLX5_ASSERT(!sh->intr_cnt);
867 mlx5_intr_callback_unregister
868 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
869 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
870 if (sh->devx_intr_cnt) {
871 if (sh->intr_handle_devx.fd)
872 rte_intr_callback_unregister(&sh->intr_handle_devx,
873 mlx5_dev_interrupt_handler_devx, sh);
875 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
878 pthread_mutex_destroy(&sh->intr_mutex);
880 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
882 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
884 claim_zero(mlx5_devx_cmd_destroy(sh->td));
886 claim_zero(mlx5_glue->close_device(sh->ctx));
887 if (sh->flow_id_pool)
888 mlx5_flow_id_pool_release(sh->flow_id_pool);
891 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
895 * Destroy table hash list and all the root entries per domain.
898 * Pointer to the private device data structure.
901 mlx5_free_table_hash_list(struct mlx5_priv *priv)
903 struct mlx5_ibv_shared *sh = priv->sh;
904 struct mlx5_flow_tbl_data_entry *tbl_data;
905 union mlx5_flow_tbl_key table_key = {
913 struct mlx5_hlist_entry *pos;
917 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
919 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
921 MLX5_ASSERT(tbl_data);
922 mlx5_hlist_remove(sh->flow_tbls, pos);
925 table_key.direction = 1;
926 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
928 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
930 MLX5_ASSERT(tbl_data);
931 mlx5_hlist_remove(sh->flow_tbls, pos);
934 table_key.direction = 0;
935 table_key.domain = 1;
936 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
938 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
940 MLX5_ASSERT(tbl_data);
941 mlx5_hlist_remove(sh->flow_tbls, pos);
944 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
948 * Initialize flow table hash list and create the root tables entry
952 * Pointer to the private device data structure.
955 * Zero on success, positive error code otherwise.
958 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
960 struct mlx5_ibv_shared *sh = priv->sh;
961 char s[MLX5_HLIST_NAMESIZE];
965 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
966 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
967 if (!sh->flow_tbls) {
968 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
972 #ifndef HAVE_MLX5DV_DR
974 * In case we have not DR support, the zero tables should be created
975 * because DV expect to see them even if they cannot be created by
978 union mlx5_flow_tbl_key table_key = {
986 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
987 sizeof(*tbl_data), 0);
993 tbl_data->entry.key = table_key.v64;
994 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
997 rte_atomic32_init(&tbl_data->tbl.refcnt);
998 rte_atomic32_inc(&tbl_data->tbl.refcnt);
999 table_key.direction = 1;
1000 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1005 tbl_data->entry.key = table_key.v64;
1006 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1009 rte_atomic32_init(&tbl_data->tbl.refcnt);
1010 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1011 table_key.direction = 0;
1012 table_key.domain = 1;
1013 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1018 tbl_data->entry.key = table_key.v64;
1019 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1022 rte_atomic32_init(&tbl_data->tbl.refcnt);
1023 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1026 mlx5_free_table_hash_list(priv);
1027 #endif /* HAVE_MLX5DV_DR */
1032 * Initialize DR related data within private structure.
1033 * Routine checks the reference counter and does actual
1034 * resources creation/initialization only if counter is zero.
1037 * Pointer to the private device data structure.
1040 * Zero on success, positive error code otherwise.
1043 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
1045 struct mlx5_ibv_shared *sh = priv->sh;
1046 char s[MLX5_HLIST_NAMESIZE];
1050 err = mlx5_alloc_table_hash_list(priv);
1052 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
1053 (void *)sh->flow_tbls);
1056 /* Create tags hash list table. */
1057 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
1058 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
1059 if (!sh->tag_table) {
1060 DRV_LOG(ERR, "tags with hash creation failed.\n");
1064 #ifdef HAVE_MLX5DV_DR
1067 if (sh->dv_refcnt) {
1068 /* Shared DV/DR structures is already initialized. */
1070 priv->dr_shared = 1;
1073 /* Reference counter is zero, we should initialize structures. */
1074 domain = mlx5_glue->dr_create_domain(sh->ctx,
1075 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
1077 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
1081 sh->rx_domain = domain;
1082 domain = mlx5_glue->dr_create_domain(sh->ctx,
1083 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
1085 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
1089 pthread_mutex_init(&sh->dv_mutex, NULL);
1090 sh->tx_domain = domain;
1091 #ifdef HAVE_MLX5DV_DR_ESWITCH
1092 if (priv->config.dv_esw_en) {
1093 domain = mlx5_glue->dr_create_domain
1094 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
1096 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
1100 sh->fdb_domain = domain;
1101 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
1104 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
1105 #endif /* HAVE_MLX5DV_DR */
1107 priv->dr_shared = 1;
1110 /* Rollback the created objects. */
1111 if (sh->rx_domain) {
1112 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1113 sh->rx_domain = NULL;
1115 if (sh->tx_domain) {
1116 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1117 sh->tx_domain = NULL;
1119 if (sh->fdb_domain) {
1120 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1121 sh->fdb_domain = NULL;
1123 if (sh->esw_drop_action) {
1124 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1125 sh->esw_drop_action = NULL;
1127 if (sh->pop_vlan_action) {
1128 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1129 sh->pop_vlan_action = NULL;
1131 if (sh->tag_table) {
1132 /* tags should be destroyed with flow before. */
1133 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1134 sh->tag_table = NULL;
1136 mlx5_free_table_hash_list(priv);
1141 * Destroy DR related data within private structure.
1144 * Pointer to the private device data structure.
1147 mlx5_free_shared_dr(struct mlx5_priv *priv)
1149 struct mlx5_ibv_shared *sh;
1151 if (!priv->dr_shared)
1153 priv->dr_shared = 0;
1156 #ifdef HAVE_MLX5DV_DR
1157 MLX5_ASSERT(sh->dv_refcnt);
1158 if (sh->dv_refcnt && --sh->dv_refcnt)
1160 if (sh->rx_domain) {
1161 mlx5_glue->dr_destroy_domain(sh->rx_domain);
1162 sh->rx_domain = NULL;
1164 if (sh->tx_domain) {
1165 mlx5_glue->dr_destroy_domain(sh->tx_domain);
1166 sh->tx_domain = NULL;
1168 #ifdef HAVE_MLX5DV_DR_ESWITCH
1169 if (sh->fdb_domain) {
1170 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1171 sh->fdb_domain = NULL;
1173 if (sh->esw_drop_action) {
1174 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1175 sh->esw_drop_action = NULL;
1178 if (sh->pop_vlan_action) {
1179 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1180 sh->pop_vlan_action = NULL;
1182 pthread_mutex_destroy(&sh->dv_mutex);
1183 #endif /* HAVE_MLX5DV_DR */
1184 if (sh->tag_table) {
1185 /* tags should be destroyed with flow before. */
1186 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1187 sh->tag_table = NULL;
1189 mlx5_free_table_hash_list(priv);
1193 * Initialize shared data between primary and secondary process.
1195 * A memzone is reserved by primary process and secondary processes attach to
1199 * 0 on success, a negative errno value otherwise and rte_errno is set.
1202 mlx5_init_shared_data(void)
1204 const struct rte_memzone *mz;
1207 rte_spinlock_lock(&mlx5_shared_data_lock);
1208 if (mlx5_shared_data == NULL) {
1209 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1210 /* Allocate shared memory. */
1211 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1212 sizeof(*mlx5_shared_data),
1216 "Cannot allocate mlx5 shared data");
1220 mlx5_shared_data = mz->addr;
1221 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1222 rte_spinlock_init(&mlx5_shared_data->lock);
1224 /* Lookup allocated shared memory. */
1225 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1228 "Cannot attach mlx5 shared data");
1232 mlx5_shared_data = mz->addr;
1233 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1237 rte_spinlock_unlock(&mlx5_shared_data_lock);
1242 * Retrieve integer value from environment variable.
1245 * Environment variable name.
1248 * Integer value, 0 if the variable is not set.
1251 mlx5_getenv_int(const char *name)
1253 const char *val = getenv(name);
1261 * Verbs callback to allocate a memory. This function should allocate the space
1262 * according to the size provided residing inside a huge page.
1263 * Please note that all allocation must respect the alignment from libmlx5
1264 * (i.e. currently sysconf(_SC_PAGESIZE)).
1267 * The size in bytes of the memory to allocate.
1269 * A pointer to the callback data.
1272 * Allocated buffer, NULL otherwise and rte_errno is set.
1275 mlx5_alloc_verbs_buf(size_t size, void *data)
1277 struct mlx5_priv *priv = data;
1279 size_t alignment = sysconf(_SC_PAGESIZE);
1280 unsigned int socket = SOCKET_ID_ANY;
1282 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1283 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1285 socket = ctrl->socket;
1286 } else if (priv->verbs_alloc_ctx.type ==
1287 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1288 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1290 socket = ctrl->socket;
1292 MLX5_ASSERT(data != NULL);
1293 ret = rte_malloc_socket(__func__, size, alignment, socket);
1300 * Verbs callback to free a memory.
1303 * A pointer to the memory to free.
1305 * A pointer to the callback data.
1308 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1310 MLX5_ASSERT(data != NULL);
1315 * DPDK callback to add udp tunnel port
1318 * A pointer to eth_dev
1319 * @param[in] udp_tunnel
1320 * A pointer to udp tunnel
1323 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1326 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1327 struct rte_eth_udp_tunnel *udp_tunnel)
1329 MLX5_ASSERT(udp_tunnel != NULL);
1330 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1331 udp_tunnel->udp_port == 4789)
1333 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1334 udp_tunnel->udp_port == 4790)
1340 * Initialize process private data structure.
1343 * Pointer to Ethernet device structure.
1346 * 0 on success, a negative errno value otherwise and rte_errno is set.
1349 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1351 struct mlx5_priv *priv = dev->data->dev_private;
1352 struct mlx5_proc_priv *ppriv;
1356 * UAR register table follows the process private structure. BlueFlame
1357 * registers for Tx queues are stored in the table.
1360 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1361 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1362 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1367 ppriv->uar_table_sz = ppriv_size;
1368 dev->process_private = ppriv;
1373 * Un-initialize process private data structure.
1376 * Pointer to Ethernet device structure.
1379 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1381 if (!dev->process_private)
1383 rte_free(dev->process_private);
1384 dev->process_private = NULL;
1388 * DPDK callback to close the device.
1390 * Destroy all queues and objects, free memory.
1393 * Pointer to Ethernet device structure.
1396 mlx5_dev_close(struct rte_eth_dev *dev)
1398 struct mlx5_priv *priv = dev->data->dev_private;
1402 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1404 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1405 /* In case mlx5_dev_stop() has not been called. */
1406 mlx5_dev_interrupt_handler_uninstall(dev);
1407 mlx5_dev_interrupt_handler_devx_uninstall(dev);
1409 * If default mreg copy action is removed at the stop stage,
1410 * the search will return none and nothing will be done anymore.
1412 mlx5_flow_stop_default(dev);
1413 mlx5_traffic_disable(dev);
1415 * If all the flows are already flushed in the device stop stage,
1416 * then this will return directly without any action.
1418 mlx5_flow_list_flush(dev, &priv->flows, true);
1419 mlx5_flow_meter_flush(dev, NULL);
1420 /* Free the intermediate buffers for flow creation. */
1421 mlx5_flow_free_intermediate(dev);
1422 /* Prevent crashes when queues are still in use. */
1423 dev->rx_pkt_burst = removed_rx_burst;
1424 dev->tx_pkt_burst = removed_tx_burst;
1426 /* Disable datapath on secondary process. */
1427 mlx5_mp_req_stop_rxtx(dev);
1428 if (priv->rxqs != NULL) {
1429 /* XXX race condition if mlx5_rx_burst() is still running. */
1431 for (i = 0; (i != priv->rxqs_n); ++i)
1432 mlx5_rxq_release(dev, i);
1436 if (priv->txqs != NULL) {
1437 /* XXX race condition if mlx5_tx_burst() is still running. */
1439 for (i = 0; (i != priv->txqs_n); ++i)
1440 mlx5_txq_release(dev, i);
1444 mlx5_proc_priv_uninit(dev);
1445 if (priv->mreg_cp_tbl)
1446 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1447 mlx5_mprq_free_mp(dev);
1448 mlx5_free_shared_dr(priv);
1449 if (priv->rss_conf.rss_key != NULL)
1450 rte_free(priv->rss_conf.rss_key);
1451 if (priv->reta_idx != NULL)
1452 rte_free(priv->reta_idx);
1453 if (priv->config.vf)
1454 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1455 dev->data->mac_addrs,
1456 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1457 if (priv->nl_socket_route >= 0)
1458 close(priv->nl_socket_route);
1459 if (priv->nl_socket_rdma >= 0)
1460 close(priv->nl_socket_rdma);
1461 if (priv->vmwa_context)
1462 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1463 ret = mlx5_hrxq_verify(dev);
1465 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1466 dev->data->port_id);
1467 ret = mlx5_ind_table_obj_verify(dev);
1469 DRV_LOG(WARNING, "port %u some indirection table still remain",
1470 dev->data->port_id);
1471 ret = mlx5_rxq_obj_verify(dev);
1473 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1474 dev->data->port_id);
1475 ret = mlx5_rxq_verify(dev);
1477 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1478 dev->data->port_id);
1479 ret = mlx5_txq_obj_verify(dev);
1481 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1482 dev->data->port_id);
1483 ret = mlx5_txq_verify(dev);
1485 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1486 dev->data->port_id);
1487 ret = mlx5_flow_verify(dev);
1489 DRV_LOG(WARNING, "port %u some flows still remain",
1490 dev->data->port_id);
1493 * Free the shared context in last turn, because the cleanup
1494 * routines above may use some shared fields, like
1495 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1496 * ifindex if Netlink fails.
1498 mlx5_free_shared_ibctx(priv->sh);
1501 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1505 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1506 struct mlx5_priv *opriv =
1507 rte_eth_devices[port_id].data->dev_private;
1510 opriv->domain_id != priv->domain_id ||
1511 &rte_eth_devices[port_id] == dev)
1517 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1519 memset(priv, 0, sizeof(*priv));
1520 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1522 * Reset mac_addrs to NULL such that it is not freed as part of
1523 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1524 * it is freed when dev_private is freed.
1526 dev->data->mac_addrs = NULL;
1529 const struct eth_dev_ops mlx5_dev_ops = {
1530 .dev_configure = mlx5_dev_configure,
1531 .dev_start = mlx5_dev_start,
1532 .dev_stop = mlx5_dev_stop,
1533 .dev_set_link_down = mlx5_set_link_down,
1534 .dev_set_link_up = mlx5_set_link_up,
1535 .dev_close = mlx5_dev_close,
1536 .promiscuous_enable = mlx5_promiscuous_enable,
1537 .promiscuous_disable = mlx5_promiscuous_disable,
1538 .allmulticast_enable = mlx5_allmulticast_enable,
1539 .allmulticast_disable = mlx5_allmulticast_disable,
1540 .link_update = mlx5_link_update,
1541 .stats_get = mlx5_stats_get,
1542 .stats_reset = mlx5_stats_reset,
1543 .xstats_get = mlx5_xstats_get,
1544 .xstats_reset = mlx5_xstats_reset,
1545 .xstats_get_names = mlx5_xstats_get_names,
1546 .fw_version_get = mlx5_fw_version_get,
1547 .dev_infos_get = mlx5_dev_infos_get,
1548 .read_clock = mlx5_read_clock,
1549 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1550 .vlan_filter_set = mlx5_vlan_filter_set,
1551 .rx_queue_setup = mlx5_rx_queue_setup,
1552 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1553 .tx_queue_setup = mlx5_tx_queue_setup,
1554 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1555 .rx_queue_release = mlx5_rx_queue_release,
1556 .tx_queue_release = mlx5_tx_queue_release,
1557 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1558 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1559 .mac_addr_remove = mlx5_mac_addr_remove,
1560 .mac_addr_add = mlx5_mac_addr_add,
1561 .mac_addr_set = mlx5_mac_addr_set,
1562 .set_mc_addr_list = mlx5_set_mc_addr_list,
1563 .mtu_set = mlx5_dev_set_mtu,
1564 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1565 .vlan_offload_set = mlx5_vlan_offload_set,
1566 .reta_update = mlx5_dev_rss_reta_update,
1567 .reta_query = mlx5_dev_rss_reta_query,
1568 .rss_hash_update = mlx5_rss_hash_update,
1569 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1570 .filter_ctrl = mlx5_dev_filter_ctrl,
1571 .rx_descriptor_status = mlx5_rx_descriptor_status,
1572 .tx_descriptor_status = mlx5_tx_descriptor_status,
1573 .rxq_info_get = mlx5_rxq_info_get,
1574 .txq_info_get = mlx5_txq_info_get,
1575 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1576 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1577 .rx_queue_count = mlx5_rx_queue_count,
1578 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1579 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1580 .is_removed = mlx5_is_removed,
1581 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1582 .get_module_info = mlx5_get_module_info,
1583 .get_module_eeprom = mlx5_get_module_eeprom,
1584 .hairpin_cap_get = mlx5_hairpin_cap_get,
1585 .mtr_ops_get = mlx5_flow_meter_ops_get,
1588 /* Available operations from secondary process. */
1589 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1590 .stats_get = mlx5_stats_get,
1591 .stats_reset = mlx5_stats_reset,
1592 .xstats_get = mlx5_xstats_get,
1593 .xstats_reset = mlx5_xstats_reset,
1594 .xstats_get_names = mlx5_xstats_get_names,
1595 .fw_version_get = mlx5_fw_version_get,
1596 .dev_infos_get = mlx5_dev_infos_get,
1597 .rx_descriptor_status = mlx5_rx_descriptor_status,
1598 .tx_descriptor_status = mlx5_tx_descriptor_status,
1599 .rxq_info_get = mlx5_rxq_info_get,
1600 .txq_info_get = mlx5_txq_info_get,
1601 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1602 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1603 .get_module_info = mlx5_get_module_info,
1604 .get_module_eeprom = mlx5_get_module_eeprom,
1607 /* Available operations in flow isolated mode. */
1608 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1609 .dev_configure = mlx5_dev_configure,
1610 .dev_start = mlx5_dev_start,
1611 .dev_stop = mlx5_dev_stop,
1612 .dev_set_link_down = mlx5_set_link_down,
1613 .dev_set_link_up = mlx5_set_link_up,
1614 .dev_close = mlx5_dev_close,
1615 .promiscuous_enable = mlx5_promiscuous_enable,
1616 .promiscuous_disable = mlx5_promiscuous_disable,
1617 .allmulticast_enable = mlx5_allmulticast_enable,
1618 .allmulticast_disable = mlx5_allmulticast_disable,
1619 .link_update = mlx5_link_update,
1620 .stats_get = mlx5_stats_get,
1621 .stats_reset = mlx5_stats_reset,
1622 .xstats_get = mlx5_xstats_get,
1623 .xstats_reset = mlx5_xstats_reset,
1624 .xstats_get_names = mlx5_xstats_get_names,
1625 .fw_version_get = mlx5_fw_version_get,
1626 .dev_infos_get = mlx5_dev_infos_get,
1627 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1628 .vlan_filter_set = mlx5_vlan_filter_set,
1629 .rx_queue_setup = mlx5_rx_queue_setup,
1630 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1631 .tx_queue_setup = mlx5_tx_queue_setup,
1632 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1633 .rx_queue_release = mlx5_rx_queue_release,
1634 .tx_queue_release = mlx5_tx_queue_release,
1635 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1636 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1637 .mac_addr_remove = mlx5_mac_addr_remove,
1638 .mac_addr_add = mlx5_mac_addr_add,
1639 .mac_addr_set = mlx5_mac_addr_set,
1640 .set_mc_addr_list = mlx5_set_mc_addr_list,
1641 .mtu_set = mlx5_dev_set_mtu,
1642 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1643 .vlan_offload_set = mlx5_vlan_offload_set,
1644 .filter_ctrl = mlx5_dev_filter_ctrl,
1645 .rx_descriptor_status = mlx5_rx_descriptor_status,
1646 .tx_descriptor_status = mlx5_tx_descriptor_status,
1647 .rxq_info_get = mlx5_rxq_info_get,
1648 .txq_info_get = mlx5_txq_info_get,
1649 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1650 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1651 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1652 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1653 .is_removed = mlx5_is_removed,
1654 .get_module_info = mlx5_get_module_info,
1655 .get_module_eeprom = mlx5_get_module_eeprom,
1656 .hairpin_cap_get = mlx5_hairpin_cap_get,
1657 .mtr_ops_get = mlx5_flow_meter_ops_get,
1661 * Verify and store value for device argument.
1664 * Key argument to verify.
1666 * Value associated with key.
1671 * 0 on success, a negative errno value otherwise and rte_errno is set.
1674 mlx5_args_check(const char *key, const char *val, void *opaque)
1676 struct mlx5_dev_config *config = opaque;
1679 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1680 if (!strcmp(MLX5_REPRESENTOR, key))
1683 tmp = strtoul(val, NULL, 0);
1686 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1689 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1690 config->cqe_comp = !!tmp;
1691 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1692 config->cqe_pad = !!tmp;
1693 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1694 config->hw_padding = !!tmp;
1695 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1696 config->mprq.enabled = !!tmp;
1697 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1698 config->mprq.stride_num_n = tmp;
1699 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1700 config->mprq.stride_size_n = tmp;
1701 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1702 config->mprq.max_memcpy_len = tmp;
1703 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1704 config->mprq.min_rxqs_num = tmp;
1705 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1706 DRV_LOG(WARNING, "%s: deprecated parameter,"
1707 " converted to txq_inline_max", key);
1708 config->txq_inline_max = tmp;
1709 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1710 config->txq_inline_max = tmp;
1711 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1712 config->txq_inline_min = tmp;
1713 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1714 config->txq_inline_mpw = tmp;
1715 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1716 config->txqs_inline = tmp;
1717 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1718 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1719 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1720 config->mps = !!tmp;
1721 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1722 if (tmp != MLX5_TXDB_CACHED &&
1723 tmp != MLX5_TXDB_NCACHED &&
1724 tmp != MLX5_TXDB_HEURISTIC) {
1725 DRV_LOG(ERR, "invalid Tx doorbell "
1726 "mapping parameter");
1731 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1732 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1733 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1734 DRV_LOG(WARNING, "%s: deprecated parameter,"
1735 " converted to txq_inline_mpw", key);
1736 config->txq_inline_mpw = tmp;
1737 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1738 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1739 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1740 config->rx_vec_en = !!tmp;
1741 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1742 config->l3_vxlan_en = !!tmp;
1743 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1744 config->vf_nl_en = !!tmp;
1745 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1746 config->dv_esw_en = !!tmp;
1747 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1748 config->dv_flow_en = !!tmp;
1749 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1750 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1751 tmp != MLX5_XMETA_MODE_META16 &&
1752 tmp != MLX5_XMETA_MODE_META32) {
1753 DRV_LOG(ERR, "invalid extensive "
1754 "metadata parameter");
1758 config->dv_xmeta_en = tmp;
1759 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1760 config->mr_ext_memseg_en = !!tmp;
1761 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1762 config->max_dump_files_num = tmp;
1763 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1764 config->lro.timeout = tmp;
1765 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1766 DRV_LOG(DEBUG, "class argument is %s.", val);
1767 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1768 config->log_hp_size = tmp;
1770 DRV_LOG(WARNING, "%s: unknown parameter", key);
1778 * Parse device parameters.
1781 * Pointer to device configuration structure.
1783 * Device arguments structure.
1786 * 0 on success, a negative errno value otherwise and rte_errno is set.
1789 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1791 const char **params = (const char *[]){
1792 MLX5_RXQ_CQE_COMP_EN,
1793 MLX5_RXQ_CQE_PAD_EN,
1794 MLX5_RXQ_PKT_PAD_EN,
1796 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1797 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1798 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1801 MLX5_TXQ_INLINE_MIN,
1802 MLX5_TXQ_INLINE_MAX,
1803 MLX5_TXQ_INLINE_MPW,
1804 MLX5_TXQS_MIN_INLINE,
1807 MLX5_TXQ_MPW_HDR_DSEG_EN,
1808 MLX5_TXQ_MAX_INLINE_LEN,
1817 MLX5_MR_EXT_MEMSEG_EN,
1819 MLX5_MAX_DUMP_FILES_NUM,
1820 MLX5_LRO_TIMEOUT_USEC,
1821 MLX5_CLASS_ARG_NAME,
1825 struct rte_kvargs *kvlist;
1829 if (devargs == NULL)
1831 /* Following UGLY cast is done to pass checkpatch. */
1832 kvlist = rte_kvargs_parse(devargs->args, params);
1833 if (kvlist == NULL) {
1837 /* Process parameters. */
1838 for (i = 0; (params[i] != NULL); ++i) {
1839 if (rte_kvargs_count(kvlist, params[i])) {
1840 ret = rte_kvargs_process(kvlist, params[i],
1841 mlx5_args_check, config);
1844 rte_kvargs_free(kvlist);
1849 rte_kvargs_free(kvlist);
1853 static struct rte_pci_driver mlx5_driver;
1856 * PMD global initialization.
1858 * Independent from individual device, this function initializes global
1859 * per-PMD data structures distinguishing primary and secondary processes.
1860 * Hence, each initialization is called once per a process.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 mlx5_init_once(void)
1868 struct mlx5_shared_data *sd;
1869 struct mlx5_local_data *ld = &mlx5_local_data;
1872 if (mlx5_init_shared_data())
1874 sd = mlx5_shared_data;
1876 rte_spinlock_lock(&sd->lock);
1877 switch (rte_eal_process_type()) {
1878 case RTE_PROC_PRIMARY:
1881 LIST_INIT(&sd->mem_event_cb_list);
1882 rte_rwlock_init(&sd->mem_event_rwlock);
1883 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1884 mlx5_mr_mem_event_cb, NULL);
1885 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1886 mlx5_mp_primary_handle);
1889 sd->init_done = true;
1891 case RTE_PROC_SECONDARY:
1894 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1895 mlx5_mp_secondary_handle);
1898 ++sd->secondary_cnt;
1899 ld->init_done = true;
1905 rte_spinlock_unlock(&sd->lock);
1910 * Configures the minimal amount of data to inline into WQE
1911 * while sending packets.
1913 * - the txq_inline_min has the maximal priority, if this
1914 * key is specified in devargs
1915 * - if DevX is enabled the inline mode is queried from the
1916 * device (HCA attributes and NIC vport context if needed).
1917 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1918 * and none (0 bytes) for other NICs
1921 * Verbs device parameters (name, port, switch_info) to spawn.
1923 * Device configuration parameters.
1926 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1927 struct mlx5_dev_config *config)
1929 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1930 /* Application defines size of inlined data explicitly. */
1931 switch (spawn->pci_dev->id.device_id) {
1932 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1933 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1934 if (config->txq_inline_min <
1935 (int)MLX5_INLINE_HSIZE_L2) {
1937 "txq_inline_mix aligned to minimal"
1938 " ConnectX-4 required value %d",
1939 (int)MLX5_INLINE_HSIZE_L2);
1940 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1946 if (config->hca_attr.eth_net_offloads) {
1947 /* We have DevX enabled, inline mode queried successfully. */
1948 switch (config->hca_attr.wqe_inline_mode) {
1949 case MLX5_CAP_INLINE_MODE_L2:
1950 /* outer L2 header must be inlined. */
1951 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1953 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1954 /* No inline data are required by NIC. */
1955 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1956 config->hw_vlan_insert =
1957 config->hca_attr.wqe_vlan_insert;
1958 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1960 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1961 /* inline mode is defined by NIC vport context. */
1962 if (!config->hca_attr.eth_virt)
1964 switch (config->hca_attr.vport_inline_mode) {
1965 case MLX5_INLINE_MODE_NONE:
1966 config->txq_inline_min =
1967 MLX5_INLINE_HSIZE_NONE;
1969 case MLX5_INLINE_MODE_L2:
1970 config->txq_inline_min =
1971 MLX5_INLINE_HSIZE_L2;
1973 case MLX5_INLINE_MODE_IP:
1974 config->txq_inline_min =
1975 MLX5_INLINE_HSIZE_L3;
1977 case MLX5_INLINE_MODE_TCP_UDP:
1978 config->txq_inline_min =
1979 MLX5_INLINE_HSIZE_L4;
1981 case MLX5_INLINE_MODE_INNER_L2:
1982 config->txq_inline_min =
1983 MLX5_INLINE_HSIZE_INNER_L2;
1985 case MLX5_INLINE_MODE_INNER_IP:
1986 config->txq_inline_min =
1987 MLX5_INLINE_HSIZE_INNER_L3;
1989 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1990 config->txq_inline_min =
1991 MLX5_INLINE_HSIZE_INNER_L4;
1997 * We get here if we are unable to deduce
1998 * inline data size with DevX. Try PCI ID
1999 * to determine old NICs.
2001 switch (spawn->pci_dev->id.device_id) {
2002 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2003 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2004 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2005 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2006 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2007 config->hw_vlan_insert = 0;
2009 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2010 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2011 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2012 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2014 * These NICs support VLAN insertion from WQE and
2015 * report the wqe_vlan_insert flag. But there is the bug
2016 * and PFC control may be broken, so disable feature.
2018 config->hw_vlan_insert = 0;
2019 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2022 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2026 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2030 * Configures the metadata mask fields in the shared context.
2033 * Pointer to Ethernet device.
2036 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2038 struct mlx5_priv *priv = dev->data->dev_private;
2039 struct mlx5_ibv_shared *sh = priv->sh;
2040 uint32_t meta, mark, reg_c0;
2042 reg_c0 = ~priv->vport_meta_mask;
2043 switch (priv->config.dv_xmeta_en) {
2044 case MLX5_XMETA_MODE_LEGACY:
2046 mark = MLX5_FLOW_MARK_MASK;
2048 case MLX5_XMETA_MODE_META16:
2049 meta = reg_c0 >> rte_bsf32(reg_c0);
2050 mark = MLX5_FLOW_MARK_MASK;
2052 case MLX5_XMETA_MODE_META32:
2054 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2062 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2063 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2064 sh->dv_mark_mask, mark);
2066 sh->dv_mark_mask = mark;
2067 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2068 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2069 sh->dv_meta_mask, meta);
2071 sh->dv_meta_mask = meta;
2072 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2073 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2074 sh->dv_meta_mask, reg_c0);
2076 sh->dv_regc0_mask = reg_c0;
2077 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2078 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2079 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2080 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2084 * Allocate page of door-bells and register it using DevX API.
2087 * Pointer to Ethernet device.
2090 * Pointer to new page on success, NULL otherwise.
2092 static struct mlx5_devx_dbr_page *
2093 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
2095 struct mlx5_priv *priv = dev->data->dev_private;
2096 struct mlx5_devx_dbr_page *page;
2098 /* Allocate space for door-bell page and management data. */
2099 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
2100 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
2102 DRV_LOG(ERR, "port %u cannot allocate dbr page",
2103 dev->data->port_id);
2106 /* Register allocated memory. */
2107 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
2108 MLX5_DBR_PAGE_SIZE, 0);
2110 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
2111 dev->data->port_id);
2119 * Find the next available door-bell, allocate new page if needed.
2122 * Pointer to Ethernet device.
2123 * @param [out] dbr_page
2124 * Door-bell page containing the page data.
2127 * Door-bell address offset on success, a negative error value otherwise.
2130 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
2132 struct mlx5_priv *priv = dev->data->dev_private;
2133 struct mlx5_devx_dbr_page *page = NULL;
2136 LIST_FOREACH(page, &priv->dbrpgs, next)
2137 if (page->dbr_count < MLX5_DBR_PER_PAGE)
2139 if (!page) { /* No page with free door-bell exists. */
2140 page = mlx5_alloc_dbr_page(dev);
2141 if (!page) /* Failed to allocate new page. */
2143 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
2145 /* Loop to find bitmap part with clear bit. */
2147 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
2150 /* Find the first clear bit. */
2151 j = rte_bsf64(~page->dbr_bitmap[i]);
2152 MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
2153 page->dbr_bitmap[i] |= (1 << j);
2156 return (((i * 64) + j) * sizeof(uint64_t));
2160 * Release a door-bell record.
2163 * Pointer to Ethernet device.
2164 * @param [in] umem_id
2165 * UMEM ID of page containing the door-bell record to release.
2166 * @param [in] offset
2167 * Offset of door-bell record in page.
2170 * 0 on success, a negative error value otherwise.
2173 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
2175 struct mlx5_priv *priv = dev->data->dev_private;
2176 struct mlx5_devx_dbr_page *page = NULL;
2179 LIST_FOREACH(page, &priv->dbrpgs, next)
2180 /* Find the page this address belongs to. */
2181 if (page->umem->umem_id == umem_id)
2186 if (!page->dbr_count) {
2187 /* Page not used, free it and remove from list. */
2188 LIST_REMOVE(page, next);
2190 ret = -mlx5_glue->devx_umem_dereg(page->umem);
2193 /* Mark in bitmap that this door-bell is not in use. */
2194 offset /= MLX5_DBR_SIZE;
2195 int i = offset / 64;
2196 int j = offset % 64;
2198 page->dbr_bitmap[i] &= ~(1 << j);
2204 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2206 static const char *const dynf_names[] = {
2207 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2208 RTE_MBUF_DYNFLAG_METADATA_NAME
2212 if (n < RTE_DIM(dynf_names))
2214 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2215 if (names[i] == NULL)
2217 strcpy(names[i], dynf_names[i]);
2219 return RTE_DIM(dynf_names);
2223 * Check sibling device configurations.
2225 * Sibling devices sharing the Infiniband device context
2226 * should have compatible configurations. This regards
2227 * representors and bonding slaves.
2230 * Private device descriptor.
2232 * Configuration of the device is going to be created.
2235 * 0 on success, EINVAL otherwise
2238 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2239 struct mlx5_dev_config *config)
2241 struct mlx5_ibv_shared *sh = priv->sh;
2242 struct mlx5_dev_config *sh_conf = NULL;
2246 /* Nothing to compare for the single/first device. */
2247 if (sh->refcnt == 1)
2249 /* Find the device with shared context. */
2250 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2251 struct mlx5_priv *opriv =
2252 rte_eth_devices[port_id].data->dev_private;
2254 if (opriv && opriv != priv && opriv->sh == sh) {
2255 sh_conf = &opriv->config;
2261 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2262 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2263 " for shared %s context", sh->ibdev_name);
2267 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2268 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2269 " for shared %s context", sh->ibdev_name);
2276 * Spawn an Ethernet device from Verbs information.
2279 * Backing DPDK device.
2281 * Verbs device parameters (name, port, switch_info) to spawn.
2283 * Device configuration parameters.
2286 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2287 * is set. The following errors are defined:
2289 * EBUSY: device is not supposed to be spawned.
2290 * EEXIST: device is already spawned
2292 static struct rte_eth_dev *
2293 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2294 struct mlx5_dev_spawn_data *spawn,
2295 struct mlx5_dev_config config)
2297 const struct mlx5_switch_info *switch_info = &spawn->info;
2298 struct mlx5_ibv_shared *sh = NULL;
2299 struct ibv_port_attr port_attr;
2300 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2301 struct rte_eth_dev *eth_dev = NULL;
2302 struct mlx5_priv *priv = NULL;
2304 unsigned int hw_padding = 0;
2306 unsigned int cqe_comp;
2307 unsigned int cqe_pad = 0;
2308 unsigned int tunnel_en = 0;
2309 unsigned int mpls_en = 0;
2310 unsigned int swp = 0;
2311 unsigned int mprq = 0;
2312 unsigned int mprq_min_stride_size_n = 0;
2313 unsigned int mprq_max_stride_size_n = 0;
2314 unsigned int mprq_min_stride_num_n = 0;
2315 unsigned int mprq_max_stride_num_n = 0;
2316 struct rte_ether_addr mac;
2317 char name[RTE_ETH_NAME_MAX_LEN];
2318 int own_domain_id = 0;
2321 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2322 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2325 /* Determine if this port representor is supposed to be spawned. */
2326 if (switch_info->representor && dpdk_dev->devargs) {
2327 struct rte_eth_devargs eth_da;
2329 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2332 DRV_LOG(ERR, "failed to process device arguments: %s",
2333 strerror(rte_errno));
2336 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2337 if (eth_da.representor_ports[i] ==
2338 (uint16_t)switch_info->port_name)
2340 if (i == eth_da.nb_representor_ports) {
2345 /* Build device name. */
2346 if (spawn->pf_bond < 0) {
2347 /* Single device. */
2348 if (!switch_info->representor)
2349 strlcpy(name, dpdk_dev->name, sizeof(name));
2351 snprintf(name, sizeof(name), "%s_representor_%u",
2352 dpdk_dev->name, switch_info->port_name);
2354 /* Bonding device. */
2355 if (!switch_info->representor)
2356 snprintf(name, sizeof(name), "%s_%s",
2357 dpdk_dev->name, spawn->ibv_dev->name);
2359 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2360 dpdk_dev->name, spawn->ibv_dev->name,
2361 switch_info->port_name);
2363 /* check if the device is already spawned */
2364 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2368 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2369 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2370 struct mlx5_mp_id mp_id;
2372 eth_dev = rte_eth_dev_attach_secondary(name);
2373 if (eth_dev == NULL) {
2374 DRV_LOG(ERR, "can not attach rte ethdev");
2378 eth_dev->device = dpdk_dev;
2379 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2380 err = mlx5_proc_priv_init(eth_dev);
2383 mp_id.port_id = eth_dev->data->port_id;
2384 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2385 /* Receive command fd from primary process */
2386 err = mlx5_mp_req_verbs_cmd_fd(&mp_id);
2389 /* Remap UAR for Tx queues. */
2390 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2394 * Ethdev pointer is still required as input since
2395 * the primary device is not accessible from the
2396 * secondary process.
2398 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2399 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2403 * Some parameters ("tx_db_nc" in particularly) are needed in
2404 * advance to create dv/verbs device context. We proceed the
2405 * devargs here to get ones, and later proceed devargs again
2406 * to override some hardware settings.
2408 err = mlx5_args(&config, dpdk_dev->devargs);
2411 DRV_LOG(ERR, "failed to process device arguments: %s",
2412 strerror(rte_errno));
2415 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2418 config.devx = sh->devx;
2419 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2420 config.dest_tir = 1;
2422 #ifdef HAVE_IBV_MLX5_MOD_SWP
2423 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2426 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2427 * as all ConnectX-5 devices.
2429 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2430 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2432 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2433 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2435 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2436 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2437 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2438 DRV_LOG(DEBUG, "enhanced MPW is supported");
2439 mps = MLX5_MPW_ENHANCED;
2441 DRV_LOG(DEBUG, "MPW is supported");
2445 DRV_LOG(DEBUG, "MPW isn't supported");
2446 mps = MLX5_MPW_DISABLED;
2448 #ifdef HAVE_IBV_MLX5_MOD_SWP
2449 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2450 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2451 DRV_LOG(DEBUG, "SWP support: %u", swp);
2454 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2455 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2456 struct mlx5dv_striding_rq_caps mprq_caps =
2457 dv_attr.striding_rq_caps;
2459 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2460 mprq_caps.min_single_stride_log_num_of_bytes);
2461 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2462 mprq_caps.max_single_stride_log_num_of_bytes);
2463 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2464 mprq_caps.min_single_wqe_log_num_of_strides);
2465 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2466 mprq_caps.max_single_wqe_log_num_of_strides);
2467 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2468 mprq_caps.supported_qpts);
2469 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2471 mprq_min_stride_size_n =
2472 mprq_caps.min_single_stride_log_num_of_bytes;
2473 mprq_max_stride_size_n =
2474 mprq_caps.max_single_stride_log_num_of_bytes;
2475 mprq_min_stride_num_n =
2476 mprq_caps.min_single_wqe_log_num_of_strides;
2477 mprq_max_stride_num_n =
2478 mprq_caps.max_single_wqe_log_num_of_strides;
2481 if (RTE_CACHE_LINE_SIZE == 128 &&
2482 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2486 config.cqe_comp = cqe_comp;
2487 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2488 /* Whether device supports 128B Rx CQE padding. */
2489 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2490 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2492 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2493 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2494 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2495 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2496 (dv_attr.tunnel_offloads_caps &
2497 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2498 (dv_attr.tunnel_offloads_caps &
2499 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2501 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2502 tunnel_en ? "" : "not ");
2505 "tunnel offloading disabled due to old OFED/rdma-core version");
2507 config.tunnel_en = tunnel_en;
2508 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2509 mpls_en = ((dv_attr.tunnel_offloads_caps &
2510 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2511 (dv_attr.tunnel_offloads_caps &
2512 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2513 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2514 mpls_en ? "" : "not ");
2516 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2517 " old OFED/rdma-core version or firmware configuration");
2519 config.mpls_en = mpls_en;
2520 /* Check port status. */
2521 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2523 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2526 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2527 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2531 if (port_attr.state != IBV_PORT_ACTIVE)
2532 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2533 mlx5_glue->port_state_str(port_attr.state),
2535 /* Allocate private eth device data. */
2536 priv = rte_zmalloc("ethdev private structure",
2538 RTE_CACHE_LINE_SIZE);
2540 DRV_LOG(ERR, "priv allocation failure");
2545 priv->ibv_port = spawn->ibv_port;
2546 priv->pci_dev = spawn->pci_dev;
2547 priv->mtu = RTE_ETHER_MTU;
2548 priv->mp_id.port_id = port_id;
2549 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN);
2551 /* Initialize UAR access locks for 32bit implementations. */
2552 rte_spinlock_init(&priv->uar_lock_cq);
2553 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2554 rte_spinlock_init(&priv->uar_lock[i]);
2556 /* Some internal functions rely on Netlink sockets, open them now. */
2557 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2558 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2559 priv->representor = !!switch_info->representor;
2560 priv->master = !!switch_info->master;
2561 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2562 priv->vport_meta_tag = 0;
2563 priv->vport_meta_mask = 0;
2564 priv->pf_bond = spawn->pf_bond;
2565 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2567 * The DevX port query API is implemented. E-Switch may use
2568 * either vport or reg_c[0] metadata register to match on
2569 * vport index. The engaged part of metadata register is
2572 if (switch_info->representor || switch_info->master) {
2573 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2574 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2575 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2579 "can't query devx port %d on device %s",
2580 spawn->ibv_port, spawn->ibv_dev->name);
2581 devx_port.comp_mask = 0;
2584 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2585 priv->vport_meta_tag = devx_port.reg_c_0.value;
2586 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2587 if (!priv->vport_meta_mask) {
2588 DRV_LOG(ERR, "vport zero mask for port %d"
2589 " on bonding device %s",
2590 spawn->ibv_port, spawn->ibv_dev->name);
2594 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2595 DRV_LOG(ERR, "invalid vport tag for port %d"
2596 " on bonding device %s",
2597 spawn->ibv_port, spawn->ibv_dev->name);
2602 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2603 priv->vport_id = devx_port.vport_num;
2604 } else if (spawn->pf_bond >= 0) {
2605 DRV_LOG(ERR, "can't deduce vport index for port %d"
2606 " on bonding device %s",
2607 spawn->ibv_port, spawn->ibv_dev->name);
2611 /* Suppose vport index in compatible way. */
2612 priv->vport_id = switch_info->representor ?
2613 switch_info->port_name + 1 : -1;
2617 * Kernel/rdma_core support single E-Switch per PF configurations
2618 * only and vport_id field contains the vport index for
2619 * associated VF, which is deduced from representor port name.
2620 * For example, let's have the IB device port 10, it has
2621 * attached network device eth0, which has port name attribute
2622 * pf0vf2, we can deduce the VF number as 2, and set vport index
2623 * as 3 (2+1). This assigning schema should be changed if the
2624 * multiple E-Switch instances per PF configurations or/and PCI
2625 * subfunctions are added.
2627 priv->vport_id = switch_info->representor ?
2628 switch_info->port_name + 1 : -1;
2630 /* representor_id field keeps the unmodified VF index. */
2631 priv->representor_id = switch_info->representor ?
2632 switch_info->port_name : -1;
2634 * Look for sibling devices in order to reuse their switch domain
2635 * if any, otherwise allocate one.
2637 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2638 const struct mlx5_priv *opriv =
2639 rte_eth_devices[port_id].data->dev_private;
2642 opriv->sh != priv->sh ||
2644 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2646 priv->domain_id = opriv->domain_id;
2649 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2650 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2653 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2654 strerror(rte_errno));
2659 /* Override some values set by hardware configuration. */
2660 mlx5_args(&config, dpdk_dev->devargs);
2661 err = mlx5_dev_check_sibling_config(priv, &config);
2664 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2665 IBV_DEVICE_RAW_IP_CSUM);
2666 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2667 (config.hw_csum ? "" : "not "));
2668 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2669 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2670 DRV_LOG(DEBUG, "counters are not supported");
2672 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2673 if (config.dv_flow_en) {
2674 DRV_LOG(WARNING, "DV flow is not supported");
2675 config.dv_flow_en = 0;
2678 config.ind_table_max_size =
2679 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2681 * Remove this check once DPDK supports larger/variable
2682 * indirection tables.
2684 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2685 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2686 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2687 config.ind_table_max_size);
2688 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2689 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2690 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2691 (config.hw_vlan_strip ? "" : "not "));
2692 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2693 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2694 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2695 (config.hw_fcs_strip ? "" : "not "));
2696 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2697 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2698 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2699 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2700 IBV_DEVICE_PCI_WRITE_END_PADDING);
2702 if (config.hw_padding && !hw_padding) {
2703 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2704 config.hw_padding = 0;
2705 } else if (config.hw_padding) {
2706 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2708 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2709 (sh->device_attr.tso_caps.supported_qpts &
2710 (1 << IBV_QPT_RAW_PACKET)));
2712 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2714 * MPW is disabled by default, while the Enhanced MPW is enabled
2717 if (config.mps == MLX5_ARG_UNSET)
2718 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2721 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2722 DRV_LOG(INFO, "%sMPS is %s",
2723 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2724 config.mps == MLX5_MPW ? "legacy " : "",
2725 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2726 if (config.cqe_comp && !cqe_comp) {
2727 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2728 config.cqe_comp = 0;
2730 if (config.cqe_pad && !cqe_pad) {
2731 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2733 } else if (config.cqe_pad) {
2734 DRV_LOG(INFO, "Rx CQE padding is enabled");
2737 priv->counter_fallback = 0;
2738 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2743 if (!config.hca_attr.flow_counters_dump)
2744 priv->counter_fallback = 1;
2745 #ifndef HAVE_IBV_DEVX_ASYNC
2746 priv->counter_fallback = 1;
2748 if (priv->counter_fallback)
2749 DRV_LOG(INFO, "Use fall-back DV counter management");
2750 /* Check for LRO support. */
2751 if (config.dest_tir && config.hca_attr.lro_cap &&
2752 config.dv_flow_en) {
2753 /* TBD check tunnel lro caps. */
2754 config.lro.supported = config.hca_attr.lro_cap;
2755 DRV_LOG(DEBUG, "Device supports LRO");
2757 * If LRO timeout is not configured by application,
2758 * use the minimal supported value.
2760 if (!config.lro.timeout)
2761 config.lro.timeout =
2762 config.hca_attr.lro_timer_supported_periods[0];
2763 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2764 config.lro.timeout);
2766 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2767 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2768 config.dv_flow_en) {
2769 uint8_t reg_c_mask =
2770 config.hca_attr.qos.flow_meter_reg_c_ids;
2772 * Meter needs two REG_C's for color match and pre-sfx
2773 * flow match. Here get the REG_C for color match.
2774 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2777 if (__builtin_popcount(reg_c_mask) < 1) {
2779 DRV_LOG(WARNING, "No available register for"
2782 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2785 priv->mtr_reg_share =
2786 config.hca_attr.qos.flow_meter_reg_share;
2787 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2788 priv->mtr_color_reg);
2793 if (config.mprq.enabled && mprq) {
2794 if (config.mprq.stride_num_n &&
2795 (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2796 config.mprq.stride_num_n < mprq_min_stride_num_n)) {
2797 config.mprq.stride_num_n =
2798 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2799 mprq_min_stride_num_n),
2800 mprq_max_stride_num_n);
2802 "the number of strides"
2803 " for Multi-Packet RQ is out of range,"
2804 " setting default value (%u)",
2805 1 << config.mprq.stride_num_n);
2807 if (config.mprq.stride_size_n &&
2808 (config.mprq.stride_size_n > mprq_max_stride_size_n ||
2809 config.mprq.stride_size_n < mprq_min_stride_size_n)) {
2810 config.mprq.stride_size_n =
2811 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N,
2812 mprq_min_stride_size_n),
2813 mprq_max_stride_size_n);
2815 "the size of a stride"
2816 " for Multi-Packet RQ is out of range,"
2817 " setting default value (%u)",
2818 1 << config.mprq.stride_size_n);
2820 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2821 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2822 } else if (config.mprq.enabled && !mprq) {
2823 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2824 config.mprq.enabled = 0;
2826 if (config.max_dump_files_num == 0)
2827 config.max_dump_files_num = 128;
2828 eth_dev = rte_eth_dev_allocate(name);
2829 if (eth_dev == NULL) {
2830 DRV_LOG(ERR, "can not allocate rte ethdev");
2834 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2835 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2836 if (priv->representor) {
2837 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2838 eth_dev->data->representor_id = priv->representor_id;
2841 * Store associated network device interface index. This index
2842 * is permanent throughout the lifetime of device. So, we may store
2843 * the ifindex here and use the cached value further.
2845 MLX5_ASSERT(spawn->ifindex);
2846 priv->if_index = spawn->ifindex;
2847 eth_dev->data->dev_private = priv;
2848 priv->dev_data = eth_dev->data;
2849 eth_dev->data->mac_addrs = priv->mac;
2850 eth_dev->device = dpdk_dev;
2851 /* Configure the first MAC address by default. */
2852 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2854 "port %u cannot get MAC address, is mlx5_en"
2855 " loaded? (errno: %s)",
2856 eth_dev->data->port_id, strerror(rte_errno));
2861 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2862 eth_dev->data->port_id,
2863 mac.addr_bytes[0], mac.addr_bytes[1],
2864 mac.addr_bytes[2], mac.addr_bytes[3],
2865 mac.addr_bytes[4], mac.addr_bytes[5]);
2866 #ifdef RTE_LIBRTE_MLX5_DEBUG
2868 char ifname[IF_NAMESIZE];
2870 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2871 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2872 eth_dev->data->port_id, ifname);
2874 DRV_LOG(DEBUG, "port %u ifname is unknown",
2875 eth_dev->data->port_id);
2878 /* Get actual MTU if possible. */
2879 err = mlx5_get_mtu(eth_dev, &priv->mtu);
2884 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2886 /* Initialize burst functions to prevent crashes before link-up. */
2887 eth_dev->rx_pkt_burst = removed_rx_burst;
2888 eth_dev->tx_pkt_burst = removed_tx_burst;
2889 eth_dev->dev_ops = &mlx5_dev_ops;
2890 /* Register MAC address. */
2891 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2892 if (config.vf && config.vf_nl_en)
2893 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2894 mlx5_ifindex(eth_dev),
2895 eth_dev->data->mac_addrs,
2896 MLX5_MAX_MAC_ADDRESSES);
2898 priv->ctrl_flows = 0;
2899 TAILQ_INIT(&priv->flow_meters);
2900 TAILQ_INIT(&priv->flow_meter_profiles);
2901 /* Hint libmlx5 to use PMD allocator for data plane resources */
2902 struct mlx5dv_ctx_allocators alctr = {
2903 .alloc = &mlx5_alloc_verbs_buf,
2904 .free = &mlx5_free_verbs_buf,
2907 mlx5_glue->dv_set_context_attr(sh->ctx,
2908 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2909 (void *)((uintptr_t)&alctr));
2910 /* Bring Ethernet device up. */
2911 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2912 eth_dev->data->port_id);
2913 mlx5_set_link_up(eth_dev);
2915 * Even though the interrupt handler is not installed yet,
2916 * interrupts will still trigger on the async_fd from
2917 * Verbs context returned by ibv_open_device().
2919 mlx5_link_update(eth_dev, 0);
2920 #ifdef HAVE_MLX5DV_DR_ESWITCH
2921 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2922 (switch_info->representor || switch_info->master)))
2923 config.dv_esw_en = 0;
2925 config.dv_esw_en = 0;
2927 /* Detect minimal data bytes to inline. */
2928 mlx5_set_min_inline(spawn, &config);
2929 /* Store device configuration on private structure. */
2930 priv->config = config;
2931 /* Create context for virtual machine VLAN workaround. */
2932 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2933 if (config.dv_flow_en) {
2934 err = mlx5_alloc_shared_dr(priv);
2938 * RSS id is shared with meter flow id. Meter flow id can only
2939 * use the 24 MSB of the register.
2941 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2942 MLX5_MTR_COLOR_BITS);
2943 if (!priv->qrss_id_pool) {
2944 DRV_LOG(ERR, "can't create flow id pool");
2949 /* Supported Verbs flow priority number detection. */
2950 err = mlx5_flow_discover_priorities(eth_dev);
2955 priv->config.flow_prio = err;
2956 if (!priv->config.dv_esw_en &&
2957 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2958 DRV_LOG(WARNING, "metadata mode %u is not supported "
2959 "(no E-Switch)", priv->config.dv_xmeta_en);
2960 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2962 mlx5_set_metadata_mask(eth_dev);
2963 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2964 !priv->sh->dv_regc0_mask) {
2965 DRV_LOG(ERR, "metadata mode %u is not supported "
2966 "(no metadata reg_c[0] is available)",
2967 priv->config.dv_xmeta_en);
2972 * Allocate the buffer for flow creating, just once.
2973 * The allocation must be done before any flow creating.
2975 mlx5_flow_alloc_intermediate(eth_dev);
2976 /* Query availibility of metadata reg_c's. */
2977 err = mlx5_flow_discover_mreg_c(eth_dev);
2982 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2984 "port %u extensive metadata register is not supported",
2985 eth_dev->data->port_id);
2986 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2987 DRV_LOG(ERR, "metadata mode %u is not supported "
2988 "(no metadata registers available)",
2989 priv->config.dv_xmeta_en);
2994 if (priv->config.dv_flow_en &&
2995 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2996 mlx5_flow_ext_mreg_supported(eth_dev) &&
2997 priv->sh->dv_regc0_mask) {
2998 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2999 MLX5_FLOW_MREG_HTABLE_SZ);
3000 if (!priv->mreg_cp_tbl) {
3008 if (priv->mreg_cp_tbl)
3009 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
3011 mlx5_free_shared_dr(priv);
3012 if (priv->nl_socket_route >= 0)
3013 close(priv->nl_socket_route);
3014 if (priv->nl_socket_rdma >= 0)
3015 close(priv->nl_socket_rdma);
3016 if (priv->vmwa_context)
3017 mlx5_vlan_vmwa_exit(priv->vmwa_context);
3018 if (priv->qrss_id_pool)
3019 mlx5_flow_id_pool_release(priv->qrss_id_pool);
3021 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
3023 if (eth_dev != NULL)
3024 eth_dev->data->dev_private = NULL;
3026 if (eth_dev != NULL) {
3027 /* mac_addrs must not be freed alone because part of dev_private */
3028 eth_dev->data->mac_addrs = NULL;
3029 rte_eth_dev_release_port(eth_dev);
3032 mlx5_free_shared_ibctx(sh);
3033 MLX5_ASSERT(err > 0);
3039 * Comparison callback to sort device data.
3041 * This is meant to be used with qsort().
3044 * Pointer to pointer to first data object.
3046 * Pointer to pointer to second data object.
3049 * 0 if both objects are equal, less than 0 if the first argument is less
3050 * than the second, greater than 0 otherwise.
3053 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
3055 const struct mlx5_switch_info *si_a =
3056 &((const struct mlx5_dev_spawn_data *)a)->info;
3057 const struct mlx5_switch_info *si_b =
3058 &((const struct mlx5_dev_spawn_data *)b)->info;
3061 /* Master device first. */
3062 ret = si_b->master - si_a->master;
3065 /* Then representor devices. */
3066 ret = si_b->representor - si_a->representor;
3069 /* Unidentified devices come last in no specific order. */
3070 if (!si_a->representor)
3072 /* Order representors by name. */
3073 return si_a->port_name - si_b->port_name;
3077 * Match PCI information for possible slaves of bonding device.
3079 * @param[in] ibv_dev
3080 * Pointer to Infiniband device structure.
3081 * @param[in] pci_dev
3082 * Pointer to PCI device structure to match PCI address.
3083 * @param[in] nl_rdma
3084 * Netlink RDMA group socket handle.
3087 * negative value if no bonding device found, otherwise
3088 * positive index of slave PF in bonding.
3091 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
3092 const struct rte_pci_device *pci_dev,
3095 char ifname[IF_NAMESIZE + 1];
3096 unsigned int ifindex;
3102 * Try to get master device name. If something goes
3103 * wrong suppose the lack of kernel support and no
3108 if (!strstr(ibv_dev->name, "bond"))
3110 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
3114 * The Master device might not be on the predefined
3115 * port (not on port index 1, it is not garanted),
3116 * we have to scan all Infiniband device port and
3119 for (i = 1; i <= np; ++i) {
3120 /* Check whether Infiniband port is populated. */
3121 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
3124 if (!if_indextoname(ifindex, ifname))
3126 /* Try to read bonding slave names from sysfs. */
3128 "/sys/class/net/%s/master/bonding/slaves", ifname);
3129 file = fopen(slaves, "r");
3135 /* Use safe format to check maximal buffer length. */
3136 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
3137 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
3138 char tmp_str[IF_NAMESIZE + 32];
3139 struct rte_pci_addr pci_addr;
3140 struct mlx5_switch_info info;
3142 /* Process slave interface names in the loop. */
3143 snprintf(tmp_str, sizeof(tmp_str),
3144 "/sys/class/net/%s", ifname);
3145 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
3146 DRV_LOG(WARNING, "can not get PCI address"
3147 " for netdev \"%s\"", ifname);
3150 if (pci_dev->addr.domain != pci_addr.domain ||
3151 pci_dev->addr.bus != pci_addr.bus ||
3152 pci_dev->addr.devid != pci_addr.devid ||
3153 pci_dev->addr.function != pci_addr.function)
3155 /* Slave interface PCI address match found. */
3157 snprintf(tmp_str, sizeof(tmp_str),
3158 "/sys/class/net/%s/phys_port_name", ifname);
3159 file = fopen(tmp_str, "rb");
3162 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
3163 if (fscanf(file, "%32s", tmp_str) == 1)
3164 mlx5_translate_port_name(tmp_str, &info);
3165 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
3166 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
3167 pf = info.port_name;
3176 * DPDK callback to register a PCI device.
3178 * This function spawns Ethernet devices out of a given PCI device.
3180 * @param[in] pci_drv
3181 * PCI driver structure (mlx5_driver).
3182 * @param[in] pci_dev
3183 * PCI device information.
3186 * 0 on success, a negative errno value otherwise and rte_errno is set.
3189 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3190 struct rte_pci_device *pci_dev)
3192 struct ibv_device **ibv_list;
3194 * Number of found IB Devices matching with requested PCI BDF.
3195 * nd != 1 means there are multiple IB devices over the same
3196 * PCI device and we have representors and master.
3198 unsigned int nd = 0;
3200 * Number of found IB device Ports. nd = 1 and np = 1..n means
3201 * we have the single multiport IB device, and there may be
3202 * representors attached to some of found ports.
3204 unsigned int np = 0;
3206 * Number of DPDK ethernet devices to Spawn - either over
3207 * multiple IB devices or multiple ports of single IB device.
3208 * Actually this is the number of iterations to spawn.
3210 unsigned int ns = 0;
3213 * < 0 - no bonding device (single one)
3214 * >= 0 - bonding device (value is slave PF index)
3217 struct mlx5_dev_spawn_data *list = NULL;
3218 struct mlx5_dev_config dev_config;
3221 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3222 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3226 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3227 mlx5_pmd_socket_init();
3228 ret = mlx5_init_once();
3230 DRV_LOG(ERR, "unable to init PMD global data: %s",
3231 strerror(rte_errno));
3234 MLX5_ASSERT(pci_drv == &mlx5_driver);
3236 ibv_list = mlx5_glue->get_device_list(&ret);
3238 rte_errno = errno ? errno : ENOSYS;
3239 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3243 * First scan the list of all Infiniband devices to find
3244 * matching ones, gathering into the list.
3246 struct ibv_device *ibv_match[ret + 1];
3247 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3248 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3252 struct rte_pci_addr pci_addr;
3254 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3255 bd = mlx5_device_bond_pci_match
3256 (ibv_list[ret], pci_dev, nl_rdma);
3259 * Bonding device detected. Only one match is allowed,
3260 * the bonding is supported over multi-port IB device,
3261 * there should be no matches on representor PCI
3262 * functions or non VF LAG bonding devices with
3263 * specified address.
3267 "multiple PCI match on bonding device"
3268 "\"%s\" found", ibv_list[ret]->name);
3273 DRV_LOG(INFO, "PCI information matches for"
3274 " slave %d bonding device \"%s\"",
3275 bd, ibv_list[ret]->name);
3276 ibv_match[nd++] = ibv_list[ret];
3279 if (mlx5_dev_to_pci_addr
3280 (ibv_list[ret]->ibdev_path, &pci_addr))
3282 if (pci_dev->addr.domain != pci_addr.domain ||
3283 pci_dev->addr.bus != pci_addr.bus ||
3284 pci_dev->addr.devid != pci_addr.devid ||
3285 pci_dev->addr.function != pci_addr.function)
3287 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3288 ibv_list[ret]->name);
3289 ibv_match[nd++] = ibv_list[ret];
3291 ibv_match[nd] = NULL;
3293 /* No device matches, just complain and bail out. */
3295 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3296 " are kernel drivers loaded?",
3297 pci_dev->addr.domain, pci_dev->addr.bus,
3298 pci_dev->addr.devid, pci_dev->addr.function);
3305 * Found single matching device may have multiple ports.
3306 * Each port may be representor, we have to check the port
3307 * number and check the representors existence.
3310 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3312 DRV_LOG(WARNING, "can not get IB device \"%s\""
3313 " ports number", ibv_match[0]->name);
3314 if (bd >= 0 && !np) {
3315 DRV_LOG(ERR, "can not get ports"
3316 " for bonding device");
3322 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3325 * This may happen if there is VF LAG kernel support and
3326 * application is compiled with older rdma_core library.
3329 "No kernel/verbs support for VF LAG bonding found.");
3330 rte_errno = ENOTSUP;
3336 * Now we can determine the maximal
3337 * amount of devices to be spawned.
3339 list = rte_zmalloc("device spawn data",
3340 sizeof(struct mlx5_dev_spawn_data) *
3342 RTE_CACHE_LINE_SIZE);
3344 DRV_LOG(ERR, "spawn data array allocation failure");
3349 if (bd >= 0 || np > 1) {
3351 * Single IB device with multiple ports found,
3352 * it may be E-Switch master device and representors.
3353 * We have to perform identification trough the ports.
3355 MLX5_ASSERT(nl_rdma >= 0);
3356 MLX5_ASSERT(ns == 0);
3357 MLX5_ASSERT(nd == 1);
3359 for (i = 1; i <= np; ++i) {
3360 list[ns].max_port = np;
3361 list[ns].ibv_port = i;
3362 list[ns].ibv_dev = ibv_match[0];
3363 list[ns].eth_dev = NULL;
3364 list[ns].pci_dev = pci_dev;
3365 list[ns].pf_bond = bd;
3366 list[ns].ifindex = mlx5_nl_ifindex
3367 (nl_rdma, list[ns].ibv_dev->name, i);
3368 if (!list[ns].ifindex) {
3370 * No network interface index found for the
3371 * specified port, it means there is no
3372 * representor on this port. It's OK,
3373 * there can be disabled ports, for example
3374 * if sriov_numvfs < sriov_totalvfs.
3380 ret = mlx5_nl_switch_info
3384 if (ret || (!list[ns].info.representor &&
3385 !list[ns].info.master)) {
3387 * We failed to recognize representors with
3388 * Netlink, let's try to perform the task
3391 ret = mlx5_sysfs_switch_info
3395 if (!ret && bd >= 0) {
3396 switch (list[ns].info.name_type) {
3397 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3398 if (list[ns].info.port_name == bd)
3401 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3402 if (list[ns].info.pf_num == bd)
3410 if (!ret && (list[ns].info.representor ^
3411 list[ns].info.master))
3416 "unable to recognize master/representors"
3417 " on the IB device with multiple ports");
3424 * The existence of several matching entries (nd > 1) means
3425 * port representors have been instantiated. No existing Verbs
3426 * call nor sysfs entries can tell them apart, this can only
3427 * be done through Netlink calls assuming kernel drivers are
3428 * recent enough to support them.
3430 * In the event of identification failure through Netlink,
3431 * try again through sysfs, then:
3433 * 1. A single IB device matches (nd == 1) with single
3434 * port (np=0/1) and is not a representor, assume
3435 * no switch support.
3437 * 2. Otherwise no safe assumptions can be made;
3438 * complain louder and bail out.
3441 for (i = 0; i != nd; ++i) {
3442 memset(&list[ns].info, 0, sizeof(list[ns].info));
3443 list[ns].max_port = 1;
3444 list[ns].ibv_port = 1;
3445 list[ns].ibv_dev = ibv_match[i];
3446 list[ns].eth_dev = NULL;
3447 list[ns].pci_dev = pci_dev;
3448 list[ns].pf_bond = -1;
3449 list[ns].ifindex = 0;
3451 list[ns].ifindex = mlx5_nl_ifindex
3452 (nl_rdma, list[ns].ibv_dev->name, 1);
3453 if (!list[ns].ifindex) {
3454 char ifname[IF_NAMESIZE];
3457 * Netlink failed, it may happen with old
3458 * ib_core kernel driver (before 4.16).
3459 * We can assume there is old driver because
3460 * here we are processing single ports IB
3461 * devices. Let's try sysfs to retrieve
3462 * the ifindex. The method works for
3463 * master device only.
3467 * Multiple devices found, assume
3468 * representors, can not distinguish
3469 * master/representor and retrieve
3470 * ifindex via sysfs.
3474 ret = mlx5_get_master_ifname
3475 (ibv_match[i]->ibdev_path, &ifname);
3478 if_nametoindex(ifname);
3479 if (!list[ns].ifindex) {
3481 * No network interface index found
3482 * for the specified device, it means
3483 * there it is neither representor
3491 ret = mlx5_nl_switch_info
3495 if (ret || (!list[ns].info.representor &&
3496 !list[ns].info.master)) {
3498 * We failed to recognize representors with
3499 * Netlink, let's try to perform the task
3502 ret = mlx5_sysfs_switch_info
3506 if (!ret && (list[ns].info.representor ^
3507 list[ns].info.master)) {
3509 } else if ((nd == 1) &&
3510 !list[ns].info.representor &&
3511 !list[ns].info.master) {
3513 * Single IB device with
3514 * one physical port and
3515 * attached network device.
3516 * May be SRIOV is not enabled
3517 * or there is no representors.
3519 DRV_LOG(INFO, "no E-Switch support detected");
3526 "unable to recognize master/representors"
3527 " on the multiple IB devices");
3535 * Sort list to probe devices in natural order for users convenience
3536 * (i.e. master first, then representors from lowest to highest ID).
3538 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3539 /* Default configuration. */
3540 dev_config = (struct mlx5_dev_config){
3542 .mps = MLX5_ARG_UNSET,
3543 .dbnc = MLX5_ARG_UNSET,
3545 .txq_inline_max = MLX5_ARG_UNSET,
3546 .txq_inline_min = MLX5_ARG_UNSET,
3547 .txq_inline_mpw = MLX5_ARG_UNSET,
3548 .txqs_inline = MLX5_ARG_UNSET,
3550 .mr_ext_memseg_en = 1,
3552 .enabled = 0, /* Disabled by default. */
3555 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3556 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3560 .log_hp_size = MLX5_ARG_UNSET,
3562 /* Device specific configuration. */
3563 switch (pci_dev->id.device_id) {
3564 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3565 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3566 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3567 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3568 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3569 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3570 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3576 for (i = 0; i != ns; ++i) {
3579 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3582 if (!list[i].eth_dev) {
3583 if (rte_errno != EBUSY && rte_errno != EEXIST)
3585 /* Device is disabled or already spawned. Ignore it. */
3588 restore = list[i].eth_dev->data->dev_flags;
3589 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3590 /* Restore non-PCI flags cleared by the above call. */
3591 list[i].eth_dev->data->dev_flags |= restore;
3592 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3593 rte_eth_dev_probing_finish(list[i].eth_dev);
3597 "probe of PCI device " PCI_PRI_FMT " aborted after"
3598 " encountering an error: %s",
3599 pci_dev->addr.domain, pci_dev->addr.bus,
3600 pci_dev->addr.devid, pci_dev->addr.function,
3601 strerror(rte_errno));
3605 if (!list[i].eth_dev)
3607 mlx5_dev_close(list[i].eth_dev);
3608 /* mac_addrs must not be freed because in dev_private */
3609 list[i].eth_dev->data->mac_addrs = NULL;
3610 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3612 /* Restore original error. */
3619 * Do the routine cleanup:
3620 * - close opened Netlink sockets
3621 * - free allocated spawn data array
3622 * - free the Infiniband device list
3630 MLX5_ASSERT(ibv_list);
3631 mlx5_glue->free_device_list(ibv_list);
3636 * Look for the ethernet device belonging to mlx5 driver.
3638 * @param[in] port_id
3639 * port_id to start looking for device.
3640 * @param[in] pci_dev
3641 * Pointer to the hint PCI device. When device is being probed
3642 * the its siblings (master and preceding representors might
3643 * not have assigned driver yet (because the mlx5_pci_probe()
3644 * is not completed yet, for this case match on hint PCI
3645 * device may be used to detect sibling device.
3648 * port_id of found device, RTE_MAX_ETHPORT if not found.
3651 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3653 while (port_id < RTE_MAX_ETHPORTS) {
3654 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3656 if (dev->state != RTE_ETH_DEV_UNUSED &&
3658 (dev->device == &pci_dev->device ||
3659 (dev->device->driver &&
3660 dev->device->driver->name &&
3661 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3665 if (port_id >= RTE_MAX_ETHPORTS)
3666 return RTE_MAX_ETHPORTS;
3671 * DPDK callback to remove a PCI device.
3673 * This function removes all Ethernet devices belong to a given PCI device.
3675 * @param[in] pci_dev
3676 * Pointer to the PCI device.
3679 * 0 on success, the function cannot fail.
3682 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3686 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3687 rte_eth_dev_close(port_id);
3691 static const struct rte_pci_id mlx5_pci_id_map[] = {
3693 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3694 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3697 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3698 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3701 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3702 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3705 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3706 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3709 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3710 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3713 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3714 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3717 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3718 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3721 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3722 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3725 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3726 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3729 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3730 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3733 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3734 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3737 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3738 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3741 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3742 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3745 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3746 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3749 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3750 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3757 static struct rte_pci_driver mlx5_driver = {
3759 .name = MLX5_DRIVER_NAME
3761 .id_table = mlx5_pci_id_map,
3762 .probe = mlx5_pci_probe,
3763 .remove = mlx5_pci_remove,
3764 .dma_map = mlx5_dma_map,
3765 .dma_unmap = mlx5_dma_unmap,
3766 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3767 RTE_PCI_DRV_PROBE_AGAIN,
3771 * Driver initialization routine.
3773 RTE_INIT(rte_mlx5_pmd_init)
3775 /* Initialize driver log type. */
3776 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3777 if (mlx5_logtype >= 0)
3778 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3780 /* Build the static tables for Verbs conversion. */
3781 mlx5_set_ptype_table();
3782 mlx5_set_cksum_table();
3783 mlx5_set_swp_types_table();
3785 rte_pci_register(&mlx5_driver);
3788 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3789 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3790 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");