drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_mp.h>
  42
  43 #include "mlx5_defs.h"
  44 #include "mlx5.h"
  45 #include "mlx5_utils.h"
  46 #include "mlx5_rxtx.h"
  47 #include "mlx5_autoconf.h"
  48 #include "mlx5_mr.h"
  49 #include "mlx5_flow.h"
  50 #include "rte_pmd_mlx5.h"
  51
  52 /* Device parameter to enable RX completion queue compression. */
  53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  54
  55 /* Device parameter to enable RX completion entry padding to 128B. */
  56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  57
  58 /* Device parameter to enable padding Rx packet to cacheline size. */
  59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  60
  61 /* Device parameter to enable Multi-Packet Rx queue. */
  62 #define MLX5_RX_MPRQ_EN "mprq_en"
  63
  64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  66
  67 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  69
  70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  72
  73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  75
  76 /* Device parameter to configure inline send. Deprecated, ignored.*/
  77 #define MLX5_TXQ_INLINE "txq_inline"
  78
  79 /* Device parameter to limit packet size to inline with ordinary SEND. */
  80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  81
  82 /* Device parameter to configure minimal data size to inline. */
  83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  84
  85 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  87
  88 /*
  89  * Device parameter to configure the number of TX queues threshold for
  90  * enabling inline send.
  91  */
  92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  93
  94 /*
  95  * Device parameter to configure the number of TX queues threshold for
  96  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  97  */
  98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  99
 100 /* Device parameter to enable multi-packet send WQEs. */
 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 102
 103 /*
 104  * Device parameter to force doorbell register mapping
 105  * to non-cahed region eliminating the extra write memory barrier.
 106  */
 107 #define MLX5_TX_DB_NC "tx_db_nc"
 108
 109 /*
 110  * Device parameter to include 2 dsegs in the title WQEBB.
 111  * Deprecated, ignored.
 112  */
 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 114
 115 /*
 116  * Device parameter to limit the size of inlining packet.
 117  * Deprecated, ignored.
 118  */
 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 120
 121 /*
 122  * Device parameter to enable hardware Tx vector.
 123  * Deprecated, ignored (no vectorized Tx routines anymore).
 124  */
 125 #define MLX5_TX_VEC_EN "tx_vec_en"
 126
 127 /* Device parameter to enable hardware Rx vector. */
 128 #define MLX5_RX_VEC_EN "rx_vec_en"
 129
 130 /* Allow L3 VXLAN flow creation. */
 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 132
 133 /* Activate DV E-Switch flow steering. */
 134 #define MLX5_DV_ESW_EN "dv_esw_en"
 135
 136 /* Activate DV flow steering. */
 137 #define MLX5_DV_FLOW_EN "dv_flow_en"
 138
 139 /* Enable extensive flow metadata support. */
 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 141
 142 /* Activate Netlink support in VF mode. */
 143 #define MLX5_VF_NL_EN "vf_nl_en"
 144
 145 /* Enable extending memsegs when creating a MR. */
 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 147
 148 /* Select port representors to instantiate. */
 149 #define MLX5_REPRESENTOR "representor"
 150
 151 /* Device parameter to configure the maximum number of dump files per queue. */
 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 153
 154 /* Configure timeout of LRO session (in microseconds). */
 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 156
 157 /*
 158  * Device parameter to configure the total data buffer size for a single
 159  * hairpin queue (logarithm value).
 160  */
 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 162
 163 /* Flow memory reclaim mode. */
 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 165
 166 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 167
 168 /* Shared memory between primary and secondary processes. */
 169 struct mlx5_shared_data *mlx5_shared_data;
 170
 171 /* Spinlock for mlx5_shared_data allocation. */
 172 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 173
 174 /* Process local data for secondary processes. */
 175 static struct mlx5_local_data mlx5_local_data;
 176 /** Driver-specific log messages type. */
 177 int mlx5_logtype;
 178
 179 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 180                                                 LIST_HEAD_INITIALIZER();
 181 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 182
 183 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 184 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 185         {
 186                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 187                 .trunk_size = 64,
 188                 .grow_trunk = 3,
 189                 .grow_shift = 2,
 190                 .need_lock = 0,
 191                 .release_mem_en = 1,
 192                 .malloc = rte_malloc_socket,
 193                 .free = rte_free,
 194                 .type = "mlx5_encap_decap_ipool",
 195         },
 196         {
 197                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 198                 .trunk_size = 64,
 199                 .grow_trunk = 3,
 200                 .grow_shift = 2,
 201                 .need_lock = 0,
 202                 .release_mem_en = 1,
 203                 .malloc = rte_malloc_socket,
 204                 .free = rte_free,
 205                 .type = "mlx5_push_vlan_ipool",
 206         },
 207         {
 208                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 209                 .trunk_size = 64,
 210                 .grow_trunk = 3,
 211                 .grow_shift = 2,
 212                 .need_lock = 0,
 213                 .release_mem_en = 1,
 214                 .malloc = rte_malloc_socket,
 215                 .free = rte_free,
 216                 .type = "mlx5_tag_ipool",
 217         },
 218         {
 219                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 220                 .trunk_size = 64,
 221                 .grow_trunk = 3,
 222                 .grow_shift = 2,
 223                 .need_lock = 0,
 224                 .release_mem_en = 1,
 225                 .malloc = rte_malloc_socket,
 226                 .free = rte_free,
 227                 .type = "mlx5_port_id_ipool",
 228         },
 229         {
 230                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 231                 .trunk_size = 64,
 232                 .grow_trunk = 3,
 233                 .grow_shift = 2,
 234                 .need_lock = 0,
 235                 .release_mem_en = 1,
 236                 .malloc = rte_malloc_socket,
 237                 .free = rte_free,
 238                 .type = "mlx5_jump_ipool",
 239         },
 240 #endif
 241         {
 242                 .size = sizeof(struct mlx5_flow_meter),
 243                 .trunk_size = 64,
 244                 .grow_trunk = 3,
 245                 .grow_shift = 2,
 246                 .need_lock = 0,
 247                 .release_mem_en = 1,
 248                 .malloc = rte_malloc_socket,
 249                 .free = rte_free,
 250                 .type = "mlx5_meter_ipool",
 251         },
 252         {
 253                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 254                 .trunk_size = 64,
 255                 .grow_trunk = 3,
 256                 .grow_shift = 2,
 257                 .need_lock = 0,
 258                 .release_mem_en = 1,
 259                 .malloc = rte_malloc_socket,
 260                 .free = rte_free,
 261                 .type = "mlx5_mcp_ipool",
 262         },
 263         {
 264                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 265                 .trunk_size = 64,
 266                 .grow_trunk = 3,
 267                 .grow_shift = 2,
 268                 .need_lock = 0,
 269                 .release_mem_en = 1,
 270                 .malloc = rte_malloc_socket,
 271                 .free = rte_free,
 272                 .type = "mlx5_hrxq_ipool",
 273         },
 274         {
 275                 /*
 276                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 277                  * It set in run time according to PCI function configuration.
 278                  */
 279                 .size = 0,
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_flow_handle_ipool",
 288         },
 289         {
 290                 .size = sizeof(struct rte_flow),
 291                 .trunk_size = 4096,
 292                 .need_lock = 1,
 293                 .release_mem_en = 1,
 294                 .malloc = rte_malloc_socket,
 295                 .free = rte_free,
 296                 .type = "rte_flow_ipool",
 297         },
 298 };
 299
 300
 301 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 302 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 303
 304 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 305
 306 /**
 307  * Allocate ID pool structure.
 308  *
 309  * @param[in] max_id
 310  *   The maximum id can be allocated from the pool.
 311  *
 312  * @return
 313  *   Pointer to pool object, NULL value otherwise.
 314  */
 315 struct mlx5_flow_id_pool *
 316 mlx5_flow_id_pool_alloc(uint32_t max_id)
 317 {
 318         struct mlx5_flow_id_pool *pool;
 319         void *mem;
 320
 321         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 322                            RTE_CACHE_LINE_SIZE);
 323         if (!pool) {
 324                 DRV_LOG(ERR, "can't allocate id pool");
 325                 rte_errno  = ENOMEM;
 326                 return NULL;
 327         }
 328         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 329                           RTE_CACHE_LINE_SIZE);
 330         if (!mem) {
 331                 DRV_LOG(ERR, "can't allocate mem for id pool");
 332                 rte_errno  = ENOMEM;
 333                 goto error;
 334         }
 335         pool->free_arr = mem;
 336         pool->curr = pool->free_arr;
 337         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 338         pool->base_index = 0;
 339         pool->max_id = max_id;
 340         return pool;
 341 error:
 342         rte_free(pool);
 343         return NULL;
 344 }
 345
 346 /**
 347  * Release ID pool structure.
 348  *
 349  * @param[in] pool
 350  *   Pointer to flow id pool object to free.
 351  */
 352 void
 353 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 354 {
 355         rte_free(pool->free_arr);
 356         rte_free(pool);
 357 }
 358
 359 /**
 360  * Generate ID.
 361  *
 362  * @param[in] pool
 363  *   Pointer to flow id pool.
 364  * @param[out] id
 365  *   The generated ID.
 366  *
 367  * @return
 368  *   0 on success, error value otherwise.
 369  */
 370 uint32_t
 371 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 372 {
 373         if (pool->curr == pool->free_arr) {
 374                 if (pool->base_index == pool->max_id) {
 375                         rte_errno  = ENOMEM;
 376                         DRV_LOG(ERR, "no free id");
 377                         return -rte_errno;
 378                 }
 379                 *id = ++pool->base_index;
 380                 return 0;
 381         }
 382         *id = *(--pool->curr);
 383         return 0;
 384 }
 385
 386 /**
 387  * Release ID.
 388  *
 389  * @param[in] pool
 390  *   Pointer to flow id pool.
 391  * @param[out] id
 392  *   The generated ID.
 393  *
 394  * @return
 395  *   0 on success, error value otherwise.
 396  */
 397 uint32_t
 398 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 399 {
 400         uint32_t size;
 401         uint32_t size2;
 402         void *mem;
 403
 404         if (pool->curr == pool->last) {
 405                 size = pool->curr - pool->free_arr;
 406                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 407                 MLX5_ASSERT(size2 > size);
 408                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 409                 if (!mem) {
 410                         DRV_LOG(ERR, "can't allocate mem for id pool");
 411                         rte_errno  = ENOMEM;
 412                         return -rte_errno;
 413                 }
 414                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 415                 rte_free(pool->free_arr);
 416                 pool->free_arr = mem;
 417                 pool->curr = pool->free_arr + size;
 418                 pool->last = pool->free_arr + size2;
 419         }
 420         *pool->curr = id;
 421         pool->curr++;
 422         return 0;
 423 }
 424
 425 /**
 426  * Initialize the shared aging list information per port.
 427  *
 428  * @param[in] sh
 429  *   Pointer to mlx5_dev_ctx_shared object.
 430  */
 431 static void
 432 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 433 {
 434         uint32_t i;
 435         struct mlx5_age_info *age_info;
 436
 437         for (i = 0; i < sh->max_port; i++) {
 438                 age_info = &sh->port[i].age_info;
 439                 age_info->flags = 0;
 440                 TAILQ_INIT(&age_info->aged_counters);
 441                 rte_spinlock_init(&age_info->aged_sl);
 442                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 443         }
 444 }
 445
 446 /**
 447  * Initialize the counters management structure.
 448  *
 449  * @param[in] sh
 450  *   Pointer to mlx5_dev_ctx_shared object to free
 451  */
 452 static void
 453 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 454 {
 455         int i;
 456
 457         memset(&sh->cmng, 0, sizeof(sh->cmng));
 458         TAILQ_INIT(&sh->cmng.flow_counters);
 459         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 460                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 461                 sh->cmng.ccont[i].max_id = -1;
 462                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 463                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 464                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 465                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 466                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 467         }
 468 }
 469
 470 /**
 471  * Destroy all the resources allocated for a counter memory management.
 472  *
 473  * @param[in] mng
 474  *   Pointer to the memory management structure.
 475  */
 476 static void
 477 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 478 {
 479         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 480
 481         LIST_REMOVE(mng, next);
 482         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 483         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 484         rte_free(mem);
 485 }
 486
 487 /**
 488  * Close and release all the resources of the counters management.
 489  *
 490  * @param[in] sh
 491  *   Pointer to mlx5_dev_ctx_shared object to free.
 492  */
 493 static void
 494 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 495 {
 496         struct mlx5_counter_stats_mem_mng *mng;
 497         int i;
 498         int j;
 499         int retries = 1024;
 500
 501         rte_errno = 0;
 502         while (--retries) {
 503                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 504                 if (rte_errno != EINPROGRESS)
 505                         break;
 506                 rte_pause();
 507         }
 508         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 509                 struct mlx5_flow_counter_pool *pool;
 510                 uint32_t batch = !!(i > 1);
 511
 512                 if (!sh->cmng.ccont[i].pools)
 513                         continue;
 514                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 515                 while (pool) {
 516                         if (batch && pool->min_dcs)
 517                                 claim_zero(mlx5_devx_cmd_destroy
 518                                                                (pool->min_dcs));
 519                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 520                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 521                                         claim_zero
 522                                          (mlx5_glue->destroy_flow_action
 523                                           (MLX5_POOL_GET_CNT
 524                                           (pool, j)->action));
 525                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 526                                     (pool, j)->dcs)
 527                                         claim_zero(mlx5_devx_cmd_destroy
 528                                                    (MLX5_GET_POOL_CNT_EXT
 529                                                     (pool, j)->dcs));
 530                         }
 531                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 532                         rte_free(pool);
 533                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 534                 }
 535                 rte_free(sh->cmng.ccont[i].pools);
 536         }
 537         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 538         while (mng) {
 539                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 540                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 541         }
 542         memset(&sh->cmng, 0, sizeof(sh->cmng));
 543 }
 544
 545 /**
 546  * Initialize the flow resources' indexed mempool.
 547  *
 548  * @param[in] sh
 549  *   Pointer to mlx5_dev_ctx_shared object.
 550  * @param[in] sh
 551  *   Pointer to user dev config.
 552  */
 553 static void
 554 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 555                        const struct mlx5_dev_config *config)
 556 {
 557         uint8_t i;
 558         struct mlx5_indexed_pool_config cfg;
 559
 560         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 561                 cfg = mlx5_ipool_cfg[i];
 562                 switch (i) {
 563                 default:
 564                         break;
 565                 /*
 566                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 567                  * according to PCI function flow configuration.
 568                  */
 569                 case MLX5_IPOOL_MLX5_FLOW:
 570                         cfg.size = config->dv_flow_en ?
 571                                 sizeof(struct mlx5_flow_handle) :
 572                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 573                         break;
 574                 }
 575                 if (config->reclaim_mode)
 576                         cfg.release_mem_en = 1;
 577                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 578         }
 579 }
 580
 581 /**
 582  * Release the flow resources' indexed mempool.
 583  *
 584  * @param[in] sh
 585  *   Pointer to mlx5_dev_ctx_shared object.
 586  */
 587 static void
 588 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 589 {
 590         uint8_t i;
 591
 592         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 593                 mlx5_ipool_destroy(sh->ipool[i]);
 594 }
 595
 596 /**
 597  * Allocate shared device context. If there is multiport device the
 598  * master and representors will share this context, if there is single
 599  * port dedicated device, the context will be used by only given
 600  * port due to unification.
 601  *
 602  * Routine first searches the context for the specified device name,
 603  * if found the shared context assumed and reference counter is incremented.
 604  * If no context found the new one is created and initialized with specified
 605  * device context and parameters.
 606  *
 607  * @param[in] spawn
 608  *   Pointer to the device attributes (name, port, etc).
 609  * @param[in] config
 610  *   Pointer to device configuration structure.
 611  *
 612  * @return
 613  *   Pointer to mlx5_dev_ctx_shared object on success,
 614  *   otherwise NULL and rte_errno is set.
 615  */
 616 struct mlx5_dev_ctx_shared *
 617 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 618                            const struct mlx5_dev_config *config)
 619 {
 620         struct mlx5_dev_ctx_shared *sh;
 621         int err = 0;
 622         uint32_t i;
 623         struct mlx5_devx_tis_attr tis_attr = { 0 };
 624
 625         MLX5_ASSERT(spawn);
 626         /* Secondary process should not create the shared context. */
 627         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 628         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 629         /* Search for IB context by device name. */
 630         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 631                 if (!strcmp(sh->ibdev_name,
 632                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 633                         sh->refcnt++;
 634                         goto exit;
 635                 }
 636         }
 637         /* No device found, we have to create new shared context. */
 638         MLX5_ASSERT(spawn->max_port);
 639         sh = rte_zmalloc("ethdev shared ib context",
 640                          sizeof(struct mlx5_dev_ctx_shared) +
 641                          spawn->max_port *
 642                          sizeof(struct mlx5_dev_shared_port),
 643                          RTE_CACHE_LINE_SIZE);
 644         if (!sh) {
 645                 DRV_LOG(ERR, "shared context allocation failure");
 646                 rte_errno  = ENOMEM;
 647                 goto exit;
 648         }
 649         err = mlx5_os_open_device(spawn, config, sh);
 650         if (!sh->ctx)
 651                 goto error;
 652         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 653         if (err) {
 654                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 655                 goto error;
 656         }
 657         sh->refcnt = 1;
 658         sh->max_port = spawn->max_port;
 659         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 660                 sizeof(sh->ibdev_name) - 1);
 661         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 662                 sizeof(sh->ibdev_path) - 1);
 663         /*
 664          * Setting port_id to max unallowed value means
 665          * there is no interrupt subhandler installed for
 666          * the given port index i.
 667          */
 668         for (i = 0; i < sh->max_port; i++) {
 669                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 670                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 671         }
 672         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 673         if (sh->pd == NULL) {
 674                 DRV_LOG(ERR, "PD allocation failure");
 675                 err = ENOMEM;
 676                 goto error;
 677         }
 678         if (sh->devx) {
 679                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 680                 if (err) {
 681                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 682                         goto error;
 683                 }
 684                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 685                 if (!sh->td) {
 686                         DRV_LOG(ERR, "TD allocation failure");
 687                         err = ENOMEM;
 688                         goto error;
 689                 }
 690                 tis_attr.transport_domain = sh->td->id;
 691                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 692                 if (!sh->tis) {
 693                         DRV_LOG(ERR, "TIS allocation failure");
 694                         err = ENOMEM;
 695                         goto error;
 696                 }
 697         }
 698         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 699                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 700         if (!sh->flow_id_pool) {
 701                 DRV_LOG(ERR, "can't create flow id pool");
 702                 err = ENOMEM;
 703                 goto error;
 704         }
 705         /*
 706          * Once the device is added to the list of memory event
 707          * callback, its global MR cache table cannot be expanded
 708          * on the fly because of deadlock. If it overflows, lookup
 709          * should be done by searching MR list linearly, which is slow.
 710          *
 711          * At this point the device is not added to the memory
 712          * event list yet, context is just being created.
 713          */
 714         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 715                                  MLX5_MR_BTREE_CACHE_N * 2,
 716                                  spawn->pci_dev->device.numa_node);
 717         if (err) {
 718                 err = rte_errno;
 719                 goto error;
 720         }
 721         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 722                               &sh->share_cache.dereg_mr_cb);
 723         mlx5_os_dev_shared_handler_install(sh);
 724         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 725         if (!sh->cnt_id_tbl) {
 726                 err = rte_errno;
 727                 goto error;
 728         }
 729         mlx5_flow_aging_init(sh);
 730         mlx5_flow_counters_mng_init(sh);
 731         mlx5_flow_ipool_create(sh, config);
 732         /* Add device to memory callback list. */
 733         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 734         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 735                          sh, mem_event_cb);
 736         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 737         /* Add context to the global device list. */
 738         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 739 exit:
 740         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 741         return sh;
 742 error:
 743         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 744         MLX5_ASSERT(sh);
 745         if (sh->cnt_id_tbl) {
 746                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 747                 sh->cnt_id_tbl = NULL;
 748         }
 749         if (sh->tis)
 750                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 751         if (sh->td)
 752                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 753         if (sh->pd)
 754                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 755         if (sh->ctx)
 756                 claim_zero(mlx5_glue->close_device(sh->ctx));
 757         if (sh->flow_id_pool)
 758                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 759         rte_free(sh);
 760         MLX5_ASSERT(err > 0);
 761         rte_errno = err;
 762         return NULL;
 763 }
 764
 765 /**
 766  * Free shared IB device context. Decrement counter and if zero free
 767  * all allocated resources and close handles.
 768  *
 769  * @param[in] sh
 770  *   Pointer to mlx5_dev_ctx_shared object to free
 771  */
 772 void
 773 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 774 {
 775         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 776 #ifdef RTE_LIBRTE_MLX5_DEBUG
 777         /* Check the object presence in the list. */
 778         struct mlx5_dev_ctx_shared *lctx;
 779
 780         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 781                 if (lctx == sh)
 782                         break;
 783         MLX5_ASSERT(lctx);
 784         if (lctx != sh) {
 785                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 786                 goto exit;
 787         }
 788 #endif
 789         MLX5_ASSERT(sh);
 790         MLX5_ASSERT(sh->refcnt);
 791         /* Secondary process should not free the shared context. */
 792         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 793         if (--sh->refcnt)
 794                 goto exit;
 795         /* Remove from memory callback device list. */
 796         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 797         LIST_REMOVE(sh, mem_event_cb);
 798         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 799         /* Release created Memory Regions. */
 800         mlx5_mr_release_cache(&sh->share_cache);
 801         /* Remove context from the global device list. */
 802         LIST_REMOVE(sh, next);
 803         /*
 804          *  Ensure there is no async event handler installed.
 805          *  Only primary process handles async device events.
 806          **/
 807         mlx5_flow_counters_mng_close(sh);
 808         mlx5_flow_ipool_destroy(sh);
 809         mlx5_os_dev_shared_handler_uninstall(sh);
 810         if (sh->cnt_id_tbl) {
 811                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 812                 sh->cnt_id_tbl = NULL;
 813         }
 814         if (sh->pd)
 815                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 816         if (sh->tis)
 817                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 818         if (sh->td)
 819                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 820         if (sh->ctx)
 821                 claim_zero(mlx5_glue->close_device(sh->ctx));
 822         if (sh->flow_id_pool)
 823                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 824         rte_free(sh);
 825 exit:
 826         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 827 }
 828
 829 /**
 830  * Destroy table hash list and all the root entries per domain.
 831  *
 832  * @param[in] priv
 833  *   Pointer to the private device data structure.
 834  */
 835 void
 836 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 837 {
 838         struct mlx5_dev_ctx_shared *sh = priv->sh;
 839         struct mlx5_flow_tbl_data_entry *tbl_data;
 840         union mlx5_flow_tbl_key table_key = {
 841                 {
 842                         .table_id = 0,
 843                         .reserved = 0,
 844                         .domain = 0,
 845                         .direction = 0,
 846                 }
 847         };
 848         struct mlx5_hlist_entry *pos;
 849
 850         if (!sh->flow_tbls)
 851                 return;
 852         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 853         if (pos) {
 854                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 855                                         entry);
 856                 MLX5_ASSERT(tbl_data);
 857                 mlx5_hlist_remove(sh->flow_tbls, pos);
 858                 rte_free(tbl_data);
 859         }
 860         table_key.direction = 1;
 861         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 862         if (pos) {
 863                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 864                                         entry);
 865                 MLX5_ASSERT(tbl_data);
 866                 mlx5_hlist_remove(sh->flow_tbls, pos);
 867                 rte_free(tbl_data);
 868         }
 869         table_key.direction = 0;
 870         table_key.domain = 1;
 871         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 872         if (pos) {
 873                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 874                                         entry);
 875                 MLX5_ASSERT(tbl_data);
 876                 mlx5_hlist_remove(sh->flow_tbls, pos);
 877                 rte_free(tbl_data);
 878         }
 879         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 880 }
 881
 882 /**
 883  * Initialize flow table hash list and create the root tables entry
 884  * for each domain.
 885  *
 886  * @param[in] priv
 887  *   Pointer to the private device data structure.
 888  *
 889  * @return
 890  *   Zero on success, positive error code otherwise.
 891  */
 892 int
 893 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 894 {
 895         struct mlx5_dev_ctx_shared *sh = priv->sh;
 896         char s[MLX5_HLIST_NAMESIZE];
 897         int err = 0;
 898
 899         MLX5_ASSERT(sh);
 900         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 901         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 902         if (!sh->flow_tbls) {
 903                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 904                 err = ENOMEM;
 905                 return err;
 906         }
 907 #ifndef HAVE_MLX5DV_DR
 908         /*
 909          * In case we have not DR support, the zero tables should be created
 910          * because DV expect to see them even if they cannot be created by
 911          * RDMA-CORE.
 912          */
 913         union mlx5_flow_tbl_key table_key = {
 914                 {
 915                         .table_id = 0,
 916                         .reserved = 0,
 917                         .domain = 0,
 918                         .direction = 0,
 919                 }
 920         };
 921         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 922                                                           sizeof(*tbl_data), 0);
 923
 924         if (!tbl_data) {
 925                 err = ENOMEM;
 926                 goto error;
 927         }
 928         tbl_data->entry.key = table_key.v64;
 929         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 930         if (err)
 931                 goto error;
 932         rte_atomic32_init(&tbl_data->tbl.refcnt);
 933         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 934         table_key.direction = 1;
 935         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 936         if (!tbl_data) {
 937                 err = ENOMEM;
 938                 goto error;
 939         }
 940         tbl_data->entry.key = table_key.v64;
 941         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 942         if (err)
 943                 goto error;
 944         rte_atomic32_init(&tbl_data->tbl.refcnt);
 945         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 946         table_key.direction = 0;
 947         table_key.domain = 1;
 948         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 949         if (!tbl_data) {
 950                 err = ENOMEM;
 951                 goto error;
 952         }
 953         tbl_data->entry.key = table_key.v64;
 954         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 955         if (err)
 956                 goto error;
 957         rte_atomic32_init(&tbl_data->tbl.refcnt);
 958         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 959         return err;
 960 error:
 961         mlx5_free_table_hash_list(priv);
 962 #endif /* HAVE_MLX5DV_DR */
 963         return err;
 964 }
 965
 966 /**
 967  * Initialize shared data between primary and secondary process.
 968  *
 969  * A memzone is reserved by primary process and secondary processes attach to
 970  * the memzone.
 971  *
 972  * @return
 973  *   0 on success, a negative errno value otherwise and rte_errno is set.
 974  */
 975 static int
 976 mlx5_init_shared_data(void)
 977 {
 978         const struct rte_memzone *mz;
 979         int ret = 0;
 980
 981         rte_spinlock_lock(&mlx5_shared_data_lock);
 982         if (mlx5_shared_data == NULL) {
 983                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
 984                         /* Allocate shared memory. */
 985                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
 986                                                  sizeof(*mlx5_shared_data),
 987                                                  SOCKET_ID_ANY, 0);
 988                         if (mz == NULL) {
 989                                 DRV_LOG(ERR,
 990                                         "Cannot allocate mlx5 shared data");
 991                                 ret = -rte_errno;
 992                                 goto error;
 993                         }
 994                         mlx5_shared_data = mz->addr;
 995                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
 996                         rte_spinlock_init(&mlx5_shared_data->lock);
 997                 } else {
 998                         /* Lookup allocated shared memory. */
 999                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1000                         if (mz == NULL) {
1001                                 DRV_LOG(ERR,
1002                                         "Cannot attach mlx5 shared data");
1003                                 ret = -rte_errno;
1004                                 goto error;
1005                         }
1006                         mlx5_shared_data = mz->addr;
1007                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1008                 }
1009         }
1010 error:
1011         rte_spinlock_unlock(&mlx5_shared_data_lock);
1012         return ret;
1013 }
1014
1015 /**
1016  * Retrieve integer value from environment variable.
1017  *
1018  * @param[in] name
1019  *   Environment variable name.
1020  *
1021  * @return
1022  *   Integer value, 0 if the variable is not set.
1023  */
1024 int
1025 mlx5_getenv_int(const char *name)
1026 {
1027         const char *val = getenv(name);
1028
1029         if (val == NULL)
1030                 return 0;
1031         return atoi(val);
1032 }
1033
1034 /**
1035  * DPDK callback to add udp tunnel port
1036  *
1037  * @param[in] dev
1038  *   A pointer to eth_dev
1039  * @param[in] udp_tunnel
1040  *   A pointer to udp tunnel
1041  *
1042  * @return
1043  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1044  */
1045 int
1046 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1047                          struct rte_eth_udp_tunnel *udp_tunnel)
1048 {
1049         MLX5_ASSERT(udp_tunnel != NULL);
1050         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1051             udp_tunnel->udp_port == 4789)
1052                 return 0;
1053         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1054             udp_tunnel->udp_port == 4790)
1055                 return 0;
1056         return -ENOTSUP;
1057 }
1058
1059 /**
1060  * Initialize process private data structure.
1061  *
1062  * @param dev
1063  *   Pointer to Ethernet device structure.
1064  *
1065  * @return
1066  *   0 on success, a negative errno value otherwise and rte_errno is set.
1067  */
1068 int
1069 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1070 {
1071         struct mlx5_priv *priv = dev->data->dev_private;
1072         struct mlx5_proc_priv *ppriv;
1073         size_t ppriv_size;
1074
1075         /*
1076          * UAR register table follows the process private structure. BlueFlame
1077          * registers for Tx queues are stored in the table.
1078          */
1079         ppriv_size =
1080                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1081         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1082                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1083         if (!ppriv) {
1084                 rte_errno = ENOMEM;
1085                 return -rte_errno;
1086         }
1087         ppriv->uar_table_sz = ppriv_size;
1088         dev->process_private = ppriv;
1089         return 0;
1090 }
1091
1092 /**
1093  * Un-initialize process private data structure.
1094  *
1095  * @param dev
1096  *   Pointer to Ethernet device structure.
1097  */
1098 static void
1099 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1100 {
1101         if (!dev->process_private)
1102                 return;
1103         rte_free(dev->process_private);
1104         dev->process_private = NULL;
1105 }
1106
1107 /**
1108  * DPDK callback to close the device.
1109  *
1110  * Destroy all queues and objects, free memory.
1111  *
1112  * @param dev
1113  *   Pointer to Ethernet device structure.
1114  */
1115 void
1116 mlx5_dev_close(struct rte_eth_dev *dev)
1117 {
1118         struct mlx5_priv *priv = dev->data->dev_private;
1119         unsigned int i;
1120         int ret;
1121
1122         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1123                 /* Check if process_private released. */
1124                 if (!dev->process_private)
1125                         return;
1126                 mlx5_tx_uar_uninit_secondary(dev);
1127                 mlx5_proc_priv_uninit(dev);
1128                 rte_eth_dev_release_port(dev);
1129                 return;
1130         }
1131         if (!priv->sh)
1132                 return;
1133         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1134                 dev->data->port_id,
1135                 ((priv->sh->ctx != NULL) ?
1136                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1137         /*
1138          * If default mreg copy action is removed at the stop stage,
1139          * the search will return none and nothing will be done anymore.
1140          */
1141         mlx5_flow_stop_default(dev);
1142         mlx5_traffic_disable(dev);
1143         /*
1144          * If all the flows are already flushed in the device stop stage,
1145          * then this will return directly without any action.
1146          */
1147         mlx5_flow_list_flush(dev, &priv->flows, true);
1148         mlx5_flow_meter_flush(dev, NULL);
1149         /* Free the intermediate buffers for flow creation. */
1150         mlx5_flow_free_intermediate(dev);
1151         /* Prevent crashes when queues are still in use. */
1152         dev->rx_pkt_burst = removed_rx_burst;
1153         dev->tx_pkt_burst = removed_tx_burst;
1154         rte_wmb();
1155         /* Disable datapath on secondary process. */
1156         mlx5_mp_req_stop_rxtx(dev);
1157         if (priv->rxqs != NULL) {
1158                 /* XXX race condition if mlx5_rx_burst() is still running. */
1159                 usleep(1000);
1160                 for (i = 0; (i != priv->rxqs_n); ++i)
1161                         mlx5_rxq_release(dev, i);
1162                 priv->rxqs_n = 0;
1163                 priv->rxqs = NULL;
1164         }
1165         if (priv->txqs != NULL) {
1166                 /* XXX race condition if mlx5_tx_burst() is still running. */
1167                 usleep(1000);
1168                 for (i = 0; (i != priv->txqs_n); ++i)
1169                         mlx5_txq_release(dev, i);
1170                 priv->txqs_n = 0;
1171                 priv->txqs = NULL;
1172         }
1173         mlx5_proc_priv_uninit(dev);
1174         if (priv->mreg_cp_tbl)
1175                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1176         mlx5_mprq_free_mp(dev);
1177         mlx5_os_free_shared_dr(priv);
1178         if (priv->rss_conf.rss_key != NULL)
1179                 rte_free(priv->rss_conf.rss_key);
1180         if (priv->reta_idx != NULL)
1181                 rte_free(priv->reta_idx);
1182         if (priv->config.vf)
1183                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1184                                        dev->data->mac_addrs,
1185                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1186         if (priv->nl_socket_route >= 0)
1187                 close(priv->nl_socket_route);
1188         if (priv->nl_socket_rdma >= 0)
1189                 close(priv->nl_socket_rdma);
1190         if (priv->vmwa_context)
1191                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1192         ret = mlx5_hrxq_verify(dev);
1193         if (ret)
1194                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1195                         dev->data->port_id);
1196         ret = mlx5_ind_table_obj_verify(dev);
1197         if (ret)
1198                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1199                         dev->data->port_id);
1200         ret = mlx5_rxq_obj_verify(dev);
1201         if (ret)
1202                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1203                         dev->data->port_id);
1204         ret = mlx5_rxq_verify(dev);
1205         if (ret)
1206                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1207                         dev->data->port_id);
1208         ret = mlx5_txq_obj_verify(dev);
1209         if (ret)
1210                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1211                         dev->data->port_id);
1212         ret = mlx5_txq_verify(dev);
1213         if (ret)
1214                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1215                         dev->data->port_id);
1216         ret = mlx5_flow_verify(dev);
1217         if (ret)
1218                 DRV_LOG(WARNING, "port %u some flows still remain",
1219                         dev->data->port_id);
1220         /*
1221          * Free the shared context in last turn, because the cleanup
1222          * routines above may use some shared fields, like
1223          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1224          * ifindex if Netlink fails.
1225          */
1226         mlx5_free_shared_dev_ctx(priv->sh);
1227         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1228                 unsigned int c = 0;
1229                 uint16_t port_id;
1230
1231                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1232                         struct mlx5_priv *opriv =
1233                                 rte_eth_devices[port_id].data->dev_private;
1234
1235                         if (!opriv ||
1236                             opriv->domain_id != priv->domain_id ||
1237                             &rte_eth_devices[port_id] == dev)
1238                                 continue;
1239                         ++c;
1240                         break;
1241                 }
1242                 if (!c)
1243                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1244         }
1245         memset(priv, 0, sizeof(*priv));
1246         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1247         /*
1248          * Reset mac_addrs to NULL such that it is not freed as part of
1249          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1250          * it is freed when dev_private is freed.
1251          */
1252         dev->data->mac_addrs = NULL;
1253 }
1254
1255 /**
1256  * Verify and store value for device argument.
1257  *
1258  * @param[in] key
1259  *   Key argument to verify.
1260  * @param[in] val
1261  *   Value associated with key.
1262  * @param opaque
1263  *   User data.
1264  *
1265  * @return
1266  *   0 on success, a negative errno value otherwise and rte_errno is set.
1267  */
1268 static int
1269 mlx5_args_check(const char *key, const char *val, void *opaque)
1270 {
1271         struct mlx5_dev_config *config = opaque;
1272         unsigned long tmp;
1273
1274         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1275         if (!strcmp(MLX5_REPRESENTOR, key))
1276                 return 0;
1277         errno = 0;
1278         tmp = strtoul(val, NULL, 0);
1279         if (errno) {
1280                 rte_errno = errno;
1281                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1282                 return -rte_errno;
1283         }
1284         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1285                 config->cqe_comp = !!tmp;
1286         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1287                 config->cqe_pad = !!tmp;
1288         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1289                 config->hw_padding = !!tmp;
1290         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1291                 config->mprq.enabled = !!tmp;
1292         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1293                 config->mprq.stride_num_n = tmp;
1294         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1295                 config->mprq.stride_size_n = tmp;
1296         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1297                 config->mprq.max_memcpy_len = tmp;
1298         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1299                 config->mprq.min_rxqs_num = tmp;
1300         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1301                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1302                                  " converted to txq_inline_max", key);
1303                 config->txq_inline_max = tmp;
1304         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1305                 config->txq_inline_max = tmp;
1306         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1307                 config->txq_inline_min = tmp;
1308         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1309                 config->txq_inline_mpw = tmp;
1310         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1311                 config->txqs_inline = tmp;
1312         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1313                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1314         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1315                 config->mps = !!tmp;
1316         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1317                 if (tmp != MLX5_TXDB_CACHED &&
1318                     tmp != MLX5_TXDB_NCACHED &&
1319                     tmp != MLX5_TXDB_HEURISTIC) {
1320                         DRV_LOG(ERR, "invalid Tx doorbell "
1321                                      "mapping parameter");
1322                         rte_errno = EINVAL;
1323                         return -rte_errno;
1324                 }
1325                 config->dbnc = tmp;
1326         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1327                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1328         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1329                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1330                                  " converted to txq_inline_mpw", key);
1331                 config->txq_inline_mpw = tmp;
1332         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1333                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1334         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1335                 config->rx_vec_en = !!tmp;
1336         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1337                 config->l3_vxlan_en = !!tmp;
1338         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1339                 config->vf_nl_en = !!tmp;
1340         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1341                 config->dv_esw_en = !!tmp;
1342         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1343                 config->dv_flow_en = !!tmp;
1344         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1345                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1346                     tmp != MLX5_XMETA_MODE_META16 &&
1347                     tmp != MLX5_XMETA_MODE_META32) {
1348                         DRV_LOG(ERR, "invalid extensive "
1349                                      "metadata parameter");
1350                         rte_errno = EINVAL;
1351                         return -rte_errno;
1352                 }
1353                 config->dv_xmeta_en = tmp;
1354         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1355                 config->mr_ext_memseg_en = !!tmp;
1356         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1357                 config->max_dump_files_num = tmp;
1358         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1359                 config->lro.timeout = tmp;
1360         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1361                 DRV_LOG(DEBUG, "class argument is %s.", val);
1362         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1363                 config->log_hp_size = tmp;
1364         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1365                 if (tmp != MLX5_RCM_NONE &&
1366                     tmp != MLX5_RCM_LIGHT &&
1367                     tmp != MLX5_RCM_AGGR) {
1368                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1369                         rte_errno = EINVAL;
1370                         return -rte_errno;
1371                 }
1372                 config->reclaim_mode = tmp;
1373         } else {
1374                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1375                 rte_errno = EINVAL;
1376                 return -rte_errno;
1377         }
1378         return 0;
1379 }
1380
1381 /**
1382  * Parse device parameters.
1383  *
1384  * @param config
1385  *   Pointer to device configuration structure.
1386  * @param devargs
1387  *   Device arguments structure.
1388  *
1389  * @return
1390  *   0 on success, a negative errno value otherwise and rte_errno is set.
1391  */
1392 int
1393 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1394 {
1395         const char **params = (const char *[]){
1396                 MLX5_RXQ_CQE_COMP_EN,
1397                 MLX5_RXQ_CQE_PAD_EN,
1398                 MLX5_RXQ_PKT_PAD_EN,
1399                 MLX5_RX_MPRQ_EN,
1400                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1401                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1402                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1403                 MLX5_RXQS_MIN_MPRQ,
1404                 MLX5_TXQ_INLINE,
1405                 MLX5_TXQ_INLINE_MIN,
1406                 MLX5_TXQ_INLINE_MAX,
1407                 MLX5_TXQ_INLINE_MPW,
1408                 MLX5_TXQS_MIN_INLINE,
1409                 MLX5_TXQS_MAX_VEC,
1410                 MLX5_TXQ_MPW_EN,
1411                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1412                 MLX5_TXQ_MAX_INLINE_LEN,
1413                 MLX5_TX_DB_NC,
1414                 MLX5_TX_VEC_EN,
1415                 MLX5_RX_VEC_EN,
1416                 MLX5_L3_VXLAN_EN,
1417                 MLX5_VF_NL_EN,
1418                 MLX5_DV_ESW_EN,
1419                 MLX5_DV_FLOW_EN,
1420                 MLX5_DV_XMETA_EN,
1421                 MLX5_MR_EXT_MEMSEG_EN,
1422                 MLX5_REPRESENTOR,
1423                 MLX5_MAX_DUMP_FILES_NUM,
1424                 MLX5_LRO_TIMEOUT_USEC,
1425                 MLX5_CLASS_ARG_NAME,
1426                 MLX5_HP_BUF_SIZE,
1427                 MLX5_RECLAIM_MEM,
1428                 NULL,
1429         };
1430         struct rte_kvargs *kvlist;
1431         int ret = 0;
1432         int i;
1433
1434         if (devargs == NULL)
1435                 return 0;
1436         /* Following UGLY cast is done to pass checkpatch. */
1437         kvlist = rte_kvargs_parse(devargs->args, params);
1438         if (kvlist == NULL) {
1439                 rte_errno = EINVAL;
1440                 return -rte_errno;
1441         }
1442         /* Process parameters. */
1443         for (i = 0; (params[i] != NULL); ++i) {
1444                 if (rte_kvargs_count(kvlist, params[i])) {
1445                         ret = rte_kvargs_process(kvlist, params[i],
1446                                                  mlx5_args_check, config);
1447                         if (ret) {
1448                                 rte_errno = EINVAL;
1449                                 rte_kvargs_free(kvlist);
1450                                 return -rte_errno;
1451                         }
1452                 }
1453         }
1454         rte_kvargs_free(kvlist);
1455         return 0;
1456 }
1457
1458 /**
1459  * PMD global initialization.
1460  *
1461  * Independent from individual device, this function initializes global
1462  * per-PMD data structures distinguishing primary and secondary processes.
1463  * Hence, each initialization is called once per a process.
1464  *
1465  * @return
1466  *   0 on success, a negative errno value otherwise and rte_errno is set.
1467  */
1468 int
1469 mlx5_init_once(void)
1470 {
1471         struct mlx5_shared_data *sd;
1472         struct mlx5_local_data *ld = &mlx5_local_data;
1473         int ret = 0;
1474
1475         if (mlx5_init_shared_data())
1476                 return -rte_errno;
1477         sd = mlx5_shared_data;
1478         MLX5_ASSERT(sd);
1479         rte_spinlock_lock(&sd->lock);
1480         switch (rte_eal_process_type()) {
1481         case RTE_PROC_PRIMARY:
1482                 if (sd->init_done)
1483                         break;
1484                 LIST_INIT(&sd->mem_event_cb_list);
1485                 rte_rwlock_init(&sd->mem_event_rwlock);
1486                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1487                                                 mlx5_mr_mem_event_cb, NULL);
1488                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1489                                            mlx5_mp_primary_handle);
1490                 if (ret)
1491                         goto out;
1492                 sd->init_done = true;
1493                 break;
1494         case RTE_PROC_SECONDARY:
1495                 if (ld->init_done)
1496                         break;
1497                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1498                                              mlx5_mp_secondary_handle);
1499                 if (ret)
1500                         goto out;
1501                 ++sd->secondary_cnt;
1502                 ld->init_done = true;
1503                 break;
1504         default:
1505                 break;
1506         }
1507 out:
1508         rte_spinlock_unlock(&sd->lock);
1509         return ret;
1510 }
1511
1512 /**
1513  * Configures the minimal amount of data to inline into WQE
1514  * while sending packets.
1515  *
1516  * - the txq_inline_min has the maximal priority, if this
1517  *   key is specified in devargs
1518  * - if DevX is enabled the inline mode is queried from the
1519  *   device (HCA attributes and NIC vport context if needed).
1520  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1521  *   and none (0 bytes) for other NICs
1522  *
1523  * @param spawn
1524  *   Verbs device parameters (name, port, switch_info) to spawn.
1525  * @param config
1526  *   Device configuration parameters.
1527  */
1528 void
1529 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1530                     struct mlx5_dev_config *config)
1531 {
1532         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1533                 /* Application defines size of inlined data explicitly. */
1534                 switch (spawn->pci_dev->id.device_id) {
1535                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1536                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1537                         if (config->txq_inline_min <
1538                                        (int)MLX5_INLINE_HSIZE_L2) {
1539                                 DRV_LOG(DEBUG,
1540                                         "txq_inline_mix aligned to minimal"
1541                                         " ConnectX-4 required value %d",
1542                                         (int)MLX5_INLINE_HSIZE_L2);
1543                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1544                         }
1545                         break;
1546                 }
1547                 goto exit;
1548         }
1549         if (config->hca_attr.eth_net_offloads) {
1550                 /* We have DevX enabled, inline mode queried successfully. */
1551                 switch (config->hca_attr.wqe_inline_mode) {
1552                 case MLX5_CAP_INLINE_MODE_L2:
1553                         /* outer L2 header must be inlined. */
1554                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1555                         goto exit;
1556                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1557                         /* No inline data are required by NIC. */
1558                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1559                         config->hw_vlan_insert =
1560                                 config->hca_attr.wqe_vlan_insert;
1561                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1562                         goto exit;
1563                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1564                         /* inline mode is defined by NIC vport context. */
1565                         if (!config->hca_attr.eth_virt)
1566                                 break;
1567                         switch (config->hca_attr.vport_inline_mode) {
1568                         case MLX5_INLINE_MODE_NONE:
1569                                 config->txq_inline_min =
1570                                         MLX5_INLINE_HSIZE_NONE;
1571                                 goto exit;
1572                         case MLX5_INLINE_MODE_L2:
1573                                 config->txq_inline_min =
1574                                         MLX5_INLINE_HSIZE_L2;
1575                                 goto exit;
1576                         case MLX5_INLINE_MODE_IP:
1577                                 config->txq_inline_min =
1578                                         MLX5_INLINE_HSIZE_L3;
1579                                 goto exit;
1580                         case MLX5_INLINE_MODE_TCP_UDP:
1581                                 config->txq_inline_min =
1582                                         MLX5_INLINE_HSIZE_L4;
1583                                 goto exit;
1584                         case MLX5_INLINE_MODE_INNER_L2:
1585                                 config->txq_inline_min =
1586                                         MLX5_INLINE_HSIZE_INNER_L2;
1587                                 goto exit;
1588                         case MLX5_INLINE_MODE_INNER_IP:
1589                                 config->txq_inline_min =
1590                                         MLX5_INLINE_HSIZE_INNER_L3;
1591                                 goto exit;
1592                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1593                                 config->txq_inline_min =
1594                                         MLX5_INLINE_HSIZE_INNER_L4;
1595                                 goto exit;
1596                         }
1597                 }
1598         }
1599         /*
1600          * We get here if we are unable to deduce
1601          * inline data size with DevX. Try PCI ID
1602          * to determine old NICs.
1603          */
1604         switch (spawn->pci_dev->id.device_id) {
1605         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1606         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1607         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1608         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1609                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1610                 config->hw_vlan_insert = 0;
1611                 break;
1612         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1613         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1614         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1615         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1616                 /*
1617                  * These NICs support VLAN insertion from WQE and
1618                  * report the wqe_vlan_insert flag. But there is the bug
1619                  * and PFC control may be broken, so disable feature.
1620                  */
1621                 config->hw_vlan_insert = 0;
1622                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1623                 break;
1624         default:
1625                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1626                 break;
1627         }
1628 exit:
1629         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1630 }
1631
1632 /**
1633  * Configures the metadata mask fields in the shared context.
1634  *
1635  * @param [in] dev
1636  *   Pointer to Ethernet device.
1637  */
1638 void
1639 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1640 {
1641         struct mlx5_priv *priv = dev->data->dev_private;
1642         struct mlx5_dev_ctx_shared *sh = priv->sh;
1643         uint32_t meta, mark, reg_c0;
1644
1645         reg_c0 = ~priv->vport_meta_mask;
1646         switch (priv->config.dv_xmeta_en) {
1647         case MLX5_XMETA_MODE_LEGACY:
1648                 meta = UINT32_MAX;
1649                 mark = MLX5_FLOW_MARK_MASK;
1650                 break;
1651         case MLX5_XMETA_MODE_META16:
1652                 meta = reg_c0 >> rte_bsf32(reg_c0);
1653                 mark = MLX5_FLOW_MARK_MASK;
1654                 break;
1655         case MLX5_XMETA_MODE_META32:
1656                 meta = UINT32_MAX;
1657                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1658                 break;
1659         default:
1660                 meta = 0;
1661                 mark = 0;
1662                 MLX5_ASSERT(false);
1663                 break;
1664         }
1665         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1666                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1667                                  sh->dv_mark_mask, mark);
1668         else
1669                 sh->dv_mark_mask = mark;
1670         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1671                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1672                                  sh->dv_meta_mask, meta);
1673         else
1674                 sh->dv_meta_mask = meta;
1675         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1676                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1677                                  sh->dv_meta_mask, reg_c0);
1678         else
1679                 sh->dv_regc0_mask = reg_c0;
1680         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1681         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1682         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1683         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1684 }
1685
1686 /**
1687  * Allocate page of door-bells and register it using DevX API.
1688  *
1689  * @param [in] dev
1690  *   Pointer to Ethernet device.
1691  *
1692  * @return
1693  *   Pointer to new page on success, NULL otherwise.
1694  */
1695 static struct mlx5_devx_dbr_page *
1696 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1697 {
1698         struct mlx5_priv *priv = dev->data->dev_private;
1699         struct mlx5_devx_dbr_page *page;
1700
1701         /* Allocate space for door-bell page and management data. */
1702         page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1703                                  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1704         if (!page) {
1705                 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1706                         dev->data->port_id);
1707                 return NULL;
1708         }
1709         /* Register allocated memory. */
1710         page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1711                                               MLX5_DBR_PAGE_SIZE, 0);
1712         if (!page->umem) {
1713                 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1714                         dev->data->port_id);
1715                 rte_free(page);
1716                 return NULL;
1717         }
1718         return page;
1719 }
1720
1721 /**
1722  * Find the next available door-bell, allocate new page if needed.
1723  *
1724  * @param [in] dev
1725  *   Pointer to Ethernet device.
1726  * @param [out] dbr_page
1727  *   Door-bell page containing the page data.
1728  *
1729  * @return
1730  *   Door-bell address offset on success, a negative error value otherwise.
1731  */
1732 int64_t
1733 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1734 {
1735         struct mlx5_priv *priv = dev->data->dev_private;
1736         struct mlx5_devx_dbr_page *page = NULL;
1737         uint32_t i, j;
1738
1739         LIST_FOREACH(page, &priv->dbrpgs, next)
1740                 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1741                         break;
1742         if (!page) { /* No page with free door-bell exists. */
1743                 page = mlx5_alloc_dbr_page(dev);
1744                 if (!page) /* Failed to allocate new page. */
1745                         return (-1);
1746                 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1747         }
1748         /* Loop to find bitmap part with clear bit. */
1749         for (i = 0;
1750              i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1751              i++)
1752                 ; /* Empty. */
1753         /* Find the first clear bit. */
1754         MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE);
1755         j = rte_bsf64(~page->dbr_bitmap[i]);
1756         page->dbr_bitmap[i] |= (UINT64_C(1) << j);
1757         page->dbr_count++;
1758         *dbr_page = page;
1759         return (((i * 64) + j) * sizeof(uint64_t));
1760 }
1761
1762 /**
1763  * Release a door-bell record.
1764  *
1765  * @param [in] dev
1766  *   Pointer to Ethernet device.
1767  * @param [in] umem_id
1768  *   UMEM ID of page containing the door-bell record to release.
1769  * @param [in] offset
1770  *   Offset of door-bell record in page.
1771  *
1772  * @return
1773  *   0 on success, a negative error value otherwise.
1774  */
1775 int32_t
1776 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1777 {
1778         struct mlx5_priv *priv = dev->data->dev_private;
1779         struct mlx5_devx_dbr_page *page = NULL;
1780         int ret = 0;
1781
1782         LIST_FOREACH(page, &priv->dbrpgs, next)
1783                 /* Find the page this address belongs to. */
1784                 if (mlx5_os_get_umem_id(page->umem) == umem_id)
1785                         break;
1786         if (!page)
1787                 return -EINVAL;
1788         page->dbr_count--;
1789         if (!page->dbr_count) {
1790                 /* Page not used, free it and remove from list. */
1791                 LIST_REMOVE(page, next);
1792                 if (page->umem)
1793                         ret = -mlx5_glue->devx_umem_dereg(page->umem);
1794                 rte_free(page);
1795         } else {
1796                 /* Mark in bitmap that this door-bell is not in use. */
1797                 offset /= MLX5_DBR_SIZE;
1798                 int i = offset / 64;
1799                 int j = offset % 64;
1800
1801                 page->dbr_bitmap[i] &= ~(UINT64_C(1) << j);
1802         }
1803         return ret;
1804 }
1805
1806 int
1807 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1808 {
1809         static const char *const dynf_names[] = {
1810                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1811                 RTE_MBUF_DYNFLAG_METADATA_NAME
1812         };
1813         unsigned int i;
1814
1815         if (n < RTE_DIM(dynf_names))
1816                 return -ENOMEM;
1817         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1818                 if (names[i] == NULL)
1819                         return -EINVAL;
1820                 strcpy(names[i], dynf_names[i]);
1821         }
1822         return RTE_DIM(dynf_names);
1823 }
1824
1825 /**
1826  * Comparison callback to sort device data.
1827  *
1828  * This is meant to be used with qsort().
1829  *
1830  * @param a[in]
1831  *   Pointer to pointer to first data object.
1832  * @param b[in]
1833  *   Pointer to pointer to second data object.
1834  *
1835  * @return
1836  *   0 if both objects are equal, less than 0 if the first argument is less
1837  *   than the second, greater than 0 otherwise.
1838  */
1839 int
1840 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1841                               struct mlx5_dev_config *config)
1842 {
1843         struct mlx5_dev_ctx_shared *sh = priv->sh;
1844         struct mlx5_dev_config *sh_conf = NULL;
1845         uint16_t port_id;
1846
1847         MLX5_ASSERT(sh);
1848         /* Nothing to compare for the single/first device. */
1849         if (sh->refcnt == 1)
1850                 return 0;
1851         /* Find the device with shared context. */
1852         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1853                 struct mlx5_priv *opriv =
1854                         rte_eth_devices[port_id].data->dev_private;
1855
1856                 if (opriv && opriv != priv && opriv->sh == sh) {
1857                         sh_conf = &opriv->config;
1858                         break;
1859                 }
1860         }
1861         if (!sh_conf)
1862                 return 0;
1863         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1864                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1865                              " for shared %s context", sh->ibdev_name);
1866                 rte_errno = EINVAL;
1867                 return rte_errno;
1868         }
1869         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1870                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1871                              " for shared %s context", sh->ibdev_name);
1872                 rte_errno = EINVAL;
1873                 return rte_errno;
1874         }
1875         return 0;
1876 }
1877
1878 /**
1879  * Look for the ethernet device belonging to mlx5 driver.
1880  *
1881  * @param[in] port_id
1882  *   port_id to start looking for device.
1883  * @param[in] pci_dev
1884  *   Pointer to the hint PCI device. When device is being probed
1885  *   the its siblings (master and preceding representors might
1886  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1887  *   is not completed yet, for this case match on hint PCI
1888  *   device may be used to detect sibling device.
1889  *
1890  * @return
1891  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1892  */
1893 uint16_t
1894 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1895 {
1896         while (port_id < RTE_MAX_ETHPORTS) {
1897                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1898
1899                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1900                     dev->device &&
1901                     (dev->device == &pci_dev->device ||
1902                      (dev->device->driver &&
1903                      dev->device->driver->name &&
1904                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1905                         break;
1906                 port_id++;
1907         }
1908         if (port_id >= RTE_MAX_ETHPORTS)
1909                 return RTE_MAX_ETHPORTS;
1910         return port_id;
1911 }
1912
1913 /**
1914  * DPDK callback to remove a PCI device.
1915  *
1916  * This function removes all Ethernet devices belong to a given PCI device.
1917  *
1918  * @param[in] pci_dev
1919  *   Pointer to the PCI device.
1920  *
1921  * @return
1922  *   0 on success, the function cannot fail.
1923  */
1924 static int
1925 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1926 {
1927         uint16_t port_id;
1928
1929         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1930                 /*
1931                  * mlx5_dev_close() is not registered to secondary process,
1932                  * call the close function explicitly for secondary process.
1933                  */
1934                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1935                         mlx5_dev_close(&rte_eth_devices[port_id]);
1936                 else
1937                         rte_eth_dev_close(port_id);
1938         }
1939         return 0;
1940 }
1941
1942 static const struct rte_pci_id mlx5_pci_id_map[] = {
1943         {
1944                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1946         },
1947         {
1948                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1949                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1950         },
1951         {
1952                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1953                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1954         },
1955         {
1956                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1957                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1958         },
1959         {
1960                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1961                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1962         },
1963         {
1964                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1965                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1966         },
1967         {
1968                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1969                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1970         },
1971         {
1972                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1973                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1974         },
1975         {
1976                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1977                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1978         },
1979         {
1980                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1981                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1982         },
1983         {
1984                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1985                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1986         },
1987         {
1988                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1989                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1990         },
1991         {
1992                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1993                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1994         },
1995         {
1996                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1997                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1998         },
1999         {
2000                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2001                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2002         },
2003         {
2004                 .vendor_id = 0
2005         }
2006 };
2007
2008 struct rte_pci_driver mlx5_driver = {
2009         .driver = {
2010                 .name = MLX5_DRIVER_NAME
2011         },
2012         .id_table = mlx5_pci_id_map,
2013         .probe = mlx5_os_pci_probe,
2014         .remove = mlx5_pci_remove,
2015         .dma_map = mlx5_dma_map,
2016         .dma_unmap = mlx5_dma_unmap,
2017         .drv_flags = PCI_DRV_FLAGS,
2018 };
2019
2020 /**
2021  * Driver initialization routine.
2022  */
2023 RTE_INIT(rte_mlx5_pmd_init)
2024 {
2025         /* Initialize driver log type. */
2026         mlx5_logtype = rte_log_register("pmd.net.mlx5");
2027         if (mlx5_logtype >= 0)
2028                 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
2029
2030         /* Build the static tables for Verbs conversion. */
2031         mlx5_set_ptype_table();
2032         mlx5_set_cksum_table();
2033         mlx5_set_swp_types_table();
2034         if (mlx5_glue)
2035                 rte_pci_register(&mlx5_driver);
2036 }
2037
2038 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2039 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2040 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");