drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_legacy_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355         [MLX5_IPOOL_MTR_POLICY] = {
 356                 /**
 357                  * The ipool index should grow continually from small to big,
 358                  * for policy idx, so not set grow_trunk to avoid policy index
 359                  * not jump continually.
 360                  */
 361                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 362                 .trunk_size = 64,
 363                 .need_lock = 1,
 364                 .release_mem_en = 1,
 365                 .malloc = mlx5_malloc,
 366                 .free = mlx5_free,
 367                 .type = "mlx5_meter_policy_ipool",
 368         },
 369 };
 370
 371
 372 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 373 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 374
 375 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 376
 377 /**
 378  * Decide whether representor ID is a HPF(host PF) port on BF2.
 379  *
 380  * @param dev
 381  *   Pointer to Ethernet device structure.
 382  *
 383  * @return
 384  *   Non-zero if HPF, otherwise 0.
 385  */
 386 bool
 387 mlx5_is_hpf(struct rte_eth_dev *dev)
 388 {
 389         struct mlx5_priv *priv = dev->data->dev_private;
 390         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 391         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 392
 393         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 394                MLX5_REPRESENTOR_REPR(-1) == repr;
 395 }
 396
 397 /**
 398  * Initialize the ASO aging management structure.
 399  *
 400  * @param[in] sh
 401  *   Pointer to mlx5_dev_ctx_shared object to free
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 int
 407 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 408 {
 409         int err;
 410
 411         if (sh->aso_age_mng)
 412                 return 0;
 413         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 414                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 415         if (!sh->aso_age_mng) {
 416                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 417                 rte_errno = ENOMEM;
 418                 return -ENOMEM;
 419         }
 420         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 421         if (err) {
 422                 mlx5_free(sh->aso_age_mng);
 423                 return -1;
 424         }
 425         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 426         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 427         LIST_INIT(&sh->aso_age_mng->free);
 428         return 0;
 429 }
 430
 431 /**
 432  * Close and release all the resources of the ASO aging management structure.
 433  *
 434  * @param[in] sh
 435  *   Pointer to mlx5_dev_ctx_shared object to free.
 436  */
 437 static void
 438 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 439 {
 440         int i, j;
 441
 442         mlx5_aso_flow_hit_queue_poll_stop(sh);
 443         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 444         if (sh->aso_age_mng->pools) {
 445                 struct mlx5_aso_age_pool *pool;
 446
 447                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 448                         pool = sh->aso_age_mng->pools[i];
 449                         claim_zero(mlx5_devx_cmd_destroy
 450                                                 (pool->flow_hit_aso_obj));
 451                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 452                                 if (pool->actions[j].dr_action)
 453                                         claim_zero
 454                                             (mlx5_flow_os_destroy_flow_action
 455                                               (pool->actions[j].dr_action));
 456                         mlx5_free(pool);
 457                 }
 458                 mlx5_free(sh->aso_age_mng->pools);
 459         }
 460         mlx5_free(sh->aso_age_mng);
 461 }
 462
 463 /**
 464  * Initialize the shared aging list information per port.
 465  *
 466  * @param[in] sh
 467  *   Pointer to mlx5_dev_ctx_shared object.
 468  */
 469 static void
 470 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 471 {
 472         uint32_t i;
 473         struct mlx5_age_info *age_info;
 474
 475         for (i = 0; i < sh->max_port; i++) {
 476                 age_info = &sh->port[i].age_info;
 477                 age_info->flags = 0;
 478                 TAILQ_INIT(&age_info->aged_counters);
 479                 LIST_INIT(&age_info->aged_aso);
 480                 rte_spinlock_init(&age_info->aged_sl);
 481                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 482         }
 483 }
 484
 485 /**
 486  * Initialize the counters management structure.
 487  *
 488  * @param[in] sh
 489  *   Pointer to mlx5_dev_ctx_shared object to free
 490  */
 491 static void
 492 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 493 {
 494         int i;
 495
 496         memset(&sh->cmng, 0, sizeof(sh->cmng));
 497         TAILQ_INIT(&sh->cmng.flow_counters);
 498         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 499         sh->cmng.max_id = -1;
 500         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 501         rte_spinlock_init(&sh->cmng.pool_update_sl);
 502         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 503                 TAILQ_INIT(&sh->cmng.counters[i]);
 504                 rte_spinlock_init(&sh->cmng.csl[i]);
 505         }
 506 }
 507
 508 /**
 509  * Destroy all the resources allocated for a counter memory management.
 510  *
 511  * @param[in] mng
 512  *   Pointer to the memory management structure.
 513  */
 514 static void
 515 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 516 {
 517         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 518
 519         LIST_REMOVE(mng, next);
 520         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 521         claim_zero(mlx5_os_umem_dereg(mng->umem));
 522         mlx5_free(mem);
 523 }
 524
 525 /**
 526  * Close and release all the resources of the counters management.
 527  *
 528  * @param[in] sh
 529  *   Pointer to mlx5_dev_ctx_shared object to free.
 530  */
 531 static void
 532 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 533 {
 534         struct mlx5_counter_stats_mem_mng *mng;
 535         int i, j;
 536         int retries = 1024;
 537
 538         rte_errno = 0;
 539         while (--retries) {
 540                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 541                 if (rte_errno != EINPROGRESS)
 542                         break;
 543                 rte_pause();
 544         }
 545
 546         if (sh->cmng.pools) {
 547                 struct mlx5_flow_counter_pool *pool;
 548                 uint16_t n_valid = sh->cmng.n_valid;
 549                 bool fallback = sh->cmng.counter_fallback;
 550
 551                 for (i = 0; i < n_valid; ++i) {
 552                         pool = sh->cmng.pools[i];
 553                         if (!fallback && pool->min_dcs)
 554                                 claim_zero(mlx5_devx_cmd_destroy
 555                                                                (pool->min_dcs));
 556                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 557                                 struct mlx5_flow_counter *cnt =
 558                                                 MLX5_POOL_GET_CNT(pool, j);
 559
 560                                 if (cnt->action)
 561                                         claim_zero
 562                                          (mlx5_flow_os_destroy_flow_action
 563                                           (cnt->action));
 564                                 if (fallback && MLX5_POOL_GET_CNT
 565                                     (pool, j)->dcs_when_free)
 566                                         claim_zero(mlx5_devx_cmd_destroy
 567                                                    (cnt->dcs_when_free));
 568                         }
 569                         mlx5_free(pool);
 570                 }
 571                 mlx5_free(sh->cmng.pools);
 572         }
 573         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 574         while (mng) {
 575                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 576                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 577         }
 578         memset(&sh->cmng, 0, sizeof(sh->cmng));
 579 }
 580
 581 /**
 582  * Initialize the aso flow meters management structure.
 583  *
 584  * @param[in] sh
 585  *   Pointer to mlx5_dev_ctx_shared object to free
 586  */
 587 int
 588 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 589 {
 590         if (!sh->mtrmng) {
 591                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 592                         sizeof(*sh->mtrmng),
 593                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 594                 if (!sh->mtrmng) {
 595                         DRV_LOG(ERR,
 596                         "meter management allocation was failed.");
 597                         rte_errno = ENOMEM;
 598                         return -ENOMEM;
 599                 }
 600                 if (sh->meter_aso_en) {
 601                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 602                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 603                         sh->mtrmng->policy_idx_tbl =
 604                                 mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 605                 }
 606                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 607         }
 608         return 0;
 609 }
 610
 611 /**
 612  * Close and release all the resources of
 613  * the ASO flow meter management structure.
 614  *
 615  * @param[in] sh
 616  *   Pointer to mlx5_dev_ctx_shared object to free.
 617  */
 618 static void
 619 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 620 {
 621         struct mlx5_aso_mtr_pool *mtr_pool;
 622         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 623         uint32_t idx;
 624 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 625         struct mlx5_aso_mtr *aso_mtr;
 626         int i;
 627 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 628
 629         if (sh->meter_aso_en) {
 630                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 631                 idx = mtrmng->pools_mng.n_valid;
 632                 while (idx--) {
 633                         mtr_pool = mtrmng->pools_mng.pools[idx];
 634 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 635                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 636                                 aso_mtr = &mtr_pool->mtrs[i];
 637                                 if (aso_mtr->fm.meter_action)
 638                                         claim_zero
 639                                         (mlx5_glue->destroy_flow_action
 640                                         (aso_mtr->fm.meter_action));
 641                         }
 642 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 643                         claim_zero(mlx5_devx_cmd_destroy
 644                                                 (mtr_pool->devx_obj));
 645                         mtrmng->pools_mng.n_valid--;
 646                         mlx5_free(mtr_pool);
 647                 }
 648                 mlx5_free(sh->mtrmng->pools_mng.pools);
 649         }
 650         mlx5_free(sh->mtrmng);
 651         sh->mtrmng = NULL;
 652 }
 653
 654 /* Send FLOW_AGED event if needed. */
 655 void
 656 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 657 {
 658         struct mlx5_age_info *age_info;
 659         uint32_t i;
 660
 661         for (i = 0; i < sh->max_port; i++) {
 662                 age_info = &sh->port[i].age_info;
 663                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 664                         continue;
 665                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER))
 666                         rte_eth_dev_callback_process
 667                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 668                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 669                 age_info->flags = 0;
 670         }
 671 }
 672
 673 /**
 674  * Initialize the flow resources' indexed mempool.
 675  *
 676  * @param[in] sh
 677  *   Pointer to mlx5_dev_ctx_shared object.
 678  * @param[in] sh
 679  *   Pointer to user dev config.
 680  */
 681 static void
 682 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 683                        const struct mlx5_dev_config *config)
 684 {
 685         uint8_t i;
 686         struct mlx5_indexed_pool_config cfg;
 687
 688         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 689                 cfg = mlx5_ipool_cfg[i];
 690                 switch (i) {
 691                 default:
 692                         break;
 693                 /*
 694                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 695                  * according to PCI function flow configuration.
 696                  */
 697                 case MLX5_IPOOL_MLX5_FLOW:
 698                         cfg.size = config->dv_flow_en ?
 699                                 sizeof(struct mlx5_flow_handle) :
 700                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 701                         break;
 702                 }
 703                 if (config->reclaim_mode)
 704                         cfg.release_mem_en = 1;
 705                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 706         }
 707 }
 708
 709 /**
 710  * Release the flow resources' indexed mempool.
 711  *
 712  * @param[in] sh
 713  *   Pointer to mlx5_dev_ctx_shared object.
 714  */
 715 static void
 716 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 717 {
 718         uint8_t i;
 719
 720         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 721                 mlx5_ipool_destroy(sh->ipool[i]);
 722 }
 723
 724 /*
 725  * Check if dynamic flex parser for eCPRI already exists.
 726  *
 727  * @param dev
 728  *   Pointer to Ethernet device structure.
 729  *
 730  * @return
 731  *   true on exists, false on not.
 732  */
 733 bool
 734 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 735 {
 736         struct mlx5_priv *priv = dev->data->dev_private;
 737         struct mlx5_flex_parser_profiles *prf =
 738                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 739
 740         return !!prf->obj;
 741 }
 742
 743 /*
 744  * Allocation of a flex parser for eCPRI. Once created, this parser related
 745  * resources will be held until the device is closed.
 746  *
 747  * @param dev
 748  *   Pointer to Ethernet device structure.
 749  *
 750  * @return
 751  *   0 on success, a negative errno value otherwise and rte_errno is set.
 752  */
 753 int
 754 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 755 {
 756         struct mlx5_priv *priv = dev->data->dev_private;
 757         struct mlx5_flex_parser_profiles *prf =
 758                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 759         struct mlx5_devx_graph_node_attr node = {
 760                 .modify_field_select = 0,
 761         };
 762         uint32_t ids[8];
 763         int ret;
 764
 765         if (!priv->config.hca_attr.parse_graph_flex_node) {
 766                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 767                         "for device %s.", priv->dev_data->name);
 768                 return -ENOTSUP;
 769         }
 770         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 771         /* 8 bytes now: 4B common header + 4B message body header. */
 772         node.header_length_base_value = 0x8;
 773         /* After MAC layer: Ether / VLAN. */
 774         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 775         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 776         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 777         /* Sample #0: type in common header. */
 778         node.sample[0].flow_match_sample_en = 1;
 779         /* Fixed offset. */
 780         node.sample[0].flow_match_sample_offset_mode = 0x0;
 781         /* Only the 2nd byte will be used. */
 782         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 783         /* Sample #1: message payload. */
 784         node.sample[1].flow_match_sample_en = 1;
 785         /* Fixed offset. */
 786         node.sample[1].flow_match_sample_offset_mode = 0x0;
 787         /*
 788          * Only the first two bytes will be used right now, and its offset will
 789          * start after the common header that with the length of a DW(u32).
 790          */
 791         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 792         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 793         if (!prf->obj) {
 794                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 795                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 796         }
 797         prf->num = 2;
 798         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 799         if (ret) {
 800                 DRV_LOG(ERR, "Failed to query sample IDs.");
 801                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 802         }
 803         prf->offset[0] = 0x0;
 804         prf->offset[1] = sizeof(uint32_t);
 805         prf->ids[0] = ids[0];
 806         prf->ids[1] = ids[1];
 807         return 0;
 808 }
 809
 810 /*
 811  * Destroy the flex parser node, including the parser itself, input / output
 812  * arcs and DW samples. Resources could be reused then.
 813  *
 814  * @param dev
 815  *   Pointer to Ethernet device structure.
 816  */
 817 static void
 818 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 819 {
 820         struct mlx5_priv *priv = dev->data->dev_private;
 821         struct mlx5_flex_parser_profiles *prf =
 822                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 823
 824         if (prf->obj)
 825                 mlx5_devx_cmd_destroy(prf->obj);
 826         prf->obj = NULL;
 827 }
 828
 829 /*
 830  * Allocate Rx and Tx UARs in robust fashion.
 831  * This routine handles the following UAR allocation issues:
 832  *
 833  *  - tries to allocate the UAR with the most appropriate memory
 834  *    mapping type from the ones supported by the host
 835  *
 836  *  - tries to allocate the UAR with non-NULL base address
 837  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 838  *    UAR base address if UAR was not the first object in the UAR page.
 839  *    It caused the PMD failure and we should try to get another UAR
 840  *    till we get the first one with non-NULL base address returned.
 841  */
 842 static int
 843 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 844                      const struct mlx5_dev_config *config)
 845 {
 846         uint32_t uar_mapping, retry;
 847         int err = 0;
 848         void *base_addr;
 849
 850         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 851 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 852                 /* Control the mapping type according to the settings. */
 853                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 854                               MLX5DV_UAR_ALLOC_TYPE_NC :
 855                               MLX5DV_UAR_ALLOC_TYPE_BF;
 856 #else
 857                 RTE_SET_USED(config);
 858                 /*
 859                  * It seems we have no way to control the memory mapping type
 860                  * for the UAR, the default "Write-Combining" type is supposed.
 861                  * The UAR initialization on queue creation queries the
 862                  * actual mapping type done by Verbs/kernel and setups the
 863                  * PMD datapath accordingly.
 864                  */
 865                 uar_mapping = 0;
 866 #endif
 867                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 868 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 869                 if (!sh->tx_uar &&
 870                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 871                         if (config->dbnc == MLX5_TXDB_CACHED ||
 872                             config->dbnc == MLX5_TXDB_HEURISTIC)
 873                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 874                                                  "is not supported by DevX");
 875                         /*
 876                          * In some environments like virtual machine
 877                          * the Write Combining mapped might be not supported
 878                          * and UAR allocation fails. We try "Non-Cached"
 879                          * mapping for the case. The tx_burst routines take
 880                          * the UAR mapping type into account on UAR setup
 881                          * on queue creation.
 882                          */
 883                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 884                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 885                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 886                                                         (sh->ctx, uar_mapping);
 887                 } else if (!sh->tx_uar &&
 888                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 889                         if (config->dbnc == MLX5_TXDB_NCACHED)
 890                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 891                                                  "is not supported by DevX");
 892                         /*
 893                          * If Verbs/kernel does not support "Non-Cached"
 894                          * try the "Write-Combining".
 895                          */
 896                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 897                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 898                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 899                                                         (sh->ctx, uar_mapping);
 900                 }
 901 #endif
 902                 if (!sh->tx_uar) {
 903                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 904                         err = ENOMEM;
 905                         goto exit;
 906                 }
 907                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
 908                 if (base_addr)
 909                         break;
 910                 /*
 911                  * The UARs are allocated by rdma_core within the
 912                  * IB device context, on context closure all UARs
 913                  * will be freed, should be no memory/object leakage.
 914                  */
 915                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
 916                 sh->tx_uar = NULL;
 917         }
 918         /* Check whether we finally succeeded with valid UAR allocation. */
 919         if (!sh->tx_uar) {
 920                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
 921                 err = ENOMEM;
 922                 goto exit;
 923         }
 924         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 925                 uar_mapping = 0;
 926                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 927                                                         (sh->ctx, uar_mapping);
 928 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 929                 if (!sh->devx_rx_uar &&
 930                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 931                         /*
 932                          * Rx UAR is used to control interrupts only,
 933                          * should be no datapath noticeable impact,
 934                          * can try "Non-Cached" mapping safely.
 935                          */
 936                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
 937                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 938                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
 939                                                         (sh->ctx, uar_mapping);
 940                 }
 941 #endif
 942                 if (!sh->devx_rx_uar) {
 943                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
 944                         err = ENOMEM;
 945                         goto exit;
 946                 }
 947                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
 948                 if (base_addr)
 949                         break;
 950                 /*
 951                  * The UARs are allocated by rdma_core within the
 952                  * IB device context, on context closure all UARs
 953                  * will be freed, should be no memory/object leakage.
 954                  */
 955                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
 956                 sh->devx_rx_uar = NULL;
 957         }
 958         /* Check whether we finally succeeded with valid UAR allocation. */
 959         if (!sh->devx_rx_uar) {
 960                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
 961                 err = ENOMEM;
 962         }
 963 exit:
 964         return err;
 965 }
 966
 967 /**
 968  * Allocate shared device context. If there is multiport device the
 969  * master and representors will share this context, if there is single
 970  * port dedicated device, the context will be used by only given
 971  * port due to unification.
 972  *
 973  * Routine first searches the context for the specified device name,
 974  * if found the shared context assumed and reference counter is incremented.
 975  * If no context found the new one is created and initialized with specified
 976  * device context and parameters.
 977  *
 978  * @param[in] spawn
 979  *   Pointer to the device attributes (name, port, etc).
 980  * @param[in] config
 981  *   Pointer to device configuration structure.
 982  *
 983  * @return
 984  *   Pointer to mlx5_dev_ctx_shared object on success,
 985  *   otherwise NULL and rte_errno is set.
 986  */
 987 struct mlx5_dev_ctx_shared *
 988 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 989                            const struct mlx5_dev_config *config)
 990 {
 991         struct mlx5_dev_ctx_shared *sh;
 992         int err = 0;
 993         uint32_t i;
 994         struct mlx5_devx_tis_attr tis_attr = { 0 };
 995
 996         MLX5_ASSERT(spawn);
 997         /* Secondary process should not create the shared context. */
 998         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 999         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1000         /* Search for IB context by device name. */
1001         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1002                 if (!strcmp(sh->ibdev_name,
1003                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1004                         sh->refcnt++;
1005                         goto exit;
1006                 }
1007         }
1008         /* No device found, we have to create new shared context. */
1009         MLX5_ASSERT(spawn->max_port);
1010         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1011                          sizeof(struct mlx5_dev_ctx_shared) +
1012                          spawn->max_port *
1013                          sizeof(struct mlx5_dev_shared_port),
1014                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1015         if (!sh) {
1016                 DRV_LOG(ERR, "shared context allocation failure");
1017                 rte_errno  = ENOMEM;
1018                 goto exit;
1019         }
1020         if (spawn->bond_info)
1021                 sh->bond = *spawn->bond_info;
1022         err = mlx5_os_open_device(spawn, config, sh);
1023         if (!sh->ctx)
1024                 goto error;
1025         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1026         if (err) {
1027                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1028                 goto error;
1029         }
1030         sh->refcnt = 1;
1031         sh->max_port = spawn->max_port;
1032         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1033                 sizeof(sh->ibdev_name) - 1);
1034         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1035                 sizeof(sh->ibdev_path) - 1);
1036         /*
1037          * Setting port_id to max unallowed value means
1038          * there is no interrupt subhandler installed for
1039          * the given port index i.
1040          */
1041         for (i = 0; i < sh->max_port; i++) {
1042                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1043                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1044         }
1045         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1046         if (sh->pd == NULL) {
1047                 DRV_LOG(ERR, "PD allocation failure");
1048                 err = ENOMEM;
1049                 goto error;
1050         }
1051         if (sh->devx) {
1052                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1053                 if (err) {
1054                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1055                         goto error;
1056                 }
1057                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1058                 if (!sh->td) {
1059                         DRV_LOG(ERR, "TD allocation failure");
1060                         err = ENOMEM;
1061                         goto error;
1062                 }
1063                 tis_attr.transport_domain = sh->td->id;
1064                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1065                 if (!sh->tis) {
1066                         DRV_LOG(ERR, "TIS allocation failure");
1067                         err = ENOMEM;
1068                         goto error;
1069                 }
1070                 err = mlx5_alloc_rxtx_uars(sh, config);
1071                 if (err)
1072                         goto error;
1073                 MLX5_ASSERT(sh->tx_uar);
1074                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1075
1076                 MLX5_ASSERT(sh->devx_rx_uar);
1077                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1078         }
1079 #ifndef RTE_ARCH_64
1080         /* Initialize UAR access locks for 32bit implementations. */
1081         rte_spinlock_init(&sh->uar_lock_cq);
1082         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1083                 rte_spinlock_init(&sh->uar_lock[i]);
1084 #endif
1085         /*
1086          * Once the device is added to the list of memory event
1087          * callback, its global MR cache table cannot be expanded
1088          * on the fly because of deadlock. If it overflows, lookup
1089          * should be done by searching MR list linearly, which is slow.
1090          *
1091          * At this point the device is not added to the memory
1092          * event list yet, context is just being created.
1093          */
1094         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1095                                  MLX5_MR_BTREE_CACHE_N * 2,
1096                                  spawn->pci_dev->device.numa_node);
1097         if (err) {
1098                 err = rte_errno;
1099                 goto error;
1100         }
1101         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1102                               &sh->share_cache.dereg_mr_cb);
1103         mlx5_os_dev_shared_handler_install(sh);
1104         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1105         if (!sh->cnt_id_tbl) {
1106                 err = rte_errno;
1107                 goto error;
1108         }
1109         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1110                 err = mlx5_flow_os_init_workspace_once();
1111                 if (err)
1112                         goto error;
1113         }
1114         mlx5_flow_aging_init(sh);
1115         mlx5_flow_counters_mng_init(sh);
1116         mlx5_flow_ipool_create(sh, config);
1117         /* Add device to memory callback list. */
1118         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1119         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1120                          sh, mem_event_cb);
1121         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1122         /* Add context to the global device list. */
1123         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1124         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1125 exit:
1126         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1127         return sh;
1128 error:
1129         pthread_mutex_destroy(&sh->txpp.mutex);
1130         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1131         MLX5_ASSERT(sh);
1132         if (sh->cnt_id_tbl)
1133                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1134         if (sh->tis)
1135                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1136         if (sh->td)
1137                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1138         if (sh->devx_rx_uar)
1139                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1140         if (sh->tx_uar)
1141                 mlx5_glue->devx_free_uar(sh->tx_uar);
1142         if (sh->pd)
1143                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1144         if (sh->ctx)
1145                 claim_zero(mlx5_glue->close_device(sh->ctx));
1146         mlx5_free(sh);
1147         MLX5_ASSERT(err > 0);
1148         rte_errno = err;
1149         return NULL;
1150 }
1151
1152 /**
1153  * Free shared IB device context. Decrement counter and if zero free
1154  * all allocated resources and close handles.
1155  *
1156  * @param[in] sh
1157  *   Pointer to mlx5_dev_ctx_shared object to free
1158  */
1159 void
1160 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1161 {
1162         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1163 #ifdef RTE_LIBRTE_MLX5_DEBUG
1164         /* Check the object presence in the list. */
1165         struct mlx5_dev_ctx_shared *lctx;
1166
1167         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1168                 if (lctx == sh)
1169                         break;
1170         MLX5_ASSERT(lctx);
1171         if (lctx != sh) {
1172                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1173                 goto exit;
1174         }
1175 #endif
1176         MLX5_ASSERT(sh);
1177         MLX5_ASSERT(sh->refcnt);
1178         /* Secondary process should not free the shared context. */
1179         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1180         if (--sh->refcnt)
1181                 goto exit;
1182         /* Remove from memory callback device list. */
1183         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1184         LIST_REMOVE(sh, mem_event_cb);
1185         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1186         /* Release created Memory Regions. */
1187         mlx5_mr_release_cache(&sh->share_cache);
1188         /* Remove context from the global device list. */
1189         LIST_REMOVE(sh, next);
1190         /* Release flow workspaces objects on the last device. */
1191         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1192                 mlx5_flow_os_release_workspace();
1193         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1194         /*
1195          *  Ensure there is no async event handler installed.
1196          *  Only primary process handles async device events.
1197          **/
1198         mlx5_flow_counters_mng_close(sh);
1199         if (sh->aso_age_mng) {
1200                 mlx5_flow_aso_age_mng_close(sh);
1201                 sh->aso_age_mng = NULL;
1202         }
1203         if (sh->mtrmng)
1204                 mlx5_aso_flow_mtrs_mng_close(sh);
1205         mlx5_flow_ipool_destroy(sh);
1206         mlx5_os_dev_shared_handler_uninstall(sh);
1207         if (sh->cnt_id_tbl) {
1208                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1209                 sh->cnt_id_tbl = NULL;
1210         }
1211         if (sh->tx_uar) {
1212                 mlx5_glue->devx_free_uar(sh->tx_uar);
1213                 sh->tx_uar = NULL;
1214         }
1215         if (sh->pd)
1216                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1217         if (sh->tis)
1218                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1219         if (sh->td)
1220                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1221         if (sh->devx_rx_uar)
1222                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1223         if (sh->ctx)
1224                 claim_zero(mlx5_glue->close_device(sh->ctx));
1225         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1226         pthread_mutex_destroy(&sh->txpp.mutex);
1227         mlx5_free(sh);
1228         return;
1229 exit:
1230         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1231 }
1232
1233 /**
1234  * Destroy table hash list.
1235  *
1236  * @param[in] priv
1237  *   Pointer to the private device data structure.
1238  */
1239 void
1240 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1241 {
1242         struct mlx5_dev_ctx_shared *sh = priv->sh;
1243
1244         if (!sh->flow_tbls)
1245                 return;
1246         mlx5_hlist_destroy(sh->flow_tbls);
1247 }
1248
1249 /**
1250  * Initialize flow table hash list and create the root tables entry
1251  * for each domain.
1252  *
1253  * @param[in] priv
1254  *   Pointer to the private device data structure.
1255  *
1256  * @return
1257  *   Zero on success, positive error code otherwise.
1258  */
1259 int
1260 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1261 {
1262         int err = 0;
1263         /* Tables are only used in DV and DR modes. */
1264 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1265         struct mlx5_dev_ctx_shared *sh = priv->sh;
1266         char s[MLX5_HLIST_NAMESIZE];
1267
1268         MLX5_ASSERT(sh);
1269         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1270         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1271                                           0, 0, flow_dv_tbl_create_cb,
1272                                           flow_dv_tbl_match_cb,
1273                                           flow_dv_tbl_remove_cb);
1274         if (!sh->flow_tbls) {
1275                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1276                 err = ENOMEM;
1277                 return err;
1278         }
1279         sh->flow_tbls->ctx = sh;
1280 #ifndef HAVE_MLX5DV_DR
1281         struct rte_flow_error error;
1282         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1283
1284         /*
1285          * In case we have not DR support, the zero tables should be created
1286          * because DV expect to see them even if they cannot be created by
1287          * RDMA-CORE.
1288          */
1289         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1290                 NULL, 0, 1, 0, &error) ||
1291             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1292                 NULL, 0, 1, 0, &error) ||
1293             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1294                 NULL, 0, 1, 0, &error)) {
1295                 err = ENOMEM;
1296                 goto error;
1297         }
1298         return err;
1299 error:
1300         mlx5_free_table_hash_list(priv);
1301 #endif /* HAVE_MLX5DV_DR */
1302 #endif
1303         return err;
1304 }
1305
1306 /**
1307  * Retrieve integer value from environment variable.
1308  *
1309  * @param[in] name
1310  *   Environment variable name.
1311  *
1312  * @return
1313  *   Integer value, 0 if the variable is not set.
1314  */
1315 int
1316 mlx5_getenv_int(const char *name)
1317 {
1318         const char *val = getenv(name);
1319
1320         if (val == NULL)
1321                 return 0;
1322         return atoi(val);
1323 }
1324
1325 /**
1326  * DPDK callback to add udp tunnel port
1327  *
1328  * @param[in] dev
1329  *   A pointer to eth_dev
1330  * @param[in] udp_tunnel
1331  *   A pointer to udp tunnel
1332  *
1333  * @return
1334  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1335  */
1336 int
1337 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1338                          struct rte_eth_udp_tunnel *udp_tunnel)
1339 {
1340         MLX5_ASSERT(udp_tunnel != NULL);
1341         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1342             udp_tunnel->udp_port == 4789)
1343                 return 0;
1344         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1345             udp_tunnel->udp_port == 4790)
1346                 return 0;
1347         return -ENOTSUP;
1348 }
1349
1350 /**
1351  * Initialize process private data structure.
1352  *
1353  * @param dev
1354  *   Pointer to Ethernet device structure.
1355  *
1356  * @return
1357  *   0 on success, a negative errno value otherwise and rte_errno is set.
1358  */
1359 int
1360 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1361 {
1362         struct mlx5_priv *priv = dev->data->dev_private;
1363         struct mlx5_proc_priv *ppriv;
1364         size_t ppriv_size;
1365
1366         /*
1367          * UAR register table follows the process private structure. BlueFlame
1368          * registers for Tx queues are stored in the table.
1369          */
1370         ppriv_size =
1371                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1372         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1373                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1374         if (!ppriv) {
1375                 rte_errno = ENOMEM;
1376                 return -rte_errno;
1377         }
1378         ppriv->uar_table_sz = priv->txqs_n;
1379         dev->process_private = ppriv;
1380         return 0;
1381 }
1382
1383 /**
1384  * Un-initialize process private data structure.
1385  *
1386  * @param dev
1387  *   Pointer to Ethernet device structure.
1388  */
1389 void
1390 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1391 {
1392         if (!dev->process_private)
1393                 return;
1394         mlx5_free(dev->process_private);
1395         dev->process_private = NULL;
1396 }
1397
1398 /**
1399  * DPDK callback to close the device.
1400  *
1401  * Destroy all queues and objects, free memory.
1402  *
1403  * @param dev
1404  *   Pointer to Ethernet device structure.
1405  */
1406 int
1407 mlx5_dev_close(struct rte_eth_dev *dev)
1408 {
1409         struct mlx5_priv *priv = dev->data->dev_private;
1410         unsigned int i;
1411         int ret;
1412
1413         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1414                 /* Check if process_private released. */
1415                 if (!dev->process_private)
1416                         return 0;
1417                 mlx5_tx_uar_uninit_secondary(dev);
1418                 mlx5_proc_priv_uninit(dev);
1419                 rte_eth_dev_release_port(dev);
1420                 return 0;
1421         }
1422         if (!priv->sh)
1423                 return 0;
1424         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1425                 dev->data->port_id,
1426                 ((priv->sh->ctx != NULL) ?
1427                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1428         /*
1429          * If default mreg copy action is removed at the stop stage,
1430          * the search will return none and nothing will be done anymore.
1431          */
1432         mlx5_flow_stop_default(dev);
1433         mlx5_traffic_disable(dev);
1434         /*
1435          * If all the flows are already flushed in the device stop stage,
1436          * then this will return directly without any action.
1437          */
1438         mlx5_flow_list_flush(dev, &priv->flows, true);
1439         mlx5_action_handle_flush(dev);
1440         mlx5_flow_meter_flush(dev, NULL);
1441         /* Prevent crashes when queues are still in use. */
1442         dev->rx_pkt_burst = removed_rx_burst;
1443         dev->tx_pkt_burst = removed_tx_burst;
1444         rte_wmb();
1445         /* Disable datapath on secondary process. */
1446         mlx5_mp_os_req_stop_rxtx(dev);
1447         /* Free the eCPRI flex parser resource. */
1448         mlx5_flex_parser_ecpri_release(dev);
1449         if (priv->rxqs != NULL) {
1450                 /* XXX race condition if mlx5_rx_burst() is still running. */
1451                 rte_delay_us_sleep(1000);
1452                 for (i = 0; (i != priv->rxqs_n); ++i)
1453                         mlx5_rxq_release(dev, i);
1454                 priv->rxqs_n = 0;
1455                 priv->rxqs = NULL;
1456         }
1457         if (priv->txqs != NULL) {
1458                 /* XXX race condition if mlx5_tx_burst() is still running. */
1459                 rte_delay_us_sleep(1000);
1460                 for (i = 0; (i != priv->txqs_n); ++i)
1461                         mlx5_txq_release(dev, i);
1462                 priv->txqs_n = 0;
1463                 priv->txqs = NULL;
1464         }
1465         mlx5_proc_priv_uninit(dev);
1466         if (priv->q_counters) {
1467                 mlx5_devx_cmd_destroy(priv->q_counters);
1468                 priv->q_counters = NULL;
1469         }
1470         if (priv->drop_queue.hrxq)
1471                 mlx5_drop_action_destroy(dev);
1472         if (priv->mreg_cp_tbl)
1473                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1474         mlx5_mprq_free_mp(dev);
1475         mlx5_os_free_shared_dr(priv);
1476         if (priv->rss_conf.rss_key != NULL)
1477                 mlx5_free(priv->rss_conf.rss_key);
1478         if (priv->reta_idx != NULL)
1479                 mlx5_free(priv->reta_idx);
1480         if (priv->config.vf)
1481                 mlx5_os_mac_addr_flush(dev);
1482         if (priv->nl_socket_route >= 0)
1483                 close(priv->nl_socket_route);
1484         if (priv->nl_socket_rdma >= 0)
1485                 close(priv->nl_socket_rdma);
1486         if (priv->vmwa_context)
1487                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1488         ret = mlx5_hrxq_verify(dev);
1489         if (ret)
1490                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1491                         dev->data->port_id);
1492         ret = mlx5_ind_table_obj_verify(dev);
1493         if (ret)
1494                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1495                         dev->data->port_id);
1496         ret = mlx5_rxq_obj_verify(dev);
1497         if (ret)
1498                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1499                         dev->data->port_id);
1500         ret = mlx5_rxq_verify(dev);
1501         if (ret)
1502                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1503                         dev->data->port_id);
1504         ret = mlx5_txq_obj_verify(dev);
1505         if (ret)
1506                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1507                         dev->data->port_id);
1508         ret = mlx5_txq_verify(dev);
1509         if (ret)
1510                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1511                         dev->data->port_id);
1512         ret = mlx5_flow_verify(dev);
1513         if (ret)
1514                 DRV_LOG(WARNING, "port %u some flows still remain",
1515                         dev->data->port_id);
1516         mlx5_cache_list_destroy(&priv->hrxqs);
1517         /*
1518          * Free the shared context in last turn, because the cleanup
1519          * routines above may use some shared fields, like
1520          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1521          * ifindex if Netlink fails.
1522          */
1523         mlx5_free_shared_dev_ctx(priv->sh);
1524         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1525                 unsigned int c = 0;
1526                 uint16_t port_id;
1527
1528                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1529                         struct mlx5_priv *opriv =
1530                                 rte_eth_devices[port_id].data->dev_private;
1531
1532                         if (!opriv ||
1533                             opriv->domain_id != priv->domain_id ||
1534                             &rte_eth_devices[port_id] == dev)
1535                                 continue;
1536                         ++c;
1537                         break;
1538                 }
1539                 if (!c)
1540                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1541         }
1542         memset(priv, 0, sizeof(*priv));
1543         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1544         /*
1545          * Reset mac_addrs to NULL such that it is not freed as part of
1546          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1547          * it is freed when dev_private is freed.
1548          */
1549         dev->data->mac_addrs = NULL;
1550         return 0;
1551 }
1552
1553 const struct eth_dev_ops mlx5_dev_ops = {
1554         .dev_configure = mlx5_dev_configure,
1555         .dev_start = mlx5_dev_start,
1556         .dev_stop = mlx5_dev_stop,
1557         .dev_set_link_down = mlx5_set_link_down,
1558         .dev_set_link_up = mlx5_set_link_up,
1559         .dev_close = mlx5_dev_close,
1560         .promiscuous_enable = mlx5_promiscuous_enable,
1561         .promiscuous_disable = mlx5_promiscuous_disable,
1562         .allmulticast_enable = mlx5_allmulticast_enable,
1563         .allmulticast_disable = mlx5_allmulticast_disable,
1564         .link_update = mlx5_link_update,
1565         .stats_get = mlx5_stats_get,
1566         .stats_reset = mlx5_stats_reset,
1567         .xstats_get = mlx5_xstats_get,
1568         .xstats_reset = mlx5_xstats_reset,
1569         .xstats_get_names = mlx5_xstats_get_names,
1570         .fw_version_get = mlx5_fw_version_get,
1571         .dev_infos_get = mlx5_dev_infos_get,
1572         .representor_info_get = mlx5_representor_info_get,
1573         .read_clock = mlx5_txpp_read_clock,
1574         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1575         .vlan_filter_set = mlx5_vlan_filter_set,
1576         .rx_queue_setup = mlx5_rx_queue_setup,
1577         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1578         .tx_queue_setup = mlx5_tx_queue_setup,
1579         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1580         .rx_queue_release = mlx5_rx_queue_release,
1581         .tx_queue_release = mlx5_tx_queue_release,
1582         .rx_queue_start = mlx5_rx_queue_start,
1583         .rx_queue_stop = mlx5_rx_queue_stop,
1584         .tx_queue_start = mlx5_tx_queue_start,
1585         .tx_queue_stop = mlx5_tx_queue_stop,
1586         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1587         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1588         .mac_addr_remove = mlx5_mac_addr_remove,
1589         .mac_addr_add = mlx5_mac_addr_add,
1590         .mac_addr_set = mlx5_mac_addr_set,
1591         .set_mc_addr_list = mlx5_set_mc_addr_list,
1592         .mtu_set = mlx5_dev_set_mtu,
1593         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1594         .vlan_offload_set = mlx5_vlan_offload_set,
1595         .reta_update = mlx5_dev_rss_reta_update,
1596         .reta_query = mlx5_dev_rss_reta_query,
1597         .rss_hash_update = mlx5_rss_hash_update,
1598         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1599         .flow_ops_get = mlx5_flow_ops_get,
1600         .rxq_info_get = mlx5_rxq_info_get,
1601         .txq_info_get = mlx5_txq_info_get,
1602         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1603         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1604         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1605         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1606         .is_removed = mlx5_is_removed,
1607         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1608         .get_module_info = mlx5_get_module_info,
1609         .get_module_eeprom = mlx5_get_module_eeprom,
1610         .hairpin_cap_get = mlx5_hairpin_cap_get,
1611         .mtr_ops_get = mlx5_flow_meter_ops_get,
1612         .hairpin_bind = mlx5_hairpin_bind,
1613         .hairpin_unbind = mlx5_hairpin_unbind,
1614         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1615         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1616         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1617         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1618 };
1619
1620 /* Available operations from secondary process. */
1621 const struct eth_dev_ops mlx5_dev_sec_ops = {
1622         .stats_get = mlx5_stats_get,
1623         .stats_reset = mlx5_stats_reset,
1624         .xstats_get = mlx5_xstats_get,
1625         .xstats_reset = mlx5_xstats_reset,
1626         .xstats_get_names = mlx5_xstats_get_names,
1627         .fw_version_get = mlx5_fw_version_get,
1628         .dev_infos_get = mlx5_dev_infos_get,
1629         .read_clock = mlx5_txpp_read_clock,
1630         .rx_queue_start = mlx5_rx_queue_start,
1631         .rx_queue_stop = mlx5_rx_queue_stop,
1632         .tx_queue_start = mlx5_tx_queue_start,
1633         .tx_queue_stop = mlx5_tx_queue_stop,
1634         .rxq_info_get = mlx5_rxq_info_get,
1635         .txq_info_get = mlx5_txq_info_get,
1636         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1637         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1638         .get_module_info = mlx5_get_module_info,
1639         .get_module_eeprom = mlx5_get_module_eeprom,
1640 };
1641
1642 /* Available operations in flow isolated mode. */
1643 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1644         .dev_configure = mlx5_dev_configure,
1645         .dev_start = mlx5_dev_start,
1646         .dev_stop = mlx5_dev_stop,
1647         .dev_set_link_down = mlx5_set_link_down,
1648         .dev_set_link_up = mlx5_set_link_up,
1649         .dev_close = mlx5_dev_close,
1650         .promiscuous_enable = mlx5_promiscuous_enable,
1651         .promiscuous_disable = mlx5_promiscuous_disable,
1652         .allmulticast_enable = mlx5_allmulticast_enable,
1653         .allmulticast_disable = mlx5_allmulticast_disable,
1654         .link_update = mlx5_link_update,
1655         .stats_get = mlx5_stats_get,
1656         .stats_reset = mlx5_stats_reset,
1657         .xstats_get = mlx5_xstats_get,
1658         .xstats_reset = mlx5_xstats_reset,
1659         .xstats_get_names = mlx5_xstats_get_names,
1660         .fw_version_get = mlx5_fw_version_get,
1661         .dev_infos_get = mlx5_dev_infos_get,
1662         .read_clock = mlx5_txpp_read_clock,
1663         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1664         .vlan_filter_set = mlx5_vlan_filter_set,
1665         .rx_queue_setup = mlx5_rx_queue_setup,
1666         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1667         .tx_queue_setup = mlx5_tx_queue_setup,
1668         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1669         .rx_queue_release = mlx5_rx_queue_release,
1670         .tx_queue_release = mlx5_tx_queue_release,
1671         .rx_queue_start = mlx5_rx_queue_start,
1672         .rx_queue_stop = mlx5_rx_queue_stop,
1673         .tx_queue_start = mlx5_tx_queue_start,
1674         .tx_queue_stop = mlx5_tx_queue_stop,
1675         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1676         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1677         .mac_addr_remove = mlx5_mac_addr_remove,
1678         .mac_addr_add = mlx5_mac_addr_add,
1679         .mac_addr_set = mlx5_mac_addr_set,
1680         .set_mc_addr_list = mlx5_set_mc_addr_list,
1681         .mtu_set = mlx5_dev_set_mtu,
1682         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1683         .vlan_offload_set = mlx5_vlan_offload_set,
1684         .flow_ops_get = mlx5_flow_ops_get,
1685         .rxq_info_get = mlx5_rxq_info_get,
1686         .txq_info_get = mlx5_txq_info_get,
1687         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1688         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1689         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1690         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1691         .is_removed = mlx5_is_removed,
1692         .get_module_info = mlx5_get_module_info,
1693         .get_module_eeprom = mlx5_get_module_eeprom,
1694         .hairpin_cap_get = mlx5_hairpin_cap_get,
1695         .mtr_ops_get = mlx5_flow_meter_ops_get,
1696         .hairpin_bind = mlx5_hairpin_bind,
1697         .hairpin_unbind = mlx5_hairpin_unbind,
1698         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1699         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1700         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1701         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1702 };
1703
1704 /**
1705  * Verify and store value for device argument.
1706  *
1707  * @param[in] key
1708  *   Key argument to verify.
1709  * @param[in] val
1710  *   Value associated with key.
1711  * @param opaque
1712  *   User data.
1713  *
1714  * @return
1715  *   0 on success, a negative errno value otherwise and rte_errno is set.
1716  */
1717 static int
1718 mlx5_args_check(const char *key, const char *val, void *opaque)
1719 {
1720         struct mlx5_dev_config *config = opaque;
1721         unsigned long mod;
1722         signed long tmp;
1723
1724         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1725         if (!strcmp(MLX5_REPRESENTOR, key))
1726                 return 0;
1727         errno = 0;
1728         tmp = strtol(val, NULL, 0);
1729         if (errno) {
1730                 rte_errno = errno;
1731                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1732                 return -rte_errno;
1733         }
1734         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1735                 /* Negative values are acceptable for some keys only. */
1736                 rte_errno = EINVAL;
1737                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1738                 return -rte_errno;
1739         }
1740         mod = tmp >= 0 ? tmp : -tmp;
1741         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1742                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1743                         DRV_LOG(ERR, "invalid CQE compression "
1744                                      "format parameter");
1745                         rte_errno = EINVAL;
1746                         return -rte_errno;
1747                 }
1748                 config->cqe_comp = !!tmp;
1749                 config->cqe_comp_fmt = tmp;
1750         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1751                 config->hw_padding = !!tmp;
1752         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1753                 config->mprq.enabled = !!tmp;
1754         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1755                 config->mprq.stride_num_n = tmp;
1756         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1757                 config->mprq.stride_size_n = tmp;
1758         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1759                 config->mprq.max_memcpy_len = tmp;
1760         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1761                 config->mprq.min_rxqs_num = tmp;
1762         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1763                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1764                                  " converted to txq_inline_max", key);
1765                 config->txq_inline_max = tmp;
1766         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1767                 config->txq_inline_max = tmp;
1768         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1769                 config->txq_inline_min = tmp;
1770         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1771                 config->txq_inline_mpw = tmp;
1772         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1773                 config->txqs_inline = tmp;
1774         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1775                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1776         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1777                 config->mps = !!tmp;
1778         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1779                 if (tmp != MLX5_TXDB_CACHED &&
1780                     tmp != MLX5_TXDB_NCACHED &&
1781                     tmp != MLX5_TXDB_HEURISTIC) {
1782                         DRV_LOG(ERR, "invalid Tx doorbell "
1783                                      "mapping parameter");
1784                         rte_errno = EINVAL;
1785                         return -rte_errno;
1786                 }
1787                 config->dbnc = tmp;
1788         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1789                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1790         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1791                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1792                                  " converted to txq_inline_mpw", key);
1793                 config->txq_inline_mpw = tmp;
1794         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1795                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1796         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1797                 if (!mod) {
1798                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1799                         rte_errno = EINVAL;
1800                         return -rte_errno;
1801                 }
1802                 config->tx_pp = tmp;
1803         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1804                 config->tx_skew = tmp;
1805         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1806                 config->rx_vec_en = !!tmp;
1807         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1808                 config->l3_vxlan_en = !!tmp;
1809         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1810                 config->vf_nl_en = !!tmp;
1811         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1812                 config->dv_esw_en = !!tmp;
1813         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1814                 config->dv_flow_en = !!tmp;
1815         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1816                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1817                     tmp != MLX5_XMETA_MODE_META16 &&
1818                     tmp != MLX5_XMETA_MODE_META32 &&
1819                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1820                         DRV_LOG(ERR, "invalid extensive "
1821                                      "metadata parameter");
1822                         rte_errno = EINVAL;
1823                         return -rte_errno;
1824                 }
1825                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1826                         config->dv_xmeta_en = tmp;
1827                 else
1828                         config->dv_miss_info = 1;
1829         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1830                 config->lacp_by_user = !!tmp;
1831         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1832                 config->mr_ext_memseg_en = !!tmp;
1833         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1834                 config->max_dump_files_num = tmp;
1835         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1836                 config->lro.timeout = tmp;
1837         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1838                 DRV_LOG(DEBUG, "class argument is %s.", val);
1839         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1840                 config->log_hp_size = tmp;
1841         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1842                 if (tmp != MLX5_RCM_NONE &&
1843                     tmp != MLX5_RCM_LIGHT &&
1844                     tmp != MLX5_RCM_AGGR) {
1845                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1846                         rte_errno = EINVAL;
1847                         return -rte_errno;
1848                 }
1849                 config->reclaim_mode = tmp;
1850         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1851                 config->sys_mem_en = !!tmp;
1852         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1853                 config->decap_en = !!tmp;
1854         } else {
1855                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1856                 rte_errno = EINVAL;
1857                 return -rte_errno;
1858         }
1859         return 0;
1860 }
1861
1862 /**
1863  * Parse device parameters.
1864  *
1865  * @param config
1866  *   Pointer to device configuration structure.
1867  * @param devargs
1868  *   Device arguments structure.
1869  *
1870  * @return
1871  *   0 on success, a negative errno value otherwise and rte_errno is set.
1872  */
1873 int
1874 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1875 {
1876         const char **params = (const char *[]){
1877                 MLX5_RXQ_CQE_COMP_EN,
1878                 MLX5_RXQ_PKT_PAD_EN,
1879                 MLX5_RX_MPRQ_EN,
1880                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1881                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1882                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1883                 MLX5_RXQS_MIN_MPRQ,
1884                 MLX5_TXQ_INLINE,
1885                 MLX5_TXQ_INLINE_MIN,
1886                 MLX5_TXQ_INLINE_MAX,
1887                 MLX5_TXQ_INLINE_MPW,
1888                 MLX5_TXQS_MIN_INLINE,
1889                 MLX5_TXQS_MAX_VEC,
1890                 MLX5_TXQ_MPW_EN,
1891                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1892                 MLX5_TXQ_MAX_INLINE_LEN,
1893                 MLX5_TX_DB_NC,
1894                 MLX5_TX_PP,
1895                 MLX5_TX_SKEW,
1896                 MLX5_TX_VEC_EN,
1897                 MLX5_RX_VEC_EN,
1898                 MLX5_L3_VXLAN_EN,
1899                 MLX5_VF_NL_EN,
1900                 MLX5_DV_ESW_EN,
1901                 MLX5_DV_FLOW_EN,
1902                 MLX5_DV_XMETA_EN,
1903                 MLX5_LACP_BY_USER,
1904                 MLX5_MR_EXT_MEMSEG_EN,
1905                 MLX5_REPRESENTOR,
1906                 MLX5_MAX_DUMP_FILES_NUM,
1907                 MLX5_LRO_TIMEOUT_USEC,
1908                 MLX5_CLASS_ARG_NAME,
1909                 MLX5_HP_BUF_SIZE,
1910                 MLX5_RECLAIM_MEM,
1911                 MLX5_SYS_MEM_EN,
1912                 MLX5_DECAP_EN,
1913                 NULL,
1914         };
1915         struct rte_kvargs *kvlist;
1916         int ret = 0;
1917         int i;
1918
1919         if (devargs == NULL)
1920                 return 0;
1921         /* Following UGLY cast is done to pass checkpatch. */
1922         kvlist = rte_kvargs_parse(devargs->args, params);
1923         if (kvlist == NULL) {
1924                 rte_errno = EINVAL;
1925                 return -rte_errno;
1926         }
1927         /* Process parameters. */
1928         for (i = 0; (params[i] != NULL); ++i) {
1929                 if (rte_kvargs_count(kvlist, params[i])) {
1930                         ret = rte_kvargs_process(kvlist, params[i],
1931                                                  mlx5_args_check, config);
1932                         if (ret) {
1933                                 rte_errno = EINVAL;
1934                                 rte_kvargs_free(kvlist);
1935                                 return -rte_errno;
1936                         }
1937                 }
1938         }
1939         rte_kvargs_free(kvlist);
1940         return 0;
1941 }
1942
1943 /**
1944  * Configures the minimal amount of data to inline into WQE
1945  * while sending packets.
1946  *
1947  * - the txq_inline_min has the maximal priority, if this
1948  *   key is specified in devargs
1949  * - if DevX is enabled the inline mode is queried from the
1950  *   device (HCA attributes and NIC vport context if needed).
1951  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1952  *   and none (0 bytes) for other NICs
1953  *
1954  * @param spawn
1955  *   Verbs device parameters (name, port, switch_info) to spawn.
1956  * @param config
1957  *   Device configuration parameters.
1958  */
1959 void
1960 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1961                     struct mlx5_dev_config *config)
1962 {
1963         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1964                 /* Application defines size of inlined data explicitly. */
1965                 switch (spawn->pci_dev->id.device_id) {
1966                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1967                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1968                         if (config->txq_inline_min <
1969                                        (int)MLX5_INLINE_HSIZE_L2) {
1970                                 DRV_LOG(DEBUG,
1971                                         "txq_inline_mix aligned to minimal"
1972                                         " ConnectX-4 required value %d",
1973                                         (int)MLX5_INLINE_HSIZE_L2);
1974                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1975                         }
1976                         break;
1977                 }
1978                 goto exit;
1979         }
1980         if (config->hca_attr.eth_net_offloads) {
1981                 /* We have DevX enabled, inline mode queried successfully. */
1982                 switch (config->hca_attr.wqe_inline_mode) {
1983                 case MLX5_CAP_INLINE_MODE_L2:
1984                         /* outer L2 header must be inlined. */
1985                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1986                         goto exit;
1987                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1988                         /* No inline data are required by NIC. */
1989                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1990                         config->hw_vlan_insert =
1991                                 config->hca_attr.wqe_vlan_insert;
1992                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1993                         goto exit;
1994                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1995                         /* inline mode is defined by NIC vport context. */
1996                         if (!config->hca_attr.eth_virt)
1997                                 break;
1998                         switch (config->hca_attr.vport_inline_mode) {
1999                         case MLX5_INLINE_MODE_NONE:
2000                                 config->txq_inline_min =
2001                                         MLX5_INLINE_HSIZE_NONE;
2002                                 goto exit;
2003                         case MLX5_INLINE_MODE_L2:
2004                                 config->txq_inline_min =
2005                                         MLX5_INLINE_HSIZE_L2;
2006                                 goto exit;
2007                         case MLX5_INLINE_MODE_IP:
2008                                 config->txq_inline_min =
2009                                         MLX5_INLINE_HSIZE_L3;
2010                                 goto exit;
2011                         case MLX5_INLINE_MODE_TCP_UDP:
2012                                 config->txq_inline_min =
2013                                         MLX5_INLINE_HSIZE_L4;
2014                                 goto exit;
2015                         case MLX5_INLINE_MODE_INNER_L2:
2016                                 config->txq_inline_min =
2017                                         MLX5_INLINE_HSIZE_INNER_L2;
2018                                 goto exit;
2019                         case MLX5_INLINE_MODE_INNER_IP:
2020                                 config->txq_inline_min =
2021                                         MLX5_INLINE_HSIZE_INNER_L3;
2022                                 goto exit;
2023                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2024                                 config->txq_inline_min =
2025                                         MLX5_INLINE_HSIZE_INNER_L4;
2026                                 goto exit;
2027                         }
2028                 }
2029         }
2030         /*
2031          * We get here if we are unable to deduce
2032          * inline data size with DevX. Try PCI ID
2033          * to determine old NICs.
2034          */
2035         switch (spawn->pci_dev->id.device_id) {
2036         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2037         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2038         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2039         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2040                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2041                 config->hw_vlan_insert = 0;
2042                 break;
2043         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2044         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2045         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2046         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2047                 /*
2048                  * These NICs support VLAN insertion from WQE and
2049                  * report the wqe_vlan_insert flag. But there is the bug
2050                  * and PFC control may be broken, so disable feature.
2051                  */
2052                 config->hw_vlan_insert = 0;
2053                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2054                 break;
2055         default:
2056                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2057                 break;
2058         }
2059 exit:
2060         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2061 }
2062
2063 /**
2064  * Configures the metadata mask fields in the shared context.
2065  *
2066  * @param [in] dev
2067  *   Pointer to Ethernet device.
2068  */
2069 void
2070 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2071 {
2072         struct mlx5_priv *priv = dev->data->dev_private;
2073         struct mlx5_dev_ctx_shared *sh = priv->sh;
2074         uint32_t meta, mark, reg_c0;
2075
2076         reg_c0 = ~priv->vport_meta_mask;
2077         switch (priv->config.dv_xmeta_en) {
2078         case MLX5_XMETA_MODE_LEGACY:
2079                 meta = UINT32_MAX;
2080                 mark = MLX5_FLOW_MARK_MASK;
2081                 break;
2082         case MLX5_XMETA_MODE_META16:
2083                 meta = reg_c0 >> rte_bsf32(reg_c0);
2084                 mark = MLX5_FLOW_MARK_MASK;
2085                 break;
2086         case MLX5_XMETA_MODE_META32:
2087                 meta = UINT32_MAX;
2088                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2089                 break;
2090         default:
2091                 meta = 0;
2092                 mark = 0;
2093                 MLX5_ASSERT(false);
2094                 break;
2095         }
2096         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2097                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2098                                  sh->dv_mark_mask, mark);
2099         else
2100                 sh->dv_mark_mask = mark;
2101         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2102                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2103                                  sh->dv_meta_mask, meta);
2104         else
2105                 sh->dv_meta_mask = meta;
2106         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2107                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2108                                  sh->dv_meta_mask, reg_c0);
2109         else
2110                 sh->dv_regc0_mask = reg_c0;
2111         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2112         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2113         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2114         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2115 }
2116
2117 int
2118 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2119 {
2120         static const char *const dynf_names[] = {
2121                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2122                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2123                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2124         };
2125         unsigned int i;
2126
2127         if (n < RTE_DIM(dynf_names))
2128                 return -ENOMEM;
2129         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2130                 if (names[i] == NULL)
2131                         return -EINVAL;
2132                 strcpy(names[i], dynf_names[i]);
2133         }
2134         return RTE_DIM(dynf_names);
2135 }
2136
2137 /**
2138  * Comparison callback to sort device data.
2139  *
2140  * This is meant to be used with qsort().
2141  *
2142  * @param a[in]
2143  *   Pointer to pointer to first data object.
2144  * @param b[in]
2145  *   Pointer to pointer to second data object.
2146  *
2147  * @return
2148  *   0 if both objects are equal, less than 0 if the first argument is less
2149  *   than the second, greater than 0 otherwise.
2150  */
2151 int
2152 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2153                               struct mlx5_dev_config *config)
2154 {
2155         struct mlx5_dev_ctx_shared *sh = priv->sh;
2156         struct mlx5_dev_config *sh_conf = NULL;
2157         uint16_t port_id;
2158
2159         MLX5_ASSERT(sh);
2160         /* Nothing to compare for the single/first device. */
2161         if (sh->refcnt == 1)
2162                 return 0;
2163         /* Find the device with shared context. */
2164         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2165                 struct mlx5_priv *opriv =
2166                         rte_eth_devices[port_id].data->dev_private;
2167
2168                 if (opriv && opriv != priv && opriv->sh == sh) {
2169                         sh_conf = &opriv->config;
2170                         break;
2171                 }
2172         }
2173         if (!sh_conf)
2174                 return 0;
2175         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2176                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2177                              " for shared %s context", sh->ibdev_name);
2178                 rte_errno = EINVAL;
2179                 return rte_errno;
2180         }
2181         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2182                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2183                              " for shared %s context", sh->ibdev_name);
2184                 rte_errno = EINVAL;
2185                 return rte_errno;
2186         }
2187         return 0;
2188 }
2189
2190 /**
2191  * Look for the ethernet device belonging to mlx5 driver.
2192  *
2193  * @param[in] port_id
2194  *   port_id to start looking for device.
2195  * @param[in] pci_dev
2196  *   Pointer to the hint PCI device. When device is being probed
2197  *   the its siblings (master and preceding representors might
2198  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2199  *   is not completed yet, for this case match on hint PCI
2200  *   device may be used to detect sibling device.
2201  *
2202  * @return
2203  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2204  */
2205 uint16_t
2206 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2207 {
2208         while (port_id < RTE_MAX_ETHPORTS) {
2209                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2210
2211                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2212                     dev->device &&
2213                     (dev->device == &pci_dev->device ||
2214                      (dev->device->driver &&
2215                      dev->device->driver->name &&
2216                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2217                         break;
2218                 port_id++;
2219         }
2220         if (port_id >= RTE_MAX_ETHPORTS)
2221                 return RTE_MAX_ETHPORTS;
2222         return port_id;
2223 }
2224
2225 /**
2226  * DPDK callback to remove a PCI device.
2227  *
2228  * This function removes all Ethernet devices belong to a given PCI device.
2229  *
2230  * @param[in] pci_dev
2231  *   Pointer to the PCI device.
2232  *
2233  * @return
2234  *   0 on success, the function cannot fail.
2235  */
2236 static int
2237 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2238 {
2239         uint16_t port_id;
2240         int ret = 0;
2241
2242         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2243                 /*
2244                  * mlx5_dev_close() is not registered to secondary process,
2245                  * call the close function explicitly for secondary process.
2246                  */
2247                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2248                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2249                 else
2250                         ret |= rte_eth_dev_close(port_id);
2251         }
2252         return ret == 0 ? 0 : -EIO;
2253 }
2254
2255 static const struct rte_pci_id mlx5_pci_id_map[] = {
2256         {
2257                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2258                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2259         },
2260         {
2261                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2262                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2263         },
2264         {
2265                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2266                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2267         },
2268         {
2269                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2270                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2271         },
2272         {
2273                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2274                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2275         },
2276         {
2277                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2278                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2279         },
2280         {
2281                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2282                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2283         },
2284         {
2285                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2286                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2287         },
2288         {
2289                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2290                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2291         },
2292         {
2293                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2294                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2295         },
2296         {
2297                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2298                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2299         },
2300         {
2301                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2302                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2303         },
2304         {
2305                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2306                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2307         },
2308         {
2309                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2310                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2311         },
2312         {
2313                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2314                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2315         },
2316         {
2317                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2318                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2319         },
2320         {
2321                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2322                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2323         },
2324         {
2325                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2326                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2327         },
2328         {
2329                 .vendor_id = 0
2330         }
2331 };
2332
2333 static struct mlx5_pci_driver mlx5_driver = {
2334         .driver_class = MLX5_CLASS_NET,
2335         .pci_driver = {
2336                 .driver = {
2337                         .name = MLX5_PCI_DRIVER_NAME,
2338                 },
2339                 .id_table = mlx5_pci_id_map,
2340                 .probe = mlx5_os_pci_probe,
2341                 .remove = mlx5_pci_remove,
2342                 .dma_map = mlx5_dma_map,
2343                 .dma_unmap = mlx5_dma_unmap,
2344                 .drv_flags = PCI_DRV_FLAGS,
2345         },
2346 };
2347
2348 /* Initialize driver log type. */
2349 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2350
2351 /**
2352  * Driver initialization routine.
2353  */
2354 RTE_INIT(rte_mlx5_pmd_init)
2355 {
2356         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2357         mlx5_common_init();
2358         /* Build the static tables for Verbs conversion. */
2359         mlx5_set_ptype_table();
2360         mlx5_set_cksum_table();
2361         mlx5_set_swp_types_table();
2362         if (mlx5_glue)
2363                 mlx5_pci_driver_register(&mlx5_driver);
2364 }
2365
2366 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2367 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2368 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");